; --------------------------------------------------------------------------------
; @Title: J721E On-Chip Peripherals
; @Props: Released
; @Author: BGI, KWI, PIW
; @Changelog: 2019-04-25 BGI
;             2019-08-06 BGI
;             2020-02-03 KWI
;             2022-05-13 PIW
; @Manufacturer: TI - Texas Instruments
; @Doc: XML generated (TIXML2PER 2.1.2), based on:
;       J721E_DRA829_TDA4VM_AM752x_SR1.0.xml (Rev. 1.0)
; @Core: Cortex-A72, CORTEX-M3, CORTEX-R5F, C66X, C71X
; @Chip: AM752X
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perj721e.per 17823 2024-04-26 11:44:52Z dorthofer $

sif (CORENAME()!="PRU")
sif (CORENAME()=="CORTEXM3")
tree.close "Core Registers (Cortex-M3)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
group 0x10--0x1b
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "      CLKSOURCE       ,Clock Source" "External,Core"
bitfld.long 0x00 1. "                  TICKINT        ,SysTick Handler" "Not SysTick,SysTick"
textline "                    "
bitfld.long 0x00 0. " ENABLE       ,Counter Enable" "Disabled,Enabled"
;group 0x14++0x03
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,The value to load into the SYST_CVR when the counter reaches 0"
;group 0x18++0x03
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Current Value"
rgroup 0x1c++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW            ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "                   TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
textline "                    "
rgroup 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer Code"
bitfld.long 0x00 20.--23. "               VARIANT         ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "                        CONSTANT       ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
hexmask.long.word 0x00 4.--15. 1. " PARTNO       ,Number of Processor"
bitfld.long 0x00 0.--3. "             REVISION        ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group 0xd04--0xd17
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Set Pending NMI Bit" "Not set,Set"
bitfld.long 0x00 28. "          PENDSVSET       ,Set Pending pendSV Bit" "Not set,Set"
bitfld.long 0x00 27. "                   PENDSVCLR      ,Clear Pending pendSV Bit" "Not cleared,Cleared"
textline "                    "
bitfld.long 0x00 26. " PENDSTSET    ,Set Pending SysTick Bit" "Not set,Set"
bitfld.long 0x00 25. "          PENDSTCLR       ,Clear Pending SysTick Bit" "Not cleared,Cleared"
bitfld.long 0x00 23. "               ISRPREEMPT     ,Use Only at Debug Time" "Not active,Active"
textline "                    "
bitfld.long 0x00 22. " ISRPENDING   ,Interrupt Pending Flag" "Not pending,Pending"
hexmask.long.word 0x00 12.--21. 1. "      VECTPENDING     ,Pending ISR Number Field"
bitfld.long 0x00 11. "                      RETTOBASE      ,Interrupt Exception" "Active,Not active"
textline "                    "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE   ,Active ISR Number Field"
;group 0xd08++0x03
line.long 0x04 "VTOR,Vector Table Offset Register"
bitfld.long 0x04 29. " TBLBASE      ,Table Base" "Code,RAM"
hexmask.long.tbyte 0x04 7.--28. 1. "             TBLOFF          ,Vector Table Base Offset Field"
;group 0xd0c++0x03
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY      ,Register Key"
rbitfld.long 0x08 15. "             ENDIANESS       ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "                    PRIGROUP       ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                    "
bitfld.long 0x08 2. " SYSRESETREQ  ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "    VECTCLRACTIVE   ,Clear Active Vector Bit" "Not cleared,Cleared all"
bitfld.long 0x08 0. "               VECTRESET      ,System Reset" "No reset,Reset"
;group 0xd10++0x03
line.long 0x0c "SCR,System Control Register"
bitfld.long 0x0c 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0c 2. "       SLEEPDEEP       ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                    "
bitfld.long 0x0c 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
;group 0xd14++0x03
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 9. " STKALIGN     ,8-byte Stack Frame Alignment" "4-byte,8-byte"
bitfld.long 0x10 8. "           BFHFNMIGN       ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
textline "                    "
bitfld.long 0x10 4. " DIV_0_TRP    ,Trap Divide by Zero" "Disabled,Enabled"
bitfld.long 0x10 3. "         UNALIGN_TRP     ,Trap for Unaligned Access" "Disabled,Enabled"
textline "                    "
bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
bitfld.long 0x10 0. "         NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
group 0xd18--0xd23
line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " PRI_7        ,Priority of System Handler 7"
hexmask.long.byte 0x00 16.--23. 1. "               PRI_6           ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x00 8.--15. 1. "                        PRI_5          ,Priority of system handler 5(BusFault)"
textline "                    "
hexmask.long.byte 0x00 0.--7. 1. " PRI_4        ,Priority of system handler 4(MemManage)"
line.long 0x04 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x04 24.--31. 1. " PRI_11       ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x04 16.--23. 1. "               PRI_10          ,Priority of System Handler 10"
hexmask.long.byte 0x04 8.--15. 1. "                        PRI_9          ,Priority of System Handler 9"
textline "                    "
hexmask.long.byte 0x04 0.--7. 1. " PRI_8        ,Priority of System Handler 8"
line.long 0x08 "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x08 24.--31. 1. " PRI_15       ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x08 16.--23. 1. "               PRI_14          ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x08 8.--15. 1. "                        PRI_13         ,Priority of System Handler 13"
textline "                    "
hexmask.long.byte 0x08 0.--7. 1. " PRI_12       ,Priority of System Handler 12(DebugMonitor)"
group 0xd24++0x3
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 18. " USGFAULTENA  ,USGFAULTENA" "Disabled,Enabled"
bitfld.long 0x00 17. "         BUSFAULTENA     ,BUSFAULTENA" "Disabled,Enabled"
bitfld.long 0x00 16. "                  MEMFAULTENA    ,MEMFAULTENA" "Disabled,Enabled"
textline "                    "
bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
bitfld.long 0x00 14. "     BUSFAULTPENDED  ,BusFault is Pended Started" "Not replaced,Replaced"
bitfld.long 0x00 13. "              MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
textline "                    "
bitfld.long 0x00 11. " SYSTICKACT   ,SysTick is Active" "Not active,Active"
bitfld.long 0x00 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
bitfld.long 0x00 8. "                MONITORACT     ,Monitor is Active" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " SVCALLACT    ,SVCall is Active" "Not active,Active"
bitfld.long 0x00 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
bitfld.long 0x00 1. "                BUSFAULTACT    ,BusFault is Active" "Not active,Active"
textline "                    "
bitfld.long 0x00 0. " MEMFAULTACT  ,MemManage is Active" "Not active,Active"
group 0xd28--0xd3b
line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
bitfld.byte 0x0 7. "       MMARVALID    ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x0 4. "        MSTKERR         ,Stacking Access Violations" "No error,Error"
bitfld.byte 0x0 3. "                  MUNSTKERR      ,Unstack Access Violations" "No error,Error"
textline "                    "
bitfld.byte 0x0 1. " DACCVIOL     ,Data Access Violation" "No error,Error"
bitfld.byte 0x0 0. "         IACCVIOL        ,Instruction Access Violation" "No error,Error"
;group 0xd29++0x00
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID    ,Address Valid" "Not valid,Valid"
bitfld.byte 0x01 4. "        STKERR          ,Stacking from Exception has Caused Bus Faults" "No error,Error"
bitfld.byte 0x01 3. "                  UNSTKERR       ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
textline "                    "
bitfld.byte 0x01 2. " IMPRECISERR  ,Imprecise Data Bus Error" "No error,Error"
bitfld.byte 0x01 1. "         PRECISERR       ,Precise Data Bus Error Return" "No error,Error"
bitfld.byte 0x01 0. "                  IBUSERR        ,Instruction Bus Error Flag" "No error,Error"
;group 0xd2a++0x01
line.word 0x02 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x02 9. "     DIVBYZERO    ,Illegal PC Load" "No error,Error"
bitfld.word 0x02 8. "         UNALIGNED       ,Illegal Unaligned Access" "No error,Error"
bitfld.word 0x02 3. "                  NOCP           ,Attempt to use a coprocessor instruction" "No error,Error"
textline "                    "
bitfld.word 0x02 2. " INVPC        ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
bitfld.word 0x02 1. "         INVSTATE        , Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x02 0. "                  UNDEFINSTR     ,Illegal Processor State" "No error,Error"
;group 0xd2c++0x03
line.long 0x04 "HFSR,Hard Fault Status Register"
bitfld.long 0x04 31. " DEBUGEVT     ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
bitfld.long 0x04 30. "         FORCED          ,Hard Fault Activated" "No error,Error"
bitfld.long 0x04 1. "                  VECTTBL        ,Bus Fault" "No error,Error"
;group 0xd30++0x03
line.long 0x08 "DFSR,Debug Fault Status Register"
bitfld.long 0x08 4. " EXTERNAL     ,External Debug Request Flag" "Not asserted,Asserted"
bitfld.long 0x08 3. "     VCATCH          ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x08 2. "              DWTTRAP        ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
textline "                    "
bitfld.long 0x08 1. " BKPT         ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x08 0. "     HALTED          ,Halt Request Flag" "Not requested,Requested"
;group 0xd34++0x03
line.long 0xc "MMFAR,Memory Manage Fault Address Register"
;group 0xd38++0x03
line.long 0x10 "BFAR,Bus Fault Address Register"
wgroup 0xf00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID        ,Indicates the interrupt to be triggered"
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
tree "CoreSight Identification Registers"
width 6.
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 1. "   C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 5. " C_SNAPSTALL       ,Halting debug to gain control of the core" "Disabled,Enabled"
bitfld.long 0x00 3. "     C_MASKINTS         ,Interrupts Mask" "Not masked,Masked"
textline "                "
bitfld.long 0x00 2. " C_STEP            ,Core Step" "No step,Step"
bitfld.long 0x00 1. "      C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
group 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "     S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "            DBGKEY             ,Debug Key" "0,1"
textline "                "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core running and Lockup/Debug Key" "Not running,Running"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
textline "                "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "   S_REGRDY/DBGKEY    ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                "
bitfld.long 0x00 2. " C_STEP            ,Core Step" "No step,Step"
bitfld.long 0x00 1. "      C_HALT             ,Core Halted" "Not halted,Halted"
textline "                "
bitfld.long 0x00 0. " C_DEBUGEN         ,Debug Enable" "Disabled,Enabled"
endif
wgroup 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "        REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
group 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "     MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "         MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
textline "                "
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "  MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "  VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "     VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "  VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "     VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "  VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "     MON_REQ    ,DebugMonitor semaphore bit" "0,1"
textline "                "
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "  MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "  VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "     VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "  VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "     VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "  VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
textline "                "
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group 0x00--0x27
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "  NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "  KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. "  ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
;group 0x04++0x03
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP   ,Remap Base Address Field"
;group 0x08++0x03
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x8 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x8 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0xC 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0xC 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x10 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x10 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x14 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x14 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x18 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x18 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x1C 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x1C 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x20 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x20 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x24 2.--28. 1. "  COMP ,Comparison Address"
bitfld.long 0x24 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
tree "Coresight Management Registers"
rgroup 0xfd0--0xfff
line.long 0x00 "PID4,Peripheral ID4"
line.long 0x04 "PID5,Peripheral ID5"
line.long 0x08 "PID6,Peripheral ID6"
line.long 0x0c "PID7,Peripheral ID7"
line.long 0x10 "PID0,Peripheral ID0"
line.long 0x14 "PID1,Peripheral ID1"
line.long 0x18 "PID2,Peripheral ID2"
line.long 0x1c "PID3,Peripheral ID3"
line.long 0x20 "CID0,Component ID0"
line.long 0x24 "CID1,Component ID1"
line.long 0x28 "CID2,Component ID2"
line.long 0x2c "CID3,Component ID3"
tree.end
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group 0x00--0x1B
line.long 0x00 "DWT_CTRL,DWT Control Register"
bitfld.long 0x00 28.--31. " NUMCOMP    ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22. "        CYCEVTENA   ,Enables Cycle Count Event" "Disabled,Enabled"
bitfld.long 0x00 21. "  FOLDEVTENA  ,Enables Folded Instruction Count Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 20. " LSUEVTENA  ,Enables LSU Count Event" "Disabled,Enabled"
bitfld.long 0x00 19. "  SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
bitfld.long 0x00 18. "  EXCEVTENA   ,Enables Interrupt Overhead Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 17. " CPIEVTENA  ,Enables CPI Count Event" "Disabled,Enabled"
bitfld.long 0x00 16. "  EXCTRCENA   ,Enables Interrupt Event Tracing" "Disabled,Enabled"
bitfld.long 0x00 12. "  PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 10.--11. " SYNCTAP    ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
bitfld.long 0x00 9. "  CYCTAP      ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
bitfld.long 0x00 5.--8. "    POSTCNT     ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "        CYCCNTENA   ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
;group 0x04++0x03
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
;group 0x08++0x03
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT     ,The base CPI counter"
;group 0x0c++0x03
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT     ,The exception overhead counter"
;group 0x10++0x03
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT   ,Sleep Counter"
;group 0x14++0x03
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT     ,Load-store counter"
;group 0x18++0x03
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT    ,Folded-instruction counter"
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
group.long 0x24++0x03
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x03
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x03
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x00 0.--3. " MASK       ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
group.long 0x38++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x38++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
group.long 0x48++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x48++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
group.long 0x58++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
else
group.long 0x58++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "         DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "        DATAVSIZE ,Data Value Size" "byte,half,word,res"
bitfld.long 0x00 9. "  LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH   ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
bitfld.long 0x00 5. "    EMITRANGE  ,Emit Range Field" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 0.--3. " FUNCTION   ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
endif
tree "Coresight Management Registers"
rgroup 0xfd0--0xfff
line.long 0x00 "PID4,Peripheral ID4"
line.long 0x04 "PID5,Peripheral ID5"
line.long 0x08 "PID6,Peripheral ID6"
line.long 0x0c "PID7,Peripheral ID7"
line.long 0x10 "PID0,Peripheral ID1"
line.long 0x14 "PID1,Peripheral ID2"
line.long 0x18 "PID2,Peripheral ID3"
line.long 0x1c "PID3,Peripheral ID4"
line.long 0x20 "CID0,Component ID0"
line.long 0x24 "CID1,Component ID1"
line.long 0x28 "CID2,Component ID2"
line.long 0x2c "CID3,Component ID3"
tree.end
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
else
sif (CORENAME()=="CORTEXR5F")
tree "Core Registers (Cortex-R5F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 0x8
; --------------------------------------------------------------------------------
;    Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup.long c15:0x00++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL     ,Implementer code"
bitfld.long 0x0 20.--23.  "           VAR      ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "           ARCH     ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline "                 "
hexmask.long.word 0x0 4.--15. 0x1 " PART     ,Primary Part Number"
bitfld.long 0x0 0.--3. "         REV      ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. " CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
bitfld.long 0x00 20.--23. " ERG      ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "           DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. "  L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline "                 "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup.long c15:0x400--0x400
line.long 0x0 "MPUIR,MPU type register"
hexmask.long.byte 0x00 8.--15. 1. " REGNUM   ,Number of regions"
bitfld.long 0x00 0. "           TYPE     ,Type of MPU regions" "Unified,Seperated"
rgroup.long c15:0x500++0x00
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
textline "                 "
hexmask.long.byte 0x00 16.--23. 1. " AFFL2    ,Affitnity Level 2"
hexmask.long.byte 0x00 8.--15. 1. "           AFFL1    ,Affitnity Level 1"
hexmask.long.byte 0x00 0.--7. 1. "           AFFL0    ,Affitnity Level 0"
textline "                 "
rgroup.long c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SL         ,Number of Shareability levels implemented" "1,?..."
bitfld.long 0x00 8.--11. "              OS         ,Outermost Shareability domain support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "   L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "  L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "  WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. " SS         ,Supersection support" "Supported,?..."
bitfld.long 0x00 20.--23. "      CW         ,Coherent walk" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MB         ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c15:0x020++0x00
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "  DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "  CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " SI         ,Swap Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x120++0x00
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x220++0x00
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x320++0x00
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      SVCI       ,SVC Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x420++0x00
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. " SWP_FRAC   ,SWAP_frac" "Supported,?..."
bitfld.long 0x00 24.--27. "      PSR_M_I    ,PSR_M Instructions Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup.long c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup.long c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup.long c15:0x010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "  STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "  STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM    ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "  SE     ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      PM     ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline "                 "
rgroup.long c15:0x210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "      TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c15:0x310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x02f++0x00
line.long 0x00 "BO1R,Build Options 1 Register"
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR    ,Default high address for the TCM"
bitfld.long 0x00 1. "                  FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
textline "                 "
bitfld.long 0x00 0. " PP_BUS_ECC          ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
group.long c15:0x12f++0x00
line.long 0x00 "BO2R,Build Options 2 Register"
bitfld.long 0x00 31. " NUM_CPU             ,Number of CPUs" "1,2"
bitfld.long 0x00 30. "                       LOCK_STEP       ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
textline "                 "
bitfld.long 0x00 29. " NO_ICACHE           ,Indicate whether the CPU contains instruction cache" "Yes,No"
bitfld.long 0x00 28. "                     NO_DCACHE       ,Indicate whether the CPU contains data cache" "Yes,No"
textline "                 "
bitfld.long 0x00 26.--27. " ATCM_ES             ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
bitfld.long 0x00 23.--25. "  BTCM_ES         ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
textline "                 "
bitfld.long 0x00 23. " NO_IE               ,Indicate whether the processor supports big-endian instructions" "Yes,No"
bitfld.long 0x00 22. "                     NO_FPU          ,Indicate whether the CPU contains a floating point unit" "Yes,No"
textline "                 "
bitfld.long 0x00 20.--21. " MPU_REGIONS         ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
bitfld.long 0x00 17.--19. "              BREAK_POINTS    ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
textline "                 "
bitfld.long 0x00 14.--16. " WATCH_POINTS        ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "                       NO_A_TCM_INF    ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 12. " NO_B0_TCM_INF       ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
bitfld.long 0x00 11. "                     NO_B1_TCM_INF   ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 10. " TCMBUSPARITY        ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
bitfld.long 0x00 9. "                     NO_SLAVE        ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
textline "                 "
bitfld.long 0x00 7.--8. " ICACHE_ES           ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
bitfld.long 0x00 5.--6. "         DCACHE_ES       ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
textline "                 "
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
bitfld.long 0x00 3. "                     AXI_BUS_ECC     ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
textline "                 "
bitfld.long 0x00 2. " SL                  ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
bitfld.long 0x00 1. "                     AHB_PP          ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
textline "                 "
bitfld.long 0x00 0. " MICRO_SCU           ,Indicate whether the processor contain an ACP interface" "No,Yes"
group.long c15:0x72f++0x00
line.long 0x00 "POR,Pin Options Register"
bitfld.long 0x00 4. " DBGNOCLKSTOP        ,Value of the DBGNOCLKSTOP pin" "Low,High"
bitfld.long 0x00 3. "                    INTSYNCEN       ,Value of the INTSYNCEN pin" "Low,High"
textline "                 "
bitfld.long 0x00 2. " IRQADDRVSYNCEN      ,Value of the IRQADDRVSYNCEN pin" "Low,High"
bitfld.long 0x00 1. "                    SLBTCMSB        ,Value of the SLBTCMSBm pin" "Low,High"
textline "                 "
bitfld.long 0x00 0. " PARITYLEVEL         ,Value of the PARITYLEVEL pin" "Low,High"
tree.end
width 0x8
tree "System Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x101++0x00
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " DICDI     ,Disable Case C dual issue control" "Enable,Disable"
bitfld.long 0x00 30. "    DIB2DI    ,Disable Case B2 dual issue control" "Enable,Disable"
bitfld.long 0x00 29. "    DIB1DI    ,Disable Case B1 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 28. " DIADI     ,Disable Case A dual issue control" "Enable,Disable"
bitfld.long 0x00 27. "    B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 26. "    B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 25. " ATCMPCEN  ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 24. "    AXISCEN   ,AXI slave cache access enable" "Disable,Enable"
bitfld.long 0x00 23. "    AXISCUEN  ,AXI slave cache User mode access enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 22. " DILSM     ,Disable LIL on load/store multiples" "Enable,Disable"
bitfld.long 0x00 21. "    DEOLP     ,Disable end of loop prediction" "Enable,Disable"
bitfld.long 0x00 20. "    DBHE      ,Disable BH extension" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " FRCDIS    ,Fetch rate control disable" "Enable,Disable"
bitfld.long 0x00 17. "    RSDIS     ,Return stack disable" "Enable,Disable"
bitfld.long 0x00 15.--16. "    BP        ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
textline "                 "
bitfld.long 0x00 14. " DBWR      ,Disable write_burst on AXI master" "Enable,Disable"
bitfld.long 0x00 13. "    DLFO      ,Disable linefill optimization in the AXI master" "Enable,Disable"
bitfld.long 0x00 12. "    ERPEG     ,Enable random parity error generation" "Disable,Enable"
textline "                 "
bitfld.long 0x00 11. " DNCH      ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
bitfld.long 0x00 10. "    FORA      ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
bitfld.long 0x00 9. " FWT       ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
textline "                 "
bitfld.long 0x00 8. " FDSnS     ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
bitfld.long 0x00 7. " SMOV      ,sMOV disabled" "Enabled,Disabled"
bitfld.long 0x0 6. "   DILS      ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
textline "                 "
bitfld.long 0x00 3.--5. " CEC       ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
textline "                 "
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
bitfld.long 0x00 1. "    B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMECEN  ,ATCM external error enable" "Disable,Enable"
textline " "
group.long c15:0x0f++0x00
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
bitfld.long 0x00 22. " DCHE      ,Disable hard-error support in the caches" "Enable,Disable"
bitfld.long 0x00 21. "    DR2B      ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
bitfld.long 0x00 20. "    DF6DI     ,F6 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " DF2DI     ,F2 dual issue control" "Enable,Disable"
bitfld.long 0x00 18. "    DDI       ,F1/F3/F4 dual issue control" "Enable,Disable"
bitfld.long 0x00 17. "    DOODPFP   ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 16. " DOOFMACS  ,Out-of-order FMACS control" "Enable,Disable"
bitfld.long 0x00 13. "    IXC       ,Floating-point inexact exception output mask" "Mask,Propagate"
bitfld.long 0x00 12. "  OFC       ,Floating-point overflow exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 11. " UFC       ,Floating-point underflow exception output mask" "Mask,Propagate"
bitfld.long 0x00 10. "  IOC       ,Floating-point invalid operation exception output mask" "Mask,Propagate"
bitfld.long 0x00 9. "  DZC       ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 8. " IDC       ,Floating-point input denormal exception output mask" "Mask,Propagate"
bitfld.long 0x00 3. "  BTCMECC   ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
bitfld.long 0x00 2. "    ATCMECC   ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
textline "                 "
bitfld.long 0x00 1. " BTCMRMW   ,Enable 64-bit stores on BTCMs" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMRMW   ,Enable 64-bit stores on ATCM" "Disable,Enable"
textline " "
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. " ASEDIS    ,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 30. "        D32DIS    ,Disable use of D16-D31 of the VFP register file" "No,Yes"
textline "                 "
bitfld.long 0x0 26.--27. " CP13      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 22.--23. " CP11      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 18.--19. " CP9       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 14.--15. " CP7       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 10.--11. " CP5       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 6.--7. " CP3       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 2.--3. " CP1       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                      "
group.long c15:0x000b++0x00
line.long 0x00 "SPCR,Slave Port Control Register"
bitfld.long 0x00 1. " PRIV    ,Privilege access only" "User/Privilege,Privilege only"
bitfld.long 0x00 0. "  AXISLEN ,AXI slave port disable" "Enabled,Disabled"
tree.end
width 0x8
tree "MPU Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x05++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 11. "            RW       ,Access Caused an Abort Type" "Read,Write"
textline "                 "
bitfld.long 0x00 4.--7. " DOMAIN   ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10.  "               STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x15++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x06++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
textline " "
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 0.--3. 10. "            STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
textline " "
group.long c15:0x0016++0x00
line.long 0x00 "RBAR,Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group.long c15:0x0216++0x00
line.long 0x00 "RSER,Region Size and Enable Register"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group.long c15:0x0416++0x00
line.long 0x00 "RACR,Region Access Control Register"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " TYPE  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
group.long c15:0x0026++0x00
line.long 0x00 "MRNR,Memory Region Number Register"
bitfld.long 0x00 0.--3. " REGION  ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
group.long c15:0x010d++0x00
line.long 0x00 "CIDR,Context ID Register"
group.long c15:0x20d++0x00
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
group.long c15:0x30d++0x00
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
group.long c15:0x40d++0x00
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
width 0x08
tree "MPU regions"
group c15:0x0016++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RBAR0,Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RSER0,Region Size and Enable Register 0"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RACR0,Region Access Control Register 0"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RBAR1,Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RSER1,Region Size and Enable Register 1"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RACR1,Region Access Control Register 1"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RBAR2,Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RSER2,Region Size and Enable Register 2"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RACR2,Region Access Control Register 2"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RBAR3,Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RSER3,Region Size and Enable Register 3"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RACR3,Region Access Control Register 3"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RBAR4,Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RSER4,Region Size and Enable Register 4"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RACR4,Region Access Control Register 4"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RBAR5,Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RSER5,Region Size and Enable Register 5"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RACR5,Region Access Control Register 5"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RBAR6,Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RSER6,Region Size and Enable Register 6"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RACR6,Region Access Control Register 6"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RBAR7,Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RSER7,Region Size and Enable Register 7"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RACR7,Region Access Control Register 7"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RBAR8,Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RSER8,Region Size and Enable Register 8"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RACR8,Region Access Control Register 8"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RBAR9,Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RSER9,Region Size and Enable Register 9"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RACR9,Region Access Control Register 9"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RBAR10,Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RSER10,Region Size and Enable Register 10"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RACR10,Region Access Control Register 10"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RBAR11,Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RSER11,Region Size and Enable Register 11"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RACR11,Region Access Control Register 11"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RBAR12,Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RSER12,Region Size and Enable Register 12"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RACR12,Region Access Control Register 12"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RBAR13,Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RSER13,Region Size and Enable Register 13"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RACR13,Region Access Control Register 13"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RBAR14,Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RSER14,Region Size and Enable Register 14"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RACR14,Region Access Control Register 14"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RBAR15,Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RSER15,Region Size and Enable Register 15"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RACR15,Region Access Control Register 15"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
tree.end
tree.end
width 0x9
tree "TCM Control and Configuration"
rgroup.long c15:0x200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
group.long c15:0x019++0x00
line.long 0x00 "BTCMRR,BTCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
group.long c15:0x119++0x00
line.long 0x00 "ATCMRR,ATCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
rgroup.long c15:0x29++0x00
line.long 0x00 "TCMSEL,TCM Selection Register"
textline " "
group.long c15:0x10f++0x00
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x20f++0x00
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x30f++0x00
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU      ,Level of Unification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "  LOC       ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline "                     "
bitfld.long 0x00 21.--23. " CL8      ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "  CL7       ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 15.--17. " CL6      ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "  CL5       ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 9.--11. " CL4      ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "  CL3       ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 3.--5. " CL2      ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "  CL1       ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "  WB     ,Write-Back" "Not supported,Supported"
textline "                     "
bitfld.long 0x00 29. " RA       ,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. "  WA     ,Write-Allocate" "Not supported,Supported"
textline "                     "
hexmask.long.word 0x00 13.--27. 1. " NUMSETS  ,Number of sets"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Associativity"
textline "                     "
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
group.long c15:0x2000++0x00
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Cache level to select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "              IND    ,Instruction or data or unified cache to use" "Data/unified,Instruction"
group.long c15:0x03f++0x00
line.long 0x00 "CFLR,Correctable Fault Location Register"
bitfld.long 0x00 26.--29. " WAY      ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "             SIDE   ,Source of the error" "0,1,2,3"
textline "                     "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,index of the location where the error occurred"
bitfld.long 0x00 0.--1. "           TYPE   ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
group.long c15:0x5f++0x00
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
bitfld.long 0x00 30.--31. " WAY      ,Cache way to invalidate or clean" "0,1,2,3"
hexmask.long.byte 0x00 5.--10. 1. "              SET    ,Cache set to invalidate or clean"
group.long c15:0xef++0x00
line.long 0x00 "CSOR,Cache Size Override Register"
bitfld.long 0x00 4.--7. " Dcache   ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
bitfld.long 0x00 0.--3. "       Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
tree.end
width 12.
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "           IDCODE ,Identification code"
bitfld.long 0x00 11.--15. "           N  ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "           DP ,Disable PMCCNTR when prohibited" "No,Yes"
textline "                     "
bitfld.long 0x00 4. " X   ,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. "     D      ,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "  C  ,Clock counter reset" "No action,Reset"
bitfld.long 0x00 1. "    P  ,Event counter reset" "No action,Reset"
textline "                     "
bitfld.long 0x00 0. " E   ,Enable" "Disabled,Enabled"
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
eventfld.long 0x00 31. " C   ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00  2. "  P2     ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00  1. "  P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00  0. "  P0 ,PMN0 overflowed" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x0 "PMSWINC,Software Increment Register"
eventfld.long 0x00  2. " P2  ,Increment  PMN2" "No action,Increment"
eventfld.long 0x00  1. "    P1     ,Increment  PMN1" "No action,Increment"
eventfld.long 0x00  0. "    P0 ,Increment  PMN0" "No action,Increment"
group.long c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
group.long c15:0x02d9++0x00
line.long 0x00 "PMXEVCNTR,Event Count Register"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Cycle Count Register"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "ESR0,Event Selection Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "ESR1,Event Selection Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "ESR2,Event Selection Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00  0. " EN  ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
tree "Validation Registers"
group.long c15:0x01f++0x00
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x11f++0x00
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x21f++0x00
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x31f++0x00
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
group.long c15:0x41f++0x00
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x51f++0x00
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x61f++0x00
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x71f++0x00
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
tree.end
tree.end
width 11.
width 18.
tree "Debug Registers"
tree "Processor Identifier Registers"
rgroup.long c14:832.++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL       ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 "               SPECREV    ,Variant number"
textline "                           "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH       ,Architecture"
hexmask.long.word 0x0 4.--15. 0x1 "               PARTNUM    ,Part Number"
textline "                           "
hexmask.long.byte 0x0 0.--3. 0x1 " REV        ,Layout Revision"
rgroup.long c14:833.++0x00
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE   ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. "  L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " IMINLINE   ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup.long c14:834.++0x00
line.long 0x00 "TCMTR,TCM Type Register"
group.long c14:835.++0x00
line.long 0x00 "AMIDR,Alias of MIDR"
rgroup.long c14:836.++0x00
line.long 0x00 "MPUTR,MPU Type Register"
rgroup.long c14:837.++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
group.long c14:838.++0x00
line.long 0x00 "AMIDR0,Alias of MIDR"
group.long c14:839.++0x00
line.long 0x00 "AMIDR1,Alias of MIDR"
rgroup.long c14:840.++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3     ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        STATE2     ,Java Extension Interface Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " STATE1     ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        STATE0     ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c14:841.++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM        ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "        SE         ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " PM         ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c14:842.++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM     ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    TDM_MM     ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " TDM_CB     ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CDM_MM     ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SDM_CB     ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    CDM_CB     ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c14:843.++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c14:844.++0x00
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " CC_PLEA    ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CC_CPUA    ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c14:845.++0x00
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "     L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c14:846.++0x00
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "    WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c14:847.++0x00
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c14:848.++0x00
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "    DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "    CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "        BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " AI         ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:849.++0x00
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:850.++0x00
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:851.++0x00
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        SWII       ,SWI Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:852.++0x00
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c14:853.++0x00
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 15.
tree "Coresight Management Registers"
group.long c14:960.++0x00
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x00 0. " INTMODE      ,Processor integration mode" "Normal,Integration"
group.long c14:1000.++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS          ,Claim tag set"
group.long c14:1001.++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x00 0.--7. 1. " CTC          ,Claim tag clear"
wgroup.long c14:1004.++0x00
line.long 0x00 "DBGLAR,Lock Access Register"
rgroup.long c14:1005.++0x00
line.long 0x00 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " 32BA         ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
textline "                        "
bitfld.long 0x00 1. " LB           ,Lock bit" "Not locked,Locked"
bitfld.long 0x00 0. "              LIB          ,Lock implemented bit" "Not locked,Locked"
rgroup.long c14:1006.++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
bitfld.long 0x00 7. " SNDFI        ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "         SNDFE        ,Secure non-invasive debug features enable" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " SIDFI        ,Secure invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "         SIDFE        ,Secure invasive debug features enabled" "Disabled,Enabled"
rgroup.long c14:1011.++0x00
line.long 0x00 "DBGDEVTYPE,Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE      ,Subtype"
hexmask.long.byte 0x00 0.--3. 1. "                      MAIN_CLASS   ,Main class"
tree.end
textline "                     "
width 12.
rgroup.long c14:0.++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP          ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
bitfld.long 0x0 24.--27. "                       BRP          ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
textline "                     "
bitfld.long 0x0 20.--23. " CTX_CMP      ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.byte 0x0 16.--19. 1. "                      VERSION      ,Debug Architecture Version"
textline "                     "
bitfld.long 0x0 15. " DEVID        ,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "                    NSUHD        ,Secure User halting debug-mode" "Low,High"
textline "                     "
bitfld.long 0x0 13. " PCSR         ,PC Sample register implemented" "Low,High"
bitfld.long 0x0 12. "                    SE           ,Security Extensions implemented" "Low,High"
textline "                     "
hexmask.long.byte 0x0 4.--7. 1. " VARIANT      ,Implementation-defined Variant Number"
hexmask.long.byte 0x0 0.--3. 1. "                      REVISION     ,Implementation-defined Revision Number"
group.long c14:34.++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
bitfld.long 0x00 30. " RXFULL       ,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "                   TXFULL       ,DBGDTRTX Register full" "Empty,Full"
textline "                     "
bitfld.long 0x00 25. " PIPEADV      ,PIPEADV Processor Idle flag" "Not idle,Idle"
bitfld.long 0x00 24. "                INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
textline "                     "
bitfld.long 0x00 20.--21. " EXTDCCMODE   ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x00 19. "            ADADISCARD   ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
bitfld.long 0x00 18. "         NS      ,Non-secure status bit" "Secure,Non-secure"
textline "                     "
bitfld.long 0x00 17. " SPNIDDIS     ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "                     SPIDDIS      ,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "            MDBGEN  ,Monitor debug-mode enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 14. " HDBGEN       ,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 13. "                ITREN        ,Execute ARM instruction enable" "Disabled,Enabled"
bitfld.long 0x00 12. "       UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " INTDIS       ,Interrupt disable" "No,Yes"
bitfld.long 0x00 10. "                     DBGACK       ,Force debug acknowledge" "Normal,Forced"
textline "                     "
bitfld.long 0x00 8. " UND_L        ,Sticky undefined bit" "Not occurred,Occurred"
bitfld.long 0x00 7. "            ADABORT      ,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. "    SDABORT ,Synchronous data abort" "Not aborted,Aborted"
textline "                     "
bitfld.long 0x00 2.--5. " MOE          ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
bitfld.long 0x00 1. "  RESTARTED    ,Processor restarted" "Pending,Exited"
bitfld.long 0x00 0. "        HALTED  ,Processor halted" "Non-debug,Debug"
group.long c14:0x7++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 7. " FIQVCE_S     ,FIQ vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " IRQVCE_S     ,IRQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "                DAVCE_S      ,Data Abort vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " PAVCE_S      ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. "                SVCVCE_S     ,SVC vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 1. " UIVCE_S      ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "                RVCE         ,Reset vector catch enable" "Disabled,Enabled"
hgroup.long c14:32.++0x0
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
in
group.long c14:35.++0x00
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
hexmask.long 0x00 0.--31. 1. " HTD          ,Host -> target data"
group.long c14:10.++0x0
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT          ,Write through disable" "No,Yes"
bitfld.long 0x00 1. "                     NIL          ,L1 instruction cache line-fills disable" "No,Yes"
textline "                     "
bitfld.long 0x00 0. " NDL          ,L1 data cache line-fills disable" "No,Yes"
wgroup.long c14:33.++0x0
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup.long c14:36.++0x0
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 4. " CMR          ,Cancel memory requests" "Not cancel,Cancel"
bitfld.long 0x00 3. "              CSPA         ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
textline "                     "
bitfld.long 0x00 2. " CSE          ,Clear Sticky Exceptions bits" "No effect,Clear"
bitfld.long 0x00 1. "               RR           ,Restart request" "No effect,Restart"
textline "                     "
bitfld.long 0x00 0. " HR           ,Halt request" "No effect,Halt"
textline "                     "
rgroup.long c14:193.++0x0
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
group.long c14:196.++0x0
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
bitfld.long 0x00 2. " HCWR         ,Hold core warm reset" "Not held,Held"
textline "                     "
bitfld.long 0x00 1. " CWRR         ,Reset reguest" "Not requested,Requested"
bitfld.long 0x00 0. "    CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
rgroup.long c14:197.++0x0
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
bitfld.long 0x00 3. " SR           ,Sticky Reset Status" "Not reset,Reset"
bitfld.long 0x00 2. "        R         ,Reset Status" "No reset,Reset"
textline "                     "
bitfld.long 0x00 1. " SPD          ,Sticky Power-down Status" "Not reset,Reset"
bitfld.long 0x00 0. "        PU        ,Power-up Status" "Powered down,Powered up"
tree.end
width 7.
tree "Breakpoint Registers"
group.long c14:64.++0x0
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
group.long c14:80.++0x0
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:65.++0x0
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
group.long c14:81.++0x0
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:66.++0x0
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
group.long c14:82.++0x0
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:67.++0x0
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
group.long c14:83.++0x0
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:68.++0x0
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
group.long c14:84.++0x0
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:69.++0x0
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
group.long c14:85.++0x0
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:70.++0x0
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
group.long c14:86.++0x0
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:71.++0x0
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
group.long c14:87.++0x0
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.long c14:96.++0x0
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:112.++0x0
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:97.++0x0
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:113.++0x0
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:98.++0x0
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:114.++0x0
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:99.++0x0
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:115.++0x0
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:100.++0x0
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:116.++0x0
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:101.++0x0
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:117.++0x0
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:102.++0x0
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:118.++0x0
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:103.++0x0
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:119.++0x0
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:6.++0x0
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
tree.end
width 11.
AUTOINDENT.POP
tree.end
elif (CORENAME()=="CORTEXA72")
tree "Core Registers (Cortex-A72)"
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x0
line.quad 0x00 "MIDR_EL1,Main ID Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23.  "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19.  "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.quad spr:0x33001++0x0
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.quad spr:0x30005++0x00
line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register"
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
newline
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4"
rgroup.quad spr:0x30006++0x0
line.quad 0x00 "REVIDR_EL1,Revision ID Register"
rgroup.quad spr:0x30014++0x00
line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..."
newline
bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,2 levels,?..."
bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad spr:0x30015++0x00
line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..."
bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad spr:0x30016++0x00
line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad spr:0x30017++0x00
line.quad 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3"
bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.quad 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.quad 0x00 "ID_MMFR4_EL1,ID_MMFR4_EL1"
bitfld.quad 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
rgroup.quad spr:0x30020++0x00
line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.quad 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.quad spr:0x30021++0x00
line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.quad 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30022++0x00
line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.quad 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad spr:0x30023++0x00
line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30024++0x00
line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.quad 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad spr:0x30025++0x00
line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2, SHA2 instructions are implemented" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1, SHA1 instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
rgroup.quad spr:0x30010++0x00
line.quad 0x00 "ID_PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30011++0x00
line.quad 0x00 "ID_PFR1_EL1,Processor Feature Register 1"
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,Support for the GIC System register interface" "Not supported,GICv3 supported,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,Implemented,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,Implemented,?..."
rgroup.quad spr:0x30012++0x00
line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..."
bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,PMUv3,?..."
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug v8-A,?..."
rgroup.quad spr:0x339C6++0x0
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented"
bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented"
bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented"
bitfld.quad 0x00 25. "DA,Bus access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented"
bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.quad 0x00 13. "BI,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented"
bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented"
newline
bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented"
bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.quad spr:0x33007++0x00
line.quad 0x00 "DCZID_EL0,Data Cache Zero ID"
bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Thread Pointer/ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Thread Pointer/ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Thread Pointer/ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Thread Pointer/ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Thread Pointer/ID Register"
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced"
newline
bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced"
newline
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
newline
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
newline
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
newline
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
newline
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes"
newline
bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes"
bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes"
newline
bitfld.quad 0x00 41. "ESHWSHAEP,Enables snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests"
bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error"
group.quad spr:0x34101++0x0
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register"
bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad spr:0x36101++0x0
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register"
bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap EL0/EL1,Trap EL0,Trap EL0/EL1,No trap"
group.quad spr:0x36110++0x0
line.quad 0x00 "SCR_EL3,Secure Configuration Register"
bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
bitfld.quad 0x00 3. "EA,External Abort and SError Interrupt Routing" "Not to EL3,To EL3"
newline
bitfld.quad 0x00 2. "FIQ,Physical FIQ Routing" "Not to EL3,To EL3"
bitfld.quad 0x00 1. "IRQ,Physical IRQ Routing" "Not to EL3,To EL3"
newline
bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers 0 (EL1)"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers 1 (EL1)"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers 0 (EL2)"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers 1 (EL2)"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers 0 (EL3)"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers 1 (EL3)"
tree.open "Exception Syndrome Registers"
if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
newline
bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable"
newline
bitfld.quad 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable"
bitfld.quad 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave,"
elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
newline
bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt"
elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
newline
bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined"
elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt"
elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
tree.end
newline
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level"
rgroup.quad spr:0x30C10++0x00
line.quad 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.quad spr:0x36C02++0x00
line.quad 0x00 "RMR_EL3,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address"
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]"
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID registers"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID registers"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID registers"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID registers"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID registers"
tree.end
tree "Memory Management Unit"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,Reserved,Reserved"
newline
bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KB,64 KB"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB"
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved"
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,16 KB,Reserved"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved"
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,16 KB,Reserved"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad spr:0x34300++0x00
line.quad 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.quad 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.quad 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device,?..."
newline
hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000)))
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--47. 0x1000 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st level,Synchronous parity error on memory access on translation table walk/2nd level,Synchronous parity error on memory access on translation table walk/3rd level,Reserved,Alignment fault,Debug event,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
tree.end
newline
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
tree.end
tree "Virtualization Extensions"
group.quad spr:0x34000++0x0
line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register"
group.quad spr:0x34005++0x00
line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes"
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.quad 0x00 28. "TDZ,Traps DC ZVA instruction" "Disabled,Enabled"
bitfld.quad 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.quad 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.quad 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
bitfld.quad 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
newline
bitfld.quad 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
bitfld.quad 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.quad 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
group.quad spr:0x34111++0x00
line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.quad spr:0x36131++0x00
line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpointregisters disabled" "No,Yes"
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
group.quad spr:0x34112++0x00
line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad spr:0x36112++0x00
line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad spr:0x34113++0x00
line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.quad 0x00 16. "TTEE,Trap T32EE" "Disabled,Enabled"
bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap"
bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap"
newline
bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap"
bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap"
bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap"
newline
bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap"
bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap"
bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap"
newline
bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap"
bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap"
bitfld.quad 0x00 4. "T4,Trap to Hypervisor mode Non-secure priv 4" "No effect,Trap"
newline
bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap"
bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap"
bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap"
newline
bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (((per.q(spr:0x34212))&0xC000)==0x0000)
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..."
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate"
bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 2,Level 1,Level 0,?..."
newline
bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..."
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate"
bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 3,Level 2,Level 1,?..."
newline
bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address"
tree.end
tree "Cache Control and Configuration"
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,CTR_EL0"
bitfld.quad 0x0 29.--31. "FORMAT,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical"
bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..."
group.quad spr:0x32000++0x0
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
rgroup.quad spr:0x31001++0x0
line.quad 0x00 "CLIDR_EL1,Cache Level ID Register"
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.quad 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.quad 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.quad 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.quad 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..."
rgroup.quad spr:0x31000++0x0
line.quad 0x00 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,Supported"
bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
newline
bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32bytes,64 bytes,128 bytes,?..."
tree "Level 1 memory system"
group.quad spr:0x30F10++0x00
line.quad 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register"
group.quad spr:0x30F11++0x00
line.quad 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register"
group.quad spr:0x30F12++0x00
line.quad 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register"
group.quad spr:0x30F13++0x00
line.quad 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register"
group.quad spr:0x30F14++0x00
line.quad 0x00 "DL1DATA4_EL1,Data L1 Data 3 Register"
group.quad spr:0x30F00++0x00
line.quad 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register"
group.quad spr:0x30F01++0x00
line.quad 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register"
group.quad spr:0x30F02++0x00
line.quad 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register"
group.quad spr:0x30F03++0x00
line.quad 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register"
tree.end
tree "Level 2 memory system"
group.quad spr:0x31B02++0x0
line.quad 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.quad 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset"
bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.quad 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported"
newline
rbitfld.quad 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported"
bitfld.quad 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled"
bitfld.quad 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
newline
rbitfld.quad 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
rbitfld.quad 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.quad 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..."
newline
bitfld.quad 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.quad 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
newline
bitfld.quad 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles"
group.quad spr:0x31B03++0x0
line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad spr:0x31F00++0x00
line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.quad 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU"
bitfld.quad 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random"
bitfld.quad 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.quad 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.quad 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes"
bitfld.quad 0x00 23. "DACPMUWLUT,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes"
bitfld.quad 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.quad 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.quad 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.quad 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.quad 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled"
bitfld.quad 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
newline
bitfld.quad 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes"
bitfld.quad 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.quad 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.quad 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes"
bitfld.quad 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.quad 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
newline
bitfld.quad 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
bitfld.quad 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes"
bitfld.quad 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes"
bitfld.quad 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.quad 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
tree.end
tree.end
tree "System Performance Monitor"
group.quad spr:0x339C0++0x00
line.quad 0x00 "PMCR_EL0,Performance Monitor Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad spr:0x339C1++0x00
line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register "
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.quad spr:0x339C2++0x00
line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.quad spr:0x339C3++0x00
line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.quad 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
wgroup.quad spr:0x339C4++0x00
line.quad 0x00 "PMSWINC_EL0,Performance Monitors Software Increment Register"
bitfld.quad 0x00 5. "P5,Increment  PMN5" "No action,Increment"
bitfld.quad 0x00 4. "P4,Increment  PMN4" "No action,Increment"
bitfld.quad 0x00 3. "P3,Increment  PMN3" "No action,Increment"
newline
bitfld.quad 0x00 2. "P2,Increment  PMN2" "No action,Increment"
bitfld.quad 0x00 1. "P1,Increment  PMN1" "No action,Increment"
bitfld.quad 0x00 0. "P0,Increment  PMN0" "No action,Increment"
group.quad spr:0x339C5++0x00
line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register"
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,%d..."
tree.open "Common Event Identification Registers"
group.quad spr:0x339c6++0x00
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented"
newline
bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented"
bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented"
bitfld.quad 0x00 25. "BA,Bus access" "Not implemented,Implemented"
bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented"
bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented"
bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented"
bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented"
newline
bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented"
bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
group.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
group.quad spr:0x339D2++0x00
line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
group.quad spr:0x339E0++0x00
line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.quad spr:0x309E1++0x00
line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
newline
bitfld.quad 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad spr:0x309E2++0x00
line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00  5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00  4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00  3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00  2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00  1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00  0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.quad spr:0x339E3++0x00
line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
group.quad spr:(0x33E80+0x0)++0x00
line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.quad spr:(0x33EC0+0x0)++0x00
line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad spr:(0x33E80+0x1)++0x00
line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.quad spr:(0x33EC0+0x1)++0x00
line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad spr:(0x33E80+0x2)++0x00
line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.quad spr:(0x33EC0+0x2)++0x00
line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad spr:(0x33E80+0x3)++0x00
line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.quad spr:(0x33EC0+0x3)++0x00
line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad spr:(0x33E80+0x4)++0x00
line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.quad spr:(0x33EC0+0x4)++0x00
line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad spr:(0x33E80+0x5)++0x00
line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.quad spr:(0x33EC0+0x5)++0x00
line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad spr:0x33EF7++0x00
line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad spr:0x33E00++0x00
line.quad 0x00 "CNTFRQ_EL0,Counter Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register"
group.quad spr:0x30E10++0x00
line.quad 0x00 "CNTKCTL_EL1,Timer PL1 Control Register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad spr:0x33E20++0x00
line.quad 0x00 "CNTP_TVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register"
bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E30++0x00
line.quad 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register"
group.quad spr:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register"
bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register"
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad spr:0x34E20++0x00
line.quad 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register"
group.quad spr:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register"
bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register"
group.quad spr:0x37E20++0x00
line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register"
group.quad spr:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interruptidentifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "RM,Routing Modifier" "Normal,Special values"
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,EOI mode for interrupts handledat non-secure EL1 and EL2" "0,1"
bitfld.quad 0x00 3. "EOIMODE_EL1S,EOI mode for interrupts handled at secure EL1" "0,1"
bitfld.quad 0x00 2. "EOIMODE_EL3,EOI mode for interrupts handled at EL3" "0,1"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Non-secure accesses to GICC_BPR allowed." "Not allowed,Allowed"
bitfld.quad 0x00 0. "CBPR_EL1S,Secure EL1 accesses to ICC_BPR1 allowed" "Not allowed,Allowed"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt"
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x36CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.quad spr:0x30CC5++0x00
line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad spr:0x34C95++0x00
line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad spr:0x36CC5++0x00
line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
group.quad spr:0x34C80++0x00
line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Register 0-0"
rgroup.quad spr:0x34CB3++0x00
line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.quad spr:0x34CB5++0x00
line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.quad spr:0x34CB0++0x00
line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((per.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
rgroup.quad spr:0x34CB2++0x00
line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.quad spr:0x34CB7++0x00
line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.quad spr:0x34C94++0x00
line.quad 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register"
rgroup.quad spr:0x34CB1++0x00
line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
rgroup.quad spr:0x23010++0x00
line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad spr:0x20020++0x00
line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable Register"
bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
hexmask.quad.long 0x00 32.--63. 1. "HW,HighWord - Write/read DTRRX/DTRTX value without changing RXfull/TXfull"
hexmask.quad.long 0x00 0.--31. 1. "LW,LowWord - Write/read DTRTX/DTRRX value without changing TXfull/RXfull"
hgroup.quad spr:0x23050++0x00
hide.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
in
wgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad spr:0x24070++0x00
line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled"
group.quad spr:0x20002++0x00
line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
if (((per.q(spr:0x20114)&0x02)==0x00))
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full"
rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full"
newline
rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High"
newline
rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3"
rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High"
newline
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
else
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full"
newline
bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High"
newline
bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3"
bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High"
newline
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled"
newline
bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
endif
group.quad spr:0x20032++0x00
line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad spr:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--43. 0x10 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad spr:0x20104++0x00
line.quad 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad spr:0x20114++0x00
line.quad 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x20134++0x00
line.quad 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad spr:0x20144++0x00
line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
group.quad spr:0x20786++0x00
line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set"
newline
bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad spr:0x20796++0x00
line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
if (((per.q(spr:0x207e6))&0xAA)==0xAA)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0xA8)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0xA2)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0xA0)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0x8A)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0x88)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0x82)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0x80)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0x2A)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0x28)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0x22)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0x20)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0x0A)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0x08)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.q(spr:0x207e6))&0xAA)==0x02)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.q(spr:0x207e6))&0xAA)==0x00)
rgroup.quad spr:0x207e6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
endif
group.quad spr:0x33450++0x00
line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
group.quad spr:0x33451++0x00
line.quad 0x00 "DLR_EL0,Debug Link Register"
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x000000)
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x800000)
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x200000)
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
else
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
if (((per.q(spr:0x20005+0x0))&0x400000)==0x400000)
group.quad spr:(0x20005+0x0)++0x0
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x0))&0x800000)==0x800000)
group.quad spr:(0x20005+0x0)++0x0
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x0)++0x0
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 1"
if (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x000000)
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x800000)
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x200000)
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
else
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
if (((per.q(spr:0x20005+0x10))&0x400000)==0x400000)
group.quad spr:(0x20005+0x10)++0x0
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x10))&0x800000)==0x800000)
group.quad spr:(0x20005+0x10)++0x0
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x10)++0x0
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 2"
if (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x000000)
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x800000)
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x200000)
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
else
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
if (((per.q(spr:0x20005+0x20))&0x400000)==0x400000)
group.quad spr:(0x20005+0x20)++0x0
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x20))&0x800000)==0x800000)
group.quad spr:(0x20005+0x20)++0x0
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x20)++0x0
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 3"
if (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x000000)
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x800000)
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x200000)
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
else
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
if (((per.q(spr:0x20005+0x30))&0x400000)==0x400000)
group.quad spr:(0x20005+0x30)++0x0
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x30))&0x800000)==0x800000)
group.quad spr:(0x20005+0x30)++0x0
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x30)++0x0
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 4"
if (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x000000)
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x800000)
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x200000)
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
else
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
if (((per.q(spr:0x20005+0x40))&0x400000)==0x400000)
group.quad spr:(0x20005+0x40)++0x0
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x40))&0x800000)==0x800000)
group.quad spr:(0x20005+0x40)++0x0
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x40)++0x0
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree "Breakpoint 5"
if (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x000000)
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x800000)
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x200000)
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
else
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
if (((per.q(spr:0x20005+0x50))&0x400000)==0x400000)
group.quad spr:(0x20005+0x50)++0x0
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x50))&0x800000)==0x800000)
group.quad spr:(0x20005+0x50)++0x0
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x50)++0x0
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
endif
tree.end
tree.end
tree "Watchpoint Control Registers"
tree "Watchpoint 0"
group.quad spr:(0x20006+0x0)++0x00
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 1"
group.quad spr:(0x20006+0x10)++0x00
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 2"
group.quad spr:(0x20006+0x20)++0x00
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 3"
group.quad spr:(0x20006+0x30)++0x00
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0000++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x0100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.long c15:0x0300++0x00
line.long 0x00 "TLBTR,TLB Type Register"
bitfld.long 0x00 0. "NU,Not Unified. Indicates whether the implementation has a unified TLB" "Unified,"
rgroup.long c15:0x0500++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largery independent,Very interdependent"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.long 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4"
rgroup.long c15:0x0600++0x00
line.long 0x00 "REVIDR,Revision ID Register"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,ID_MMFR4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
rgroup.long c15:0x6C9++0x00
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "CH,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "BC,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.long 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "ME,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "BA,Bus access" "Not implemented,Implemented"
newline
bitfld.long 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "MA,Data memory access" "Not implemented,Implemented"
newline
bitfld.long 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "CC,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "UL,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "BI,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.long 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "ET,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "ST,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
newline
bitfld.long 0x00 6. "LD,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
tree.end
tree "System Control and Configuration"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
else
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
endif
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced"
newline
bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced"
newline
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
newline
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
newline
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
newline
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
newline
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes"
newline
bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes"
bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes"
newline
bitfld.quad 0x00 41. "ESHWSHAEP,Enable snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests"
bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error"
group.long c15:0x0101++0x00
line.long 0x00 "ACTLR,Auxiliary Control Register"
group.long c15:0x0201++0x00
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 28. "TRCDIS,Disable CP14 access to trace registers" "No,"
newline
bitfld.long 0x00 22.--23. "CP11,Coprocesor access control" "Denied,EL1 or higher,Reserved,Full"
bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
group.long c15:0x0011++0x00
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
rgroup.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
rgroup.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long"
newline
bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[43:32],Periphbase[43:32]"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
tree.end
tree "Memory Management Unit"
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,ThumbEE Enable" "Not implemented,"
bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled"
bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled"
group.long c15:0x4001++0x00
line.long 0x00 "HSCTLR,Hypervisor System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled"
bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled"
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x02))
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
newline
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x00))
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address"
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address"
endif
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x02))
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base 1 Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
newline
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x00))
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address"
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR0/TTBR1 ASID field" "TTBR0,TTBR1"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
endif
if (((per.l(c15:0x4202))&0x07)==0x00)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x01)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x02)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x03)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x04)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x05)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x06)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address"
else
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Outer Non-cacheable,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 8.--9. "IRGN0,  ,Inner cacheability attribute, Normal memory" "Inner Non-cacheable,Inner Write-Back Write-Allocate Cacheable,Inner Write-Through Cacheable,Inner Write-Back no Write-Allocate Cacheable"
hexmask.long.byte 0x00 0.--2. 0x1 "T0SZ, ,Size offset of the memory region addressed by HTTBR"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address"
newline
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "No,Yes"
newline
bitfld.long 0x00 9. "NS,Non-secure" "No,Yes"
bitfld.long 0x00 7. "SH,Shareable attribute for the region" "No,Yes"
newline
bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Strongly-ordered,Reserved,Device,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 1. "SS,Supersection" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
newline
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
newline
newline
newline
bitfld.long 0x00 6. "FS[5],Fault status bit - External abort type" "DECERR,SLVERR"
newline
bitfld.long 0x00 1.--5. "FS[0:4],Fault status bit - Fault source" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external abort/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external abort on translation table walk/1st level,Permission/1st level,Sync. external abort on translation table walk/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external abort,Reserved,Async. parity error on memory access,Sync. parity error on memory access,Reserved,Reserved,Sync. parity error on translation table walk/1st level,Reserved,Sync. parity error on translation table walk/2nd level,?..."
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0))
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA"
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes"
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
newline
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address/0th level,Address/1st level,Address/2nd level,Address/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. ext. abort,Async. external abort,Reserved,Reserved,Sync. ext. abort/0th level,Sync. ext. abort/1st level,Sync. ext. abort/2nd level,Sync. ext. abort/3rd level,Sync. parity error on memory access,Async. parity error on memory access,Reserved,Reserved,Reserved,Sync. parity error on translation table walk/0th level,Sync. parity error on translation table walk/1st level,Sync. parity error on translation table walk/2nd level,Sync. parity error on translation table walk/3rd level,Reserved,Alignment,Debug event,?..."
newline
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00))
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
else
hgroup.long c15:0x002A++0x00
hide.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
endif
if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00))
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
else
hgroup.long c15:0x012A++0x00
hide.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
endif
if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00))
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
else
hgroup.long c15:0x402A++0x00
hide.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
endif
if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..."
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00))
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient"
else
hgroup.long c15:0x412A++0x00
hide.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
endif
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x002A++0x00
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Non-shareable,Shareable"
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Non-shareable,Shareable"
newline
bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Non-shareable,Shareable"
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Non-shareable,Shareable"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
group.long c15:0x012A++0x00
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
else
hgroup.long c15:0x002A++0x00
hide.long 0x00 "PRRR,Primary Region Remap Register"
hgroup.long c15:0x012A++0x00
hide.long 0x00 "NMRR,Normal Memory Remap Register"
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
endif
tree.end
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x00
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x00
line.long 0x00 "HSCTLR,Hypervisor System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled"
bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR access control" "Disabled,Enabled"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full"
newline
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
newline
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x00 20. "TTA,Trap Trace Access" "Not supported,"
newline
bitfld.long 0x00 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
newline
bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap"
bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap"
newline
bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap"
bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap"
newline
bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap"
bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap"
newline
bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap"
bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap"
newline
bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap"
bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap"
newline
bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap"
bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap"
newline
bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap"
bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap"
rgroup.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
if (((per.l(c15:0x4202))&0x07)==0x00)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x01)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x02)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x03)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x04)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x05)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address"
elif (((per.l(c15:0x4202))&0x07)==0x06)
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address"
else
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
if (((per.l(c15:0x4212))&0x0F)==0x00)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x01)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x02)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x03)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x04)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x05)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x06)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x07)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x08)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 22.--47. 0x40 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x09)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 21.--47. 0x20 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x0A)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 20.--47. 0x10 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x0B)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 19.--47. 0x8 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x0C)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 18.--47. 0x4 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x0D)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 17.--47. 0x2 "BADDR,Translation table base address"
elif (((per.l(c15:0x4212))&0x0F)==0x0E)
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad.long 0x00 16.--47. 0x1 "BADDR,Translation table base address"
else
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 15.--47. 0x80 "BADDR,Translation table base address"
endif
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "2nd level,1st level,,"
newline
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x54000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(c15:0x4025))&0xFC000000)==0x60000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
newline
bitfld.long 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0800000||0xB0800000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0000000||0xB0000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.l(c15:0x4025))&0xFD000000)==0xBD000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable"
newline
bitfld.long 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable"
bitfld.long 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave,"
elif (((per.l(c15:0x4025))&0xFD000000)==0xBC000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((per.l(c15:0x4025))&0xFC000000)==(0xC0000000||0xC4000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.l(c15:0x4025))&0xFC000000)==(0xC8000000||0xCC000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.l(c15:0x4025))&0xFC000000)==(0xD0000000||0xD4000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((per.l(c15:0x4025))&0xFC000000)==(0xE0000000||0xF0000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA,Bits [39:12] of the faulting intermediate physical address"
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,Reserved,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
newline
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
newline
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
rgroup.long c15:0x1700++0x0
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,"
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
tree "Level 1 memory system"
group.long c15:0x001F++0x00
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
group.long c15:0x011F++0x00
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
group.long c15:0x021F++0x00
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
group.long c15:0x031F++0x00
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
group.long c15:0x041F++0x00
line.long 0x00 "DL1DATA4,Data L1 Data 4 Register"
group.long c15:0x000F++0x00
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
group.long c15:0x010F++0x00
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
group.long c15:0x020F++0x00
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
group.long c15:0x030F++0x00
line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register"
wgroup.long c15:0x04F++0x00
line.long 0x00 "RAMINDEX,RAM Index Operation Register"
hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM identifier"
bitfld.long 0x00 18.--21. "WAY,Indicates the way of the RAM that is being accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the RAM that is being accessed"
tree.end
tree "Level 2 memory system"
group.long c15:0x1209++0x00
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.long 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported"
newline
rbitfld.long 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported"
bitfld.long 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled"
bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
newline
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..."
newline
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
newline
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles"
group.long c15:0x1309++0x00
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU"
bitfld.long 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.long 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.long 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes"
bitfld.long 0x00 23. "DACPMUWLU,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled"
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
newline
bitfld.long 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.long 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes"
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
bitfld.long 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes"
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes"
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad c15:0x130F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register "
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
newline
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.long c15:0x3c9++0x00
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 5. "P5,PMN5 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 4. "P4,PMN4 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 3. "P3,PMN3 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 2. "P2,PMN2 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 1. "P1,PMN1 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 0. "P0,PMN0 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear"
group.long c15:0x4c9++0x00
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
bitfld.long 0x00 5. "P5,Increment  PMN5" "No action,Increment"
bitfld.long 0x00 4. "P4,Increment  PMN4" "No action,Increment"
bitfld.long 0x00 3. "P3,Increment  PMN3" "No action,Increment"
newline
bitfld.long 0x00 2. "P2,Increment  PMN2" "No action,Increment"
bitfld.long 0x00 1. "P1,Increment  PMN1" "No action,Increment"
bitfld.long 0x00 0. "P0,Increment  PMN0" "No action,Increment"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
group.long c15:0x1d9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
group.long c15:0x2d9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
bitfld.long 0x00 5. "EVENT[5],Value of 5 event counter" "0,1"
bitfld.long 0x00 4. "EVENT[4],Value of 4 event counter" "0,1"
bitfld.long 0x00 3. "EVENT[3],Value of 3 event counter" "0,1"
newline
bitfld.long 0x00 2. "EVENT[2],Value of 2 event counter" "0,1"
bitfld.long 0x00 1. "EVENT[1],Value of 1 event counter" "0,1"
bitfld.long 0x00 0. "EVENT[0],Value of 0 event counter" "0,1"
newline
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.long c15:0x3e9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x40)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x40)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x40)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x40)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x40)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x40)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported"
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access."
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt"
hgroup.long c15:0x008C++0x00
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
in
hgroup.long c15:0x00CC++0x00
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
in
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Interrupt Controller Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Register 0-0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active priority 31" "0,1"
bitfld.long 0x00 30. "P30,Group 0 interrupt active priority 30" "0,1"
bitfld.long 0x00 29. "P29,Group 0 interrupt active priority 29" "0,1"
bitfld.long 0x00 28. "P28,Group 0 interrupt active priority 28" "0,1"
newline
bitfld.long 0x00 27. "P27,Group 0 interrupt active priority 27" "0,1"
bitfld.long 0x00 26. "P26,Group 0 interrupt active priority 26" "0,1"
bitfld.long 0x00 25. "P25,Group 0 interrupt active priority 25" "0,1"
bitfld.long 0x00 24. "P24,Group 0 interrupt active priority 24" "0,1"
newline
bitfld.long 0x00 23. "P23,Group 0 interrupt active priority 23" "0,1"
bitfld.long 0x00 22. "P22,Group 0 interrupt active priority 22" "0,1"
bitfld.long 0x00 21. "P21,Group 0 interrupt active priority 21" "0,1"
bitfld.long 0x00 20. "P20,Group 0 interrupt active priority 20" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active priority 19" "0,1"
bitfld.long 0x00 18. "P18,Group 0 interrupt active priority 18" "0,1"
bitfld.long 0x00 17. "P17,Group 0 interrupt active priority 17" "0,1"
bitfld.long 0x00 16. "P16,Group 0 interrupt active priority 16" "0,1"
newline
bitfld.long 0x00 15. "P15,Group 0 interrupt active priority 15" "0,1"
bitfld.long 0x00 14. "P14,Group 0 interrupt active priority 14" "0,1"
bitfld.long 0x00 13. "P13,Group 0 interrupt active priority 13" "0,1"
bitfld.long 0x00 12. "P12,Group 0 interrupt active priority 12" "0,1"
newline
bitfld.long 0x00 11. "P11,Group 0 interrupt active priority 11" "0,1"
bitfld.long 0x00 10. "P10,Group 0 interrupt active priority 10" "0,1"
bitfld.long 0x00 9. "P9,Group 0 interrupt active priority 9" "0,1"
bitfld.long 0x00 8. "P8,Group 0 interrupt active priority 8" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active priority 7" "0,1"
bitfld.long 0x00 6. "P6,Group 0 interrupt active priority 6" "0,1"
bitfld.long 0x00 5. "P5,Group 0 interrupt active priority 5" "0,1"
bitfld.long 0x00 4. "P4,Group 0 interrupt active priority 4" "0,1"
newline
bitfld.long 0x00 3. "P3,Group 0 interrupt active priority 3" "0,1"
bitfld.long 0x00 2. "P2,Group 0 interrupt active priority 2" "0,1"
bitfld.long 0x00 1. "P1,Group 0 interrupt active priority 1" "0,1"
bitfld.long 0x00 0. "P0,Group 0 interrupt active priority 0" "0,1"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Register 1-0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active priority 31" "0,1"
bitfld.long 0x00 30. "P30,Group 1 interrupt active priority 30" "0,1"
bitfld.long 0x00 29. "P29,Group 1 interrupt active priority 29" "0,1"
bitfld.long 0x00 28. "P28,Group 1 interrupt active priority 28" "0,1"
newline
bitfld.long 0x00 27. "P27,Group 1 interrupt active priority 27" "0,1"
bitfld.long 0x00 26. "P26,Group 1 interrupt active priority 26" "0,1"
bitfld.long 0x00 25. "P25,Group 1 interrupt active priority 25" "0,1"
bitfld.long 0x00 24. "P24,Group 1 interrupt active priority 24" "0,1"
newline
bitfld.long 0x00 23. "P23,Group 1 interrupt active priority 23" "0,1"
bitfld.long 0x00 22. "P22,Group 1 interrupt active priority 22" "0,1"
bitfld.long 0x00 21. "P21,Group 1 interrupt active priority 21" "0,1"
bitfld.long 0x00 20. "P20,Group 1 interrupt active priority 20" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active priority 19" "0,1"
bitfld.long 0x00 18. "P18,Group 1 interrupt active priority 18" "0,1"
bitfld.long 0x00 17. "P17,Group 1 interrupt active priority 17" "0,1"
bitfld.long 0x00 16. "P16,Group 1 interrupt active priority 16" "0,1"
newline
bitfld.long 0x00 15. "P15,Group 1 interrupt active priority 15" "0,1"
bitfld.long 0x00 14. "P14,Group 1 interrupt active priority 14" "0,1"
bitfld.long 0x00 13. "P13,Group 1 interrupt active priority 13" "0,1"
bitfld.long 0x00 12. "P12,Group 1 interrupt active priority 12" "0,1"
newline
bitfld.long 0x00 11. "P11,Group 1 interrupt active priority 11" "0,1"
bitfld.long 0x00 10. "P10,Group 1 interrupt active priority 10" "0,1"
bitfld.long 0x00 9. "P9,Group 1 interrupt active priority 9" "0,1"
bitfld.long 0x00 8. "P8,Group 1 interrupt active priority 8" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active priority 7" "0,1"
bitfld.long 0x00 6. "P6,Group 1 interrupt active priority 6" "0,1"
bitfld.long 0x00 5. "P5,Group 1 interrupt active priority 5" "0,1"
bitfld.long 0x00 4. "P4,Group 1 interrupt active priority 4" "0,1"
newline
bitfld.long 0x00 3. "P3,Group 1 interrupt active priority 3" "0,1"
bitfld.long 0x00 2. "P2,Group 1 interrupt active priority 2" "0,1"
bitfld.long 0x00 1. "P1,Group 1 interrupt active priority 1" "0,1"
bitfld.long 0x00 0. "P0,Group 1 interrupt active priority 0" "0,1"
tree.end
newline
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x459C++0x00
line.long 0x00 "ICH_SRE,Hypervisor System Register"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..."
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..."
newline
bitfld.long 0x0 16.--19. "VERSION,Debug Architecture Version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..."
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not implemented"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
hgroup.long c14:0x0050++0x0
hide.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)"
in
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
bitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "0,1,2,3"
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
newline
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
newline
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
wgroup.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
group.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)"
group.long c14:0x0687++0x0
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x0
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
if (((per.l(c14:0x06E7))&0xAA)==0xAA)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0xA8)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0xA2)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0xA0)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0x8A)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0x88)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0x82)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0x80)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0x2A)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0x28)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0x22)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0x20)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0x0A)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0x08)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
elif (((per.l(c14:0x06E7))&0xAA)==0x02)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
elif (((per.l(c14:0x06E7))&0xAA)==0x00)
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
endif
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" ",,No offset,?..."
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" ",Supported,?..."
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
hexmask.quad 0x0 12.--47. 0x10 "ROMADDR,ROM physical address"
bitfld.quad 0x0 0.--1. "VALID,ROM table address valid" "Not valid,,,Valid"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
hgroup.long c14:0x0260++0x00
hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Power down,Emulate"
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x0)++0x0
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
hgroup.long c14:(0x0400+0x0)++0x0
hide.long 0x00 "DBGBVR0,Breakpoint Value Register"
else
group.long c14:(0x0400+0x0)++0x0
line.long 0x00 "DBGBVR0,Breakpoint ContextID Register"
endif
group.long c14:(0x0500+0x0)++0x0
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..."
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 1"
if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x10)++0x0
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
hgroup.long c14:(0x0400+0x10)++0x0
hide.long 0x00 "DBGBVR1,Breakpoint Value Register"
else
group.long c14:(0x0400+0x10)++0x0
line.long 0x00 "DBGBVR1,Breakpoint ContextID Register"
endif
group.long c14:(0x0500+0x10)++0x0
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..."
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 2"
if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x20)++0x0
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
hgroup.long c14:(0x0400+0x20)++0x0
hide.long 0x00 "DBGBVR2,Breakpoint Value Register"
else
group.long c14:(0x0400+0x20)++0x0
line.long 0x00 "DBGBVR2,Breakpoint ContextID Register"
endif
group.long c14:(0x0500+0x20)++0x0
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..."
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 3"
if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x30)++0x0
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
hgroup.long c14:(0x0400+0x30)++0x0
hide.long 0x00 "DBGBVR3,Breakpoint Value Register"
else
group.long c14:(0x0400+0x30)++0x0
line.long 0x00 "DBGBVR3,Breakpoint ContextID Register"
endif
group.long c14:(0x0500+0x30)++0x0
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..."
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 4"
if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x40)++0x0
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
hgroup.long c14:(0x0400+0x40)++0x0
hide.long 0x00 "DBGBVR4,Breakpoint Value Register"
else
group.long c14:(0x0400+0x40)++0x0
line.long 0x00 "DBGBVR4,Breakpoint ContextID Register"
endif
if (((per.l(c14:(0x500+0x40)))&0x800000)==0x800000)
group.long c14:(0x0101+0x40)++0x0
line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register"
hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison"
else
hgroup.long c14:(0x0101+0x40)++0x0
hide.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register"
endif
group.long c14:(0x0500+0x40)++0x0
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..."
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Breakpoint 5"
if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x50)++0x0
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
hgroup.long c14:(0x0400+0x50)++0x0
hide.long 0x00 "DBGBVR5,Breakpoint Value Register"
else
group.long c14:(0x0400+0x50)++0x0
line.long 0x00 "DBGBVR5,Breakpoint ContextID Register"
endif
if (((per.l(c14:(0x500+0x50)))&0x800000)==0x800000)
group.long c14:(0x0101+0x50)++0x0
line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register"
hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison"
else
hgroup.long c14:(0x0101+0x50)++0x0
hide.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register"
endif
group.long c14:(0x0500+0x50)++0x0
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..."
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree.end
tree "Watchpoint Control Registers"
tree "Watchpoint 0"
group.long c14:(0x0600+0x0)++0x00
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..."
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 1"
group.long c14:(0x0600+0x10)++0x00
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..."
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 2"
group.long c14:(0x0600+0x20)++0x00
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..."
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint 3"
group.long c14:(0x0600+0x30)++0x00
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..."
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree.end
tree.end
AUTOINDENT.OFF
tree.open "Interrupt Controller (GIC-500)"
base COMP.BASE("GICD",-1.)
width 17.
tree "Distributor Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)))
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 6. "       DS            ,Disable Security" "No,Yes"
textline "                          "
bitfld.long 0x00 5. " ARE_NS       ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_S      ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       ENABLEGRP1S   ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_NS        ,Affinity Routing Enable" "Reserved,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1A  ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
rbitfld.long 0x00 6. "       DS            ,Disable Security" "Reserved,Yes"
textline "                          "
bitfld.long 0x00 4. " ARE          ,Affinity Routing Enable" "Reserved,Enabled"
bitfld.long 0x00 1. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0    ,Enable Group 0 interrupts" "Disabled,Enabled"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 25. " NO1N         ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported"
bitfld.long 0x00 24. "  A3V        ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported"
bitfld.long 0x00 19.--23. "  IDBITS        ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
textline "                          "
bitfld.long 0x00 17. " LPIS         ,Indicates whether the implementation supports LPIs" "Not supported,Supported"
bitfld.long 0x00 16. "  MBIS       ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported"
bitfld.long 0x00 10. "  SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER    ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 0.--4. "              ITLN       ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved"
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID       ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "        VAR        ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV          ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "             IMP        ,Implementer"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000)
wgroup.long 0x40++0x03
line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
wgroup.long 0x48++0x03
line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
wgroup.long 0x50++0x03
line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
wgroup.long 0x58++0x03
line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
endif
else
hgroup.long 0x40++0x03
hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hgroup.long 0x48++0x03
hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register"
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register"
endif
width 17.
tree "Group Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080))
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30  ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29  ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27  ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26  ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24  ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23  ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21  ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20  ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18  ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17  ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15  ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14  ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12  ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11  ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9   ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8   ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6   ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5   ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3   ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2   ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0   ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30  ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29  ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27  ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26  ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24  ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23  ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21  ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20  ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18  ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17  ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15  ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14  ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12  ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11  ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9   ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8   ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6   ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5   ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3   ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2   ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0   ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x0080++0x03
hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB62  ,Group Status Bit 62" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB61  ,Group Status Bit 61" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB59  ,Group Status Bit 59" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB58  ,Group Status Bit 58" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB56  ,Group Status Bit 56" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB55  ,Group Status Bit 55" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB53  ,Group Status Bit 53" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB52  ,Group Status Bit 52" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB50  ,Group Status Bit 50" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB49  ,Group Status Bit 49" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB47  ,Group Status Bit 47" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB46  ,Group Status Bit 46" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB44  ,Group Status Bit 44" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB43  ,Group Status Bit 43" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB41  ,Group Status Bit 41" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB40  ,Group Status Bit 40" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB38  ,Group Status Bit 38" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB37  ,Group Status Bit 37" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB35  ,Group Status Bit 35" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB34  ,Group Status Bit 34" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB32  ,Group Status Bit 32" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB62  ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB61  ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB59  ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB58  ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB56  ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB55  ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB53  ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB52  ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB50  ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB49  ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB47  ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB46  ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB44  ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB43  ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB41  ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB40  ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB38  ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB37  ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB35  ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB34  ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB32  ,Group Status Bit 32" "Group 0,Group 1"
else
hgroup.long 0x0084++0x03
hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)"
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB94  ,Group Status Bit 94" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB93  ,Group Status Bit 93" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB91  ,Group Status Bit 91" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB90  ,Group Status Bit 90" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB88  ,Group Status Bit 88" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB87  ,Group Status Bit 87" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB85  ,Group Status Bit 85" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB84  ,Group Status Bit 84" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB82  ,Group Status Bit 82" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB81  ,Group Status Bit 81" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB79  ,Group Status Bit 79" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB78  ,Group Status Bit 78" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB76  ,Group Status Bit 76" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB75  ,Group Status Bit 75" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB73  ,Group Status Bit 73" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB72  ,Group Status Bit 72" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB70  ,Group Status Bit 70" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB69  ,Group Status Bit 69" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB67  ,Group Status Bit 67" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB66  ,Group Status Bit 66" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB64  ,Group Status Bit 64" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB94  ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB93  ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB91  ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB90  ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB88  ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB87  ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB85  ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB84  ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB82  ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB81  ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB79  ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB78  ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB76  ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB75  ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB73  ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB72  ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB70  ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB69  ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB67  ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB66  ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB64  ,Group Status Bit 64" "Group 0,Group 1"
else
hgroup.long 0x0088++0x03
hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)"
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB99  ,Group Status Bit 99" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB98  ,Group Status Bit 98" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB96  ,Group Status Bit 96" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB126 ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB125 ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB123 ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB122 ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB120 ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB119 ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB117 ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB116 ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB114 ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB113 ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB111 ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB110 ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB108 ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB107 ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB105 ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB104 ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB102 ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB101 ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB99  ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB98  ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB96  ,Group Status Bit 96" "Group 0,Group 1"
else
hgroup.long 0x008C++0x03
hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)"
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB158 ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB157 ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB155 ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB154 ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB152 ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB151 ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB149 ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB148 ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB146 ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB145 ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB143 ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB142 ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB140 ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB139 ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB137 ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB136 ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB134 ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB133 ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB131 ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB130 ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB128 ,Group Status Bit 128" "Group 0,Group 1"
else
hgroup.long 0x0090++0x03
hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)"
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB190 ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB189 ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB187 ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB186 ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB184 ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB183 ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB181 ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB180 ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB178 ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB177 ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB175 ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB174 ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB172 ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB171 ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB169 ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB168 ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB166 ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB165 ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB163 ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB162 ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB160 ,Group Status Bit 160" "Group 0,Group 1"
else
hgroup.long 0x0094++0x03
hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)"
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB222 ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB221 ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB219 ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB218 ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB216 ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB215 ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB213 ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB212 ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB210 ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB209 ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB207 ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB206 ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB204 ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB203 ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB201 ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB200 ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB198 ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB197 ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB195 ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB194 ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB192 ,Group Status Bit 192" "Group 0,Group 1"
else
hgroup.long 0x0098++0x03
hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)"
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB254 ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB253 ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB251 ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB250 ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB248 ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB247 ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB245 ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB244 ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB242 ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB241 ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB239 ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB238 ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB236 ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB235 ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB233 ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB232 ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB230 ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB229 ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB227 ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB226 ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB224 ,Group Status Bit 224" "Group 0,Group 1"
else
hgroup.long 0x009C++0x03
hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)"
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB286 ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB285 ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB283 ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB282 ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB280 ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB279 ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB277 ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB276 ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB274 ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB273 ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB271 ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB270 ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB268 ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB267 ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB265 ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB264 ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB262 ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB261 ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB259 ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB258 ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB256 ,Group Status Bit 256" "Group 0,Group 1"
else
hgroup.long 0x00A0++0x03
hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)"
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB318 ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB317 ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB315 ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB314 ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB312 ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB311 ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB309 ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB308 ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB306 ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB305 ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB303 ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB302 ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB300 ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB299 ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB297 ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB296 ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB294 ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB293 ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB291 ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB290 ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB288 ,Group Status Bit 288" "Group 0,Group 1"
else
hgroup.long 0x00A4++0x03
hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB350 ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB349 ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB347 ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB346 ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB344 ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB343 ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB341 ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB340 ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB338 ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB337 ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB335 ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB334 ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB332 ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB331 ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB329 ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB328 ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB326 ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB325 ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB323 ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB322 ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB320 ,Group Status Bit 320" "Group 0,Group 1"
else
hgroup.long 0x00A8++0x03
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB382 ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB381 ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB379 ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB378 ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB376 ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB375 ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB373 ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB372 ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB370 ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB369 ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB367 ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB366 ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB364 ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB363 ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB361 ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB360 ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB358 ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB357 ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB355 ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB354 ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB352 ,Group Status Bit 352" "Group 0,Group 1"
else
hgroup.long 0x00AC++0x03
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB414 ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB413 ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB411 ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB410 ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB408 ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB407 ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB405 ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB404 ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB402 ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB401 ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB399 ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB398 ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB396 ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB395 ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB393 ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB392 ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB390 ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB389 ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB387 ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB386 ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB384 ,Group Status Bit 384" "Group 0,Group 1"
else
hgroup.long 0x00B0++0x03
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB446 ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB445 ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB443 ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB442 ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB440 ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB439 ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB437 ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB436 ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB434 ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB433 ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB431 ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB430 ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB428 ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB427 ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB425 ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB424 ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB422 ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB421 ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB419 ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB418 ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB416 ,Group Status Bit 416" "Group 0,Group 1"
else
hgroup.long 0x00B4++0x03
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB478 ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB477 ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB475 ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB474 ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB472 ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB471 ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB469 ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB468 ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB466 ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB465 ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB463 ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB462 ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB460 ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB459 ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB457 ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB456 ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB454 ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB453 ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB451 ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB450 ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB448 ,Group Status Bit 448" "Group 0,Group 1"
else
hgroup.long 0x00B8++0x03
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB510 ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB509 ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB507 ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB506 ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB504 ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB503 ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB501 ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB500 ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB498 ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB497 ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB495 ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB494 ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB492 ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB491 ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB489 ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB488 ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB486 ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB485 ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB483 ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB482 ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB480 ,Group Status Bit 480" "Group 0,Group 1"
else
hgroup.long 0x00BC++0x03
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB542 ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB541 ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB539 ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB538 ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB536 ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB535 ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB533 ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB532 ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB530 ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB529 ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB527 ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB526 ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB524 ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB523 ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB521 ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB520 ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB518 ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB517 ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB515 ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB514 ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB512 ,Group Status Bit 512" "Group 0,Group 1"
else
hgroup.long 0x00C0++0x03
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB574 ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB573 ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB571 ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB570 ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB568 ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB567 ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB565 ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB564 ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB562 ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB561 ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB559 ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB558 ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB556 ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB555 ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB553 ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB552 ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB550 ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB549 ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB547 ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB546 ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB544 ,Group Status Bit 544" "Group 0,Group 1"
else
hgroup.long 0x00C4++0x03
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB606 ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB605 ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB603 ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB602 ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB600 ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB599 ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB597 ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB596 ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB594 ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB593 ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB591 ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB590 ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB588 ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB587 ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB585 ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB584 ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB582 ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB581 ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB579 ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB578 ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB576 ,Group Status Bit 576" "Group 0,Group 1"
else
hgroup.long 0x00C8++0x03
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB638 ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB637 ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB635 ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB634 ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB632 ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB631 ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB629 ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB628 ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB626 ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB625 ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB623 ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB622 ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB620 ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB619 ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB617 ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB616 ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB614 ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB613 ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB611 ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB610 ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB608 ,Group Status Bit 608" "Group 0,Group 1"
else
hgroup.long 0x00CC++0x03
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB670 ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB669 ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB667 ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB666 ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB664 ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB663 ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB661 ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB660 ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB658 ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB657 ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB655 ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB654 ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB652 ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB651 ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB649 ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB648 ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB646 ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB645 ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB643 ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB642 ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB640 ,Group Status Bit 640" "Group 0,Group 1"
else
hgroup.long 0x00D0++0x03
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB702 ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB701 ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB699 ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB698 ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB696 ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB695 ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB693 ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB692 ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB690 ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB689 ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB687 ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB686 ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB684 ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB683 ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB681 ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB680 ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB678 ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB677 ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB675 ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB674 ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB672 ,Group Status Bit 672" "Group 0,Group 1"
else
hgroup.long 0x00D4++0x03
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB734 ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB733 ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB731 ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB730 ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB728 ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB727 ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB725 ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB724 ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB722 ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB721 ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB719 ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB718 ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB716 ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB715 ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB713 ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB712 ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB710 ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB709 ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB707 ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB706 ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB704 ,Group Status Bit 704" "Group 0,Group 1"
else
hgroup.long 0x00D8++0x03
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB766 ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB765 ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB763 ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB762 ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB760 ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB759 ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB757 ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB756 ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB754 ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB753 ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB751 ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB750 ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB748 ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB747 ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB745 ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB744 ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB742 ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB741 ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB739 ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB738 ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB736 ,Group Status Bit 736" "Group 0,Group 1"
else
hgroup.long 0x00DC++0x03
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB798 ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB797 ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB795 ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB794 ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB792 ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB791 ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB789 ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB788 ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB786 ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB785 ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB783 ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB782 ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB780 ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB779 ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB777 ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB776 ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB774 ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB773 ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB771 ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB770 ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB768 ,Group Status Bit 768" "Group 0,Group 1"
else
hgroup.long 0x00E0++0x03
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB830 ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB829 ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB827 ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB826 ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB824 ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB823 ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB821 ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB820 ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB818 ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB817 ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB815 ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB814 ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB812 ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB811 ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB809 ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB808 ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB806 ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB805 ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB803 ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB802 ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB800 ,Group Status Bit 800" "Group 0,Group 1"
else
hgroup.long 0x00E4++0x03
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB862 ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB861 ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB859 ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB858 ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB856 ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB855 ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB853 ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB852 ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB850 ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB849 ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB847 ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB846 ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB844 ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB843 ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB841 ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB840 ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB838 ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB837 ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB835 ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB834 ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB832 ,Group Status Bit 832" "Group 0,Group 1"
else
hgroup.long 0x00E8++0x03
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB894 ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB893 ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB891 ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB890 ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB888 ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB887 ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB885 ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB884 ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB882 ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB881 ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB879 ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB878 ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB876 ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB875 ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB873 ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB872 ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB870 ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB869 ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB867 ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB866 ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB864 ,Group Status Bit 864" "Group 0,Group 1"
else
hgroup.long 0x00EC++0x03
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB926 ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB925 ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB923 ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB922 ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB920 ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB919 ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB917 ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB916 ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB914 ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB913 ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB911 ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB910 ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB908 ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB907 ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB905 ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB904 ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB902 ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB901 ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB899 ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB898 ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB896 ,Group Status Bit 896" "Group 0,Group 1"
else
hgroup.long 0x00F0++0x03
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB958 ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB957 ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB955 ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB954 ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB952 ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB951 ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB949 ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB948 ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB946 ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB945 ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB943 ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB942 ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB940 ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB939 ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB937 ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB936 ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB934 ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB933 ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB931 ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB930 ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB928 ,Group Status Bit 928" "Group 0,Group 1"
else
hgroup.long 0x00F4++0x03
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB990 ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB989 ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB987 ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB986 ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB984 ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB983 ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB981 ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB980 ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB978 ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB977 ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB975 ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB974 ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB972 ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB971 ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB969 ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB968 ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB966 ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB965 ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB963 ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB962 ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB960 ,Group Status Bit 960" "Group 0,Group 1"
else
hgroup.long 0x00F8++0x03
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
endif
tree.end
width 24.
tree "Set/Clear Enable Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0100++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
hgroup.long 0x0104++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
hgroup.long 0x0108++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
hgroup.long 0x010C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
hgroup.long 0x0110++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
hgroup.long 0x0114++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
hgroup.long 0x0118++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
hgroup.long 0x011C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
hgroup.long 0x0120++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
hgroup.long 0x0124++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
hgroup.long 0x0128++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
hgroup.long 0x012C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
hgroup.long 0x0130++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
hgroup.long 0x0134++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
hgroup.long 0x0138++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
hgroup.long 0x013C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
hgroup.long 0x0140++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
hgroup.long 0x0144++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
hgroup.long 0x0148++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
hgroup.long 0x014C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
hgroup.long 0x0150++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
hgroup.long 0x0154++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
hgroup.long 0x0158++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
hgroup.long 0x015C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
hgroup.long 0x0160++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
hgroup.long 0x0164++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
hgroup.long 0x0168++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
hgroup.long 0x016C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
hgroup.long 0x0170++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
hgroup.long 0x0174++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
hgroup.long 0x0178++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0200++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
hgroup.long 0x0204++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
hgroup.long 0x0208++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
hgroup.long 0x020C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
hgroup.long 0x0210++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
hgroup.long 0x0214++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
hgroup.long 0x0218++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
hgroup.long 0x021C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
hgroup.long 0x0220++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
hgroup.long 0x0224++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
hgroup.long 0x0228++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
hgroup.long 0x022C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
hgroup.long 0x0230++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
hgroup.long 0x0234++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
hgroup.long 0x0238++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
hgroup.long 0x023C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
hgroup.long 0x0240++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
hgroup.long 0x0244++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
hgroup.long 0x0248++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
hgroup.long 0x024C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
hgroup.long 0x0250++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
hgroup.long 0x0254++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
hgroup.long 0x0258++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
hgroup.long 0x025C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
hgroup.long 0x0260++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
hgroup.long 0x0264++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
hgroup.long 0x0268++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
hgroup.long 0x026C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
hgroup.long 0x0270++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
hgroup.long 0x0274++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
hgroup.long 0x0278++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0300++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
hgroup.long 0x0304++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
hgroup.long 0x0308++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
hgroup.long 0x030C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
hgroup.long 0x0310++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
hgroup.long 0x0314++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
hgroup.long 0x0318++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
hgroup.long 0x031C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
hgroup.long 0x0320++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
hgroup.long 0x0324++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
hgroup.long 0x0328++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
hgroup.long 0x032C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
hgroup.long 0x0330++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
hgroup.long 0x0334++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
hgroup.long 0x0338++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
hgroup.long 0x033C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active"
else
hgroup.long 0x0340++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active"
else
hgroup.long 0x0344++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active"
else
hgroup.long 0x0348++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active"
else
hgroup.long 0x034C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active"
else
hgroup.long 0x0350++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active"
else
hgroup.long 0x0354++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active"
else
hgroup.long 0x0358++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active"
else
hgroup.long 0x035C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active"
else
hgroup.long 0x0360++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active"
else
hgroup.long 0x0364++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active"
else
hgroup.long 0x0368++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active"
else
hgroup.long 0x036C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active"
else
hgroup.long 0x0370++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active"
else
hgroup.long 0x0374++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active"
else
hgroup.long 0x0378++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
endif
tree.end
width 20.
tree "Priority Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x400++0x03
hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hgroup.long 0x404++0x03
hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hgroup.long 0x408++0x03
hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hgroup.long 0x40C++0x03
hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hgroup.long 0x410++0x03
hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hgroup.long 0x414++0x03
hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hgroup.long 0x418++0x03
hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hgroup.long 0x41C++0x03
hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
else
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
hgroup.long 0x420++0x03
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hgroup.long 0x424++0x03
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hgroup.long 0x428++0x03
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hgroup.long 0x42C++0x03
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hgroup.long 0x430++0x03
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hgroup.long 0x434++0x03
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hgroup.long 0x438++0x03
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hgroup.long 0x43C++0x03
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
hgroup.long 0x440++0x03
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hgroup.long 0x444++0x03
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hgroup.long 0x448++0x03
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hgroup.long 0x44C++0x03
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hgroup.long 0x450++0x03
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hgroup.long 0x454++0x03
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hgroup.long 0x458++0x03
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hgroup.long 0x45C++0x03
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
hgroup.long 0x460++0x03
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hgroup.long 0x464++0x03
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hgroup.long 0x468++0x03
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hgroup.long 0x46C++0x03
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hgroup.long 0x470++0x03
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hgroup.long 0x474++0x03
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hgroup.long 0x478++0x03
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hgroup.long 0x47C++0x03
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
hgroup.long 0x480++0x03
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hgroup.long 0x484++0x03
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hgroup.long 0x488++0x03
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hgroup.long 0x48C++0x03
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hgroup.long 0x490++0x03
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hgroup.long 0x494++0x03
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hgroup.long 0x498++0x03
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hgroup.long 0x49C++0x03
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
hgroup.long 0x4A0++0x03
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hgroup.long 0x4A4++0x03
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hgroup.long 0x4A8++0x03
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hgroup.long 0x4AC++0x03
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hgroup.long 0x4B0++0x03
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hgroup.long 0x4B4++0x03
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hgroup.long 0x4B8++0x03
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hgroup.long 0x4BC++0x03
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
hgroup.long 0x4C0++0x03
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hgroup.long 0x4C4++0x03
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hgroup.long 0x4C8++0x03
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hgroup.long 0x4CC++0x03
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hgroup.long 0x4D0++0x03
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hgroup.long 0x4D4++0x03
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hgroup.long 0x4D8++0x03
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hgroup.long 0x4DC++0x03
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
hgroup.long 0x4E0++0x03
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hgroup.long 0x4E4++0x03
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hgroup.long 0x4E8++0x03
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hgroup.long 0x4EC++0x03
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hgroup.long 0x4F0++0x03
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hgroup.long 0x4F4++0x03
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hgroup.long 0x4F8++0x03
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hgroup.long 0x4FC++0x03
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
hgroup.long 0x500++0x03
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hgroup.long 0x504++0x03
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hgroup.long 0x508++0x03
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hgroup.long 0x50C++0x03
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hgroup.long 0x510++0x03
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hgroup.long 0x514++0x03
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hgroup.long 0x518++0x03
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hgroup.long 0x51C++0x03
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
hgroup.long 0x520++0x03
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hgroup.long 0x524++0x03
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hgroup.long 0x528++0x03
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hgroup.long 0x52C++0x03
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hgroup.long 0x530++0x03
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hgroup.long 0x534++0x03
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hgroup.long 0x538++0x03
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hgroup.long 0x53C++0x03
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
hgroup.long 0x540++0x03
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hgroup.long 0x544++0x03
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hgroup.long 0x548++0x03
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hgroup.long 0x54C++0x03
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hgroup.long 0x550++0x03
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hgroup.long 0x554++0x03
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hgroup.long 0x558++0x03
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hgroup.long 0x55C++0x03
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
hgroup.long 0x560++0x03
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hgroup.long 0x564++0x03
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hgroup.long 0x568++0x03
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hgroup.long 0x56C++0x03
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hgroup.long 0x570++0x03
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hgroup.long 0x574++0x03
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hgroup.long 0x578++0x03
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hgroup.long 0x57C++0x03
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
hgroup.long 0x580++0x03
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hgroup.long 0x584++0x03
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hgroup.long 0x588++0x03
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hgroup.long 0x58C++0x03
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hgroup.long 0x590++0x03
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hgroup.long 0x594++0x03
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hgroup.long 0x598++0x03
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hgroup.long 0x59C++0x03
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
hgroup.long 0x5A0++0x03
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hgroup.long 0x5A4++0x03
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hgroup.long 0x5A8++0x03
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hgroup.long 0x5AC++0x03
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hgroup.long 0x5B0++0x03
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hgroup.long 0x5B4++0x03
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hgroup.long 0x5B8++0x03
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hgroup.long 0x5BC++0x03
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
hgroup.long 0x5C0++0x03
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hgroup.long 0x5C4++0x03
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hgroup.long 0x5C8++0x03
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hgroup.long 0x5CC++0x03
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hgroup.long 0x5D0++0x03
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hgroup.long 0x5D4++0x03
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hgroup.long 0x5D8++0x03
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hgroup.long 0x5DC++0x03
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
hgroup.long 0x5E0++0x03
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hgroup.long 0x5E4++0x03
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hgroup.long 0x5E8++0x03
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hgroup.long 0x5EC++0x03
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hgroup.long 0x5F0++0x03
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hgroup.long 0x5F4++0x03
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hgroup.long 0x5F8++0x03
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hgroup.long 0x5FC++0x03
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
hgroup.long 0x600++0x03
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hgroup.long 0x604++0x03
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hgroup.long 0x608++0x03
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hgroup.long 0x60C++0x03
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hgroup.long 0x610++0x03
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hgroup.long 0x614++0x03
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hgroup.long 0x618++0x03
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hgroup.long 0x61C++0x03
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
hgroup.long 0x620++0x03
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hgroup.long 0x624++0x03
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hgroup.long 0x628++0x03
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hgroup.long 0x62C++0x03
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hgroup.long 0x630++0x03
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hgroup.long 0x634++0x03
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hgroup.long 0x638++0x03
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hgroup.long 0x63C++0x03
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
hgroup.long 0x640++0x03
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hgroup.long 0x644++0x03
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hgroup.long 0x648++0x03
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hgroup.long 0x64C++0x03
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hgroup.long 0x650++0x03
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hgroup.long 0x654++0x03
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hgroup.long 0x658++0x03
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hgroup.long 0x65C++0x03
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
hgroup.long 0x660++0x03
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hgroup.long 0x664++0x03
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hgroup.long 0x668++0x03
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hgroup.long 0x66C++0x03
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hgroup.long 0x670++0x03
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hgroup.long 0x674++0x03
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hgroup.long 0x678++0x03
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hgroup.long 0x67C++0x03
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
hgroup.long 0x680++0x03
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hgroup.long 0x684++0x03
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hgroup.long 0x688++0x03
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hgroup.long 0x68C++0x03
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hgroup.long 0x690++0x03
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hgroup.long 0x694++0x03
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hgroup.long 0x698++0x03
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hgroup.long 0x69C++0x03
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
hgroup.long 0x6A0++0x03
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hgroup.long 0x6A4++0x03
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hgroup.long 0x6A8++0x03
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hgroup.long 0x6AC++0x03
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hgroup.long 0x6B0++0x03
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hgroup.long 0x6B4++0x03
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hgroup.long 0x6B8++0x03
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hgroup.long 0x6BC++0x03
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
hgroup.long 0x6C0++0x03
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hgroup.long 0x6C4++0x03
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hgroup.long 0x6C8++0x03
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hgroup.long 0x6CC++0x03
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hgroup.long 0x6D0++0x03
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hgroup.long 0x6D4++0x03
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hgroup.long 0x6D8++0x03
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hgroup.long 0x6DC++0x03
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
hgroup.long 0x6E0++0x03
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hgroup.long 0x6E4++0x03
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hgroup.long 0x6E8++0x03
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hgroup.long 0x6EC++0x03
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hgroup.long 0x6F0++0x03
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hgroup.long 0x6F4++0x03
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hgroup.long 0x6F8++0x03
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hgroup.long 0x6FC++0x03
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
hgroup.long 0x700++0x03
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hgroup.long 0x704++0x03
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hgroup.long 0x708++0x03
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hgroup.long 0x70C++0x03
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hgroup.long 0x710++0x03
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hgroup.long 0x714++0x03
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hgroup.long 0x718++0x03
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hgroup.long 0x71C++0x03
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
hgroup.long 0x720++0x03
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hgroup.long 0x724++0x03
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hgroup.long 0x728++0x03
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hgroup.long 0x72C++0x03
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hgroup.long 0x730++0x03
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hgroup.long 0x734++0x03
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hgroup.long 0x738++0x03
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hgroup.long 0x73C++0x03
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
hgroup.long 0x740++0x03
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hgroup.long 0x744++0x03
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hgroup.long 0x748++0x03
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hgroup.long 0x74C++0x03
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hgroup.long 0x750++0x03
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hgroup.long 0x754++0x03
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hgroup.long 0x758++0x03
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hgroup.long 0x75C++0x03
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
hgroup.long 0x760++0x03
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hgroup.long 0x764++0x03
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hgroup.long 0x768++0x03
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hgroup.long 0x76C++0x03
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hgroup.long 0x770++0x03
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hgroup.long 0x774++0x03
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hgroup.long 0x778++0x03
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hgroup.long 0x77C++0x03
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
hgroup.long 0x780++0x03
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hgroup.long 0x784++0x03
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hgroup.long 0x788++0x03
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hgroup.long 0x78C++0x03
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hgroup.long 0x790++0x03
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hgroup.long 0x794++0x03
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hgroup.long 0x798++0x03
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hgroup.long 0x79C++0x03
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
hgroup.long 0x7A0++0x03
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hgroup.long 0x7A4++0x03
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hgroup.long 0x7A8++0x03
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hgroup.long 0x7AC++0x03
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hgroup.long 0x7B0++0x03
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hgroup.long 0x7B4++0x03
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hgroup.long 0x7B8++0x03
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hgroup.long 0x7BC++0x03
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
hgroup.long 0x7C0++0x03
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hgroup.long 0x7C4++0x03
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hgroup.long 0x7C8++0x03
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hgroup.long 0x7CC++0x03
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hgroup.long 0x7D0++0x03
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hgroup.long 0x7D4++0x03
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hgroup.long 0x7D8++0x03
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hgroup.long 0x7DC++0x03
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
tree.end
width 19.
tree "Interrupt Targets Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1)
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
else
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SGI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SGI)" "Level,Edge"
group.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (PPI)" "Level,Edge"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC08++0x03
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
hgroup.long 0xC0C++0x03
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC10++0x03
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
hgroup.long 0xC14++0x03
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC18++0x03
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
hgroup.long 0xC1C++0x03
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC20++0x03
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
hgroup.long 0xC24++0x03
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC28++0x03
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
hgroup.long 0xC2C++0x03
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC30++0x03
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
hgroup.long 0xC34++0x03
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC38++0x03
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
hgroup.long 0xC3C++0x03
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC40++0x03
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
hgroup.long 0xC44++0x03
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC48++0x03
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
hgroup.long 0xC4C++0x03
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC50++0x03
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
hgroup.long 0xC54++0x03
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC58++0x03
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
hgroup.long 0xC5C++0x03
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC60++0x03
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
hgroup.long 0xC64++0x03
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC68++0x03
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
hgroup.long 0xC6C++0x03
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC70++0x03
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
hgroup.long 0xC74++0x03
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC78++0x03
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
hgroup.long 0xC7C++0x03
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC80++0x03
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
hgroup.long 0xC84++0x03
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC88++0x03
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
hgroup.long 0xC8C++0x03
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC90++0x03
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
hgroup.long 0xC94++0x03
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC98++0x03
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
hgroup.long 0xC9C++0x03
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA0++0x03
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
hgroup.long 0xCA4++0x03
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA8++0x03
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
hgroup.long 0xCAC++0x03
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB0++0x03
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
hgroup.long 0xCB4++0x03
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB8++0x03
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
hgroup.long 0xCBC++0x03
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC0++0x03
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
hgroup.long 0xCC4++0x03
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC8++0x03
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
hgroup.long 0xCCC++0x03
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD0++0x03
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
hgroup.long 0xCD4++0x03
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD8++0x03
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
hgroup.long 0xCDC++0x03
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE0++0x03
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
hgroup.long 0xCE4++0x03
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE8++0x03
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
hgroup.long 0xCEC++0x03
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCF0++0x03
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
hgroup.long 0xCF4++0x03
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
tree.end
width 17.
tree "Interrupt Group Modifier Registers"
hgroup.long 0x0D00++0x03
hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01))
group.long 0x0D04++0x03
line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
bitfld.long 0x00 31. " GMB63  ,Group Modifier Bit 63" "0,1"
bitfld.long 0x00 30. "  GMB62  ,Group Modifier Bit 62" "0,1"
bitfld.long 0x00 29. "  GMB61  ,Group Modifier Bit 61" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB60  ,Group Modifier Bit 60" "0,1"
bitfld.long 0x00 27. "  GMB59  ,Group Modifier Bit 59" "0,1"
bitfld.long 0x00 26. "  GMB58  ,Group Modifier Bit 58" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB57  ,Group Modifier Bit 57" "0,1"
bitfld.long 0x00 24. "  GMB56  ,Group Modifier Bit 56" "0,1"
bitfld.long 0x00 23. "  GMB55  ,Group Modifier Bit 55" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB54  ,Group Modifier Bit 54" "0,1"
bitfld.long 0x00 21. "  GMB53  ,Group Modifier Bit 53" "0,1"
bitfld.long 0x00 20. "  GMB52  ,Group Modifier Bit 52" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB51  ,Group Modifier Bit 51" "0,1"
bitfld.long 0x00 18. "  GMB50  ,Group Modifier Bit 50" "0,1"
bitfld.long 0x00 17. "  GMB49  ,Group Modifier Bit 49" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB48  ,Group Modifier Bit 48" "0,1"
bitfld.long 0x00 15. "  GMB47  ,Group Modifier Bit 47" "0,1"
bitfld.long 0x00 14. "  GMB46  ,Group Modifier Bit 46" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB45  ,Group Modifier Bit 45" "0,1"
bitfld.long 0x00 12. "  GMB44  ,Group Modifier Bit 44" "0,1"
bitfld.long 0x00 11. "  GMB43  ,Group Modifier Bit 43" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB42  ,Group Modifier Bit 42" "0,1"
bitfld.long 0x00 9. "  GMB41  ,Group Modifier Bit 41" "0,1"
bitfld.long 0x00 8. "  GMB40  ,Group Modifier Bit 40" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB39  ,Group Modifier Bit 39" "0,1"
bitfld.long 0x00 6. "  GMB38  ,Group Modifier Bit 38" "0,1"
bitfld.long 0x00 5. "  GMB37  ,Group Modifier Bit 37" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB36  ,Group Modifier Bit 36" "0,1"
bitfld.long 0x00 3. "  GMB35  ,Group Modifier Bit 35" "0,1"
bitfld.long 0x00 2. "  GMB34  ,Group Modifier Bit 34" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB33  ,Group Modifier Bit 33" "0,1"
bitfld.long 0x00 0. "  GMB32  ,Group Modifier Bit 32" "0,1"
else
hgroup.long 0x0D04++0x03
hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02))
group.long 0x0D08++0x03
line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
bitfld.long 0x00 31. " GMB95  ,Group Modifier Bit 95" "0,1"
bitfld.long 0x00 30. "  GMB94  ,Group Modifier Bit 94" "0,1"
bitfld.long 0x00 29. "  GMB93  ,Group Modifier Bit 93" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB92  ,Group Modifier Bit 92" "0,1"
bitfld.long 0x00 27. "  GMB91  ,Group Modifier Bit 91" "0,1"
bitfld.long 0x00 26. "  GMB90  ,Group Modifier Bit 90" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB89  ,Group Modifier Bit 89" "0,1"
bitfld.long 0x00 24. "  GMB88  ,Group Modifier Bit 88" "0,1"
bitfld.long 0x00 23. "  GMB87  ,Group Modifier Bit 87" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB86  ,Group Modifier Bit 86" "0,1"
bitfld.long 0x00 21. "  GMB85  ,Group Modifier Bit 85" "0,1"
bitfld.long 0x00 20. "  GMB84  ,Group Modifier Bit 84" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB83  ,Group Modifier Bit 83" "0,1"
bitfld.long 0x00 18. "  GMB82  ,Group Modifier Bit 82" "0,1"
bitfld.long 0x00 17. "  GMB81  ,Group Modifier Bit 81" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB80  ,Group Modifier Bit 80" "0,1"
bitfld.long 0x00 15. "  GMB79  ,Group Modifier Bit 79" "0,1"
bitfld.long 0x00 14. "  GMB78  ,Group Modifier Bit 78" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB77  ,Group Modifier Bit 77" "0,1"
bitfld.long 0x00 12. "  GMB76  ,Group Modifier Bit 76" "0,1"
bitfld.long 0x00 11. "  GMB75  ,Group Modifier Bit 75" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB74  ,Group Modifier Bit 74" "0,1"
bitfld.long 0x00 9. "  GMB73  ,Group Modifier Bit 73" "0,1"
bitfld.long 0x00 8. "  GMB72  ,Group Modifier Bit 72" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB71  ,Group Modifier Bit 71" "0,1"
bitfld.long 0x00 6. "  GMB70  ,Group Modifier Bit 70" "0,1"
bitfld.long 0x00 5. "  GMB69  ,Group Modifier Bit 69" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB68  ,Group Modifier Bit 68" "0,1"
bitfld.long 0x00 3. "  GMB67  ,Group Modifier Bit 67" "0,1"
bitfld.long 0x00 2. "  GMB66  ,Group Modifier Bit 66" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB65  ,Group Modifier Bit 65" "0,1"
bitfld.long 0x00 0. "  GMB64  ,Group Modifier Bit 64" "0,1"
else
hgroup.long 0x0D08++0x03
hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03))
group.long 0x0D0C++0x03
line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1"
bitfld.long 0x00 30. "  GMB126 ,Group Modifier Bit 126" "0,1"
bitfld.long 0x00 29. "  GMB125 ,Group Modifier Bit 125" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1"
bitfld.long 0x00 27. "  GMB123 ,Group Modifier Bit 123" "0,1"
bitfld.long 0x00 26. "  GMB122 ,Group Modifier Bit 122" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1"
bitfld.long 0x00 24. "  GMB120 ,Group Modifier Bit 120" "0,1"
bitfld.long 0x00 23. "  GMB119 ,Group Modifier Bit 119" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1"
bitfld.long 0x00 21. "  GMB117 ,Group Modifier Bit 117" "0,1"
bitfld.long 0x00 20. "  GMB116 ,Group Modifier Bit 116" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1"
bitfld.long 0x00 18. "  GMB114 ,Group Modifier Bit 114" "0,1"
bitfld.long 0x00 17. "  GMB113 ,Group Modifier Bit 113" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1"
bitfld.long 0x00 15. "  GMB111 ,Group Modifier Bit 111" "0,1"
bitfld.long 0x00 14. "  GMB110 ,Group Modifier Bit 110" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1"
bitfld.long 0x00 12. "  GMB108 ,Group Modifier Bit 108" "0,1"
bitfld.long 0x00 11. "  GMB107 ,Group Modifier Bit 107" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1"
bitfld.long 0x00 9. "  GMB105 ,Group Modifier Bit 105" "0,1"
bitfld.long 0x00 8. "  GMB104 ,Group Modifier Bit 104" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1"
bitfld.long 0x00 6. "  GMB102 ,Group Modifier Bit 102" "0,1"
bitfld.long 0x00 5. "  GMB101 ,Group Modifier Bit 101" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1"
bitfld.long 0x00 3. "  GMB99  ,Group Modifier Bit 99" "0,1"
bitfld.long 0x00 2. "  GMB98  ,Group Modifier Bit 98" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB97  ,Group Modifier Bit 97" "0,1"
bitfld.long 0x00 0. "  GMB96  ,Group Modifier Bit 96" "0,1"
else
hgroup.long 0x0D0C++0x03
hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04))
group.long 0x0D10++0x03
line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1"
bitfld.long 0x00 30. "  GMB158 ,Group Modifier Bit 158" "0,1"
bitfld.long 0x00 29. "  GMB157 ,Group Modifier Bit 157" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1"
bitfld.long 0x00 27. "  GMB155 ,Group Modifier Bit 155" "0,1"
bitfld.long 0x00 26. "  GMB154 ,Group Modifier Bit 154" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1"
bitfld.long 0x00 24. "  GMB152 ,Group Modifier Bit 152" "0,1"
bitfld.long 0x00 23. "  GMB151 ,Group Modifier Bit 151" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1"
bitfld.long 0x00 21. "  GMB149 ,Group Modifier Bit 149" "0,1"
bitfld.long 0x00 20. "  GMB148 ,Group Modifier Bit 148" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1"
bitfld.long 0x00 18. "  GMB146 ,Group Modifier Bit 146" "0,1"
bitfld.long 0x00 17. "  GMB145 ,Group Modifier Bit 145" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1"
bitfld.long 0x00 15. "  GMB143 ,Group Modifier Bit 143" "0,1"
bitfld.long 0x00 14. "  GMB142 ,Group Modifier Bit 142" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1"
bitfld.long 0x00 12. "  GMB140 ,Group Modifier Bit 140" "0,1"
bitfld.long 0x00 11. "  GMB139 ,Group Modifier Bit 139" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1"
bitfld.long 0x00 9. "  GMB137 ,Group Modifier Bit 137" "0,1"
bitfld.long 0x00 8. "  GMB136 ,Group Modifier Bit 136" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1"
bitfld.long 0x00 6. "  GMB134 ,Group Modifier Bit 134" "0,1"
bitfld.long 0x00 5. "  GMB133 ,Group Modifier Bit 133" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1"
bitfld.long 0x00 3. "  GMB131 ,Group Modifier Bit 131" "0,1"
bitfld.long 0x00 2. "  GMB130 ,Group Modifier Bit 130" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1"
bitfld.long 0x00 0. "  GMB128 ,Group Modifier Bit 128" "0,1"
else
hgroup.long 0x0D10++0x03
hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05))
group.long 0x0D14++0x03
line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1"
bitfld.long 0x00 30. "  GMB190 ,Group Modifier Bit 190" "0,1"
bitfld.long 0x00 29. "  GMB189 ,Group Modifier Bit 189" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1"
bitfld.long 0x00 27. "  GMB187 ,Group Modifier Bit 187" "0,1"
bitfld.long 0x00 26. "  GMB186 ,Group Modifier Bit 186" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1"
bitfld.long 0x00 24. "  GMB184 ,Group Modifier Bit 184" "0,1"
bitfld.long 0x00 23. "  GMB183 ,Group Modifier Bit 183" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1"
bitfld.long 0x00 21. "  GMB181 ,Group Modifier Bit 181" "0,1"
bitfld.long 0x00 20. "  GMB180 ,Group Modifier Bit 180" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1"
bitfld.long 0x00 18. "  GMB178 ,Group Modifier Bit 178" "0,1"
bitfld.long 0x00 17. "  GMB177 ,Group Modifier Bit 177" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1"
bitfld.long 0x00 15. "  GMB175 ,Group Modifier Bit 175" "0,1"
bitfld.long 0x00 14. "  GMB174 ,Group Modifier Bit 174" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1"
bitfld.long 0x00 12. "  GMB172 ,Group Modifier Bit 172" "0,1"
bitfld.long 0x00 11. "  GMB171 ,Group Modifier Bit 171" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1"
bitfld.long 0x00 9. "  GMB169 ,Group Modifier Bit 169" "0,1"
bitfld.long 0x00 8. "  GMB168 ,Group Modifier Bit 168" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1"
bitfld.long 0x00 6. "  GMB166 ,Group Modifier Bit 166" "0,1"
bitfld.long 0x00 5. "  GMB165 ,Group Modifier Bit 165" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1"
bitfld.long 0x00 3. "  GMB163 ,Group Modifier Bit 163" "0,1"
bitfld.long 0x00 2. "  GMB162 ,Group Modifier Bit 162" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1"
bitfld.long 0x00 0. "  GMB160 ,Group Modifier Bit 160" "0,1"
else
hgroup.long 0x0D14++0x03
hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06))
group.long 0x0D18++0x03
line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1"
bitfld.long 0x00 30. "  GMB222 ,Group Modifier Bit 222" "0,1"
bitfld.long 0x00 29. "  GMB221 ,Group Modifier Bit 221" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1"
bitfld.long 0x00 27. "  GMB219 ,Group Modifier Bit 219" "0,1"
bitfld.long 0x00 26. "  GMB218 ,Group Modifier Bit 218" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1"
bitfld.long 0x00 24. "  GMB216 ,Group Modifier Bit 216" "0,1"
bitfld.long 0x00 23. "  GMB215 ,Group Modifier Bit 215" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1"
bitfld.long 0x00 21. "  GMB213 ,Group Modifier Bit 213" "0,1"
bitfld.long 0x00 20. "  GMB212 ,Group Modifier Bit 212" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1"
bitfld.long 0x00 18. "  GMB210 ,Group Modifier Bit 210" "0,1"
bitfld.long 0x00 17. "  GMB209 ,Group Modifier Bit 209" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1"
bitfld.long 0x00 15. "  GMB207 ,Group Modifier Bit 207" "0,1"
bitfld.long 0x00 14. "  GMB206 ,Group Modifier Bit 206" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1"
bitfld.long 0x00 12. "  GMB204 ,Group Modifier Bit 204" "0,1"
bitfld.long 0x00 11. "  GMB203 ,Group Modifier Bit 203" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1"
bitfld.long 0x00 9. "  GMB201 ,Group Modifier Bit 201" "0,1"
bitfld.long 0x00 8. "  GMB200 ,Group Modifier Bit 200" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1"
bitfld.long 0x00 6. "  GMB198 ,Group Modifier Bit 198" "0,1"
bitfld.long 0x00 5. "  GMB197 ,Group Modifier Bit 197" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1"
bitfld.long 0x00 3. "  GMB195 ,Group Modifier Bit 195" "0,1"
bitfld.long 0x00 2. "  GMB194 ,Group Modifier Bit 194" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1"
bitfld.long 0x00 0. "  GMB192 ,Group Modifier Bit 192" "0,1"
else
hgroup.long 0x0D18++0x03
hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07))
group.long 0x0D1C++0x03
line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1"
bitfld.long 0x00 30. "  GMB254 ,Group Modifier Bit 254" "0,1"
bitfld.long 0x00 29. "  GMB253 ,Group Modifier Bit 253" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1"
bitfld.long 0x00 27. "  GMB251 ,Group Modifier Bit 251" "0,1"
bitfld.long 0x00 26. "  GMB250 ,Group Modifier Bit 250" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1"
bitfld.long 0x00 24. "  GMB248 ,Group Modifier Bit 248" "0,1"
bitfld.long 0x00 23. "  GMB247 ,Group Modifier Bit 247" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1"
bitfld.long 0x00 21. "  GMB245 ,Group Modifier Bit 245" "0,1"
bitfld.long 0x00 20. "  GMB244 ,Group Modifier Bit 244" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1"
bitfld.long 0x00 18. "  GMB242 ,Group Modifier Bit 242" "0,1"
bitfld.long 0x00 17. "  GMB241 ,Group Modifier Bit 241" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1"
bitfld.long 0x00 15. "  GMB239 ,Group Modifier Bit 239" "0,1"
bitfld.long 0x00 14. "  GMB238 ,Group Modifier Bit 238" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1"
bitfld.long 0x00 12. "  GMB236 ,Group Modifier Bit 236" "0,1"
bitfld.long 0x00 11. "  GMB235 ,Group Modifier Bit 235" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1"
bitfld.long 0x00 9. "  GMB233 ,Group Modifier Bit 233" "0,1"
bitfld.long 0x00 8. "  GMB232 ,Group Modifier Bit 232" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1"
bitfld.long 0x00 6. "  GMB230 ,Group Modifier Bit 230" "0,1"
bitfld.long 0x00 5. "  GMB229 ,Group Modifier Bit 229" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1"
bitfld.long 0x00 3. "  GMB227 ,Group Modifier Bit 227" "0,1"
bitfld.long 0x00 2. "  GMB226 ,Group Modifier Bit 226" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1"
bitfld.long 0x00 0. "  GMB224 ,Group Modifier Bit 224" "0,1"
else
hgroup.long 0x0D1C++0x03
hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08))
group.long 0x0D20++0x03
line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1"
bitfld.long 0x00 30. "  GMB286 ,Group Modifier Bit 286" "0,1"
bitfld.long 0x00 29. "  GMB285 ,Group Modifier Bit 285" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1"
bitfld.long 0x00 27. "  GMB283 ,Group Modifier Bit 283" "0,1"
bitfld.long 0x00 26. "  GMB282 ,Group Modifier Bit 282" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1"
bitfld.long 0x00 24. "  GMB280 ,Group Modifier Bit 280" "0,1"
bitfld.long 0x00 23. "  GMB279 ,Group Modifier Bit 279" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1"
bitfld.long 0x00 21. "  GMB277 ,Group Modifier Bit 277" "0,1"
bitfld.long 0x00 20. "  GMB276 ,Group Modifier Bit 276" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1"
bitfld.long 0x00 18. "  GMB274 ,Group Modifier Bit 274" "0,1"
bitfld.long 0x00 17. "  GMB273 ,Group Modifier Bit 273" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1"
bitfld.long 0x00 15. "  GMB271 ,Group Modifier Bit 271" "0,1"
bitfld.long 0x00 14. "  GMB270 ,Group Modifier Bit 270" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1"
bitfld.long 0x00 12. "  GMB268 ,Group Modifier Bit 268" "0,1"
bitfld.long 0x00 11. "  GMB267 ,Group Modifier Bit 267" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1"
bitfld.long 0x00 9. "  GMB265 ,Group Modifier Bit 265" "0,1"
bitfld.long 0x00 8. "  GMB264 ,Group Modifier Bit 264" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1"
bitfld.long 0x00 6. "  GMB262 ,Group Modifier Bit 262" "0,1"
bitfld.long 0x00 5. "  GMB261 ,Group Modifier Bit 261" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1"
bitfld.long 0x00 3. "  GMB259 ,Group Modifier Bit 259" "0,1"
bitfld.long 0x00 2. "  GMB258 ,Group Modifier Bit 258" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1"
bitfld.long 0x00 0. "  GMB256 ,Group Modifier Bit 256" "0,1"
else
hgroup.long 0x0D20++0x03
hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09))
group.long 0x0D24++0x03
line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1"
bitfld.long 0x00 30. "  GMB318 ,Group Modifier Bit 318" "0,1"
bitfld.long 0x00 29. "  GMB317 ,Group Modifier Bit 317" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1"
bitfld.long 0x00 27. "  GMB315 ,Group Modifier Bit 315" "0,1"
bitfld.long 0x00 26. "  GMB314 ,Group Modifier Bit 314" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1"
bitfld.long 0x00 24. "  GMB312 ,Group Modifier Bit 312" "0,1"
bitfld.long 0x00 23. "  GMB311 ,Group Modifier Bit 311" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1"
bitfld.long 0x00 21. "  GMB309 ,Group Modifier Bit 309" "0,1"
bitfld.long 0x00 20. "  GMB308 ,Group Modifier Bit 308" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1"
bitfld.long 0x00 18. "  GMB306 ,Group Modifier Bit 306" "0,1"
bitfld.long 0x00 17. "  GMB305 ,Group Modifier Bit 305" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1"
bitfld.long 0x00 15. "  GMB303 ,Group Modifier Bit 303" "0,1"
bitfld.long 0x00 14. "  GMB302 ,Group Modifier Bit 302" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1"
bitfld.long 0x00 12. "  GMB300 ,Group Modifier Bit 300" "0,1"
bitfld.long 0x00 11. "  GMB299 ,Group Modifier Bit 299" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1"
bitfld.long 0x00 9. "  GMB297 ,Group Modifier Bit 297" "0,1"
bitfld.long 0x00 8. "  GMB296 ,Group Modifier Bit 296" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1"
bitfld.long 0x00 6. "  GMB294 ,Group Modifier Bit 294" "0,1"
bitfld.long 0x00 5. "  GMB293 ,Group Modifier Bit 293" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1"
bitfld.long 0x00 3. "  GMB291 ,Group Modifier Bit 291" "0,1"
bitfld.long 0x00 2. "  GMB290 ,Group Modifier Bit 290" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1"
bitfld.long 0x00 0. "  GMB288 ,Group Modifier Bit 288" "0,1"
else
hgroup.long 0x0D24++0x03
hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A))
group.long 0x0D28++0x03
line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1"
bitfld.long 0x00 30. "  GMB350 ,Group Modifier Bit 350" "0,1"
bitfld.long 0x00 29. "  GMB349 ,Group Modifier Bit 349" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1"
bitfld.long 0x00 27. "  GMB347 ,Group Modifier Bit 347" "0,1"
bitfld.long 0x00 26. "  GMB346 ,Group Modifier Bit 346" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1"
bitfld.long 0x00 24. "  GMB344 ,Group Modifier Bit 344" "0,1"
bitfld.long 0x00 23. "  GMB343 ,Group Modifier Bit 343" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1"
bitfld.long 0x00 21. "  GMB341 ,Group Modifier Bit 341" "0,1"
bitfld.long 0x00 20. "  GMB340 ,Group Modifier Bit 340" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1"
bitfld.long 0x00 18. "  GMB338 ,Group Modifier Bit 338" "0,1"
bitfld.long 0x00 17. "  GMB337 ,Group Modifier Bit 337" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1"
bitfld.long 0x00 15. "  GMB335 ,Group Modifier Bit 335" "0,1"
bitfld.long 0x00 14. "  GMB334 ,Group Modifier Bit 334" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1"
bitfld.long 0x00 12. "  GMB332 ,Group Modifier Bit 332" "0,1"
bitfld.long 0x00 11. "  GMB331 ,Group Modifier Bit 331" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1"
bitfld.long 0x00 9. "  GMB329 ,Group Modifier Bit 329" "0,1"
bitfld.long 0x00 8. "  GMB328 ,Group Modifier Bit 328" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1"
bitfld.long 0x00 6. "  GMB326 ,Group Modifier Bit 326" "0,1"
bitfld.long 0x00 5. "  GMB325 ,Group Modifier Bit 325" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1"
bitfld.long 0x00 3. "  GMB323 ,Group Modifier Bit 323" "0,1"
bitfld.long 0x00 2. "  GMB322 ,Group Modifier Bit 322" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1"
bitfld.long 0x00 0. "  GMB320 ,Group Modifier Bit 320" "0,1"
else
hgroup.long 0x0D28++0x03
hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B))
group.long 0x0D2C++0x03
line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1"
bitfld.long 0x00 30. "  GMB382 ,Group Modifier Bit 382" "0,1"
bitfld.long 0x00 29. "  GMB381 ,Group Modifier Bit 381" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1"
bitfld.long 0x00 27. "  GMB379 ,Group Modifier Bit 379" "0,1"
bitfld.long 0x00 26. "  GMB378 ,Group Modifier Bit 378" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1"
bitfld.long 0x00 24. "  GMB376 ,Group Modifier Bit 376" "0,1"
bitfld.long 0x00 23. "  GMB375 ,Group Modifier Bit 375" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1"
bitfld.long 0x00 21. "  GMB373 ,Group Modifier Bit 373" "0,1"
bitfld.long 0x00 20. "  GMB372 ,Group Modifier Bit 372" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1"
bitfld.long 0x00 18. "  GMB370 ,Group Modifier Bit 370" "0,1"
bitfld.long 0x00 17. "  GMB369 ,Group Modifier Bit 369" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1"
bitfld.long 0x00 15. "  GMB367 ,Group Modifier Bit 367" "0,1"
bitfld.long 0x00 14. "  GMB366 ,Group Modifier Bit 366" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1"
bitfld.long 0x00 12. "  GMB364 ,Group Modifier Bit 364" "0,1"
bitfld.long 0x00 11. "  GMB363 ,Group Modifier Bit 363" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1"
bitfld.long 0x00 9. "  GMB361 ,Group Modifier Bit 361" "0,1"
bitfld.long 0x00 8. "  GMB360 ,Group Modifier Bit 360" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1"
bitfld.long 0x00 6. "  GMB358 ,Group Modifier Bit 358" "0,1"
bitfld.long 0x00 5. "  GMB357 ,Group Modifier Bit 357" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1"
bitfld.long 0x00 3. "  GMB355 ,Group Modifier Bit 355" "0,1"
bitfld.long 0x00 2. "  GMB354 ,Group Modifier Bit 354" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1"
bitfld.long 0x00 0. "  GMB352 ,Group Modifier Bit 352" "0,1"
else
hgroup.long 0x0D2C++0x03
hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C))
group.long 0x0D30++0x03
line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1"
bitfld.long 0x00 30. "  GMB414 ,Group Modifier Bit 414" "0,1"
bitfld.long 0x00 29. "  GMB413 ,Group Modifier Bit 413" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1"
bitfld.long 0x00 27. "  GMB411 ,Group Modifier Bit 411" "0,1"
bitfld.long 0x00 26. "  GMB410 ,Group Modifier Bit 410" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1"
bitfld.long 0x00 24. "  GMB408 ,Group Modifier Bit 408" "0,1"
bitfld.long 0x00 23. "  GMB407 ,Group Modifier Bit 407" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1"
bitfld.long 0x00 21. "  GMB405 ,Group Modifier Bit 405" "0,1"
bitfld.long 0x00 20. "  GMB404 ,Group Modifier Bit 404" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1"
bitfld.long 0x00 18. "  GMB402 ,Group Modifier Bit 402" "0,1"
bitfld.long 0x00 17. "  GMB401 ,Group Modifier Bit 401" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1"
bitfld.long 0x00 15. "  GMB399 ,Group Modifier Bit 399" "0,1"
bitfld.long 0x00 14. "  GMB398 ,Group Modifier Bit 398" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1"
bitfld.long 0x00 12. "  GMB396 ,Group Modifier Bit 396" "0,1"
bitfld.long 0x00 11. "  GMB395 ,Group Modifier Bit 395" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1"
bitfld.long 0x00 9. "  GMB393 ,Group Modifier Bit 393" "0,1"
bitfld.long 0x00 8. "  GMB392 ,Group Modifier Bit 392" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1"
bitfld.long 0x00 6. "  GMB390 ,Group Modifier Bit 390" "0,1"
bitfld.long 0x00 5. "  GMB389 ,Group Modifier Bit 389" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1"
bitfld.long 0x00 3. "  GMB387 ,Group Modifier Bit 387" "0,1"
bitfld.long 0x00 2. "  GMB386 ,Group Modifier Bit 386" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1"
bitfld.long 0x00 0. "  GMB384 ,Group Modifier Bit 384" "0,1"
else
hgroup.long 0x0D30++0x03
hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D))
group.long 0x0D34++0x03
line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1"
bitfld.long 0x00 30. "  GMB446 ,Group Modifier Bit 446" "0,1"
bitfld.long 0x00 29. "  GMB445 ,Group Modifier Bit 445" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1"
bitfld.long 0x00 27. "  GMB443 ,Group Modifier Bit 443" "0,1"
bitfld.long 0x00 26. "  GMB442 ,Group Modifier Bit 442" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1"
bitfld.long 0x00 24. "  GMB440 ,Group Modifier Bit 440" "0,1"
bitfld.long 0x00 23. "  GMB439 ,Group Modifier Bit 439" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1"
bitfld.long 0x00 21. "  GMB437 ,Group Modifier Bit 437" "0,1"
bitfld.long 0x00 20. "  GMB436 ,Group Modifier Bit 436" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1"
bitfld.long 0x00 18. "  GMB434 ,Group Modifier Bit 434" "0,1"
bitfld.long 0x00 17. "  GMB433 ,Group Modifier Bit 433" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1"
bitfld.long 0x00 15. "  GMB431 ,Group Modifier Bit 431" "0,1"
bitfld.long 0x00 14. "  GMB430 ,Group Modifier Bit 430" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1"
bitfld.long 0x00 12. "  GMB428 ,Group Modifier Bit 428" "0,1"
bitfld.long 0x00 11. "  GMB427 ,Group Modifier Bit 427" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1"
bitfld.long 0x00 9. "  GMB425 ,Group Modifier Bit 425" "0,1"
bitfld.long 0x00 8. "  GMB424 ,Group Modifier Bit 424" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1"
bitfld.long 0x00 6. "  GMB422 ,Group Modifier Bit 422" "0,1"
bitfld.long 0x00 5. "  GMB421 ,Group Modifier Bit 421" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1"
bitfld.long 0x00 3. "  GMB419 ,Group Modifier Bit 419" "0,1"
bitfld.long 0x00 2. "  GMB418 ,Group Modifier Bit 418" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1"
bitfld.long 0x00 0. "  GMB416 ,Group Modifier Bit 416" "0,1"
else
hgroup.long 0x0D34++0x03
hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E))
group.long 0x0D38++0x03
line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1"
bitfld.long 0x00 30. "  GMB478 ,Group Modifier Bit 478" "0,1"
bitfld.long 0x00 29. "  GMB477 ,Group Modifier Bit 477" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1"
bitfld.long 0x00 27. "  GMB475 ,Group Modifier Bit 475" "0,1"
bitfld.long 0x00 26. "  GMB474 ,Group Modifier Bit 474" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1"
bitfld.long 0x00 24. "  GMB472 ,Group Modifier Bit 472" "0,1"
bitfld.long 0x00 23. "  GMB471 ,Group Modifier Bit 471" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1"
bitfld.long 0x00 21. "  GMB469 ,Group Modifier Bit 469" "0,1"
bitfld.long 0x00 20. "  GMB468 ,Group Modifier Bit 468" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1"
bitfld.long 0x00 18. "  GMB466 ,Group Modifier Bit 466" "0,1"
bitfld.long 0x00 17. "  GMB465 ,Group Modifier Bit 465" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1"
bitfld.long 0x00 15. "  GMB463 ,Group Modifier Bit 463" "0,1"
bitfld.long 0x00 14. "  GMB462 ,Group Modifier Bit 462" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1"
bitfld.long 0x00 12. "  GMB460 ,Group Modifier Bit 460" "0,1"
bitfld.long 0x00 11. "  GMB459 ,Group Modifier Bit 459" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1"
bitfld.long 0x00 9. "  GMB457 ,Group Modifier Bit 457" "0,1"
bitfld.long 0x00 8. "  GMB456 ,Group Modifier Bit 456" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1"
bitfld.long 0x00 6. "  GMB454 ,Group Modifier Bit 454" "0,1"
bitfld.long 0x00 5. "  GMB453 ,Group Modifier Bit 453" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1"
bitfld.long 0x00 3. "  GMB451 ,Group Modifier Bit 451" "0,1"
bitfld.long 0x00 2. "  GMB450 ,Group Modifier Bit 450" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1"
bitfld.long 0x00 0. "  GMB448 ,Group Modifier Bit 448" "0,1"
else
hgroup.long 0x0D38++0x03
hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F))
group.long 0x0D3C++0x03
line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1"
bitfld.long 0x00 30. "  GMB510 ,Group Modifier Bit 510" "0,1"
bitfld.long 0x00 29. "  GMB509 ,Group Modifier Bit 509" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1"
bitfld.long 0x00 27. "  GMB507 ,Group Modifier Bit 507" "0,1"
bitfld.long 0x00 26. "  GMB506 ,Group Modifier Bit 506" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1"
bitfld.long 0x00 24. "  GMB504 ,Group Modifier Bit 504" "0,1"
bitfld.long 0x00 23. "  GMB503 ,Group Modifier Bit 503" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1"
bitfld.long 0x00 21. "  GMB501 ,Group Modifier Bit 501" "0,1"
bitfld.long 0x00 20. "  GMB500 ,Group Modifier Bit 500" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1"
bitfld.long 0x00 18. "  GMB498 ,Group Modifier Bit 498" "0,1"
bitfld.long 0x00 17. "  GMB497 ,Group Modifier Bit 497" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1"
bitfld.long 0x00 15. "  GMB495 ,Group Modifier Bit 495" "0,1"
bitfld.long 0x00 14. "  GMB494 ,Group Modifier Bit 494" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1"
bitfld.long 0x00 12. "  GMB492 ,Group Modifier Bit 492" "0,1"
bitfld.long 0x00 11. "  GMB491 ,Group Modifier Bit 491" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1"
bitfld.long 0x00 9. "  GMB489 ,Group Modifier Bit 489" "0,1"
bitfld.long 0x00 8. "  GMB488 ,Group Modifier Bit 488" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1"
bitfld.long 0x00 6. "  GMB486 ,Group Modifier Bit 486" "0,1"
bitfld.long 0x00 5. "  GMB485 ,Group Modifier Bit 485" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1"
bitfld.long 0x00 3. "  GMB483 ,Group Modifier Bit 483" "0,1"
bitfld.long 0x00 2. "  GMB482 ,Group Modifier Bit 482" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1"
bitfld.long 0x00 0. "  GMB480 ,Group Modifier Bit 480" "0,1"
else
hgroup.long 0x0D3C++0x03
hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x0D40++0x03
line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1"
bitfld.long 0x00 30. "  GMB542 ,Group Modifier Bit 542" "0,1"
bitfld.long 0x00 29. "  GMB541 ,Group Modifier Bit 541" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1"
bitfld.long 0x00 27. "  GMB539 ,Group Modifier Bit 539" "0,1"
bitfld.long 0x00 26. "  GMB538 ,Group Modifier Bit 538" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1"
bitfld.long 0x00 24. "  GMB536 ,Group Modifier Bit 536" "0,1"
bitfld.long 0x00 23. "  GMB535 ,Group Modifier Bit 535" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1"
bitfld.long 0x00 21. "  GMB533 ,Group Modifier Bit 533" "0,1"
bitfld.long 0x00 20. "  GMB532 ,Group Modifier Bit 532" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1"
bitfld.long 0x00 18. "  GMB530 ,Group Modifier Bit 530" "0,1"
bitfld.long 0x00 17. "  GMB529 ,Group Modifier Bit 529" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1"
bitfld.long 0x00 15. "  GMB527 ,Group Modifier Bit 527" "0,1"
bitfld.long 0x00 14. "  GMB526 ,Group Modifier Bit 526" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1"
bitfld.long 0x00 12. "  GMB524 ,Group Modifier Bit 524" "0,1"
bitfld.long 0x00 11. "  GMB523 ,Group Modifier Bit 523" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1"
bitfld.long 0x00 9. "  GMB521 ,Group Modifier Bit 521" "0,1"
bitfld.long 0x00 8. "  GMB520 ,Group Modifier Bit 520" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1"
bitfld.long 0x00 6. "  GMB518 ,Group Modifier Bit 518" "0,1"
bitfld.long 0x00 5. "  GMB517 ,Group Modifier Bit 517" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1"
bitfld.long 0x00 3. "  GMB515 ,Group Modifier Bit 515" "0,1"
bitfld.long 0x00 2. "  GMB514 ,Group Modifier Bit 514" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1"
bitfld.long 0x00 0. "  GMB512 ,Group Modifier Bit 512" "0,1"
else
hgroup.long 0x0D40++0x03
hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x0D44++0x03
line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1"
bitfld.long 0x00 30. "  GMB574 ,Group Modifier Bit 574" "0,1"
bitfld.long 0x00 29. "  GMB573 ,Group Modifier Bit 573" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1"
bitfld.long 0x00 27. "  GMB571 ,Group Modifier Bit 571" "0,1"
bitfld.long 0x00 26. "  GMB570 ,Group Modifier Bit 570" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1"
bitfld.long 0x00 24. "  GMB568 ,Group Modifier Bit 568" "0,1"
bitfld.long 0x00 23. "  GMB567 ,Group Modifier Bit 567" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1"
bitfld.long 0x00 21. "  GMB565 ,Group Modifier Bit 565" "0,1"
bitfld.long 0x00 20. "  GMB564 ,Group Modifier Bit 564" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1"
bitfld.long 0x00 18. "  GMB562 ,Group Modifier Bit 562" "0,1"
bitfld.long 0x00 17. "  GMB561 ,Group Modifier Bit 561" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1"
bitfld.long 0x00 15. "  GMB559 ,Group Modifier Bit 559" "0,1"
bitfld.long 0x00 14. "  GMB558 ,Group Modifier Bit 558" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1"
bitfld.long 0x00 12. "  GMB556 ,Group Modifier Bit 556" "0,1"
bitfld.long 0x00 11. "  GMB555 ,Group Modifier Bit 555" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1"
bitfld.long 0x00 9. "  GMB553 ,Group Modifier Bit 553" "0,1"
bitfld.long 0x00 8. "  GMB552 ,Group Modifier Bit 552" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1"
bitfld.long 0x00 6. "  GMB550 ,Group Modifier Bit 550" "0,1"
bitfld.long 0x00 5. "  GMB549 ,Group Modifier Bit 549" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1"
bitfld.long 0x00 3. "  GMB547 ,Group Modifier Bit 547" "0,1"
bitfld.long 0x00 2. "  GMB546 ,Group Modifier Bit 546" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1"
bitfld.long 0x00 0. "  GMB544 ,Group Modifier Bit 544" "0,1"
else
hgroup.long 0x0D44++0x03
hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x0D48++0x03
line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1"
bitfld.long 0x00 30. "  GMB606 ,Group Modifier Bit 606" "0,1"
bitfld.long 0x00 29. "  GMB605 ,Group Modifier Bit 605" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1"
bitfld.long 0x00 27. "  GMB603 ,Group Modifier Bit 603" "0,1"
bitfld.long 0x00 26. "  GMB602 ,Group Modifier Bit 602" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1"
bitfld.long 0x00 24. "  GMB600 ,Group Modifier Bit 600" "0,1"
bitfld.long 0x00 23. "  GMB599 ,Group Modifier Bit 599" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1"
bitfld.long 0x00 21. "  GMB597 ,Group Modifier Bit 597" "0,1"
bitfld.long 0x00 20. "  GMB596 ,Group Modifier Bit 596" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1"
bitfld.long 0x00 18. "  GMB594 ,Group Modifier Bit 594" "0,1"
bitfld.long 0x00 17. "  GMB593 ,Group Modifier Bit 593" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1"
bitfld.long 0x00 15. "  GMB591 ,Group Modifier Bit 591" "0,1"
bitfld.long 0x00 14. "  GMB590 ,Group Modifier Bit 590" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1"
bitfld.long 0x00 12. "  GMB588 ,Group Modifier Bit 588" "0,1"
bitfld.long 0x00 11. "  GMB587 ,Group Modifier Bit 587" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1"
bitfld.long 0x00 9. "  GMB585 ,Group Modifier Bit 585" "0,1"
bitfld.long 0x00 8. "  GMB584 ,Group Modifier Bit 584" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1"
bitfld.long 0x00 6. "  GMB582 ,Group Modifier Bit 582" "0,1"
bitfld.long 0x00 5. "  GMB581 ,Group Modifier Bit 581" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1"
bitfld.long 0x00 3. "  GMB579 ,Group Modifier Bit 579" "0,1"
bitfld.long 0x00 2. "  GMB578 ,Group Modifier Bit 578" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1"
bitfld.long 0x00 0. "  GMB576 ,Group Modifier Bit 576" "0,1"
else
hgroup.long 0x0D48++0x03
hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x0D4C++0x03
line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1"
bitfld.long 0x00 30. "  GMB638 ,Group Modifier Bit 638" "0,1"
bitfld.long 0x00 29. "  GMB637 ,Group Modifier Bit 637" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1"
bitfld.long 0x00 27. "  GMB635 ,Group Modifier Bit 635" "0,1"
bitfld.long 0x00 26. "  GMB634 ,Group Modifier Bit 634" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1"
bitfld.long 0x00 24. "  GMB632 ,Group Modifier Bit 632" "0,1"
bitfld.long 0x00 23. "  GMB631 ,Group Modifier Bit 631" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1"
bitfld.long 0x00 21. "  GMB629 ,Group Modifier Bit 629" "0,1"
bitfld.long 0x00 20. "  GMB628 ,Group Modifier Bit 628" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1"
bitfld.long 0x00 18. "  GMB626 ,Group Modifier Bit 626" "0,1"
bitfld.long 0x00 17. "  GMB625 ,Group Modifier Bit 625" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1"
bitfld.long 0x00 15. "  GMB623 ,Group Modifier Bit 623" "0,1"
bitfld.long 0x00 14. "  GMB622 ,Group Modifier Bit 622" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1"
bitfld.long 0x00 12. "  GMB620 ,Group Modifier Bit 620" "0,1"
bitfld.long 0x00 11. "  GMB619 ,Group Modifier Bit 619" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1"
bitfld.long 0x00 9. "  GMB617 ,Group Modifier Bit 617" "0,1"
bitfld.long 0x00 8. "  GMB616 ,Group Modifier Bit 616" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1"
bitfld.long 0x00 6. "  GMB614 ,Group Modifier Bit 614" "0,1"
bitfld.long 0x00 5. "  GMB613 ,Group Modifier Bit 613" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1"
bitfld.long 0x00 3. "  GMB611 ,Group Modifier Bit 611" "0,1"
bitfld.long 0x00 2. "  GMB610 ,Group Modifier Bit 610" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1"
bitfld.long 0x00 0. "  GMB608 ,Group Modifier Bit 608" "0,1"
else
hgroup.long 0x0D4C++0x03
hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x0D50++0x03
line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1"
bitfld.long 0x00 30. "  GMB670 ,Group Modifier Bit 670" "0,1"
bitfld.long 0x00 29. "  GMB669 ,Group Modifier Bit 669" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1"
bitfld.long 0x00 27. "  GMB667 ,Group Modifier Bit 667" "0,1"
bitfld.long 0x00 26. "  GMB666 ,Group Modifier Bit 666" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1"
bitfld.long 0x00 24. "  GMB664 ,Group Modifier Bit 664" "0,1"
bitfld.long 0x00 23. "  GMB663 ,Group Modifier Bit 663" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1"
bitfld.long 0x00 21. "  GMB661 ,Group Modifier Bit 661" "0,1"
bitfld.long 0x00 20. "  GMB660 ,Group Modifier Bit 660" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1"
bitfld.long 0x00 18. "  GMB658 ,Group Modifier Bit 658" "0,1"
bitfld.long 0x00 17. "  GMB657 ,Group Modifier Bit 657" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1"
bitfld.long 0x00 15. "  GMB655 ,Group Modifier Bit 655" "0,1"
bitfld.long 0x00 14. "  GMB654 ,Group Modifier Bit 654" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1"
bitfld.long 0x00 12. "  GMB652 ,Group Modifier Bit 652" "0,1"
bitfld.long 0x00 11. "  GMB651 ,Group Modifier Bit 651" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1"
bitfld.long 0x00 9. "  GMB649 ,Group Modifier Bit 649" "0,1"
bitfld.long 0x00 8. "  GMB648 ,Group Modifier Bit 648" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1"
bitfld.long 0x00 6. "  GMB646 ,Group Modifier Bit 646" "0,1"
bitfld.long 0x00 5. "  GMB645 ,Group Modifier Bit 645" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1"
bitfld.long 0x00 3. "  GMB643 ,Group Modifier Bit 643" "0,1"
bitfld.long 0x00 2. "  GMB642 ,Group Modifier Bit 642" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1"
bitfld.long 0x00 0. "  GMB640 ,Group Modifier Bit 640" "0,1"
else
hgroup.long 0x0D50++0x03
hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x0D54++0x03
line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1"
bitfld.long 0x00 30. "  GMB702 ,Group Modifier Bit 702" "0,1"
bitfld.long 0x00 29. "  GMB701 ,Group Modifier Bit 701" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1"
bitfld.long 0x00 27. "  GMB699 ,Group Modifier Bit 699" "0,1"
bitfld.long 0x00 26. "  GMB698 ,Group Modifier Bit 698" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1"
bitfld.long 0x00 24. "  GMB696 ,Group Modifier Bit 696" "0,1"
bitfld.long 0x00 23. "  GMB695 ,Group Modifier Bit 695" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1"
bitfld.long 0x00 21. "  GMB693 ,Group Modifier Bit 693" "0,1"
bitfld.long 0x00 20. "  GMB692 ,Group Modifier Bit 692" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1"
bitfld.long 0x00 18. "  GMB690 ,Group Modifier Bit 690" "0,1"
bitfld.long 0x00 17. "  GMB689 ,Group Modifier Bit 689" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1"
bitfld.long 0x00 15. "  GMB687 ,Group Modifier Bit 687" "0,1"
bitfld.long 0x00 14. "  GMB686 ,Group Modifier Bit 686" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1"
bitfld.long 0x00 12. "  GMB684 ,Group Modifier Bit 684" "0,1"
bitfld.long 0x00 11. "  GMB683 ,Group Modifier Bit 683" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1"
bitfld.long 0x00 9. "  GMB681 ,Group Modifier Bit 681" "0,1"
bitfld.long 0x00 8. "  GMB680 ,Group Modifier Bit 680" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1"
bitfld.long 0x00 6. "  GMB678 ,Group Modifier Bit 678" "0,1"
bitfld.long 0x00 5. "  GMB677 ,Group Modifier Bit 677" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1"
bitfld.long 0x00 3. "  GMB675 ,Group Modifier Bit 675" "0,1"
bitfld.long 0x00 2. "  GMB674 ,Group Modifier Bit 674" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1"
bitfld.long 0x00 0. "  GMB672 ,Group Modifier Bit 672" "0,1"
else
hgroup.long 0x0D54++0x03
hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x0D58++0x03
line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1"
bitfld.long 0x00 30. "  GMB734 ,Group Modifier Bit 734" "0,1"
bitfld.long 0x00 29. "  GMB733 ,Group Modifier Bit 733" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1"
bitfld.long 0x00 27. "  GMB731 ,Group Modifier Bit 731" "0,1"
bitfld.long 0x00 26. "  GMB730 ,Group Modifier Bit 730" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1"
bitfld.long 0x00 24. "  GMB728 ,Group Modifier Bit 728" "0,1"
bitfld.long 0x00 23. "  GMB727 ,Group Modifier Bit 727" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1"
bitfld.long 0x00 21. "  GMB725 ,Group Modifier Bit 725" "0,1"
bitfld.long 0x00 20. "  GMB724 ,Group Modifier Bit 724" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1"
bitfld.long 0x00 18. "  GMB722 ,Group Modifier Bit 722" "0,1"
bitfld.long 0x00 17. "  GMB721 ,Group Modifier Bit 721" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1"
bitfld.long 0x00 15. "  GMB719 ,Group Modifier Bit 719" "0,1"
bitfld.long 0x00 14. "  GMB718 ,Group Modifier Bit 718" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1"
bitfld.long 0x00 12. "  GMB716 ,Group Modifier Bit 716" "0,1"
bitfld.long 0x00 11. "  GMB715 ,Group Modifier Bit 715" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1"
bitfld.long 0x00 9. "  GMB713 ,Group Modifier Bit 713" "0,1"
bitfld.long 0x00 8. "  GMB712 ,Group Modifier Bit 712" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1"
bitfld.long 0x00 6. "  GMB710 ,Group Modifier Bit 710" "0,1"
bitfld.long 0x00 5. "  GMB709 ,Group Modifier Bit 709" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1"
bitfld.long 0x00 3. "  GMB707 ,Group Modifier Bit 707" "0,1"
bitfld.long 0x00 2. "  GMB706 ,Group Modifier Bit 706" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1"
bitfld.long 0x00 0. "  GMB704 ,Group Modifier Bit 704" "0,1"
else
hgroup.long 0x0D58++0x03
hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x0D5C++0x03
line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1"
bitfld.long 0x00 30. "  GMB766 ,Group Modifier Bit 766" "0,1"
bitfld.long 0x00 29. "  GMB765 ,Group Modifier Bit 765" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1"
bitfld.long 0x00 27. "  GMB763 ,Group Modifier Bit 763" "0,1"
bitfld.long 0x00 26. "  GMB762 ,Group Modifier Bit 762" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1"
bitfld.long 0x00 24. "  GMB760 ,Group Modifier Bit 760" "0,1"
bitfld.long 0x00 23. "  GMB759 ,Group Modifier Bit 759" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1"
bitfld.long 0x00 21. "  GMB757 ,Group Modifier Bit 757" "0,1"
bitfld.long 0x00 20. "  GMB756 ,Group Modifier Bit 756" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1"
bitfld.long 0x00 18. "  GMB754 ,Group Modifier Bit 754" "0,1"
bitfld.long 0x00 17. "  GMB753 ,Group Modifier Bit 753" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1"
bitfld.long 0x00 15. "  GMB751 ,Group Modifier Bit 751" "0,1"
bitfld.long 0x00 14. "  GMB750 ,Group Modifier Bit 750" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1"
bitfld.long 0x00 12. "  GMB748 ,Group Modifier Bit 748" "0,1"
bitfld.long 0x00 11. "  GMB747 ,Group Modifier Bit 747" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1"
bitfld.long 0x00 9. "  GMB745 ,Group Modifier Bit 745" "0,1"
bitfld.long 0x00 8. "  GMB744 ,Group Modifier Bit 744" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1"
bitfld.long 0x00 6. "  GMB742 ,Group Modifier Bit 742" "0,1"
bitfld.long 0x00 5. "  GMB741 ,Group Modifier Bit 741" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1"
bitfld.long 0x00 3. "  GMB739 ,Group Modifier Bit 739" "0,1"
bitfld.long 0x00 2. "  GMB738 ,Group Modifier Bit 738" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1"
bitfld.long 0x00 0. "  GMB736 ,Group Modifier Bit 736" "0,1"
else
hgroup.long 0x0D5C++0x03
hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x0D60++0x03
line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1"
bitfld.long 0x00 30. "  GMB798 ,Group Modifier Bit 798" "0,1"
bitfld.long 0x00 29. "  GMB797 ,Group Modifier Bit 797" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1"
bitfld.long 0x00 27. "  GMB795 ,Group Modifier Bit 795" "0,1"
bitfld.long 0x00 26. "  GMB794 ,Group Modifier Bit 794" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1"
bitfld.long 0x00 24. "  GMB792 ,Group Modifier Bit 792" "0,1"
bitfld.long 0x00 23. "  GMB791 ,Group Modifier Bit 791" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1"
bitfld.long 0x00 21. "  GMB789 ,Group Modifier Bit 789" "0,1"
bitfld.long 0x00 20. "  GMB788 ,Group Modifier Bit 788" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1"
bitfld.long 0x00 18. "  GMB786 ,Group Modifier Bit 786" "0,1"
bitfld.long 0x00 17. "  GMB785 ,Group Modifier Bit 785" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1"
bitfld.long 0x00 15. "  GMB783 ,Group Modifier Bit 783" "0,1"
bitfld.long 0x00 14. "  GMB782 ,Group Modifier Bit 782" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1"
bitfld.long 0x00 12. "  GMB780 ,Group Modifier Bit 780" "0,1"
bitfld.long 0x00 11. "  GMB779 ,Group Modifier Bit 779" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1"
bitfld.long 0x00 9. "  GMB777 ,Group Modifier Bit 777" "0,1"
bitfld.long 0x00 8. "  GMB776 ,Group Modifier Bit 776" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1"
bitfld.long 0x00 6. "  GMB774 ,Group Modifier Bit 774" "0,1"
bitfld.long 0x00 5. "  GMB773 ,Group Modifier Bit 773" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1"
bitfld.long 0x00 3. "  GMB771 ,Group Modifier Bit 771" "0,1"
bitfld.long 0x00 2. "  GMB770 ,Group Modifier Bit 770" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1"
bitfld.long 0x00 0. "  GMB768 ,Group Modifier Bit 768" "0,1"
else
hgroup.long 0x0D60++0x03
hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x0D64++0x03
line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1"
bitfld.long 0x00 30. "  GMB830 ,Group Modifier Bit 830" "0,1"
bitfld.long 0x00 29. "  GMB829 ,Group Modifier Bit 829" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1"
bitfld.long 0x00 27. "  GMB827 ,Group Modifier Bit 827" "0,1"
bitfld.long 0x00 26. "  GMB826 ,Group Modifier Bit 826" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1"
bitfld.long 0x00 24. "  GMB824 ,Group Modifier Bit 824" "0,1"
bitfld.long 0x00 23. "  GMB823 ,Group Modifier Bit 823" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1"
bitfld.long 0x00 21. "  GMB821 ,Group Modifier Bit 821" "0,1"
bitfld.long 0x00 20. "  GMB820 ,Group Modifier Bit 820" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1"
bitfld.long 0x00 18. "  GMB818 ,Group Modifier Bit 818" "0,1"
bitfld.long 0x00 17. "  GMB817 ,Group Modifier Bit 817" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1"
bitfld.long 0x00 15. "  GMB815 ,Group Modifier Bit 815" "0,1"
bitfld.long 0x00 14. "  GMB814 ,Group Modifier Bit 814" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1"
bitfld.long 0x00 12. "  GMB812 ,Group Modifier Bit 812" "0,1"
bitfld.long 0x00 11. "  GMB811 ,Group Modifier Bit 811" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1"
bitfld.long 0x00 9. "  GMB809 ,Group Modifier Bit 809" "0,1"
bitfld.long 0x00 8. "  GMB808 ,Group Modifier Bit 808" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1"
bitfld.long 0x00 6. "  GMB806 ,Group Modifier Bit 806" "0,1"
bitfld.long 0x00 5. "  GMB805 ,Group Modifier Bit 805" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1"
bitfld.long 0x00 3. "  GMB803 ,Group Modifier Bit 803" "0,1"
bitfld.long 0x00 2. "  GMB802 ,Group Modifier Bit 802" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1"
bitfld.long 0x00 0. "  GMB800 ,Group Modifier Bit 800" "0,1"
else
hgroup.long 0x0D64++0x03
hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A))
group.long 0x0D68++0x03
line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1"
bitfld.long 0x00 30. "  GMB862 ,Group Modifier Bit 862" "0,1"
bitfld.long 0x00 29. "  GMB861 ,Group Modifier Bit 861" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1"
bitfld.long 0x00 27. "  GMB859 ,Group Modifier Bit 859" "0,1"
bitfld.long 0x00 26. "  GMB858 ,Group Modifier Bit 858" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1"
bitfld.long 0x00 24. "  GMB856 ,Group Modifier Bit 856" "0,1"
bitfld.long 0x00 23. "  GMB855 ,Group Modifier Bit 855" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1"
bitfld.long 0x00 21. "  GMB853 ,Group Modifier Bit 853" "0,1"
bitfld.long 0x00 20. "  GMB852 ,Group Modifier Bit 852" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1"
bitfld.long 0x00 18. "  GMB850 ,Group Modifier Bit 850" "0,1"
bitfld.long 0x00 17. "  GMB849 ,Group Modifier Bit 849" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1"
bitfld.long 0x00 15. "  GMB847 ,Group Modifier Bit 847" "0,1"
bitfld.long 0x00 14. "  GMB846 ,Group Modifier Bit 846" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1"
bitfld.long 0x00 12. "  GMB844 ,Group Modifier Bit 844" "0,1"
bitfld.long 0x00 11. "  GMB843 ,Group Modifier Bit 843" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1"
bitfld.long 0x00 9. "  GMB841 ,Group Modifier Bit 841" "0,1"
bitfld.long 0x00 8. "  GMB840 ,Group Modifier Bit 840" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1"
bitfld.long 0x00 6. "  GMB838 ,Group Modifier Bit 838" "0,1"
bitfld.long 0x00 5. "  GMB837 ,Group Modifier Bit 837" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1"
bitfld.long 0x00 3. "  GMB835 ,Group Modifier Bit 835" "0,1"
bitfld.long 0x00 2. "  GMB834 ,Group Modifier Bit 834" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1"
bitfld.long 0x00 0. "  GMB832 ,Group Modifier Bit 832" "0,1"
else
hgroup.long 0x0D68++0x03
hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x0D6C++0x03
line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1"
bitfld.long 0x00 30. "  GMB894 ,Group Modifier Bit 894" "0,1"
bitfld.long 0x00 29. "  GMB893 ,Group Modifier Bit 893" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1"
bitfld.long 0x00 27. "  GMB891 ,Group Modifier Bit 891" "0,1"
bitfld.long 0x00 26. "  GMB890 ,Group Modifier Bit 890" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1"
bitfld.long 0x00 24. "  GMB888 ,Group Modifier Bit 888" "0,1"
bitfld.long 0x00 23. "  GMB887 ,Group Modifier Bit 887" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1"
bitfld.long 0x00 21. "  GMB885 ,Group Modifier Bit 885" "0,1"
bitfld.long 0x00 20. "  GMB884 ,Group Modifier Bit 884" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1"
bitfld.long 0x00 18. "  GMB882 ,Group Modifier Bit 882" "0,1"
bitfld.long 0x00 17. "  GMB881 ,Group Modifier Bit 881" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1"
bitfld.long 0x00 15. "  GMB879 ,Group Modifier Bit 879" "0,1"
bitfld.long 0x00 14. "  GMB878 ,Group Modifier Bit 878" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1"
bitfld.long 0x00 12. "  GMB876 ,Group Modifier Bit 876" "0,1"
bitfld.long 0x00 11. "  GMB875 ,Group Modifier Bit 875" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1"
bitfld.long 0x00 9. "  GMB873 ,Group Modifier Bit 873" "0,1"
bitfld.long 0x00 8. "  GMB872 ,Group Modifier Bit 872" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1"
bitfld.long 0x00 6. "  GMB870 ,Group Modifier Bit 870" "0,1"
bitfld.long 0x00 5. "  GMB869 ,Group Modifier Bit 869" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1"
bitfld.long 0x00 3. "  GMB867 ,Group Modifier Bit 867" "0,1"
bitfld.long 0x00 2. "  GMB866 ,Group Modifier Bit 866" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1"
bitfld.long 0x00 0. "  GMB864 ,Group Modifier Bit 864" "0,1"
else
hgroup.long 0x0D6C++0x03
hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x0D70++0x03
line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1"
bitfld.long 0x00 30. "  GMB926 ,Group Modifier Bit 926" "0,1"
bitfld.long 0x00 29. "  GMB925 ,Group Modifier Bit 925" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1"
bitfld.long 0x00 27. "  GMB923 ,Group Modifier Bit 923" "0,1"
bitfld.long 0x00 26. "  GMB922 ,Group Modifier Bit 922" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1"
bitfld.long 0x00 24. "  GMB920 ,Group Modifier Bit 920" "0,1"
bitfld.long 0x00 23. "  GMB919 ,Group Modifier Bit 919" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1"
bitfld.long 0x00 21. "  GMB917 ,Group Modifier Bit 917" "0,1"
bitfld.long 0x00 20. "  GMB916 ,Group Modifier Bit 916" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1"
bitfld.long 0x00 18. "  GMB914 ,Group Modifier Bit 914" "0,1"
bitfld.long 0x00 17. "  GMB913 ,Group Modifier Bit 913" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1"
bitfld.long 0x00 15. "  GMB911 ,Group Modifier Bit 911" "0,1"
bitfld.long 0x00 14. "  GMB910 ,Group Modifier Bit 910" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1"
bitfld.long 0x00 12. "  GMB908 ,Group Modifier Bit 908" "0,1"
bitfld.long 0x00 11. "  GMB907 ,Group Modifier Bit 907" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1"
bitfld.long 0x00 9. "  GMB905 ,Group Modifier Bit 905" "0,1"
bitfld.long 0x00 8. "  GMB904 ,Group Modifier Bit 904" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1"
bitfld.long 0x00 6. "  GMB902 ,Group Modifier Bit 902" "0,1"
bitfld.long 0x00 5. "  GMB901 ,Group Modifier Bit 901" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1"
bitfld.long 0x00 3. "  GMB899 ,Group Modifier Bit 899" "0,1"
bitfld.long 0x00 2. "  GMB898 ,Group Modifier Bit 898" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1"
bitfld.long 0x00 0. "  GMB896 ,Group Modifier Bit 896" "0,1"
else
hgroup.long 0x0D70++0x03
hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x0D74++0x03
line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1"
bitfld.long 0x00 30. "  GMB958 ,Group Modifier Bit 958" "0,1"
bitfld.long 0x00 29. "  GMB957 ,Group Modifier Bit 957" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1"
bitfld.long 0x00 27. "  GMB955 ,Group Modifier Bit 955" "0,1"
bitfld.long 0x00 26. "  GMB954 ,Group Modifier Bit 954" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1"
bitfld.long 0x00 24. "  GMB952 ,Group Modifier Bit 952" "0,1"
bitfld.long 0x00 23. "  GMB951 ,Group Modifier Bit 951" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1"
bitfld.long 0x00 21. "  GMB949 ,Group Modifier Bit 949" "0,1"
bitfld.long 0x00 20. "  GMB948 ,Group Modifier Bit 948" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1"
bitfld.long 0x00 18. "  GMB946 ,Group Modifier Bit 946" "0,1"
bitfld.long 0x00 17. "  GMB945 ,Group Modifier Bit 945" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1"
bitfld.long 0x00 15. "  GMB943 ,Group Modifier Bit 943" "0,1"
bitfld.long 0x00 14. "  GMB942 ,Group Modifier Bit 942" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1"
bitfld.long 0x00 12. "  GMB940 ,Group Modifier Bit 940" "0,1"
bitfld.long 0x00 11. "  GMB939 ,Group Modifier Bit 939" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1"
bitfld.long 0x00 9. "  GMB937 ,Group Modifier Bit 937" "0,1"
bitfld.long 0x00 8. "  GMB936 ,Group Modifier Bit 936" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1"
bitfld.long 0x00 6. "  GMB934 ,Group Modifier Bit 934" "0,1"
bitfld.long 0x00 5. "  GMB933 ,Group Modifier Bit 933" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1"
bitfld.long 0x00 3. "  GMB931 ,Group Modifier Bit 931" "0,1"
bitfld.long 0x00 2. "  GMB930 ,Group Modifier Bit 930" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1"
bitfld.long 0x00 0. "  GMB928 ,Group Modifier Bit 928" "0,1"
else
hgroup.long 0x0D74++0x03
hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x0D78++0x03
line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1"
bitfld.long 0x00 30. "  GMB990 ,Group Modifier Bit 990" "0,1"
bitfld.long 0x00 29. "  GMB989 ,Group Modifier Bit 989" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1"
bitfld.long 0x00 27. "  GMB987 ,Group Modifier Bit 987" "0,1"
bitfld.long 0x00 26. "  GMB986 ,Group Modifier Bit 986" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1"
bitfld.long 0x00 24. "  GMB984 ,Group Modifier Bit 984" "0,1"
bitfld.long 0x00 23. "  GMB983 ,Group Modifier Bit 983" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1"
bitfld.long 0x00 21. "  GMB981 ,Group Modifier Bit 981" "0,1"
bitfld.long 0x00 20. "  GMB980 ,Group Modifier Bit 980" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1"
bitfld.long 0x00 18. "  GMB978 ,Group Modifier Bit 978" "0,1"
bitfld.long 0x00 17. "  GMB977 ,Group Modifier Bit 977" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1"
bitfld.long 0x00 15. "  GMB975 ,Group Modifier Bit 975" "0,1"
bitfld.long 0x00 14. "  GMB974 ,Group Modifier Bit 974" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1"
bitfld.long 0x00 12. "  GMB972 ,Group Modifier Bit 972" "0,1"
bitfld.long 0x00 11. "  GMB971 ,Group Modifier Bit 971" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1"
bitfld.long 0x00 9. "  GMB969 ,Group Modifier Bit 969" "0,1"
bitfld.long 0x00 8. "  GMB968 ,Group Modifier Bit 968" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1"
bitfld.long 0x00 6. "  GMB966 ,Group Modifier Bit 966" "0,1"
bitfld.long 0x00 5. "  GMB965 ,Group Modifier Bit 965" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1"
bitfld.long 0x00 3. "  GMB963 ,Group Modifier Bit 963" "0,1"
bitfld.long 0x00 2. "  GMB962 ,Group Modifier Bit 962" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1"
bitfld.long 0x00 0. "  GMB960 ,Group Modifier Bit 960" "0,1"
else
hgroup.long 0x0D78++0x03
hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
endif
tree.end
width 14.
tree "Non-secure Access Control Registers"
hgroup.long 0x0E00++0x03
hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0"
hgroup.long 0xE04++0x03
hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08)))
group.long 0xE08++0x03
line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
bitfld.long 0x00 30.--31. " NS_ACCESS47  ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS46  ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS45  ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS44  ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS43  ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS42  ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS41  ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS40  ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS39  ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS38  ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS37  ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS36  ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS35  ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS34  ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS33  ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS32  ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE08++0x03
hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C)))
group.long 0xE0C++0x03
line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
bitfld.long 0x00 30.--31. " NS_ACCESS63  ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS62  ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS61  ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS60  ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS59  ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS58  ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS57  ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS56  ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS55  ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS54  ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS53  ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS52  ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS51  ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS50  ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS49  ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS48  ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE0C++0x03
hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10)))
group.long 0xE10++0x03
line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
bitfld.long 0x00 30.--31. " NS_ACCESS79  ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS78  ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS77  ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS76  ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS75  ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS74  ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS73  ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS72  ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS71  ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS70  ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS69  ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS68  ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS67  ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS66  ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS65  ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS64  ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE10++0x03
hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14)))
group.long 0xE14++0x03
line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
bitfld.long 0x00 30.--31. " NS_ACCESS95  ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS94  ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS93  ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS92  ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS91  ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS90  ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS89  ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS88  ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS87  ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS86  ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS85  ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS84  ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS83  ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS82  ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS81  ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS80  ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE14++0x03
hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18)))
group.long 0xE18++0x03
line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS99  ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS98  ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS97  ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS96  ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE18++0x03
hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C)))
group.long 0xE1C++0x03
line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE1C++0x03
hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20)))
group.long 0xE20++0x03
line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE20++0x03
hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24)))
group.long 0xE24++0x03
line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE24++0x03
hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28)))
group.long 0xE28++0x03
line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE28++0x03
hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C)))
group.long 0xE2C++0x03
line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE2C++0x03
hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30)))
group.long 0xE30++0x03
line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE30++0x03
hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34)))
group.long 0xE34++0x03
line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE34++0x03
hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38)))
group.long 0xE38++0x03
line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE38++0x03
hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C)))
group.long 0xE3C++0x03
line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE3C++0x03
hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40)))
group.long 0xE40++0x03
line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE40++0x03
hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44)))
group.long 0xE44++0x03
line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE44++0x03
hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48)))
group.long 0xE48++0x03
line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE48++0x03
hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C)))
group.long 0xE4C++0x03
line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE4C++0x03
hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50)))
group.long 0xE50++0x03
line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE50++0x03
hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54)))
group.long 0xE54++0x03
line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE54++0x03
hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58)))
group.long 0xE58++0x03
line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE58++0x03
hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C)))
group.long 0xE5C++0x03
line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE5C++0x03
hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60)))
group.long 0xE60++0x03
line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE60++0x03
hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64)))
group.long 0xE64++0x03
line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE64++0x03
hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68)))
group.long 0xE68++0x03
line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE68++0x03
hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C)))
group.long 0xE6C++0x03
line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE6C++0x03
hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70)))
group.long 0xE70++0x03
line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE70++0x03
hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74)))
group.long 0xE74++0x03
line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE74++0x03
hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78)))
group.long 0xE78++0x03
line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE78++0x03
hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C)))
group.long 0xE7C++0x03
line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE7C++0x03
hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80)))
group.long 0xE80++0x03
line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE80++0x03
hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84)))
group.long 0xE84++0x03
line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE84++0x03
hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88)))
group.long 0xE88++0x03
line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE88++0x03
hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C)))
group.long 0xE8C++0x03
line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE8C++0x03
hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90)))
group.long 0xE90++0x03
line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE90++0x03
hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94)))
group.long 0xE94++0x03
line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE94++0x03
hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98)))
group.long 0xE98++0x03
line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE98++0x03
hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C)))
group.long 0xE9C++0x03
line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE9C++0x03
hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0)))
group.long 0xEA0++0x03
line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA0++0x03
hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4)))
group.long 0xEA4++0x03
line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA4++0x03
hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8)))
group.long 0xEA8++0x03
line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA8++0x03
hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC)))
group.long 0xEAC++0x03
line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEAC++0x03
hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0)))
group.long 0xEB0++0x03
line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB0++0x03
hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4)))
group.long 0xEB4++0x03
line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB4++0x03
hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8)))
group.long 0xEB8++0x03
line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB8++0x03
hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC)))
group.long 0xEBC++0x03
line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEBC++0x03
hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0)))
group.long 0xEC0++0x03
line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC0++0x03
hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4)))
group.long 0xEC4++0x03
line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC4++0x03
hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8)))
group.long 0xEC8++0x03
line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC8++0x03
hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC)))
group.long 0xECC++0x03
line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xECC++0x03
hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0)))
group.long 0xED0++0x03
line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED0++0x03
hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4)))
group.long 0xED4++0x03
line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED4++0x03
hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8)))
group.long 0xED8++0x03
line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED8++0x03
hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC)))
group.long 0xEDC++0x03
line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEDC++0x03
hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0)))
group.long 0xEE0++0x03
line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE0++0x03
hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4)))
group.long 0xEE4++0x03
line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE4++0x03
hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8)))
group.long 0xEE8++0x03
line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE8++0x03
hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC)))
group.long 0xEEC++0x03
line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEEC++0x03
hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0)))
group.long 0xEF0++0x03
line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF0++0x03
hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4)))
group.long 0xEF4++0x03
line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF4++0x03
hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0F00++0x03
hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
hgroup.long 0xF10++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
hgroup.long 0xF14++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
hgroup.long 0xF18++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
hgroup.long 0xF1C++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
hgroup.long 0xF20++0x03
hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
hgroup.long 0xF24++0x03
hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
hgroup.long 0xF28++0x03
hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
hgroup.long 0xF2C++0x03
hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
group.long 0xF10++0x03
line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
group.long 0xF14++0x03
line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
group.long 0xF18++0x03
line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
group.long 0xF1C++0x03
line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
group.long 0xF20++0x03
line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
group.long 0xF24++0x03
line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
group.long 0xF28++0x03
line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
group.long 0xF2C++0x03
line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
endif
tree.end
width 24.
tree "Interrupt Routing Registers"
group.quad 0x6100++0x07
line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6108++0x07
line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6110++0x07
line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6118++0x07
line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6120++0x07
line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6128++0x07
line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6130++0x07
line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6138++0x07
line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6140++0x07
line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6148++0x07
line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6150++0x07
line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6158++0x07
line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6160++0x07
line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6168++0x07
line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6170++0x07
line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6178++0x07
line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6180++0x07
line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6188++0x07
line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6190++0x07
line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6198++0x07
line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A0++0x07
line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A8++0x07
line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B0++0x07
line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B8++0x07
line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C0++0x07
line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C8++0x07
line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D0++0x07
line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D8++0x07
line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E0++0x07
line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E8++0x07
line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F0++0x07
line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F8++0x07
line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6200++0x07
line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6208++0x07
line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6210++0x07
line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6218++0x07
line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6220++0x07
line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6228++0x07
line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6230++0x07
line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6238++0x07
line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6240++0x07
line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6248++0x07
line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6250++0x07
line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6258++0x07
line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6260++0x07
line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6268++0x07
line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6270++0x07
line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6278++0x07
line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6280++0x07
line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6288++0x07
line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6290++0x07
line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6298++0x07
line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A0++0x07
line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A8++0x07
line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B0++0x07
line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B8++0x07
line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C0++0x07
line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C8++0x07
line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D0++0x07
line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D8++0x07
line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E0++0x07
line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E8++0x07
line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F0++0x07
line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F8++0x07
line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6300++0x07
line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6308++0x07
line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6310++0x07
line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6318++0x07
line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6320++0x07
line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6328++0x07
line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6330++0x07
line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6338++0x07
line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6340++0x07
line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6348++0x07
line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6350++0x07
line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6358++0x07
line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6360++0x07
line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6368++0x07
line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6370++0x07
line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6378++0x07
line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6380++0x07
line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6388++0x07
line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6390++0x07
line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6398++0x07
line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A0++0x07
line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A8++0x07
line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B0++0x07
line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B8++0x07
line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C0++0x07
line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C8++0x07
line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D0++0x07
line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D8++0x07
line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E0++0x07
line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E8++0x07
line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F0++0x07
line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F8++0x07
line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6400++0x07
line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6408++0x07
line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6410++0x07
line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6418++0x07
line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6420++0x07
line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6428++0x07
line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6430++0x07
line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6438++0x07
line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6440++0x07
line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6448++0x07
line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6450++0x07
line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6458++0x07
line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6460++0x07
line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6468++0x07
line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6470++0x07
line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6478++0x07
line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6480++0x07
line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6488++0x07
line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6490++0x07
line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6498++0x07
line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A0++0x07
line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A8++0x07
line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B0++0x07
line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B8++0x07
line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C0++0x07
line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C8++0x07
line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D0++0x07
line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D8++0x07
line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E0++0x07
line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E8++0x07
line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F0++0x07
line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F8++0x07
line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6500++0x07
line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6508++0x07
line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6510++0x07
line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6518++0x07
line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6520++0x07
line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6528++0x07
line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6530++0x07
line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6538++0x07
line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6540++0x07
line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6548++0x07
line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6550++0x07
line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6558++0x07
line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6560++0x07
line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6568++0x07
line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6570++0x07
line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6578++0x07
line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6580++0x07
line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6588++0x07
line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6590++0x07
line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6598++0x07
line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A0++0x07
line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A8++0x07
line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B0++0x07
line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B8++0x07
line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C0++0x07
line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C8++0x07
line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D0++0x07
line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D8++0x07
line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E0++0x07
line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E8++0x07
line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F0++0x07
line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F8++0x07
line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6600++0x07
line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6608++0x07
line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6610++0x07
line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6618++0x07
line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6620++0x07
line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6628++0x07
line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6630++0x07
line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6638++0x07
line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6640++0x07
line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6648++0x07
line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6650++0x07
line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6658++0x07
line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6660++0x07
line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6668++0x07
line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6670++0x07
line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6678++0x07
line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6680++0x07
line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6688++0x07
line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6690++0x07
line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6698++0x07
line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A0++0x07
line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A8++0x07
line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B0++0x07
line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B8++0x07
line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C0++0x07
line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C8++0x07
line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D0++0x07
line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D8++0x07
line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E0++0x07
line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E8++0x07
line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F0++0x07
line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F8++0x07
line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6700++0x07
line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6708++0x07
line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6710++0x07
line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6718++0x07
line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6720++0x07
line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6728++0x07
line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6730++0x07
line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6738++0x07
line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6740++0x07
line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6748++0x07
line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6750++0x07
line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6758++0x07
line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6760++0x07
line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6768++0x07
line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6770++0x07
line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6778++0x07
line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6780++0x07
line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6788++0x07
line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6790++0x07
line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6798++0x07
line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A0++0x07
line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A8++0x07
line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B0++0x07
line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B8++0x07
line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C0++0x07
line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C8++0x07
line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D0++0x07
line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D8++0x07
line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E0++0x07
line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E8++0x07
line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F0++0x07
line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F8++0x07
line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6800++0x07
line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6808++0x07
line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6810++0x07
line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6818++0x07
line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6820++0x07
line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6828++0x07
line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6830++0x07
line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6838++0x07
line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6840++0x07
line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6848++0x07
line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6850++0x07
line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6858++0x07
line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6860++0x07
line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6868++0x07
line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6870++0x07
line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6878++0x07
line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6880++0x07
line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6888++0x07
line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6890++0x07
line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6898++0x07
line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A0++0x07
line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A8++0x07
line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B0++0x07
line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B8++0x07
line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C0++0x07
line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C8++0x07
line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D0++0x07
line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D8++0x07
line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E0++0x07
line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E8++0x07
line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F0++0x07
line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F8++0x07
line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6900++0x07
line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6908++0x07
line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6910++0x07
line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6918++0x07
line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6920++0x07
line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6928++0x07
line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6930++0x07
line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6938++0x07
line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6940++0x07
line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6948++0x07
line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6950++0x07
line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6958++0x07
line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6960++0x07
line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6968++0x07
line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6970++0x07
line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6978++0x07
line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6980++0x07
line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6988++0x07
line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6990++0x07
line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6998++0x07
line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A0++0x07
line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A8++0x07
line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B0++0x07
line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B8++0x07
line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C0++0x07
line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C8++0x07
line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D0++0x07
line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D8++0x07
line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E0++0x07
line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E8++0x07
line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F0++0x07
line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F8++0x07
line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A00++0x07
line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A08++0x07
line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A10++0x07
line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A18++0x07
line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A20++0x07
line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A28++0x07
line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A30++0x07
line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A38++0x07
line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A40++0x07
line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A48++0x07
line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A50++0x07
line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A58++0x07
line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A60++0x07
line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A68++0x07
line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A70++0x07
line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A78++0x07
line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A80++0x07
line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A88++0x07
line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A90++0x07
line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A98++0x07
line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA0++0x07
line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA8++0x07
line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB0++0x07
line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB8++0x07
line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC0++0x07
line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC8++0x07
line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD0++0x07
line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD8++0x07
line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE0++0x07
line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE8++0x07
line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF0++0x07
line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF8++0x07
line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B00++0x07
line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B08++0x07
line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B10++0x07
line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B18++0x07
line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B20++0x07
line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B28++0x07
line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B30++0x07
line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B38++0x07
line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B40++0x07
line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B48++0x07
line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B50++0x07
line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B58++0x07
line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B60++0x07
line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B68++0x07
line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B70++0x07
line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B78++0x07
line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B80++0x07
line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B88++0x07
line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B90++0x07
line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B98++0x07
line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA0++0x07
line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA8++0x07
line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB0++0x07
line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB8++0x07
line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC0++0x07
line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC8++0x07
line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD0++0x07
line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD8++0x07
line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE0++0x07
line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE8++0x07
line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF0++0x07
line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF8++0x07
line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C00++0x07
line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C08++0x07
line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C10++0x07
line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C18++0x07
line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C20++0x07
line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C28++0x07
line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C30++0x07
line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C38++0x07
line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C40++0x07
line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C48++0x07
line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C50++0x07
line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C58++0x07
line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C60++0x07
line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C68++0x07
line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C70++0x07
line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C78++0x07
line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C80++0x07
line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C88++0x07
line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C90++0x07
line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C98++0x07
line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA0++0x07
line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA8++0x07
line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB0++0x07
line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB8++0x07
line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC0++0x07
line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC8++0x07
line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD0++0x07
line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD8++0x07
line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE0++0x07
line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE8++0x07
line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF0++0x07
line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF8++0x07
line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D00++0x07
line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D08++0x07
line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D10++0x07
line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D18++0x07
line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D20++0x07
line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D28++0x07
line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D30++0x07
line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D38++0x07
line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D40++0x07
line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D48++0x07
line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D50++0x07
line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D58++0x07
line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D60++0x07
line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D68++0x07
line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D70++0x07
line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D78++0x07
line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D80++0x07
line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D88++0x07
line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D90++0x07
line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D98++0x07
line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA0++0x07
line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA8++0x07
line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB0++0x07
line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB8++0x07
line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC0++0x07
line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC8++0x07
line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD0++0x07
line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD8++0x07
line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE0++0x07
line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE8++0x07
line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF0++0x07
line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF8++0x07
line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E00++0x07
line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E08++0x07
line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E10++0x07
line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E18++0x07
line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E20++0x07
line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E28++0x07
line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E30++0x07
line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E38++0x07
line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E40++0x07
line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E48++0x07
line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E50++0x07
line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E58++0x07
line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E60++0x07
line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E68++0x07
line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E70++0x07
line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E78++0x07
line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E80++0x07
line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E88++0x07
line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E90++0x07
line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E98++0x07
line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA0++0x07
line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA8++0x07
line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB0++0x07
line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB8++0x07
line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC0++0x07
line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC8++0x07
line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED0++0x07
line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED8++0x07
line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE0++0x07
line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE8++0x07
line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF0++0x07
line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF8++0x07
line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F00++0x07
line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F08++0x07
line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F10++0x07
line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F18++0x07
line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F20++0x07
line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F28++0x07
line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F30++0x07
line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F38++0x07
line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F40++0x07
line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F48++0x07
line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F50++0x07
line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F58++0x07
line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F60++0x07
line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F68++0x07
line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F70++0x07
line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F78++0x07
line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F80++0x07
line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F88++0x07
line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F90++0x07
line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F98++0x07
line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA0++0x07
line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA8++0x07
line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB0++0x07
line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB8++0x07
line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC0++0x07
line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC8++0x07
line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD0++0x07
line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD8++0x07
line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE0++0x07
line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE8++0x07
line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF0++0x07
line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF8++0x07
line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7000++0x07
line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7008++0x07
line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7010++0x07
line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7018++0x07
line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7020++0x07
line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7028++0x07
line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7030++0x07
line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7038++0x07
line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7040++0x07
line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7048++0x07
line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7050++0x07
line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7058++0x07
line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7060++0x07
line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7068++0x07
line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7070++0x07
line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7078++0x07
line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7080++0x07
line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7088++0x07
line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7090++0x07
line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7098++0x07
line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A0++0x07
line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A8++0x07
line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B0++0x07
line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B8++0x07
line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C0++0x07
line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C8++0x07
line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D0++0x07
line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D8++0x07
line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E0++0x07
line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E8++0x07
line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F0++0x07
line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F8++0x07
line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7100++0x07
line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7108++0x07
line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7110++0x07
line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7118++0x07
line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7120++0x07
line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7128++0x07
line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7130++0x07
line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7138++0x07
line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7140++0x07
line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7148++0x07
line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7150++0x07
line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7158++0x07
line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7160++0x07
line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7168++0x07
line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7170++0x07
line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7178++0x07
line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7180++0x07
line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7188++0x07
line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7190++0x07
line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7198++0x07
line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A0++0x07
line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A8++0x07
line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B0++0x07
line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B8++0x07
line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C0++0x07
line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C8++0x07
line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D0++0x07
line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D8++0x07
line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E0++0x07
line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E8++0x07
line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F0++0x07
line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F8++0x07
line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7200++0x07
line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7208++0x07
line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7210++0x07
line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7218++0x07
line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7220++0x07
line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7228++0x07
line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7230++0x07
line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7238++0x07
line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7240++0x07
line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7248++0x07
line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7250++0x07
line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7258++0x07
line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7260++0x07
line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7268++0x07
line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7270++0x07
line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7278++0x07
line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7280++0x07
line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7288++0x07
line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7290++0x07
line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7298++0x07
line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A0++0x07
line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A8++0x07
line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B0++0x07
line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B8++0x07
line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C0++0x07
line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C8++0x07
line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D0++0x07
line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D8++0x07
line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E0++0x07
line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E8++0x07
line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F0++0x07
line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F8++0x07
line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7300++0x07
line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7308++0x07
line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7310++0x07
line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7318++0x07
line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7320++0x07
line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7328++0x07
line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7330++0x07
line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7338++0x07
line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7340++0x07
line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7348++0x07
line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7350++0x07
line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7358++0x07
line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7360++0x07
line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7368++0x07
line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7370++0x07
line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7378++0x07
line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7380++0x07
line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7388++0x07
line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7390++0x07
line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7398++0x07
line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A0++0x07
line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A8++0x07
line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B0++0x07
line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B8++0x07
line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C0++0x07
line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C8++0x07
line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D0++0x07
line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D8++0x07
line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E0++0x07
line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E8++0x07
line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F0++0x07
line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F8++0x07
line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7400++0x07
line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7408++0x07
line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7410++0x07
line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7418++0x07
line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7420++0x07
line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7428++0x07
line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7430++0x07
line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7438++0x07
line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7440++0x07
line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7448++0x07
line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7450++0x07
line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7458++0x07
line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7460++0x07
line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7468++0x07
line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7470++0x07
line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7478++0x07
line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7480++0x07
line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7488++0x07
line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7490++0x07
line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7498++0x07
line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A0++0x07
line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A8++0x07
line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B0++0x07
line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B8++0x07
line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C0++0x07
line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C8++0x07
line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D0++0x07
line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D8++0x07
line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E0++0x07
line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E8++0x07
line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F0++0x07
line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F8++0x07
line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7500++0x07
line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7508++0x07
line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7510++0x07
line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7518++0x07
line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7520++0x07
line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7528++0x07
line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7530++0x07
line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7538++0x07
line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7540++0x07
line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7548++0x07
line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7550++0x07
line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7558++0x07
line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7560++0x07
line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7568++0x07
line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7570++0x07
line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7578++0x07
line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7580++0x07
line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7588++0x07
line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7590++0x07
line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7598++0x07
line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A0++0x07
line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A8++0x07
line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B0++0x07
line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B8++0x07
line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C0++0x07
line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C8++0x07
line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D0++0x07
line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D8++0x07
line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E0++0x07
line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E8++0x07
line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F0++0x07
line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F8++0x07
line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7600++0x07
line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7608++0x07
line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7610++0x07
line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7618++0x07
line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7620++0x07
line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7628++0x07
line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7630++0x07
line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7638++0x07
line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7640++0x07
line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7648++0x07
line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7650++0x07
line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7658++0x07
line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7660++0x07
line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7668++0x07
line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7670++0x07
line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7678++0x07
line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7680++0x07
line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7688++0x07
line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7690++0x07
line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7698++0x07
line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A0++0x07
line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A8++0x07
line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B0++0x07
line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B8++0x07
line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C0++0x07
line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C8++0x07
line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D0++0x07
line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D8++0x07
line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E0++0x07
line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E8++0x07
line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F0++0x07
line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F8++0x07
line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7700++0x07
line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7708++0x07
line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7710++0x07
line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7718++0x07
line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7720++0x07
line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7728++0x07
line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7730++0x07
line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7738++0x07
line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7740++0x07
line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7748++0x07
line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7750++0x07
line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7758++0x07
line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7760++0x07
line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7768++0x07
line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7770++0x07
line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7778++0x07
line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7780++0x07
line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7788++0x07
line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7790++0x07
line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7798++0x07
line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A0++0x07
line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A8++0x07
line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B0++0x07
line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B8++0x07
line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C0++0x07
line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C8++0x07
line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D0++0x07
line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D8++0x07
line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E0++0x07
line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E8++0x07
line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F0++0x07
line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F8++0x07
line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7800++0x07
line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7808++0x07
line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7810++0x07
line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7818++0x07
line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7820++0x07
line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7828++0x07
line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7830++0x07
line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7838++0x07
line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7840++0x07
line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7848++0x07
line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7850++0x07
line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7858++0x07
line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7860++0x07
line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7868++0x07
line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7870++0x07
line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7878++0x07
line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7880++0x07
line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7888++0x07
line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7890++0x07
line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7898++0x07
line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A0++0x07
line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A8++0x07
line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B0++0x07
line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B8++0x07
line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C0++0x07
line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C8++0x07
line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D0++0x07
line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D8++0x07
line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E0++0x07
line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E8++0x07
line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F0++0x07
line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F8++0x07
line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7900++0x07
line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7908++0x07
line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7910++0x07
line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7918++0x07
line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7920++0x07
line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7928++0x07
line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7930++0x07
line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7938++0x07
line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7940++0x07
line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7948++0x07
line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7950++0x07
line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7958++0x07
line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7960++0x07
line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7968++0x07
line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7970++0x07
line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7978++0x07
line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7980++0x07
line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7988++0x07
line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7990++0x07
line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7998++0x07
line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A0++0x07
line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A8++0x07
line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B0++0x07
line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B8++0x07
line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C0++0x07
line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C8++0x07
line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D0++0x07
line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D8++0x07
line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E0++0x07
line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E8++0x07
line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F0++0x07
line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F8++0x07
line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A00++0x07
line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A08++0x07
line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A10++0x07
line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A18++0x07
line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A20++0x07
line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A28++0x07
line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A30++0x07
line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A38++0x07
line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A40++0x07
line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A48++0x07
line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A50++0x07
line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A58++0x07
line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A60++0x07
line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A68++0x07
line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A70++0x07
line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A78++0x07
line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A80++0x07
line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A88++0x07
line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A90++0x07
line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A98++0x07
line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA0++0x07
line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA8++0x07
line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB0++0x07
line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB8++0x07
line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC0++0x07
line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC8++0x07
line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD0++0x07
line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD8++0x07
line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE0++0x07
line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE8++0x07
line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF0++0x07
line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF8++0x07
line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B00++0x07
line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B08++0x07
line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B10++0x07
line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B18++0x07
line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B20++0x07
line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B28++0x07
line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B30++0x07
line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B38++0x07
line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B40++0x07
line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B48++0x07
line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B50++0x07
line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B58++0x07
line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B60++0x07
line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B68++0x07
line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B70++0x07
line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B78++0x07
line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B80++0x07
line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B88++0x07
line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B90++0x07
line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B98++0x07
line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA0++0x07
line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA8++0x07
line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB0++0x07
line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB8++0x07
line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC0++0x07
line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC8++0x07
line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD0++0x07
line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD8++0x07
line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE0++0x07
line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE8++0x07
line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF0++0x07
line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF8++0x07
line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C00++0x07
line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C08++0x07
line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C10++0x07
line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C18++0x07
line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C20++0x07
line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C28++0x07
line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C30++0x07
line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C38++0x07
line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C40++0x07
line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C48++0x07
line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C50++0x07
line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C58++0x07
line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C60++0x07
line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C68++0x07
line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C70++0x07
line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C78++0x07
line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C80++0x07
line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C88++0x07
line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C90++0x07
line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C98++0x07
line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA0++0x07
line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA8++0x07
line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB0++0x07
line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB8++0x07
line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC0++0x07
line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC8++0x07
line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD0++0x07
line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD8++0x07
line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE0++0x07
line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE8++0x07
line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF0++0x07
line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF8++0x07
line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D00++0x07
line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D08++0x07
line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D10++0x07
line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D18++0x07
line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D20++0x07
line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D28++0x07
line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D30++0x07
line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D38++0x07
line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D40++0x07
line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D48++0x07
line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D50++0x07
line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D58++0x07
line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D60++0x07
line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D68++0x07
line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D70++0x07
line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D78++0x07
line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D80++0x07
line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D88++0x07
line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D90++0x07
line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D98++0x07
line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA0++0x07
line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA8++0x07
line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB0++0x07
line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB8++0x07
line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC0++0x07
line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC8++0x07
line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD0++0x07
line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD8++0x07
line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE0++0x07
line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE8++0x07
line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF0++0x07
line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF8++0x07
line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E00++0x07
line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E08++0x07
line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E10++0x07
line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E18++0x07
line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E20++0x07
line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E28++0x07
line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E30++0x07
line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E38++0x07
line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E40++0x07
line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E48++0x07
line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E50++0x07
line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E58++0x07
line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E60++0x07
line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E68++0x07
line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E70++0x07
line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E78++0x07
line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E80++0x07
line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E88++0x07
line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E90++0x07
line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E98++0x07
line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA0++0x07
line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA8++0x07
line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB0++0x07
line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB8++0x07
line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC0++0x07
line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC8++0x07
line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED0++0x07
line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED8++0x07
line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE0++0x07
line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE8++0x07
line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF0++0x07
line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF8++0x07
line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
tree.end
width 22.
tree "Implementation Defined Test Registers"
rgroup.long 0xC000++0x03
line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR"
bitfld.long 0x00 31. " SRWP     ,Super Register Write Pending" "Not pending,Pending"
wgroup.long 0xC004++0x03
line.long 0x00 "GICD_ERRTESTR,Error Test Register"
bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High"
bitfld.long 0x00 0. "         ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High"
textline "                               "
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
rgroup.long 0xC084++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
bitfld.long 0x00 31. " SPIS63  ,SPI Status Bit 63" "Low,High"
bitfld.long 0x00 30. "  SPIS62  ,SPI Status Bit 62" "Low,High"
bitfld.long 0x00 29. "  SPIS61  ,SPI Status Bit 61" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS60  ,SPI Status Bit 60" "Low,High"
bitfld.long 0x00 27. "  SPIS59  ,SPI Status Bit 59" "Low,High"
bitfld.long 0x00 26. "  SPIS58  ,SPI Status Bit 58" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS57  ,SPI Status Bit 57" "Low,High"
bitfld.long 0x00 24. "  SPIS56  ,SPI Status Bit 56" "Low,High"
bitfld.long 0x00 23. "  SPIS55  ,SPI Status Bit 55" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS54  ,SPI Status Bit 54" "Low,High"
bitfld.long 0x00 21. "  SPIS53  ,SPI Status Bit 53" "Low,High"
bitfld.long 0x00 20. "  SPIS52  ,SPI Status Bit 52" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS51  ,SPI Status Bit 51" "Low,High"
bitfld.long 0x00 18. "  SPIS50  ,SPI Status Bit 50" "Low,High"
bitfld.long 0x00 17. "  SPIS49  ,SPI Status Bit 49" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS48  ,SPI Status Bit 48" "Low,High"
bitfld.long 0x00 15. "  SPIS47  ,SPI Status Bit 47" "Low,High"
bitfld.long 0x00 14. "  SPIS46  ,SPI Status Bit 46" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS45  ,SPI Status Bit 45" "Low,High"
bitfld.long 0x00 12. "  SPIS44  ,SPI Status Bit 44" "Low,High"
bitfld.long 0x00 11. "  SPIS43  ,SPI Status Bit 43" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS42  ,SPI Status Bit 42" "Low,High"
bitfld.long 0x00 9. "  SPIS41  ,SPI Status Bit 41" "Low,High"
bitfld.long 0x00 8. "  SPIS40  ,SPI Status Bit 40" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS39  ,SPI Status Bit 39" "Low,High"
bitfld.long 0x00 6. "  SPIS38  ,SPI Status Bit 38" "Low,High"
bitfld.long 0x00 5. "  SPIS37  ,SPI Status Bit 37" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS36  ,SPI Status Bit 36" "Low,High"
bitfld.long 0x00 3. "  SPIS35  ,SPI Status Bit 35" "Low,High"
bitfld.long 0x00 2. "  SPIS34  ,SPI Status Bit 34" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS33  ,SPI Status Bit 33" "Low,High"
bitfld.long 0x00 0. "  SPIS32  ,SPI Status Bit 32" "Low,High"
else
hgroup.long 0xC084++0x03
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
rgroup.long 0xC088++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
bitfld.long 0x00 31. " SPIS95  ,SPI Status Bit 95" "Low,High"
bitfld.long 0x00 30. "  SPIS94  ,SPI Status Bit 94" "Low,High"
bitfld.long 0x00 29. "  SPIS93  ,SPI Status Bit 93" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS92  ,SPI Status Bit 92" "Low,High"
bitfld.long 0x00 27. "  SPIS91  ,SPI Status Bit 91" "Low,High"
bitfld.long 0x00 26. "  SPIS90  ,SPI Status Bit 90" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS89  ,SPI Status Bit 89" "Low,High"
bitfld.long 0x00 24. "  SPIS88  ,SPI Status Bit 88" "Low,High"
bitfld.long 0x00 23. "  SPIS87  ,SPI Status Bit 87" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS86  ,SPI Status Bit 86" "Low,High"
bitfld.long 0x00 21. "  SPIS85  ,SPI Status Bit 85" "Low,High"
bitfld.long 0x00 20. "  SPIS84  ,SPI Status Bit 84" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS83  ,SPI Status Bit 83" "Low,High"
bitfld.long 0x00 18. "  SPIS82  ,SPI Status Bit 82" "Low,High"
bitfld.long 0x00 17. "  SPIS81  ,SPI Status Bit 81" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS80  ,SPI Status Bit 80" "Low,High"
bitfld.long 0x00 15. "  SPIS79  ,SPI Status Bit 79" "Low,High"
bitfld.long 0x00 14. "  SPIS78  ,SPI Status Bit 78" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS77  ,SPI Status Bit 77" "Low,High"
bitfld.long 0x00 12. "  SPIS76  ,SPI Status Bit 76" "Low,High"
bitfld.long 0x00 11. "  SPIS75  ,SPI Status Bit 75" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS74  ,SPI Status Bit 74" "Low,High"
bitfld.long 0x00 9. "  SPIS73  ,SPI Status Bit 73" "Low,High"
bitfld.long 0x00 8. "  SPIS72  ,SPI Status Bit 72" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS71  ,SPI Status Bit 71" "Low,High"
bitfld.long 0x00 6. "  SPIS70  ,SPI Status Bit 70" "Low,High"
bitfld.long 0x00 5. "  SPIS69  ,SPI Status Bit 69" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS68  ,SPI Status Bit 68" "Low,High"
bitfld.long 0x00 3. "  SPIS67  ,SPI Status Bit 67" "Low,High"
bitfld.long 0x00 2. "  SPIS66  ,SPI Status Bit 66" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS65  ,SPI Status Bit 65" "Low,High"
bitfld.long 0x00 0. "  SPIS64  ,SPI Status Bit 64" "Low,High"
else
hgroup.long 0xC088++0x03
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
rgroup.long 0xC08C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High"
bitfld.long 0x00 30. "  SPIS126 ,SPI Status Bit 126" "Low,High"
bitfld.long 0x00 29. "  SPIS125 ,SPI Status Bit 125" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High"
bitfld.long 0x00 27. "  SPIS123 ,SPI Status Bit 123" "Low,High"
bitfld.long 0x00 26. "  SPIS122 ,SPI Status Bit 122" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High"
bitfld.long 0x00 24. "  SPIS120 ,SPI Status Bit 120" "Low,High"
bitfld.long 0x00 23. "  SPIS119 ,SPI Status Bit 119" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High"
bitfld.long 0x00 21. "  SPIS117 ,SPI Status Bit 117" "Low,High"
bitfld.long 0x00 20. "  SPIS116 ,SPI Status Bit 116" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High"
bitfld.long 0x00 18. "  SPIS114 ,SPI Status Bit 114" "Low,High"
bitfld.long 0x00 17. "  SPIS113 ,SPI Status Bit 113" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High"
bitfld.long 0x00 15. "  SPIS111 ,SPI Status Bit 111" "Low,High"
bitfld.long 0x00 14. "  SPIS110 ,SPI Status Bit 110" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High"
bitfld.long 0x00 12. "  SPIS108 ,SPI Status Bit 108" "Low,High"
bitfld.long 0x00 11. "  SPIS107 ,SPI Status Bit 107" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High"
bitfld.long 0x00 9. "  SPIS105 ,SPI Status Bit 105" "Low,High"
bitfld.long 0x00 8. "  SPIS104 ,SPI Status Bit 104" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High"
bitfld.long 0x00 6. "  SPIS102 ,SPI Status Bit 102" "Low,High"
bitfld.long 0x00 5. "  SPIS101 ,SPI Status Bit 101" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High"
bitfld.long 0x00 3. "  SPIS99  ,SPI Status Bit 99" "Low,High"
bitfld.long 0x00 2. "  SPIS98  ,SPI Status Bit 98" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS97  ,SPI Status Bit 97" "Low,High"
bitfld.long 0x00 0. "  SPIS96  ,SPI Status Bit 96" "Low,High"
else
hgroup.long 0xC08C++0x03
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
rgroup.long 0xC090++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High"
bitfld.long 0x00 30. "  SPIS158 ,SPI Status Bit 158" "Low,High"
bitfld.long 0x00 29. "  SPIS157 ,SPI Status Bit 157" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High"
bitfld.long 0x00 27. "  SPIS155 ,SPI Status Bit 155" "Low,High"
bitfld.long 0x00 26. "  SPIS154 ,SPI Status Bit 154" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High"
bitfld.long 0x00 24. "  SPIS152 ,SPI Status Bit 152" "Low,High"
bitfld.long 0x00 23. "  SPIS151 ,SPI Status Bit 151" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High"
bitfld.long 0x00 21. "  SPIS149 ,SPI Status Bit 149" "Low,High"
bitfld.long 0x00 20. "  SPIS148 ,SPI Status Bit 148" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High"
bitfld.long 0x00 18. "  SPIS146 ,SPI Status Bit 146" "Low,High"
bitfld.long 0x00 17. "  SPIS145 ,SPI Status Bit 145" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High"
bitfld.long 0x00 15. "  SPIS143 ,SPI Status Bit 143" "Low,High"
bitfld.long 0x00 14. "  SPIS142 ,SPI Status Bit 142" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High"
bitfld.long 0x00 12. "  SPIS140 ,SPI Status Bit 140" "Low,High"
bitfld.long 0x00 11. "  SPIS139 ,SPI Status Bit 139" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High"
bitfld.long 0x00 9. "  SPIS137 ,SPI Status Bit 137" "Low,High"
bitfld.long 0x00 8. "  SPIS136 ,SPI Status Bit 136" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High"
bitfld.long 0x00 6. "  SPIS134 ,SPI Status Bit 134" "Low,High"
bitfld.long 0x00 5. "  SPIS133 ,SPI Status Bit 133" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High"
bitfld.long 0x00 3. "  SPIS131 ,SPI Status Bit 131" "Low,High"
bitfld.long 0x00 2. "  SPIS130 ,SPI Status Bit 130" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High"
bitfld.long 0x00 0. "  SPIS128 ,SPI Status Bit 128" "Low,High"
else
hgroup.long 0xC090++0x03
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
rgroup.long 0xC094++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High"
bitfld.long 0x00 30. "  SPIS190 ,SPI Status Bit 190" "Low,High"
bitfld.long 0x00 29. "  SPIS189 ,SPI Status Bit 189" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High"
bitfld.long 0x00 27. "  SPIS187 ,SPI Status Bit 187" "Low,High"
bitfld.long 0x00 26. "  SPIS186 ,SPI Status Bit 186" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High"
bitfld.long 0x00 24. "  SPIS184 ,SPI Status Bit 184" "Low,High"
bitfld.long 0x00 23. "  SPIS183 ,SPI Status Bit 183" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High"
bitfld.long 0x00 21. "  SPIS181 ,SPI Status Bit 181" "Low,High"
bitfld.long 0x00 20. "  SPIS180 ,SPI Status Bit 180" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High"
bitfld.long 0x00 18. "  SPIS178 ,SPI Status Bit 178" "Low,High"
bitfld.long 0x00 17. "  SPIS177 ,SPI Status Bit 177" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High"
bitfld.long 0x00 15. "  SPIS175 ,SPI Status Bit 175" "Low,High"
bitfld.long 0x00 14. "  SPIS174 ,SPI Status Bit 174" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High"
bitfld.long 0x00 12. "  SPIS172 ,SPI Status Bit 172" "Low,High"
bitfld.long 0x00 11. "  SPIS171 ,SPI Status Bit 171" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High"
bitfld.long 0x00 9. "  SPIS169 ,SPI Status Bit 169" "Low,High"
bitfld.long 0x00 8. "  SPIS168 ,SPI Status Bit 168" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High"
bitfld.long 0x00 6. "  SPIS166 ,SPI Status Bit 166" "Low,High"
bitfld.long 0x00 5. "  SPIS165 ,SPI Status Bit 165" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High"
bitfld.long 0x00 3. "  SPIS163 ,SPI Status Bit 163" "Low,High"
bitfld.long 0x00 2. "  SPIS162 ,SPI Status Bit 162" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High"
bitfld.long 0x00 0. "  SPIS160 ,SPI Status Bit 160" "Low,High"
else
hgroup.long 0xC094++0x03
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
rgroup.long 0xC098++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High"
bitfld.long 0x00 30. "  SPIS222 ,SPI Status Bit 222" "Low,High"
bitfld.long 0x00 29. "  SPIS221 ,SPI Status Bit 221" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High"
bitfld.long 0x00 27. "  SPIS219 ,SPI Status Bit 219" "Low,High"
bitfld.long 0x00 26. "  SPIS218 ,SPI Status Bit 218" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High"
bitfld.long 0x00 24. "  SPIS216 ,SPI Status Bit 216" "Low,High"
bitfld.long 0x00 23. "  SPIS215 ,SPI Status Bit 215" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High"
bitfld.long 0x00 21. "  SPIS213 ,SPI Status Bit 213" "Low,High"
bitfld.long 0x00 20. "  SPIS212 ,SPI Status Bit 212" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High"
bitfld.long 0x00 18. "  SPIS210 ,SPI Status Bit 210" "Low,High"
bitfld.long 0x00 17. "  SPIS209 ,SPI Status Bit 209" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High"
bitfld.long 0x00 15. "  SPIS207 ,SPI Status Bit 207" "Low,High"
bitfld.long 0x00 14. "  SPIS206 ,SPI Status Bit 206" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High"
bitfld.long 0x00 12. "  SPIS204 ,SPI Status Bit 204" "Low,High"
bitfld.long 0x00 11. "  SPIS203 ,SPI Status Bit 203" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High"
bitfld.long 0x00 9. "  SPIS201 ,SPI Status Bit 201" "Low,High"
bitfld.long 0x00 8. "  SPIS200 ,SPI Status Bit 200" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High"
bitfld.long 0x00 6. "  SPIS198 ,SPI Status Bit 198" "Low,High"
bitfld.long 0x00 5. "  SPIS197 ,SPI Status Bit 197" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High"
bitfld.long 0x00 3. "  SPIS195 ,SPI Status Bit 195" "Low,High"
bitfld.long 0x00 2. "  SPIS194 ,SPI Status Bit 194" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High"
bitfld.long 0x00 0. "  SPIS192 ,SPI Status Bit 192" "Low,High"
else
hgroup.long 0xC098++0x03
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
rgroup.long 0xC09C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High"
bitfld.long 0x00 30. "  SPIS254 ,SPI Status Bit 254" "Low,High"
bitfld.long 0x00 29. "  SPIS253 ,SPI Status Bit 253" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High"
bitfld.long 0x00 27. "  SPIS251 ,SPI Status Bit 251" "Low,High"
bitfld.long 0x00 26. "  SPIS250 ,SPI Status Bit 250" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High"
bitfld.long 0x00 24. "  SPIS248 ,SPI Status Bit 248" "Low,High"
bitfld.long 0x00 23. "  SPIS247 ,SPI Status Bit 247" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High"
bitfld.long 0x00 21. "  SPIS245 ,SPI Status Bit 245" "Low,High"
bitfld.long 0x00 20. "  SPIS244 ,SPI Status Bit 244" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High"
bitfld.long 0x00 18. "  SPIS242 ,SPI Status Bit 242" "Low,High"
bitfld.long 0x00 17. "  SPIS241 ,SPI Status Bit 241" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High"
bitfld.long 0x00 15. "  SPIS239 ,SPI Status Bit 239" "Low,High"
bitfld.long 0x00 14. "  SPIS238 ,SPI Status Bit 238" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High"
bitfld.long 0x00 12. "  SPIS236 ,SPI Status Bit 236" "Low,High"
bitfld.long 0x00 11. "  SPIS235 ,SPI Status Bit 235" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High"
bitfld.long 0x00 9. "  SPIS233 ,SPI Status Bit 233" "Low,High"
bitfld.long 0x00 8. "  SPIS232 ,SPI Status Bit 232" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High"
bitfld.long 0x00 6. "  SPIS230 ,SPI Status Bit 230" "Low,High"
bitfld.long 0x00 5. "  SPIS229 ,SPI Status Bit 229" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High"
bitfld.long 0x00 3. "  SPIS227 ,SPI Status Bit 227" "Low,High"
bitfld.long 0x00 2. "  SPIS226 ,SPI Status Bit 226" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High"
bitfld.long 0x00 0. "  SPIS224 ,SPI Status Bit 224" "Low,High"
else
hgroup.long 0xC09C++0x03
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
rgroup.long 0xC0A0++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High"
bitfld.long 0x00 30. "  SPIS286 ,SPI Status Bit 286" "Low,High"
bitfld.long 0x00 29. "  SPIS285 ,SPI Status Bit 285" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High"
bitfld.long 0x00 27. "  SPIS283 ,SPI Status Bit 283" "Low,High"
bitfld.long 0x00 26. "  SPIS282 ,SPI Status Bit 282" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High"
bitfld.long 0x00 24. "  SPIS280 ,SPI Status Bit 280" "Low,High"
bitfld.long 0x00 23. "  SPIS279 ,SPI Status Bit 279" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High"
bitfld.long 0x00 21. "  SPIS277 ,SPI Status Bit 277" "Low,High"
bitfld.long 0x00 20. "  SPIS276 ,SPI Status Bit 276" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High"
bitfld.long 0x00 18. "  SPIS274 ,SPI Status Bit 274" "Low,High"
bitfld.long 0x00 17. "  SPIS273 ,SPI Status Bit 273" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High"
bitfld.long 0x00 15. "  SPIS271 ,SPI Status Bit 271" "Low,High"
bitfld.long 0x00 14. "  SPIS270 ,SPI Status Bit 270" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High"
bitfld.long 0x00 12. "  SPIS268 ,SPI Status Bit 268" "Low,High"
bitfld.long 0x00 11. "  SPIS267 ,SPI Status Bit 267" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High"
bitfld.long 0x00 9. "  SPIS265 ,SPI Status Bit 265" "Low,High"
bitfld.long 0x00 8. "  SPIS264 ,SPI Status Bit 264" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High"
bitfld.long 0x00 6. "  SPIS262 ,SPI Status Bit 262" "Low,High"
bitfld.long 0x00 5. "  SPIS261 ,SPI Status Bit 261" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High"
bitfld.long 0x00 3. "  SPIS259 ,SPI Status Bit 259" "Low,High"
bitfld.long 0x00 2. "  SPIS258 ,SPI Status Bit 258" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High"
bitfld.long 0x00 0. "  SPIS256 ,SPI Status Bit 256" "Low,High"
else
hgroup.long 0xC0A0++0x03
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
rgroup.long 0xC0A4++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High"
bitfld.long 0x00 30. "  SPIS318 ,SPI Status Bit 318" "Low,High"
bitfld.long 0x00 29. "  SPIS317 ,SPI Status Bit 317" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High"
bitfld.long 0x00 27. "  SPIS315 ,SPI Status Bit 315" "Low,High"
bitfld.long 0x00 26. "  SPIS314 ,SPI Status Bit 314" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High"
bitfld.long 0x00 24. "  SPIS312 ,SPI Status Bit 312" "Low,High"
bitfld.long 0x00 23. "  SPIS311 ,SPI Status Bit 311" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High"
bitfld.long 0x00 21. "  SPIS309 ,SPI Status Bit 309" "Low,High"
bitfld.long 0x00 20. "  SPIS308 ,SPI Status Bit 308" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High"
bitfld.long 0x00 18. "  SPIS306 ,SPI Status Bit 306" "Low,High"
bitfld.long 0x00 17. "  SPIS305 ,SPI Status Bit 305" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High"
bitfld.long 0x00 15. "  SPIS303 ,SPI Status Bit 303" "Low,High"
bitfld.long 0x00 14. "  SPIS302 ,SPI Status Bit 302" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High"
bitfld.long 0x00 12. "  SPIS300 ,SPI Status Bit 300" "Low,High"
bitfld.long 0x00 11. "  SPIS299 ,SPI Status Bit 299" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High"
bitfld.long 0x00 9. "  SPIS297 ,SPI Status Bit 297" "Low,High"
bitfld.long 0x00 8. "  SPIS296 ,SPI Status Bit 296" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High"
bitfld.long 0x00 6. "  SPIS294 ,SPI Status Bit 294" "Low,High"
bitfld.long 0x00 5. "  SPIS293 ,SPI Status Bit 293" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High"
bitfld.long 0x00 3. "  SPIS291 ,SPI Status Bit 291" "Low,High"
bitfld.long 0x00 2. "  SPIS290 ,SPI Status Bit 290" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High"
bitfld.long 0x00 0. "  SPIS288 ,SPI Status Bit 288" "Low,High"
else
hgroup.long 0xC0A4++0x03
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
rgroup.long 0xC0A8++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High"
bitfld.long 0x00 30. "  SPIS350 ,SPI Status Bit 350" "Low,High"
bitfld.long 0x00 29. "  SPIS349 ,SPI Status Bit 349" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High"
bitfld.long 0x00 27. "  SPIS347 ,SPI Status Bit 347" "Low,High"
bitfld.long 0x00 26. "  SPIS346 ,SPI Status Bit 346" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High"
bitfld.long 0x00 24. "  SPIS344 ,SPI Status Bit 344" "Low,High"
bitfld.long 0x00 23. "  SPIS343 ,SPI Status Bit 343" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High"
bitfld.long 0x00 21. "  SPIS341 ,SPI Status Bit 341" "Low,High"
bitfld.long 0x00 20. "  SPIS340 ,SPI Status Bit 340" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High"
bitfld.long 0x00 18. "  SPIS338 ,SPI Status Bit 338" "Low,High"
bitfld.long 0x00 17. "  SPIS337 ,SPI Status Bit 337" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High"
bitfld.long 0x00 15. "  SPIS335 ,SPI Status Bit 335" "Low,High"
bitfld.long 0x00 14. "  SPIS334 ,SPI Status Bit 334" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High"
bitfld.long 0x00 12. "  SPIS332 ,SPI Status Bit 332" "Low,High"
bitfld.long 0x00 11. "  SPIS331 ,SPI Status Bit 331" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High"
bitfld.long 0x00 9. "  SPIS329 ,SPI Status Bit 329" "Low,High"
bitfld.long 0x00 8. "  SPIS328 ,SPI Status Bit 328" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High"
bitfld.long 0x00 6. "  SPIS326 ,SPI Status Bit 326" "Low,High"
bitfld.long 0x00 5. "  SPIS325 ,SPI Status Bit 325" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High"
bitfld.long 0x00 3. "  SPIS323 ,SPI Status Bit 323" "Low,High"
bitfld.long 0x00 2. "  SPIS322 ,SPI Status Bit 322" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High"
bitfld.long 0x00 0. "  SPIS320 ,SPI Status Bit 320" "Low,High"
else
hgroup.long 0xC0A8++0x03
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
rgroup.long 0xC0AC++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High"
bitfld.long 0x00 30. "  SPIS382 ,SPI Status Bit 382" "Low,High"
bitfld.long 0x00 29. "  SPIS381 ,SPI Status Bit 381" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High"
bitfld.long 0x00 27. "  SPIS379 ,SPI Status Bit 379" "Low,High"
bitfld.long 0x00 26. "  SPIS378 ,SPI Status Bit 378" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High"
bitfld.long 0x00 24. "  SPIS376 ,SPI Status Bit 376" "Low,High"
bitfld.long 0x00 23. "  SPIS375 ,SPI Status Bit 375" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High"
bitfld.long 0x00 21. "  SPIS373 ,SPI Status Bit 373" "Low,High"
bitfld.long 0x00 20. "  SPIS372 ,SPI Status Bit 372" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High"
bitfld.long 0x00 18. "  SPIS370 ,SPI Status Bit 370" "Low,High"
bitfld.long 0x00 17. "  SPIS369 ,SPI Status Bit 369" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High"
bitfld.long 0x00 15. "  SPIS367 ,SPI Status Bit 367" "Low,High"
bitfld.long 0x00 14. "  SPIS366 ,SPI Status Bit 366" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High"
bitfld.long 0x00 12. "  SPIS364 ,SPI Status Bit 364" "Low,High"
bitfld.long 0x00 11. "  SPIS363 ,SPI Status Bit 363" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High"
bitfld.long 0x00 9. "  SPIS361 ,SPI Status Bit 361" "Low,High"
bitfld.long 0x00 8. "  SPIS360 ,SPI Status Bit 360" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High"
bitfld.long 0x00 6. "  SPIS358 ,SPI Status Bit 358" "Low,High"
bitfld.long 0x00 5. "  SPIS357 ,SPI Status Bit 357" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High"
bitfld.long 0x00 3. "  SPIS355 ,SPI Status Bit 355" "Low,High"
bitfld.long 0x00 2. "  SPIS354 ,SPI Status Bit 354" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High"
bitfld.long 0x00 0. "  SPIS352 ,SPI Status Bit 352" "Low,High"
else
hgroup.long 0xC0AC++0x03
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
rgroup.long 0xC0B0++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High"
bitfld.long 0x00 30. "  SPIS414 ,SPI Status Bit 414" "Low,High"
bitfld.long 0x00 29. "  SPIS413 ,SPI Status Bit 413" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High"
bitfld.long 0x00 27. "  SPIS411 ,SPI Status Bit 411" "Low,High"
bitfld.long 0x00 26. "  SPIS410 ,SPI Status Bit 410" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High"
bitfld.long 0x00 24. "  SPIS408 ,SPI Status Bit 408" "Low,High"
bitfld.long 0x00 23. "  SPIS407 ,SPI Status Bit 407" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High"
bitfld.long 0x00 21. "  SPIS405 ,SPI Status Bit 405" "Low,High"
bitfld.long 0x00 20. "  SPIS404 ,SPI Status Bit 404" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High"
bitfld.long 0x00 18. "  SPIS402 ,SPI Status Bit 402" "Low,High"
bitfld.long 0x00 17. "  SPIS401 ,SPI Status Bit 401" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High"
bitfld.long 0x00 15. "  SPIS399 ,SPI Status Bit 399" "Low,High"
bitfld.long 0x00 14. "  SPIS398 ,SPI Status Bit 398" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High"
bitfld.long 0x00 12. "  SPIS396 ,SPI Status Bit 396" "Low,High"
bitfld.long 0x00 11. "  SPIS395 ,SPI Status Bit 395" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High"
bitfld.long 0x00 9. "  SPIS393 ,SPI Status Bit 393" "Low,High"
bitfld.long 0x00 8. "  SPIS392 ,SPI Status Bit 392" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High"
bitfld.long 0x00 6. "  SPIS390 ,SPI Status Bit 390" "Low,High"
bitfld.long 0x00 5. "  SPIS389 ,SPI Status Bit 389" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High"
bitfld.long 0x00 3. "  SPIS387 ,SPI Status Bit 387" "Low,High"
bitfld.long 0x00 2. "  SPIS386 ,SPI Status Bit 386" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High"
bitfld.long 0x00 0. "  SPIS384 ,SPI Status Bit 384" "Low,High"
else
hgroup.long 0xC0B0++0x03
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
rgroup.long 0xC0B4++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High"
bitfld.long 0x00 30. "  SPIS446 ,SPI Status Bit 446" "Low,High"
bitfld.long 0x00 29. "  SPIS445 ,SPI Status Bit 445" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High"
bitfld.long 0x00 27. "  SPIS443 ,SPI Status Bit 443" "Low,High"
bitfld.long 0x00 26. "  SPIS442 ,SPI Status Bit 442" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High"
bitfld.long 0x00 24. "  SPIS440 ,SPI Status Bit 440" "Low,High"
bitfld.long 0x00 23. "  SPIS439 ,SPI Status Bit 439" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High"
bitfld.long 0x00 21. "  SPIS437 ,SPI Status Bit 437" "Low,High"
bitfld.long 0x00 20. "  SPIS436 ,SPI Status Bit 436" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High"
bitfld.long 0x00 18. "  SPIS434 ,SPI Status Bit 434" "Low,High"
bitfld.long 0x00 17. "  SPIS433 ,SPI Status Bit 433" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High"
bitfld.long 0x00 15. "  SPIS431 ,SPI Status Bit 431" "Low,High"
bitfld.long 0x00 14. "  SPIS430 ,SPI Status Bit 430" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High"
bitfld.long 0x00 12. "  SPIS428 ,SPI Status Bit 428" "Low,High"
bitfld.long 0x00 11. "  SPIS427 ,SPI Status Bit 427" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High"
bitfld.long 0x00 9. "  SPIS425 ,SPI Status Bit 425" "Low,High"
bitfld.long 0x00 8. "  SPIS424 ,SPI Status Bit 424" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High"
bitfld.long 0x00 6. "  SPIS422 ,SPI Status Bit 422" "Low,High"
bitfld.long 0x00 5. "  SPIS421 ,SPI Status Bit 421" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High"
bitfld.long 0x00 3. "  SPIS419 ,SPI Status Bit 419" "Low,High"
bitfld.long 0x00 2. "  SPIS418 ,SPI Status Bit 418" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High"
bitfld.long 0x00 0. "  SPIS416 ,SPI Status Bit 416" "Low,High"
else
hgroup.long 0xC0B4++0x03
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
rgroup.long 0xC0B8++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High"
bitfld.long 0x00 30. "  SPIS478 ,SPI Status Bit 478" "Low,High"
bitfld.long 0x00 29. "  SPIS477 ,SPI Status Bit 477" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High"
bitfld.long 0x00 27. "  SPIS475 ,SPI Status Bit 475" "Low,High"
bitfld.long 0x00 26. "  SPIS474 ,SPI Status Bit 474" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High"
bitfld.long 0x00 24. "  SPIS472 ,SPI Status Bit 472" "Low,High"
bitfld.long 0x00 23. "  SPIS471 ,SPI Status Bit 471" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High"
bitfld.long 0x00 21. "  SPIS469 ,SPI Status Bit 469" "Low,High"
bitfld.long 0x00 20. "  SPIS468 ,SPI Status Bit 468" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High"
bitfld.long 0x00 18. "  SPIS466 ,SPI Status Bit 466" "Low,High"
bitfld.long 0x00 17. "  SPIS465 ,SPI Status Bit 465" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High"
bitfld.long 0x00 15. "  SPIS463 ,SPI Status Bit 463" "Low,High"
bitfld.long 0x00 14. "  SPIS462 ,SPI Status Bit 462" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High"
bitfld.long 0x00 12. "  SPIS460 ,SPI Status Bit 460" "Low,High"
bitfld.long 0x00 11. "  SPIS459 ,SPI Status Bit 459" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High"
bitfld.long 0x00 9. "  SPIS457 ,SPI Status Bit 457" "Low,High"
bitfld.long 0x00 8. "  SPIS456 ,SPI Status Bit 456" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High"
bitfld.long 0x00 6. "  SPIS454 ,SPI Status Bit 454" "Low,High"
bitfld.long 0x00 5. "  SPIS453 ,SPI Status Bit 453" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High"
bitfld.long 0x00 3. "  SPIS451 ,SPI Status Bit 451" "Low,High"
bitfld.long 0x00 2. "  SPIS450 ,SPI Status Bit 450" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High"
bitfld.long 0x00 0. "  SPIS448 ,SPI Status Bit 448" "Low,High"
else
hgroup.long 0xC0B8++0x03
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
rgroup.long 0xC0BC++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High"
bitfld.long 0x00 30. "  SPIS510 ,SPI Status Bit 510" "Low,High"
bitfld.long 0x00 29. "  SPIS509 ,SPI Status Bit 509" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High"
bitfld.long 0x00 27. "  SPIS507 ,SPI Status Bit 507" "Low,High"
bitfld.long 0x00 26. "  SPIS506 ,SPI Status Bit 506" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High"
bitfld.long 0x00 24. "  SPIS504 ,SPI Status Bit 504" "Low,High"
bitfld.long 0x00 23. "  SPIS503 ,SPI Status Bit 503" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High"
bitfld.long 0x00 21. "  SPIS501 ,SPI Status Bit 501" "Low,High"
bitfld.long 0x00 20. "  SPIS500 ,SPI Status Bit 500" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High"
bitfld.long 0x00 18. "  SPIS498 ,SPI Status Bit 498" "Low,High"
bitfld.long 0x00 17. "  SPIS497 ,SPI Status Bit 497" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High"
bitfld.long 0x00 15. "  SPIS495 ,SPI Status Bit 495" "Low,High"
bitfld.long 0x00 14. "  SPIS494 ,SPI Status Bit 494" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High"
bitfld.long 0x00 12. "  SPIS492 ,SPI Status Bit 492" "Low,High"
bitfld.long 0x00 11. "  SPIS491 ,SPI Status Bit 491" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High"
bitfld.long 0x00 9. "  SPIS489 ,SPI Status Bit 489" "Low,High"
bitfld.long 0x00 8. "  SPIS488 ,SPI Status Bit 488" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High"
bitfld.long 0x00 6. "  SPIS486 ,SPI Status Bit 486" "Low,High"
bitfld.long 0x00 5. "  SPIS485 ,SPI Status Bit 485" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High"
bitfld.long 0x00 3. "  SPIS483 ,SPI Status Bit 483" "Low,High"
bitfld.long 0x00 2. "  SPIS482 ,SPI Status Bit 482" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High"
bitfld.long 0x00 0. "  SPIS480 ,SPI Status Bit 480" "Low,High"
else
hgroup.long 0xC0BC++0x03
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
rgroup.long 0xC0C0++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High"
bitfld.long 0x00 30. "  SPIS542 ,SPI Status Bit 542" "Low,High"
bitfld.long 0x00 29. "  SPIS541 ,SPI Status Bit 541" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High"
bitfld.long 0x00 27. "  SPIS539 ,SPI Status Bit 539" "Low,High"
bitfld.long 0x00 26. "  SPIS538 ,SPI Status Bit 538" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High"
bitfld.long 0x00 24. "  SPIS536 ,SPI Status Bit 536" "Low,High"
bitfld.long 0x00 23. "  SPIS535 ,SPI Status Bit 535" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High"
bitfld.long 0x00 21. "  SPIS533 ,SPI Status Bit 533" "Low,High"
bitfld.long 0x00 20. "  SPIS532 ,SPI Status Bit 532" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High"
bitfld.long 0x00 18. "  SPIS530 ,SPI Status Bit 530" "Low,High"
bitfld.long 0x00 17. "  SPIS529 ,SPI Status Bit 529" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High"
bitfld.long 0x00 15. "  SPIS527 ,SPI Status Bit 527" "Low,High"
bitfld.long 0x00 14. "  SPIS526 ,SPI Status Bit 526" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High"
bitfld.long 0x00 12. "  SPIS524 ,SPI Status Bit 524" "Low,High"
bitfld.long 0x00 11. "  SPIS523 ,SPI Status Bit 523" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High"
bitfld.long 0x00 9. "  SPIS521 ,SPI Status Bit 521" "Low,High"
bitfld.long 0x00 8. "  SPIS520 ,SPI Status Bit 520" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High"
bitfld.long 0x00 6. "  SPIS518 ,SPI Status Bit 518" "Low,High"
bitfld.long 0x00 5. "  SPIS517 ,SPI Status Bit 517" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High"
bitfld.long 0x00 3. "  SPIS515 ,SPI Status Bit 515" "Low,High"
bitfld.long 0x00 2. "  SPIS514 ,SPI Status Bit 514" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High"
bitfld.long 0x00 0. "  SPIS512 ,SPI Status Bit 512" "Low,High"
else
hgroup.long 0xC0C0++0x03
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
rgroup.long 0xC0C4++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High"
bitfld.long 0x00 30. "  SPIS574 ,SPI Status Bit 574" "Low,High"
bitfld.long 0x00 29. "  SPIS573 ,SPI Status Bit 573" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High"
bitfld.long 0x00 27. "  SPIS571 ,SPI Status Bit 571" "Low,High"
bitfld.long 0x00 26. "  SPIS570 ,SPI Status Bit 570" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High"
bitfld.long 0x00 24. "  SPIS568 ,SPI Status Bit 568" "Low,High"
bitfld.long 0x00 23. "  SPIS567 ,SPI Status Bit 567" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High"
bitfld.long 0x00 21. "  SPIS565 ,SPI Status Bit 565" "Low,High"
bitfld.long 0x00 20. "  SPIS564 ,SPI Status Bit 564" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High"
bitfld.long 0x00 18. "  SPIS562 ,SPI Status Bit 562" "Low,High"
bitfld.long 0x00 17. "  SPIS561 ,SPI Status Bit 561" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High"
bitfld.long 0x00 15. "  SPIS559 ,SPI Status Bit 559" "Low,High"
bitfld.long 0x00 14. "  SPIS558 ,SPI Status Bit 558" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High"
bitfld.long 0x00 12. "  SPIS556 ,SPI Status Bit 556" "Low,High"
bitfld.long 0x00 11. "  SPIS555 ,SPI Status Bit 555" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High"
bitfld.long 0x00 9. "  SPIS553 ,SPI Status Bit 553" "Low,High"
bitfld.long 0x00 8. "  SPIS552 ,SPI Status Bit 552" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High"
bitfld.long 0x00 6. "  SPIS550 ,SPI Status Bit 550" "Low,High"
bitfld.long 0x00 5. "  SPIS549 ,SPI Status Bit 549" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High"
bitfld.long 0x00 3. "  SPIS547 ,SPI Status Bit 547" "Low,High"
bitfld.long 0x00 2. "  SPIS546 ,SPI Status Bit 546" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High"
bitfld.long 0x00 0. "  SPIS544 ,SPI Status Bit 544" "Low,High"
else
hgroup.long 0xC0C4++0x03
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
rgroup.long 0xC0C8++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High"
bitfld.long 0x00 30. "  SPIS606 ,SPI Status Bit 606" "Low,High"
bitfld.long 0x00 29. "  SPIS605 ,SPI Status Bit 605" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High"
bitfld.long 0x00 27. "  SPIS603 ,SPI Status Bit 603" "Low,High"
bitfld.long 0x00 26. "  SPIS602 ,SPI Status Bit 602" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High"
bitfld.long 0x00 24. "  SPIS600 ,SPI Status Bit 600" "Low,High"
bitfld.long 0x00 23. "  SPIS599 ,SPI Status Bit 599" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High"
bitfld.long 0x00 21. "  SPIS597 ,SPI Status Bit 597" "Low,High"
bitfld.long 0x00 20. "  SPIS596 ,SPI Status Bit 596" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High"
bitfld.long 0x00 18. "  SPIS594 ,SPI Status Bit 594" "Low,High"
bitfld.long 0x00 17. "  SPIS593 ,SPI Status Bit 593" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High"
bitfld.long 0x00 15. "  SPIS591 ,SPI Status Bit 591" "Low,High"
bitfld.long 0x00 14. "  SPIS590 ,SPI Status Bit 590" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High"
bitfld.long 0x00 12. "  SPIS588 ,SPI Status Bit 588" "Low,High"
bitfld.long 0x00 11. "  SPIS587 ,SPI Status Bit 587" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High"
bitfld.long 0x00 9. "  SPIS585 ,SPI Status Bit 585" "Low,High"
bitfld.long 0x00 8. "  SPIS584 ,SPI Status Bit 584" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High"
bitfld.long 0x00 6. "  SPIS582 ,SPI Status Bit 582" "Low,High"
bitfld.long 0x00 5. "  SPIS581 ,SPI Status Bit 581" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High"
bitfld.long 0x00 3. "  SPIS579 ,SPI Status Bit 579" "Low,High"
bitfld.long 0x00 2. "  SPIS578 ,SPI Status Bit 578" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High"
bitfld.long 0x00 0. "  SPIS576 ,SPI Status Bit 576" "Low,High"
else
hgroup.long 0xC0C8++0x03
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
rgroup.long 0xC0CC++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High"
bitfld.long 0x00 30. "  SPIS638 ,SPI Status Bit 638" "Low,High"
bitfld.long 0x00 29. "  SPIS637 ,SPI Status Bit 637" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High"
bitfld.long 0x00 27. "  SPIS635 ,SPI Status Bit 635" "Low,High"
bitfld.long 0x00 26. "  SPIS634 ,SPI Status Bit 634" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High"
bitfld.long 0x00 24. "  SPIS632 ,SPI Status Bit 632" "Low,High"
bitfld.long 0x00 23. "  SPIS631 ,SPI Status Bit 631" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High"
bitfld.long 0x00 21. "  SPIS629 ,SPI Status Bit 629" "Low,High"
bitfld.long 0x00 20. "  SPIS628 ,SPI Status Bit 628" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High"
bitfld.long 0x00 18. "  SPIS626 ,SPI Status Bit 626" "Low,High"
bitfld.long 0x00 17. "  SPIS625 ,SPI Status Bit 625" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High"
bitfld.long 0x00 15. "  SPIS623 ,SPI Status Bit 623" "Low,High"
bitfld.long 0x00 14. "  SPIS622 ,SPI Status Bit 622" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High"
bitfld.long 0x00 12. "  SPIS620 ,SPI Status Bit 620" "Low,High"
bitfld.long 0x00 11. "  SPIS619 ,SPI Status Bit 619" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High"
bitfld.long 0x00 9. "  SPIS617 ,SPI Status Bit 617" "Low,High"
bitfld.long 0x00 8. "  SPIS616 ,SPI Status Bit 616" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High"
bitfld.long 0x00 6. "  SPIS614 ,SPI Status Bit 614" "Low,High"
bitfld.long 0x00 5. "  SPIS613 ,SPI Status Bit 613" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High"
bitfld.long 0x00 3. "  SPIS611 ,SPI Status Bit 611" "Low,High"
bitfld.long 0x00 2. "  SPIS610 ,SPI Status Bit 610" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High"
bitfld.long 0x00 0. "  SPIS608 ,SPI Status Bit 608" "Low,High"
else
hgroup.long 0xC0CC++0x03
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
rgroup.long 0xC0D0++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High"
bitfld.long 0x00 30. "  SPIS670 ,SPI Status Bit 670" "Low,High"
bitfld.long 0x00 29. "  SPIS669 ,SPI Status Bit 669" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High"
bitfld.long 0x00 27. "  SPIS667 ,SPI Status Bit 667" "Low,High"
bitfld.long 0x00 26. "  SPIS666 ,SPI Status Bit 666" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High"
bitfld.long 0x00 24. "  SPIS664 ,SPI Status Bit 664" "Low,High"
bitfld.long 0x00 23. "  SPIS663 ,SPI Status Bit 663" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High"
bitfld.long 0x00 21. "  SPIS661 ,SPI Status Bit 661" "Low,High"
bitfld.long 0x00 20. "  SPIS660 ,SPI Status Bit 660" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High"
bitfld.long 0x00 18. "  SPIS658 ,SPI Status Bit 658" "Low,High"
bitfld.long 0x00 17. "  SPIS657 ,SPI Status Bit 657" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High"
bitfld.long 0x00 15. "  SPIS655 ,SPI Status Bit 655" "Low,High"
bitfld.long 0x00 14. "  SPIS654 ,SPI Status Bit 654" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High"
bitfld.long 0x00 12. "  SPIS652 ,SPI Status Bit 652" "Low,High"
bitfld.long 0x00 11. "  SPIS651 ,SPI Status Bit 651" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High"
bitfld.long 0x00 9. "  SPIS649 ,SPI Status Bit 649" "Low,High"
bitfld.long 0x00 8. "  SPIS648 ,SPI Status Bit 648" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High"
bitfld.long 0x00 6. "  SPIS646 ,SPI Status Bit 646" "Low,High"
bitfld.long 0x00 5. "  SPIS645 ,SPI Status Bit 645" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High"
bitfld.long 0x00 3. "  SPIS643 ,SPI Status Bit 643" "Low,High"
bitfld.long 0x00 2. "  SPIS642 ,SPI Status Bit 642" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High"
bitfld.long 0x00 0. "  SPIS640 ,SPI Status Bit 640" "Low,High"
else
hgroup.long 0xC0D0++0x03
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
rgroup.long 0xC0D4++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High"
bitfld.long 0x00 30. "  SPIS702 ,SPI Status Bit 702" "Low,High"
bitfld.long 0x00 29. "  SPIS701 ,SPI Status Bit 701" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High"
bitfld.long 0x00 27. "  SPIS699 ,SPI Status Bit 699" "Low,High"
bitfld.long 0x00 26. "  SPIS698 ,SPI Status Bit 698" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High"
bitfld.long 0x00 24. "  SPIS696 ,SPI Status Bit 696" "Low,High"
bitfld.long 0x00 23. "  SPIS695 ,SPI Status Bit 695" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High"
bitfld.long 0x00 21. "  SPIS693 ,SPI Status Bit 693" "Low,High"
bitfld.long 0x00 20. "  SPIS692 ,SPI Status Bit 692" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High"
bitfld.long 0x00 18. "  SPIS690 ,SPI Status Bit 690" "Low,High"
bitfld.long 0x00 17. "  SPIS689 ,SPI Status Bit 689" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High"
bitfld.long 0x00 15. "  SPIS687 ,SPI Status Bit 687" "Low,High"
bitfld.long 0x00 14. "  SPIS686 ,SPI Status Bit 686" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High"
bitfld.long 0x00 12. "  SPIS684 ,SPI Status Bit 684" "Low,High"
bitfld.long 0x00 11. "  SPIS683 ,SPI Status Bit 683" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High"
bitfld.long 0x00 9. "  SPIS681 ,SPI Status Bit 681" "Low,High"
bitfld.long 0x00 8. "  SPIS680 ,SPI Status Bit 680" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High"
bitfld.long 0x00 6. "  SPIS678 ,SPI Status Bit 678" "Low,High"
bitfld.long 0x00 5. "  SPIS677 ,SPI Status Bit 677" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High"
bitfld.long 0x00 3. "  SPIS675 ,SPI Status Bit 675" "Low,High"
bitfld.long 0x00 2. "  SPIS674 ,SPI Status Bit 674" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High"
bitfld.long 0x00 0. "  SPIS672 ,SPI Status Bit 672" "Low,High"
else
hgroup.long 0xC0D4++0x03
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
rgroup.long 0xC0D8++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High"
bitfld.long 0x00 30. "  SPIS734 ,SPI Status Bit 734" "Low,High"
bitfld.long 0x00 29. "  SPIS733 ,SPI Status Bit 733" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High"
bitfld.long 0x00 27. "  SPIS731 ,SPI Status Bit 731" "Low,High"
bitfld.long 0x00 26. "  SPIS730 ,SPI Status Bit 730" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High"
bitfld.long 0x00 24. "  SPIS728 ,SPI Status Bit 728" "Low,High"
bitfld.long 0x00 23. "  SPIS727 ,SPI Status Bit 727" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High"
bitfld.long 0x00 21. "  SPIS725 ,SPI Status Bit 725" "Low,High"
bitfld.long 0x00 20. "  SPIS724 ,SPI Status Bit 724" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High"
bitfld.long 0x00 18. "  SPIS722 ,SPI Status Bit 722" "Low,High"
bitfld.long 0x00 17. "  SPIS721 ,SPI Status Bit 721" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High"
bitfld.long 0x00 15. "  SPIS719 ,SPI Status Bit 719" "Low,High"
bitfld.long 0x00 14. "  SPIS718 ,SPI Status Bit 718" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High"
bitfld.long 0x00 12. "  SPIS716 ,SPI Status Bit 716" "Low,High"
bitfld.long 0x00 11. "  SPIS715 ,SPI Status Bit 715" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High"
bitfld.long 0x00 9. "  SPIS713 ,SPI Status Bit 713" "Low,High"
bitfld.long 0x00 8. "  SPIS712 ,SPI Status Bit 712" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High"
bitfld.long 0x00 6. "  SPIS710 ,SPI Status Bit 710" "Low,High"
bitfld.long 0x00 5. "  SPIS709 ,SPI Status Bit 709" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High"
bitfld.long 0x00 3. "  SPIS707 ,SPI Status Bit 707" "Low,High"
bitfld.long 0x00 2. "  SPIS706 ,SPI Status Bit 706" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High"
bitfld.long 0x00 0. "  SPIS704 ,SPI Status Bit 704" "Low,High"
else
hgroup.long 0xC0D8++0x03
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
rgroup.long 0xC0DC++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High"
bitfld.long 0x00 30. "  SPIS766 ,SPI Status Bit 766" "Low,High"
bitfld.long 0x00 29. "  SPIS765 ,SPI Status Bit 765" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High"
bitfld.long 0x00 27. "  SPIS763 ,SPI Status Bit 763" "Low,High"
bitfld.long 0x00 26. "  SPIS762 ,SPI Status Bit 762" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High"
bitfld.long 0x00 24. "  SPIS760 ,SPI Status Bit 760" "Low,High"
bitfld.long 0x00 23. "  SPIS759 ,SPI Status Bit 759" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High"
bitfld.long 0x00 21. "  SPIS757 ,SPI Status Bit 757" "Low,High"
bitfld.long 0x00 20. "  SPIS756 ,SPI Status Bit 756" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High"
bitfld.long 0x00 18. "  SPIS754 ,SPI Status Bit 754" "Low,High"
bitfld.long 0x00 17. "  SPIS753 ,SPI Status Bit 753" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High"
bitfld.long 0x00 15. "  SPIS751 ,SPI Status Bit 751" "Low,High"
bitfld.long 0x00 14. "  SPIS750 ,SPI Status Bit 750" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High"
bitfld.long 0x00 12. "  SPIS748 ,SPI Status Bit 748" "Low,High"
bitfld.long 0x00 11. "  SPIS747 ,SPI Status Bit 747" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High"
bitfld.long 0x00 9. "  SPIS745 ,SPI Status Bit 745" "Low,High"
bitfld.long 0x00 8. "  SPIS744 ,SPI Status Bit 744" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High"
bitfld.long 0x00 6. "  SPIS742 ,SPI Status Bit 742" "Low,High"
bitfld.long 0x00 5. "  SPIS741 ,SPI Status Bit 741" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High"
bitfld.long 0x00 3. "  SPIS739 ,SPI Status Bit 739" "Low,High"
bitfld.long 0x00 2. "  SPIS738 ,SPI Status Bit 738" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High"
bitfld.long 0x00 0. "  SPIS736 ,SPI Status Bit 736" "Low,High"
else
hgroup.long 0xC0DC++0x03
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
rgroup.long 0xC0E0++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High"
bitfld.long 0x00 30. "  SPIS798 ,SPI Status Bit 798" "Low,High"
bitfld.long 0x00 29. "  SPIS797 ,SPI Status Bit 797" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High"
bitfld.long 0x00 27. "  SPIS795 ,SPI Status Bit 795" "Low,High"
bitfld.long 0x00 26. "  SPIS794 ,SPI Status Bit 794" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High"
bitfld.long 0x00 24. "  SPIS792 ,SPI Status Bit 792" "Low,High"
bitfld.long 0x00 23. "  SPIS791 ,SPI Status Bit 791" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High"
bitfld.long 0x00 21. "  SPIS789 ,SPI Status Bit 789" "Low,High"
bitfld.long 0x00 20. "  SPIS788 ,SPI Status Bit 788" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High"
bitfld.long 0x00 18. "  SPIS786 ,SPI Status Bit 786" "Low,High"
bitfld.long 0x00 17. "  SPIS785 ,SPI Status Bit 785" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High"
bitfld.long 0x00 15. "  SPIS783 ,SPI Status Bit 783" "Low,High"
bitfld.long 0x00 14. "  SPIS782 ,SPI Status Bit 782" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High"
bitfld.long 0x00 12. "  SPIS780 ,SPI Status Bit 780" "Low,High"
bitfld.long 0x00 11. "  SPIS779 ,SPI Status Bit 779" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High"
bitfld.long 0x00 9. "  SPIS777 ,SPI Status Bit 777" "Low,High"
bitfld.long 0x00 8. "  SPIS776 ,SPI Status Bit 776" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High"
bitfld.long 0x00 6. "  SPIS774 ,SPI Status Bit 774" "Low,High"
bitfld.long 0x00 5. "  SPIS773 ,SPI Status Bit 773" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High"
bitfld.long 0x00 3. "  SPIS771 ,SPI Status Bit 771" "Low,High"
bitfld.long 0x00 2. "  SPIS770 ,SPI Status Bit 770" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High"
bitfld.long 0x00 0. "  SPIS768 ,SPI Status Bit 768" "Low,High"
else
hgroup.long 0xC0E0++0x03
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
rgroup.long 0xC0E4++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High"
bitfld.long 0x00 30. "  SPIS830 ,SPI Status Bit 830" "Low,High"
bitfld.long 0x00 29. "  SPIS829 ,SPI Status Bit 829" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High"
bitfld.long 0x00 27. "  SPIS827 ,SPI Status Bit 827" "Low,High"
bitfld.long 0x00 26. "  SPIS826 ,SPI Status Bit 826" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High"
bitfld.long 0x00 24. "  SPIS824 ,SPI Status Bit 824" "Low,High"
bitfld.long 0x00 23. "  SPIS823 ,SPI Status Bit 823" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High"
bitfld.long 0x00 21. "  SPIS821 ,SPI Status Bit 821" "Low,High"
bitfld.long 0x00 20. "  SPIS820 ,SPI Status Bit 820" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High"
bitfld.long 0x00 18. "  SPIS818 ,SPI Status Bit 818" "Low,High"
bitfld.long 0x00 17. "  SPIS817 ,SPI Status Bit 817" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High"
bitfld.long 0x00 15. "  SPIS815 ,SPI Status Bit 815" "Low,High"
bitfld.long 0x00 14. "  SPIS814 ,SPI Status Bit 814" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High"
bitfld.long 0x00 12. "  SPIS812 ,SPI Status Bit 812" "Low,High"
bitfld.long 0x00 11. "  SPIS811 ,SPI Status Bit 811" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High"
bitfld.long 0x00 9. "  SPIS809 ,SPI Status Bit 809" "Low,High"
bitfld.long 0x00 8. "  SPIS808 ,SPI Status Bit 808" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High"
bitfld.long 0x00 6. "  SPIS806 ,SPI Status Bit 806" "Low,High"
bitfld.long 0x00 5. "  SPIS805 ,SPI Status Bit 805" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High"
bitfld.long 0x00 3. "  SPIS803 ,SPI Status Bit 803" "Low,High"
bitfld.long 0x00 2. "  SPIS802 ,SPI Status Bit 802" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High"
bitfld.long 0x00 0. "  SPIS800 ,SPI Status Bit 800" "Low,High"
else
hgroup.long 0xC0E4++0x03
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
rgroup.long 0xC0E8++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High"
bitfld.long 0x00 30. "  SPIS862 ,SPI Status Bit 862" "Low,High"
bitfld.long 0x00 29. "  SPIS861 ,SPI Status Bit 861" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High"
bitfld.long 0x00 27. "  SPIS859 ,SPI Status Bit 859" "Low,High"
bitfld.long 0x00 26. "  SPIS858 ,SPI Status Bit 858" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High"
bitfld.long 0x00 24. "  SPIS856 ,SPI Status Bit 856" "Low,High"
bitfld.long 0x00 23. "  SPIS855 ,SPI Status Bit 855" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High"
bitfld.long 0x00 21. "  SPIS853 ,SPI Status Bit 853" "Low,High"
bitfld.long 0x00 20. "  SPIS852 ,SPI Status Bit 852" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High"
bitfld.long 0x00 18. "  SPIS850 ,SPI Status Bit 850" "Low,High"
bitfld.long 0x00 17. "  SPIS849 ,SPI Status Bit 849" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High"
bitfld.long 0x00 15. "  SPIS847 ,SPI Status Bit 847" "Low,High"
bitfld.long 0x00 14. "  SPIS846 ,SPI Status Bit 846" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High"
bitfld.long 0x00 12. "  SPIS844 ,SPI Status Bit 844" "Low,High"
bitfld.long 0x00 11. "  SPIS843 ,SPI Status Bit 843" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High"
bitfld.long 0x00 9. "  SPIS841 ,SPI Status Bit 841" "Low,High"
bitfld.long 0x00 8. "  SPIS840 ,SPI Status Bit 840" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High"
bitfld.long 0x00 6. "  SPIS838 ,SPI Status Bit 838" "Low,High"
bitfld.long 0x00 5. "  SPIS837 ,SPI Status Bit 837" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High"
bitfld.long 0x00 3. "  SPIS835 ,SPI Status Bit 835" "Low,High"
bitfld.long 0x00 2. "  SPIS834 ,SPI Status Bit 834" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High"
bitfld.long 0x00 0. "  SPIS832 ,SPI Status Bit 832" "Low,High"
else
hgroup.long 0xC0E8++0x03
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
rgroup.long 0xC0EC++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High"
bitfld.long 0x00 30. "  SPIS894 ,SPI Status Bit 894" "Low,High"
bitfld.long 0x00 29. "  SPIS893 ,SPI Status Bit 893" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High"
bitfld.long 0x00 27. "  SPIS891 ,SPI Status Bit 891" "Low,High"
bitfld.long 0x00 26. "  SPIS890 ,SPI Status Bit 890" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High"
bitfld.long 0x00 24. "  SPIS888 ,SPI Status Bit 888" "Low,High"
bitfld.long 0x00 23. "  SPIS887 ,SPI Status Bit 887" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High"
bitfld.long 0x00 21. "  SPIS885 ,SPI Status Bit 885" "Low,High"
bitfld.long 0x00 20. "  SPIS884 ,SPI Status Bit 884" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High"
bitfld.long 0x00 18. "  SPIS882 ,SPI Status Bit 882" "Low,High"
bitfld.long 0x00 17. "  SPIS881 ,SPI Status Bit 881" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High"
bitfld.long 0x00 15. "  SPIS879 ,SPI Status Bit 879" "Low,High"
bitfld.long 0x00 14. "  SPIS878 ,SPI Status Bit 878" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High"
bitfld.long 0x00 12. "  SPIS876 ,SPI Status Bit 876" "Low,High"
bitfld.long 0x00 11. "  SPIS875 ,SPI Status Bit 875" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High"
bitfld.long 0x00 9. "  SPIS873 ,SPI Status Bit 873" "Low,High"
bitfld.long 0x00 8. "  SPIS872 ,SPI Status Bit 872" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High"
bitfld.long 0x00 6. "  SPIS870 ,SPI Status Bit 870" "Low,High"
bitfld.long 0x00 5. "  SPIS869 ,SPI Status Bit 869" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High"
bitfld.long 0x00 3. "  SPIS867 ,SPI Status Bit 867" "Low,High"
bitfld.long 0x00 2. "  SPIS866 ,SPI Status Bit 866" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High"
bitfld.long 0x00 0. "  SPIS864 ,SPI Status Bit 864" "Low,High"
else
hgroup.long 0xC0EC++0x03
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
rgroup.long 0xC0F0++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High"
bitfld.long 0x00 30. "  SPIS926 ,SPI Status Bit 926" "Low,High"
bitfld.long 0x00 29. "  SPIS925 ,SPI Status Bit 925" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High"
bitfld.long 0x00 27. "  SPIS923 ,SPI Status Bit 923" "Low,High"
bitfld.long 0x00 26. "  SPIS922 ,SPI Status Bit 922" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High"
bitfld.long 0x00 24. "  SPIS920 ,SPI Status Bit 920" "Low,High"
bitfld.long 0x00 23. "  SPIS919 ,SPI Status Bit 919" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High"
bitfld.long 0x00 21. "  SPIS917 ,SPI Status Bit 917" "Low,High"
bitfld.long 0x00 20. "  SPIS916 ,SPI Status Bit 916" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High"
bitfld.long 0x00 18. "  SPIS914 ,SPI Status Bit 914" "Low,High"
bitfld.long 0x00 17. "  SPIS913 ,SPI Status Bit 913" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High"
bitfld.long 0x00 15. "  SPIS911 ,SPI Status Bit 911" "Low,High"
bitfld.long 0x00 14. "  SPIS910 ,SPI Status Bit 910" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High"
bitfld.long 0x00 12. "  SPIS908 ,SPI Status Bit 908" "Low,High"
bitfld.long 0x00 11. "  SPIS907 ,SPI Status Bit 907" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High"
bitfld.long 0x00 9. "  SPIS905 ,SPI Status Bit 905" "Low,High"
bitfld.long 0x00 8. "  SPIS904 ,SPI Status Bit 904" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High"
bitfld.long 0x00 6. "  SPIS902 ,SPI Status Bit 902" "Low,High"
bitfld.long 0x00 5. "  SPIS901 ,SPI Status Bit 901" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High"
bitfld.long 0x00 3. "  SPIS899 ,SPI Status Bit 899" "Low,High"
bitfld.long 0x00 2. "  SPIS898 ,SPI Status Bit 898" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High"
bitfld.long 0x00 0. "  SPIS896 ,SPI Status Bit 896" "Low,High"
else
hgroup.long 0xC0F0++0x03
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
rgroup.long 0xC0F4++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High"
bitfld.long 0x00 30. "  SPIS958 ,SPI Status Bit 958" "Low,High"
bitfld.long 0x00 29. "  SPIS957 ,SPI Status Bit 957" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High"
bitfld.long 0x00 27. "  SPIS955 ,SPI Status Bit 955" "Low,High"
bitfld.long 0x00 26. "  SPIS954 ,SPI Status Bit 954" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High"
bitfld.long 0x00 24. "  SPIS952 ,SPI Status Bit 952" "Low,High"
bitfld.long 0x00 23. "  SPIS951 ,SPI Status Bit 951" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High"
bitfld.long 0x00 21. "  SPIS949 ,SPI Status Bit 949" "Low,High"
bitfld.long 0x00 20. "  SPIS948 ,SPI Status Bit 948" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High"
bitfld.long 0x00 18. "  SPIS946 ,SPI Status Bit 946" "Low,High"
bitfld.long 0x00 17. "  SPIS945 ,SPI Status Bit 945" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High"
bitfld.long 0x00 15. "  SPIS943 ,SPI Status Bit 943" "Low,High"
bitfld.long 0x00 14. "  SPIS942 ,SPI Status Bit 942" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High"
bitfld.long 0x00 12. "  SPIS940 ,SPI Status Bit 940" "Low,High"
bitfld.long 0x00 11. "  SPIS939 ,SPI Status Bit 939" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High"
bitfld.long 0x00 9. "  SPIS937 ,SPI Status Bit 937" "Low,High"
bitfld.long 0x00 8. "  SPIS936 ,SPI Status Bit 936" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High"
bitfld.long 0x00 6. "  SPIS934 ,SPI Status Bit 934" "Low,High"
bitfld.long 0x00 5. "  SPIS933 ,SPI Status Bit 933" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High"
bitfld.long 0x00 3. "  SPIS931 ,SPI Status Bit 931" "Low,High"
bitfld.long 0x00 2. "  SPIS930 ,SPI Status Bit 930" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High"
bitfld.long 0x00 0. "  SPIS928 ,SPI Status Bit 928" "Low,High"
else
hgroup.long 0xC0F4++0x03
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
rgroup.long 0xC0F8++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High"
bitfld.long 0x00 30. "  SPIS990 ,SPI Status Bit 990" "Low,High"
bitfld.long 0x00 29. "  SPIS989 ,SPI Status Bit 989" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High"
bitfld.long 0x00 27. "  SPIS987 ,SPI Status Bit 987" "Low,High"
bitfld.long 0x00 26. "  SPIS986 ,SPI Status Bit 986" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High"
bitfld.long 0x00 24. "  SPIS984 ,SPI Status Bit 984" "Low,High"
bitfld.long 0x00 23. "  SPIS983 ,SPI Status Bit 983" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High"
bitfld.long 0x00 21. "  SPIS981 ,SPI Status Bit 981" "Low,High"
bitfld.long 0x00 20. "  SPIS980 ,SPI Status Bit 980" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High"
bitfld.long 0x00 18. "  SPIS978 ,SPI Status Bit 978" "Low,High"
bitfld.long 0x00 17. "  SPIS977 ,SPI Status Bit 977" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High"
bitfld.long 0x00 15. "  SPIS975 ,SPI Status Bit 975" "Low,High"
bitfld.long 0x00 14. "  SPIS974 ,SPI Status Bit 974" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High"
bitfld.long 0x00 12. "  SPIS972 ,SPI Status Bit 972" "Low,High"
bitfld.long 0x00 11. "  SPIS971 ,SPI Status Bit 971" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High"
bitfld.long 0x00 9. "  SPIS969 ,SPI Status Bit 969" "Low,High"
bitfld.long 0x00 8. "  SPIS968 ,SPI Status Bit 968" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High"
bitfld.long 0x00 6. "  SPIS966 ,SPI Status Bit 966" "Low,High"
bitfld.long 0x00 5. "  SPIS965 ,SPI Status Bit 965" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High"
bitfld.long 0x00 3. "  SPIS963 ,SPI Status Bit 963" "Low,High"
bitfld.long 0x00 2. "  SPIS962 ,SPI Status Bit 962" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High"
bitfld.long 0x00 0. "  SPIS960 ,SPI Status Bit 960" "Low,High"
else
hgroup.long 0xC0F8++0x03
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
endif
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
base (COMP.BASE("GICD",-1.)+0x20000)
width 24.
tree "Interrupt Translation Service"
group.long 0x00++0x03
line.long 0x00 "GITS_CTLR,ITS Control Register"
rbitfld.long 0x00 31. "         QUIESCENT              ,Indicates completion of all ITS operations" "Not quiescent,Quiescent"
bitfld.long 0x00 0. "                      ENABLED                ,Controls whether the ITS is enabled" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID                 ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "                            VAR                    ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " REV                    ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                                 IMP                    ,Implementer"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 2. "                                 CCT                    ,Cumulative Collection Tables" "0,1"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.quad 0x00 2. " CCT                    ,Cumulative Collection Tables" "0,1"
else
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.quad 0x80++0x07
line.quad 0x00 "GITS_CBASER,The command queue control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated"
bitfld.quad 0x00 59.--61. "                      INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "    PHYSICAL_ADDRESS       ,Bits [51:12] of the base physical address of the command queue"
textline "                                         "
bitfld.quad 0x00 10.--11. " SHAREABILITY           ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                    SIZE                   ,The number of 4KB pages of physical memory allocated to the command queue minus one"
group.quad 0x88++0x7
line.quad 0x00 "GITS_CWRITER,The command queue write pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               RETRY                  ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted"
group.quad 0x90++0x07
line.quad 0x00 "GITS_CREADR,The command queue read pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               STALLED                ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00)
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
else
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                               SIZE                   ,The number of pages of physical memory allocated to the table minus one"
endif
textline "                                         "
wgroup.long 0xC000++0x03
line.long 0x00 "GITS_TRKCTLR,Tracking Control Register"
bitfld.long 0x00 1. "         LPI_TRACK              ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture"
bitfld.long 0x00 0. "  CACHE_COUNT_RESET      ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset"
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 6. "         PID_OUT_OF_RANGE       ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1"
bitfld.long 0x00 5. "          TARGET_OUT_OF_RANGE    ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1"
textline "                                 "
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 3. "         INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
bitfld.long 0x00 2. "          DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
textline "                                 "
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
else
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC008++0x03
line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
hexmask.long.tbyte 0x00 0.--19. 1. "         LPI_DID                ,The Device ID for the interrupt that was tracked"
else
hgroup.long 0xC008++0x03
hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC00C++0x03
line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_PID                ,The ID after translation for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC00C++0x03
hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC010++0x03
line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_ID                 ,The ID before translation of the interrupt that was tracked"
else
hgroup.long 0xC010++0x03
hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC014++0x03
line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
hexmask.long.byte 0x00 0.--6. 1. "         LPI_TARGET_CORE        ,The target core for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC014++0x03
hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
endif
rgroup.long 0xC018++0x03
line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         ITE_CACHE_HITS         ,Number of hits in the ITE cache"
hexmask.long.word 0x00 0.--15. 1. "       ITE_CACHE_MISSES       ,Number of misses in the ITE cache"
rgroup.long 0xC01C++0x03
line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         LPI_CACHE_HITS         ,Number of hits in the LPI cache"
hexmask.long.word 0x00 0.--15. 1. "       LPI_CACHE_MISSES       ,Number of misses in the LPI cache"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         PART_0                 ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. "         DES_1                  ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         PART_1                 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. "         ARCHREV                ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "   JEDEC                  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
textline "                                 "
bitfld.long 0x00 0.--2. "         DES_1                  ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. "         REVAND                 ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         CMOD                   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. "         SIZE                   ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         DES_2                  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GITS_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GITS_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GITS_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GITS_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
textline "                                 "
base (COMP.BASE("GICD",-1.)+0x20000)+0x10000
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01)
wgroup.long 0x40++0x03
line.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
else
hgroup.long 0x40++0x03
hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
endif
tree.end
width 0x0B
base COMP.BASE("GICR",-1.)
width 17.
tree "Redistributor Interface"
tree "Control Registers"
if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID    ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "           VAR            ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 12.--15. " REV       ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                IMP            ,Implementer"
rgroup.quad 0x0008++0x07
line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register"
hexmask.quad.byte 0x00 56.--63. 1. " AFF3      ,Affinity level 3 value for the Redistributor"
hexmask.quad.byte 0x00 48.--55. 1. "                AFF2           ,Affinity level 2 value for the Redistributor"
hexmask.quad.byte 0x00 40.--47. 1. "              AFF1             ,Affinity level 1 value for the Redistributor"
textline "                                  "
hexmask.quad.byte 0x00 32.--39. 1. " AFF0      ,Affinity level 0 value for the Redistributor"
bitfld.quad 0x00 24.--25. "                COMMONLPIAFF   ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1"
hexmask.quad.word 0x00 8.--23. 1. "  PROCESSOR_NUMBER ,A unique identifier for the PE"
textline "                                  "
bitfld.quad 0x00 5. " DPGS      ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported"
bitfld.quad 0x00 4. "     LAST           ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest"
bitfld.quad 0x00 3. "     DIRECTLPI        ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported"
textline "                                  "
bitfld.quad 0x00 0. " PLPIS     ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014))))
group.long 0x0014++0x03
line.long 0x00 "GICR_WAKER,Power Management Control Register"
bitfld.long 0x00 31. "         QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent"
bitfld.long 0x00 2. "     CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent"
bitfld.long 0x00 1. "   PROCESSORASLEEP  ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes"
textline "                                  "
bitfld.long 0x00 0. " SLEEP     ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes"
textline "                                  "
else
hgroup.long 0x0014++0x03
hide.long 0x00 "GICR_WAKER,Power Management Control Register"
endif
group.quad 0x070++0x07
line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register"
bitfld.quad 0x00 56.--58. " OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "  PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table"
textline "                                  "
bitfld.quad 0x00 10.--11. " SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
bitfld.quad 0x00 7.--9. "                  INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                  "
bitfld.quad 0x00 0.--4. " IDBITS           ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address"
group.quad 0x78++0x07
line.quad 0x00 "GICR_PENDBASER,LPI pending table base register"
bitfld.quad 0x00 62. "         PTZ              ,Pending Table Zero" "Not zero,Zero" 
bitfld.quad 0x00 56.--58. "                         OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
textline "                                  "
hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table"
bitfld.quad 0x00 10.--11. "                 SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                  "
bitfld.quad 0x00 7.--9. " INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                 "
tree.end
tree "SGI and PPI Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080))
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9  ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8  ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6  ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5  ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3  ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2  ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0  ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000)
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30 ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29 ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27 ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26 ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24 ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23 ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21 ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20 ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18 ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17 ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15 ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14 ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12 ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11 ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9  ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8  ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6  ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5  ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3  ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2  ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0  ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x10080++0x03
hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
textline "                          "
width 24.
group.long 0x10100++0x03
line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRENB31    ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRENB30    ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRENB29    ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRENB28    ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRENB27    ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRENB26    ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRENB25    ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRENB24    ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRENB23    ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRENB22    ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRENB21    ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRENB20    ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRENB19    ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRENB18    ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRENB17    ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRENB16    ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRENB15    ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRENB14    ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRENB13    ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRENB12    ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRENB11    ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRENB10    ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRENB9     ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRENB8     ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRENB7     ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRENB6     ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRENB5     ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRENB4     ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRENB3     ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRENB2     ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRENB1     ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRENB0     ,Set/Clear Enable Bit 0" "Disabled,Enabled"
group.long 0x10200++0x03
line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
group.long 0x10300++0x03
line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9  ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8  ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRACTIVE7  ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6  ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5  ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRACTIVE4  ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3  ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2  ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRACTIVE1  ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0  ,Set/Clear Active Bit 0" "Not active,Active"
textline "                                 "
width 18.
group.long 0x10400++0x03
line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID2    ,Interrupt ID2    Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID0    ,Interrupt ID0    Priority/Priority Byte Offset 0   "
group.long 0x10404++0x03
line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID6    ,Interrupt ID6    Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID4    ,Interrupt ID4    Priority/Priority Byte Offset 4   "
group.long 0x10408++0x03
line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID10   ,Interrupt ID10   Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID8    ,Interrupt ID8    Priority/Priority Byte Offset 8   "
group.long 0x1040C++0x03
line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID14   ,Interrupt ID14   Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID12   ,Interrupt ID12   Priority/Priority Byte Offset 12  "
group.long 0x10410++0x03
line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID18   ,Interrupt ID18   Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID16   ,Interrupt ID16   Priority/Priority Byte Offset 16  "
group.long 0x10414++0x03
line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID22   ,Interrupt ID22   Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID20   ,Interrupt ID20   Priority/Priority Byte Offset 20  "
group.long 0x10418++0x03
line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID26   ,Interrupt ID26   Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID24   ,Interrupt ID24   Priority/Priority Byte Offset 24  "
group.long 0x1041C++0x03
line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID30   ,Interrupt ID30   Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID28   ,Interrupt ID28   Priority/Priority Byte Offset 28  "
textline "                                 "
rgroup.long 0x10C00++0x03
line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (SGI)" "Level,Edge"
group.long 0x10C04++0x03
line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1    ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                           "
width 18.
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00))
group.long 0x10D00++0x03
line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1"
bitfld.long 0x00 30. "  GMB30 ,Group Modifier Bit 30" "0,1"
bitfld.long 0x00 29. "  GMB29 ,Group Modifier Bit 29" "0,1"
textline "                           "
bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1"
bitfld.long 0x00 27. "  GMB27 ,Group Modifier Bit 27" "0,1"
bitfld.long 0x00 26. "  GMB26 ,Group Modifier Bit 26" "0,1"
textline "                           "
bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1"
bitfld.long 0x00 24. "  GMB24 ,Group Modifier Bit 24" "0,1"
bitfld.long 0x00 23. "  GMB23 ,Group Modifier Bit 23" "0,1"
textline "                           "
bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1"
bitfld.long 0x00 21. "  GMB21 ,Group Modifier Bit 21" "0,1"
bitfld.long 0x00 20. "  GMB20 ,Group Modifier Bit 20" "0,1"
textline "                           "
bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1"
bitfld.long 0x00 18. "  GMB18 ,Group Modifier Bit 18" "0,1"
bitfld.long 0x00 17. "  GMB17 ,Group Modifier Bit 17" "0,1"
textline "                           "
bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1"
bitfld.long 0x00 15. "  GMB15 ,Group Modifier Bit 15" "0,1"
bitfld.long 0x00 14. "  GMB14 ,Group Modifier Bit 14" "0,1"
textline "                           "
bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1"
bitfld.long 0x00 12. "  GMB12 ,Group Modifier Bit 12" "0,1"
bitfld.long 0x00 11. "  GMB11 ,Group Modifier Bit 11" "0,1"
textline "                           "
bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1"
bitfld.long 0x00 9. "  GMB9  ,Group Modifier Bit 9" "0,1"
bitfld.long 0x00 8. "  GMB8  ,Group Modifier Bit 8" "0,1"
textline "                           "
bitfld.long 0x00 7. " GMB7  ,Group Modifier Bit 7" "0,1"
bitfld.long 0x00 6. "  GMB6  ,Group Modifier Bit 6" "0,1"
bitfld.long 0x00 5. "  GMB5  ,Group Modifier Bit 5" "0,1"
textline "                           "
bitfld.long 0x00 4. " GMB4  ,Group Modifier Bit 4" "0,1"
bitfld.long 0x00 3. "  GMB3  ,Group Modifier Bit 3" "0,1"
bitfld.long 0x00 2. "  GMB2  ,Group Modifier Bit 2" "0,1"
textline "                           "
bitfld.long 0x00 1. " GMB1  ,Group Modifier Bit 1" "0,1"
bitfld.long 0x00 0. "  GMB0  ,Group Modifier Bit 0" "0,1"
textline "                           "
else
hgroup.long 0x10D00++0x03
hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00))
group.long 0x10E00++0x03
line.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 28.--29. "  NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 26.--27. "  NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 22.--23. "  NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 20.--21. "  NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 18.--19. " NS_ACCESS9  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 16.--17. "  NS_ACCESS8  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 14.--15. "  NS_ACCESS7  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 12.--13. " NS_ACCESS6  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 10.--11. "  NS_ACCESS5  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 8.--9. "  NS_ACCESS4  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 6.--7. " NS_ACCESS3  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 4.--5. "  NS_ACCESS2  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 2.--3. "  NS_ACCESS1  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 0.--1. " NS_ACCESS0  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..."
textline "                           "
else
hgroup.long 0x10E00++0x03
hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
rgroup.long 0x1C000++0x03
line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register"
bitfld.long 0x00 31. " CPU_AS     ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High"
bitfld.long 0x00 2. "  ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
bitfld.long 0x00 1. "     ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1"
textline "                           "
bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1"
rgroup.long 0x1C080++0x03
line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 31. " PPI31S     ,Actual status of the PPI31 input signal" "Low,High"
bitfld.long 0x00 30. "  PPI30S       ,Actual status of the PPI30 input signal" "Low,High"
bitfld.long 0x00 29. "  PPI29S        ,Actual status of the PPI29 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 28. " PPI28S     ,Actual status of the PPI28 input signal" "Low,High"
bitfld.long 0x00 27. "  PPI27S       ,Actual status of the PPI27 input signal" "Low,High"
bitfld.long 0x00 26. "  PPI26S        ,Actual status of the PPI26 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 25. " PPI25S     ,Actual status of the PPI25 input signal" "Low,High"
bitfld.long 0x00 24. "  PPI24S       ,Actual status of the PPI24 input signal" "Low,High"
bitfld.long 0x00 23. "  PPI23S        ,Actual status of the PPI23 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 22. " PPI22S     ,Actual status of the PPI22 input signal" "Low,High"
bitfld.long 0x00 21. "  PPI21S       ,Actual status of the PPI21 input signal" "Low,High"
bitfld.long 0x00 20. "  PPI20S        ,Actual status of the PPI20 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 19. " PPI19S     ,Actual status of the PPI19 input signal" "Low,High"
bitfld.long 0x00 18. "  PPI18S       ,Actual status of the PPI18 input signal" "Low,High"
bitfld.long 0x00 17. "  PPI17S        ,Actual status of the PPI17 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 16. " PPI16S     ,Actual status of the PPI16 input signal" "Low,High"
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICR_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICR_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICR_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICR_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
sif COMP.AVAILABLE("GICC")
base COMP.BASE("GICC",-1.)
width 14.
tree "CPU Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.)))
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 10. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 9. "  EOIMODES      ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 6. "          IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 4. " CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "               FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODE       ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 7. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 4. "          CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
textline "                       "
bitfld.long 0x00 3. " FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
endif
textline "                       "
group.long 0x04++0x03
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICC_BPR,Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x0C++0x03
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
in
wgroup.long 0x10++0x03
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x20++0x03
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
in
wgroup.long 0x24++0x03
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x2C++0x03
line.long 0x00 "GICC_STATUSR,CPU Interface Status Register"
bitfld.long 0x00 4. " ASV      ,Attempted security violation" "Not detected,Detected"
bitfld.long 0x00 3. "  WROD    ,Write to an RO location" "Not detected,Detected"
bitfld.long 0x00 2. "  RWOD ,Read of a WO location" "Not detected,Detected"
textline "                       "
bitfld.long 0x00 1. " WRD      ,Write to a reserved location" "Not detected,Detected"
bitfld.long 0x00 0. "  RRD     ,Read of a reserved location" "Not detected,Detected"
group.long 0xD0++0x03
line.long 0x00 "GICC_APR0,Active Priorities Register 0"
group.long 0xD4++0x03
line.long 0x00 "GICC_APR1,Active Priorities Register 1"
group.long 0xD8++0x03
line.long 0x00 "GICC_APR2,Active Priorities Register 2"
group.long 0xDC++0x03
line.long 0x00 "GICC_APR3,Active Priorities Register 3"
group.long 0xE0++0x03
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0"
group.long 0xE4++0x03
line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1"
group.long 0xE8++0x03
line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2"
group.long 0xEC++0x03
line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3"
rgroup.long 0xFC++0x03
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID   ,Product ID"
bitfld.long 0x00 16.--19. "          ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..."
bitfld.long 0x00 12.--15. "         REV  ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "            IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICH")
base COMP.BASE("GICH",-1.)
width 13.
tree "Virtual CPU Control Interface"
group.long 0x00++0x03
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "             VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "      VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "             VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "       NPIE     ,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      LRENPIE  ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "             UIE      ,Underflow Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " EN       ,Virtual CPU interface Enable" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GICH_VTR,Virtual Type Register"
bitfld.long 0x00 29.--31. " PRIBITS  ,Number of priority bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 26.--28. "              PREBITS  ,Number of pre-emption bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 23.--25. "             IDBITS   ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..."
textline "                      "
bitfld.long 0x00 22. " SEIS     ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "  A3V      ,Affinity 3 valid" "Invalid,Valid"
bitfld.long 0x00 0.--4. "       LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x08++0x03
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. " VPMR     ,Virtual priority mask"
bitfld.long 0x00 21.--23. "             VBPR0    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "             VBPR1    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "                    VEOIM    ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
textline "                      "
bitfld.long 0x00 4. " VCBPR    ,Virtual Common Binary Point Register" "ABPR,BPR"
bitfld.long 0x00 3. "           VFIQEN   ,Virtual FIQ enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      VACKCTL  ,Virtual AckCtl" "INTID=1022,INTID=corresponding"
bitfld.long 0x00 1. "  VENG1    ,Virtual interrupt enable for group 1" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " VENG0    ,Virtual interrupt enable for group 0" "Disabled,Enabled"
rgroup.long 0x10++0x03
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
bitfld.long 0x00 7. " VGRP1D   ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 6. "   VGRP1E   ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 5. "  VGRP0D   ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 4. "         VGRP0E   ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
textline "                      "
bitfld.long 0x00 3. " NP       ,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 2. "   LRENP    ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 1. "  U        ,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 0. "         EOI      ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
rgroup.long 0x20++0x03
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "GICH_ELRSR0,Empty List register Status Register"
bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,Status bit for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,Status bit for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,Status bit for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,Status bit for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,Status bit for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,Status bit for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,Status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,Status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,Status bit for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,Status bit for List register 0" "No interrupt,Interrupt"
textline "                      "
group.long 0xF0++0x03
line.long 0x00 "GICH_APR0,Active Priorities Register 0"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF4++0x03
line.long 0x00 "GICH_APR1,Active Priorities Register 1"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "GICH_APR2,Active Priorities Register 2"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "GICH_APR3,Active Priorities Register 3"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
textline "                       "
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x110++0x03
line.long 0x00 "GICH_LR4,List Register 4"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x114++0x03
line.long 0x00 "GICH_LR5,List Register 5"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x118++0x03
line.long 0x00 "GICH_LR6,List Register 6"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x11C++0x03
line.long 0x00 "GICH_LR7,List Register 7"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x120++0x03
line.long 0x00 "GICH_LR8,List Register 8"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x124++0x03
line.long 0x00 "GICH_LR9,List Register 9"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x128++0x03
line.long 0x00 "GICH_LR10,List Register 10"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x12C++0x03
line.long 0x00 "GICH_LR11,List Register 11"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x130++0x03
line.long 0x00 "GICH_LR12,List Register 12"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x134++0x03
line.long 0x00 "GICH_LR13,List Register 13"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x138++0x03
line.long 0x00 "GICH_LR14,List Register 14"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICV")
base COMP.BASE("GICV",-1.)
width 14.
tree "Virtual CPU Interface"
group.long 0x00++0x03
line.long 0x00 "GICV_CTLR,VM Control Register"
bitfld.long 0x00 9. " EOIMODE    ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 4. "  CBPR       ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "       FIQEN ,FIQ Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding"
textline "                      "
bitfld.long 0x00 1. "  ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
group.long 0x04++0x03
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority mask level for the virtual CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICV_BPR,VM Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x0C++0x03
line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x10++0x03
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICV_RPR,VM Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x20++0x03
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x24++0x03
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
textline ""
group.long 0xD0++0x03
line.long 0x00 "GICV_APR0,VM Active Priority Register 0"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD4++0x03
line.long 0x00 "GICV_APR1,VM Active Priority Register 1"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD8++0x03
line.long 0x00 "GICV_APR2,VM Active Priority Register 2"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xDC++0x03
line.long 0x00 "GICV_APR3,VM Active Priority Register 3"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
textline "                      "
rgroup.long 0xFC++0x03
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID     ,Product ID"
bitfld.long 0x00 16.--19. "    ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "  REV ,Revision number for the CPU interface" ",,,GICv3,?..."
hexmask.long.word 0x00 0.--11. 1. "  IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
tree.end
width 0x0b
endif
width 0x0B
tree.end
tree.end
elif (CORENAME()=="C66X")
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "Core Registers (c66x)"
config 16. 8.
width 0x0b
tree.open "Cache"
tree "L1P Cache"
base d:0x01840000
width 9.
group.long 0x20++0x7 "L1P Cache Control Registers"
line.long 0x00 "L1PCFG,L1P Configuration Register"
bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
line.long 0x04 "L1PCC,L1P Cache Control Register"
bitfld.long 0x04 16. " POPER   ,Holds the previous value of the OPER field" "0,1"
bitfld.long 0x04 0. "            OPER ,Controls the L1P freeze mode" "Disabled,Enabled"
wgroup.long 0x4020++0x3
line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register"
hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation"
group.long 0x4024++0x3
line.long 0x00 "L1PIWC,L1P Invalidate Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1PIWC  ,Word count for block invalidation"
group.long 0x5028++0x3
line.long 0x00 "L1PINV,L1P Invalidate Register"
bitfld.long 0x00 0. " I       ,Controls the global invalidation of L1P cache" "Normal,Invalidate"
//width 13.
//wgroup.long 0xD00++0x13 "Memory Protection Lock Registers"
//    line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0"
//        hexmask.long 0x00 0.--31. 1. " LB   ,Lock Bits 31:0"
//    line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1"
//        hexmask.long 0x04 0.--31. 1. " LB   ,Lock Bits 63:32"
//    line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2"
//        hexmask.long 0x08 0.--31. 1. " LB   ,Lock Bits 95:64"
//    line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3"
//        hexmask.long 0x0c 0.--31. 1. " LB   ,Lock Bits 127:96"
//    line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register"
//        bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset"
//        bitfld.long 0x10 1. "   LOCK ,Interface to complete a lock sequence" "No effect,Locked"
//        bitfld.long 0x10 0. "  UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
//rgroup.long 0xD14++0x3
//    line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register"
//        bitfld.long 0x00 0. " LK   ,Indicates the lock's current status" "Disengaged,Engaged"
base d:0x0184a000
width 12.
tree "Memory Page Protection Attribute Registers"
group.long 0x640++0x3f
line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16"
bitfld.long 0x0 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x0 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x0 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x0 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x0 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x0 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x0 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x0 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x0 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x0 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x0 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x0 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x0 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x0 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17"
bitfld.long 0x4 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x4 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x4 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x4 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x4 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x4 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x4 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x4 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x4 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18"
bitfld.long 0x8 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x8 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x8 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x8 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x8 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x8 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x8 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x8 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x8 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x8 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x8 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x8 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x8 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x8 0. "      UX     ,User execute access type" "Normal,User"
line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19"
bitfld.long 0xC 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0xC 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0xC 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0xC 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0xC 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0xC 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0xC 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0xC 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0xC 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0xC 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0xC 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0xC 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0xC 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0xC 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20"
bitfld.long 0x10 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x10 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x10 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x10 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x10 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x10 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x10 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x10 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x10 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x10 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x10 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x10 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x10 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x10 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21"
bitfld.long 0x14 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x14 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x14 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x14 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x14 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x14 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x14 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x14 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x14 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x14 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x14 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x14 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x14 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x14 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22"
bitfld.long 0x18 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x18 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x18 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x18 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x18 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x18 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x18 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x18 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x18 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x18 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x18 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x18 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x18 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x18 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23"
bitfld.long 0x1C 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x1C 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x1C 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x1C 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x1C 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x1C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x1C 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x1C 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x1C 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x1C 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x1C 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x1C 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x1C 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x1C 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24"
bitfld.long 0x20 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x20 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x20 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x20 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x20 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x20 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x20 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x20 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x20 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x20 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x20 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x20 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x20 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x20 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25"
bitfld.long 0x24 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x24 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x24 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x24 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x24 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x24 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x24 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x24 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x24 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x24 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x24 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x24 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x24 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x24 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26"
bitfld.long 0x28 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x28 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x28 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x28 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x28 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x28 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x28 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x28 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x28 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x28 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x28 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x28 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x28 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x28 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27"
bitfld.long 0x2C 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x2C 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x2C 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x2C 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x2C 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x2C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x2C 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x2C 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x2C 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x2C 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x2C 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x2C 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x2C 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x2C 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28"
bitfld.long 0x30 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x30 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x30 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x30 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x30 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x30 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x30 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x30 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x30 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x30 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x30 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x30 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x30 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x30 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29"
bitfld.long 0x34 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x34 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x34 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x34 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x34 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x34 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x34 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x34 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x34 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x34 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x34 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x34 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x34 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x34 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30"
bitfld.long 0x38 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x38 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x38 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x38 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x38 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x38 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x38 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x38 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x38 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x38 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x38 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x38 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x38 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x38 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31"
bitfld.long 0x3C 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x3C 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x3C 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x3C 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x3C 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x3C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x3C 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x3C 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x3C 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x3C 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x3C 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x3C 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x3C 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x3C 0. "      UX     ,User execute access type" "Normal,User"
tree.end
width 11.
rgroup.long 0x400++0x7 "Memory Protection Fault Registers"
line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address"
hexmask.long 0x00 0.--31. 1. " FA     ,Fault Address"
line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register"
hexmask.long.byte 0x04 9.--15. 1. " FID    ,Bit 6:0 of faulting requestor"
bitfld.long 0x04 8. "         LOCAL ,Local access" "Normal,Local"
bitfld.long 0x04 5. "  SR ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x04 4. "  SW ,Supervisor write access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x04 2. " UR     ,User read access type" "Normal,User"
bitfld.long 0x04 1. "     UW    ,User write access type" "Normal,User"
group.long 0x408++0x3
line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear"
bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear"
AUTOINDENT.ON right tree
rgroup.long 0x6404++0x3 "Error Detection Registers"
line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register"
bitfld.long 0x0  6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
bitfld.long 0x0  5. "PERR,Program fetch resulted in parity check error" "False,True"
bitfld.long 0x0  3. "SUSP,Error detection logic is suspended" "False,True"
bitfld.long 0x0  2. "DIS,Error detection logic is disabled" "False,True"
bitfld.long 0x0  0. "EN,Error detection logic is enabled" "False,True"
group.long 0x6408++0x3
line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register"
bitfld.long 0x0  6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
bitfld.long 0x0  5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
bitfld.long 0x0  3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
bitfld.long 0x0  2. "DIS,Disables the error detection logic" "No effect,Disable"
bitfld.long 0x0  0. "EN,Enables the error detection logic" "No effect,Enable"
rgroup.long 0x640C++0x3
line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register"
hexmask.long.long 0x0   5.--31. 32. "ADDR,Contains the upper 27 bit of error location"
bitfld.long       0x0        0.     "RAM,Location where error was detected" "L1P cache,L1P RAM"
AUTOINDENT.OFF
width 0xb
tree.end
tree "L1D Cache"
base d:0x01840000
width 10.
group.long 0x40++0x7 "L1D Cache Control Registers"
line.long 0x00 "L1DCFG,L1D Cache Configuration"
bitfld.long 0x00 0.--2. " L1DMODE  ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
line.long 0x04 "L1DCC,L1D Cache Control Register"
bitfld.long 0x04 16. " POPER    ,Holds the previous value of the OPER field" "0,1"
bitfld.long 0x04 0. "             OPER ,Controls the L1D freeze mode" "Disabled,Enabled"
wgroup.long 0x4030++0x3
line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address"
hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address"
group.long 0x4034++0x3
line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1DWIWC  ,L1D Writeback-Invalidated Word Count"
wgroup.long 0x4040++0x3
line.long 0x00 "L1DWBAR,L1D Writeback Base Address"
hexmask.long 0x00 0.--31. 1. " L1DWBAR  ,L1D Writeback Base Address"
group.long 0x4044++0x3
line.long 0x00 "L1DWWC,L1D Writeback Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1DWWC   ,L1D Writeback Word Count"
wgroup.long 0x4048++0x3
line.long 0x00 "L1DIBAR,L1D Invalidate Base Address"
hexmask.long 0x00 0.--31. 1. " L1DIBAR  ,L1D Invalidate Base Address"
group.long 0x404c++0x3
line.long 0x00 "L1DIWC,L1D Invalidate Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1DIWC   ,L1D Invalidate Word Count"
group.long 0x5048++0x3
line.long 0x00 "L1DINV,L1D Invalidate Register"
bitfld.long 0x00 0. " I        ,Controls the global invalidation of L1D cache" "Normal,Invalidate"
group.long 0x5040++0x3
line.long 0x00 "L1DWB,L1P Writeback Register"
bitfld.long 0x00 0. " C        ,Controls the global writeback operation of L1D cache" "Normal,Write back"
group.long 0x5044++0x3
line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register"
bitfld.long 0x00 0. " C        ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate"
width 11.
base d:0x0184a000
tree "Memory Protection Attribute Registers"
group.long 0xe40++0x3f
line.long 0x0 "MPPA16,Memory Protection Attribute Register"
bitfld.long 0x0 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x0 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x0 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x0 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x0 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x0 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x0 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x0 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x0 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x0 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x0 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x0 1. "        UW    ,User write access type" "Normal,User"
line.long 0x4 "MPPA17,Memory Protection Attribute Register"
bitfld.long 0x4 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x4 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x4 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x4 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x4 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x4 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x4 1. "        UW    ,User write access type" "Normal,User"
line.long 0x8 "MPPA18,Memory Protection Attribute Register"
bitfld.long 0x8 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x8 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x8 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x8 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x8 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x8 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x8 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x8 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x8 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x8 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x8 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x8 1. "        UW    ,User write access type" "Normal,User"
line.long 0xC "MPPA19,Memory Protection Attribute Register"
bitfld.long 0xC 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0xC 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0xC 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0xC 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0xC 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0xC 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0xC 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0xC 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0xC 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0xC 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0xC 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0xC 1. "        UW    ,User write access type" "Normal,User"
line.long 0x10 "MPPA20,Memory Protection Attribute Register"
bitfld.long 0x10 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x10 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x10 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x10 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x10 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x10 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x10 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x10 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x10 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x10 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x10 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x10 1. "        UW    ,User write access type" "Normal,User"
line.long 0x14 "MPPA21,Memory Protection Attribute Register"
bitfld.long 0x14 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x14 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x14 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x14 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x14 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x14 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x14 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x14 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x14 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x14 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x14 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x14 1. "        UW    ,User write access type" "Normal,User"
line.long 0x18 "MPPA22,Memory Protection Attribute Register"
bitfld.long 0x18 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x18 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x18 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x18 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x18 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x18 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x18 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x18 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x18 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x18 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x18 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x18 1. "        UW    ,User write access type" "Normal,User"
line.long 0x1C "MPPA23,Memory Protection Attribute Register"
bitfld.long 0x1C 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x1C 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x1C 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x1C 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x1C 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x1C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x1C 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x1C 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x1C 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x1C 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x1C 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x1C 1. "        UW    ,User write access type" "Normal,User"
line.long 0x20 "MPPA24,Memory Protection Attribute Register"
bitfld.long 0x20 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x20 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x20 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x20 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x20 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x20 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x20 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x20 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x20 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x20 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x20 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x20 1. "        UW    ,User write access type" "Normal,User"
line.long 0x24 "MPPA25,Memory Protection Attribute Register"
bitfld.long 0x24 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x24 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x24 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x24 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x24 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x24 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x24 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x24 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x24 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x24 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x24 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x24 1. "        UW    ,User write access type" "Normal,User"
line.long 0x28 "MPPA26,Memory Protection Attribute Register"
bitfld.long 0x28 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x28 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x28 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x28 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x28 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x28 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x28 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x28 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x28 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x28 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x28 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x28 1. "        UW    ,User write access type" "Normal,User"
line.long 0x2C "MPPA27,Memory Protection Attribute Register"
bitfld.long 0x2C 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x2C 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x2C 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x2C 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x2C 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x2C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x2C 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x2C 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x2C 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x2C 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x2C 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x2C 1. "        UW    ,User write access type" "Normal,User"
line.long 0x30 "MPPA28,Memory Protection Attribute Register"
bitfld.long 0x30 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x30 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x30 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x30 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x30 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x30 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x30 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x30 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x30 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x30 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x30 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x30 1. "        UW    ,User write access type" "Normal,User"
line.long 0x34 "MPPA29,Memory Protection Attribute Register"
bitfld.long 0x34 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x34 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x34 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x34 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x34 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x34 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x34 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x34 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x34 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x34 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x34 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x34 1. "        UW    ,User write access type" "Normal,User"
line.long 0x38 "MPPA30,Memory Protection Attribute Register"
bitfld.long 0x38 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x38 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x38 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x38 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x38 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x38 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x38 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x38 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x38 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x38 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x38 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x38 1. "        UW    ,User write access type" "Normal,User"
line.long 0x3C "MPPA31,Memory Protection Attribute Register"
bitfld.long 0x3C 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x3C 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x3C 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x3C 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x3C 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x3C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x3C 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x3C 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x3C 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x3C 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x3C 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x3C 1. "        UW    ,User write access type" "Normal,User"
tree.end
base d:0x0184a000
width 10.
rgroup.long 0xc00++0x7 "Memory Protection Fault Registers"
line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register"
hexmask.long 0x00 0.--31. 1. " FA     ,Fault Address"
line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register"
hexmask.long.byte 0x04 9.--15. 1. " FID    ,Bit 6:0 of ID of faulting requestor"
bitfld.long 0x04 8. "          LOCAL ,Local access" "Normal,Supervisor"
bitfld.long 0x04 5. "  SR ,Supervisor read access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x04 4. " SW     ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x04 2. "  UR    ,User read access type" "Normal,User"
bitfld.long 0x04 1. "      UW ,User write access type" "Normal,User"
group.long 0xc08++0x3
line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register"
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared"
width 13.
wgroup.long 0xd00++0xf "Memory Protection Lock Registers"
line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0"
hexmask.long 0x00 0.--31. 1. " LB   ,Lock Bits 31:0"
line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1"
hexmask.long 0x04 0.--31. 1. " LB   ,Lock Bits 63:32"
line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2"
line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3"
wgroup.long 0xd10++0x3
line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register"
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
bitfld.long 0x00 1. "   LOCK ,Interface to complete a lock sequence" "No effect,Locked"
bitfld.long 0x00 0. "  UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
rgroup.long 0xd14++0x3
line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register"
bitfld.long 0x00 0. " LK   ,Indicates the lock's current status" "Disengaged,Engaged"
width 0xb
tree.end
tree "L2 Cache"
base d:0x01840000
width 9.
group.long 0x00++0x3 "L2 Cache Control Registers"
line.long 0x00 "L2CFG,L2 Configuration Register"
hexmask.long.byte 0x00 24.--27. 1. " NUM_MM  ,Number of megamodules minus one"
hexmask.long.byte 0x00 16.--19. 1. "           MMID  ,Contains the Megamodule ID number"
bitfld.long 0x00 9. "          IP     ,L1P global invalidate bit" "Normal,Invalidate"
textline "                  "
bitfld.long 0x00 8. " ID      ,L1D global invalidate bit" "Normal,Invalidate"
bitfld.long 0x00 3. "   L2CC  ,Freeze mode" "Normal,Frozen"
bitfld.long 0x00 0.--2. "      L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum"
wgroup.long 0x4000++0x3
line.long 0x00 "L2WBAR,L2 Writeback Base Address Register"
hexmask.long 0x00 0.--31. 1. " L2WBAR  ,L2 Writeback Base Address"
group.long 0x4004++0x3
line.long 0x00 "L2WWC,L2 Writeback Word Count Register"
hexmask.long.word 0x00 0.--15. 1. " L2WWC   ,L2 Writeback Word Count"
wgroup.long 0x4010++0x3
line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address"
hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address"
group.long 0x4014++0x3
line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register"
hexmask.long.word 0x00 0.--15. 1. " L2WIWC  ,L2 Writeback Invalidate Word Count"
wgroup.long 0x4018++0x3
line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register"
hexmask.long 0x00 0.--31. 1. " L2IBAR  ,L2 Invalidate Base Address"
group.long 0x401c++0x3
line.long 0x00 "L2IWC,L2 Invalidate Word Count Register"
hexmask.long.word 0x00 0.--15. 1. " L2IWC   ,L2 Invalidate Word Count"
group.long 0x5000++0xb
line.long 0x00 "L2WB,L2 Writeback Register"
bitfld.long 0x00 0. " C       ,Controls the global writeback operation of L2 cache" "Normal,Writeback"
line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register"
bitfld.long 0x04 0. " C       ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback"
line.long 0x08 "L2INV,L2 Invalidate Register"
bitfld.long 0x08 0. " I       ,Controls the global invalidation of L2 cache" "Normal,Invalidate"
tree "Memory Attribute Registers"
width 8.
base d:0x01848000
rgroup.long 0x00++0x2f
line.long 0x0 "MAR0,Memory Attribute Register 0"
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x4 "MAR1,Memory Attribute Register 1"
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x8 "MAR2,Memory Attribute Register 2"
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC "MAR3,Memory Attribute Register 3"
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x10 "MAR4,Memory Attribute Register 4"
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x10 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x14 "MAR5,Memory Attribute Register 5"
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x14 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x18 "MAR6,Memory Attribute Register 6"
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x18 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C "MAR7,Memory Attribute Register 7"
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x20 "MAR8,Memory Attribute Register 8"
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x20 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x24 "MAR9,Memory Attribute Register 9"
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x24 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x28 "MAR10,Memory Attribute Register 10"
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x28 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C "MAR11,Memory Attribute Register 11"
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
group.long 0x30++0x3cf
line.long 0x0 "MAR12,Memory Attribute Register 12"
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x4 "MAR13,Memory Attribute Register 13"
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x8 "MAR14,Memory Attribute Register 14"
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC "MAR15,Memory Attribute Register 15"
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x10 "MAR16,Memory Attribute Register 16"
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x10 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x14 "MAR17,Memory Attribute Register 17"
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x14 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x18 "MAR18,Memory Attribute Register 18"
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x18 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C "MAR19,Memory Attribute Register 19"
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x20 "MAR20,Memory Attribute Register 20"
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x20 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x24 "MAR21,Memory Attribute Register 21"
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x24 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x28 "MAR22,Memory Attribute Register 22"
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x28 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C "MAR23,Memory Attribute Register 23"
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x30 "MAR24,Memory Attribute Register 24"
bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x30 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x34 "MAR25,Memory Attribute Register 25"
bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x34 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x38 "MAR26,Memory Attribute Register 26"
bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x38 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C "MAR27,Memory Attribute Register 27"
bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x40 "MAR28,Memory Attribute Register 28"
bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x40 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x44 "MAR29,Memory Attribute Register 29"
bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x44 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x48 "MAR30,Memory Attribute Register 30"
bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x48 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x4C "MAR31,Memory Attribute Register 31"
bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x4C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x50 "MAR32,Memory Attribute Register 32"
bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x50 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x54 "MAR33,Memory Attribute Register 33"
bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x54 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x58 "MAR34,Memory Attribute Register 34"
bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x58 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x5C "MAR35,Memory Attribute Register 35"
bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x5C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x60 "MAR36,Memory Attribute Register 36"
bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x60 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x64 "MAR37,Memory Attribute Register 37"
bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x64 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x68 "MAR38,Memory Attribute Register 38"
bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x68 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x6C "MAR39,Memory Attribute Register 39"
bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x6C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x70 "MAR40,Memory Attribute Register 40"
bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x70 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x74 "MAR41,Memory Attribute Register 41"
bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x74 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x78 "MAR42,Memory Attribute Register 42"
bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x78 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x7C "MAR43,Memory Attribute Register 43"
bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x7C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x80 "MAR44,Memory Attribute Register 44"
bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x80 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x84 "MAR45,Memory Attribute Register 45"
bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x84 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x88 "MAR46,Memory Attribute Register 46"
bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x88 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x8C "MAR47,Memory Attribute Register 47"
bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x8C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x90 "MAR48,Memory Attribute Register 48"
bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x90 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x94 "MAR49,Memory Attribute Register 49"
bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x94 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x98 "MAR50,Memory Attribute Register 50"
bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x98 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x9C "MAR51,Memory Attribute Register 51"
bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x9C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xA0 "MAR52,Memory Attribute Register 52"
bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xA0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xA4 "MAR53,Memory Attribute Register 53"
bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xA4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xA8 "MAR54,Memory Attribute Register 54"
bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xA8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xAC "MAR55,Memory Attribute Register 55"
bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xAC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xB0 "MAR56,Memory Attribute Register 56"
bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xB0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xB4 "MAR57,Memory Attribute Register 57"
bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xB4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xB8 "MAR58,Memory Attribute Register 58"
bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xB8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xBC "MAR59,Memory Attribute Register 59"
bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xBC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC0 "MAR60,Memory Attribute Register 60"
bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC4 "MAR61,Memory Attribute Register 61"
bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC8 "MAR62,Memory Attribute Register 62"
bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xCC "MAR63,Memory Attribute Register 63"
bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xCC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xD0 "MAR64,Memory Attribute Register 64"
bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xD0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xD4 "MAR65,Memory Attribute Register 65"
bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xD4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xD8 "MAR66,Memory Attribute Register 66"
bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xD8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xDC "MAR67,Memory Attribute Register 67"
bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xDC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xE0 "MAR68,Memory Attribute Register 68"
bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xE0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xE4 "MAR69,Memory Attribute Register 69"
bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xE4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xE8 "MAR70,Memory Attribute Register 70"
bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xE8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xEC "MAR71,Memory Attribute Register 71"
bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xEC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xF0 "MAR72,Memory Attribute Register 72"
bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xF0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xF4 "MAR73,Memory Attribute Register 73"
bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xF4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xF8 "MAR74,Memory Attribute Register 74"
bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xF8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xFC "MAR75,Memory Attribute Register 75"
bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xFC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x100 "MAR76,Memory Attribute Register 76"
bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x100 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x104 "MAR77,Memory Attribute Register 77"
bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x104 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x108 "MAR78,Memory Attribute Register 78"
bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x108 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x10C "MAR79,Memory Attribute Register 79"
bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x10C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x110 "MAR80,Memory Attribute Register 80"
bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x110 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x114 "MAR81,Memory Attribute Register 81"
bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x114 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x118 "MAR82,Memory Attribute Register 82"
bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x118 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x11C "MAR83,Memory Attribute Register 83"
bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x11C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x120 "MAR84,Memory Attribute Register 84"
bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x120 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x124 "MAR85,Memory Attribute Register 85"
bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x124 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x128 "MAR86,Memory Attribute Register 86"
bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x128 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x12C "MAR87,Memory Attribute Register 87"
bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x12C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x130 "MAR88,Memory Attribute Register 88"
bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x130 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x134 "MAR89,Memory Attribute Register 89"
bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x134 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x138 "MAR90,Memory Attribute Register 90"
bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x138 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x13C "MAR91,Memory Attribute Register 91"
bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x13C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x140 "MAR92,Memory Attribute Register 92"
bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x140 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x144 "MAR93,Memory Attribute Register 93"
bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x144 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x148 "MAR94,Memory Attribute Register 94"
bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x148 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x14C "MAR95,Memory Attribute Register 95"
bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x14C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x150 "MAR96,Memory Attribute Register 96"
bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x150 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x154 "MAR97,Memory Attribute Register 97"
bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x154 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x158 "MAR98,Memory Attribute Register 98"
bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x158 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x15C "MAR99,Memory Attribute Register 99"
bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x15C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x160 "MAR100,Memory Attribute Register 100"
bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x160 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x164 "MAR101,Memory Attribute Register 101"
bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x164 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x168 "MAR102,Memory Attribute Register 102"
bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x168 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x16C "MAR103,Memory Attribute Register 103"
bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x16C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x170 "MAR104,Memory Attribute Register 104"
bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x170 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x174 "MAR105,Memory Attribute Register 105"
bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x174 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x178 "MAR106,Memory Attribute Register 106"
bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x178 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x17C "MAR107,Memory Attribute Register 107"
bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x17C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x180 "MAR108,Memory Attribute Register 108"
bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x180 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x184 "MAR109,Memory Attribute Register 109"
bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x184 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x188 "MAR110,Memory Attribute Register 110"
bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x188 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x18C "MAR111,Memory Attribute Register 111"
bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x18C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x190 "MAR112,Memory Attribute Register 112"
bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x190 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x194 "MAR113,Memory Attribute Register 113"
bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x194 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x198 "MAR114,Memory Attribute Register 114"
bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x198 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x19C "MAR115,Memory Attribute Register 115"
bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x19C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1A0 "MAR116,Memory Attribute Register 116"
bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1A0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1A4 "MAR117,Memory Attribute Register 117"
bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1A4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1A8 "MAR118,Memory Attribute Register 118"
bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1A8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1AC "MAR119,Memory Attribute Register 119"
bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1AC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1B0 "MAR120,Memory Attribute Register 120"
bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1B0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1B4 "MAR121,Memory Attribute Register 121"
bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1B4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1B8 "MAR122,Memory Attribute Register 122"
bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1B8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1BC "MAR123,Memory Attribute Register 123"
bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1BC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C0 "MAR124,Memory Attribute Register 124"
bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C4 "MAR125,Memory Attribute Register 125"
bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C8 "MAR126,Memory Attribute Register 126"
bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1CC "MAR127,Memory Attribute Register 127"
bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1CC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1D0 "MAR128,Memory Attribute Register 128"
bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1D0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1D4 "MAR129,Memory Attribute Register 129"
bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1D4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1D8 "MAR130,Memory Attribute Register 130"
bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1D8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1DC "MAR131,Memory Attribute Register 131"
bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1DC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1E0 "MAR132,Memory Attribute Register 132"
bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1E0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1E4 "MAR133,Memory Attribute Register 133"
bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1E4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1E8 "MAR134,Memory Attribute Register 134"
bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1E8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1EC "MAR135,Memory Attribute Register 135"
bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1EC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1F0 "MAR136,Memory Attribute Register 136"
bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1F0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1F4 "MAR137,Memory Attribute Register 137"
bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1F4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1F8 "MAR138,Memory Attribute Register 138"
bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1F8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1FC "MAR139,Memory Attribute Register 139"
bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1FC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x200 "MAR140,Memory Attribute Register 140"
bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x200 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x204 "MAR141,Memory Attribute Register 141"
bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x204 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x208 "MAR142,Memory Attribute Register 142"
bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x208 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x20C "MAR143,Memory Attribute Register 143"
bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x20C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x210 "MAR144,Memory Attribute Register 144"
bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x210 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x214 "MAR145,Memory Attribute Register 145"
bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x214 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x218 "MAR146,Memory Attribute Register 146"
bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x218 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x21C "MAR147,Memory Attribute Register 147"
bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x21C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x220 "MAR148,Memory Attribute Register 148"
bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x220 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x224 "MAR149,Memory Attribute Register 149"
bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x224 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x228 "MAR150,Memory Attribute Register 150"
bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x228 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x22C "MAR151,Memory Attribute Register 151"
bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x22C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x230 "MAR152,Memory Attribute Register 152"
bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x230 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x234 "MAR153,Memory Attribute Register 153"
bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x234 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x238 "MAR154,Memory Attribute Register 154"
bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x238 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x23C "MAR155,Memory Attribute Register 155"
bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x23C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x240 "MAR156,Memory Attribute Register 156"
bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x240 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x244 "MAR157,Memory Attribute Register 157"
bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x244 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x248 "MAR158,Memory Attribute Register 158"
bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x248 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x24C "MAR159,Memory Attribute Register 159"
bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x24C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x250 "MAR160,Memory Attribute Register 160"
bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x250 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x254 "MAR161,Memory Attribute Register 161"
bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x254 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x258 "MAR162,Memory Attribute Register 162"
bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x258 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x25C "MAR163,Memory Attribute Register 163"
bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x25C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x260 "MAR164,Memory Attribute Register 164"
bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x260 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x264 "MAR165,Memory Attribute Register 165"
bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x264 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x268 "MAR166,Memory Attribute Register 166"
bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x268 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x26C "MAR167,Memory Attribute Register 167"
bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x26C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x270 "MAR168,Memory Attribute Register 168"
bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x270 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x274 "MAR169,Memory Attribute Register 169"
bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x274 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x278 "MAR170,Memory Attribute Register 170"
bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x278 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x27C "MAR171,Memory Attribute Register 171"
bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x27C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x280 "MAR172,Memory Attribute Register 172"
bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x280 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x284 "MAR173,Memory Attribute Register 173"
bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x284 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x288 "MAR174,Memory Attribute Register 174"
bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x288 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x28C "MAR175,Memory Attribute Register 175"
bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x28C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x290 "MAR176,Memory Attribute Register 176"
bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x290 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x294 "MAR177,Memory Attribute Register 177"
bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x294 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x298 "MAR178,Memory Attribute Register 178"
bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x298 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x29C "MAR179,Memory Attribute Register 179"
bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x29C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2A0 "MAR180,Memory Attribute Register 180"
bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2A0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2A4 "MAR181,Memory Attribute Register 181"
bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2A4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2A8 "MAR182,Memory Attribute Register 182"
bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2A8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2AC "MAR183,Memory Attribute Register 183"
bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2AC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2B0 "MAR184,Memory Attribute Register 184"
bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2B0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2B4 "MAR185,Memory Attribute Register 185"
bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2B4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2B8 "MAR186,Memory Attribute Register 186"
bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2B8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2BC "MAR187,Memory Attribute Register 187"
bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2BC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C0 "MAR188,Memory Attribute Register 188"
bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C4 "MAR189,Memory Attribute Register 189"
bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C8 "MAR190,Memory Attribute Register 190"
bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2CC "MAR191,Memory Attribute Register 191"
bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2CC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2D0 "MAR192,Memory Attribute Register 192"
bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2D0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2D4 "MAR193,Memory Attribute Register 193"
bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2D4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2D8 "MAR194,Memory Attribute Register 194"
bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2D8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2DC "MAR195,Memory Attribute Register 195"
bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2DC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2E0 "MAR196,Memory Attribute Register 196"
bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2E0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2E4 "MAR197,Memory Attribute Register 197"
bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2E4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2E8 "MAR198,Memory Attribute Register 198"
bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2E8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2EC "MAR199,Memory Attribute Register 199"
bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2EC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2F0 "MAR200,Memory Attribute Register 200"
bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2F0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2F4 "MAR201,Memory Attribute Register 201"
bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2F4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2F8 "MAR202,Memory Attribute Register 202"
bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2F8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2FC "MAR203,Memory Attribute Register 203"
bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2FC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x300 "MAR204,Memory Attribute Register 204"
bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x300 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x304 "MAR205,Memory Attribute Register 205"
bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x304 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x308 "MAR206,Memory Attribute Register 206"
bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x308 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x30C "MAR207,Memory Attribute Register 207"
bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x30C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x310 "MAR208,Memory Attribute Register 208"
bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x310 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x314 "MAR209,Memory Attribute Register 209"
bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x314 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x318 "MAR210,Memory Attribute Register 210"
bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x318 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x31C "MAR211,Memory Attribute Register 211"
bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x31C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x320 "MAR212,Memory Attribute Register 212"
bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x320 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x324 "MAR213,Memory Attribute Register 213"
bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x324 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x328 "MAR214,Memory Attribute Register 214"
bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x328 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x32C "MAR215,Memory Attribute Register 215"
bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x32C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x330 "MAR216,Memory Attribute Register 216"
bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x330 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x334 "MAR217,Memory Attribute Register 217"
bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x334 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x338 "MAR218,Memory Attribute Register 218"
bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x338 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x33C "MAR219,Memory Attribute Register 219"
bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x33C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x340 "MAR220,Memory Attribute Register 220"
bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x340 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x344 "MAR221,Memory Attribute Register 221"
bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x344 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x348 "MAR222,Memory Attribute Register 222"
bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x348 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x34C "MAR223,Memory Attribute Register 223"
bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x34C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x350 "MAR224,Memory Attribute Register 224"
bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x350 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x354 "MAR225,Memory Attribute Register 225"
bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x354 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x358 "MAR226,Memory Attribute Register 226"
bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x358 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x35C "MAR227,Memory Attribute Register 227"
bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x35C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x360 "MAR228,Memory Attribute Register 228"
bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x360 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x364 "MAR229,Memory Attribute Register 229"
bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x364 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x368 "MAR230,Memory Attribute Register 230"
bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x368 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x36C "MAR231,Memory Attribute Register 231"
bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x36C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x370 "MAR232,Memory Attribute Register 232"
bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x370 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x374 "MAR233,Memory Attribute Register 233"
bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x374 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x378 "MAR234,Memory Attribute Register 234"
bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x378 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x37C "MAR235,Memory Attribute Register 235"
bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x37C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x380 "MAR236,Memory Attribute Register 236"
bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x380 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x384 "MAR237,Memory Attribute Register 237"
bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x384 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x388 "MAR238,Memory Attribute Register 238"
bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x388 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x38C "MAR239,Memory Attribute Register 239"
bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x38C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x390 "MAR240,Memory Attribute Register 240"
bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x390 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x394 "MAR241,Memory Attribute Register 241"
bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x394 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x398 "MAR242,Memory Attribute Register 242"
bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x398 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x39C "MAR243,Memory Attribute Register 243"
bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x39C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3A0 "MAR244,Memory Attribute Register 244"
bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3A0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3A4 "MAR245,Memory Attribute Register 245"
bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3A4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3A8 "MAR246,Memory Attribute Register 246"
bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3A8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3AC "MAR247,Memory Attribute Register 247"
bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3AC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3B0 "MAR248,Memory Attribute Register 248"
bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3B0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3B4 "MAR249,Memory Attribute Register 249"
bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3B4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3B8 "MAR250,Memory Attribute Register 250"
bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3B8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3BC "MAR251,Memory Attribute Register 251"
bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3BC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C0 "MAR252,Memory Attribute Register 252"
bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C4 "MAR253,Memory Attribute Register 253"
bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C8 "MAR254,Memory Attribute Register 254"
bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3CC "MAR255,Memory Attribute Register 255"
bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3CC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
tree.end
width 10.
base d:0x0184a000
tree "Memory Protection Page Attribute Registers"
group.long 0x200++0x7f
line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0"
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x0 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x0 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x0 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x0 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x0 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x0 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x0 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x0 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x0 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x0 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x0 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1"
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x4 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x4 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x4 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x4 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x4 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x4 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2"
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x8 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x8 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x8 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x8 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x8 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x8 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x8 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x8 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x8 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x8 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x8 0. "     UX   ,User execute access type" "Normal,User"
line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3"
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0xC 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0xC 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0xC 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0xC 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0xC 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0xC 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0xC 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0xC 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0xC 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0xC 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0xC 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4"
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x10 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x10 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x10 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x10 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x10 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x10 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x10 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x10 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x10 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x10 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x10 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5"
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x14 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x14 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x14 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x14 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x14 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x14 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x14 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x14 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x14 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x14 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x14 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6"
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x18 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x18 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x18 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x18 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x18 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x18 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x18 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x18 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x18 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x18 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x18 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7"
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x1C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x1C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x1C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x1C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x1C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x1C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x1C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x1C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x1C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x1C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x1C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8"
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x20 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x20 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x20 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x20 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x20 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x20 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x20 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x20 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x20 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x20 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x20 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9"
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x24 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x24 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x24 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x24 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x24 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x24 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x24 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x24 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x24 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x24 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x24 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10"
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x28 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x28 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x28 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x28 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x28 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x28 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x28 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x28 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x28 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x28 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x28 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11"
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x2C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x2C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x2C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x2C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x2C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x2C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x2C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x2C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x2C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x2C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x2C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12"
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x30 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x30 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x30 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x30 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x30 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x30 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x30 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x30 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x30 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x30 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x30 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13"
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x34 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x34 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x34 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x34 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x34 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x34 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x34 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x34 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x34 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x34 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x34 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14"
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x38 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x38 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x38 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x38 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x38 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x38 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x38 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x38 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x38 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x38 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x38 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15"
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x3C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x3C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x3C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x3C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x3C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x3C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x3C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x3C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x3C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x3C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x3C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16"
bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x40 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x40 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x40 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x40 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x40 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x40 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x40 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x40 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x40 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x40 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x40 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17"
bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x44 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x44 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x44 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x44 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x44 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x44 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x44 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x44 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x44 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x44 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x44 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18"
bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x48 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x48 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x48 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x48 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x48 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x48 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x48 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x48 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x48 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x48 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x48 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19"
bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x4C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x4C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x4C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x4C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x4C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x4C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20"
bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x50 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x50 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x50 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x50 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x50 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x50 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x50 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x50 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x50 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x50 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x50 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21"
bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x54 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x54 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x54 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x54 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x54 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x54 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x54 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x54 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x54 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x54 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x54 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22"
bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x58 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x58 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x58 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x58 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x58 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x58 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x58 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x58 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x58 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x58 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x58 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23"
bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x5C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x5C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x5C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x5C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x5C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x5C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x5C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x5C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x5C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x5C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x5C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24"
bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x60 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x60 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x60 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x60 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x60 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x60 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x60 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x60 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x60 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x60 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x60 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25"
bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x64 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x64 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x64 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x64 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x64 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x64 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x64 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x64 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x64 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x64 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x64 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26"
bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x68 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x68 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x68 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x68 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x68 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x68 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x68 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x68 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x68 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x68 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x68 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27"
bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x6C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x6C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x6C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x6C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x6C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x6C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x6C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x6C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x6C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x6C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x6C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28"
bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x70 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x70 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x70 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x70 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x70 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x70 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x70 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x70 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x70 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x70 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x70 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29"
bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x74 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x74 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x74 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x74 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x74 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x74 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x74 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x74 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x74 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x74 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x74 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30"
bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x78 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x78 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x78 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x78 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x78 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x78 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x78 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x78 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x78 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x78 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x78 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31"
bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x7C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x7C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x7C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x7C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x7C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x7C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x7C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x7C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x7C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x7C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x7C 0. "     UX   ,User execute access type" "Normal,User"
tree.end
width 9.
rgroup.long 0x000++0x7 "Memory Protection Fault Registers"
line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register"
hexmask.long 0x00 0.--31. 1. " FA     ,Fault Address"
line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register"
hexmask.long.byte 0x04 9.--15. 1. " FID    ,Bit 6:0 of ID of faulting requestor"
bitfld.long 0x04 8. "          LOCAL ,Local access" "Normal,Supervisor"
bitfld.long 0x04 5. "  SR ,Supervisor read access type" "Normal,Supervisor"
textline "                  "
bitfld.long 0x04 4. " SW     ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x04 2. "  UR    ,User read access type" "Normal,User"
bitfld.long 0x04 1. "      UW ,User write access type" "Normal,User"
group.long 0x008++0x3
line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register"
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear"
width 12.
wgroup.long 0x100++0xf "Memory Protection Lock Registers"
line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0"
hexmask.long 0x00 0.--31. 1. " LB   ,Lock Bits 31:0"
line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1"
hexmask.long 0x04 0.--31. 1. " LB   ,Lock Bits 63:32"
line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2"
hexmask.long 0x08 0.--31. 1. " LB   ,Lock Bits 95:64"
line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3"
hexmask.long 0x0c 0.--31. 1. " LB   ,Lock Bits 127:96"
wgroup.long 0x110++0x3
line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register"
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
bitfld.long 0x00 1. "   LOCK ,Interface to complete a lock sequence" "No effect,Locked"
bitfld.long 0x00 0. "  UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
rgroup.long 0x114++0x3
line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register"
bitfld.long 0x00 0. " LK   ,Indicates the lock's current status" "Disengaged,Engaged"
AUTOINDENT.ON right tree
base d:0x01846000
rgroup.long 0x4++0x3 "Error Detection Registers"
line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register"
decmask.long.byte 0x0  16.--23. "BITPOS,Single Bit error position"
bitfld.long       0x0    8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value"
newline
bitfld.long       0x0        7. "VERR,Error occurred on L2 victims" "False,True"
bitfld.long       0x0        6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
bitfld.long       0x0        5. "PERR,Program fetch resulted in parity check error" "False,True"
newline
bitfld.long       0x0        3. "SUSP,Error detection logic is suspended" "False,True"
bitfld.long       0x0        2. "DIS,Error detection logic is disabled" "False,True"
bitfld.long       0x0        0. "EN,Error detection logic is enabled" "False,True"
group.long 0x8++0x3
line.long 0x0 "L2EDCMD, L2 Error Detection Command Register"
bitfld.long 0x0  7. "VCLR,Clears the victim parity error status" "No effect,Clear"
bitfld.long 0x0  6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
bitfld.long 0x0  5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
bitfld.long 0x0  4. "DCLR,Clears the data fetch parity error status" "No effect,Clear"
newline
bitfld.long 0x0  3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
bitfld.long 0x0  2. "DIS,Disables the error detection logic" "No effect,Disable"
bitfld.long 0x0  0. "EN,Enables the error detection logic" "No effect,Enable"
rgroup.long 0xC++0x3
line.long 0x0 "L2EDADDR,L2 Error Detection Address Register"
hexmask.long.long 0x0   5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)"
bitfld.long       0x0    8.--9.     "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3"
bitfld.long       0x0        0.     "RAM,Location where error was detected" "L2,RAM"
rgroup.long 0x18++0x3
line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register"
hexmask.long.byte 0x0    0.--7.     "CNT,Counter value"
rgroup.long 0x1C++0x3
line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register"
hexmask.long.byte 0x0    0.--7.     "CNT,Counter value"
group.long 0x30++0x3
line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register"
bitfld.long       0x0        0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled"
bitfld.long       0x0        0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled"
bitfld.long       0x0        0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled"
bitfld.long       0x0        0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
bitfld.long       0x0        0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
AUTOINDENT.OFF
width 0xb
tree.end
tree.end
tree "IDMA (Internal Direct Memory Access Controller)"
width 14.
base d:0x01820000
rgroup.long 0x00++0x3 "Channel 0"
line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register"
bitfld.long 0x00 1. " PEND       ,Pending transfer" "Not pending,Pending"
bitfld.long 0x00 0. "  ACTV  ,Active transfer" "Not active,Active"
group.long 0x04++0xf
line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register"
bitfld.long 0x00 31. " M31        ,Mask bit 31" "Not masked,Masked"
bitfld.long 0x00 30. "   M30   ,Mask bit 30" "Not masked,Masked"
bitfld.long 0x00 29. "  M29  ,Mask bit 29" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 28. " M28        ,Mask bit 28" "Not masked,Masked"
bitfld.long 0x00 27. "   M27   ,Mask bit 27" "Not masked,Masked"
bitfld.long 0x00 26. "  M26  ,Mask bit 26" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 25. " M25        ,Mask bit 25" "Not masked,Masked"
bitfld.long 0x00 24. "   M24   ,Mask bit 24" "Not masked,Masked"
bitfld.long 0x00 23. "  M23  ,Mask bit 23" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 22. " M22        ,Mask bit 22" "Not masked,Masked"
bitfld.long 0x00 21. "   M21   ,Mask bit 21" "Not masked,Masked"
bitfld.long 0x00 20. "  M20  ,Mask bit 20" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 19. " M19        ,Mask bit 19" "Not masked,Masked"
bitfld.long 0x00 18. "   M18   ,Mask bit 18" "Not masked,Masked"
bitfld.long 0x00 17. "  M17  ,Mask bit 17" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 16. " M16        ,Mask bit 16" "Not masked,Masked"
bitfld.long 0x00 15. "   M15   ,Mask bit 15" "Not masked,Masked"
bitfld.long 0x00 14. "  M14  ,Mask bit 14" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 13. " M13        ,Mask bit 13" "Not masked,Masked"
bitfld.long 0x00 12. "   M12   ,Mask bit 12" "Not masked,Masked"
bitfld.long 0x00 11. "  M11  ,Mask bit 11" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 10. " M10        ,Mask bit 10" "Not masked,Masked"
bitfld.long 0x00 9. "   M9    ,Mask bit 9" "Not masked,Masked"
bitfld.long 0x00 8. "  M8   ,Mask bit 8" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 7. " M7         ,Mask bit 7" "Not masked,Masked"
bitfld.long 0x00 6. "   M6    ,Mask bit 6" "Not masked,Masked"
bitfld.long 0x00 5. "  M5   ,Mask bit 5" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 4. " M4         ,Mask bit 4" "Not masked,Masked"
bitfld.long 0x00 3. "   M3    ,Mask bit 3" "Not masked,Masked"
bitfld.long 0x00 2. "  M2   ,Mask bit 2" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 1. " M1         ,Mask bit 1" "Not masked,Masked"
bitfld.long 0x00 0. "   M0    ,Mask bit 0" "Not masked,Masked"
line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register"
hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address"
line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register"
hexmask.long 0x08 5.--31. 0x20 " DESTADDR   ,Destination address"
line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register"
bitfld.long 0x0c 28. " INT        ,CPU interrupt enable" "Disabled,Enabled"
bitfld.long 0x0c 0.--3. "     COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
rgroup.long 0x100++0x3 "Channel 1"
line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register"
bitfld.long 0x00 1. " PEND       ,Pending transfer" "Not pending,Pending"
bitfld.long 0x00 0. "  ACTV  ,Active transfer" "Not active,Active"
group.long 0x108++0xb
line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register"
hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address"
line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register"
hexmask.long 0x04 2.--31. 0x4 " DESTADDR   ,Destination address"
line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register"
bitfld.long 0x08 29.--31. " PRI        ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x08 28. "      INT   ,CPU interrupt enable" "Disabled,Enabled"
bitfld.long 0x08 16. "    FILL ,Block fill" "0,1"
textline "                       "
hexmask.long.word 0x08 0.--15. 1. " COUNT      ,Byte count"
width 0xb
tree.end
tree "XMC (Extended Memory Controller)"
width 14.
AUTOINDENT.ON right tree
base d:0x08000000
group.long 0x00++0x7F "XMC MPAX Segment Registers"
line.long 0x0 "XMPAXL0,MPAX segment 0 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x0       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x0       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x0       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x0       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x0       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x0       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x0    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x8 "XMPAXL1,MPAX segment 1 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x8       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x8       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x8       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x8       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x8       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x8       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x8    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x10 "XMPAXL2,MPAX segment 2 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x10       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x10       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x10       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x10       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x10       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x10       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x10    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x18 "XMPAXL3,MPAX segment 3 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x18       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x18       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x18       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x18       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x18       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x18       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x18    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x20 "XMPAXL4,MPAX segment 4 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x20       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x20       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x20       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x20       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x20       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x20       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x20    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x28 "XMPAXL5,MPAX segment 5 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x28       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x28       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x28       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x28       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x28       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x28       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x28    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x30 "XMPAXL6,MPAX segment 6 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x30       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x30       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x30       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x30       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x30       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x30       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x30    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x38 "XMPAXL7,MPAX segment 7 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x38       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x38       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x38       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x38       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x38       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x38       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x38    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x40 "XMPAXL8,MPAX segment 8 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x40       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x40       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x40       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x40       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x40       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x40       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x40    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x48 "XMPAXL9,MPAX segment 9 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x48       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x48       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x48       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x48       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x48       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x48       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x48    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x50 "XMPAXL10,MPAX segment 10 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x50       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x50       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x50       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x50       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x50       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x50       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x50    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x58 "XMPAXL11,MPAX segment 11 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x58       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x58       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x58       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x58       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x58       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x58       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x58    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x60 "XMPAXL12,MPAX segment 12 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x60       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x60       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x60       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x60       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x60       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x60       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x60    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x68 "XMPAXL13,MPAX segment 13 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x68       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x68       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x68       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x68       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x68       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x68       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x68    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x70 "XMPAXL14,MPAX segment 14 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x70       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x70       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x70       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x70       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x70       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x70       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x70    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x78 "XMPAXL15,MPAX segment 15 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x78       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x78       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x78       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x78       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x78       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x78       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x78    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
textline ""
rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers"
line.long 0. "XMPFAR,Memory Protection Fault Address Register"
hexmask.long 0x0   0.--31.    "Fault Address,Fault Address"
rgroup.long 0x204++0x3
line.long 0. "XMPFSR,Memory Protection Fault Status Register"
bitfld.long  0.         8.    "LOCAL,Access was a LOCAL access" "False,True"
bitfld.long  0.         5.    "SR,When set, indicates a supervisor read request" "False,True"
bitfld.long  0.         4.    "SW,When set, indicates a supervisor write request" "False,True"
bitfld.long  0.         3.    "SX,When set, indicates a supervisor program fetch request" "False,True"
bitfld.long  0.         2.    "UR,When set, indicates a user read request" "False,True"
bitfld.long  0.         1.    "UW,When set, indicates a user write request" "False,True"
bitfld.long  0.         0.    "UX,When set, indicates a user program fetch request" "False,True"
group.long 0x208++0x3
line.long 0. "XMPFCR,Memory Protection Fault Clear Register"
bitfld.long  0.         0.    "MPFCLR,Clear fault" "No effect,Clear"
group.long 0x280++0x3 "Prefetch Priority Register"
line.long 0. "MDMAARBX,MDMA Arbitration Priority Register"
bitfld.long  0.  16.--18.    "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)"
rgroup.long 0x300++0x3 "Prefetch Buffer Registers"
line.long 0. "XPFCMD,Prefetch Command Register"
bitfld.long        0.      4.    "ACRST,Analysis Counter Reset" "No effect,Reset"
hexmask.long.byte  0.  2.--3.    "ACEN,Analysis Counter Enable"
bitfld.long        0.      1.    "ACENL,Analysis Counter ENable (ACEN) Load" "False,True"
bitfld.long        0.      0.    "INV,Invalidate prefetch buffer contents" "No effect,Invalidate"
rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers"
line.long 0. "XPFACS,Prefetch Analysis Counter Status"
rgroup.long 0x310++0xF
line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0"
line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1"
line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2"
line.long 0xC "XPFAC3,Prefetch Analysis Counter 3"
rgroup.long 0x400++0x1F
line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0"
line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1"
line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2"
line.long 0xC "XPFADDR3,Prefetch Address for Slot 3"
line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4"
line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5"
line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6"
line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7"
AUTOINDENT.OFF
width 0xb
tree.end
tree "Bandwith Management"
width 13.
base d:0x01841000
group.long 0x40++0xf "L1D"
line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register"
bitfld.long 0x00 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
bitfld.long 0x00 0.--5. "  MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register"
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register"
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register"
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
width 13.
group.long 0x00++0xf "L2"
line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register"
bitfld.long 0x00 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
bitfld.long 0x00 0.--5. "  MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register"
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register"
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register"
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
width 13.
base d:0x01820000
group.long 0x200++0xf "EMC"
line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register"
bitfld.long 0x00 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
bitfld.long 0x00 0.--5. "  MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register"
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register"
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register"
bitfld.long 0x0c 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
width 0xb
tree.end
tree "Interrupt Controller"
width 11.
base d:0x01800000
group.long 0x00++0xf
line.long 0x00 "EVTFLAG0,Event Flag Register 0"
setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr  ,State of event EVT14" "Not occurred,Occurred"
setclrfld.long 0x00 13. 0x20 13. 0x40 13. "  EF13_set/clr  ,State of event EVT13" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr  ,State of event EVT12" "Not occurred,Occurred"
setclrfld.long 0x00 11. 0x20 11. 0x40 11. "  EF11_set/clr  ,State of event EVT11" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr   ,State of event EVT9" "Not occurred,Occurred"
setclrfld.long 0x00 8. 0x20 8. 0x40 8. "  EF8_set/clr   ,State of event EVT8" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr   ,State of event EVT7" "Not occurred,Occurred"
setclrfld.long 0x00 6. 0x20 6. 0x40 6. "  EF6_set/clr   ,State of event EVT6" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr   ,State of event EVT5" "Not occurred,Occurred"
setclrfld.long 0x00 4. 0x20 4. 0x40 4. "  EF4_set/clr   ,State of event EVT4" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr   ,State of event EVT3" "Not occurred,Occurred"
setclrfld.long 0x00 2. 0x20 2. 0x40 2. "  EF2_set/clr   ,State of event EVT2" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr   ,State of event EVT1" "Not occurred,Occurred"
setclrfld.long 0x00 0. 0x20 0. 0x40 0. "  EF0_set/clr   ,State of event EVT0" "Not occurred,Occurred"
line.long 0x04 "EVTFLAG1,Event Flag Register 1"
setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr  ,State of event EVT60" "Not occurred,Occurred"
setclrfld.long 0x04 27. 0x24 27. 0x44 27. "  EF59_set/clr  ,State of event EVT59" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr  ,State of event EVT56" "Not occurred,Occurred"
setclrfld.long 0x04 23. 0x24 23. 0x44 23. "  EF55_set/clr  ,State of event EVT55" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr  ,State of event EVT54" "Not occurred,Occurred"
setclrfld.long 0x04 21. 0x24 21. 0x44 21. "  EF53_set/clr  ,State of event EVT53" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr  ,State of event EVT51" "Not occurred,Occurred"
setclrfld.long 0x04 18. 0x24 18. 0x44 18. "  EF50_set/clr  ,State of event EVT50" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr  ,State of event EVT49" "Not occurred,Occurred"
setclrfld.long 0x04 16. 0x24 16. 0x44 16. "  EF48_set/clr  ,State of event EVT48" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr  ,State of event EVT47" "Not occurred,Occurred"
setclrfld.long 0x04 11. 0x24 11. 0x44 11. "  EF43_set/clr  ,State of event EVT43" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr  ,State of event EVT41" "Not occurred,Occurred"
setclrfld.long 0x04 8. 0x24 8. 0x44 8. "  EF40_set/clr  ,State of event EVT40" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr  ,State of event EVT39" "Not occurred,Occurred"
setclrfld.long 0x04 6. 0x24 6. 0x44 6. "  EF38_set/clr  ,State of event EVT38" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr  ,State of event EVT37" "Not occurred,Occurred"
setclrfld.long 0x04 4. 0x24 4. 0x44 4. "  EF36_set/clr  ,State of event EVT36" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr  ,State of event EVT35" "Not occurred,Occurred"
setclrfld.long 0x04 2. 0x24 2. 0x44 2. "  EF34_set/clr  ,State of event EVT34" "Not occurred,Occurred"
line.long 0x08 "EVTFLAG2,Event Flag Register 2"
setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr  ,State of event EVT85" "Not occurred,Occurred"
setclrfld.long 0x08 20. 0x28 20. 0x48 20. "  EF84_set/clr  ,State of event EVT84" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr  ,State of event EVT83" "Not occurred,Occurred"
setclrfld.long 0x08 18. 0x28 18. 0x48 18. "  EF82_set/clr  ,State of event EVT82" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr  ,State of event EVT81" "Not occurred,Occurred"
setclrfld.long 0x08 16. 0x28 16. 0x48 16. "  EF80_set/clr  ,State of event EVT80" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr  ,State of event EVT78" "Not occurred,Occurred"
setclrfld.long 0x08 13. 0x28 13. 0x48 13. "  EF77_set/clr  ,State of event EVT77" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr  ,State of event EVT76" "Not occurred,Occurred"
setclrfld.long 0x08 11. 0x28 11. 0x48 11. "  EF75_set/clr  ,State of event EVT75" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr  ,State of event EVT74" "Not occurred,Occurred"
setclrfld.long 0x08 9. 0x28 9. 0x48 9. "  EF73_set/clr  ,State of event EVT73" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr  ,State of event EVT72" "Not occurred,Occurred"
setclrfld.long 0x08 7. 0x28 7. 0x48 7. "  EF71_set/clr  ,State of event EVT71" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr  ,State of event EVT70" "Not occurred,Occurred"
setclrfld.long 0x08 5. 0x28 5. 0x48 5. "  EF69_set/clr  ,State of event EVT69" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr  ,State of event EVT68" "Not occurred,Occurred"
setclrfld.long 0x08 3. 0x28 3. 0x48 3. "  EF67_set/clr  ,State of event EVT67" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr  ,State of event EVT66" "Not occurred,Occurred"
setclrfld.long 0x08 1. 0x28 1. 0x48 1. "  EF65_set/clr  ,State of event EVT65" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr  ,State of event EVT64" "Not occurred,Occurred"
line.long 0x0c "EVTFLAG3,Event Flag Register 3"
setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred"
setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. "  EF126_set/clr ,State of event EVT126" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred"
setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. "  EF124_set/clr ,State of event EVT124" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred"
setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. "  EF122_set/clr ,State of event EVT122" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred"
setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. "  EF120_set/clr ,State of event EVT120" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred"
setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. "  EF118_set/clr ,State of event EVT118" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred"
setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. "  EF116_set/clr ,State of event EVT116" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred"
setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. "  EF97_set/clr  ,State of event EVT97" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr  ,State of event EVT96" "Not occurred,Occurred"
width 11.
group.long 0x80++0xf
line.long 0x00 "EVTMASK0,Event Mask Register 0"
bitfld.long 0x00 14. " EM14  ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 13. "  EM13  ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 12. "  EM12  ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 11. " EM11  ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 9. "  EM9   ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 8. "  EM8   ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 7. " EM7   ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 6. "  EM6   ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 5. "  EM5   ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 4. " EM4   ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 3. "  EM3   ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 2. "  EM2   ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 1. " EM1   ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 0. "  EM0   ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled"
line.long 0x04 "EVTMASK1,Event Mask Register 1"
bitfld.long 0x04 28. " EM60  ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 27. "  EM59  ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 24. "  EM56  ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 23. " EM55  ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 22. "  EM54  ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 21. "  EM53  ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 19. " EM51  ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 18. "  EM50  ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 17. "  EM49  ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 16. " EM48  ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 15. "  EM47  ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 11. "  EM43  ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 9. " EM41  ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 8. "  EM40  ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 7. "  EM39  ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 6. " EM38  ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 5. "  EM37  ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 4. "  EM36  ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 3. " EM35  ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 2. "  EM34  ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled"
line.long 0x08 "EVTMASK2,Event Mask Register 2"
bitfld.long 0x08 21. " EM85  ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 20. "  EM84  ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 19. "  EM83  ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 18. " EM82  ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 17. "  EM81  ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 16. "  EM80  ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 14. " EM78  ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 13. "  EM77  ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 12. "  EM76  ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 11. " EM75  ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 10. "  EM74  ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 9. "  EM73  ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 8. " EM72  ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 7. "  EM71  ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 6. "  EM70  ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 5. " EM69  ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 4. "  EM68  ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 3. "  EM67  ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 2. " EM66  ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 1. "  EM65  ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 0. "  EM64  ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled"
line.long 0x0c "EVTMASK3,Event Mask Register 3"
bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 30. "  EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 29. "  EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 27. "  EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 26. "  EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 24. "  EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 23. "  EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 21. "  EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 20. "  EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 1. "  EM97  ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 0. "  EM96  ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled"
group.long 0xc0++0xf
line.long 0x00 "EXPMASK0,Exception Mask Register 0"
bitfld.long 0x00 14. " XM14  ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 13. "  XM13  ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 12. "  XM12  ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 11. " XM11  ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 9. "  XM9   ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 8. "  XM8   ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 7. " XM7   ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 6. "  XM6   ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 5. "  XM5   ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 4. " XM4   ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 3. "  XM3   ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 2. "  XM2   ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 1. " XM1   ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 0. "  XM0   ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled"
line.long 0x04 "EXPMASK1,Exception Mask Register 1"
bitfld.long 0x04 28. " XM60  ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 27. "  XM59  ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 24. "  XM56  ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 23. " XM55  ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 22. "  XM54  ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 21. "  XM53  ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 19. " XM51  ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 18. "  XM50  ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 17. "  XM49  ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 16. " XM48  ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 15. "  XM47  ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 11. "  XM43  ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 9. " XM41  ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 8. "  XM40  ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 7. "  XM39  ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 6. " XM38  ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 5. "  XM37  ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 4. "  XM36  ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 3. " XM35  ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 2. "  XM34  ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled"
line.long 0x08 "EXPMASK2,Exception Mask Register 2"
bitfld.long 0x08 21. " XM85  ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 20. "  XM84  ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 19. "  XM83  ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 18. " XM82  ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 17. "  XM81  ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 16. "  XM80  ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 14. " XM78  ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 13. "  XM77  ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 12. "  XM76  ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 11. " XM75  ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 10. "  XM74  ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 9. "  XM73  ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 8. " XM72  ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 7. "  XM71  ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 6. "  XM70  ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 5. " XM69  ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 4. "  XM68  ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 3. "  XM67  ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 2. " XM66  ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 1. "  XM65  ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 0. "  XM64  ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled"
line.long 0x0c "EXPMASK3,Exception Mask Register 3"
bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 30. "  XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 29. "  XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 27. "  XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 26. "  XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 24. "  XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 23. "  XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 21. "  XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 20. "  XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 1. "  XM97  ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 0. "  XM96  ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled"
width 11.
rgroup.long 0xa0++0xf
line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0"
hexmask.long 0x00 0.--31. 1. " MEF[31:0]   ,Displays content of EF when EM=0"
line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1"
hexmask.long 0x04 0.--31. 1. " MEF[63:32]  ,Displays content of EF when EM=0"
line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2"
hexmask.long 0x08 0.--31. 1. " MEF[95:64]  ,Displays content of EF when EM=0"
line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3"
hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0"
rgroup.long 0xe0++0xf
line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0"
line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1"
line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2"
line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3"
width 11.
group.long 0x104++0xb
line.long 0x00 "INTMUX1,Interrupt Mux Register 1"
hexmask.long.byte 0x00 24.--30. 1. " INTSEL7  ,Number of the event that maps to CPUINT7"
hexmask.long.byte 0x00 16.--22. 1. "  INTSEL6  ,Number of the event that maps to CPUINT6"
hexmask.long.byte 0x00 8.--14. 1. "  INTSEL5  ,Number of the event that maps to CPUINT5"
hexmask.long.byte 0x00 0.--6. 1. "  INTSEL4  ,Number of the event that maps to CPUINT4"
line.long 0x04 "INTMUX2,Interrupt Mux Register 2"
hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11"
hexmask.long.byte 0x04 16.--22. 1. "  INTSEL10 ,Number of the event that maps to CPUINT10"
hexmask.long.byte 0x04 8.--14. 1. "  INTSEL9  ,Number of the event that maps to CPUINT9"
hexmask.long.byte 0x04 0.--6. 1. "  INTSEL8  ,Number of the event that maps to CPUINT8"
line.long 0x08 "INTMUX3,Interrupt Mux Register 3"
hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15"
hexmask.long.byte 0x08 16.--22. 1. "  INTSEL14 ,Number of the event that maps to CPUINT14"
hexmask.long.byte 0x08 8.--14. 1. "  INTSEL13 ,Number of the event that maps to CPUINT13"
hexmask.long.byte 0x08 0.--6. 1. "  INTSEL12 ,Number of the event that maps to CPUINT12"
rgroup.long 0x180++0x3
line.long 0x00 "INTXSTAT,Interrupt Exception Status Register"
hexmask.long.byte 0x00 24.--31. 1. " SYSINT   ,System Event number"
hexmask.long.byte 0x00 16.--23. 1. "  CPUINT   ,CPU interrupt number"
bitfld.long 0x00 0. "  DROP     ,Dropped event flag" "No event dropped,Event dropped"
width 11.
wgroup.long 0x184++0x3
line.long 0x00 "INTXCLR,Interrupt Exception Clear Register"
bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared"
rgroup.long 0x188++0x3
line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register"
bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 14. "  IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 13. "  IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored"
textline "                    "
bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 11. "  IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 10. "  IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored"
textline "                    "
bitfld.long 0x00 9. " IDM9  ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 8. "  IDM8  ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 7. "  IDM7  ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored"
textline "                    "
bitfld.long 0x00 6. " IDM6  ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 5. "  IDM5  ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 4. "  IDM4  ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored"
width 11.
group.long 0x140++0x07
line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers"
hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select"
hexmask.long.byte 0x00 16.--23. 1. "  AEGSEL2 ,Advanced Event Generator Select"
hexmask.long.byte 0x00 8.--15. 1. "  AEGSEL1 ,Advanced Event Generator Select"
hexmask.long.byte 0x00 0.--7. 1. "  AEGSEL0 ,Advanced Event Generator Select"
line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers"
hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select"
hexmask.long.byte 0x04 16.--23. 1. "  AEGSEL6 ,Advanced Event Generator Select"
hexmask.long.byte 0x04 8.--15. 1. "  AEGSEL5 ,Advanced Event Generator Select"
hexmask.long.byte 0x04 0.--7. 1. "  AEGSEL4 ,Advanced Event Generator Select"
width 0xb
tree.end
tree "Power-Down Controller"
width 8.
base d:0x01810000
group.long 0x00++0x3
line.long 0x00 "PDCCMD,Power-Down Controller Command Register"
bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode"
width 0xb
tree.end
tree.end
AUTOINDENT.POP
elif (CORENAME()=="C71X")
tree.close "Core Registers (c71x)"
sif (FILE.EXIST(~~/perc71x.per))
INCLUDE ~~/perc71x.per
else
base AVM:0x00000000
wgroup AVM:0x00++0
textline " Peripheral File Notification - "
sif (CORENAME()=="C75X")
button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files: perc75x.per"""
else
button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files: perc71x.per"""
endif
textline " ---------------------------------------------------------------"
textline " The peripheral file for this SoC cannot be displayed.          "
textline " Possible reasons are:                                          "
textline " - it is missing in the local installation or under development "
textline " - it is confidential                                           "
textline "                                                                "
textline " As fallback only the core registers are shown.                 "
textline " Please check    www.lauterbach.com/scripts.html                "
textline " or contact      support@lauterbach.com .                       "
textline "                                                                "
endif
tree.end
endif
AUTOINDENT.ON center tree
tree "_2_L_SerDes"
repeat 4. (list 0. 1. 2. 3. )(list ad:0x5000000 ad:0x5010000 ad:0x5020000 ad:0x5030000 )
tree "SERDES_16G$1"
base $2
rgroup.long 0x00++0x0B
line.long 0x00 "MACRO_ID_REG,"
hexmask.long.word 0x00 0.--15. 1. "MACRO_ID_TYPE,ASCII representation of sd for SerDes type"
line.long 0x04 "MACRO_ID_NUMBER_REG,"
hexmask.long.word 0x04 16.--31. 1. "MACRO_ID_NUMBER,Product family in binary coded decimal"
line.long 0x08 "MACRO_ID_REV_REG,Note this read-only field may vary from product to product"
hexmask.long.word 0x08 0.--15. 1. "MACRO_ID_REV,Revision number in binary coded decimal"
rgroup.long 0x10++0x0B
line.long 0x00 "MACRO_ID_NODE_REG__MACRO_ID_MFG_REG,Note this read-only field may vary from product to product"
hexmask.long.word 0x00 16.--31. 1. "MACRO_ID_NODE,Technology node in binary coded decimal"
newline
hexmask.long.word 0x00 0.--15. 1. "MACRO_ID_MFG,ASCII representation of the manufacturer"
line.long 0x04 "MACRO_ID_FLAVOR_REG,Note this read-only field may vary from product to product"
hexmask.long.word 0x04 0.--15. 1. "MACRO_ID_FLAVOR,ASCII representation of fc for finfet compact flavor"
line.long 0x08 "MACRO_ID_NUM_LANES_REG__MACRO_ID_IO_VOLTAGE_REG,Note this read-only field may vary from product to product"
hexmask.long.byte 0x08 24.--31. 1. "MACRO_ID_NUM_LANES_LEFT,The number of lanes on the left side of the common module in binary coded decimal"
newline
hexmask.long.byte 0x08 16.--23. 1. "MACRO_ID_NUM_LANES_RIGHT,The number of lanes on the right side of the common module in binary coded decimal"
newline
hexmask.long.word 0x08 0.--9. 1. "MACRO_ID_IO_VOLTAGE,Product I/O voltage ID in binary coded decimal"
rgroup.long 0x20++0x0B
line.long 0x00 "MACRO_ID_METAL_LAYERS_1_REG__MACRO_ID_METAL_LAYERS_0_REG,Note this read-only field may vary from product to product"
bitfld.long 0x00 28.--31. "MACRO_ID_XC,Number xc metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "MACRO_ID_XY,Number xy metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "MACRO_ID_Y,Number y metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "MACRO_ID_YY,Number yy metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "MACRO_ID_X,Number x metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MACRO_ID_XA,Number xa metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "MACRO_ID_XD,Number xd metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "MACRO_ID_XE,Number xe metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MACRO_ID_METAL_LAYERS_3_REG__MACRO_ID_METAL_LAYERS_2_REG,Note this read-only field may vary from product to product"
hexmask.long.byte 0x04 16.--23. 1. "MACRO_ID_XD_DIR,Direction of xd metal in ASCII format"
newline
bitfld.long 0x04 12.--15. "MACRO_ID_YZ,Number yz metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8.--11. "MACRO_ID_Z,Number z metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 4.--7. "MACRO_ID_R,Number r metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "MACRO_ID_U,Number u metals in stack up in binary decimal format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MACRO_ID_METAL_LAYERS_5_REG__MACRO_ID_METAL_LAYERS_4_REG,Note this read-only field may vary from product to product"
hexmask.long.byte 0x08 24.--31. 1. "MACRO_ID_XE3_DIR,Direction of second highest lowest xe metal in ASCII format"
newline
hexmask.long.byte 0x08 16.--23. 1. "MACRO_ID_XE4_DIR,Direction of highest xe metal in ASCII format"
newline
hexmask.long.byte 0x08 8.--15. 1. "MACRO_ID_XE1_DIR,Direction of lowest xe metal in ASCII format"
newline
hexmask.long.byte 0x08 0.--7. 1. "MACRO_ID_XE2_DIR,Direction of second lowest xe metal in ASCII format"
group.long 0x40++0x03
line.long 0x00 "CMN_PWRISO_OVRD_PREG__CMN_PWRISO_CTRL_PREG,Common power-gated supply island control register"
bitfld.long 0x00 28. "CMN_PWRISO_OVRD_EN_PREG,cmn power gate active high override enable" "0,1"
newline
bitfld.long 0x00 24. "CMN_PWRISO_ISOLATION_EN_OVRD_PREG,cmn power gate isolation override" "0,1"
newline
bitfld.long 0x00 20. "CMN_PWRISO_PHASE2EN_OVRD_PREG,cmn power gate phase2en override" "0,1"
newline
bitfld.long 0x00 16. "CMN_PWRISO_PHASE1EN_OVRD_PREG,cmn_pwriso power gate phase1en override" "0,1"
newline
bitfld.long 0x00 14. "CMN_PWRISO_PWRDN_DISABLE_PREG,Power down disable" "0,1"
newline
bitfld.long 0x00 4.--7. "CMN_PWRISO_EN_PH2DLY_PREG,Power enable phase 2 timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CMN_PWRISO_EN_PH1DLY_PREG,Power enable phase 1 timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x0B
line.long 0x00 "CMN_SSM_BIAS_TMR_PREG__CMN_SSM_BANDGAP_TMR_PREG,Startup State Machine bandgap enable timer register"
hexmask.long.word 0x00 16.--27. 1. "CMN_SSM_BIAS_TMR_VAL_PREG,Bias enable state timer value"
newline
hexmask.long.word 0x00 0.--11. 1. "CMN_SSM_BANDGAP_TMR_VAL_PREG,Bandgap enable state timer value"
line.long 0x04 "CMN_SSM_STATE_PREG__CMN_SSM_DIAG_PREG,Startup State Machine diagnostic register"
hexmask.long.word 0x04 16.--24. 1. "CMN_SSM_STATE,Startup state machine current state"
newline
bitfld.long 0x04 8. "CMN_SSM_DIAG_SKIP_AUTO_RECAL_PREG,Skip auto re-calibration enable : When this bit is active (1'b1) the auto calibration state will be skipped if it was previously run unless the macro is disabled or reset" "0,1"
newline
bitfld.long 0x04 0. "CMN_SSM_DIAG_SKIP_POST_BGEN_RECAL_PREG,Skip post bandgap enable re-calibration : When this bit is active (1'b1) the post bandgap enable calibration state will be skipped if it was previously run unless the macro is disabled or reset" "0,1"
line.long 0x08 "CMN_SMCSM_STATE_PREG,Startup State Machine Multi-cal State Machine current state register"
bitfld.long 0x08 0.--1. "CMN_SMCSM_STATE,Startup State Machine Multi-cal State Machine current state register" "0,1,2,3"
rgroup.long 0x80++0x47
line.long 0x00 "CMN_PLLLC_STATUS_B_PREG__CMN_PLLLC_STATUS_A_PREG,PLLCMNLC status register A"
hexmask.long.word 0x00 16.--25. 1. "CMN_PLLLC_STATUS_B_SSTWOPT_CODE,Main PLLLC Spread Spectrum two point value result"
newline
hexmask.long.byte 0x00 8.--14. 1. "CMN_PLLLC_STATUS_A_DSMCORR_CODE,PLLCMNLC DSM spur correction code result"
newline
bitfld.long 0x00 7. "CMN_PLLLC_STATUS_A_LOCKED,PLLCMNLC locked Status" "0,1"
newline
bitfld.long 0x00 6. "CMN_PLLLC_STATUS_A_DCOCAL_DONE,PLLCMNLC DCO calibration status" "0,1"
newline
bitfld.long 0x00 0.--5. "CMN_PLLLC_STATUS_A_DCOCAL_CODE,PLLCMNLC DCO calibration code result" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CMN_PLLLC_FBDIV_INT_PREG__CMN_PLLLC_GEN_PREG,PLLCMNLC general control register"
hexmask.long.word 0x04 16.--25. 1. "CMN_PLLLC_FBDIVINT_PREG,This value sets the mode dependent PLLCMNLC fbdivint value"
newline
bitfld.long 0x04 13. "CMN_PLLLC_LOCKED_OVRD_EN_PREG,PLLCMNLC locked active high override enable" "0,1"
newline
bitfld.long 0x04 12. "CMN_PLLLC_LOCKED_OVRD_PREG,PLLCMNLC locked signal force" "0,1"
newline
bitfld.long 0x04 9. "CMN_PLLLC_PLL_REG_ISO_OVRD_EN_PREG,PLLCMNLC regulator isolation active high override enable" "0,1"
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bitfld.long 0x04 8. "CMN_PLLLC_PLL_REG_ISO_OVRD_PREG,When cmn_plllc_pll_reg_iso_ovrd_en_preg is asserted high overrides the state dependent PLLCMNLC regulator isolation value" "0,1"
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bitfld.long 0x04 7. "CMN_PLLLC_LOCK_HOLD_OVRD_EN_PREG,Lock detection hold function active high override enable" "0,1"
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bitfld.long 0x04 6. "CMN_PLLLC_LOCK_HOLD_OVRD_PREG,When cmn_plllc_lock_hold_ovrd_en_preg is asserted high overrides the state dependent lock detect function value" "0,1"
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bitfld.long 0x04 5. "CMN_PLLLC_PLL_EN_OVRD_EN_PREG,PLLCMNLC enable active high override enable" "0,1"
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bitfld.long 0x04 4. "CMN_PLLLC_PLL_EN_OVRD_PREG,When cmn_plllc_pll_en_ovrd_en_preg is asserted high overrides the state dependent PLLCMNLC enable value" "0,1"
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bitfld.long 0x04 3. "CMN_PLLLC_PLL_RESET_N_OVRD_EN_PREG,PLLCMNLC active high reset override enable" "0,1"
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bitfld.long 0x04 2. "CMN_PLLLC_PLL_RESET_N_OVRD_PREG,When cmn_plllc_pll_reset_n_ovrd_en_preg is asserted high overrides the state dependent PLLCMNLC active low reset value" "0,1"
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bitfld.long 0x04 1. "CMN_PLLLC_PFDCLK1_SEL_PREG,When asserted the pfdclk1 is used as the reference clock When deasserted pfdclk is used" "0,1"
line.long 0x08 "CMN_PLLLC_DCOCAL_CTRL_PREG__CMN_PLLLC_FBDIV_FRAC_PREG,PLLCMNLC fractional feedback divider register"
bitfld.long 0x08 25. "CMN_PLLLC_DCOCAL_START_OVRD_EN_PREG,DCO calibration start active high override enable" "0,1"
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bitfld.long 0x08 24. "CMN_PLLLC_DCOCAL_START_OVRD_PREG,When cmn_plllc_dcocal_start_ovrd_en_preg is asserted high this value overrides the mode dependent DCO calibration start value" "0,1"
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bitfld.long 0x08 16.--21. "CMN_PLLLC_DCOCAL_STARTVAL_PREG,This value sets the DCO calibration startval value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 0.--15. 1. "CMN_PLLLC_FBDIVFRAC_PREG,This value sets the mode dependent PLLCMNLC fbdivfrac value"
line.long 0x0C "CMN_PLLLC_ITERTMR_PREG__CMN_PLLLC_INIT_PREG,PLLCMNLC DCO calibration initialization register"
hexmask.long.word 0x0C 16.--27. 1. "CMN_PLLLC_DCOCAL_ITERTMR_PREG,This value sets the DCO calibration iteration timer value"
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bitfld.long 0x0C 12.--14. "CMN_PLLLC_DCOCAL_INITSTEP_PREG,This value sets the DCO calibration initialization step value" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0C 0.--11. 1. "CMN_PLLLC_DCOCAL_INITTMR_PREG,This value sets the DCO calibration initialization timer value"
line.long 0x10 "CMN_PLLLC_LF_COEFF_MODE1_PREG__CMN_PLLLC_MODE_PREG,PLLCMNLC mode register"
bitfld.long 0x10 28.--30. "CMN_PLLLC_LF_PROPCOEFF_MODE1_PREG,This value sets the loop filter proportional coefficient value when cmn_plllc_mode is asserted" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 20.--24. "CMN_PLLLC_LF_PROPFRAC_MODE1_PREG,This value sets the loop filter fractional coefficient value when cmn_plllc_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16.--19. "CMN_PLLLC_LF_INTCOEFF_MODE1_PREG,This value sets the loop filter integer coefficient value when cmn_plllc_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8. "CMN_PLLLC_INTMODE_PREG,This value sets the integer mode value" "0,1"
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bitfld.long 0x10 0.--3. "CMN_PLLLC_TDCMODE_PREG,This value sets the TDC mode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CMN_PLLLC_LOCK_CNTSTART_PREG__CMN_PLLLC_LF_COEFF_MODE0_PREG,PLLCMNLC loop filter register for mode 0"
hexmask.long.word 0x14 16.--27. 1. "CMN_PLLLC_LOCK_CNTSTART_PREG,This value sets the lock counter start value"
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bitfld.long 0x14 12.--14. "CMN_PLLLC_LF_PROPCOEFF_MODE0_PREG,This value sets the loop filter proportional coefficient value when cmn_plllc_mode is deasserted" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4.--8. "CMN_PLLLC_LF_PROPFRAC_MODE0_PREG,This value sets the loop filter fractional coefficient value when cmn_plllc_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--3. "CMN_PLLLC_LF_INTCOEFF_MODE0_PREG,This value sets the loop filter integer coefficient value when cmn_plllc_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "CMN_PLLLC_CLK1_PREG__CMN_PLLLC_LOCK_CNTTHRESH_PREG,PLLCMNLC lock count threshold register"
bitfld.long 0x18 28. "CMN_PLLLC_CLK1_EN_PREG,This value sets the clock1 enable value" "0,1"
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hexmask.long.byte 0x18 16.--22. 1. "CMN_PLLLC_CLK1OUTDIV_PREG,This value sets the clock1 output divider value"
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hexmask.long.word 0x18 0.--11. 1. "CMN_PLLLC_LOCK_CNTTHRESH_PREG,PLLCMNLC lock counter threshold value"
line.long 0x1C "CMN_PLLLC_BWCAL_MODE1_PREG__CMN_PLLLC_CLK0_PREG,PLLCMNLC clock0 register"
bitfld.long 0x1C 31. "CMN_PLLLC_BWCAL_EN_MODE1_PREG,This value sets the bwcal enable value when cmn_plllc_mode is asserted" "0,1"
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bitfld.long 0x1C 24.--27. "CMN_PLLLC_BWCAL_THRESH_MODE1_PREG,This value sets the bwcal threshold value when cmn_plllc_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--20. "CMN_PLLLC_BWCAL_TMR_MODE1_PREG,This value sets the bwcal timer value when cmn_plllc_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 12. "CMN_PLLLC_CLK0_EN_PREG,This value sets the clock0 enable value" "0,1"
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hexmask.long.byte 0x1C 0.--6. 1. "CMN_PLLLC_CLK0OUTDIV_PREG,This value sets the clock0 output divider value"
line.long 0x20 "CMN_PLLLC_DSMCORR_PREG__CMN_PLLLC_BWCAL_MODE0_PREG,PLLCMNLC bandwidth cal register for mode 0"
bitfld.long 0x20 26. "CMN_PLLLC_DSMCORR_EN_PREG,This value sets the DSM spur correction coefficient enable value" "0,1"
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hexmask.long.byte 0x20 19.--25. 1. "CMN_PLLLC_DSMCORR_STARTVAL_PREG,This value sets the DSM spur correction coefficient startval value"
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bitfld.long 0x20 16.--18. "CMN_PLLLC_DSMCORR_GAIN_PREG,This value sets the DSM spur correction coefficient gain value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 15. "CMN_PLLLC_BWCAL_EN_MODE0_PREG,This value sets the bwcal enable value when cmn_plllc_mode is deasserted" "0,1"
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bitfld.long 0x20 8.--11. "CMN_PLLLC_BWCAL_THRESH_MODE0_PREG,This value sets the bwcal threhsold value when cmn_plllc_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--4. "CMN_PLLLC_BWCAL_TMR_MODE0_PREG,This value sets the bwcal timer value when cmn_plllc_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "CMN_PLLLC_SS_AMP_STEP_SIZE_PREG__CMN_PLLLC_SS_PREG,PLLCMNLC spread spectrum register"
hexmask.long.word 0x24 16.--27. 1. "CMN_PLLLC_SS_AMP_STEP_SIZE_PREG,This value sets the spread spectrum amp step size value"
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hexmask.long.byte 0x24 8.--14. 1. "CMN_PLLLC_SS_NUM_STEPS_PREG,This value sets the spread spectrum number of steps value"
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bitfld.long 0x24 7. "CMN_PLLLC_SS_ENABLE_PREG,This value sets the spread spectrum enable value" "0,1"
line.long 0x28 "CMN_PLLLC_LF_PROP_OVR_PREG__CMN_PLLLC_SSTWOPT_PREG,PLLCMNLC spread spectrum two point register"
bitfld.long 0x28 25. "CMN_PLLLC_LF_PROP_OVREN_PREG,Drives the lfprop_ovren pin on the PLLCMNLC" "0,1"
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hexmask.long.word 0x28 16.--24. 1. "CMN_PLLLC_LF_PROP_OVRVAL_PREG,Drives the lfprop_ovrval on the PLLCMNLC"
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bitfld.long 0x28 10. "CMN_PLLLC_SSTWOPT_EN_PREG,This value sets the sstwopt_en pin on the PLL" "0,1"
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hexmask.long.word 0x28 0.--9. 1. "CMN_PLLLC_SSTWOPT_STARTVAL_PREG,This value sets the sstwoopt_startval pins on the PLL"
line.long 0x2C "CMN_PLLLC_DSMCORR_OVR_PREG__CMN_PLLLC_LF_INT_OVR_PREG,PLLCMNLC debug and test loop filter integer override register"
bitfld.long 0x2C 23. "CMN_PLLLC_DSMCORR_OVREN_PREG,Drives the dsmcorr_ovren port on the PLLCMNLC" "0,1"
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hexmask.long.byte 0x2C 16.--22. 1. "CMN_PLLLC_DSMCORR_OVRVAL_PREG,Drives the dsmcorr_ovrval port on the PLLCMNLC"
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bitfld.long 0x2C 13. "CMN_PLLLC_LF_INT_OVREN_PREG,Drives the lf_int_ovren pin on the PLLCMNLC" "0,1"
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hexmask.long.word 0x2C 0.--12. 1. "CMN_PLLLC_LF_INT_OVRVAL_PREG,Drives the lf_int_ovrval pin on the PLLCMNLC"
line.long 0x30 "CMN_PLLLC_DCO_PREG__CMN_PLLLC_SSTWOPT_OVR_PREG,PLLCMNLC debug and test loop Spread Spectrum two point override register"
bitfld.long 0x30 30. "CMN_PLLLC_DCOCAL_OVREN_PREG,When asserted the cmnda_plllc_dcocal_ovren which drives the dcocal_ovren port on the PLLCMNLC is forced high" "0,1"
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bitfld.long 0x30 24.--29. "CMN_PLLLC_DCOCAL_OVRVAL_PREG,When cmnda_plllc_dcocal_ovren is asserted this value is driven onto cmnda_plllc_dcocal_ovrval which drives the dcocal_ovrval port on the PLLCMNLC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x30 19.--21. "CMN_PLLLC_DCO_ITRIM_PREG,Drives the DCO trim current on the PLLCMNLC" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 16.--18. "CMN_PLLLC_ROFFSET_PREG,DCO tank offset resistor trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 10. "CMN_PLLLC_SSTWOPT_OVREN_PREG,Drives the sstwopt_ovren port on the PLLCMNLC" "0,1"
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hexmask.long.word 0x30 0.--9. 1. "CMN_PLLLC_SSTWOPT_OVRVAL_PREG,Drives the sstwopt_ovrval port on the PLLCMNLC"
line.long 0x34 "CMN_PLLLCSM_STATUS_PREG__CMN_PLLLC_AVDD_PREG,PLLCMNLC debug and test avdd register"
hexmask.long.word 0x34 16.--29. 1. "CMN_PLLLCSM_STATE,State machine state register"
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bitfld.long 0x34 9.--11. "CMN_PLLLC_LFAVDDREG_VTRIM_PREG,Drives the lfavddreg_vtrim port on the PLLCMNLC" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 6.--8. "CMN_PLLLC_HFAVDDREG_VTRIM_PREG,Drives the hfavddreg_vtrim port on the PLLCMNLC" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 3.--5. "CMN_PLLLC_CLK1AVDDREG_VTRIM_PREG,Drives the clk1avddreg_vtrim port on the PLLCMNLC" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 0.--2. "CMN_PLLLC_CLK0AVDDREG_VTRIM_PREG,Drives the clk0avddreg_vtrim port on the PLLCMNLC" "0,1,2,3,4,5,6,7"
line.long 0x38 "CMN_PLLLCSM_PLLEN_TMR_PREG__CMN_PLLLCSM_CTRL_PREG,PLLCMNLC Control State Machine Control register"
hexmask.long.word 0x38 16.--27. 1. "CMN_PLLLCSM_PLLEN_TMR_VAL_PREG,PLL enable state timer value"
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bitfld.long 0x38 4. "CMN_PLLLCSM_FORCE_CAL_DONE_PREG,Asserting this bit immediately advances the State Machine from the PLLSM_CAL state currently in or once entered" "0,1"
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bitfld.long 0x38 0. "CMN_PLLLCSM_SKIP_PLL_CAL_RECAL_PREG,Skip PLL calibration re-calibration enable" "0,1"
line.long 0x3C "CMN_PLLLCSM_PLLVREF_TMR_PREG__CMN_PLLLCSM_PLLPRE_TMR_PREG,PLLCMNLC Control State Machine PLL pre-charge timer register"
hexmask.long.word 0x3C 16.--27. 1. "CMN_PLLLCSM_PLLVREF_TMR_VAL_PREG,PLL pre-charge state timer value"
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hexmask.long.word 0x3C 0.--11. 1. "CMN_PLLLCSM_PLLPRE_TMR_VAL_PREG,PLL pre-charge state timer value"
line.long 0x40 "CMN_PLLLC_STATUS_C_PREG__CMN_PLLLC_CLK2_PREG,PLLCMNLC clock2 register"
hexmask.long.byte 0x40 16.--23. 1. "CMN_PLLLC_STATUS_C_BWCAL_CODE,PLLCMNLC Band Width calibration code result"
newline
bitfld.long 0x40 12. "CMN_PLLLC_CLK2_EN_PREG,This value sets the clock2 enable value" "0,1"
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bitfld.long 0x40 8.--11. "CMN_PLLLC_CLK2OUTDIVFRAC_PREG,This value sets the clock2 fractional output divider's fraction value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x40 0.--6. 1. "CMN_PLLLC_CLK2OUTDIVINT_PREG,This value sets the clock2 fractional output divider's integer value"
line.long 0x44 "CMN_PLLLC_LOCK_DELAY_CTRL_PREG__CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG,PLLCMNLC spread spectrum Time Step Size Mode register"
hexmask.long.word 0x44 16.--24. 1. "CMN_PLLLC_LOCK_DELAY_PREG,This value sets a delay from internal lock assertion to assertion of cmn_plllc_locked"
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hexmask.long.byte 0x44 8.--14. 1. "CMN_PLLLC_SS_TIME_STEP_SIZE_MODE1_PREG,This value sets the spread spectrum time step size value when cmn_plllc_mode is asserted"
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hexmask.long.byte 0x44 0.--6. 1. "CMN_PLLLC_SS_TIME_STEP_SIZE_MODE0_PREG,This value sets the spread spectrum time step size value when cmn_plllc_mode is deasserted"
group.long 0xD0++0x1B
line.long 0x00 "SDOSCCAL_CTRL_PREG__CMN_SDOSC_OVRD_PREG,Signal detection oscillator override register"
bitfld.long 0x00 31. "SDOSCCAL_RUN_PREG,Signal detection oscillator calibration manual initiation active high enable" "0,1"
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bitfld.long 0x00 28.--30. "SDOSCCAL_INITSTEP_PREG,Signal detection oscillator calibration initial step size" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 22. "SDOSCCAL_DONE,Signal detection oscillator calibration active high complete flag" "0,1"
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rbitfld.long 0x00 16.--21. "SDOSCCAL_CODE,Signal detection oscillator calibration result" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4. "CMN_SDOSC_EN_OVRD_EN_PREG,Active high override enable for the signal detection oscillator circuit enable" "0,1"
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bitfld.long 0x00 0. "CMN_SDOSC_EN_OVRD_VAL_PREG,When cmn_sdosc_en_ovrd_en_preg is asserted this value drives the cmnda_sdosc_en circuit enable" "0,1"
line.long 0x04 "SDOSCCAL_INIT_TMR_PREG__SDOSCCAL_OVR_PREG,Signal detection oscillator calibration override register"
hexmask.long.byte 0x04 16.--23. 1. "SDOSCCAL_INITTMR_PREG,Signal detection calibration initial wait timer to allow the analog circuits to settle on initiation of the calibration sequence"
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bitfld.long 0x04 15. "SDOSCCAL_OVREN_PREG,Signal detection oscillator override active high enable" "0,1"
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bitfld.long 0x04 0.--5. "SDOSCCAL_OVRVAL_PREG,When sdosccal_ovren_pregis asserted high this value is used by the Signal detection oscillator rather than the calibration engine result" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "SDOSCCAL_TMR_PREG__SDOSCCAL_ITER_TMR_PREG,Signal detection oscillator calibration iteration timer register"
hexmask.long.word 0x08 16.--25. 1. "SDOSCCAL_TMRVAL_PREG,This value sets the Signal detection oscillator frequency evaluation time"
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hexmask.long.byte 0x08 0.--7. 1. "SDOSCCAL_ITERTMR_PREG,Signal detection calibration wait timer to allow the analog circuits to settle to the new frequency after a calibration code change"
line.long 0x0C "SDOSCCAL_START_PREG__SDOSCCAL_CLK_CNT_PREG,Signal detection oscillator calibration oscillator clock count target register"
bitfld.long 0x0C 16.--21. "SDOSCCAL_STARTVAL_PREG,This value sets the Signal detection oscillator calibration starting code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x0C 0.--9. 1. "SDOSCCAL_CLKCNT_PREG,This value sets the Signal detection oscillator expected clock count target"
line.long 0x10 "PROCMON_STATUS_PREG__PROCMON_CTRL_PREG,Process Monitor control register"
rbitfld.long 0x10 31. "PROCMON_DONE,Active high process monitor ring oscillator count complete flag" "0,1"
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rbitfld.long 0x10 29. "PROCMON_CNT_OVERNOM,When asserted this bit indicates the process monitor ring oscillator counter reached the value expected for a nominal PVT part as established by procmon_rocnt_preg" "0,1"
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hexmask.long.word 0x10 16.--28. 1. "PROCMON_CNT_VAL,Process monitor ring oscillator counter value"
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bitfld.long 0x10 15. "PROCMON_RUN_PREG,Active high process monitor counter start" "0,1"
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bitfld.long 0x10 13.--14. "PROCMON_ROSEL_PREG,Process monitor ring oscillator select" "0,1,2,3"
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hexmask.long.word 0x10 0.--12. 1. "PROCMON_ROCNT_PREG,Expected oscillator clocks counted for nominal process at typical conditions"
line.long 0x14 "PROCMON_CNTWAIT_PREG__PROCMON_INITWAIT_PREG,Process Monitor initial wait timer register"
hexmask.long.word 0x14 16.--28. 1. "PROCMON_CNTWAIT_TMRVAL_PREG,Time to count the selected ring oscillator clocks"
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bitfld.long 0x14 0.--2. "PROCMON_INITWAIT_TMRVAL_PREG,Nominal number of cmn_refclk_gated clock periods to wait while the analog circuit powers up and the enabled ring oscillator settles" "0,1,2,3,4,5,6,7"
line.long 0x18 "PROCMON_DIAGNOSTIC_PREG__PROCMON_OVRD_PREG,Process monitor override register"
rbitfld.long 0x18 16.--21. "PROCMON_FSM_STATE,Process monitor state machine state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 8. "PROCMON_OVRD_EN_PREG,Active high analog control override enable" "0,1"
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bitfld.long 0x18 5. "PROCMON_OVRD_ISOAVDD_EN_PREG,When procmon_ovrd_en_preg is asserted this value overrides the analog circuit's power gate enable cmnda_pmc_isoavdd_en" "0,1"
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bitfld.long 0x18 4. "PROCMON_OVRD_ISOAVDD_FWEN_N_PREG,When procmon_ovrd_en_preg is asserted this value overrides the power gate isolation control cmnda_pmc_isoavdd_fwen_n" "0,1"
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bitfld.long 0x18 3. "PROCMON_OVRD_LVT_EN_PREG,When procmon_ovrd_en_preg is asserted this value overrides the analog circuit's LVT ring oscillator enable cmnda_pmc_lvt_en" "0,1"
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bitfld.long 0x18 2. "PROCMON_OVRD_SVT_EN_PREG,When procmon_ovrd_en_preg is asserted this value overrides the analog circuit's SVT ring oscillator enable cmnda_pmc_svt_en" "0,1"
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bitfld.long 0x18 1. "PROCMON_OVRD_THICKOX_EN_PREG,When procmon_ovrd_en_preg is asserted this value overrides the analog circuit's thick oxide ring oscillator enable cmnda_pmc_thickox_en" "0,1"
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bitfld.long 0x18 0. "PROCMON_OVRD_ULVT_EN_PREG,When procmon_ovrd_en_preg is asserted this value overrides the analog circuit's ULVT ring oscillator enable cmnda_pmc_ulvt_en" "0,1"
rgroup.long 0x100++0x13
line.long 0x00 "CMN_CTRL_DIAG_RESET_PREG__CDB_DIAG_PREG,CDB diagnostic register"
bitfld.long 0x00 19. "CMN_RESET_SYNC_N,Current state of the cmn_reset_sync_n reset" "0,1"
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bitfld.long 0x00 18. "CMNDA_RSTREL_RST_N,Current state of the cmnda_rstrel_rst_n reset" "0,1"
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bitfld.long 0x00 17. "CMNDA_PLLLC1_RST_N,Current state of the cmnda_plllc1_rst_n reset" "0,1"
newline
bitfld.long 0x00 16. "CMNDA_PLLLC_RST_N,Current state of the cmnda_plllc_rst_n reset" "0,1"
newline
bitfld.long 0x00 0. "CDB_PSLVERR_REG,CDB bus error" "0,1"
line.long 0x04 "CMN_FUNC_DIAG_RESET_PREG,Common functions submodule reset diagnostic register"
bitfld.long 0x04 7. "CMN_ATBDIG_RST_N,Current state of the cmn_atbdig_rst_n reset" "0,1"
newline
bitfld.long 0x04 6. "CMN_RESCAL_RST_N,Current state of the cmn_rescal_rst_n reset" "0,1"
newline
bitfld.long 0x04 5. "PROCMON_RST_N,Current state of the procmon_rst_n reset" "0,1"
newline
bitfld.long 0x04 4. "SDOSCCAL_RST_N,Current state of the sdosccal_rst_n reset" "0,1"
newline
bitfld.long 0x04 3. "SDOSCCAL_CNTRST_N,Current state of the sdosccal_cntrst_n reset" "0,1"
newline
bitfld.long 0x04 2. "CMN_HSRRSM_RST_N,Current state of the cmn_hsrrsm_rst_n reset" "0,1"
newline
bitfld.long 0x04 1. "PROCMON_PMCRST_N,Current state of the procmon_pmcrst_n reset" "0,1"
newline
bitfld.long 0x04 0. "SCANOVRD_ATBADC_RST_N,Current state of the scanovrd_atbadc_rst_n reset" "0,1"
line.long 0x08 "CMN_CMSMT_REF_CLK_TMR_VALUE_PREG__CMN_CLK_FREQ_MSMT_CTRL_PREG,Common clock frequency measurement control register"
hexmask.long.word 0x08 16.--27. 1. "CMN_CMSMT_REF_CLK_TMR_VALUE_PREG,Reference clock timer value"
newline
bitfld.long 0x08 1.--3. "CMN_TEST_CLK_SEL_PREG,Test clock selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "CMN_CMSMT_MEASUREMENT_RUN_PREG,Test clock measurement active high enable" "0,1"
line.long 0x0C "CMN_CLK_FREQ_MSMT_OBS_PREG__CMN_CMSMT_TEST_CLK_CNT_VALUE_PREG,Common clock frequency measurement result register"
bitfld.long 0x0C 16. "CMN_CMSMT_MEASUREMENT_DONE,Test clock measurement done" "0,1"
newline
hexmask.long.word 0x0C 0.--11. 1. "CMN_CMSMT_TEST_CLK_CNT_VALUE,Test clock counter value"
line.long 0x10 "CMN_SPARE_REG_PREG,Common spare registers to analog"
hexmask.long.word 0x10 0.--15. 1. "SPARE_PREG,Spare register bits assigned to cmnda_sparecdb"
group.long 0x120++0x07
line.long 0x00 "CMN_BIAS_TRIM_PREG__CMN_BIAS_EN_OVRD_PREG,Bias diagnostic override register"
hexmask.long.word 0x00 16.--30. 1. "CMN_BIAS_TRIM_PREG,Drives the cmn_ana_bias block's thermometer encoded bus"
newline
bitfld.long 0x00 1. "CMN_BIAS_EN_OVRD_EN_PREG,cmn_ana_bias enable active high override enable" "0,1"
newline
bitfld.long 0x00 0. "CMN_BIAS_EN_OVRD_VAL_PREG,When cmn_bias_en_ovrd_en_preg is asserted high this value overrides the normal mission-mode bias enable" "0,1"
line.long 0x04 "CMN_BIAS_VREF_TRIM_PREG,Bias debug and test voltage reference trim register"
bitfld.long 0x04 12. "CMN_BIAS_VREFSEL_PREG,Drives the cmn_ana_bias block vrefsel to select for voltage reference source" "0,1"
newline
hexmask.long.word 0x04 0.--11. 1. "CMN_BIAS_VREFTRIM_PREG,Drives the cmn_ana_bias block's vreftrim setting the resistor ladder voltage reference trim"
group.long 0x130++0x03
line.long 0x00 "CMN_PSMCLK_SDOSCSEL_CTRL_PREG__CMN_REFRCV_PREG,Reference clock receiver register"
bitfld.long 0x00 16. "CMN_PSMCLK_SDOSCSEL_PREG,cmn_psmclk_out source select" "0,1"
newline
bitfld.long 0x00 13.--14. "CMN_REFRCV_BWVAL_PREG,Bus to control the receiver bandwidth" "0,1,2,3"
newline
bitfld.long 0x00 12. "CMN_REFRCV_REFCLK_TESTCLKEN_PREG,Active high enable for CMOS only path from cmn_refclk_p to the digital" "0,1"
newline
bitfld.long 0x00 8. "CMN_REFRCV_REFCLK_PLLLC1EN_PREG,Active high enable for refclk driver to PLLCMNLC1" "0,1"
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bitfld.long 0x00 0. "CMN_REFRCV_REFCLK_TERMEN_PREG,Active high termination enable for the refclk receiver" "0,1"
group.long 0x140++0x07
line.long 0x00 "CMN_RESCAL_CTRLB_PREG__CMN_RESCAL_CTRLA_PREG,Resistor calibration debug and test control register A"
bitfld.long 0x00 25. "CMN_RESCAL_RXOVREN_PREG,RX resistor calibration LUT value active high override enable" "0,1"
newline
bitfld.long 0x00 21.--24. "CMN_RESCAL_RXOVRVAL_PREG,When cmn_rescal_rxovren_preg is asserted this value overrides the RX resistor calibration LUT value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20. "CMN_RESCAL_TXOVREN_PREG,TX resistor calibration LUT value active high override enable" "0,1"
newline
bitfld.long 0x00 16.--19. "CMN_RESCAL_TXOVRVAL_PREG,When cmn_rescal_txovren_preg is asserted this value overrides the TX resistor calibration LUT value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 15. "CMN_RESCAL_DONE,Resistor calibration active high done flag" "0,1"
newline
bitfld.long 0x00 12.--14. "CMN_RESCAL_INITTMR_PREG,Sets the value of the timer used to allow the clock to settle at startup and before incrementing calibration code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--11. "CMN_RESCAL_RXOFFSET_PREG,Twos compliment offset to be added to the calibrated resistor code prior to the receive LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "CMN_RESCAL_TXOFFSET_PREG,Twos compliment offset to be added to the calibrated resistor code prior to the transmit LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CMN_RESCAL_STATUS_PREG__CMN_RESCAL_OVRD_PREG,Resistor diagnostic override register"
hexmask.long.byte 0x04 16.--22. 1. "CMN_RESCAL_STATE,Resistor calibration FSM state vector"
newline
bitfld.long 0x04 4. "CMN_RESCAL_EN_FORCE_PREG,Resistor calibration analog enable force" "0,1"
newline
bitfld.long 0x04 0. "CMN_RESCAL_RUN_OVRD_PREG,Resistor calibration active high run override" "0,1"
group.long 0x150++0x07
line.long 0x00 "CMN_ATB_ADC_PREG__CMN_ATB_CTRL_PREG,ATB debug and test control register"
bitfld.long 0x00 31. "CMN_ATB_ADC_START_PREG,Active high signal that initiates the ADC to convert the ATB analog signal" "0,1"
newline
rbitfld.long 0x00 30. "CMN_ATB_ADC_DONE,Active high flag indicating current conversion is complete" "0,1"
newline
bitfld.long 0x00 27.--29. "CMN_ATB_ADC_MODE_PREG,Drives the mode port on the ADC selecting the input mux configuration as follows" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 16.--23. 1. "CMN_ATB_ADC_CODE,Current conversion results of the analog value on the ATB"
newline
bitfld.long 0x00 15. "CMN_ATB_CTRL_ATBEN_PREG,Internal ATB active high enable" "0,1"
newline
bitfld.long 0x00 14. "CMN_ATB_CTRL_BUMP_CON_EN_PREG,ATB bump connection active high enable" "0,1"
newline
bitfld.long 0x00 13. "CMN_ATB_CTRL_REGION_SEL_PREG,ATB region select" "0,1"
newline
bitfld.long 0x00 9.--12. "CMN_ATB_CTRL_LANE_SEL_PREG,ATB lane select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--8. "CMN_ATB_CTRL_COMPONENT_SEL_PREG,ATB component select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--3. "CMN_ATB_CTRL_ATBSEL_PREG,ATB test point select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CMN_CORE_ATB_EN_PREG__CMN_ATB_ADC_EN_TMR_PREG,ATB debug and test ADC enable and timer register"
bitfld.long 0x04 16. "CMN_CORE_ATBESD_EN_PREG,Core ATB pin connection active high enable" "0,1"
newline
bitfld.long 0x04 10. "CMN_ATB_ADC_EN_PREG,ADC enable force overriding state dependent enable" "0,1"
newline
hexmask.long.word 0x04 0.--9. 1. "CMN_ATB_ADC_EN_TMR_PREG,Enable timer value"
group.long 0x160++0x03
line.long 0x00 "HSRRSM_STATUS_PREG__HSRRSM_CTRL_PREG,High Speed Reset Release State Machine control register"
rbitfld.long 0x00 16.--18. "HSRRSM_STATE,High Speed Reset Release State Machine state vector" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "HSRRSM_DELAY_PREG,Reset delay" "0,1,2,3,4,5,6,7"
group.long 0x170++0x03
line.long 0x00 "CMN_REFRCV1_PREG,Auxiliary reference clock receiver (refrcv1) register"
bitfld.long 0x00 13.--14. "CMN_REFRCV1_BWVAL_PREG,Bus to control the receiver bandwidth" "0,1,2,3"
newline
bitfld.long 0x00 12. "CMN_REFRCV1_REFCLK_TESTCLKEN_PREG,Active high enable for CMOS only path from cmn_refclk1_p to the digital" "0,1"
newline
bitfld.long 0x00 8. "CMN_REFRCV1_REFCLK_PLLLC1EN_PREG,Active high enable for refclk1 driver to PLLCMNLC" "0,1"
newline
bitfld.long 0x00 0. "CMN_REFRCV1_REFCLK_TERMEN_PREG,Active high termination enable for the refclk1 receiver" "0,1"
rgroup.long 0x180++0x47
line.long 0x00 "CMN_PLLLC1_STATUS_B_PREG__CMN_PLLLC1_STATUS_A_PREG,PLLCMNLC1 status register A"
hexmask.long.word 0x00 16.--25. 1. "CMN_PLLLC1_STATUS_B_SSTWOPT_CODE,Main PLLLC1 Spread Spectrum two point value result"
newline
hexmask.long.byte 0x00 8.--14. 1. "CMN_PLLLC1_STATUS_A_DSMCORR_CODE,PLLCMNLC1 DSM spur correction code result"
newline
bitfld.long 0x00 7. "CMN_PLLLC1_STATUS_A_LOCKED,PLLCMNLC1 locked Status" "0,1"
newline
bitfld.long 0x00 6. "CMN_PLLLC1_STATUS_A_DCOCAL_DONE,PLLCMNLC1 DCO calibration status" "0,1"
newline
bitfld.long 0x00 0.--5. "CMN_PLLLC1_STATUS_A_DCOCAL_CODE,PLLCMNLC1 DCO calibration code result" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CMN_PLLLC1_FBDIV_INT_PREG__CMN_PLLLC1_GEN_PREG,PLLCMNLC1 general control register"
hexmask.long.word 0x04 16.--25. 1. "CMN_PLLLC1_FBDIVINT_PREG,This value sets the mode dependent PLLCMNLC1 fbdivint value"
newline
bitfld.long 0x04 13. "CMN_PLLLC1_LOCKED_OVRD_EN_PREG,PLLCMNLC1 locked active high override enable" "0,1"
newline
bitfld.long 0x04 12. "CMN_PLLLC1_LOCKED_OVRD_PREG,PLLCMNLC locked signal force" "0,1"
newline
bitfld.long 0x04 9. "CMN_PLLLC1_PLL_REG_ISO_OVRD_EN_PREG,PLLCMNLC1 regulator isolation active high override enable" "0,1"
newline
bitfld.long 0x04 8. "CMN_PLLLC1_PLL_REG_ISO_OVRD_PREG,When cmn_plllc1_pll_reg_iso_ovrd_en_preg is asserted high overrides the state dependent PLLCMNLC1 regulator isolation value" "0,1"
newline
bitfld.long 0x04 7. "CMN_PLLLC1_LOCK_HOLD_OVRD_EN_PREG,Lock detection hold function active high override enable" "0,1"
newline
bitfld.long 0x04 6. "CMN_PLLLC1_LOCK_HOLD_OVRD_PREG,When cmn_plllc1_lock_hold_ovrd_en_preg is asserted high overrides the state dependent lock detect function value" "0,1"
newline
bitfld.long 0x04 5. "CMN_PLLLC1_PLL_EN_OVRD_EN_PREG,PLLCMNLC1 enable active high override enable" "0,1"
newline
bitfld.long 0x04 4. "CMN_PLLLC1_PLL_EN_OVRD_PREG,When cmn_plllc1_pll_en_ovrd_en_preg is asserted high overrides the state dependent PLLCMNLC1 enable value" "0,1"
newline
bitfld.long 0x04 3. "CMN_PLLLC1_PLL_RESET_N_OVRD_EN_PREG,PLLCMNLC1 active high reset override enable" "0,1"
newline
bitfld.long 0x04 2. "CMN_PLLLC1_PLL_RESET_N_OVRD_PREG,When cmn_plllc1_pll_reset_n_ovrd_en_preg is asserted high overrides the state dependent PLLCMNLC1 active low reset value" "0,1"
newline
bitfld.long 0x04 1. "CMN_PLLLC1_PFDCLK1_SEL_PREG,When asserted the pfdclk1 is used as the reference clock When deasserted pfdclk is used" "0,1"
line.long 0x08 "CMN_PLLLC1_DCOCAL_CTRL_PREG__CMN_PLLLC1_FBDIV_FRAC_PREG,PLLCMNLC1 fractional feedback divider register"
bitfld.long 0x08 25. "CMN_PLLLC1_DCOCAL_START_OVRD_EN_PREG,DCO calibration start active high override enable" "0,1"
newline
bitfld.long 0x08 24. "CMN_PLLLC1_DCOCAL_START_OVRD_PREG,When cmn_plllc1_dcocal_start_ovrd_en_preg is asserted high this value overrides the mode dependent DCO calibration start value" "0,1"
newline
bitfld.long 0x08 16.--21. "CMN_PLLLC1_DCOCAL_STARTVAL_PREG,This value sets the DCO calibration startval value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x08 0.--15. 1. "CMN_PLLLC1_FBDIVFRAC_PREG,This value sets the mode dependent PLLCMNLC1 fbdivfrac value"
line.long 0x0C "CMN_PLLLC1_ITERTMR_PREG__CMN_PLLLC1_INIT_PREG,PLLCMNLC1 DCO calibration initialization register"
hexmask.long.word 0x0C 16.--27. 1. "CMN_PLLLC1_DCOCAL_ITERTMR_PREG,This value sets the DCO calibration iteration timer value"
newline
bitfld.long 0x0C 12.--14. "CMN_PLLLC1_DCOCAL_INITSTEP_PREG,This value sets the DCO calibration initialization step value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--11. 1. "CMN_PLLLC1_DCOCAL_INITTMR_PREG,This value sets the DCO calibration initialization timer value"
line.long 0x10 "CMN_PLLLC1_LF_COEFF_MODE1_PREG__CMN_PLLLC1_MODE_PREG,PLLCMNLC1 mode register"
bitfld.long 0x10 28.--30. "CMN_PLLLC1_LF_PROPCOEFF_MODE1_PREG,This value sets the loop filter proportional coefficient value when cmn_plllc1_mode is asserted" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--24. "CMN_PLLLC1_LF_PROPFRAC_MODE1_PREG,This value sets the loop filter fractional coefficient value when cmn_plllc1_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--19. "CMN_PLLLC1_LF_INTCOEFF_MODE1_PREG,This value sets the loop filter integer coefficient value when cmn_plllc1_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 8. "CMN_PLLLC1_INTMODE_PREG,This value sets the integer mode value" "0,1"
newline
bitfld.long 0x10 0.--3. "CMN_PLLLC1_TDCMODE_PREG,This value sets the TDC mode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CMN_PLLLC1_LOCK_CNTSTART_PREG__CMN_PLLLC1_LF_COEFF_MODE0_PREG,PLLCMNLC1 loop filter register for mode 0"
hexmask.long.word 0x14 16.--27. 1. "CMN_PLLLC1_LOCK_CNTSTART_PREG,This value sets the lock counter start value"
newline
bitfld.long 0x14 12.--14. "CMN_PLLLC1_LF_PROPCOEFF_MODE0_PREG,This value sets the loop filter proportional coefficient value when cmn_plllc1_mode is deasserted" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 4.--8. "CMN_PLLLC1_LF_PROPFRAC_MODE0_PREG,This value sets the loop filter fractional coefficient value when cmn_plllc1_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 0.--3. "CMN_PLLLC1_LF_INTCOEFF_MODE0_PREG,This value sets the loop filter integer coefficient value when cmn_plllc1_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "CMN_PLLLC1_CLK1_PREG__CMN_PLLLC1_LOCK_CNTTHRESH_PREG,PLLCMNLC1 lock count threshold register"
bitfld.long 0x18 28. "CMN_PLLLC1_CLK1_EN_PREG,This value sets the clock1 enable value" "0,1"
newline
hexmask.long.byte 0x18 16.--22. 1. "CMN_PLLLC1_CLK1OUTDIV_PREG,This value sets the clock1 output divider value"
newline
hexmask.long.word 0x18 0.--11. 1. "CMN_PLLLC1_LOCK_CNTTHRESH_PREG,PLLCMNLC1 lock counter threshold value"
line.long 0x1C "CMN_PLLLC1_BWCAL_MODE1_PREG__CMN_PLLLC1_CLK0_PREG,PLLCMNLC1 clock0 register"
bitfld.long 0x1C 31. "CMN_PLLLC1_BWCAL_EN_MODE1_PREG,This value sets the bwcal enable value when cmn_plllc1_mode is asserted" "0,1"
newline
bitfld.long 0x1C 24.--27. "CMN_PLLLC1_BWCAL_THRESH_MODE1_PREG,This value sets the bwcal threshold value when cmn_plllc1_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 16.--20. "CMN_PLLLC1_BWCAL_TMR_MODE1_PREG,This value sets the bwcal timer value when cmn_plllc1_mode is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 12. "CMN_PLLLC1_CLK0_EN_PREG,This value sets the clock0 enable value" "0,1"
newline
hexmask.long.byte 0x1C 0.--6. 1. "CMN_PLLLC1_CLK0OUTDIV_PREG,This value sets the clock0 output divider value"
line.long 0x20 "CMN_PLLLC1_DSMCORR_PREG__CMN_PLLLC1_BWCAL_MODE0_PREG,PLLCMNLC1 bandwidth cal register for mode 0"
bitfld.long 0x20 26. "CMN_PLLLC1_DSMCORR_EN_PREG,This value sets the DSM spur correction coefficient enable value" "0,1"
newline
hexmask.long.byte 0x20 19.--25. 1. "CMN_PLLLC1_DSMCORR_STARTVAL_PREG,This value sets the DSM spur correction coefficient startval value"
newline
bitfld.long 0x20 16.--18. "CMN_PLLLC1_DSMCORR_GAIN_PREG,This value sets the DSM spur correction coefficient gain value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 15. "CMN_PLLLC1_BWCAL_EN_MODE0_PREG,This value sets the bwcal enable value when cmn_plllc1_mode is deasserted" "0,1"
newline
bitfld.long 0x20 8.--11. "CMN_PLLLC1_BWCAL_THRESH_MODE0_PREG,This value sets the bwcal threshold value when cmn_plllc1_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--4. "CMN_PLLLC1_BWCAL_TMR_MODE0_PREG,This value sets the bwcal timer value when cmn_plllc1_mode is deasserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "CMN_PLLLC1_SS_AMP_STEP_SIZE_PREG__CMN_PLLLC1_SS_PREG,PLLCMNLC1 spread spectrum register"
hexmask.long.word 0x24 16.--27. 1. "CMN_PLLLC1_SS_AMP_STEP_SIZE_PREG,This value sets the spread spectrum amp step size value"
newline
hexmask.long.byte 0x24 8.--14. 1. "CMN_PLLLC1_SS_NUM_STEPS_PREG,This value sets the spread spectrum number of steps value"
newline
bitfld.long 0x24 7. "CMN_PLLLC1_SS_ENABLE_PREG,This value sets the spread spectrum enable value" "0,1"
line.long 0x28 "CMN_PLLLC1_LF_PROP_OVR_PREG__CMN_PLLLC1_SSTWOPT_PREG,PLLCMNLC1 spread spectrum two point register"
bitfld.long 0x28 25. "CMN_PLLLC1_LF_PROP_OVREN_PREG,Drives the lfprop_ovren pin on the PLLCMNLC1" "0,1"
newline
hexmask.long.word 0x28 16.--24. 1. "CMN_PLLLC1_LF_PROP_OVRVAL_PREG,Drives the lfprop_ovrval on the PLLCMNLC1"
newline
bitfld.long 0x28 10. "CMN_PLLLC1_SSTWOPT_EN_PREG,This value sets the sstwopt_en pin on the PLL" "0,1"
newline
hexmask.long.word 0x28 0.--9. 1. "CMN_PLLLC1_SSTWOPT_STARTVAL_PREG,This value sets the sstwoopt_startval pins on the PLL"
line.long 0x2C "CMN_PLLLC1_DSMCORR_OVR_PREG__CMN_PLLLC1_LF_INT_OVR_PREG,PLLCMNLC1 debug and test loop filter integer override register"
bitfld.long 0x2C 23. "CMN_PLLLC1_DSMCORR_OVREN_PREG,Drives the dsmcorr_ovren port on the PLLCMNLC1" "0,1"
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hexmask.long.byte 0x2C 16.--22. 1. "CMN_PLLLC1_DSMCORR_OVRVAL_PREG,Drives the dsmcorr_ovrval port on the PLLCMNLC1"
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bitfld.long 0x2C 13. "CMN_PLLLC1_LF_INT_OVREN_PREG,Drives the lf_int_ovren pin on the PLLCMNLC1" "0,1"
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hexmask.long.word 0x2C 0.--12. 1. "CMN_PLLLC1_LF_INT_OVRVAL_PREG,Drives the lf_int_ovrval pin on the PLLCMNLC1"
line.long 0x30 "CMN_PLLLC1_DCO_PREG__CMN_PLLLC1_SSTWOPT_OVR_PREG,PLLCMNLC1 debug and test loop Spread Spectrum two point override register"
bitfld.long 0x30 30. "CMN_PLLLC1_DCOCAL_OVREN_PREG,When asserted the cmnda_plllc1_dcocal_ovren which drives the dcocal_ovren port on the PLLCMNLC1 is forced high" "0,1"
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bitfld.long 0x30 24.--29. "CMN_PLLLC1_DCOCAL_OVRVAL_PREG,When cmnda_plllc1_dcocal_ovren is asserted this value is driven onto cmnda_plllc1_dcocal_ovrval which drives the dcocal_ovrval port on the PLLCMNLC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x30 19.--21. "CMN_PLLLC1_DCO_ITRIM_PREG,Drives the DCO trim current on the PLLCMNLC1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 16.--18. "CMN_PLLLC1_ROFFSET_PREG,DCO tank offset resistor trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 10. "CMN_PLLLC1_SSTWOPT_OVREN_PREG,Drives the sstwopt_ovren port on the PLLCMNLC1" "0,1"
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hexmask.long.word 0x30 0.--9. 1. "CMN_PLLLC1_SSTWOPT_OVRVAL_PREG,Drives the sstwopt_ovrval port on the PLLCMNLC1"
line.long 0x34 "CMN_PLLLCSM1_STATUS_PREG__CMN_PLLLC1_AVDD_PREG,PLLCMNLC1 debug and test avdd register"
hexmask.long.word 0x34 16.--29. 1. "CMN_PLLLCSM1_STATE,State machine state register"
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bitfld.long 0x34 9.--11. "CMN_PLLLC1_LFAVDDREG_VTRIM_PREG,Drives the lfavddreg_vtrim port on the PLLCMNLC1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 6.--8. "CMN_PLLLC1_HFAVDDREG_VTRIM_PREG,Drives the hfavddreg_vtrim port on the PLLCMNLC1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 3.--5. "CMN_PLLLC1_CLK1AVDDREG_VTRIM_PREG,Drives the clk1avddreg_vtrim port on the PLLCMNLC1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 0.--2. "CMN_PLLLC1_CLK0AVDDREG_VTRIM_PREG,Drives the clk0avddreg_vtrim port on the PLLCMNLC1" "0,1,2,3,4,5,6,7"
line.long 0x38 "CMN_PLLLCSM1_PLLEN_TMR_PREG__CMN_PLLLCSM1_CTRL_PREG,PLLCMNLC1 Control State Machine Control register"
hexmask.long.word 0x38 16.--27. 1. "CMN_PLLLCSM1_PLLEN_TMR_VAL_PREG,PLL enable state timer value"
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bitfld.long 0x38 4. "CMN_PLLLCSM1_FORCE_CAL_DONE_PREG,Asserting this bit immediately advances the State Machine from the PLLSM_CAL state currently in or once entered" "0,1"
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bitfld.long 0x38 0. "CMN_PLLLCSM1_SKIP_PLL_CAL_RECAL_PREG,Skip PLL calibration re-calibration enable" "0,1"
line.long 0x3C "CMN_PLLLCSM1_PLLVREF_TMR_PREG__CMN_PLLLCSM1_PLLPRE_TMR_PREG,PLLCMNLC1 Control State Machine PLL pre-charge timer register"
hexmask.long.word 0x3C 16.--27. 1. "CMN_PLLLCSM1_PLLVREF_TMR_VAL_PREG,PLL pre-charge state timer value"
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hexmask.long.word 0x3C 0.--11. 1. "CMN_PLLLCSM1_PLLPRE_TMR_VAL_PREG,PLL pre-charge state timer value"
line.long 0x40 "CMN_PLLLC1_STATUS_C_PREG__CMN_PLLLC1_CLK2_PREG,PLLCMNLC1 clock2 register"
hexmask.long.byte 0x40 16.--23. 1. "CMN_PLLLC1_STATUS_C_BWCAL_CODE,PLLCMNLC1 Band Width calibration code result"
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bitfld.long 0x40 12. "CMN_PLLLC1_CLK2_EN_PREG,This value sets the clock2 enable value" "0,1"
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bitfld.long 0x40 8.--11. "CMN_PLLLC1_CLK2OUTDIVFRAC_PREG,his value sets the clock2 fractional output divider's fraction value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x40 0.--6. 1. "CMN_PLLLC1_CLK2OUTDIVINT_PREG,This value sets the clock2 fractional output divider's integer value"
line.long 0x44 "CMN_PLLLC1_LOCK_DELAY_CTRL_PREG__CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG,PLLCMNLC1 spread spectrum Time Step Size Mode register"
hexmask.long.byte 0x44 25.--31. 1. "CMN_PLLLC1_LOCK_DELAY_CTRL_PREG_15_9,reserved"
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hexmask.long.word 0x44 16.--24. 1. "CMN_PLLLC1_LOCK_DELAY_PREG,This value sets a delay from internal lock assertion to assertion of cmn_plllc_locked"
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hexmask.long.byte 0x44 8.--14. 1. "CMN_PLLLC1_SS_TIME_STEP_SIZE_MODE1_PREG,This value sets the spread spectrum time step size value when cmn_plllc_mode is asserted"
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hexmask.long.byte 0x44 0.--6. 1. "CMN_PLLLC1_SS_TIME_STEP_SIZE_MODE0_PREG,This value sets the spread spectrum time step size value when cmn_plllc_mode is deasserted"
rgroup.long 0x400++0x17
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the WIZ module"
bitfld.long 0x00 30.--31. "SCHEME,Module Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,Module BU" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SERDES_CTRL,Sets the SERDES control state"
bitfld.long 0x04 31. "POR_EN,The por_en allows the system to place the SERDES in a reset state Access to the SERDES registers are ignored" "0,1"
line.long 0x08 "SERDES_TOP_CTRL,The SERDES Top Level Control"
bitfld.long 0x08 30.--31. "PMA_CMN_REFCLK_MODE,The PMA common differential reference clock mode - Sets the mode of operation for differential reference clock input" "0,1,2,3"
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bitfld.long 0x08 28.--29. "PMA_CMN_REFCLK_INT_MODE,The PMA common internal reference clock mode - Sets the mode of operation for internal reference clock input" "0,1,2,3"
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bitfld.long 0x08 26.--27. "PMA_CMN_REFCLK_DIG_DIV,The PMA common reference clock digital divide ratio select - Must be set before the de-assertion of apb_preset_n/phy_reset_n" "0,1,2,3"
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bitfld.long 0x08 24.--25. "PMA_CMN_REFCLK1_DIG_DIV,The Alternate reference clock digital divide select - Selects digital divide ratio for alternate reference clock coming from analog (see PMA specification for use)" "0,1,2,3"
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bitfld.long 0x08 23. "PHY_PMA_SUSPEND_OVERRIDE,The PHY PMA common suspend override enable" "0,1"
line.long 0x0C "SERDES_RST,The SERDES Reset Register controls the Phy reset and REFCLK selection for the SERDES"
bitfld.long 0x0C 31. "PHY_RESET_N,The PHY reset : Asserting this signal low will reset all PHY logic for the entire PHY with the exception of the APB registers and TAP controller" "0,1"
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bitfld.long 0x0C 30. "PHY_EN_REFCLK,The PHY reference clock enable: When cmn_refclk_<p/m> is configured as a reference clock output " "0,1"
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bitfld.long 0x0C 29. "PLL1_REFCLK_SEL,The PMA common PLL1 reference clock source select" "0,1"
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bitfld.long 0x0C 28. "PLL0_REFCLK_SEL,The PMA common PLL0 reference clock source select" "0,1"
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bitfld.long 0x0C 27. "REFCLK_TERM_DIS,The PMA common differential reference clock termination disable - enables/disables termination for difference reference clock input (cmn_refclk_<p/m>)" "0,1"
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bitfld.long 0x0C 24.--25. "REFCLK_DIG_SEL,The Reference clock digital source select - Selects the reference clock source for the reference clock used in the PHY and PMA digital logic" "0,1,2,3"
line.long 0x10 "SERDES_TYPEC,The SERDES Type C control register allows the external lanes selection to be swapped"
bitfld.long 0x10 30. "LN10_SWAP,The LN10_SWAP will swap the lanes 0 and 1" "0,1"
line.long 0x14 "SERDES_CORE_STATUS,The contains SERDES core power state status"
bitfld.long 0x14 31. "MACRO_PWR_EN_ACK,SERDES macro_power enable acknowledgment - This signal is asserted high upon completion of the power on sequence in the SERDES" "0,1"
group.long 0x480++0x0F
line.long 0x00 "LANECTL0,The Lane Control Register sets the lane specific modes of operation"
bitfld.long 0x00 31. "P0_ENABLE,The P0_ENABLE is AND'ed with the IPx_LNy_reset_n to enable the lane" "0,1"
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bitfld.long 0x00 30. "P0_FORCE_ENABLE,The P0_FORCE_ENABLE is OR'ed with the IPx_LNy_reset_n to force enable the lane" "0,1"
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bitfld.long 0x00 29. "P0_ALIGN,The P0_ALIGN will auto align the RAW interface to 8B10B comma characters" "0,1"
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bitfld.long 0x00 28. "P0_RAW_AUTO_START,The P0_RAW_AUTO_START will auto sequence the RAW interface according to the configuration settings" "0,1"
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bitfld.long 0x00 24.--25. "P0_STANDARD_MODE,Standard Mode" "0,1,2,3"
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bitfld.long 0x00 22.--23. "P0_FULLRT_DIV,Full Rate divider for 2x MAC speed mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. "P0_MAC_SRC_SEL,MAC clock source select: Selects which PMA clock to use as clock source for pcs_mac_clk*_ln_0 signals" "0,1,2,3"
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bitfld.long 0x00 18.--19. "P0_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal" "0,1,2,3"
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bitfld.long 0x00 16.--17. "P0_OVR_SRC_SEL,Oversample clock source select: Selects which PMA clock to use as clock source for pcs_ovr_clk*_ln_0" "0,1,2,3"
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bitfld.long 0x00 12.--14. "P0_OVR_DIV_SEL,Oversample clock divider ratio select: Selects the divider ratio for pcs_ovr_clk_divx_ln_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10.--11. "P0_SUBCLK_SEL,Selects which clock sources pcs_sub_clk_0" "0,1,2,3"
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bitfld.long 0x00 8.--9. "P0_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal" "0,1,2,3"
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bitfld.long 0x00 6.--7. "P0_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal" "0,1,2,3"
line.long 0x04 "LANEDIV0,The Lane Divider Register sets the lane specific dividers of"
hexmask.long.byte 0x04 16.--22. 1. "P0_MAC_DIV_SEL0,The reg_p0_mac_div_sel0 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*"
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hexmask.long.word 0x04 0.--8. 1. "P0_MAC_DIV_SEL1,The reg_p0_mac_div_sel1 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*"
line.long 0x08 "LANALIGN0,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode"
bitfld.long 0x08 0.--5. "P0_ALIGN_RX_DELAY,The reg_p0_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "LANESTS0,The lane Status reports the lane state information for debug purposes"
bitfld.long 0x0C 1. "P0_MASTER,The reg_p0_master indicates the lane is a base lane for a multi lane link" "0,1"
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bitfld.long 0x0C 0. "P0_PWR_EN_ACK,The reg_p0_pwr_en_ack SERDES lane power enable acknowledgment - This signal is asserted high upon completion of the power on sequence in each PMA transceiver link (per-link/shared signal)" "0,1"
group.long 0x4C0++0x0F
line.long 0x00 "LANECTL1,The Lane Control Register sets the lane specific modes of operation"
bitfld.long 0x00 31. "P1_ENABLE,The p1_enable is AND'd with the IPx_LNy_reset_n to enable the lane" "0,1"
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bitfld.long 0x00 30. "P1_FORCE_ENABLE,The p1_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane" "0,1"
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bitfld.long 0x00 29. "P1_ALIGN,The p1_align will auto align the RAW interface to 8B10B comma characters" "0,1"
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bitfld.long 0x00 28. "P1_RAW_AUTO_START,The p1_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1"
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bitfld.long 0x00 24.--25. "P1_STANDARD_MODE,Standard Mode" "0,1,2,3"
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bitfld.long 0x00 22.--23. "P1_FULLRT_DIV,Full Rate divider for 2x MAC speed mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. "P1_MAC_SRC_SEL,MAC clock source select: Selects which PMA clock to use as clock source for pcs_mac_clk*_ln_1 signals" "0,1,2,3"
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bitfld.long 0x00 18.--19. "P1_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal" "0,1,2,3"
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bitfld.long 0x00 16.--17. "P1_OVR_SRC_SEL,Oversample clock source select: Selects which PMA clock to use as clock source for pcs_ovr_clk*_ln_1" "0,1,2,3"
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bitfld.long 0x00 12.--14. "P1_OVR_DIV_SEL,Oversample clock divider ratio select: Selects the divider ratio for pcs_ovr_clk_divx_ln_1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10.--11. "P1_SUBCLK_SEL,Selects which clock sources pcs_sub_clk_1" "0,1,2,3"
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bitfld.long 0x00 8.--9. "P1_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal" "0,1,2,3"
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bitfld.long 0x00 6.--7. "P1_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal" "0,1,2,3"
line.long 0x04 "LANEDIV1,The Lane Divider Register sets the lane specific dividers of"
hexmask.long.byte 0x04 16.--22. 1. "P1_MAC_DIV_SEL0,The reg_p1_mac_div_sel0 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*"
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hexmask.long.word 0x04 0.--8. 1. "P1_MAC_DIV_SEL1,The reg_p1_mac_div_sel1 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*"
line.long 0x08 "LANALIGN1,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode"
bitfld.long 0x08 0.--5. "P1_ALIGN_RX_DELAY,The reg_p1_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "LANESTS1,The lane Status reports the lane state information for debug purposes"
bitfld.long 0x0C 1. "P1_MASTER,The reg_p1_master indicates the lane is a base lane for a multi lane link" "0,1"
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bitfld.long 0x0C 0. "P1_PWR_EN_ACK,The reg_p1_pwr_en_ack SERDES lane power enable acknowledgment - This signal is asserted high upon completion of the power on sequence in each PMA transceiver link (per-link/shared signal)" "0,1"
group.long 0x5F4++0x03
line.long 0x00 "RES_CAL,The Resistor Calibration register is used to allow the elimination of the external resistor on multiple macros"
rbitfld.long 0x00 16.--21. "PMA_CMN_RESCAL_CODE_OUT,This is the current value of the pma_cmn_rescal_code_out from the SERDES and can be used to set pma_cmn_rescal_code_in for other macros" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8. "PMA_CMN_RESCAL_INSEL,Common resistor calibration selection" "0,1"
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bitfld.long 0x00 0.--5. "PMA_CMN_RESCAL_CODE_IN,External common resistor calibration result - Resistor calibration result from another Serdes PCIe PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5FC++0x03
line.long 0x00 "DIAG_TEST,The Diagnostic Test Register allows the system to validate the read and write of all data bits"
group.long 0x4000++0x33
line.long 0x00 "DET_STANDEC_B_PREG__DET_STANDEC_A_PREG_j,Standard decoder register A"
bitfld.long 0x00 27. "DEQ_TXPOSTTRAINEN_MODE3_PREG,This value sets the deq_txposttrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 26. "DEQ_TXPOSTTRAINEN_MODE2_PREG,This value sets the deq_txposttrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 25. "DEQ_TXPOSTTRAINEN_MODE1_PREG,This value sets the deq_txposttrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 24. "DEQ_TXPOSTTRAINEN_MODE0_PREG,This value sets the deq_txposttrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x00 23. "DEQ_TXPRETRAINEN_MODE3_PREG,This value sets the deq_txpretrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 22. "DEQ_TXPRETRAINEN_MODE2_PREG,This value sets the deq_txpretrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 21. "DEQ_TXPRETRAINEN_MODE1_PREG,This value sets the deq_txpretrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 20. "DEQ_TXPRETRAINEN_MODE0_PREG,This value sets the deq_txpretrainen from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x00 19. "DEQ_CLOSEDEYE_SEL_MODE3_PREG,This value sets the deq_closedeye_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 18. "DEQ_CLOSEDEYE_SEL_MODE2_PREG,This value sets the deq_closedeye_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 17. "DEQ_CLOSEDEYE_SEL_MODE1_PREG,This value sets the deq_closedeye_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 16. "DEQ_CLOSEDEYE_SEL_MODE0_PREG,This value sets the deq_closedeye_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x00 15. "DRVCTRL_EDGEBOOST_EN_MODE3_PREG,Active high enable for the transmit driver edgeboost function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 14. "DRVCTRL_EDGEBOOST_EN_MODE2_PREG,Active high enable for the transmit driver edgeboost function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 13. "DRVCTRL_EDGEBOOST_EN_MODE1_PREG,Active high enable for the transmit driver edgeboost function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 12. "DRVCTRL_EDGEBOOST_EN_MODE0_PREG,Active high enable for the transmit driver edgeboost function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x00 11. "TX_DEEMPHASIS_CTRL_SEL_MODE3_PREG,This value sets the tx_deemphasis_ctrl_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 10. "TX_DEEMPHASIS_CTRL_SEL_MODE2_PREG,This value sets the tx_deemphasis_ctrl_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 9. "TX_DEEMPHASIS_CTRL_SEL_MODE1_PREG,This value sets the tx_deemphasis_ctrl_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 8. "TX_DEEMPHASIS_CTRL_SEL_MODE0_PREG,This value sets the tx_deemphasis_ctrl_sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x00 7. "DRV_IDLE_LOWZ_MODE3_PREG,Asserting this value lowers the impedance of the transmit driver common-mode impedance when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 6. "DRV_IDLE_LOWZ_MODE2_PREG,Asserting this value lowers the impedance of the transmit driver common-mode impedance when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 5. "DRV_IDLE_LOWZ_MODE1_PREG,Asserting this value lowers the impedance of the transmit driver common-mode impedance when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 4. "DRV_IDLE_LOWZ_MODE0_PREG,Asserting this value lowers the impedance of the transmit driver common-mode impedance when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 3. "SER_GT8G_MODE3_PREG,This value overrides the ser_gt8g from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 2. "SER_GT8G_MODE2_PREG,This value overrides the ser_gt8g from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x00 1. "SER_GT8G_MODE1_PREG,This value overrides the ser_gt8g from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x00 0. "SER_GT8G_MODE0_PREG,This value overrides the ser_gt8g from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
line.long 0x04 "DET_STANDEC_D_PREG__DET_STANDEC_C_PREG_j,Standard decoder register C"
bitfld.long 0x04 29.--31. "CLKPATHCTRL_SSCLOCKADJ_MODE3_PREG,This value sets the clkpathctrl_ssclockadj from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 26.--28. "CLKPATHCTRL_SSCLOCKADJ_MODE2_PREG,This value sets the clkpathctrl_ssclockadj from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 23.--25. "CLKPATHCTRL_SSCLOCKADJ_MODE1_PREG,This value sets the clkpathctrl_ssclockadj from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 20.--22. "CLKPATHCTRL_SSCLOCKADJ_MODE0_PREG,This value sets the clkpathctrl_ssclockadj from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 19. "CLKRST_FULLRT_DIVSEL_MODE3_PREG,This value sets the clkrst_fullrt_div2sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x04 18. "CLKRST_FULLRT_DIVSEL_MODE2_PREG,This value sets the clkrst_fullrt_div2sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x04 17. "CLKRST_FULLRT_DIVSEL_MODE1_PREG,This value sets the clkrst_fullrt_div2sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x04 16. "CLKRST_FULLRT_DIVSEL_MODE0_PREG,This value sets the clkrst_fullrt_div2sel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x04 14.--15. "VGA_TAPSTEPSIZE_MODE3_PREG,Receive data path offset correction current trim when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x04 12.--13. "VGA_TAPSTEPSIZE_MODE2_PREG,Receive data path offset correction current trim when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x04 10.--11. "VGA_TAPSTEPSIZE_MODE1_PREG,Receive data path offset correction current trim when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x04 8.--9. "VGA_TAPSTEPSIZE_MODE0_PREG,Receive data path offset correction current trim when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3"
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bitfld.long 0x04 6.--7. "DEQ_CLOSEDEYE_MODE_MODE3_PREG,This value sets the deq_closedeye_mode from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x04 4.--5. "DEQ_CLOSEDEYE_MODE_MODE2_PREG,This value sets the deq_closedeye_mode from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x04 2.--3. "DEQ_CLOSEDEYE_MODE_MODE1_PREG,This value sets the deq_closedeye_mode from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x04 0.--1. "DEQ_CLOSEDEYE_MODE_MODE0_PREG,This value sets the deq_closedeye_mode from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3"
line.long 0x08 "FPWRISO_OVRD_PREG__DET_STANDEC_E_PREG_j,Standard decoder register E"
bitfld.long 0x08 28. "FPWRISO_OVRD_EN_PREG,Lane power-gated supply island active high override enable" "0,1"
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bitfld.long 0x08 24. "FPWRISO_ISOLATION_EN_OVRD_PREG,Lane power-gated supply island isolation override" "0,1"
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bitfld.long 0x08 20. "FPWRISO_PHASE2EN_OVRD_PREG,Lane power-gated supply island phase2en override" "0,1"
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bitfld.long 0x08 16. "FPWRISO_PHASE1EN_OVRD_PREG,Lane power-gated supply island phase1en override" "0,1"
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bitfld.long 0x08 9.--11. "CLKRST_DATART_DIV_MODE3_PREG,This value sets the clkrst_datart_divsel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 6.--8. "CLKRST_DATART_DIV_MODE2_PREG,This value sets the clkrst_datart_divsel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 3.--5. "CLKRST_DATART_DIV_MODE1_PREG,This value sets the clkrst_datart_divsel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--2. "CLKRST_DATART_DIV_MODE0_PREG,This value sets the clkrst_datart_divsel from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
line.long 0x0C "FPWRISO_CTRL_PREG_j,Lane power-gated supply island control register"
bitfld.long 0x0C 30. "FPWRISO_PWRDN_DISABLE_PREG,Power down disable" "0,1"
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bitfld.long 0x0C 24.--28. "FPWRISO_STAGGER_DLY_PREG,Lane to Lane power island enable/disable stagger time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 20.--23. "FPWRISO_EN_PH2DLY_PREG,Power enable phase 2 timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "FPWRISO_EN_PH1DLY_PREG,Power enable phase 1 timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PSM_A0IN_TMR_PREG__PSM_LANECAL_DLY_A1_RESETS_PREG_j,Power State Machine lane calibration delay timer and A1 resets register"
hexmask.long.byte 0x10 16.--23. 1. "PSM_A0IN_TMR_VAL_PREG,A0 in delay state timer value"
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bitfld.long 0x10 12. "PSM_TX_RESET_ACTIVE_A1_PREG,When asserted the transmit path resets will be asserted in the A1 power state" "0,1"
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bitfld.long 0x10 8. "PSM_RX_RESET_ACTIVE_A1_PREG,When asserted the receive path resets will be asserted in the A1 power state" "0,1"
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hexmask.long.byte 0x10 0.--7. 1. "PSM_LANECAL_DLY_TMR_VAL_PREG,Lane calibration delay state timer value"
line.long 0x14 "PSM_A2IN_TMR_PREG__PSM_A1IN_TMR_PREG_j,Power State Machine A1 in delay timer register"
hexmask.long.byte 0x14 16.--23. 1. "PSM_A2IN_TMR_VAL_PREG,A2 in delay state timer value"
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hexmask.long.byte 0x14 0.--7. 1. "PSM_A1IN_TMR_VAL_PREG,A1 in delay state timer value"
line.long 0x18 "PSM_A4IN_TMR_PREG__PSM_A3IN_TMR_PREG_j,Power State Machine A3 in delay timer register"
hexmask.long.byte 0x18 16.--23. 1. "PSM_A4IN_TMR_VAL_PREG,A4 in delay state timer value"
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hexmask.long.byte 0x18 0.--7. 1. "PSM_A3IN_TMR_VAL_PREG,A3 in delay state timer value"
line.long 0x1C "PSM_A0OUT_TMR_PREG_j,Power State Machine A0 out delay timer register"
bitfld.long 0x1C 16.--19. "PSM_A0OUT_TMR_VAL_PREG,A0 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "PSM_A2OUT_TMR_PREG__PSM_A1OUT_TMR_PREG_j,Power State Machine A1 out delay timer register"
bitfld.long 0x20 16.--19. "PSM_A2OUT_TMR_VAL_PREG,A2 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "PSM_A1OUT_TMR_VAL_PREG,A1 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "PSM_A4OUT_TMR_PREG__PSM_A3OUT_TMR_PREG_j,Power State Machine A3 out delay timer register"
bitfld.long 0x24 16.--19. "PSM_A4OUT_TMR_VAL_PREG,A4 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. "PSM_A3OUT_TMR_VAL_PREG,A3 out delay state timer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "PSM_DIAG_PREG_j,Power State Machine diagnostic register"
bitfld.long 0x28 31. "PSM_SKIP_LANE_RECAL_PREG,Skip lane re-calibration" "0,1"
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bitfld.long 0x28 30. "PSM_SKIP_RXMEM_RERESET_PREG,Skip reset of receive clock and data path equalization and offset memories" "0,1"
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bitfld.long 0x28 28. "PSM_FORCE_A4_EXIT_ACK_PREG,Force A4 exit acknowledge" "0,1"
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bitfld.long 0x28 27. "PSM_FORCE_A3_EXIT_ACK_PREG,Force A3 exit acknowledge" "0,1"
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bitfld.long 0x28 26. "PSM_FORCE_A2_EXIT_ACK_PREG,Force A2 exit acknowledge" "0,1"
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bitfld.long 0x28 25. "PSM_FORCE_A1_EXIT_ACK_PREG,Force A1 exit acknowledge" "0,1"
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bitfld.long 0x28 24. "PSM_FORCE_A0_EXIT_ACK_PREG,Force A0 exit acknowledge" "0,1"
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bitfld.long 0x28 23. "PSM_FORCE_LANE_CAL_CLKEN_ACK_PREG,Force lane calibration clken acknowledge" "0,1"
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bitfld.long 0x28 22. "PSM_FORCE_LANE_CAL_ENTRY_ACK_PREG,Force lane calibration entry acknowledge" "0,1"
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bitfld.long 0x28 21. "PSM_FORCE_A4_ENTRY_ACK_PREG,Force A4 entry acknowledge" "0,1"
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bitfld.long 0x28 20. "PSM_FORCE_A3_ENTRY_ACK_PREG,Force A3 entry acknowledge" "0,1"
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bitfld.long 0x28 19. "PSM_FORCE_A2_CLKEN_ACK_PREG,Force A2 clken acknowledge" "0,1"
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bitfld.long 0x28 18. "PSM_FORCE_A2_ENTRY_ACK_PREG,Force A2 entry acknowledge" "0,1"
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bitfld.long 0x28 17. "PSM_FORCE_A1_ENTRY_ACK_PREG,Force A1 entry acknowledge" "0,1"
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bitfld.long 0x28 16. "PSM_FORCE_A0_ENTRY_ACK_PREG,Force A0 entry acknowledge" "0,1"
line.long 0x2C "PSM_STATE_L_PREG__PSM_STATE_H_PREG_j,Power State Machine current state register high byte"
hexmask.long.word 0x2C 16.--31. 1. "PSM_STATE_L,Power state machine current state"
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bitfld.long 0x2C 0.--3. "PSM_STATE_H,Power state machine current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "PSTG_STATUS_PREG__PSTG_CTRL_PREG_j,Power State Token Generator Control Register Offset = 4030h + (j * 400h); where j = 0h to 1h"
rbitfld.long 0x30 16.--17. "PSTG_STATE,Power State Token Generator FSM state vector" "0,1,2,3"
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bitfld.long 0x30 0.--3. "PSTG_STAGGER_DLY_PREG,Lane to Lane power state enable/disable stagger time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4038++0x03
line.long 0x00 "PCSM_STATUS_PREG__PCSM_CTRL_PREG_j,PLL clock state machine control register Offset = 4038h + (j * 400h); where j = 0h to 1h"
rbitfld.long 0x00 16.--20. "PCSM_STATE,PLL clock state machine control state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 1. "PCSM_PLLLNEN_OVREN_PREG,PLLLN active high enable override enable" "0,1"
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bitfld.long 0x00 0. "PCSM_PLLLNEN_OVR_PREG,PLLLN active high enable override value" "0,1"
group.long 0x4040++0x4B
line.long 0x00 "PSC_LN_A1_PREG__PSC_LN_A0_PREG_j,Lane A0 power state definition register"
bitfld.long 0x00 16.--18. "PSC_LN_A1_PREG,Bit Description" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "PSC_LN_A0_PREG,Bit Description" "0,1,2,3,4,5,6,7"
line.long 0x04 "PSC_LN_A3_PREG__PSC_LN_A2_PREG_j,Lane A2 power state definition register"
bitfld.long 0x04 16.--18. "PSC_LN_A3_PREG,Bit Description" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--2. "PSC_LN_A2_PREG,Bit Description" "0,1,2,3,4,5,6,7"
line.long 0x08 "PSC_LN_A5_PREG__PSC_LN_A4_PREG_j,Lane A4 power state definition register"
bitfld.long 0x08 16.--18. "PSC_LN_A5_PREG,Bit Description" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--2. "PSC_LN_A4_PREG,Bit Description" "0,1,2,3,4,5,6,7"
line.long 0x0C "PSC_LN_IDLE_PREG_j,Lane idle power state definition register"
bitfld.long 0x0C 0.--2. "PSC_LN_IDLE_PREG,Bit Description" "0,1,2,3,4,5,6,7"
line.long 0x10 "PSC_TX_A1_PREG__PSC_TX_A0_PREG_j,Transmit A0 power state definition register"
bitfld.long 0x10 16.--20. "PSC_TX_A1_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. "PSC_TX_A0_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "PSC_TX_A3_PREG__PSC_TX_A2_PREG_j,Transmit A2 power state definition register"
bitfld.long 0x14 16.--20. "PSC_TX_A3_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--4. "PSC_TX_A2_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "PSC_TX_A5_PREG__PSC_TX_A4_PREG_j,Transmit A4 power state definition register"
bitfld.long 0x18 16.--20. "PSC_TX_A5_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 0.--4. "PSC_TX_A4_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "PSC_TX_IDLE_PREG_j,Transmit idle power state definition register"
bitfld.long 0x1C 0.--4. "PSC_TX_IDLE_PREG,Bit Description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "PSC_RX_A1_PREG__PSC_RX_A0_PREG_j,Receive A0 power state definition register"
hexmask.long.word 0x20 16.--29. 1. "PSC_RX_A1_PREG,Bit Description"
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hexmask.long.word 0x20 0.--13. 1. "PSC_RX_A0_PREG,Bit Description"
line.long 0x24 "PSC_RX_A3_PREG__PSC_RX_A2_PREG_j,Receive A2 power state definition register"
hexmask.long.word 0x24 16.--29. 1. "PSC_RX_A3_PREG,Bit Description"
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hexmask.long.word 0x24 0.--13. 1. "PSC_RX_A2_PREG,Bit Description"
line.long 0x28 "PSC_RX_A5_PREG__PSC_RX_A4_PREG_j,Receive A4 power state definition register"
hexmask.long.word 0x28 16.--29. 1. "PSC_RX_A5_PREG,Bit Description"
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hexmask.long.word 0x28 0.--13. 1. "PSC_RX_A4_PREG,Bit Description"
line.long 0x2C "PSC_RX_IDLE_PREG_j,Receive Idle power state definition register"
hexmask.long.word 0x2C 0.--13. 1. "PSC_RX_IDLE_PREG,Bit Description"
line.long 0x30 "PLLCTRL_FBDIV_MODE01_PREG__PLLCTRL_FBDIV_MODE23_PREG_j,PLLLN feedback divider control in standard modes 2 and 3"
hexmask.long.byte 0x30 24.--30. 1. "PLLCTRL_FBDIV_MODE1_PREG,This value sets the feedback divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001"
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hexmask.long.byte 0x30 16.--22. 1. "PLLCTRL_FBDIV_MODE0_PREG,This value sets the feedback divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000"
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hexmask.long.byte 0x30 8.--14. 1. "PLLCTRL_FBDIV_MODE3_PREG,This value sets the feedback divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011"
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hexmask.long.byte 0x30 0.--6. 1. "PLLCTRL_FBDIV_MODE2_PREG,This value sets the feedback divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010"
line.long 0x34 "PLLCTRL_GEN_A_PREG__PLLCTRL_SUBRATE_PREG_j,PLLLN subrate control register"
bitfld.long 0x34 29. "PLLCTRL_RSTOVREN_PREG,PLLLN reset active high override enable" "0,1"
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bitfld.long 0x34 28. "PLLCTRL_RSTOVR_PREG,When pllctrl_rstovren_preg is asserted high this active high bit overrides the reset" "0,1"
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bitfld.long 0x34 24. "PLLCTRL_LOCKOVR_PREG,Forces the lock indication from the PLLln high as enters into main digital" "0,1"
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bitfld.long 0x34 19. "PLLCTRL_PLLLC1_ANACLK0_SEL_MODE3_PREG,PLLLN reference selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x34 18. "PLLCTRL_PLLLC1_ANACLK0_SEL_MODE2_PREG,PLLLN reference selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x34 17. "PLLCTRL_PLLLC1_ANACLK0_SEL_MODE1_PREG,PLLLN reference selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x34 16. "PLLCTRL_PLLLC1_ANACLK0_SEL_MODE0_PREG,PLLLN reference selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x34 12.--13. "PLLCTRL_SUBRATE_MODE3_PREG,This value sets the subrate divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x34 8.--9. "PLLCTRL_SUBRATE_MODE2_PREG,This value sets the subrate divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x34 4.--5. "PLLCTRL_SUBRATE_MODE1_PREG,This value sets the subrate divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x34 0.--1. "PLLCTRL_SUBRATE_MODE0_PREG,This value sets the subrate divider ratio from the Lane Standards Decoder when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3"
line.long 0x38 "PLLCTRL_GEN_C_PREG__PLLCTRL_GEN_B_PREG_j,PLLLN general control register B"
hexmask.long.byte 0x38 24.--30. 1. "PLLCTRL_DIGDIV_MODE3_PREG,PLLLN digclk divider selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011"
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hexmask.long.byte 0x38 16.--22. 1. "PLLCTRL_DIGDIV_MODE2_PREG,PLLLN digclk divider selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010"
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rbitfld.long 0x38 15. "MSTR_PLLLN_AUTORST_ERROR_FLAG,Master lane PLLLN active high auto reset error flag" "0,1"
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rbitfld.long 0x38 14. "SLV_PLLLN_AUTORST_ERROR_FLAG,Combined slave lanes PLLLN active high auto reset error flag" "0,1"
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bitfld.long 0x38 12. "PLLCTRL_AUTORST_DISABLE_PREG,PLLLN active high auto reset disable" "0,1"
newline
bitfld.long 0x38 8.--9. "PLLCTRL_AUTORST_DLY_PREG,PLLLN auto reset delay selection" "0,1,2,3"
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bitfld.long 0x38 4.--6. "PLLCTRL_AUTORST_REPEAT_PREG,PLLLN auto reset maximum attempt selection" "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 0.--2. "PLLCTRL_MODE_PREG,PLLLN operating mode as defined below" "0,1,2,3,4,5,6,7"
line.long 0x3C "PLLCTRL_CPGAIN_MODE_PREG__PLLCTRL_GEN_D_PREG_j,PLLLN general control register D"
bitfld.long 0x3C 28.--30. "PLLCTRL_CPGAIN_MODE3_PREG,PLLLN charge pump gain when xcvr_standard_mode_ln_PLLCTRL_AUTORST_DLY_PREG is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 24.--26. "PLLCTRL_CPGAIN_MODE2_PREG,PLLLN charge pump gain when xcvr_standard_mode_ln_PLLCTRL_AUTORST_DLY_PREG is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 20.--22. "PLLCTRL_CPGAIN_MODE1_PREG,PLLLN charge pump gain when xcvr_standard_mode_ln_PLLCTRL_AUTORST_DLY_PREG is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 16.--18. "PLLCTRL_CPGAIN_MODE0_PREG,PLLLN charge pump gain when xcvr_standard_mode_ln_PLLCTRL_AUTORST_DLY_PREG is 3'b000" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x3C 8.--14. 1. "PLLCTRL_DIGDIV_MODE1_PREG,PLLLN digclk divider selection when xcvr_standard_mode_ln_PLLCTRL_AUTORST_DLY_PREG is 3'b001"
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hexmask.long.byte 0x3C 0.--6. 1. "PLLCTRL_DIGDIV_MODE0_PREG,PLLLN digclk divider selection when xcvr_standard_mode_ln_PLLCTRL_AUTORST_DLY_PREG is 3'b000"
line.long 0x40 "PLLCTRL_PHASE1EN_PREG__LNCTRL_CLKRST_LN_PLLCLK_OVR_PREG_j,Diagnostic access to cmn_sdosc_clk Offset = 4080h + (j * 400h); where j = 0h to 1h"
hexmask.long.word 0x40 16.--27. 1. "PLLCTRL_PHASE1EN_DLY_PREG,PLLLN phase1en delay time in xcvr_psmclk_ln_{15:0} periods"
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bitfld.long 0x40 0. "LNCTRL_CLKRST_LN_PLLCLK_OVR_EN_PREG,When asserted the cmn_sdosc_clk is used to source the ln_pllclk_fullrt" "0,1"
line.long 0x44 "PLLCTRL_AVDDREG_PREG__PLLCTRL_PHASE2EN_PREG_j,PLLLN phase2 enable delay control register"
bitfld.long 0x44 29.--31. "PLLCTRL_LFAVDDREG_VTRIM_PREG,PLLLN low frequency block regulator voltage trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "PLLCTRL_LFAVDDREG_FWEN_N_PREG,PLLLN active low firewall enable forcing for signal driven from lfavddreg power island" "0,1"
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bitfld.long 0x44 17.--19. "PLLCTRL_FRAVDDREG_VTRIM_PREG,PLLLN full rate block regulator voltage trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 16. "PLLCTRL_FRAVDDREG_FWEN_N_PREG,PLLLN active low firewall enable forcing for signal driven from fravddreg power island" "0,1"
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hexmask.long.word 0x44 0.--11. 1. "PLLCTRL_PHASE2EN_DLY_PREG,PLLLN phase2en delay time in xcvr_psmclk_ln_{15:0} periods"
line.long 0x48 "PLLLNC_STATUS_PREG__PLLCTRL_STATUS_PREG_j,PLLLN status register"
bitfld.long 0x48 24.--27. "SLV_PLLLNC_STATE,Slave lane PLL control state machine state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 16.--19. "MSTR_PLLLNC_STATE,Master lane PLL control state machine state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 8. "PLLCTRL_TESTOUT,PLLLN digital debug output" "0,1"
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bitfld.long 0x48 0. "PLLCTRL_LOCK,PLLLN active high lock flag" "0,1"
group.long 0x4090++0x0B
line.long 0x00 "LOOPBACK_BIASTRIM_PREG__TX_BIASTRIM_PREG_j,Transmit loopback bias current trim register"
bitfld.long 0x00 28.--30. "LPBKLINEMUX_BIASTRIM_PREG,Receive line loopback multiplexor bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "LPBKRCLKCMUX1_BIASTRIM_PREG,Receive recovered clock loopback clock path stage 1 multiplexer bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "LPBKRCLKDMUX1_BIASTRIM_PREG,Receive recovered clock loopback data path stage 1 multiplexer bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "LPBKRCLKMUX2_BIASTRIM_PREG,Receive recovered clock loopback stage 2 multiplexer bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "DRV_LPBK_BIASTRIM_PREG,Transmit bias current binary encoded trim shared for both serial and line/recovered clock loopbacks" "0,1,2,3,4,5,6,7"
line.long 0x04 "CLKPATH_BIASTRIM_PREG__RXFE_BIASTRIM_PREG_j,Receive front-end bias current trim register Offset = 4094h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x04 22.--24. "CTLECLK_MAINBIASTRIM_PREG,Receive clock path clock CTLE main path bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 19.--21. "CTLECLK_INDBIASTRIM_PREG,Receive clock path clock CTLE inductor circuitry bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 16.--18. "CKSMP_BIASTRIM_PREG,Receive clock path clock sampler bias current binary encoded trim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--1. "RXBUFFER_BIASTRIM_PREG,Receive buffer bias current binary encoded trim" "0,1,2,3"
line.long 0x08 "DFE_BIASTRIM_PREG_j,Receive data path DFE bias current trim register"
bitfld.long 0x08 12.--15. "SMP_BIASTRIM_PREG,Receive data path DFE sampler bias current binary encoded trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "IDAC_BIASTRIM_PREG,Receive data path DFE current DAC bias current binary encoded trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. "SUM_BIASTRIM_PREG,Receive data path DFE summer bias current binary encoded trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "AMP_BIASTRIM_PREG,Receive data path DFE amplifier bias current binary encoded trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40A0++0x03
line.long 0x00 "BSCAN_LPBKLINE_PREG__LANE_LOOPBACK_CTRL_PREG_j,Local Lane loopback control register"
bitfld.long 0x00 17. "BSCAN_LPBKLINE_ZTPSEL_PREG,Multiplexor selection for which boundary scan receiver is looped back" "0,1"
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bitfld.long 0x00 16. "BSCAN_LPBKLINE_EN_PREG,Active high enable for boundary scan receiver to driver line loopback" "0,1"
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bitfld.long 0x00 15. "LPBKNEPAR_DIGONLY_PREG,Active high digital only version of Near-end parallel loopback requiring no analog support other than reference clock reception" "0,1"
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bitfld.long 0x00 12.--14. "LPBKSER_DRVTRIM_PREG,Trim setting for txana_lpbkser in serial loopback path" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "LPBKSERRCV_BIASTRIM_PREG,Bias trim setting for rxana_lpbkserrcv in serial loopback path" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "LPBKLINEMUX_CLKSEL_PREG,Line loopback source selection" "0,1"
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bitfld.long 0x00 7. "LPBKRCLKCMUX1_QCLKSEL_PREG,Recovered clock loopback clock path mux stage 1 selection" "0,1"
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bitfld.long 0x00 6. "LPBKRCLKDMUX1_EPISEL_PREG,Recovered clock loopback data path mux stage 1 selection" "0,1"
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bitfld.long 0x00 5. "LPBKRCLKDMUX2_DCLKSEL_PREG,Recovered clock loopback mux stage 2 selection" "0,1"
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bitfld.long 0x00 4. "LPBKRCLKEN_PREG,Recovered clock loopback active high enable" "0,1"
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bitfld.long 0x00 3. "LPBKLINEEN_PREG,Line side loopback active high enable" "0,1"
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bitfld.long 0x00 2. "LPBKSEREN_PREG,Serial loopback active high enable" "0,1"
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bitfld.long 0x00 1. "LPBKNEPAREN_PREG,Near end parallel loopback active high enable" "0,1"
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bitfld.long 0x00 0. "LPBKFEPAREN_PREG,Far end parallel loopback active high enable" "0,1"
group.long 0x40A8++0x13
line.long 0x00 "TX_DIAG_SFIFO_TMR__TX_DIAG_SFIFO_CTRL_j,TX sync FIFO diagnostic control register Offset = 40A8h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x00 24.--29. "TX_SFIFO_ALIGN_SETTLE_DEL_PREG,FIFO alignment settle delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "TX_SFIFO_ALIGN_DETECT_DEL_PREG,FIFO alignment detect delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "TX_SFIFO_SYNC_REG_MODE_EN_PREG," "0,1"
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rbitfld.long 0x00 6. "TX_SFIFO_ERROR_STICKY_BIT,Sticky FIFO alignment error" "0,1"
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bitfld.long 0x00 5. "TX_SFIFO_ERROR_STICKY_BIT_CLR_PREG,Sticky FIFO alignment error clear" "0,1"
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bitfld.long 0x00 4. "TX_SFIFO_ENQ_PTR_BUMP_PREG,FIFO enqueue pointer bump" "0,1"
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rbitfld.long 0x00 3. "TX_SFIFO_ERROR,FIFO alignment error" "0,1"
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rbitfld.long 0x00 2. "TX_SFIFO_ALIGN_ACK,FIFO alignment acknowledge" "0,1"
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bitfld.long 0x00 1. "TX_SFIFO_ALIGN_EN_OVRD_EN_PREG,FIFO alignment enable override enable" "0,1"
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bitfld.long 0x00 0. "TX_SFIFO_ALIGN_EN_OVRD_PREG,FIFO alignment enable override" "0,1"
line.long 0x04 "TX_LOWLAT_CTRL_PREG_j,Ultra low latency mode control register Offset = 40ACh + (j * 400h); where j = 0h to 1h"
bitfld.long 0x04 2. "TX_SER_SLIP4_PREG,Serializer slip by 4UI request" "0,1"
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bitfld.long 0x04 1. "RX_LOW_LATENCY_PREG,Receive ultra-low latency mode enable" "0,1"
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bitfld.long 0x04 0. "TX_LOW_LATENCY_PREG,Transmit ultra-low latency mode enable" "0,1"
line.long 0x08 "TX_ELEC_IDLE_PREG_j,Transmit electrical idle control register"
bitfld.long 0x08 8.--10. "TX_ELEC_IDLE_ENTRY_DLY_PREG,Transmit path electrical idle entry programmable delay" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 5.--7. "TX_ELEC_IDLE_EXIT_DLY_PREG,Transmit path electrical idle exit programmable delay" "0,1,2,3,4,5,6,7"
line.long 0x0C "TX_SER_LOADDELAY_PREG_j,Tx serializer load delay control register"
bitfld.long 0x0C 12. "TX_SER_LOADDELAY_MODE3_PREG,Analog Serializer parallel data load delay" "0,1"
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bitfld.long 0x0C 8. "TX_SER_LOADDELAY_MODE2_PREG,Analog Serializer parallel data load delay" "0,1"
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bitfld.long 0x0C 4. "TX_SER_LOADDELAY_MODE1_PREG,Analog Serializer parallel data load delay" "0,1"
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bitfld.long 0x0C 0. "TX_SER_LOADDELAY_MODE0_PREG,Analog Serializer parallel data load delay" "0,1"
line.long 0x10 "TX_HSRRSM_STATUS_PREG_j,Transmit high speed reset release state machine status register"
bitfld.long 0x10 0.--4. "TX_HSRRSM_STATE,Transmit high speed reset release state machine state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40C0++0x2B
line.long 0x00 "DRVCTRL_PRESET_C0_OVRD_PREG__DRVCTRL_PRESET_CM1_OVRD_PREG_j,Transmit driver local preset pre-emphasis cursor override register"
bitfld.long 0x00 24. "DRVCTRL_PRESET_C0_OVRD_EN_PREG,Local preset main cursor active high override enable" "0,1"
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bitfld.long 0x00 16.--21. "DRVCTRL_PRESET_C0_OVRD_VAL_PREG,When drvctrl_preset_c0_ovrd_en_preg is asserted high this value overrides the internally generated value for tx_local_tx_preset_coef_ln_{15:0} [11:6] following a tx_get_local_preset_coef_ln_{15:0} request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8. "DRVCTRL_PRESET_CM1_OVRD_EN_PREG,Local preset pre-emphasis cursor active high override enable" "0,1"
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bitfld.long 0x00 0.--5. "DRVCTRL_PRESET_CM1_OVRD_VAL_PREG,When drvctrl_preset_cm1_ovrd_en_preg is asserted high this value overrides the internally generated value for tx_local_tx_preset_coef_ln_{15:0} [5:0] following a tx_get_local_preset_coef_ln_{15:0} request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DRVCTRL_INIT_CM1_OVRD_PREG__DRVCTRL_PRESET_CP1_OVRD_PREG_j,Transmit driver local preset post-emphasis cursor override register"
bitfld.long 0x04 24. "DRVCTRL_INIT_CM1_OVRD_EN_PREG,Local init pre-emphasis cursor active high override enable" "0,1"
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bitfld.long 0x04 16.--21. "DRVCTRL_INIT_CM1_OVRD_VAL_PREG,When drvctrl_init_cm1_ovrd_en_preg is asserted high this value overrides the internally generated value for tx_local_tx_preset_coef_ln_{15:0} [5:0] following a tx_get_local_init_coef_ln_{15:0} request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 8. "DRVCTRL_PRESET_CP1_OVRD_EN_PREG,Local preset post-emphasis cursor active high override enable" "0,1"
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bitfld.long 0x04 0.--5. "DRVCTRL_PRESET_CP1_OVRD_VAL_PREG,When drvctrl_preset_cp1_ovrd_en_preg is asserted high this value overrides the internally generated value for tx_local_tx_preset_coef_ln_{15:0} [17:12] following a tx_get_local_preset_coef_ln_{15:0} request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DRVCTRL_INIT_CP1_OVRD_PREG__DRVCTRL_INIT_C0_OVRD_PREG_j,Transmit driver local init main cursor override register"
bitfld.long 0x08 24. "DRVCTRL_INIT_CP1_OVRD_EN_PREG,Local init post-emphasis cursor active high override enable" "0,1"
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bitfld.long 0x08 16.--21. "DRVCTRL_INIT_CP1_OVRD_VAL_PREG,When drvctrl_init_cp1_ovrd_en_preg is asserted high this value overrides the internally generated value for tx_local_tx_preset_coef_ln_{15:0} [17:12] following a tx_get_local_init_coef_ln_{15:0} request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 8. "DRVCTRL_INIT_C0_OVRD_EN_PREG,Local init main cursor active high override enable" "0,1"
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bitfld.long 0x08 0.--5. "DRVCTRL_INIT_C0_OVRD_VAL_PREG,When drvctrl_init_c0_ovrd_en_preg is asserted high this value overrides the internally generated value for tx_local_tx_preset_coef_ln_{15:0} [11:6] following a tx_get_local_init_coef_ln_{15:0} request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DRVCTRL_C0_OVRD_PREG__DRVCTRL_CM1_OVRD_PREG_j,Transmit driver pre-emphasis cursor override register"
bitfld.long 0x0C 24. "DRVCTRL_C0_OVRD_EN_PREG,Main cursor active high override enable" "0,1"
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hexmask.long.byte 0x0C 16.--22. 1. "DRVCTRL_C0_OVRD_VAL_PREG,When drvctrl_c0_ovrd_en_preg is asserted high this value overrides the internally calculated main coefficient sent to the analog transmitter circuit"
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bitfld.long 0x0C 8. "DRVCTRL_CM1_OVRD_EN_PREG,Pre-emphasis cursor active high override enable" "0,1"
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hexmask.long.byte 0x0C 0.--6. 1. "DRVCTRL_CM1_OVRD_VAL_PREG,When drvctrl_cm1_ovrd_en_preg is asserted high this value overrides the internally calculated pre-cursor coefficient sent to the analog transmitter circuit"
line.long 0x10 "DRVCTRL_C0M_OVRD_PREG__DRVCTRL_CP1_OVRD_PREG_j,Transmit driver post-emphasis cursor override register"
bitfld.long 0x10 24. "DRVCTRL_C0M_OVRD_EN_PREG,Margin cursor active high override enable" "0,1"
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hexmask.long.byte 0x10 16.--22. 1. "DRVCTRL_C0M_OVRD_VAL_PREG,When drvctrl_c0m_ovrd_en_preg is asserted high this value overrides the internally calculated margin coefficient sent to the analog transmitter circuit"
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bitfld.long 0x10 8. "DRVCTRL_CP1_OVRD_EN_PREG,Post-emphasis cursor active high override enable" "0,1"
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hexmask.long.byte 0x10 0.--6. 1. "DRVCTRL_CP1_OVRD_VAL_PREG,When drvctrl_cp1_ovrd_en_preg is asserted high this value overrides the internally calculated post-emphasis coefficient sent to the analog transmitter circuit"
line.long 0x14 "DRVCTRL_CM1_CV_PREG__DRVCTRL_ATTEN_PREG_j,Transmit driver attenuation control register"
hexmask.long.byte 0x14 16.--22. 1. "CM1VAL,Current pre-emphasis cursor value to analog driver"
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bitfld.long 0x14 8. "DRVCTRL_ATTEN_VMARGIN_SEL_PREG,When asserted high the driver attenuation is controlled through tx_vmargin_ln_{15:0}" "0,1"
newline
bitfld.long 0x14 3. "DRVCTRL_ATTEN_OVRD_EN_PREG,Driver attenuation active high override enable" "0,1"
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bitfld.long 0x14 0.--2. "DRVCTRL_ATTEN_OVRD_VAL_PREG,When drvctrl_atten_ovrd_en_preg is asserted high this value overrides the internally calculated attenuation for the transmit driver" "0,1,2,3,4,5,6,7"
line.long 0x18 "DRVCTRL_CP1_CV_PREG__DRVCTRL_C0_CV_PREG_j,Transmit driver main cursor status register"
hexmask.long.byte 0x18 16.--22. 1. "CP1VAL,Current post-emphasis cursor value to analog driver"
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hexmask.long.byte 0x18 0.--6. 1. "C0VAL,Current main cursor value to analog driver"
line.long 0x1C "DRVCTRL_BOOST_PREG__DRVCTRL_C0M_CV_PREG_j,Transmit driver margin status register"
bitfld.long 0x1C 31. "DRVCTRL_AMPBOOST_EN_PREG,Amplitude boost active high enable" "0,1"
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bitfld.long 0x1C 27.--28. "DRVCTRL_AMPBOOST_OFFADJUST_PREG,When amplitude boost is disabled the calibrated resistor calibration value is increased by this value compensating for the boost circuit impedance contribution no longer present" "0,1,2,3"
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bitfld.long 0x1C 24.--26. "DRVCTRL_AMPBOOST_TUNE_PREG,Amplitude boost selection" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 16.--17. "DRVCTRL_EDGEBOOST_TUNE_PREG,Edge boost selection" "0,1,2,3"
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hexmask.long.byte 0x1C 0.--6. 1. "C0MVAL,Current margin value to analog driver"
line.long 0x20 "LANE_TX_RECEIVER_DETECT_PREG__DRVCTRL_BSCAN_PREG_j,Transmit driver boundary scan resistor calibration override register"
hexmask.long.word 0x20 16.--31. 1. "TX_RCVDET_WAIT_TIME_PREG,Receiver detection wait time"
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bitfld.long 0x20 0.--3. "DRVCTRL_BSCAN_RESCAL_PREG,Transmit driver resistor calibration level used in boundary scan operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "TX_RCVDET_OVRD_PREG_j,Transmit driver receiver detection analog override Offset = 40E4h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x24 1. "TX_RCVDET_OVRD_EN_PREG,Receiver detection analog override enable" "0,1"
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bitfld.long 0x24 0. "TX_RCVDET_OVRD_PREG,Receiver detection analog override" "0,1"
line.long 0x28 "TXCOEF_STATUS_PREG_j,Transmit coefficient calculator status register"
bitfld.long 0x28 0.--2. "TXCOEF_STATE,Transmit coefficient calculator state vector" "0,1,2,3,4,5,6,7"
group.long 0x40F0++0x03
line.long 0x00 "LANE_TX_BIST_UDD_PREG__TX_BIST_CONTROLS_PREG_j,Transmit BIST control register"
hexmask.long.word 0x00 16.--25. 1. "TX_UDD_FIFO_WR_DATA,Transmit BIST user defined data"
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bitfld.long 0x00 9. "TX_BIST_UDD_WR_CLEAR_PREG,Transmit BIST User Defined Data (UDD) FIFO write pointer clear" "0,1"
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bitfld.long 0x00 8. "TX_BIST_FORCE_ERROR_PREG,Transmit BIST force error toggle bit" "0,1"
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bitfld.long 0x00 5.--7. "TX_BIST_PRBS_SEED_PREG,Transmit BIST PRBS seed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--4. "TX_BIST_MODE_PREG,Transmit BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "TX_BIST_EN_PREG,Transmit BIST active high enable" "0,1"
rgroup.long 0x40F8++0x03
line.long 0x00 "TX_LFPSGEN_STATUS_PREG_j,Transmit LFPS generator status register"
bitfld.long 0x00 0.--3. "TX_LFPSGEN_STATE,Transmit LFPS generator state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4100++0x03
line.long 0x00 "CLKPATHCTRL_TMR_PREG__CLKPATHCTRL_OVR_PREG_j,Receive clock path controller override register"
bitfld.long 0x00 31. "CLKPATHCTRL_SSCEN_PREG,Receive clock recovery timer selection" "0,1"
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bitfld.long 0x00 24.--26. "CLKPATHCTRL_SSCTMRVAL_PREG,Receive clock recovery lock timer with spread spectrum system" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 16.--23. 1. "CLKPATHCTRL_NOSSCTMRVAL_PREG,Receive clock recovery lock timer without spread spectrum system"
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bitfld.long 0x00 9. "CLKPATHCTRL_RDYOVREN_PREG,Receive clock path ready signal to data path (deq_clkpathrdy) active high override enable" "0,1"
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bitfld.long 0x00 8. "CLKPATHCTRL_RDYOVRVAL_PREG,When clkpathctrl_rdyovren_preg is asserted high this value will override the clock path controller generated ready signal (deq_ clkpathrdy)" "0,1"
group.long 0x4108++0x6B
line.long 0x00 "RX_CREQ_FLTR_A_MODE3_PREG_j,RX_CREQ_FLTR_A_MODE3_PREG Offset = 4108h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x00 31. "CREQ_CRFLTR_RSTACCUM2ONSAT_MODE3_PREG,Clock recovery filter 's integral path accumulator reset on saturation control when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 30. "CREQ_CRFLTR_CRHOLD_MODE3_PREG,Clock recovery hold active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 27. "CREQ_CRFLTR_SUBSUMINV_MODE3_PREG,Clock recovery filter inversion active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x00 24.--26. "CREQ_CRFLTR_LEAKFREQ_MODE3_PREG,Clock recovery integral path leak frequency when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 22.--23. "CREQ_CRFLTR_GAIN1_MODE3_PREG,Clock recovery combined proportional and integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x00 19.--21. "CREQ_CRFLTR_GAIN2_MODE3_PREG,Clock recovery integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--18. "CREQ_CRFLTR_ACCUMSAT2_MODE3_PREG,Clock Recovery integral path accumulator saturation level when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x00 16. "CREQ_CRFLTR_HIRES_MODE3_PREG,CPI high resolution enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
line.long 0x04 "RX_CREQ_FLTR_A_MODE1_PREG__RX_CREQ_FLTR_A_MODE2_PREG_j,RX_CREQ_FLTR_A_MODE1_PREG__RX_CREQ_FLTR_A_MODE2_PREG Offset = 410Ch + (j * 400h); where j = 0h to 1h"
bitfld.long 0x04 31. "CREQ_CRFLTR_RSTACCUM2ONSAT_MODE1_PREG,Clock recovery filter 's integral path accumulator reset on saturation control when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x04 30. "CREQ_CRFLTR_CRHOLD_MODE1_PREG,Clock recovery hold active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x04 27. "CREQ_CRFLTR_SUBSUMINV_MODE1_PREG,Clock recovery filter inversion active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x04 24.--26. "CREQ_CRFLTR_LEAKFREQ_MODE1_PREG,Clock recovery integral path leak frequency when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 22.--23. "CREQ_CRFLTR_GAIN1_MODE1_PREG,Clock recovery combined proportional and integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x04 19.--21. "CREQ_CRFLTR_GAIN2_MODE1_PREG,Clock recovery integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 17.--18. "CREQ_CRFLTR_ACCUMSAT2_MODE1_PREG,Clock Recovery integral path accumulator saturation level when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x04 16. "CREQ_CRFLTR_HIRES_MODE1_PREG,CPI high resolution enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x04 15. "CREQ_CRFLTR_RSTACCUM2ONSAT_MODE2_PREG,Clock recovery filter 's integral path accumulator reset on saturation control when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x04 14. "CREQ_CRFLTR_CRHOLD_MODE2_PREG,Clock recovery hold active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x04 11. "CREQ_CRFLTR_SUBSUMINV_MODE2_PREG,Clock recovery filter inversion active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x04 8.--10. "CREQ_CRFLTR_LEAKFREQ_MODE2_PREG,Clock recovery integral path leak frequency when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 6.--7. "CREQ_CRFLTR_GAIN1_MODE2_PREG,Clock recovery combined proportional and integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x04 3.--5. "CREQ_CRFLTR_GAIN2_MODE2_PREG,Clock recovery integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 1.--2. "CREQ_CRFLTR_ACCUMSAT2_MODE2_PREG,Clock Recovery integral path accumulator saturation level when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x04 0. "CREQ_CRFLTR_HIRES_MODE2_PREG,CPI high resolution enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
line.long 0x08 "RX_CREQ_FLTR_B_PREG__RX_CREQ_FLTR_A_MODE0_PREG_j,Receive clock recovery filter control register A"
bitfld.long 0x08 28. "CREQ_CRFLTR_LOWLATENCYEN_MODE3_PREG,This value sets the low latency mode enable from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x08 24. "CREQ_CRFLTR_LOWLATENCYEN_MODE2_PREG,This value sets the low latency mode enable from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x08 20. "CREQ_CRFLTR_LOWLATENCYEN_MODE1_PREG,This value sets the low latency mode enable from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x08 16. "CREQ_CRFLTR_LOWLATENCYEN_MODE0_PREG,This value sets the low latency mode enable from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x08 15. "CREQ_CRFLTR_RSTACCUM2ONSAT_MODE0_PREG,Clock recovery filter 's integral path accumulator reset on saturation control when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x08 14. "CREQ_CRFLTR_CRHOLD_MODE0_PREG,Clock recovery hold active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x08 11. "CREQ_CRFLTR_SUBSUMINV_MODE0_PREG,Clock recovery filter inversion active high enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x08 8.--10. "CREQ_CRFLTR_LEAKFREQ_MODE0_PREG,Clock recovery integral path leak frequency when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 6.--7. "CREQ_CRFLTR_GAIN1_MODE0_PREG,Clock recovery combined proportional and integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3"
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bitfld.long 0x08 3.--5. "CREQ_CRFLTR_GAIN2_MODE0_PREG,Clock recovery integral path gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 1.--2. "CREQ_CRFLTR_ACCUMSAT2_MODE0_PREG,Clock Recovery integral path accumulator saturation level: Limit" "0,1,2,3"
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bitfld.long 0x08 0. "CREQ_CRFLTR_HIRES_MODE0_PREG,CPI high resolution enable when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
line.long 0x0C "RX_CPI_OVERRIDE_PREG__RX_CREQ_CR_BUMP_PREG_j,Receive clock recovery bump feature control register"
bitfld.long 0x0C 23. "CREQ_CPI_OVREN_PREG,CPI phase active high override enable" "0,1"
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hexmask.long.byte 0x0C 16.--22. 1. "CREQ_CPI_OVR_PREG,When creq_cpi_ovren_preg is asserted high this value will override the clock recovery filter CPI binary phase"
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bitfld.long 0x0C 14. "RXDA_CREQ_CRFLTR_BUMPEN_PREG,Clock recover bump feature active high enable" "0,1"
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hexmask.long.byte 0x0C 7.--13. 1. "RXDA_CREQ_CRFLTR_INACTIVTHRESHOLD_PREG,Clock recover bump feature inactivity threshold"
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hexmask.long.byte 0x0C 0.--6. 1. "RXDA_CREQ_CRFLTR_BUMPTHRESHOLD_PREG,Clock recover bump feature bump threshold"
line.long 0x10 "CREQ_CCLKDET_MODE23_PREG__CREQ_DCBIASATTEN_OVR_PREG_j,Receive clock path DC bias attenuation override register"
hexmask.long.byte 0x10 24.--31. 1. "CREQ_CLKDET_TIMERVAL_MODE3_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_{15:0}[2:0] is 3'b011"
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hexmask.long.byte 0x10 16.--23. 1. "CREQ_CLKDET_TIMERVAL_MODE2_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_{15:0}[2:0] is 3'b010"
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bitfld.long 0x10 12. "CREQ_CLKDETEN_FORCE_PREG,When asserted the ctleclk_clkdeten output of rxana_creq is forced high" "0,1"
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bitfld.long 0x10 1. "CREQ_DCBIASATTEN_OVREN_PREG,Clock path CTLE DC bias attenuation active high override enable" "0,1"
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bitfld.long 0x10 0. "CREQ_DCBIASATTEN_OVRVAL_PREG,When creq_dcbiasatten_ovren_preg is asserted high this value overrides the internally generated control to ctleclk_dcbiasatten" "0,1"
line.long 0x14 "RX_CTLE_CAL_PREG__CREQ_CCLKDET_MODE01_PREG_j,Receive clock path CTLE clock detection register for standard modes 0 and 1"
bitfld.long 0x14 31. "CREQ_CTRL_EQOVREN_PREG,Receive clock path CTLE equalization pointer active high override enable" "0,1"
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bitfld.long 0x14 27.--30. "CREQ_CTLE_EQOVR_PREG,When creq_ctrl_eqovren_preg is asserted high this value overrides rxda_creq_eqptr in selecting the appropriate CTLE LUT entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 25. "CREQ_CTLE_OSENB_PREG,Receive clock path CTLE offset calibration algorithm active low maintenance enable" "0,1"
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bitfld.long 0x14 23. "CREQ_CTLE_OFFSETOVREN_PREG,Receive clock path CTLE offset calibration active high override enable" "0,1"
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bitfld.long 0x14 16.--21. "CREQ_CTLE_OFFSETOVR_PREG,When creq_ctle_offsetovren_preg is asserted high this value overrides the calibration algorithm binary data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 8.--15. 1. "CREQ_CLKDET_TIMERVAL_MODE1_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_{15:0}[2:0] is 3'b001"
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hexmask.long.byte 0x14 0.--7. 1. "CREQ_CLKDET_TIMERVAL_MODE0_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_{15:0}[2:0] is 3'b000"
line.long 0x18 "RX_CTLE_MAINTENANCE_PREG__RX_CTLE_CTRL_PREG_j,Receive clock path CTLE Control register"
bitfld.long 0x18 24.--25. "CREQ_FSM_EQMAINTAVEDLY_PREG,Receive clock path CTLE equalization maintenance averaging timer" "0,1,2,3"
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bitfld.long 0x18 20.--21. "CREQ_FSM_OSMAINTWAIT_PREG,Receive clock path CTLE offset calibration maintenance hold off timer" "0,1,2,3"
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bitfld.long 0x18 18.--19. "CREQ_FSM_FULL_SCALE_SEL_PREG,Offset maintenance filter threshold" "0,1,2,3"
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bitfld.long 0x18 16.--17. "CREQ_FSM_OSMAINTAVEDLY_PREG,Receive clock path CTLE offset calibration maintenance =averaging timer" "0,1,2,3"
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bitfld.long 0x18 13. "CREQ_CTLESTART_OVRVAL_PREG,When creq_ctlestart_ovren_preg is asserted this value overrides the receive clock path CTLE FSM start signal from the clock path controller" "0,1"
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bitfld.long 0x18 12. "CREQ_CTLESTART_OVREN_PREG,Receive clock path CTLE start active high override enable" "0,1"
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bitfld.long 0x18 9. "CREQ_CTLESTART_ACK_OVRVAL_PREG,When creq_ctlestart_ack_ovren_preg is asserted this value overrides the receive clock path CTLE FSM start signal acknowledge to the clock path controller" "0,1"
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bitfld.long 0x18 8. "CREQ_CTLESTART_ACK_OVREN_PREG,Receive clock path CTLE start acknowledge active high override enable" "0,1"
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bitfld.long 0x18 4. "CREQ_CTLEHOLD_FORCE_PREG,Receive clock path CTLE FSM hold active high force" "0,1"
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bitfld.long 0x18 1. "CREQ_CTLEHOLD_ACK_OVRVAL_PREG,Receive clock path CTLE FSM hold acknowledge active high override value" "0,1"
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bitfld.long 0x18 0. "CREQ_CTLEHOLD_ACK_OVREN_PREG,Receive clock path CTLE FSM hold acknowledge active high override enable" "0,1"
line.long 0x1C "CREQ_EQ_CTRL_PREG__CREQ_FSMCLK_SEL_PREG_j,Receive clock recovery and equalization (CREQ) state machine clock division register"
bitfld.long 0x1C 28.--29. "CREQ_HS_IQ_HISTORY_PREG,Lookback history selection for Undereq/Overeq function" "0,1,2,3"
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bitfld.long 0x1C 24.--25. "CREQ_HS_EQ_BIAS_PREG,Programmable bias control where larger values provides more equalization" "0,1,2,3"
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bitfld.long 0x1C 19. "CREQ_FSM_OPEN_EYE_STANDARD_MODE3_PREG,When asserted clock path equalization will not be performed when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x1C 18. "CREQ_FSM_OPEN_EYE_STANDARD_MODE2_PREG,When asserted clock path equalization will not be performed when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x1C 17. "CREQ_FSM_OPEN_EYE_STANDARD_MODE1_PREG,When asserted clock path equalization will not be performed when xcvr_standard_mode_ln{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x1C 16. "CREQ_FSM_OPEN_EYE_STANDARD_MODE0_PREG,When asserted clock path equalization will not be performed when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000" "0,1"
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bitfld.long 0x1C 12.--13. "CREQ_FSMCLK_SEL_MODE3_PREG,This value sets the Clock recovery and equalization (CREQ) state machine clock fsmclk division ratio from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0} [2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x1C 8.--9. "CREQ_FSMCLK_SEL_MODE2_PREG,This value sets the Clock recovery and equalization (CREQ) state machine clock fsmclk division ratio from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0} [2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x1C 4.--5. "CREQ_FSMCLK_SEL_MODE1_PREG,This value sets the Clock recovery and equalization (CREQ) state machine clock fsmclk division ratio from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0} [2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x1C 0.--1. "CREQ_FSMCLK_SEL_MODE0_PREG,This value sets the Clock recovery and equalization (CREQ) state machine clock fsmclk division ratio from the Lane Standards Decoder when xcvr_standard_mode_ln{15:0} [2:0] is 3'b000" "0,1,2,3"
line.long 0x20 "RX_CREQ_DIAG_READ__RX_CREQ_DIAG_SEL_PREG_j,Receive clock recovery and equalization (CREQ) diagnostic bus control register"
hexmask.long.word 0x20 16.--31. 1. "CREQ_DIAG_DATA,Clock recovery and equalization (CREQ) diagnostic bus"
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bitfld.long 0x20 10. "RXDA_CREQ_DIAGCAPT_PREG,Clock recovery and equalization (CREQ) diagnostic bus active high capture signal" "0,1"
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bitfld.long 0x20 9. "CREQ_CR_ACCUM2_STICKY_CLR_PREG,Clock recovery integral path accumulator sticky saturation clear" "0,1"
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bitfld.long 0x20 8. "CREQ_HS_RESULT_STICKY_CLR_PREG,Clock path equalization high-speed circuit result sticky saturation clear" "0,1"
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hexmask.long.byte 0x20 0.--7. 1. "CREQ_DIAGSEL_PREG,Clock recovery and equalization (CREQ) diagnostic bus selection"
line.long 0x24 "CREQ_EQ_OPEN_EYE_THRESH_PREG__CREQ_SPARE_PREG_j,CREQ spare and speedup register Offset = 412Ch + (j * 400h); where j = 0h to 1h"
bitfld.long 0x24 28.--31. "CREQ_EQ_OPEN_EYE_THRESH_SEL_MODE3_PREG,Selects number of ctle_open_eye (bad codes) to declare a CTLE LUT setting invalid when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. "CREQ_EQ_OPEN_EYE_THRESH_SEL_MODE2_PREG,Selects number of ctle_open_eye (bad codes) to declare a CTLE LUT setting invalid when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "CREQ_EQ_OPEN_EYE_THRESH_SEL_MODE1_PREG,Selects number of ctle_open_eye (bad codes) to declare a CTLE LUT setting invalid when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "CREQ_EQ_OPEN_EYE_THRESH_SEL_MODE0_PREG,Selects number of ctle_open_eye (bad codes) to declare a CTLE LUT setting invalid when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 15. "CREQ_SPEEDUP_PREG,CREQ active high simulation only speedup enable" "0,1"
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bitfld.long 0x24 0.--1. "CREQ_SPARE_PREG,Spare register bits assigned to rxda_creq_spare[1:0]" "0,1,2,3"
line.long 0x28 "CTLELUT_OVRDCTRL_PREG__CTLELUT_CTRL_PREG_j,Receive clock Path CTLE LUT control register"
bitfld.long 0x28 31. "CTLELUT_OVREN_PREG,Receive clock Path CTLE LUT active high override table enable" "0,1"
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bitfld.long 0x28 12.--15. "CTLELUT_SEL_MODE3_PREG,Selects the CTLE LUT from the Lane Standards Decoder to use when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 8.--11. "CTLELUT_SEL_MODE2_PREG,Selects the CTLE LUT from the Lane Standards Decoder to use when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 4.--7. "CTLELUT_SEL_MODE1_PREG,Selects the CTLE LUT from the Lane Standards Decoder to use when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "CTLELUT_SEL_MODE0_PREG,Selects the CTLE LUT from the Lane Standards Decoder to use when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CTLELUT_OVR_0B_PREG__CTLELUT_OVR_0A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 0 register"
bitfld.long 0x2C 26. "CTLELUT_INDEN1OVR_0_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 0" "0,1"
newline
bitfld.long 0x2C 25. "CTLELUT_INDEN2OVR_0_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 0" "0,1"
newline
bitfld.long 0x2C 24. "CTLELUT_INDEN3OVR_0_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 0" "0,1"
newline
bitfld.long 0x2C 16.--19. "CTLELUT_CSELOVR_0_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 12.--14. "CTLELUT_RATESEL1OVR_0_PREG,Clock Path CTLE LUT ratesel1 Override Value Entry 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 8.--10. "CTLELUT_RATESEL2OVR_0_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 4.--6. "CTLELUT_RATESEL3OVR_0_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 0. "CTLELUT_RATESEL4OVR_0_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 0" "0,1"
line.long 0x30 "CTLELUT_OVR_1B_PREG__CTLELUT_OVR_1A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 1 register"
bitfld.long 0x30 26. "CTLELUT_INDEN1OVR_1_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 1" "0,1"
newline
bitfld.long 0x30 25. "CTLELUT_INDEN2OVR_1_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 1" "0,1"
newline
bitfld.long 0x30 24. "CTLELUT_INDEN3OVR_1_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 1" "0,1"
newline
bitfld.long 0x30 16.--19. "CTLELUT_CSELOVR_1_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x30 12.--14. "CTLELUT_RATESEL1OVR_1_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 8.--10. "CTLELUT_RATESEL2OVR_1_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 4.--6. "CTLELUT_RATESEL3OVR_1_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 0. "CTLELUT_RATESEL4OVR_1_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 1" "0,1"
line.long 0x34 "CTLELUT_OVR_2B_PREG__CTLELUT_OVR_2A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 2 register"
bitfld.long 0x34 26. "CTLELUT_INDEN1OVR_2_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 2" "0,1"
newline
bitfld.long 0x34 25. "CTLELUT_INDEN2OVR_2_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 2" "0,1"
newline
bitfld.long 0x34 24. "CTLELUT_INDEN3OVR_2_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 2" "0,1"
newline
bitfld.long 0x34 16.--19. "CTLELUT_CSELOVR_2_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x34 12.--14. "CTLELUT_RATESEL1OVR_2_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 8.--10. "CTLELUT_RATESEL2OVR_2_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 4.--6. "CTLELUT_RATESEL3OVR_2_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 0. "CTLELUT_RATESEL4OVR_2_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 2" "0,1"
line.long 0x38 "CTLELUT_OVR_3B_PREG__CTLELUT_OVR_3A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 3 register"
bitfld.long 0x38 26. "CTLELUT_INDEN1OVR_3_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 3" "0,1"
newline
bitfld.long 0x38 25. "CTLELUT_INDEN2OVR_3_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 3" "0,1"
newline
bitfld.long 0x38 24. "CTLELUT_INDEN3OVR_3_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 3" "0,1"
newline
bitfld.long 0x38 16.--19. "CTLELUT_CSELOVR_3_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 12.--14. "CTLELUT_RATESEL1OVR_3_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 8.--10. "CTLELUT_RATESEL2OVR_3_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 4.--6. "CTLELUT_RATESEL3OVR_3_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 0. "CTLELUT_RATESEL4OVR_3_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 3" "0,1"
line.long 0x3C "CTLELUT_OVR_4B_PREG__CTLELUT_OVR_4A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 4 register"
bitfld.long 0x3C 26. "CTLELUT_INDEN1OVR_4_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 4" "0,1"
newline
bitfld.long 0x3C 25. "CTLELUT_INDEN2OVR_4_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 4" "0,1"
newline
bitfld.long 0x3C 24. "CTLELUT_INDEN3OVR_4_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 4" "0,1"
newline
bitfld.long 0x3C 16.--19. "CTLELUT_CSELOVR_4_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x3C 12.--14. "CTLELUT_RATESEL1OVR_4_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 8.--10. "CTLELUT_RATESEL2OVR_4_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 4.--6. "CTLELUT_RATESEL3OVR_4_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 0. "CTLELUT_RATESEL4OVR_4_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 4" "0,1"
line.long 0x40 "CTLELUT_OVR_5B_PREG__CTLELUT_OVR_5A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 5 register"
bitfld.long 0x40 26. "CTLELUT_INDEN1OVR_5_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 5" "0,1"
newline
bitfld.long 0x40 25. "CTLELUT_INDEN2OVR_5_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 5" "0,1"
newline
bitfld.long 0x40 24. "CTLELUT_INDEN3OVR_5_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 5" "0,1"
newline
bitfld.long 0x40 16.--19. "CTLELUT_CSELOVR_5_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x40 12.--14. "CTLELUT_RATESEL1OVR_5_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 8.--10. "CTLELUT_RATESEL2OVR_5_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 4.--6. "CTLELUT_RATESEL3OVR_5_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 0. "CTLELUT_RATESEL4OVR_5_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 5" "0,1"
line.long 0x44 "CTLELUT_OVR_6B_PREG__CTLELUT_OVR_6A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 6 register"
bitfld.long 0x44 26. "CTLELUT_INDEN1OVR_6_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 6" "0,1"
newline
bitfld.long 0x44 25. "CTLELUT_INDEN2OVR_6_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 6" "0,1"
newline
bitfld.long 0x44 24. "CTLELUT_INDEN3OVR_6_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 6" "0,1"
newline
bitfld.long 0x44 16.--19. "CTLELUT_CSELOVR_6_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x44 12.--14. "CTLELUT_RATESEL1OVR_6_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 8.--10. "CTLELUT_RATESEL2OVR_6_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 4.--6. "CTLELUT_RATESEL3OVR_6_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 0. "CTLELUT_RATESEL4OVR_6_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 6" "0,1"
line.long 0x48 "CTLELUT_OVR_7B_PREG__CTLELUT_OVR_7A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 7 register"
bitfld.long 0x48 26. "CTLELUT_INDEN1OVR_7_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 7" "0,1"
newline
bitfld.long 0x48 25. "CTLELUT_INDEN2OVR_7_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 7" "0,1"
newline
bitfld.long 0x48 24. "CTLELUT_INDEN3OVR_7_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 7" "0,1"
newline
bitfld.long 0x48 16.--19. "CTLELUT_CSELOVR_7_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x48 12.--14. "CTLELUT_RATESEL1OVR_7_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 8.--10. "CTLELUT_RATESEL2OVR_7_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 4.--6. "CTLELUT_RATESEL3OVR_7_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 0. "CTLELUT_RATESEL4OVR_7_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 7" "0,1"
line.long 0x4C "CTLELUT_OVR_8B_PREG__CTLELUT_OVR_8A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 8 register"
bitfld.long 0x4C 26. "CTLELUT_INDEN1OVR_8_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 8" "0,1"
newline
bitfld.long 0x4C 25. "CTLELUT_INDEN2OVR_8_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 8" "0,1"
newline
bitfld.long 0x4C 24. "CTLELUT_INDEN3OVR_8_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 8" "0,1"
newline
bitfld.long 0x4C 16.--19. "CTLELUT_CSELOVR_8_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x4C 12.--14. "CTLELUT_RATESEL1OVR_8_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 8" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 8.--10. "CTLELUT_RATESEL2OVR_8_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 8" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 4.--6. "CTLELUT_RATESEL3OVR_8_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 8" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 0. "CTLELUT_RATESEL4OVR_8_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 8" "0,1"
line.long 0x50 "CTLELUT_OVR_9B_PREG__CTLELUT_OVR_9A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 9 register"
bitfld.long 0x50 26. "CTLELUT_INDEN1OVR_9_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 9" "0,1"
newline
bitfld.long 0x50 25. "CTLELUT_INDEN2OVR_9_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 9" "0,1"
newline
bitfld.long 0x50 24. "CTLELUT_INDEN3OVR_9_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 9" "0,1"
newline
bitfld.long 0x50 16.--19. "CTLELUT_CSELOVR_9_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x50 12.--14. "CTLELUT_RATESEL1OVR_9_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 9" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 8.--10. "CTLELUT_RATESEL2OVR_9_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 9" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 4.--6. "CTLELUT_RATESEL3OVR_9_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 9" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 0. "CTLELUT_RATESEL4OVR_9_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 9" "0,1"
line.long 0x54 "CTLELUT_OVR_10B_PREG__CTLELUT_OVR_10A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 10 register"
bitfld.long 0x54 26. "CTLELUT_INDEN1OVR_10_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 10" "0,1"
newline
bitfld.long 0x54 25. "CTLELUT_INDEN2OVR_10_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 10" "0,1"
newline
bitfld.long 0x54 24. "CTLELUT_INDEN3OVR_10_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 10" "0,1"
newline
bitfld.long 0x54 16.--19. "CTLELUT_CSELOVR_10_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x54 12.--14. "CTLELUT_RATESEL1OVR_10_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 10" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 8.--10. "CTLELUT_RATESEL2OVR_10_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 10" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 4.--6. "CTLELUT_RATESEL3OVR_10_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 10" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 0. "CTLELUT_RATESEL4OVR_10_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 10" "0,1"
line.long 0x58 "CTLELUT_OVR_11B_PREG__CTLELUT_OVR_11A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 11 register"
bitfld.long 0x58 26. "CTLELUT_INDEN1OVR_11_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 11" "0,1"
newline
bitfld.long 0x58 25. "CTLELUT_INDEN2OVR_11_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 11" "0,1"
newline
bitfld.long 0x58 24. "CTLELUT_INDEN3OVR_11_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 11" "0,1"
newline
bitfld.long 0x58 16.--19. "CTLELUT_CSELOVR_11_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x58 12.--14. "CTLELUT_RATESEL1OVR_11_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 11" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 8.--10. "CTLELUT_RATESEL2OVR_11_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 11" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 4.--6. "CTLELUT_RATESEL3OVR_11_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 11" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 0. "CTLELUT_RATESEL4OVR_11_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 11" "0,1"
line.long 0x5C "CTLELUT_OVR_12B_PREG__CTLELUT_OVR_12A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 12 register"
bitfld.long 0x5C 26. "CTLELUT_INDEN1OVR_12_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 12" "0,1"
newline
bitfld.long 0x5C 25. "CTLELUT_INDEN2OVR_12_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 12" "0,1"
newline
bitfld.long 0x5C 24. "CTLELUT_INDEN3OVR_12_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 12" "0,1"
newline
bitfld.long 0x5C 16.--19. "CTLELUT_CSELOVR_12_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x5C 12.--14. "CTLELUT_RATESEL1OVR_12_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 12" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 8.--10. "CTLELUT_RATESEL2OVR_12_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 12" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 4.--6. "CTLELUT_RATESEL3OVR_12_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 12" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 0. "CTLELUT_RATESEL4OVR_12_PREG,Clock Path CTLE LUT stage 4 tdata rate per bandwidth selection override Entry 12" "0,1"
line.long 0x60 "CTLELUT_OVR_13B_PREG__CTLELUT_OVR_13A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 13 register"
bitfld.long 0x60 26. "CTLELUT_INDEN1OVR_13_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 13" "0,1"
newline
bitfld.long 0x60 25. "CTLELUT_INDEN2OVR_13_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 13" "0,1"
newline
bitfld.long 0x60 24. "CTLELUT_INDEN3OVR_13_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 13" "0,1"
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bitfld.long 0x60 16.--19. "CTLELUT_CSELOVR_13_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x60 12.--14. "CTLELUT_RATESEL1OVR_13_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 13" "0,1,2,3,4,5,6,7"
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bitfld.long 0x60 8.--10. "CTLELUT_RATESEL2OVR_13_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 13" "0,1,2,3,4,5,6,7"
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bitfld.long 0x60 4.--6. "CTLELUT_RATESEL3OVR_13_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 13" "0,1,2,3,4,5,6,7"
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bitfld.long 0x60 0. "CTLELUT_RATESEL4OVR_13_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 13" "0,1"
line.long 0x64 "CTLELUT_OVR_14B_PREG__CTLELUT_OVR_14A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 14 register"
bitfld.long 0x64 26. "CTLELUT_INDEN1OVR_14_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 14" "0,1"
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bitfld.long 0x64 25. "CTLELUT_INDEN2OVR_14_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 14" "0,1"
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bitfld.long 0x64 24. "CTLELUT_INDEN3OVR_14_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 14" "0,1"
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bitfld.long 0x64 16.--19. "CTLELUT_CSELOVR_14_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x64 12.--14. "CTLELUT_RATESEL1OVR_14_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 14" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 8.--10. "CTLELUT_RATESEL2OVR_14_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 14" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 4.--6. "CTLELUT_RATESEL3OVR_14_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 14" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 0. "CTLELUT_RATESEL4OVR_14_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 14" "0,1"
line.long 0x68 "CTLELUT_OVR_15B_PREG__CTLELUT_OVR_15A_PREG_j,Receive clock path CTLE LUT ratesel override. entry 15 register"
bitfld.long 0x68 26. "CTLELUT_INDEN1OVR_15_PREG,Clock Path CTLE LUT stage 1 active high inductor enable override Entry 15" "0,1"
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bitfld.long 0x68 25. "CTLELUT_INDEN2OVR_15_PREG,Clock Path CTLE LUT stage 2 active high inductor enable override Entry 15" "0,1"
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bitfld.long 0x68 24. "CTLELUT_INDEN3OVR_15_PREG,Clock Path CTLE LUT stage 3 active high inductor enable override Entry 15" "0,1"
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bitfld.long 0x68 16.--19. "CTLELUT_CSELOVR_15_PREG,Clock Path CTLE LUT binary encoded boost / peaking control override Entry 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x68 12.--14. "CTLELUT_RATESEL1OVR_15_PREG,Clock Path CTLE LUT stage 1 thermometer encoded data rate per bandwidth selection override Entry 15" "0,1,2,3,4,5,6,7"
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bitfld.long 0x68 8.--10. "CTLELUT_RATESEL2OVR_15_PREG,Clock Path CTLE LUT stage 2 thermometer encoded data rate per bandwidth selection override Entry 15" "0,1,2,3,4,5,6,7"
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bitfld.long 0x68 4.--6. "CTLELUT_RATESEL3OVR_15_PREG,Clock Path CTLE LUT stage 3 thermometer encoded data rate per bandwidth selection override Entry 15" "0,1,2,3,4,5,6,7"
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bitfld.long 0x68 0. "CTLELUT_RATESEL4OVR_15_PREG,Clock Path CTLE LUT stage 4 data rate per bandwidth selection override Entry 15" "0,1"
group.long 0x4180++0x0B
line.long 0x00 "DFE_SMP_RATESEL_PREG__DFE_ECMP_RATESEL_PREG_j,Receive data path DFE error comparator rate selection register"
bitfld.long 0x00 28.--30. "SMP_RATESEL_MODE3_PREG,This value sets the receive data path DFE sampler rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "SMP_RATESEL_MODE2_PREG,This value sets the receive data path DFE sampler rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--22. "SMP_RATESEL_MODE1_PREG,This value sets the receive data path DFE sampler rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "SMP_RATESEL_MODE0_PREG,This value sets the receive data path DFE sampler rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. "ECMP_RATESEL_MODE3_PREG,This value sets the Lane Standards Decoder driven value for receive data path DFE error comparator rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "ECMP_RATESEL_MODE2_PREG,This value sets the Lane Standards Decoder driven value for receive data path DFE error comparator rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "ECMP_RATESEL_MODE1_PREG,This value sets the Lane Standards Decoder driven value for receive data path DFE error comparator rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "ECMP_RATESEL_MODE0_PREG,This value sets the Lane Standards Decoder driven value for receive data path DFE error comparator rate selection when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
line.long 0x04 "DEQ_DIAG_READ__DEQ_DIAG_SEL_PREG_j,Receive data path equalization (DEQ) diagnostic bus control register"
hexmask.long.word 0x04 16.--31. 1. "DEQ_DIAG_DATA,Receive data path equalization (DEQ) diagnostic bus"
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hexmask.long.byte 0x04 0.--7. 1. "DEQ_DIAG_SEL_PREG,Receive data path equalization (DEQ) diagnostic bus selection"
line.long 0x08 "DEQ_PHALIGN_CTRL_j,Receive data path phase alignment control register Offset = 4188h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x08 0.--1. "DEQ_PHALIGN_SAMPSIZE_PREG,Selection of sample size used to determine the position o f the ecmp_clk_n rising edge in the ST_B1_EVAL state of the rxana_deq_phalign FSM" "0,1,2,3"
group.long 0x4190++0x17
line.long 0x00 "DEQ_CONCUR_CTRL2_PREG__DEQ_CONCUR_CTRL1_PREG_j,Receive data path concurrent equalization control register 1"
bitfld.long 0x00 31. "CONCUR_TIME_SPEEDUP_PREG,Concurrent equalization active high simulation speedup enable" "0,1"
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bitfld.long 0x00 28.--30. "CONCUR_TXACK_TIMEOUT_PREG,Receive closed-eye data path equalization timeout waiting for next rx_eq_eval assertion" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "CONCUR_TIME_MNT_PREG,Receive closed-eye data path equalization concurrent process time during maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "CONCUR_TIME_ACQ_PREG,Receive closed-eye data path equalization concurrent process time during acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "CONCUR_TXACKITER_PREG,Receive closed-eye data path equalization minimum iterations of concur and tau processes after a far-end transmit equalization acknowledgement before a new far-end transmit request can be made" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "DEQ_CLEARSATFLAGS_PREG,Toggle style bit which when written high clears the equalization saturation flags of all concurrent algorithms" "0,1"
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hexmask.long.word 0x00 6.--14. 1. "CONCUR_MINITER_PREG,Receive closed-eye data path equalization minimum iterations of concur and tau processes during acquisition"
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bitfld.long 0x00 0.--5. "CONCUR_MAXTXREQ_PREG,Receive closed-eye data path equalization maximum far-end transmit equalization requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DEQ_FSM_OVR_PREG__DEQ_EPIPWR_CTRL_PREG_j,Receive data path equalization (DEQ) and EPI control register"
bitfld.long 0x04 24. "RX_DEQ_CLK_FORCE_PREG,When asserted rx_deq_clk remains on when ln_rxctrl_deq_fsm whenever rxdatclk is on" "0,1"
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bitfld.long 0x04 18. "DEQ_PHALIGN_DONE_FORCE_PREG,rxda_deq_phalign_done force" "0,1"
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bitfld.long 0x04 17. "CREQ_EQ_ACK_OVREN_PREG,rxda_creq_eq_req acknowledgement override enable" "0,1"
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bitfld.long 0x04 16. "CREQ_EQ_ACK_OVRVAL_PREG,rxda_creq_eq_req acknowledgement override value" "0,1"
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bitfld.long 0x04 15. "DEQ_CLOSEDEYE_MAINT_DISABLE_PREG,Receive data path closed-eye equalization active high disable" "0,1"
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hexmask.long.word 0x04 0.--9. 1. "EPION_TIME_PREG,Receive data path equalization EPI power on settling time"
line.long 0x08 "DEQ_EPIPWR_CTRL2_PREG__CONCUR_PREEVAL_MINITER_CTRL_PREG_j,DEQ_EPIPWR_CTRL2_PREG__CONCUR_PREEVAL_MINITER_CTRL_PREG Offset = 4198h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x08 21.--25. "FAST_MAINT_TIME_PREG,Receive data path closed-eye equalization fast maintenance cycle hold off time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 16.--20. "SLOW_MAINT_TIME_PREG,Receive data path closed-eye equalization slow maintenance cycle hold off time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x08 0.--8. 1. "CONCUR_PREEVAL_MINITER_PREG,Receive closed-eye data path equalization minimum iterations of concur and tau processes during the acquisition phase prior to the initial rx_eq_eval assertion when deq_closedeye_mode = 2'b10"
line.long 0x0C "RX_DEQ_COEF_FIFO_PREG__DEQ_FAST_MAINT_CYCLES_PREG_j,Receive data path equalization (DEQ) fast maintainance cycles register Offset = 419Ch + (j * 400h); where j = 0h to 1h"
rbitfld.long 0x0C 24.--27. "RX_DEQ_COEF_FIFO_OUTDAT,Receive data path equalization emulation mode FIFO output data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 23. "RX_DEQ_COEF_FIFO_EMPTY,Receive data path equalization emulation mode FIFO empty" "0,1"
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bitfld.long 0x0C 22. "RX_DEQ_COEF_FIFO_OVRD_EN_PREG,Receive data path equalization emulation mode FIFO output active high enable" "0,1"
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bitfld.long 0x0C 21. "RX_DEQ_COEF_FIFO_ENQ_CLR,Receive data path equalization emulation mode FIFO enqueue pointer clear" "0,1"
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bitfld.long 0x0C 20. "RX_DEQ_COEF_FIFO_ENQ_EN,Receive data path equalization emulation mode FIFO enqueue enable" "0,1"
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bitfld.long 0x0C 16.--19. "RX_DEQ_COEF_FIFO_ENQ_DATA,Receive data path equalization emulation mode FIFO write data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 0.--7. 1. "DEQ_FAST_MAINT_CYCLES_PREG,Receive data path equalization (deq) fast maintenance cycle count"
line.long 0x10 "DEQ_ERRCMPA_OVR_PREG__DEQ_ERRCMP_CTRL_PREG_j,Receive data path error comparator control register"
bitfld.long 0x10 31. "CMPA_OFF_OVREN_PREG,Receive data path error comparator error comparator A offset override active high enable" "0,1"
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hexmask.long.byte 0x10 24.--30. 1. "CMPA_OFFM_OVR_PREG,When cmpa_off_ovren_preg is asserted high this active high binary encoded value will override the A comparator negative polarity DAC input which introduces a negative offset"
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hexmask.long.byte 0x10 16.--22. 1. "CMPA_OFFP_OVR_PREG,When cmpa_off_ovren_preg is asserted high this active high binary encoded value will override the A comparator positive polarity DAC input which introduces a positive offset"
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hexmask.long.byte 0x10 8.--14. 1. "CMPB_VTH_PREG,Receive data path error comparator error comparator B target level binary encoded"
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hexmask.long.byte 0x10 0.--6. 1. "CMPA_VTH_PREG,Receive data path error comparator error comparator A target level binary encoded"
line.long 0x14 "CMP_AVR_TIMER_PREG__DEQ_ERRCMPB_OVR_PREG_j,Receive data path error comparator B override register"
hexmask.long.byte 0x14 16.--23. 1. "CMP_AVR_TIMER_PREG,Receive data path error comparators A and B average timer value"
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bitfld.long 0x14 15. "CMPB_OFF_OVREN_PREG,Receive data path error comparator error comparator B offset override active high enable" "0,1"
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hexmask.long.byte 0x14 8.--14. 1. "CMPB_OFFM_OVR_PREG,When cmpa_off_ovren_preg is asserted high this active high binary encoded value will override the B comparator negative polarity DAC input which introduces a negative offset"
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hexmask.long.byte 0x14 0.--6. 1. "CMPB_OFFP_OVR_PREG,When cmpa_off_ovren_preg is asserted high this active high binary encoded value will override the B comparator positive polarity DAC input which introduces a positive offset"
group.long 0x41B0++0x03
line.long 0x00 "DEQ_OFFSET_OVR_CTRL_PREG__DEQ_OFFSET_CTRL_PREG_j,Receive data path offset control register"
bitfld.long 0x00 24. "DATOFF_OVREN_PREG,Receive data path offset active high override enable" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "DATOFF_OVR_PREG,When datoff_ovren_preg is asserted high this value overrides the data offset"
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bitfld.long 0x00 8.--11. "DATOFF_THRESH_OE_PREG,Receive data path offset accumulator threshold for open-eye standards" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DATOFF_THRESH_MNT_PREG,Receive data path offset accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DATOFF_THRESH_ACQ_PREG,Receive data path offset accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x41C0++0x03
line.long 0x00 "DEQ_VGATUNE_CTRL_PREG__DEQ_GAIN_CTRL_PREG_j,Receive data path gain and attenuation control register"
bitfld.long 0x00 30.--31. "VGA_VGA2TUNE_N_MODE3_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x00 28.--29. "VGA_VGA2TUNE_N_MODE2_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x00 26.--27. "VGA_VGA2TUNE_N_MODE1_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x00 24.--25. "VGA_VGA2TUNE_N_MODE0_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3"
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bitfld.long 0x00 22.--23. "VGA_VGA1TUNE_N_MODE3_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x00 20.--21. "VGA_VGA1TUNE_N_MODE2_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x00 18.--19. "VGA_VGA1TUNE_N_MODE1_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x00 16.--17. "VGA_VGA1TUNE_N_MODE0_PREG,This value sets the Lane Standards Decoder value when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3"
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bitfld.long 0x00 12. "DATGAIN_OVREN_PREG,Receive data path gain and attenuation look-up table pointer active high override enable" "0,1"
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bitfld.long 0x00 8.--11. "DATGAIN_THRESH_OE_PREG,Receive data path gain accumulator threshold for open-eye standards" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "DATGAIN_THRESH_MNT_PREG,Receive data path gain accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DATGAIN_THRESH_ACQ_PREG,Receive data path gain accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x41D0++0xA3
line.long 0x00 "DEQ_GLUT1__DEQ_GLUT0_j,Receive data path equalization LUT gain. entry 0 register"
bitfld.long 0x00 22.--27. "DATGAIN_VGA2GAIN_1_PREG,Receive data path equalization LUT VGA2 peaking control entry 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "DATGAIN_VGA1GAIN_1_PREG,Receive data path equalization LUT VGA1 peaking control entry 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6.--11. "DATGAIN_VGA2GAIN_0_PREG,Receive data path equalization LUT VGA2 peaking control entry 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "DATGAIN_VGA1GAIN_0_PREG,Receive data path equalization LUT VGA1 peaking control entry 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DEQ_GLUT3__DEQ_GLUT2_j,Receive data path equalization LUT gain. entry 2 register"
bitfld.long 0x04 22.--27. "DATGAIN_VGA2GAIN_3_PREG,Receive data path equalization LUT VGA2 peaking control entry 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "DATGAIN_VGA1GAIN_3_PREG,Receive data path equalization LUT VGA1 peaking control entry 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 6.--11. "DATGAIN_VGA2GAIN_2_PREG,Receive data path equalization LUT VGA2 peaking control entry 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--5. "DATGAIN_VGA1GAIN_2_PREG,Receive data path equalization LUT VGA1 peaking control entry 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DEQ_GLUT5__DEQ_GLUT4_j,Receive data path equalization LUT gain. entry 4 register"
bitfld.long 0x08 22.--27. "DATGAIN_VGA2GAIN_5_PREG,Receive data path equalization LUT VGA2 peaking control entry 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 16.--21. "DATGAIN_VGA1GAIN_5_PREG,Receive data path equalization LUT VGA1 peaking control entry 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 6.--11. "DATGAIN_VGA2GAIN_4_PREG,Receive data path equalization LUT VGA2 peaking control entry 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 0.--5. "DATGAIN_VGA1GAIN_4_PREG,Receive data path equalization LUT VGA1 peaking control entry 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DEQ_GLUT7__DEQ_GLUT6_j,Receive data path equalization LUT gain. entry 6 register"
bitfld.long 0x0C 22.--27. "DATGAIN_VGA2GAIN_7_PREG,Receive data path equalization LUT VGA2 peaking control entry 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 16.--21. "DATGAIN_VGA1GAIN_7_PREG,Receive data path equalization LUT VGA1 peaking control entry 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 6.--11. "DATGAIN_VGA2GAIN_6_PREG,Receive data path equalization LUT VGA2 peaking control entry 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 0.--5. "DATGAIN_VGA1GAIN_6_PREG,Receive data path equalization LUT VGA1 peaking control entry 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DEQ_GLUT9__DEQ_GLUT8_j,Receive data path equalization LUT gain. entry 8 register"
bitfld.long 0x10 22.--27. "DATGAIN_VGA2GAIN_9_PREG,Receive data path equalization LUT VGA2 peaking control entry 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 16.--21. "DATGAIN_VGA1GAIN_9_PREG,Receive data path equalization LUT VGA1 peaking control entry 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 6.--11. "DATGAIN_VGA2GAIN_8_PREG,Receive data path equalization LUT VGA2 peaking control entry 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 0.--5. "DATGAIN_VGA1GAIN_8_PREG,Receive data path equalization LUT VGA1 peaking control entry 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DEQ_GLUT11__DEQ_GLUT10_j,Receive data path equalization LUT gain. entry 10 register"
bitfld.long 0x14 22.--27. "DATGAIN_VGA2GAIN_11_PREG,Receive data path equalization LUT VGA2 peaking control entry 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 16.--21. "DATGAIN_VGA1GAIN_11_PREG,Receive data path equalization LUT VGA1 peaking control entry 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 6.--11. "DATGAIN_VGA2GAIN_10_PREG,Receive data path equalization LUT VGA2 peaking control entry 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 0.--5. "DATGAIN_VGA1GAIN_10_PREG,Receive data path equalization LUT VGA1 peaking control entry 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DEQ_GLUT13__DEQ_GLUT12_j,Receive data path equalization LUT gain. entry 12 register"
bitfld.long 0x18 22.--27. "DATGAIN_VGA2GAIN_13_PREG,Receive data path equalization LUT VGA2 peaking control entry 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x18 16.--21. "DATGAIN_VGA1GAIN_13_PREG,Receive data path equalization LUT VGA1 peaking control entry 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x18 6.--11. "DATGAIN_VGA2GAIN_12_PREG,Receive data path equalization LUT VGA2 peaking control entry 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x18 0.--5. "DATGAIN_VGA1GAIN_12_PREG,Receive data path equalization LUT VGA1 peaking control entry 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DEQ_GLUT15__DEQ_GLUT14_j,Receive data path equalization LUT gain. entry 14 register"
bitfld.long 0x1C 22.--27. "DATGAIN_VGA2GAIN_15_PREG,Receive data path equalization LUT VGA2 peaking control entry 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x1C 16.--21. "DATGAIN_VGA1GAIN_15_PREG,Receive data path equalization LUT VGA1 peaking control entry 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x1C 6.--11. "DATGAIN_VGA2GAIN_14_PREG,Receive data path equalization LUT VGA2 peaking control entry 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x1C 0.--5. "DATGAIN_VGA1GAIN_14_PREG,Receive data path equalization LUT VGA1 peaking control entry 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "DEQ_GLUT17__DEQ_GLUT16_j,Receive data path equalization LUT gain. entry 16 register"
bitfld.long 0x20 22.--27. "DATGAIN_VGA2GAIN_17_PREG,Receive data path equalization LUT VGA2 peaking control entry 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 16.--21. "DATGAIN_VGA1GAIN_17_PREG,Receive data path equalization LUT VGA1 peaking control entry 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 6.--11. "DATGAIN_VGA2GAIN_16_PREG,Receive data path equalization LUT VGA2 peaking control entry 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 0.--5. "DATGAIN_VGA1GAIN_16_PREG,Receive data path equalization LUT VGA1 peaking control entry 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "DEQ_GLUT19__DEQ_GLUT18_j,Receive data path equalization LUT gain. entry 18 register"
bitfld.long 0x24 22.--27. "DATGAIN_VGA2GAIN_19_PREG,Receive data path equalization LUT VGA2 peaking control entry 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 16.--21. "DATGAIN_VGA1GAIN_19_PREG,Receive data path equalization LUT VGA1 peaking control entry 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 6.--11. "DATGAIN_VGA2GAIN_18_PREG,Receive data path equalization LUT VGA2 peaking control entry 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 0.--5. "DATGAIN_VGA1GAIN_18_PREG,Receive data path equalization LUT VGA1 peaking control entry 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "DEQ_GLUT21__DEQ_GLUT20_j,Receive data path equalization LUT gain. entry 20 register"
bitfld.long 0x28 22.--27. "DATGAIN_VGA2GAIN_21_PREG,Receive data path equalization LUT VGA2 peaking control entry 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 16.--21. "DATGAIN_VGA1GAIN_21_PREG,Receive data path equalization LUT VGA1 peaking control entry 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 6.--11. "DATGAIN_VGA2GAIN_20_PREG,Receive data path equalization LUT VGA2 peaking control entry 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 0.--5. "DATGAIN_VGA1GAIN_20_PREG,Receive data path equalization LUT VGA1 peaking control entry 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "DEQ_GLUT23__DEQ_GLUT22_j,Receive data path equalization LUT gain. entry 22 register"
bitfld.long 0x2C 22.--27. "DATGAIN_VGA2GAIN_23_PREG,Receive data path equalization LUT VGA2 peaking control entry 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 16.--21. "DATGAIN_VGA1GAIN_23_PREG,Receive data path equalization LUT VGA1 peaking control entry 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 6.--11. "DATGAIN_VGA2GAIN_22_PREG,Receive data path equalization LUT VGA2 peaking control entry 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 0.--5. "DATGAIN_VGA1GAIN_22_PREG,Receive data path equalization LUT VGA1 peaking control entry 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DEQ_GLUT25__DEQ_GLUT24_j,Receive data path equalization LUT gain. entry 24 register"
bitfld.long 0x30 22.--27. "DATGAIN_VGA2GAIN_25_PREG,Receive data path equalization LUT VGA2 peaking control entry 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 16.--21. "DATGAIN_VGA1GAIN_25_PREG,Receive data path equalization LUT VGA1 peaking control entry 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 6.--11. "DATGAIN_VGA2GAIN_24_PREG,Receive data path equalization LUT VGA2 peaking control entry 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0.--5. "DATGAIN_VGA1GAIN_24_PREG,Receive data path equalization LUT VGA1 peaking control entry 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x34 "DEQ_GLUT27__DEQ_GLUT26_j,Receive data path equalization LUT gain. entry 26 register"
bitfld.long 0x34 22.--27. "DATGAIN_VGA2GAIN_27_PREG,Receive data path equalization LUT VGA2 peaking control entry 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x34 16.--21. "DATGAIN_VGA1GAIN_27_PREG,Receive data path equalization LUT VGA1 peaking control entry 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x34 6.--11. "DATGAIN_VGA2GAIN_26_PREG,Receive data path equalization LUT VGA2 peaking control entry 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x34 0.--5. "DATGAIN_VGA1GAIN_26_PREG,Receive data path equalization LUT VGA1 peaking control entry 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "DEQ_GLUT29__DEQ_GLUT28_j,Receive data path equalization LUT gain. entry 28 register"
bitfld.long 0x38 22.--27. "DATGAIN_VGA2GAIN_29_PREG,Receive data path equalization LUT VGA2 peaking control entry 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 16.--21. "DATGAIN_VGA1GAIN_29_PREG,Receive data path equalization LUT VGA1 peaking control entry 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 6.--11. "DATGAIN_VGA2GAIN_28_PREG,Receive data path equalization LUT VGA2 peaking control entry 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 0.--5. "DATGAIN_VGA1GAIN_28_PREG,Receive data path equalization LUT VGA1 peaking control entry 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "DEQ_GLUT31__DEQ_GLUT30_j,Receive data path equalization LUT gain. entry 30 register"
bitfld.long 0x3C 22.--27. "DATGAIN_VGA2GAIN_31_PREG,Receive data path equalization LUT VGA2 peaking control entry 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x3C 16.--21. "DATGAIN_VGA1GAIN_31_PREG,Receive data path equalization LUT VGA1 peaking control entry 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x3C 6.--11. "DATGAIN_VGA2GAIN_30_PREG,Receive data path equalization LUT VGA2 peaking control entry 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x3C 0.--5. "DATGAIN_VGA1GAIN_30_PREG,Receive data path equalization LUT VGA1 peaking control entry 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x40 "DEQ_ALUT1__DEQ_ALUT0_j,Receive data path equalization LUT attenuation. entry 0 register"
bitfld.long 0x40 22.--27. "DATGAIN_VGA2ATTEN_1_PREG,Receive data path equalization LUT VGA2 attenuation control entry 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x40 16.--21. "DATGAIN_VGA1ATTEN_1_PREG,Receive data path equalization LUT VGA1 attenuation control entry 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x40 6.--11. "DATGAIN_VGA2ATTEN_0_PREG,Receive data path equalization LUT VGA2 attenuation control entry 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x40 0.--5. "DATGAIN_VGA1ATTEN_0_PREG,Receive data path equalization LUT VGA1 attenuation control entry 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DEQ_ALUT3__DEQ_ALUT2_j,Receive data path equalization LUT attenuation. entry 2 register"
bitfld.long 0x44 22.--27. "DATGAIN_VGA2ATTEN_3_PREG,Receive data path equalization LUT VGA2 attenuation control entry 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x44 16.--21. "DATGAIN_VGA1ATTEN_3_PREG,Receive data path equalization LUT VGA1 attenuation control entry 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x44 6.--11. "DATGAIN_VGA2ATTEN_2_PREG,Receive data path equalization LUT VGA2 attenuation control entry 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x44 0.--5. "DATGAIN_VGA1ATTEN_2_PREG,Receive data path equalization LUT VGA1 attenuation control entry 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x48 "DEQ_ALUT5__DEQ_ALUT4_j,Receive data path equalization LUT attenuation. entry 4 register"
bitfld.long 0x48 22.--27. "DATGAIN_VGA2ATTEN_5_PREG,Receive data path equalization LUT VGA2 attenuation control entry 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x48 16.--21. "DATGAIN_VGA1ATTEN_5_PREG,Receive data path equalization LUT VGA1 attenuation control entry 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x48 6.--11. "DATGAIN_VGA2ATTEN_4_PREG,Receive data path equalization LUT VGA2 attenuation control entry 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x48 0.--5. "DATGAIN_VGA1ATTEN_4_PREG,Receive data path equalization LUT VGA1 attenuation control entry 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4C "DEQ_ALUT7__DEQ_ALUT6_j,Receive data path equalization LUT attenuation. entry 6 register"
bitfld.long 0x4C 22.--27. "DATGAIN_VGA2ATTEN_7_PREG,Receive data path equalization LUT VGA2 attenuation control entry 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x4C 16.--21. "DATGAIN_VGA1ATTEN_7_PREG,Receive data path equalization LUT VGA1 attenuation control entry 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x4C 6.--11. "DATGAIN_VGA2ATTEN_6_PREG,Receive data path equalization LUT VGA2 attenuation control entry 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x4C 0.--5. "DATGAIN_VGA1ATTEN_6_PREG,Receive data path equalization LUT VGA1 attenuation control entry 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x50 "DEQ_ALUT9__DEQ_ALUT8_j,Receive data path equalization LUT attenuation. entry 8 register"
bitfld.long 0x50 22.--27. "DATGAIN_VGA2ATTEN_9_PREG,Receive data path equalization LUT VGA2 attenuation control entry 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x50 16.--21. "DATGAIN_VGA1ATTEN_9_PREG,Receive data path equalization LUT VGA1 attenuation control entry 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x50 6.--11. "DATGAIN_VGA2ATTEN_8_PREG,Receive data path equalization LUT VGA2 attenuation control entry 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x50 0.--5. "DATGAIN_VGA1ATTEN_8_PREG,Receive data path equalization LUT VGA1 attenuation control entry 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x54 "DEQ_ALUT11__DEQ_ALUT10_j,Receive data path equalization LUT attenuation. entry 10 register"
bitfld.long 0x54 22.--27. "DATGAIN_VGA2ATTEN_11_PREG,Receive data path equalization LUT VGA2 attenuation control entry 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x54 16.--21. "DATGAIN_VGA1ATTEN_11_PREG,Receive data path equalization LUT VGA1 attenuation control entry 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x54 6.--11. "DATGAIN_VGA2ATTEN_10_PREG,Receive data path equalization LUT VGA2 attenuation control entry 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x54 0.--5. "DATGAIN_VGA1ATTEN_10_PREG,Receive data path equalization LUT VGA1 attenuation control entry 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x58 "DEQ_ALUT13__DEQ_ALUT12_j,Receive data path equalization LUT attenuation. entry 12 register"
bitfld.long 0x58 22.--27. "DATGAIN_VGA2ATTEN_13_PREG,Receive data path equalization LUT VGA2 attenuation control entry 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x58 16.--21. "DATGAIN_VGA1ATTEN_13_PREG,Receive data path equalization LUT VGA1 attenuation control entry 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x58 6.--11. "DATGAIN_VGA2ATTEN_12_PREG,Receive data path equalization LUT VGA2 attenuation control entry 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x58 0.--5. "DATGAIN_VGA1ATTEN_12_PREG,Receive data path equalization LUT VGA1 attenuation control entry 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x5C "DEQ_ALUT15__DEQ_ALUT14_j,Receive data path equalization LUT attenuation. entry 14 register"
bitfld.long 0x5C 22.--27. "DATGAIN_VGA2ATTEN_15_PREG,Receive data path equalization LUT VGA2 attenuation control entry 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x5C 16.--21. "DATGAIN_VGA1ATTEN_15_PREG,Receive data path equalization LUT VGA1 attenuation control entry 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x5C 6.--11. "DATGAIN_VGA2ATTEN_14_PREG,Receive data path equalization LUT VGA2 attenuation control entry 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x5C 0.--5. "DATGAIN_VGA1ATTEN_14_PREG,Receive data path equalization LUT VGA1 attenuation control entry 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "DEQ_ALUT17__DEQ_ALUT16_j,Receive data path equalization LUT attenuation. entry 16 register"
bitfld.long 0x60 22.--27. "DATGAIN_VGA2ATTEN_17_PREG,Receive data path equalization LUT VGA2 attenuation control entry 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x60 16.--21. "DATGAIN_VGA1ATTEN_17_PREG,Receive data path equalization LUT VGA1 attenuation control entry 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x60 6.--11. "DATGAIN_VGA2ATTEN_16_PREG,Receive data path equalization LUT VGA2 attenuation control entry 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x60 0.--5. "DATGAIN_VGA1ATTEN_16_PREG,Receive data path equalization LUT VGA1 attenuation control entry 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x64 "DEQ_ALUT19__DEQ_ALUT18_j,Receive data path equalization LUT attenuation. entry 18 register"
bitfld.long 0x64 22.--27. "DATGAIN_VGA2ATTEN_19_PREG,Receive data path equalization LUT VGA2 attenuation control entry 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x64 16.--21. "DATGAIN_VGA1ATTEN_19_PREG,Receive data path equalization LUT VGA1 attenuation control entry 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x64 6.--11. "DATGAIN_VGA2ATTEN_18_PREG,Receive data path equalization LUT VGA2 attenuation control entry 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x64 0.--5. "DATGAIN_VGA1ATTEN_18_PREG,Receive data path equalization LUT VGA1 attenuation control entry 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x68 "DEQ_ALUT21__DEQ_ALUT20_j,Receive data path equalization LUT attenuation. entry 20 register"
bitfld.long 0x68 22.--27. "DATGAIN_VGA2ATTEN_21_PREG,Receive data path equalization LUT VGA2 attenuation control entry 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x68 16.--21. "DATGAIN_VGA1ATTEN_21_PREG,Receive data path equalization LUT VGA1 attenuation control entry 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x68 6.--11. "DATGAIN_VGA2ATTEN_20_PREG,Receive data path equalization LUT VGA2 attenuation control entry 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x68 0.--5. "DATGAIN_VGA1ATTEN_20_PREG,Receive data path equalization LUT VGA1 attenuation control entry 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x6C "DEQ_ALUT23__DEQ_ALUT22_j,Receive data path equalization LUT attenuation. entry 22 register"
bitfld.long 0x6C 22.--27. "DATGAIN_VGA2ATTEN_23_PREG,Receive data path equalization LUT VGA2 attenuation control entry 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x6C 16.--21. "DATGAIN_VGA1ATTEN_23_PREG,Receive data path equalization LUT VGA1 attenuation control entry 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x6C 6.--11. "DATGAIN_VGA2ATTEN_22_PREG,Receive data path equalization LUT VGA2 attenuation control entry 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x6C 0.--5. "DATGAIN_VGA1ATTEN_22_PREG,Receive data path equalization LUT VGA1 attenuation control entry 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x70 "DEQ_ALUT25__DEQ_ALUT24_j,Receive data path equalization LUT attenuation. entry 24 register"
bitfld.long 0x70 22.--27. "DATGAIN_VGA2ATTEN_25_PREG,Receive data path equalization LUT VGA2 attenuation control entry 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x70 16.--21. "DATGAIN_VGA1ATTEN_25_PREG,Receive data path equalization LUT VGA1 attenuation control entry 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x70 6.--11. "DATGAIN_VGA2ATTEN_24_PREG,Receive data path equalization LUT VGA2 attenuation control entry 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x70 0.--5. "DATGAIN_VGA1ATTEN_24_PREG,Receive data path equalization LUT VGA1 attenuation control entry 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x74 "DEQ_ALUT27__DEQ_ALUT26_j,Receive data path equalization LUT attenuation. entry 26 register"
bitfld.long 0x74 22.--27. "DATGAIN_VGA2ATTEN_27_PREG,Receive data path equalization LUT VGA2 attenuation control entry 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x74 16.--21. "DATGAIN_VGA1ATTEN_27_PREG,Receive data path equalization LUT VGA1 attenuation control entry 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x74 6.--11. "DATGAIN_VGA2ATTEN_26_PREG,Receive data path equalization LUT VGA2 attenuation control entry 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x74 0.--5. "DATGAIN_VGA1ATTEN_26_PREG,Receive data path equalization LUT VGA1 attenuation control entry 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DEQ_ALUT29__DEQ_ALUT28_j,Receive data path equalization LUT attenuation. entry 28 register"
bitfld.long 0x78 22.--27. "DATGAIN_VGA2ATTEN_29_PREG,Receive data path equalization LUT VGA2 attenuation control entry 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x78 16.--21. "DATGAIN_VGA1ATTEN_29_PREG,Receive data path equalization LUT VGA1 attenuation control entry 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x78 6.--11. "DATGAIN_VGA2ATTEN_28_PREG,Receive data path equalization LUT VGA2 attenuation control entry 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x78 0.--5. "DATGAIN_VGA1ATTEN_28_PREG,Receive data path equalization LUT VGA1 attenuation control entry 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x7C "DEQ_ALUT31__DEQ_ALUT30_j,Receive data path equalization LUT attenuation. entry 30 register"
bitfld.long 0x7C 22.--27. "DATGAIN_VGA2ATTEN_31_PREG,Receive data path equalization LUT VGA2 attenuation control entry 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x7C 16.--21. "DATGAIN_VGA1ATTEN_31_PREG,Receive data path equalization LUT VGA1 attenuation control entry 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x7C 6.--11. "DATGAIN_VGA2ATTEN_30_PREG,Receive data path equalization LUT VGA2 attenuation control entry 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x7C 0.--5. "DATGAIN_VGA1ATTEN_30_PREG,Receive data path equalization LUT VGA1 attenuation control entry 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DEQ_DFETAP0__DEQ_DFETAP_CTRL_PREG_j,Receive data path DFE tap control register"
bitfld.long 0x80 20.--23. "DATDFE_TAP0_THRESH_MNT_PREG,Receive data path DFE tap 0 accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x80 16.--19. "DATDFE_TAP0_THRESH_ACQ_PREG,Receive data path DFE tap 0 accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x80 8.--9. "SUM_TAP4STEPSIZE_PREG,Receive data path DFE tap 4 feedback current trim" "0,1,2,3"
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bitfld.long 0x80 6.--7. "SUM_TAP3STEPSIZE_PREG,Receive data path DFE tap 3 feedback current trim" "0,1,2,3"
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bitfld.long 0x80 4.--5. "SUM_TAP2STEPSIZE_PREG,Receive data path DFE tap 2 feedback current trim" "0,1,2,3"
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bitfld.long 0x80 2.--3. "SUM_TAP1STEPSIZE_PREG,Receive data path DFE tap 1 feedback current trim" "0,1,2,3"
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bitfld.long 0x80 0.--1. "SUM_TAP0STEPSIZE_PREG,Receive data path DFE tap 0 feedback current trim" "0,1,2,3"
line.long 0x84 "DEQ_DFETAP1__DEQ_DFETAP0_OVR_j,Receive data path DFE tap 0 override register"
bitfld.long 0x84 20.--23. "DATDFE_TAP1_THRESH_MNT_PREG,Receive data path DFE tap 1 accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x84 16.--19. "DATDFE_TAP1_THRESH_ACQ_PREG,Receive data path DFE tap 1 accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x84 8. "DATDFE_TAP0_OVREN_PREG,Receive data path DFE tap 0 weight active high override enable" "0,1"
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hexmask.long.byte 0x84 0.--7. 1. "DATDFE_TAP0_OVR_PREG,When datdfe_tap0_ovren_preg is asserted high this value overrides the tap 0 weight"
line.long 0x88 "DEQ_DFETAP2__DEQ_DFETAP1_OVR_j,Receive data path DFE tap 1 override register"
bitfld.long 0x88 20.--23. "DATDFE_TAP2_THRESH_MNT_PREG,Receive data path DFE tap 2 accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x88 16.--19. "DATDFE_TAP2_THRESH_ACQ_PREG,Receive data path DFE tap 2 accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x88 8. "DATDFE_TAP1_OVREN_PREG,Receive data path DFE tap 1 weight active high override enable" "0,1"
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hexmask.long.byte 0x88 0.--7. 1. "DATDFE_TAP1_OVR_PREG,When datdfe_tap1_ovren_preg is asserted high this value overrides the tap 1 weight"
line.long 0x8C "DEQ_DFETAP3__DEQ_DFETAP2_OVR_j,Receive data path DFE tap 2 override register"
bitfld.long 0x8C 20.--23. "DATDFE_TAP3_THRESH_MNT_PREG,Receive data path DFE tap 3 accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x8C 16.--19. "DATDFE_TAP3_THRESH_ACQ_PREG,Receive data path DFE tap 3 accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x8C 8. "DATDFE_TAP2_OVREN_PREG,Receive data path DFE tap 2 weight active high override enable" "0,1"
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hexmask.long.byte 0x8C 0.--7. 1. "DATDFE_TAP2_OVR_PREG,When datdfe_tap2_ovren_preg is asserted high this value overrides the tap 2 weight"
line.long 0x90 "DEQ_DFETAP4_PREG__DEQ_DFETAP3_OVR_j,Receive data path DFE tap 3 override register"
bitfld.long 0x90 20.--23. "DATDFE_TAP4_THRESH_MNT_PREG,Receive data path DFE tap 4 accumulator threshold for maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x90 16.--19. "DATDFE_TAP4_THRESH_ACQ_PREG,Receive data path DFE tap 4 accumulator threshold for acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x90 8. "DATDFE_TAP3_OVREN_PREG,Receive data path DFE tap 3 weight active high override enable" "0,1"
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hexmask.long.byte 0x90 0.--7. 1. "DATDFE_TAP3_OVR_PREG,When datdfe_tap3_ovren_preg is asserted high this value overrides the tap 3 weight"
line.long 0x94 "DATDFE_TAPCAP_THRESH_PREG__DEQ_DFETAP4_OVR_j,Receive data path DFE tap 4 override register"
hexmask.long.word 0x94 16.--27. 1. "DATDFE_TAPCAP_THRESH_PREG,Threshold for capping the sum of the receive data path DFE tap magnitudes"
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bitfld.long 0x94 8. "DATDFE_TAP4_OVREN_PREG,Receive data path DFE tap 4 weight active high override enable" "0,1"
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hexmask.long.byte 0x94 0.--7. 1. "DATDFE_TAP4_OVR_PREG,When datdfe_tap4_ovren_preg is asserted high this value overrides the tap 4 weight"
line.long 0x98 "DFE_TRAINING_MASK_PREG__DFE_EN_1010_IGNORE_PREG_j,DFE_TRAINING_MASK_PREG__DFE_EN_1010_IGNORE_PREG Offset = 4268h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x98 25. "DFE_TAU_TRAINING_MASK_PREG,When set to 1'b0 the tau training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 24. "DFE_DATGAIN_TRAINING_MASK_PREG,When set to 1'b0 the data path gain training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 23. "DFE_DATOFF_TRAINING_MASK_PREG,When set to 1'b0 the data path offset training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 22. "DFE_DATDFE4_TRAINING_MASK_PREG,When set to 1'b0 the DFE tap 4 training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 21. "DFE_DATDFE3_TRAINING_MASK_PREG,When set to 1'b0 the DFE tap 3 training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 20. "DFE_DATDFE2_TRAINING_MASK_PREG,When set to 1'b0 the DFE tap 2 training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 19. "DFE_DATDFE1_TRAINING_MASK_PREG,When set to 1'b0 the DFE tap 1 training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 18. "DFE_DATDFE0_TRAINING_MASK_PREG,When set to 1'b0 the DFE tap 0 training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 17. "DFE_PRECUR_TRAINING_MASK_PREG,When set to 1'b0 the far-end transmit pre cursor training will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 16. "DFE_FALSEEYE_TRAINING_MASK_PREG,When set to 1'b0 false eye detection will be paused during rx_eq_training_data_valid deassertion and during detection of 1010 pattern occurs with dfe_en_1010_ignore_modeX_preg is asserted" "0,1"
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bitfld.long 0x98 12. "DFE_EN_1010_IGNORE_MODE3_PREG,Active high enable for the DFE ignore 1010 function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1"
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bitfld.long 0x98 8. "DFE_EN_1010_IGNORE_MODE2_PREG,Active high enable for the DFE ignore 1010 function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1"
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bitfld.long 0x98 4. "DFE_EN_1010_IGNORE_MODE1_PREG,Active high enable for the DFE ignore 1010 function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1"
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bitfld.long 0x98 0. "DFE_EN_1010_IGNORE_MODE0_PREG,Active high enable for the DFE ignore 1010 function when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1"
line.long 0x9C "DFE_EN_1010_IGNORE_DIAG_PREG_j,DFE_EN_1010_IGNORE_DIAG_PREG Offset = 426Ch + (j * 400h); where j = 0h to 1h"
hexmask.long.byte 0x9C 1.--7. 1. "DFE_1010_DIAGCNTR_VAL,Indicates how many 1010"
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bitfld.long 0x9C 0. "DFE_1010_DIAGCNTR_EN_PREG,Level sensitive diagnostic bit: When de-asserted counter will be cleared and will not advance" "0,1"
line.long 0xA0 "DEQ_PRECUR_PREG_j,Receive data path far-end transmit precursor equalization control register"
bitfld.long 0xA0 0.--3. "PRECUR_THRESH_PREG,Receive data path far-end transmit precursor equalization accumulator threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4280++0x07
line.long 0x00 "DEQ_POSTCUR_INCR_PREG__DEQ_POSTCUR_PREG_j,Receive data path far-end transmit postcursor equalization control register"
bitfld.long 0x00 31. "POSTCUR_INCR_TAP0SGN_PREG,Receive data path far-end transmit postcursor equalization increment request tap 0 threshold sign" "0,1"
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hexmask.long.byte 0x00 24.--30. 1. "POSTCUR_INCR_TAP0MAG_PREG,Receive data path far-end transmit postcursor equalization increment request tap 0 threshold unsigned binary encoded magnitude"
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bitfld.long 0x00 23. "POSTCUR_INCR_TAP1SGN_PREG,Receive data path far-end transmit postcursor equalization increment request tap 1 threshold sign" "0,1"
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hexmask.long.byte 0x00 16.--22. 1. "POSTCUR_INCR_TAP1MAG_PREG,Receive data path far-end transmit postcursor equalization increment request tap 1 threshold unsigned binary encoded magnitude"
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bitfld.long 0x00 5.--9. "POSTCUR_INCR_GAIN_PREG,Receive data path far-end transmit postcursor equalization increment request gain threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "POSTCUR_DECR_GAIN_PREG,Receive data path far-end transmit postcursor equalization decrement request gain threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DEQ_POSTCUR_DECR_PREG_j,Receive data path far-end transmit postcursor equalization decrement control register"
bitfld.long 0x04 15. "POSTCUR_DECR_TAP0SGN_PREG,Receive data path far-end transmit postcursor equalization decrement request tap 0 threshold sign" "0,1"
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hexmask.long.byte 0x04 8.--14. 1. "POSTCUR_DECR_TAP0MAG_PREG,Receive data path far-end transmit postcursor equalization decrement request tap 0 threshold unsigned binary encoded magnitude"
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bitfld.long 0x04 7. "POSTCUR_DECR_TAP1SGN_PREG,Receive data path far-end transmit postcursor equalization decrement request tap 1 threshold sign" "0,1"
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hexmask.long.byte 0x04 0.--6. 1. "POSTCUR_DECR_TAP1MAG_PREG,Receive data path far-end transmit postcursor equalization decrement request tap 1 threshold unsigned binary encoded magnitude"
group.long 0x4290++0x03
line.long 0x00 "DEQ_FALSEEYE_CTRL_PREG_j,Receive data path equalization (DEQ) false eye control register"
bitfld.long 0x00 8.--13. "FALSEEYE_KICKVAL_PREG,Receive data path equalization (DEQ) false eye detection phase kick amplitude" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "FALSEEYE_DISABLE_PREG,Receive data path equalization (DEQ) false eye detection active high disable" "0,1"
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bitfld.long 0x00 5.--6. "FALSEEYE_BW_PREG,Receive data path equalization (DEQ) false eye detection bandwidth selection" "0,1,2,3"
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bitfld.long 0x00 0.--4. "FALSEEYE_THRESH_PREG,Receive data path equalization (DEQ) false eye detection binary encoded threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x429C++0x0B
line.long 0x00 "DEQ_TAU_CTRL1_FAST_MAINT_PREG_j,Receive data path equalization (DEQ) fast maintenance tau training control register 1"
bitfld.long 0x00 30. "TAU_DISABLE_FAST_MAINT_PREG,Receive data path equalization (DEQ) fast maintenance tau algorithm active high disable" "0,1"
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bitfld.long 0x00 26.--29. "TAU_FAST_MAINT_TIME_PREG,Receive data path equalization (DEQ) fast maintenance tau algorithm accumulation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 16.--25. 1. "TAU_FAST_MAINT_THRESH_PREG,Receive data path equalization (DEQ) fast maintainance tau algorithm accumulation threshold"
line.long 0x04 "DEQ_TAU_CTRL2_PREG__DEQ_TAU_CTRL1_SLOW_MAINT_PREG_j,Receive data path equalization (DEQ) slow maintenance tau training control register 1"
bitfld.long 0x04 24.--29. "TAU_DELTAMAX_PREG,Receive data path equalization (DEQ) tau algorithm maximum delta from EPI to DPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "TAU_DELTAMIN_PREG,Receive data path equalization (DEQ) tau algorithm minimum delta from EPI to DPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 14. "TAU_DISABLE_SLOW_MAINT_PREG,Receive data path equalization (DEQ) slow maintenance tau algorithm active high disable" "0,1"
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bitfld.long 0x04 10.--13. "TAU_SLOW_MAINT_TIME_PREG,Receive data path equalization (DEQ) slow maintenance tau algorithm accumulation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x04 0.--9. 1. "TAU_SLOW_MAINT_THRESH_PREG,Receive data path equalization (DEQ) slow maintenance tau algorithm accumulation threshold"
line.long 0x08 "DEQ_BLK_TAU_DELTA_PREG__DEQ_TAU_CTRL3_PREG_j,DEQ_BLK_TAU_DELTA_PREG__DEQ_TAU_CTRL3_PREG Offset = 42A4h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x08 24.--29. "BLK_TAU_DELTAMAX_PREG,Receive data path equalization (DEQ) tau algorithm's maximum delta from EPI to DPI used for block TAU acquisition and apparent center" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 16.--21. "BLK_TAU_DELTAMIN_PREG,Receive data path equalization (DEQ) tau algorithm's minimum delta from EPI to DPI used for block TAU acquisition and apparent center" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 14.--15. "TAU_MODE_PREG,TAU mode register" "0,1,2,3"
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bitfld.long 0x08 8. "MV_DPI_ACCUM_EQ_PREG,Move DPI to the left if (r_accum_a is equal to r_accum_b) and (r_delta is less than equal to tau_deltamin_preg) if this bit is set to 1'b1 else don't move DPI" "0,1"
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bitfld.long 0x08 4.--7. "CONCURRENT_EPIOFFSET_PREG,Receive data path equalization (DEQ) tau algorithm 4 bit signed offset for EPI used in concurrent eyesurf and rx margining" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "TAU_EPIOFFSET_PREG,Receive data path equalization (DEQ) tau algorithm 4 bit signed offset for EPI used tau opertions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x42B0++0x03
line.long 0x00 "DEQ_OPENEYE_CTRL_PREG_j,Receive data path equalization (DEQ) open eye algorithms control register"
bitfld.long 0x00 14. "OPENEYE_DATABLANKEN_PREG,Receive data path equalization (DEQ) open eye data blank active high enable" "0,1"
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bitfld.long 0x00 13. "OPENEYE_DISABLE_PREG,Receive data path equalization (DEQ) open eye tau algorithm active high disable" "0,1"
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bitfld.long 0x00 11.--12. "OPENEYE_TAU_SARCNTSEL_PREG,Receive data path equalization (DEQ) open eye tau algorithm SAR count selection" "0,1,2,3"
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bitfld.long 0x00 9.--10. "OPENEYE_TAU_PICNTSEL_PREG,Receive data path equalization (DEQ) open eye tau algorithm PI step count selection" "0,1,2,3"
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bitfld.long 0x00 3.--8. "OPENEYE_GAIN_ITERCNT_PREG,Open eye gain iteration count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--2. "OPENEYE_GAIN_TIME_PREG,Open eye gain accumulation time" "0,1,2,3,4,5,6,7"
group.long 0x42C0++0x03
line.long 0x00 "DEQ_PICTRL_PREG__DEQ_PI_OVR_CTRL_PREG_j,Receive data path equalization (DEQ) PI override register"
bitfld.long 0x00 21. "PICTRL_HIRES_PREG,DPI and EPI high resolution enable" "0,1"
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bitfld.long 0x00 19.--20. "PICTRL_STEPSIZE_PREG,DPI and EPI step size selection" "0,1,2,3"
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bitfld.long 0x00 16.--18. "PICTRL_SETTLE_PREG,DPI and EPI control settling time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "EPI_OVREN_PREG,EPI phase active high override enable" "0,1"
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hexmask.long.byte 0x00 8.--14. 1. "EPI_OVR_PREG,When epi_ovren_preg is asserted high this value will override the data path EPI binary phase"
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bitfld.long 0x00 7. "DPI_OVREN_PREG,DPI phase active high override enable" "0,1"
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hexmask.long.byte 0x00 0.--6. 1. "DPI_OVR_PREG,When dpi_ovren_preg is asserted high this value will override the data path DPI binary phase"
group.long 0x42D0++0x23
line.long 0x00 "CPICAL_CAP_STARTCODE_MODE23_PREG__CPICAL_CTRL_PREG_j,CPI calibration control and status register"
hexmask.long.byte 0x00 24.--30. 1. "CPICAL_CAP_STARTCODE_MODE3_PREG,This value is used as the starting code for subsequent CPI calibrations (capacitor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011"
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hexmask.long.byte 0x00 16.--22. 1. "CPICAL_CAP_STARTCODE_MODE2_PREG,This value is used as the starting code for subsequent CPI calibrations(capacitor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010"
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bitfld.long 0x00 15. "CPICAL_RUN_PREG,CPI calibration manual initiation active high enable" "0,1"
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bitfld.long 0x00 11. "CPICAL_CLKBUFEN_OVREN_PREG,overide enable for cpi cal clock buf enable" "0,1"
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bitfld.long 0x00 10. "CPICAL_CLKBUFEN_OVRVAL_PREG,overide value for cpi cal clock buf enable" "0,1"
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bitfld.long 0x00 8. "CPICAL_CALEN_FORCE_PREG,CPI analog module calen force" "0,1"
line.long 0x04 "CPICAL_CAP_OVR_PREG__CPICAL_CAP_STARTCODE_MODE01_PREG_j,CPI calibration (capacitor) starting code register for xcvr_standard_mode 0 and 1"
bitfld.long 0x04 31. "CPICAL_CAP_OVREN_PREG,CPI calibration (capacitor) override active high enable" "0,1"
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hexmask.long.byte 0x04 16.--22. 1. "CPICAL_CAP_OVRVAL_PREG,When cpical_cap_ovren_preg is asserted high this value is used by the CPI rather than the calibration engine result"
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hexmask.long.byte 0x04 8.--14. 1. "CPICAL_CAP_STARTCODE_MODE1_PREG,This value is used as the starting code for subsequent CPI calibrations(capacitor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b001"
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hexmask.long.byte 0x04 0.--6. 1. "CPICAL_CAP_STARTCODE_MODE0_PREG,This value is used as the starting code for subsequent CPI calibrations(capacitor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000"
line.long 0x08 "CPICAL_CAP_ITERTMR_PREG__CPICAL_CAP_INITTMR_PREG_j,CPI calibration(capacitor) initial delay register"
hexmask.long.word 0x08 16.--27. 1. "CPICAL_CAP_ITERTMR_PREG,CPI calibration(capacitor) iteration wait timer to allow the analog circuits to settle to the new frequency after a calibration code change"
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hexmask.long.word 0x08 0.--11. 1. "CPICAL_CAP_INITTMR_PREG,CPI calibration(capacitor) initial wait timer to allow the analog circuits to settle on initiation of the calibration sequence"
line.long 0x0C "CPICAL_TMRVAL_MODE2_PREG__CPICAL_TMRVAL_MODE3_PREG_j,CPI calibration mode3 evaluation time register Offset = 42DCh + (j * 400h); where j = 0h to 1h"
hexmask.long.word 0x0C 16.--28. 1. "CPICAL_TMRVAL_MODE2_PREG,This value sets the Lane Standards Decoder frequency evaluation time"
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hexmask.long.word 0x0C 0.--12. 1. "CPICAL_TMRVAL_MODE3_PREG,This value sets the Lane Standards Decoder frequency evaluation time"
line.long 0x10 "CPICAL_TMRVAL_MODE0_PREG__CPICAL_TMRVAL_MODE1_PREG_j,CPI calibration mode1 evaluation time register Offset = 42E0h + (j * 400h); where j = 0h to 1h"
hexmask.long.word 0x10 16.--28. 1. "CPICAL_TMRVAL_MODE0_PREG,This value sets the Lane Standards Decoder frequency evaluation time"
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hexmask.long.word 0x10 0.--12. 1. "CPICAL_TMRVAL_MODE1_PREG,This value sets the Lane Standards Decoder frequency evaluation time"
line.long 0x14 "CPICAL_PICNT_MODE2_PREG__CPICAL_PICNT_MODE3_PREG_j,CPI calibration PI clock cnt. mode 3 register"
hexmask.long.word 0x14 16.--27. 1. "CPICAL_PICNT_MODE2_PREG,This value sets the Lane Standards Decoder PI clock counter expected value when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010"
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hexmask.long.word 0x14 0.--11. 1. "CPICAL_PICNT_MODE3_PREG,This value sets the Lane Standards Decoder PI clock counter expected value when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011"
line.long 0x18 "CPICAL_PICNT_MODE0_PREG__CPICAL_PICNT_MODE1_PREG_j,CPI calibration PI clock cnt. mode 1 register"
hexmask.long.word 0x18 16.--27. 1. "CPICAL_PICNT_MODE0_PREG,This value sets the Lane Standards Decoder PI clock counter expected value when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000"
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hexmask.long.word 0x18 0.--11. 1. "CPICAL_PICNT_MODE1_PREG,This value sets the Lane Standards Decoder PI clock counter expected value when xcvr_standard_mode_ln{15:0}[2:0] is 3'b001"
line.long 0x1C "CPICAL_STATUS_PREG_j,Fine PI calibration control and status register Offset = 42ECh + (j * 400h); where j = 0h to 1h"
hexmask.long.byte 0x1C 24.--31. 1. "CPICAL_RES_CODE,CPI calibration resistor code"
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hexmask.long.byte 0x1C 17.--23. 1. "CPICAL_CAP_CODE,CPI calibration capacitor code"
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bitfld.long 0x1C 16. "CPICAL_DONE,CPI calibration active high complete flag" "0,1"
line.long 0x20 "CPICAL_OFFSET_PREG_j,CPI calibration offset register(resistor and capacitor) Offset = 42F0h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x20 11.--15. "CPICAL_RES_OFFSET_PREG,Twos compliment offset to be added to the calibrated course code sent to the CPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 5. "CPICAL_CAP_OFFSET_WR_TOGGLE_PREG,Cal (cap)Offset write toggle bit" "0,1"
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bitfld.long 0x20 0.--4. "CPICAL_CAP_OFFSET_PREG,Twos compliment offset to be added to the calibrated course code sent to the CPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x42F8++0x23
line.long 0x00 "CPI_OUTBUF_RATESEL_PREG_j,CPI output buffers BW control Offset = 42F8h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x00 6.--7. "CPI_OUTBUF_RATESEL_MODE3_PREG,CPI output buffers BW control when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011" "0,1,2,3"
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bitfld.long 0x00 4.--5. "CPI_OUTBUF_RATESEL_MODE2_PREG,CPI output buffers BW control when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010" "0,1,2,3"
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bitfld.long 0x00 2.--3. "CPI_OUTBUF_RATESEL_MODE1_PREG,CPI output buffers BW control when xcvr_standard_mode_ln{15:0}[2:0] is 3'b001" "0,1,2,3"
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bitfld.long 0x00 0.--1. "CPI_OUTBUF_RATESEL_MODE0_PREG,CPI output buffers BW control when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000" "0,1,2,3"
line.long 0x04 "CPI_TRIM_PREG__CPI_RESBIAS_BIN_PREG_j,CPI res bias Offset = 42FCh + (j * 400h); where j = 0h to 1h"
bitfld.long 0x04 19.--21. "CPI_IDIVTRIM_PREG,bias current magnitude controll" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 16.--18. "CPI_IPTATTRIM_PREG,ptat percentage control" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 9.--11. "CPI_RESBIAS_BIN_MODE3_PREG,CPI res bias when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 6.--8. "CPI_RESBIAS_BIN_MODE2_PREG,CPI res bias when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 3.--5. "CPI_RESBIAS_BIN_MODE1_PREG,CPI res bias when xcvr_standard_mode_ln{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--2. "CPI_RESBIAS_BIN_MODE0_PREG,CPI res bias when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
line.long 0x08 "CPI_R2DEC_OVR_PREG__CPI_R1DEC_OVR_PREG_j,CPI_R2DEC_OVR_PREG__CPI_R1DEC_OVR_PREG Offset = 4300h + (j * 400h); where j = 0h to 1h"
hexmask.long.word 0x08 16.--27. 1. "CPICAL_R2DEC_OVR_VAL_PREG,Overide value for cpi cal resistor decoder 2 output"
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bitfld.long 0x08 15. "CPICAL_RDEC_OVR_EN_PREG,Overide enable for cpi cal resistor decoder 1 /2 (r1dec and r2dec) outputs" "0,1"
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hexmask.long.word 0x08 0.--11. 1. "CPICAL_R1DEC_OVR_VAL_PREG,Overide value for cpi cal resistor decoder 1 output"
line.long 0x0C "CPICAL_RES_STARTCODE_MODE23_PREG__CPICAL_INCR_DECR_PREG_j,CPICAL_RES_STARTCODE_MODE23_PREG__CPICAL_INCR_DECR_PREG Offset = 4304h + (j * 400h); where j = 0h to 1h"
hexmask.long.byte 0x0C 24.--31. 1. "CPICAL_RES_STARTCODE_MODE3_PREG,This value is used as the starting code for subsequent CPI calibrations (resistor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b011"
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hexmask.long.byte 0x0C 16.--23. 1. "CPICAL_RES_STARTCODE_MODE2_PREG,This value is used as the starting code for subsequent CPI calibrations(resistor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b010"
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bitfld.long 0x0C 12.--15. "CPICAL_RES_INCR_PREG,CPI calibration Resistor code steps up by this value while incrementing the code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. "CPICAL_RES_DECR_PREG,CPI calibration Resistor code steps down by this value while decrementing the code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "CPICAL_CAP_DECR_PREG,CPI calibration Capacitor code steps down by this value while decrementing the code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CPICAL_RES_INITTMR_PREG__CPICAL_RES_STARTCODE_MODE01_PREG_j,CPI calibration (resisitor) starting code register for xcvr_standard_mode 0 and 1"
hexmask.long.word 0x10 16.--27. 1. "CPICAL_RES_INITTMR_PREG,CPI calibration(resistor) initial wait timer to allow the analog circuits to settle on initiation of the calibration sequence"
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hexmask.long.byte 0x10 8.--15. 1. "CPICAL_RES_STARTCODE_MODE1_PREG,This value is used as the starting code for subsequent CPI calibrations (resistor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b0001"
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hexmask.long.byte 0x10 0.--7. 1. "CPICAL_RES_STARTCODE_MODE0_PREG,This value is used as the starting code for subsequent CPI calibrations(resistor) when xcvr_standard_mode_ln{15:0}[2:0] is 3'b000"
line.long 0x14 "EPI_CTRL_PREG__CPICAL_RES_ITERTMR_PREG_j,CPI calibration(resisitor)iteration delay register"
bitfld.long 0x14 17. "EPIDEC_EN_OVR_PREG,EPI IDDQ style PSC enable override" "0,1"
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bitfld.long 0x14 16. "EPATHPWRISO_EN_PREG,EPI power island manual active high enable" "0,1"
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hexmask.long.word 0x14 0.--11. 1. "CPICAL_RES_ITERTMR_PREG,CPI calibration(resistor) iteration wait timer to allow the analog circuits to settle to the new frequency after a calibration code change"
line.long 0x18 "LFPSFILT_MD_PREG__LFPSDET_SUPPORT_PREG_j,LFPS Detector Support Register Offset = 4310h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x18 16.--20. "LFPSFILT_MD_COUNT_PREG,Minimum pulse distance counter value (MD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 12. "LFPSFILT_DISABLE_PULSE_NONE_MD_CHK_PREG,When asserted the MD check using pulse_none is disabled" "0,1"
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bitfld.long 0x18 9. "LFPSDET_OVREN_PREG,LFPS detect active high analog override enable" "0,1"
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bitfld.long 0x18 8. "LFPSDET_OVRVAL_PREG,When lfpsdet_ovren_preg is asserted high this value drives the filter rather than the analog circuit result" "0,1"
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bitfld.long 0x18 0.--2. "LFPSDET_VTHRESH_PREG,Voltage threshold control" "0,1,2,3,4,5,6,7"
line.long 0x1C "LFPSFILT_RD_PREG__LFPSFILT_NS_PREG_j,LFPS Detection Filter No Signal Counter Register Offset = 4314h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x1C 16.--20. "LFPSFILT_RD_COUNT_PREG,Ramp down counter value (RD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 0.--3. "LFPSFILT_NS_COUNT_PREG,No signal counter value (NS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "LFPSFILT_MP_PREG_j,LFPS Detection Filter Minimum Pulse Duration Counter Register Offset = 4318h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x20 0.--2. "LFPSFILT_MP_COUNT_PREG,Minimum pulse duration (MP)" "0,1,2,3,4,5,6,7"
group.long 0x4320++0x13
line.long 0x00 "SDFILT_H2L_A_PREG__SIGDET_SUPPORT_PREG_j,Receive signal detection support register"
bitfld.long 0x00 31. "SDFILT_H2LSEL_PREG,Receive signal detect high to low filter select value" "0,1"
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hexmask.long.byte 0x00 24.--30. 1. "SDFILT_H2L_DLY_TMR_PREG,Receive signal detect high to low filter delay timer value"
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hexmask.long.byte 0x00 16.--22. 1. "SDFILT_H2L_FILTER_TMR_PREG,Receive signal detect high to low filter timer value"
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bitfld.long 0x00 12.--14. "SIGDET_VTHRESH_PREG,Receive signal detection voltage threshold binary encoded selection" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "SIGDET_OVREN_PREG,Receive signal detect active high analog override enable" "0,1"
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bitfld.long 0x00 8. "SIGDET_OVRVAL_PREG,When sigdet_ovren_preg is asserted high this value drives the filter rather than the analog circuit result" "0,1"
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bitfld.long 0x00 4.--5. "SIGDET_STRESSPROT_PREG,Receive signal detection analog device protection binary encoded selection" "0,1,2,3"
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bitfld.long 0x00 0.--2. "SIGDET_BIASTRIM_PREG,Receive signal detection bias current binary encoded trim" "0,1,2,3,4,5,6,7"
line.long 0x04 "SDFILT_L2H_PREG__SDFILT_H2L_B_PREG_j,Receive signal detection high to low filter control register B"
bitfld.long 0x04 31. "SDFILT_L2HSEL_PREG,Receive signal detect low to high filter select value" "0,1"
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hexmask.long.byte 0x04 24.--30. 1. "SDFILT_L2H_MIN_TMR_PREG,Receive signal detect low to high filter minimum timer value"
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hexmask.long.byte 0x04 16.--22. 1. "SDFILT_L2H_FILTER_TMR_PREG,Receive signal detect low to high filter timer value"
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hexmask.long.byte 0x04 0.--6. 1. "SDFILT_H2L_MIN_TMR_PREG,Receive signal detect high to low filter minimum timer value"
line.long 0x08 "SDCAL_OVR_PREG__SDCAL_CTRL_PREG_j,Receive signal detection calibration control register"
bitfld.long 0x08 31. "SDCAL_OVREN_PREG,Receive signal detect code active high override enable" "0,1"
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bitfld.long 0x08 16.--20. "SDCAL_OVRVAL_PREG,When sdcal_ovren_preg is asserted high this value overrides the internally signal detection calibration code from the calibration circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15. "SDCAL_RUN_PREG,Receive signal detection calibration manual start signal" "0,1"
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rbitfld.long 0x08 14. "SDCAL_DONE,Receive signal detection calibration active high complete flag" "0,1"
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rbitfld.long 0x08 13. "SDCAL_NO_ANA_RESP,Receive sigdet detection calibration no analog response flag" "0,1"
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rbitfld.long 0x08 12. "SDCAL_VALID,Receive signal detection calibration has completed flag" "0,1"
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bitfld.long 0x08 8. "SDCAL_VALID_OVR_PREG,Receive signal detection calibration has completed override" "0,1"
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rbitfld.long 0x08 0.--4. "SDCAL_CODE,Receive signal detection calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "SDCAL_TUNE_PREG__SDCAL_START_PREG_j,Receive signal detection calibration starting code register"
bitfld.long 0x0C 16.--20. "SDCAL_TUNE_PREG,Receive signal detection mission mode amplitude threshold binary encoded selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. "SDCAL_START_PREG,Receive signal detect calibration start code when the calibration sequence begins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "SDCAL_ITER_PREG__SDCAL_INIT_PREG_j,Receive signal detection calibration initialization timer register"
hexmask.long.word 0x10 16.--24. 1. "SDCAL_ITER_WAIT_PREG,Receive signal detect calibration iteration wait timer providing delay for settling between each offset adjustment level change"
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hexmask.long.word 0x10 0.--8. 1. "SDCAL_INIT_WAIT_PREG,Receive signal detect calibration initial wait timer providing a circuit settling period at the initiation of the calibration sequence"
group.long 0x4338++0x0B
line.long 0x00 "RXTERM_ENABLE_PREG__RXTERM_BSCAN_PREG_j,Receiver termination boundary scan support register Offset = 4338h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x00 20. "RX_TERM_GNDRESSEL_PREG,Receive termination configuration select" "0,1"
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bitfld.long 0x00 17. "RXTERM_EN_OVRVAL_PREG,Receive termination enable override value" "0,1"
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bitfld.long 0x00 16. "RXTERM_EN_OVREN_PREG,Receive termination enable override enable" "0,1"
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bitfld.long 0x00 0.--3. "RXTERM_BSCAN_RESCAL_PREG,Receive termination resistor calibration level used in boundary scan operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "RXBUFFER_RCDFECTRL_PREG__RXBUFFER_CTLECTRL_PREG_j,RX buffer CTLE control register Offset = 433Ch + (j * 400h); where j = 0h to 1h"
bitfld.long 0x04 28.--30. "RXBUFFER_RCTRIMDFE_MODE3_PREG,Trim for rxana_dfe path high frequency gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 24.--26. "RXBUFFER_RCTRIMDFE_MODE2_PREG,Trim for rxana_dfe path high frequency gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 20.--22. "RXBUFFER_RCTRIMDFE_MODE1_PREG,Trim for rxana_dfe path high frequency gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 16.--18. "RXBUFFER_RCTRIMDFE_MODE0_PREG,Trim for rxana_dfe path high frequency gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 12.--14. "RXBUFFER_RCTRIMCTLE_DCBIASATTEN1_PREG,Trim for rxana_ctleclk path high frequency gain when ctleclk_dcbiasatten is 1'b1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 8.--10. "RXBUFFER_RCTRIMCTLE_DCBIASATTEN0_PREG,Trim for rxana_ctleclk path high frequency gain when ctleclk_dcbiasatten is 1'b0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 4.--6. "RXBUFFER_TRIMCTLE_DCBIASATTEN1_PREG,Trim for rxana_ctleclk path DC gain when ctleclk_dcbiasatten is 1'b1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--2. "RXBUFFER_TRIMCTLE_DCBIASATTEN0_PREG,Trim for rxana_ctleclk path DC gain when ctleclk_dcbiasatten is 1'b0" "0,1,2,3,4,5,6,7"
line.long 0x08 "RXBUFFER_DFECTRL_PREG_j,RX buffer DFE control register Offset = 4340h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x08 12.--14. "RXBUFFER_TRIMDFE_MODE3_PREG,Trim for rxana_dfe path DC gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b011" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 8.--10. "RXBUFFER_TRIMDFE_MODE2_PREG,Trim for rxana_dfe path DC gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b010" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 4.--6. "RXBUFFER_TRIMDFE_MODE1_PREG,Trim for rxana_dfe path DC gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b001" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--2. "RXBUFFER_TRIMDFE_MODE0_PREG,Trim for rxana_dfe path DC gain when xcvr_standard_mode_ln_{15:0}[2:0] is 3'b000" "0,1,2,3,4,5,6,7"
group.long 0x4348++0x0F
line.long 0x00 "DEQ_EYESURF_VTH_PREG__DEQ_EYESURF_CTRL_PREG_j,Receive data path eye surf control register"
hexmask.long.byte 0x00 16.--22. 1. "EYESURF_ECMPVTH_PREG,Receive data path eye surf comparator voltage binary encoded threshold selection"
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bitfld.long 0x00 12.--15. "EYESURF_TIME_PREG,Receive data path eye surf accumulation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 11. "EYESURF_VALID,Receive data path eye surf accumulation period active high complete flag" "0,1"
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bitfld.long 0x00 10. "EYESURF_START_PREG,Receive data path eye surf active high start sequence enable" "0,1"
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bitfld.long 0x00 9. "EYESURF_MODE_PREG,Receive data path eye surf active high mode enable" "0,1"
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hexmask.long.byte 0x00 0.--6. 1. "EYESURF_EPIADJ_PREG,Receive data path eye surf EPI position shift control"
line.long 0x04 "DEQ_EYESURF_ACCUMB__DEQ_EYESURF_ACCUMA_j,Receive data path eye surf accumulator A status register"
hexmask.long.word 0x04 16.--25. 1. "EYESURF_ACCUMB,Receive data path eye surf accumulator B result"
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hexmask.long.word 0x04 0.--9. 1. "EYESURF_ACCUMA,Receive data path eye surf accumulator A result"
line.long 0x08 "RX_BIST_SYNCCNT_PREG__RX_BIST_CONTROLS_PREG_j,Receive BIST control register"
hexmask.long.word 0x08 16.--31. 1. "RX_BIST_SYNC_COUNT_PREG,Receive BIST synchronization count"
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bitfld.long 0x08 8.--11. "RX_BIST_MODE_PREG,Receive BIST mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "RX_BIST_ERR_RESET_PREG,Receive BIST error clear" "0,1"
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bitfld.long 0x08 1. "RX_BIST_UDD_WR_CLEAR_PREG,Receive BIST User Defined Data (UDD) FIFO write pointer clear" "0,1"
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bitfld.long 0x08 0. "RX_BIST_EN_PREG,Receive BIST active high enable" "0,1"
line.long 0x0C "RX_BIST_ERRCNT_PREG__RX_BIST_UDD_PREG_j,Receive BIST user defined data (UDD) FIFO definition register"
hexmask.long.word 0x0C 16.--31. 1. "RX_BIST_ERR_COUNT,Receive BIST accumulated error count"
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hexmask.long.word 0x0C 0.--9. 1. "RX_UDD_FIFO_WR_DATA,Receive BIST user defined data"
group.long 0x4360++0x03
line.long 0x00 "LN_SPARE_REG_PREG_j,Local Lane spare register"
hexmask.long.word 0x00 0.--15. 1. "SPARE_PREG,Spare register bits assigned to lnda_sparecdb"
group.long 0x4370++0x03
line.long 0x00 "PREADAPT_CTRL_PREG_j,Pre-adaptation control register"
bitfld.long 0x00 12. "PREADAPT_EN_PREG,Active high pre-adaptation enable" "0,1"
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bitfld.long 0x00 8.--9. "PREADAPT_STANDARD_MODE_SEL_PREG,Pre-adaptation xcvr_standard_mode selection" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "PREADAPT_STATE,Pre-adpatation current state"
rgroup.long 0x4380++0x0B
line.long 0x00 "LN_CTRL_DIAG_RESET_PREG__LN_FPWRISO_DIAG_RESET_PREG_j,Lane fpwriso reset diagnostic register Offset = 4380h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x00 19. "LN_PSMRST_N,Current state of the ln_psmrst_n reset" "0,1"
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bitfld.long 0x00 18. "PSTG_RST_N,Current state of the pstg_rst_n reset" "0,1"
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bitfld.long 0x00 17. "CMN_RESET_SYNCED_LN_PLLCLK_N,Current state of the cmn_reset_synced_ln_pllclk_n reset" "0,1"
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bitfld.long 0x00 16. "SCANOVRD_PLLLN_RST_N,Current state of the scanovrd_pllln_rst_n reset" "0,1"
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bitfld.long 0x00 0. "LNDA_RSTGEN_RST_N,Current state of the lnda_rstgen_rst_n reset" "0,1"
line.long 0x04 "LN_TXDSYNC_DIAG_RESET_PREG__LN_TXCTRL_DIAG_RESET_PREG_j,Lane Tx control reset diagnostic register Offset = 4384h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x04 17. "TX_SYNC_FIFO_RD_RESET_N,Current state of the tx_sync_fifo_rd_reset_n reset" "0,1"
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bitfld.long 0x04 16. "TX_SYNC_FIFO_WR_RESET_N,Current state of the tx_sync_fifo_wr_reset_n reset" "0,1"
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bitfld.long 0x04 2. "CMN_RESET_SYNCED_TX_REFCLK_GATED_N,Current state of the cmn_reset_synced_tx_refclk_gated_n reset" "0,1"
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bitfld.long 0x04 1. "TX_LFPSGEN_RST_N,Current state of the tx_lfpsgen_rst_n reset" "0,1"
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bitfld.long 0x04 0. "TX_BIST_RST_N,Current state of the tx_bist_rst_n reset" "0,1"
line.long 0x08 "LN_RXDSYNC_DIAG_RESET_PREG__LN_RXCTRL_DIAG_RESET_PREG_j,Lane Rx control reset diagnostic register Offset = 4388h + (j * 400h); where j = 0h to 1h"
bitfld.long 0x08 19. "TX_TD_FE_LPBK_RST_N,Current state of the tx_td_fe_lpbk_rst_n reset" "0,1"
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bitfld.long 0x08 18. "RXDA_DEQ_RST_N,Current state of the rxda_deq_rst_n reset" "0,1"
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bitfld.long 0x08 17. "RXDATRST_N,Current state of the rxdatrst_n reset" "0,1"
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bitfld.long 0x08 16. "RXMEMRST_N,Current state of the rxmemrst_n reset" "0,1"
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bitfld.long 0x08 5. "CMN_RESET_SYNCED_RX_REFCLK_GATED_N,Current state of the cmn_reset_synced_rx_refclk_gated_n reset" "0,1"
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bitfld.long 0x08 4. "CMN_RESET_SYNCED_LN_PLLCLK_FULLRT_N,Current state of the cmn_reset_synced_ln_pllclk_fullrt_n reset" "0,1"
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bitfld.long 0x08 3. "CMN_RESET_SYNCED_CMN_SDOSC_CLK_N,Current state of the cmn_reset_synced_cmn_sdosc_clk_n reset" "0,1"
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bitfld.long 0x08 2. "CPICAL_CNTRST_N,Current state of the cpical_cntrst_n reset" "0,1"
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bitfld.long 0x08 1. "RXDA_ECMP_RST_N,Current state of the rxda_ecmp_rst_n reset" "0,1"
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bitfld.long 0x08 0. "RXDA_SMP_RST_N,Current state of the rxda_smp_rst_n reset" "0,1"
group.long 0x4390++0x07
line.long 0x00 "LN_CMSMT_REF_CLK_TMR_VALUE_PREG__LN_CLK_FREQ_MSMT_CTRL_PREG_j,Register For Controlling Clock Frequency Measurement Module"
hexmask.long.word 0x00 16.--27. 1. "LN_CMSMT_REF_CLK_TMR_VALUE_PREG,Reference clock Timer Value"
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bitfld.long 0x00 1.--3. "LN_TEST_CLK_SEL_PREG,Select Line For Clock Signal Muxing" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "LN_CMSMT_MEASUREMENT_RUN_PREG,Clock Frequency Measurement Enablign Signal" "0,1"
line.long 0x04 "LN_CLK_FREQ_MSMT_OBS_PREG__LN_CMSMT_TEST_CLK_CNT_VALUE_PREG_j,Status Register Indicating the test clock count value from Clock Frequency Measurement Module"
bitfld.long 0x04 16. "LN_CMSMT_MEASUREMENT_DONE,Clock Frequency Measurement Done Output" "0,1"
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hexmask.long.word 0x04 0.--11. 1. "LN_CMSMT_TEST_CLK_CNT_VALUE,Test Clock Count value Output"
group.long 0x43A0++0x03
line.long 0x00 "RXMRGN_CTRL_PREG_j,RX margining control and status register Offset = 43A0h + (j * 400h); where j = 0h to 1h"
rbitfld.long 0x00 12.--15. "RXMRGN_FSM_STATE,ln_rxctrl_rxmrgn FSM state vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "RXMRGN_CLK_FORCE_PREG,When asserted rxmrgb_clk remains on when whenever rxdatclk is on in power state where psc_rxmrgn_en is asserted" "0,1"
group.long 0x43B0++0x17
line.long 0x00 "SMPCAL_INIT_PREG__SMPCAL_CTRL_PREG_j,Data path sampler offset calibration control register"
hexmask.long.word 0x00 16.--25. 1. "SMPCAL_INIT_WAIT_PREG,Data path sampler offset calibration initial wait timer"
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bitfld.long 0x00 15. "SMPCAL_RUN_PREG,Data path sampler offset calibration manual start signal" "0,1"
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bitfld.long 0x00 14. "SMPCALMEM_POSOFF_INVERT,Data path sampler offset calibration positive offset correction inversion" "0,1"
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rbitfld.long 0x00 13. "SMPCAL_NO_ANA_RESP,Data path sampler offset calibration no analog response flag" "0,1"
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rbitfld.long 0x00 12. "SMPCAL_ERROR,Data path sampler offset calibration error flag" "0,1"
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bitfld.long 0x00 4.--5. "SMPCAL_SCALE_PREG,Data path sampler offset calibration scale register" "0,1,2,3"
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bitfld.long 0x00 2. "SMPCAL_DONE_OVR_PREG,Data path sampler offset calibration done override" "0,1"
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bitfld.long 0x00 1. "SMPCAL_EN_OVR_PREG,Data path sampler offset calibration enable active high override enable" "0,1"
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bitfld.long 0x00 0. "SMPCAL_EN_OVRVAL_PREG,Data path sampler offset calibration enable active high override value" "0,1"
line.long 0x04 "SMPCAL_NUM_WORDS_PREG__SMPCAL_ITER_PREG_j,Data path sampler offset calibration iteration timer register"
hexmask.long.word 0x04 16.--25. 1. "SMPCAL_NUM_WORDS_PREG,Data path sampler offset calibration accumulation period timer"
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hexmask.long.word 0x04 0.--9. 1. "SMPCAL_ITER_WAIT_PREG,Data path sampler offset calibration iteration wait timer"
line.long 0x08 "SMPCAL_TUNE_PREG__SMPCAL_START_PREG_j,Data path sampler offset calibration starting code register"
hexmask.long.byte 0x08 16.--23. 1. "SMPCAL_TUNE_PREG,Data path sampler offset calibration tuning offset"
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hexmask.long.byte 0x08 0.--7. 1. "SMPCAL_START_PREG,Data path sampler offset calibration start code"
line.long 0x0C "SMPCAL_CALODDCODE_OVR_PREG__SMPCAL_CALEVNCODE_OVR_PREG_j,Data path sampler offset calibration even code override register"
bitfld.long 0x0C 31. "SMPCALMEM_CALODDCODE_OVREN_PREG,Data path sampler offset calibration odd code active high override enable" "0,1"
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hexmask.long.byte 0x0C 16.--23. 1. "SMPCALMEM_CALODDCODE_OVRVAL_PREG,When smpcalmem_caloddcode_ovren_preg is asserted high this value overrides the rxda_smp_caloddmag and rxda_smp_caloddposoff analog controls as follows"
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bitfld.long 0x0C 15. "SMPCALMEM_CALEVNCODE_OVREN_PREG,Data path sampler offset calibration even code active high override enable" "0,1"
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hexmask.long.byte 0x0C 0.--7. 1. "SMPCALMEM_CALEVNCODE_OVRVAL_PREG,When smpcalmem_calevncode_ovren_preg is asserted high this value overrides the rxda_smp_calevnmag and rxda_smp_calevnposoff analog controls as follows"
line.long 0x10 "SMPCAL_CALODDCODE_PREG__SMPCAL_CALEVNCODE_PREG_j,Data path sampler offset calibration even slicer status register"
bitfld.long 0x10 31. "SMPCAL_ODDDONE,Data path sampler offset odd calibration active high complete flag" "0,1"
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hexmask.long.byte 0x10 16.--23. 1. "SMPCAL_CALODDCODE,Data path sampler offset calibration odd calibration result"
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bitfld.long 0x10 15. "SMPCAL_EVNDONE,Data path sampler offset even calibration active high complete flag" "0,1"
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hexmask.long.byte 0x10 0.--7. 1. "SMPCAL_CALEVNCODE,Data path sampler offset calibration even calibration result"
line.long 0x14 "SMPCAL_STATE_PREG_j,Data path sampler offset calibration master state machine state vector status register"
hexmask.long.word 0x14 0.--9. 1. "SMPCAL_STATE,Data path sampler offset calibration master state machine state vector"
group.long 0x43D0++0x0F
line.long 0x00 "DEQ_BMPR_TAU_CTRL2_PREG__DEQ_BMPR_TAU_CTRL1_PREG_j,Receive data path equalization (DEQ) bumper TAU algorithm control register 1 Offset = 43D0h + (j * 400h); where j = 0h to 1h"
hexmask.long.word 0x00 16.--25. 1. "BMPR_TAU_ERROR_THRESH_PREG,Bumper TAU algorithm error accumulation threshold"
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bitfld.long 0x00 15. "BMPR_TAU_DIR_PREG,Bumper TAU algorithm EPI initial direction control" "0,1"
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bitfld.long 0x00 12.--13. "BMPR_TAU_PING_PONG_EN_PREG,Bumper TAU ping pong enable register" "0,1,2,3"
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bitfld.long 0x00 0.--3. "BMPR_TAU_EPIOFFSET_PREG,Bumper TAU algorithm 4 bit signed offset for EPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DEQ_TAU_MAINT_VTH_PREG__DEQ_TAU_ACQ_VTH_PREG_j,Receive data path equalization (DEQ) TAU algorithm acquisition voltage threshold control register Offset = 43D4h + (j * 400h); where j = 0h to 1h"
hexmask.long.byte 0x04 24.--30. 1. "TAU_MAINTECMPA_VTH_PREG,TAU algorithm voltage threshold control register for both error comparators A and B binary encoded used for maintenance for bumper TAU during ST_BMPR_TAU_ACCUM_A and for apparent center and maintenace for block TAU during.."
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hexmask.long.byte 0x04 16.--22. 1. "TAU_MAINTECMPB_VTH_PREG,TAU algorithm voltage threshold control register for both error comparators A and B binary encoded used for maintenance for bumper TAU during ST_BMPR_TAU_ACCUM_B and for apparent center and maintenace for block TAU during.."
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hexmask.long.byte 0x04 8.--14. 1. "TAU_ECMPA_VTH_PREG,TAU algorithm voltage threshold control register for both error comparators A and B binary encoded used for initial acquisition for bumper TAU during ST_BMPR_TAU_ACCUM_A and block TAU during ST_BLK_TAU_ACCUM_A"
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hexmask.long.byte 0x04 0.--6. 1. "TAU_ECMPB_VTH_PREG,TAU algorithm voltage threshold control register for both error comparators A and B binary encoded used for initial acquisition for bumper TAU during ST_BMPR_TAU_ACCUM_B and block TAU during ST_BLK_TAU_ACCUM_B"
line.long 0x08 "DEQ_BLK_TAU_CTRL2_PREG__DEQ_BLK_TAU_CTRL1_PREG_j,Receive data path equalization (DEQ) block TAU algorithm control register 1 Offset = 43D8h + (j * 400h); where j = 0h to 1h"
hexmask.long.byte 0x08 24.--30. 1. "BLK_TAU_EPISHIFT_OPTCENT,Block TAU algorithm optimal EPI phase shift obtained from AC_TAU"
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bitfld.long 0x08 23. "BLK_TAU_EPISHIFT_OPTCENT_OVREN_PREG,Block TAU algorithm EPI phase shift override enable used for maintenance" "0,1"
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hexmask.long.byte 0x08 16.--22. 1. "BLK_TAU_EPISHIFT_OPTCENT_OVRD_PREG,Block TAU algorithm EPI phase shift override value used for maintenance"
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bitfld.long 0x08 12.--15. "BLK_TAU_EPIOFFSETA_PREG,Block TAU algorithm 4 bit signed offset for EPI used for accumulation during ST_TAU3_ACCUM_A during initial acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "BLK_TAU_EPIOFFSETB_PREG,Block TAU algorithm 4 bit signed offset for EPI used for accumulation during ST_TAU3_ACCUM_B during initial acquisition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. "BLK_TAU_MAINT_EPIOFFSETA_PREG,Block TAU algorithm 4 bit signed offset for EPI used for accumulation during ST_TAU3_ACCUM_A during AC_TAU and maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "BLK_TAU_MAINT_EPIOFFSETB_PREG,Block TAU algorithm 4 bit signed offset for EPI used for accumulation during ST_TAU3_ACCUM_B during AC_TAU and maintenance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DEQ_BLK_TAU_CTRL4_PREG__DEQ_BLK_TAU_CTRL3_PREG_j,Receive data path equalization (DEQ) block TAU algorithm control register 3 Offset = 43DCh + (j * 400h); where j = 0h to 1h"
hexmask.long.byte 0x0C 16.--22. 1. "BLK_TAU_DPI_OPTCENT,Block TAU algorithm optimal DPI phase obtained from initial acquisition"
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bitfld.long 0x0C 10.--13. "BLK_TAU_PATTERN_MASK_PREG,Block TAU algorithm pattern filter mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 9. "BLK_TAU_AC_BYPASS_CONCUR_PREG,Block TAU algorithm bypass concur register" "0,1"
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hexmask.long.word 0x0C 0.--8. 1. "BLK_TAU_AC_MINITER_PREG,Block TAU algorithm minimum iterations of AC_TAU and concur processes during the apparent center states"
group.long 0xC000++0x17
line.long 0x00 "PHY_PIPE_CMN_CTRL2__PHY_PIPE_CMN_CTRL1,PIPE common control1 register"
bitfld.long 0x00 28.--31. "PHY_PIPE_CMN_CTRL2_15_12,USB SuperSpeed Tx LFPS Stretch: Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeed rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PHY_PIPE_CMN_CTRL2_11_8,USB SuperSpeedPlus Tx LFPS Stretch: Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeedPlus rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "PHY_PIPE_CMN_CTRL2_7,PCIe PIPE Gen 4 Rx mode" "0,1"
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bitfld.long 0x00 22. "PHY_PIPE_CMN_CTRL2_6,TX electrical idle pre release: When this bit is set the TX electrical idle release to the PMA is advanced 1 cycle to allow the adjustment of the data path timing" "0,1"
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bitfld.long 0x00 21. "PHY_PIPE_CMN_CTRL2_5,RX equalizer complete mask: When this bit is cleared the PHY will return direction change of 0 when PMA indicates evaluation complete" "0,1"
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bitfld.long 0x00 20. "PHY_PIPE_CMN_CTRL2_4,PCIe Gen 1/2 EIOS cycle error mask: When this bit is enabled and the pipe rx interface is outputting a PCIe Gen 1/2 EIOS symbol decode errors will be masked out" "0,1"
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bitfld.long 0x00 19. "PHY_PIPE_CMN_CTRL2_3,USB Gen 2 Bit Error Correction Disable: When this bit is high bit error correction on SKP and SDS symbols is disabled" "0,1"
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bitfld.long 0x00 18. "PHY_PIPE_CMN_CTRL2_2,USB PIPE3 Compatibility Mode enable: When this bit is set to 1 USB PIPE3 compatibility mode is enabled" "0,1"
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bitfld.long 0x00 17. "PHY_PIPE_CMN_CTRL2_1,USB Loopback Slave Error Count disable: When this bit is set to 1 disables the error count for US loopback slave such that the error count is not inserted into the BCNT OS" "0,1"
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bitfld.long 0x00 16. "PHY_PIPE_CMN_CTRL2_0,USB Elasticity Buffer Re-align enable: When this bit is set to 1 when Rx for a USB link is initially started the elasticity buffer is re-aligned to its idle point upon seeing 3 consecutive COMMAs (i.e. from TS1/TS2s) in the same.." "0,1"
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rbitfld.long 0x00 13.--15. "PHY_PIPE_CMN_CTRL1_15_13,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12. "PHY_PIPE_CMN_CTRL1_12,PHY APB access timeout: When set an APB read/write request to PHY registers failed (i.e. timed out)" "0,1"
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rbitfld.long 0x00 11. "PHY_PIPE_CMN_CTRL1_11,Reserved" "0,1"
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bitfld.long 0x00 10. "PHY_PIPE_CMN_CTRL1_10,Comma realign: This field controls the comma alignment state machine to re-align to new bit position without going to loss of sync state for Gen1/2" "0,1"
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bitfld.long 0x00 9. "PHY_PIPE_CMN_CTRL1_9,Block alignment clear on EIOS Gen4: When this bit is enabled and the Gen 3/4 block alignment sees an EIOS then the block alignment will automatically reset regardless of signal detect from the PMA" "0,1"
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bitfld.long 0x00 8. "PHY_PIPE_CMN_CTRL1_8,Comma alignment clear on EIOS Gen2: When this bit is enabled and the Gen 1/2 comma alignment sees an EIOS then the COMMA alignment will automatically reset regardless of signal detect from the PMA" "0,1"
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bitfld.long 0x00 7. "PHY_PIPE_CMN_CTRL1_7,Block alignment ignore rx_sigdetect Gen4: When this signal is enabled the PCS receive path block alignment will not clear due to loss of signal detection from the PMA in Gen 3/4 mode" "0,1"
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bitfld.long 0x00 6. "PHY_PIPE_CMN_CTRL1_6,Comma alignment ignore rx_sigdetect Gen2: When this signal is enabled the PCS receive path COMMA alignment will not clear due to loss of signal detection from the PMA in Gen 1/2 mode" "0,1"
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bitfld.long 0x00 4.--5. "PHY_PIPE_CMN_CTRL1_5_4,RX signal detect delay: Controls how much delay to add to the PMA signal detect to delay when the bit alignment blocks should be reset after losing signal" "0,1,2,3"
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rbitfld.long 0x00 0.--3. "PHY_PIPE_CMN_CTRL1_3_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PHY_PIPE_COM_LOCK_CFG2__PHY_PIPE_COM_LOCK_CFG1,PIPE comma lock configuration1 register ()"
hexmask.long.byte 0x04 24.--31. 1. "PHY_PIPE_COM_LOCK_CFG2_15_8,comma lock count fast: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock for Gen1/2"
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hexmask.long.byte 0x04 16.--23. 1. "PHY_PIPE_COM_LOCK_CFG2_7_0,comma lock count: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock for Gen1/2"
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bitfld.long 0x04 12.--15. "PHY_PIPE_COM_LOCK_CFG1_15_12,Symbol unlock count: The number of COMMA symbols that needs to be seen in the wrong bit position before the comma alignment state machine will transition to RESYNC or LOS state for Gen1/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x04 0.--11. 1. "PHY_PIPE_COM_LOCK_CFG1_11_0,comma full lock count: The number of COMMA symbols that needs to be seen in the same bit position for the comma alignment state machine to lock for Gen1/2"
line.long 0x08 "PHY_PIPE_LANE_DSBL__PHY_PIPE_EIE_LOCK_CFG,PIPE EIEOS lock configuration register ()"
hexmask.long.word 0x08 16.--31. 1. "PHY_PIPE_LANE_DSBL_15_0,lane disable: When set the appropriate lane is disabled"
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bitfld.long 0x08 12.--15. "PHY_PIPE_EIE_LOCK_CFG_15_12,EIE lock count fast: The number of EIEOS blocks that need to be seen in the same bit position for the alignment state machine to lock for Gen3/4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "PHY_PIPE_EIE_LOCK_CFG_11_8,EIE lock count: The number of EIEOS blocks that need to be seen in the same bit position for the alignment state machine to lock for Gen3/4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 0.--7. 1. "PHY_PIPE_EIE_LOCK_CFG_7_0,EIE full lock count: The number of EIEOS blocks that need to be seen in the same bit position for the alignment state machine to lock for Gen3/4"
line.long 0x0C "PHY_PIPE_RX_ELEC_IDLE_DLY__PHY_PIPE_RCV_DET_INH,PIPE receiver detect inhibit register ()"
bitfld.long 0x0C 26.--31. "PHY_PIPE_RX_ELEC_IDLE_DLY_15_10,L1.x exit Rx electrical idle force fast count: Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x0C 16.--25. 1. "PHY_PIPE_RX_ELEC_IDLE_DLY_9_0,L1.x exit Rx electrical idle force full count: Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x when the PMA common was powered down"
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hexmask.long.word 0x0C 0.--15. 1. "PHY_PIPE_RCV_DET_INH_15_0,Receiver Detect Inhibit Counter Load Value: Counter load value to delay receiver detection request to PMA until PMA common mode is within the required range"
line.long 0x10 "PHY_ISO_CMN_CTRL,PHY common control signal isolation register"
hexmask.long.word 0x10 1.--15. 1. "PHY_ISO_CMN_CTRL_15_1,Reserved"
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bitfld.long 0x10 0. "PHY_ISO_CMN_CTRL_0,Drives the phy_reset_n PHY input when in PHY macro and PMA isolation modes" "0,1"
line.long 0x14 "PHY_STATE_CHG_TIMEOUT,PHY state change monitor timeout"
hexmask.long.word 0x14 0.--15. 1. "PHY_STATE_CHG_TIMEOUT_15_0,State change timeout: Bits [19:4] of the state change timeout (bits [3:0] are zero)"
group.long 0xC01C++0x2B
line.long 0x00 "PHY_AUTO_CFG_CTRL__PHY_PLL_CFG,PHY PLL configuration register"
hexmask.long.word 0x00 20.--31. 1. "PHY_AUTO_CFG_CTRL_15_4,Reserved"
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rbitfld.long 0x00 19. "PHY_AUTO_CFG_CTRL_3,Auto-configuration complete" "0,1"
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bitfld.long 0x00 18. "PHY_AUTO_CFG_CTRL_2,Auto-configuration stall" "0,1"
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rbitfld.long 0x00 17. "PHY_AUTO_CFG_CTRL_1,Reserved" "0,1"
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bitfld.long 0x00 16. "PHY_AUTO_CFG_CTRL_0,Auto-configuration disable" "0,1"
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rbitfld.long 0x00 10.--15. "PHY_PLL_CFG_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 9. "PHY_PLL_CFG_9,RefClk1 disable override: When set to 1 overrides asserting cmn_refclk1_disable to the PMA high when the PMA is suspended (i.e. all links in low power state)" "0,1"
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bitfld.long 0x00 8. "PHY_PLL_CFG_8,RefClk disable override: When set to 1 overrides asserting cmn_refclk_disable to the PMA high when the PMA is suspended (i.e. all links in low power state)" "0,1"
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bitfld.long 0x00 4.--7. "PHY_PLL_CFG_7_4,Dual port mode port 1 lane number: When configured for dual port mode this field selects the master lane for port/link 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 3. "PHY_PLL_CFG_3,Reserved" "0,1"
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bitfld.long 0x00 2. "PHY_PLL_CFG_2,Dual port mode enable" "0,1"
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bitfld.long 0x00 1. "PHY_PLL_CFG_1,PLL LC only" "0,1"
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bitfld.long 0x00 0. "PHY_PLL_CFG_0,Single link PCIe configuration" "0,1"
line.long 0x04 "PHY_REFCLK1_DET_THRES_LOW__PHY_REFCLK_DET_THRES_LOW,PHY external reference clock detect low threshold register"
hexmask.long.word 0x04 16.--31. 1. "PHY_REFCLK1_DET_THRES_LOW_15_0,External Reference Clock1 Active Detect Low Threshold: This is the minimum number of external reference clock cycles (on cmn_refclk1_p/m) which must be counted during the measurement interval to indicate a valid clock.."
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hexmask.long.word 0x04 0.--15. 1. "PHY_REFCLK_DET_THRES_LOW_15_0,External Reference Clock Active Detect Low Threshold: This is the minimum number of external reference clock cycles (on cmn_refclk_p/m) which must be counted during the measurement interval to indicate a valid clock detected"
line.long 0x08 "PHY_REFCLK1_DET_THRES_HIGH__PHY_REFCLK_DET_THRES_HIGH,PHY external reference clock detect high threshold register"
hexmask.long.word 0x08 16.--31. 1. "PHY_REFCLK1_DET_THRES_HIGH_15_0,External Reference Clock1 Active Detect High Threshold: This is the maximum number of external reference clock cycles (on cmn_refclk1_p/m) which must be counted during the measurement interval to indicate a valid clock.."
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hexmask.long.word 0x08 0.--15. 1. "PHY_REFCLK_DET_THRES_HIGH_15_0,External Reference Clock Active Detect High Threshold: This is the maximum number of external reference clock cycles (on cmn_refclk_p/m) which must be counted during the measurement interval to indicate a valid clock.."
line.long 0x0C "PHY_REFCLK1_DET_INTERVAL__PHY_REFCLK_DET_INTERVAL,PHY external reference clock detect measurement interval register"
hexmask.long.word 0x0C 16.--31. 1. "PHY_REFCLK1_DET_INTERVAL_15_0,External Reference Clock1 Active Detect Measurement Interval: This is the number of apb_pclk cycles in which to count external reference clock cycles (on cmn_refclk1_p/m)"
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hexmask.long.word 0x0C 0.--15. 1. "PHY_REFCLK_DET_INTERVAL_15_0,External Reference Clock Active Detect Measurement Interval: This is the number of apb_pclk cycles in which to count external reference clock cycles (on cmn_refclk_p/m)"
line.long 0x10 "PHY_REFCLK1_DET_OP_DELAY__PHY_REFCLK_DET_OP_DELAY,PHY external reference clock detect delay register"
hexmask.long.byte 0x10 24.--31. 1. "PHY_REFCLK1_DET_OP_DELAY_15_8,External Reference Clock1 Active Detect End Delay: This is the number of apb_pclk cycles to wait upon completion of measurement interval before capturing the result (accounts for synchronization delays) for measurement on.."
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hexmask.long.byte 0x10 16.--23. 1. "PHY_REFCLK1_DET_OP_DELAY_7_0,External Reference Clock1 Active Detect Start Delay: This is the number of apb_pclk cycles to wait prior to start of measurement interval (accounts for enable delay of reference clock in PMA) for measurement on cmn_refclk1_p/m"
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hexmask.long.byte 0x10 8.--15. 1. "PHY_REFCLK_DET_OP_DELAY_15_8,External Reference Clock Active Detect End Delay: This is the number of apb_pclk cycles to wait upon completion of measurement interval before capturing the result (accounts for synchronization delays) for measurement on.."
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hexmask.long.byte 0x10 0.--7. 1. "PHY_REFCLK_DET_OP_DELAY_7_0,External Reference Clock Active Detect Start Delay: This is the number of apb_pclk cycles to wait prior to start of measurement interval (accounts for enable delay of reference clock in PMA) for measurement on cmn_refclk_p/m"
line.long 0x14 "PHY_REFCLK_DET_ISO_CTRL,PHY external reference clock detect isolation control register"
rbitfld.long 0x14 14.--15. "PHY_REFCLK_DET_ISO_CTRL_15_14,Reserved" "0,1,2,3"
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rbitfld.long 0x14 13. "PHY_REFCLK_DET_ISO_CTRL_13,Captures the current value of the pma_cmn_ext_refclk1_detected_cfg PHY input" "0,1"
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rbitfld.long 0x14 12. "PHY_REFCLK_DET_ISO_CTRL_12,Captures the current value of the pma_cmn_ext_refclk_detected_cfg PHY input" "0,1"
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rbitfld.long 0x14 11. "PHY_REFCLK_DET_ISO_CTRL_11,Current value of pma_cmn_ext_refclk1_detected PHY output" "0,1"
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rbitfld.long 0x14 10. "PHY_REFCLK_DET_ISO_CTRL_10,Current value of pma_cmn_ext_refclk1_detected_valid PHY output" "0,1"
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rbitfld.long 0x14 9. "PHY_REFCLK_DET_ISO_CTRL_9,Current value of pma_cmn_ext_refclk_detected PHY output" "0,1"
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rbitfld.long 0x14 8. "PHY_REFCLK_DET_ISO_CTRL_8,Current value of pma_cmn_ext_refclk_detected_valid PHY output" "0,1"
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rbitfld.long 0x14 2.--7. "PHY_REFCLK_DET_ISO_CTRL_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "PHY_REFCLK_DET_ISO_CTRL_1,External Reference Clock1 Active Detect Start: Write with 1 to initiate an external reference clock active detect operation on cmn_refclk1_p/m" "0,1"
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bitfld.long 0x14 0. "PHY_REFCLK_DET_ISO_CTRL_0,External Reference Clock Active Detect Start: Write with 1 to initiate an external reference clock active detect operation on cmn_refclk_p/m" "0,1"
line.long 0x18 "PHY_PIPE_LM_CFG0,PHY PIPE lane margining configuration 0 register (#)"
hexmask.long.byte 0x18 24.--31. 1. "PHY_PIPE_LM_CFG0_15_8,Reserved"
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hexmask.long.byte 0x18 16.--23. 1. "PHY_PIPE_LM_CFG0_7_0,Lane margining direction configuration: Maps the PIPE margin direction encoding to the PMA margin direction encoding"
line.long 0x1C "PHY_PIPE_LM_CFG2__PHY_PIPE_LM_CFG1,PHY PIPE lane margining configuration 1 register (#)"
hexmask.long.byte 0x1C 24.--31. 1. "PHY_PIPE_LM_CFG2_15_8,Lane margining sample count threshold: This is the sample count saturation point"
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hexmask.long.byte 0x1C 16.--23. 1. "PHY_PIPE_LM_CFG2_7_0,Lane margining sample count maximum: This is sample count value reported whenever total sample count value X= sample count threshold (bits [15:8])"
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rbitfld.long 0x1C 12.--15. "PHY_PIPE_LM_CFG1_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 8.--11. "PHY_PIPE_LM_CFG1_11_8,Lane margining wait time: This is wait time at PMA interface between setting PMA inputs rx_mrgn_offset and rx_mrgn_dir before asserting rx_mrgn_req" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 6.--7. "PHY_PIPE_LM_CFG1_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x1C 0.--5. "PHY_PIPE_LM_CFG1_5_0,Lane margining sample count 3 logn value: This is the value of 3 * logn (number of samples per PMA eye surf iteration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "PHY_PIPE_LM_CFG4__PHY_PIPE_LM_CFG3,PHY PIPE lane margining configuration 3 register (#)"
rbitfld.long 0x20 31. "PHY_PIPE_LM_CFG4_15,Reserved" "0,1"
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hexmask.long.byte 0x20 24.--30. 1. "PHY_PIPE_LM_CFG4_14_8,Lane margining maximum voltage offset: This is the maximum voltage offset supported by the PMA"
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rbitfld.long 0x20 22.--23. "PHY_PIPE_LM_CFG4_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x20 16.--21. "PHY_PIPE_LM_CFG4_5_0,Lane margining maximum timing offset: This is the maximum timing offset supported by the PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x20 14.--15. "PHY_PIPE_LM_CFG3_15_14,Reserved" "0,1,2,3"
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bitfld.long 0x20 8.--13. "PHY_PIPE_LM_CFG3_13_8,Lane margining error count threshold: Maximum total error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x20 6.--7. "PHY_PIPE_LM_CFG3_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x20 0.--5. "PHY_PIPE_LM_CFG3_5_0,Lane margining error count maximum: This is the error count reported whenever the total error count value X= error count threshold (bits [13:8])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "PHY_PIPE_USB3_GEN2_PRE_CFG1__PHY_PIPE_USB3_GEN2_PRE_CFG0,PHY USB3 Gen 2 pre-shoot configuration 0 register ()"
hexmask.long.byte 0x24 24.--31. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG1_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration"
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hexmask.long.byte 0x24 16.--23. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG1_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration"
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hexmask.long.byte 0x24 8.--15. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG0_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration"
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hexmask.long.byte 0x24 0.--7. 1. "PHY_PIPE_USB3_GEN2_PRE_CFG0_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration"
line.long 0x28 "PHY_PIPE_USB3_GEN2_POST_CFG1__PHY_PIPE_USB3_GEN2_POST_CFG0,PHY USB3 Gen 2 de-emphasis configuration 0 register ()"
hexmask.long.byte 0x28 24.--31. 1. "PHY_PIPE_USB3_GEN2_POST_CFG1_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration"
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hexmask.long.byte 0x28 16.--23. 1. "PHY_PIPE_USB3_GEN2_POST_CFG1_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration"
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hexmask.long.byte 0x28 8.--15. 1. "PHY_PIPE_USB3_GEN2_POST_CFG0_15_8,USB3 Gen 2 transmit pre-shoot multiplier configuration"
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hexmask.long.byte 0x28 0.--7. 1. "PHY_PIPE_USB3_GEN2_POST_CFG0_7_0,USB3 Gen 2 transmit pre-shoot multiplier configuration"
group.long 0xD000++0x27
line.long 0x00 "PHY_PIPE_ISO_TX_LPC_LO__PHY_PIPE_ISO_TX_CTRL_j,PIPE TX control signal isolation register () Offset = D000h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x00 30.--31. "PHY_PIPE_ISO_TX_LPC_LO_15_14,Reserved" "0,1,2,3"
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rbitfld.long 0x00 24.--29. "PHY_PIPE_ISO_TX_LPC_LO_13_8,Current value of pipe_tx_local_tx_preset_coefficients[11:6] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 22.--23. "PHY_PIPE_ISO_TX_LPC_LO_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x00 16.--21. "PHY_PIPE_ISO_TX_LPC_LO_5_0,Current value of pipe_tx_local_tx_preset_coefficients[5:0] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 12.--15. "PHY_PIPE_ISO_TX_CTRL_15_12,Drives pipe_tx_data_k PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 9.--11. "PHY_PIPE_ISO_TX_CTRL_11_9,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "PHY_PIPE_ISO_TX_CTRL_8,Drives pipe_tx_ones_zeros input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x00 5.--7. "PHY_PIPE_ISO_TX_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "PHY_PIPE_ISO_TX_CTRL_4,Drives pipe_tx_elec_idle PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x00 3. "PHY_PIPE_ISO_TX_CTRL_3,Drives pipe_tx_128b_enc_byp PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x00 2. "PHY_PIPE_ISO_TX_CTRL_2,Drives pipe_tx_compliance PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x00 0.--1. "PHY_PIPE_ISO_TX_CTRL_1_0,Drives pipe_tx_pattern PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3"
line.long 0x04 "PHY_PIPE_ISO_TX_DMPH_LO__PHY_PIPE_ISO_TX_LPC_HI_j,PIPE TX local preset coefficients high isolation register () Offset = D004h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x04 30.--31. "PHY_PIPE_ISO_TX_DMPH_LO_15_14,Reserved" "0,1,2,3"
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bitfld.long 0x04 24.--29. "PHY_PIPE_ISO_TX_DMPH_LO_13_8,Drives pipe_tx_deemph[11:6] PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x04 22.--23. "PHY_PIPE_ISO_TX_DMPH_LO_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x04 16.--21. "PHY_PIPE_ISO_TX_DMPH_LO_5_0,Drives pipe_tx_deemph[5:0] PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x04 15. "PHY_PIPE_ISO_TX_LPC_HI_15,Set upon assertion of pipe_tx_local_tx_coeff_vld PHY output for the associated lane" "0,1"
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rbitfld.long 0x04 14. "PHY_PIPE_ISO_TX_LPC_HI_14,Reserved" "0,1"
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bitfld.long 0x04 13. "PHY_PIPE_ISO_TX_LPC_HI_13,Drives pipe_tx_get_local_preset_coef PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x04 8.--12. "PHY_PIPE_ISO_TX_LPC_HI_12_8,Drives pipe_tx_local_preset_index PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x04 6.--7. "PHY_PIPE_ISO_TX_LPC_HI_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x04 0.--5. "PHY_PIPE_ISO_TX_LPC_HI_5_0,Current value of pipe_tx_local_tx_preset_coefficients[17:12] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PHY_PIPE_ISO_TX_FSLF__PHY_PIPE_ISO_TX_DMPH_HI_j,PIPE TX deemphasis isolation register () Offset = D008h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x08 30.--31. "PHY_PIPE_ISO_TX_FSLF_15_14,Reserved" "0,1,2,3"
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rbitfld.long 0x08 24.--29. "PHY_PIPE_ISO_TX_FSLF_13_8,Current value of pipe_tx_local_fs PHY output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x08 22.--23. "PHY_PIPE_ISO_TX_FSLF_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x08 16.--21. "PHY_PIPE_ISO_TX_FSLF_5_0,Current value of pipe_tx_local_lf PHY output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 6.--15. 1. "PHY_PIPE_ISO_TX_DMPH_HI_15_6,Reserved"
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bitfld.long 0x08 0.--5. "PHY_PIPE_ISO_TX_DMPH_HI_5_0,Drives pipe_tx_deemph[17:12] PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "PHY_PIPE_ISO_TX_DATA_HI__PHY_PIPE_ISO_TX_DATA_LO_j,PIPE TX data lower isolation register () Offset = D00Ch + (j * 200h); where j = 0h to 1h"
hexmask.long.word 0x0C 16.--31. 1. "PHY_PIPE_ISO_TX_DATA_HI_15_0,Drives pipe_tx_data[31:16] PHY input for the associated lane when in PHY macro and PMA isolation modes"
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hexmask.long.word 0x0C 0.--15. 1. "PHY_PIPE_ISO_TX_DATA_LO_15_0,Drives pipe_tx_data[15:0] PHY input for the associated lane when in PHY macro and PMA isolation modes"
line.long 0x10 "PHY_PIPE_ISO_RX_EQ_EVAL__PHY_PIPE_ISO_RX_CTRL_j,PIPE RX control signal isolation register () Offset = D010h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x10 29.--31. "PHY_PIPE_ISO_RX_EQ_EVAL_15_13,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 28. "PHY_PIPE_ISO_RX_EQ_EVAL_12,Drives pipe_rx_invalid_request PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x10 27. "PHY_PIPE_ISO_RX_EQ_EVAL_11,pipe_link_eval_dir_change[5:4] bit reversal enable" "0,1"
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bitfld.long 0x10 26. "PHY_PIPE_ISO_RX_EQ_EVAL_10,pipe_link_eval_dir_change[3:2] bit reversal enable" "0,1"
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bitfld.long 0x10 25. "PHY_PIPE_ISO_RX_EQ_EVAL_9,pipe_link_eval_dir_change[1:0] bit reversal enable" "0,1"
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bitfld.long 0x10 24. "PHY_PIPE_ISO_RX_EQ_EVAL_8,Drives pipe_rx_eval PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x10 23. "PHY_PIPE_ISO_RX_EQ_EVAL_7,Reserved" "0,1"
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rbitfld.long 0x10 22. "PHY_PIPE_ISO_RX_EQ_EVAL_6,Captures pipe_phy_status for Rx equalization evaluation PHY output for the associated lane (does not include power state change signaling)" "0,1"
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rbitfld.long 0x10 16.--21. "PHY_PIPE_ISO_RX_EQ_EVAL_5_0,pipe_link_eval_dir_change PHY output for the associated lane (prior to bit reversal logic) upon completion of Rx equalization evaluation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x10 12.--15. "PHY_PIPE_ISO_RX_CTRL_15_12,Current value of pipe_rx_data_k PHY output for the associated lane when PHY_PCS_ISO_RX_CTRL[6] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 10.--11. "PHY_PIPE_ISO_RX_CTRL_11_10,Reserved" "0,1,2,3"
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bitfld.long 0x10 9. "PHY_PIPE_ISO_RX_CTRL_9,Drives pipe_rx_eq_training PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x10 8. "PHY_PIPE_ISO_RX_CTRL_8,Drives pipe_rx_termination PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x10 7. "PHY_PIPE_ISO_RX_CTRL_7,Drives pipe_rx_polarity PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x10 6. "PHY_PIPE_ISO_RX_CTRL_6,Reserved" "0,1"
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rbitfld.long 0x10 5. "PHY_PIPE_ISO_RX_CTRL_5,Current value of pipe_rx_valid PHY output for the associated lane" "0,1"
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rbitfld.long 0x10 4. "PHY_PIPE_ISO_RX_CTRL_4,Current value of pipe_rx_elec_idle PHY output for the associated lane" "0,1"
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rbitfld.long 0x10 3. "PHY_PIPE_ISO_RX_CTRL_3,Captures pipe_align_detect for PHY output for the associated lane" "0,1"
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rbitfld.long 0x10 0.--2. "PHY_PIPE_ISO_RX_CTRL_2_0,Current value of pipe_rx_status PHY output for the associated lane" "0,1,2,3,4,5,6,7"
line.long 0x14 "PHY_ISO_LINK_CTRL__PHY_ISO_LINK_CFG_j,PHY Link configuration isolation register Offset = D014h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x14 31. "PHY_ISO_LINK_CTRL_15,Current value of pma_l{nnnn}_pwr_en_ack PHY output" "0,1"
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bitfld.long 0x14 30. "PHY_ISO_LINK_CTRL_14,Drives pma_l{nnnn}_pwr_en PHY input when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x14 29. "PHY_ISO_LINK_CTRL_13,Current value of phy_l{nnnn}_ack_l1_x PHY output" "0,1"
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bitfld.long 0x14 28. "PHY_ISO_LINK_CTRL_12,Drives phy_l{nnnn}_ent_l1_x PHY input when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 27. "PHY_ISO_LINK_CTRL_11,Drives phy_l{nnnn}_rx_elec_idle_det_en PHY input when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 26. "PHY_ISO_LINK_CTRL_10,Drives phy_l{nnnn}_tx_cmn_mode_en PHY input when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 24.--25. "PHY_ISO_LINK_CTRL_9_8,Drives pipe_l{nnnn}_rate PHY input when in PHY macro and PMA isolation modes" "0,1,2,3"
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rbitfld.long 0x14 23. "PHY_ISO_LINK_CTRL_7,Reserved" "0,1"
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bitfld.long 0x14 20.--22. "PHY_ISO_LINK_CTRL_6_4,Drives pipe_l{nnnn}_powerdown PHY input when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 19. "PHY_ISO_LINK_CTRL_3,Reserved" "0,1"
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bitfld.long 0x14 18. "PHY_ISO_LINK_CTRL_2,Drives pipe_l{nnnn}_tx_det_rx_lpbk PHY input when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x14 17. "PHY_ISO_LINK_CTRL_1,Captures pipe_l{nnnn}_ phy_status for power state change PHY output (does not include Rx equalization signaling)" "0,1"
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bitfld.long 0x14 16. "PHY_ISO_LINK_CTRL_0,Drives phy_l{nnnn}_reset_n PHY input when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 15. "PHY_ISO_LINK_CFG_15,Drives phy_link_cfg_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x14 13.--14. "PHY_ISO_LINK_CFG_14_13,Reserved" "0,1,2,3"
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bitfld.long 0x14 12. "PHY_ISO_LINK_CFG_12,Drives pipe_l{nnnn}_32bit_sel PHY input when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x14 6.--11. "PHY_ISO_LINK_CFG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5. "PHY_ISO_LINK_CFG_5,Drives phy_l{nnnn}_pcie_l1_ss_sel PHY input when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 4. "PHY_ISO_LINK_CFG_4,Drives pipe_l{nnnn}_eb_mode PHY input when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 3. "PHY_ISO_LINK_CFG_3,Drives phy_eth_mode PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 2. "PHY_ISO_LINK_CFG_2,Drives phy_eth_mode_en PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 0.--1. "PHY_ISO_LINK_CFG_1_0,Drives phy_l{nnnn}_mode PHY input when in PHY macro and PMA isolation modes" "0,1,2,3"
line.long 0x18 "PHY_PIPE_ISO_USB_BER_CNT_j,PIPE USB loopback slave BER count register () Offset = D018h + (j * 200h); where j = 0h to 1h"
hexmask.long.byte 0x18 8.--15. 1. "PHY_PIPE_ISO_USB_BER_CNT_15_8,Reserved"
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hexmask.long.byte 0x18 0.--7. 1. "PHY_PIPE_ISO_USB_BER_CNT_7_0,Current value of USB 3.0 loopback slave Bit Error Count from the PCS"
line.long 0x1C "PHY_PIPE_ISO_RX_DATA_HI__PHY_PIPE_ISO_RX_DATA_LO_j,PIPE RX data low isolation register () Offset = D01Ch + (j * 200h); where j = 0h to 1h"
hexmask.long.word 0x1C 16.--31. 1. "PHY_PIPE_ISO_RX_DATA_HI_15_0,Current value of pipe_rx_data[31:16] PHY output for the associated lane"
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hexmask.long.word 0x1C 0.--15. 1. "PHY_PIPE_ISO_RX_DATA_LO_15_0,Current value of pipe_rx_data[15:0] PHY output for the associated lane"
line.long 0x20 "PHY_ETH_ISO_MAC_CLK_DIV__PHY_ETH_ISO_MAC_CLK_CFG_j,Ethernet MAC clock configuration isolation register Offset = D020h + (j * 200h); where j = 0h to 1h"
hexmask.long.word 0x20 23.--31. 1. "PHY_ETH_ISO_MAC_CLK_DIV_15_7,Drives mac_div_sel1 PHY input for the associated lane when in PHY macro and PMA isolation mode"
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hexmask.long.byte 0x20 16.--22. 1. "PHY_ETH_ISO_MAC_CLK_DIV_6_0,Drives mac_div_sel0 PHY input for the associated lane when in PHY macro and PMA isolation mode"
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rbitfld.long 0x20 10.--15. "PHY_ETH_ISO_MAC_CLK_CFG_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 8.--9. "PHY_ETH_ISO_MAC_CLK_CFG_9_8,Drives mac_src_sel PHY input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3"
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rbitfld.long 0x20 6.--7. "PHY_ETH_ISO_MAC_CLK_CFG_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x20 4.--5. "PHY_ETH_ISO_MAC_CLK_CFG_5_4,Drives ovr_src_sel PHY input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3"
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rbitfld.long 0x20 3. "PHY_ETH_ISO_MAC_CLK_CFG_3,Reserved" "0,1"
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bitfld.long 0x20 0.--2. "PHY_ETH_ISO_MAC_CLK_CFG_2_0,Drives ovr_div_sel PHY input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3,4,5,6,7"
line.long 0x24 "PHY_INTERRUPT_STS_j,PHY interrupt status register Offset = D024h + (j * 200h); where j = 0h to 1h"
bitfld.long 0x24 15. "PHY_INTERRUPT_STS_15,State change monitor enable" "0,1"
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rbitfld.long 0x24 11.--14. "PHY_INTERRUPT_STS_14_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 8.--10. "PHY_INTERRUPT_STS_10_8,Next power state/data rate - Only valid when one of the interrupt status bits is set" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 7. "PHY_INTERRUPT_STS_7,Reserved" "0,1"
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rbitfld.long 0x24 4.--6. "PHY_INTERRUPT_STS_6_4,Current power state/data rate - Only valid when one of the interrupt status bits is set" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 2.--3. "PHY_INTERRUPT_STS_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x24 1. "PHY_INTERRUPT_STS_1,Data rate state change interrupt status - Set to 1 upon data rate change timeout" "0,1"
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bitfld.long 0x24 0. "PHY_INTERRUPT_STS_0,Power state change interrupt status - Set to 1 upon power state change timeout" "0,1"
group.long 0xD030++0x0F
line.long 0x00 "PHY_PIPE_ISO_LM_MAC2PHY0__PHY_PIPE_LM_CTRL_STS_j,PHY PIPE lane margining control and status register (#) Offset = D030h + (j * 200h); where j = 0h to 1h"
hexmask.long.byte 0x00 24.--31. 1. "PHY_PIPE_ISO_LM_MAC2PHY0_15_8,When in PHY isolation mode this field provides the data for the 2nd cycle of a MAC-to-PHY register interface operation (for operations that require 2 or more cycle)"
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hexmask.long.byte 0x00 16.--23. 1. "PHY_PIPE_ISO_LM_MAC2PHY0_7_0,When in PHY isolation mode this field provides the data for the 1st cycle of a MAC-to-PHY register interface operation"
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rbitfld.long 0x00 12.--15. "PHY_PIPE_LM_CTRL_STS_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 11. "PHY_PIPE_LM_CTRL_STS_11,Error count saturated flag: When set to 1 the error counter for the associated lane has saturated" "0,1"
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rbitfld.long 0x00 10. "PHY_PIPE_LM_CTRL_STS_10,Sample count saturated flag: When set to 1 the sample counter for the associated lane has saturated" "0,1"
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rbitfld.long 0x00 9. "PHY_PIPE_LM_CTRL_STS_9,Committed write invalid address error: When set to 1 an invalid register address was received on the PIPE MAC-to-PHY register interface for a committed write operation for the associated lane" "0,1"
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rbitfld.long 0x00 8. "PHY_PIPE_LM_CTRL_STS_8,Uncommitted write invalid address error: When set to 1 an invalid register address was received on the PIPE MAC-to-PHY register interface for an uncommitted write operation for the associated lane" "0,1"
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rbitfld.long 0x00 6.--7. "PHY_PIPE_LM_CTRL_STS_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x00 5. "PHY_PIPE_LM_CTRL_STS_5,Lane margining enable" "0,1"
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bitfld.long 0x00 4. "PHY_PIPE_LM_CTRL_STS_4,Lane margining controller soft reset: Soft reset to the associated lane's lane margining controller block (i.e" "0,1"
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bitfld.long 0x00 3. "PHY_PIPE_LM_CTRL_STS_3,Lane margining PMA I/F soft reset: Soft reset to the associated lane's lane margining PMA interface block (i.e. MAC-XPHY)" "0,1"
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bitfld.long 0x00 2. "PHY_PIPE_LM_CTRL_STS_2,Lane margining PIPE Tx I/F soft reset: Soft reset to the associated lane's lane margining PIPE transmit block (i.e. MAC-XPHY)" "0,1"
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bitfld.long 0x00 1. "PHY_PIPE_LM_CTRL_STS_1,Lane margining PIPE Rx I/F soft reset: Soft reset to the associated lane's lane margining PIPE receive block (i.e. MAC-XPHY)" "0,1"
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bitfld.long 0x00 0. "PHY_PIPE_LM_CTRL_STS_0,Lane margining soft reset: Soft reset to the associated lane's lane margining logic" "0,1"
line.long 0x04 "PHY_PIPE_ISO_LM_PHY2MAC0__PHY_PIPE_ISO_LM_MAC2PHY1_j,PHY PIPE lane margining MAC-to-PHY isolation register 1 (#) Offset = D034h + (j * 200h); where j = 0h to 1h"
hexmask.long.byte 0x04 24.--31. 1. "PHY_PIPE_ISO_LM_PHY2MAC0_15_8,Captures the data from a PHY-to-MAC write (committed or uncommitted) operation to address 1"
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hexmask.long.byte 0x04 16.--23. 1. "PHY_PIPE_ISO_LM_PHY2MAC0_7_0,Captures the data from a PHY-to-MAC write (committed or uncommitted) operation to address 0"
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hexmask.long.byte 0x04 9.--15. 1. "PHY_PIPE_ISO_LM_MAC2PHY1_15_9,Reserved"
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bitfld.long 0x04 8. "PHY_PIPE_ISO_LM_MAC2PHY1_8,When in PHY isolation mode write a 1 to this bit to initiate a MAC-to-PHY register interface operation" "0,1"
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hexmask.long.byte 0x04 0.--7. 1. "PHY_PIPE_ISO_LM_MAC2PHY1_7_0,When in PHY isolation mode this field provides the data for the 3rd cycle of a MAC-to-PHY register interface operation"
line.long 0x08 "PHY_PIPE_ISO_LM_PHY2MAC1_j,PHY PIPE lane margining PHY-to-MAC isolation register 1 (#) Offset = D038h + (j * 200h); where j = 0h to 1h"
hexmask.long.byte 0x08 8.--15. 1. "PHY_PIPE_ISO_LM_PHY2MAC1_15_8,Captures the data from a PHY-to-MAC read completion operation"
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hexmask.long.byte 0x08 0.--7. 1. "PHY_PIPE_ISO_LM_PHY2MAC1_7_0,Captures the data from a PHY-to-MAC write (committed or uncommitted) operation to address 2"
line.long 0x0C "PHY_PIPE_ISO_LM_PHY2MAC_STS_j,PHY PIPE lane margining PHY-to-MAC status isolation register 1 (#) Offset = D03Ch + (j * 200h); where j = 0h to 1h"
bitfld.long 0x0C 12.--15. "PHY_PIPE_ISO_LM_PHY2MAC_STS_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 11. "PHY_PIPE_ISO_LM_PHY2MAC_STS_11,Set upon receiving a PHY-to-MAC read completion" "0,1"
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bitfld.long 0x0C 10. "PHY_PIPE_ISO_LM_PHY2MAC_STS_10,Set upon receiving a PHY-to-MAC write acknowledgment" "0,1"
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bitfld.long 0x0C 9. "PHY_PIPE_ISO_LM_PHY2MAC_STS_9,Set upon receiving a PHY-to-MAC committed write to an unsupported address" "0,1"
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bitfld.long 0x0C 8. "PHY_PIPE_ISO_LM_PHY2MAC_STS_8,Reserved" "0,1"
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bitfld.long 0x0C 7. "PHY_PIPE_ISO_LM_PHY2MAC_STS_7,Set upon receiving a PHY-to-MAC committed write to address 2" "0,1"
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bitfld.long 0x0C 6. "PHY_PIPE_ISO_LM_PHY2MAC_STS_6,Set upon receiving a PHY-to-MAC committed write to address 1" "0,1"
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bitfld.long 0x0C 5. "PHY_PIPE_ISO_LM_PHY2MAC_STS_5,Set upon receiving a PHY-to-MAC committed write to address 0" "0,1"
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bitfld.long 0x0C 4. "PHY_PIPE_ISO_LM_PHY2MAC_STS_4,Set upon receiving a PHY-to-MAC uncommitted write to an unsupported address" "0,1"
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bitfld.long 0x0C 3. "PHY_PIPE_ISO_LM_PHY2MAC_STS_3,Reserved" "0,1"
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bitfld.long 0x0C 2. "PHY_PIPE_ISO_LM_PHY2MAC_STS_2,Set upon receiving a PHY-to-MAC uncommitted write to address 2" "0,1"
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bitfld.long 0x0C 1. "PHY_PIPE_ISO_LM_PHY2MAC_STS_1,Set upon receiving a PHY-to-MAC uncommitted write to address 1" "0,1"
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bitfld.long 0x0C 0. "PHY_PIPE_ISO_LM_PHY2MAC_STS_0,Set upon receiving a PHY-to-MAC uncommitted write to address 0" "0,1"
group.long 0xE000++0x03
line.long 0x00 "PHY_PMA_CMN_CTRL,PMA common control register"
bitfld.long 0x00 14.--15. "PHY_PMA_CMN_CTRL_15_14,Drives cmn_psmclk_dig_div PMA input" "0,1,2,3"
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rbitfld.long 0x00 13. "PHY_PMA_CMN_CTRL_13,Current value of cmn_plllc1_disabled PMA output" "0,1"
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rbitfld.long 0x00 12. "PHY_PMA_CMN_CTRL_12,Current value of cmn_plllc_disabled PMA output" "0,1"
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rbitfld.long 0x00 11. "PHY_PMA_CMN_CTRL_11,Current value of cmn_plllc1_ready PMA output" "0,1"
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rbitfld.long 0x00 10. "PHY_PMA_CMN_CTRL_10,Current value of cmn_plllc_ready PMA output" "0,1"
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rbitfld.long 0x00 8.--9. "PHY_PMA_CMN_CTRL_9_8,Reserved" "0,1,2,3"
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bitfld.long 0x00 7. "PHY_PMA_CMN_CTRL_7,Drives cmn_refclk1_rcv_out_en PMA input" "0,1"
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bitfld.long 0x00 6. "PHY_PMA_CMN_CTRL_6,Drives cmn_refclk_rcv_out_en PMA input" "0,1"
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rbitfld.long 0x00 5. "PHY_PMA_CMN_CTRL_5,Current value of cmn_refclk1_active PMA output" "0,1"
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rbitfld.long 0x00 4. "PHY_PMA_CMN_CTRL_4,Current value of cmn_refclk_active PMA output" "0,1"
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rbitfld.long 0x00 3. "PHY_PMA_CMN_CTRL_3,Current value of cmn_plllc1_locked PMA output" "0,1"
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rbitfld.long 0x00 2. "PHY_PMA_CMN_CTRL_2,Current value of cmn_plllc_locked PMA output" "0,1"
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rbitfld.long 0x00 1. "PHY_PMA_CMN_CTRL_1,Current value of cmn_macro_suspend_ack PMA output" "0,1"
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rbitfld.long 0x00 0. "PHY_PMA_CMN_CTRL_0,Current value of cmn_ready PMA output" "0,1"
group.long 0xE008++0x07
line.long 0x00 "PHY_PMA_ISO_CMN_PLLLC_CTRL__PHY_PMA_ISO_CMN_CTRL,PMA common control signal isolation register"
hexmask.long.word 0x00 22.--31. 1. "PHY_PMA_ISO_CMN_PLLLC_CTRL_15_6,Reserved"
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bitfld.long 0x00 21. "PHY_PMA_ISO_CMN_PLLLC_CTRL_5,Drives cmn_plllc1_suspend PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 20. "PHY_PMA_ISO_CMN_PLLLC_CTRL_4,Drives cmn_plllc_suspend PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 19. "PHY_PMA_ISO_CMN_PLLLC_CTRL_3,Drives cmn_plllc1_mode PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 18. "PHY_PMA_ISO_CMN_PLLLC_CTRL_2,Drives cmn_plllc_mode PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 17. "PHY_PMA_ISO_CMN_PLLLC_CTRL_1,Drives cmn_plllc1_en PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 16. "PHY_PMA_ISO_CMN_PLLLC_CTRL_0,Drives cmn_plllc_en PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 14.--15. "PHY_PMA_ISO_CMN_CTRL_15_14,Drives cmn_refclk1_dig_div PMA input when in PHY macro or PMA isolation mode" "0,1,2,3"
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bitfld.long 0x00 12.--13. "PHY_PMA_ISO_CMN_CTRL_13_12,Drives cmn_refclk_dig_div PMA input when in PHY macro or PMA isolation mode" "0,1,2,3"
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bitfld.long 0x00 10.--11. "PHY_PMA_ISO_CMN_CTRL_11_10,Drives cmn_refclk_dig_sel PMA input when in PHY macro or PMA isolation mode" "0,1,2,3"
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rbitfld.long 0x00 9. "PHY_PMA_ISO_CMN_CTRL_9,Current value of cmn_macro_pwr_en_ack PMA output" "0,1"
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bitfld.long 0x00 8. "PHY_PMA_ISO_CMN_CTRL_8,Drives cmn_macro_pwr_en PMA input when in PHY macro and PMA isolation mode" "0,1"
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bitfld.long 0x00 7. "PHY_PMA_ISO_CMN_CTRL_7,Drives cmn_refclk1_sel PMA input when in PHY macro and PMA isolation mode" "0,1"
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bitfld.long 0x00 6. "PHY_PMA_ISO_CMN_CTRL_6,Drives cmn_refclk_sel PMA input when in PHY macro and PMA isolation mode" "0,1"
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bitfld.long 0x00 5. "PHY_PMA_ISO_CMN_CTRL_5,Drives cmn_refclk1_disable PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 4. "PHY_PMA_ISO_CMN_CTRL_4,Drives cmn_refclk_disable PMA input when in PMA isolation mode" "0,1"
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rbitfld.long 0x00 3. "PHY_PMA_ISO_CMN_CTRL_3,Reserved" "0,1"
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bitfld.long 0x00 2. "PHY_PMA_ISO_CMN_CTRL_2,Drives macro_suspend_req PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 1. "PHY_PMA_ISO_CMN_CTRL_1,Drives cmn_macro_en PMA input when in PMA isolation mode" "0,1"
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bitfld.long 0x00 0. "PHY_PMA_ISO_CMN_CTRL_0,Drives cmn_reset_n PMA input when in PMA isolation mode" "0,1"
line.long 0x04 "PHY_PMA_ISO_RESCAL,PMA Isolation resistor calibration code register"
rbitfld.long 0x04 14.--15. "PHY_PMA_ISO_RESCAL_15_14,Reserved" "0,1,2,3"
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rbitfld.long 0x04 8.--13. "PHY_PMA_ISO_RESCAL_13_8,Current value cmn_rescal_code_out PMA output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 7. "PHY_PMA_ISO_RESCAL_7,Drives cmn_rescal_insel PMA input in PMA isolation mode" "0,1"
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rbitfld.long 0x04 6. "PHY_PMA_ISO_RESCAL_6,Reserved" "0,1"
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bitfld.long 0x04 0.--5. "PHY_PMA_ISO_RESCAL_5_0,Drives cmn_rescal_code_in PMA input in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE01C++0x03
line.long 0x00 "PHY_PMA_ISOLATION_CTRL__PHY_PMA_LN_ISOLATION_CTRL,PMA Lane Isolation control register"
bitfld.long 0x00 31. "PHY_PMA_ISOLATION_CTRL_15,PHY/PMA isolation enable (isolation_en) - When set enables isolation (PHY or PMA)" "0,1"
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bitfld.long 0x00 30. "PHY_PMA_ISOLATION_CTRL_14,PHY/PMA common isolation enable (cmn_isolation_en) - When in PHY Macro Isolation Mode the PHY common isolation register(s) are selected" "0,1"
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rbitfld.long 0x00 29. "PHY_PMA_ISOLATION_CTRL_13,Reserved" "0,1"
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bitfld.long 0x00 28. "PHY_PMA_ISOLATION_CTRL_12,PHY/PMA isolation mode select (isolation_mode_sel) - When isolation_en is set this bit selects between PHY isolation mode and PMA isolation mode" "0,1"
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hexmask.long.word 0x00 16.--27. 1. "PHY_PMA_ISOLATION_CTRL_11_0,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "PHY_PMA_LN_ISOLATION_CTRL_15_0,PHY/PMA lane isolation enable (ln_isolation_en) - When in PHY Macro Isolation Mode the selected PHY lane(s) isolation registers are selected"
group.long 0xF000++0x23
line.long 0x00 "PHY_PMA_XCVR_CTRL_j,PMA transceiver control register Offset = F000h + (j * 200h); where j = 0h to 1h"
bitfld.long 0x00 15. "PHY_PMA_XCVR_CTRL_15,Drives rx_termination PMA input for the associated lane when the lane is configured for Ethernet" "0,1"
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rbitfld.long 0x00 14. "PHY_PMA_XCVR_CTRL_14,Reserved" "0,1"
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rbitfld.long 0x00 13. "PHY_PMA_XCVR_CTRL_13,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane" "0,1"
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rbitfld.long 0x00 12. "PHY_PMA_XCVR_CTRL_12,Current value of xcvr_lane_en_ack PMA output for the associated lane" "0,1"
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rbitfld.long 0x00 10.--11. "PHY_PMA_XCVR_CTRL_11_10,Reserved" "0,1,2,3"
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bitfld.long 0x00 9. "PHY_PMA_XCVR_CTRL_9,Drives the tx_bist_hold PMA input for all lanes in the associated link (for the master lane) - synchronized to the Tx data rate clock for the link" "0,1"
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bitfld.long 0x00 8. "PHY_PMA_XCVR_CTRL_8,Drives the tx_differential_invert PMA input for the associated lane" "0,1"
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rbitfld.long 0x00 6.--7. "PHY_PMA_XCVR_CTRL_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x00 5. "PHY_PMA_XCVR_CTRL_5,Current value of ln_plln_locked PMA output for the associated lane" "0,1"
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bitfld.long 0x00 4. "PHY_PMA_XCVR_CTRL_4,Drives rx_rd10_clken PMA input for the associated lane" "0,1"
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rbitfld.long 0x00 3. "PHY_PMA_XCVR_CTRL_3,Current value of rx_bist_status PMA output for the associated lane" "0,1"
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rbitfld.long 0x00 2. "PHY_PMA_XCVR_CTRL_2,Current value of rx_bist_err_toggle PMA output for the associated lane" "0,1"
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rbitfld.long 0x00 1. "PHY_PMA_XCVR_CTRL_1,Current value of rx_bist_sync PMA output for the associated lane" "0,1"
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bitfld.long 0x00 0. "PHY_PMA_XCVR_CTRL_0,Drives the rx_differential_invert PMA input for the associated lane" "0,1"
line.long 0x04 "PHY_PMA_ISO_XCVR_CTRL_j,PMA Isolation Transceiver control register Offset = F004h + (j * 200h); where j = 0h to 1h"
bitfld.long 0x04 31. "PHY_PMA_ISO_XCVR_CTRL_15,Drives tx_high_z PMA input for the associated lane when in PMA isolation mode" "0,1"
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rbitfld.long 0x04 30. "PHY_PMA_ISO_XCVR_CTRL_14,Reserved" "0,1"
newline
bitfld.long 0x04 29. "PHY_PMA_ISO_XCVR_CTRL_13,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x04 28. "PHY_PMA_ISO_XCVR_CTRL_12,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x04 27. "PHY_PMA_ISO_XCVR_CTRL_11,Current value of tx_rcv_detected PMA output for the associated lane when PHY_PMA_ISO_XCVR_CTRL[9] == 1 and PHY_PMA_ISO_XCVR_CTRL[10] == 1" "0,1"
newline
rbitfld.long 0x04 26. "PHY_PMA_ISO_XCVR_CTRL_10,Current value of tx_rcv_detect_done PMA output for the associated lane" "0,1"
newline
bitfld.long 0x04 25. "PHY_PMA_ISO_XCVR_CTRL_9,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x04 24. "PHY_PMA_ISO_XCVR_CTRL_8,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x04 23. "PHY_PMA_ISO_XCVR_CTRL_7,Drives xcvr_pllclk_en PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x04 22. "PHY_PMA_ISO_XCVR_CTRL_6,Reserved" "0,1"
newline
bitfld.long 0x04 21. "PHY_PMA_ISO_XCVR_CTRL_5,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x04 20. "PHY_PMA_ISO_XCVR_CTRL_4,Current value of rx_lfps_detect PMA output for the associated lane" "0,1"
newline
rbitfld.long 0x04 19. "PHY_PMA_ISO_XCVR_CTRL_3,Current value of rx_signal_detect PMA output for the associated lane" "0,1"
newline
rbitfld.long 0x04 18. "PHY_PMA_ISO_XCVR_CTRL_2,Reserved" "0,1"
newline
bitfld.long 0x04 17. "PHY_PMA_ISO_XCVR_CTRL_1,Drives rx_termination PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x04 16. "PHY_PMA_ISO_XCVR_CTRL_0,Drives xcvr_lane_en PMA input for the associated lane when in PMA isolation mode" "0,1"
line.long 0x08 "PHY_PMA_ISO_TX_LPC_HI__PHY_PMA_ISO_TX_LPC_LO_j,PMA Isolation transmitter local preset coefficient register Offset = F008h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x08 31. "PHY_PMA_ISO_TX_LPC_HI_15,Current value of tx_local_preset_coeff_valid PMA output for the associated lane" "0,1"
newline
rbitfld.long 0x08 30. "PHY_PMA_ISO_TX_LPC_HI_14,Reserved" "0,1"
newline
bitfld.long 0x08 29. "PHY_PMA_ISO_TX_LPC_HI_13,Drives tx_get_local_init_coef PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x08 28. "PHY_PMA_ISO_TX_LPC_HI_12,Drives tx_get_local_preset_coef PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x08 24.--27. "PHY_PMA_ISO_TX_LPC_HI_11_8,Drives tx_local_preset_index PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 22.--23. "PHY_PMA_ISO_TX_LPC_HI_7_6,Reserved" "0,1,2,3"
newline
rbitfld.long 0x08 16.--21. "PHY_PMA_ISO_TX_LPC_HI_5_0,Current value of tx_local_tx_preset_coef[17:12] PMA output for the associated lane when (PHY_PMA_ISO_TX_LPC_HI[12] == 1 or PHY_PMA_ISO_TX_LPC_HI[13] == 1) and PHY_PMA_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x08 14.--15. "PHY_PMA_ISO_TX_LPC_LO_15_14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x08 8.--13. "PHY_PMA_ISO_TX_LPC_LO_13_8,Current value of tx_local_tx_preset_coef[11:6] PMA output for the associated lane when (PHY_PMA_ISO_TX_LPC_HI[12] == 1 or PHY_PMA_ISO_TX_LPC_HI[13] == 1) and PHY_PMA_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x08 6.--7. "PHY_PMA_ISO_TX_LPC_LO_7_6,Reserved" "0,1,2,3"
newline
rbitfld.long 0x08 0.--5. "PHY_PMA_ISO_TX_LPC_LO_5_0,Current value of tx_local_tx_preset_coef[5:0] PMA output for the associated lane when (PHY_PMA_ISO_TX_LPC_HI[12] == 1 or PHY_PMA_ISO_TX_LPC_HI[13] == 1) and PHY_PMA_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "PHY_PMA_ISO_TX_DMPH_HI__PHY_PMA_ISO_TX_DMPH_LO_j,PMA TX de-emphasis low isolation register Offset = F00Ch + (j * 200h); where j = 0h to 1h"
hexmask.long.word 0x0C 22.--31. 1. "PHY_PMA_ISO_TX_DMPH_HI_15_6,Reserved"
newline
bitfld.long 0x0C 16.--21. "PHY_PMA_ISO_TX_DMPH_HI_5_0,Drives tx_deemphasis[17:12] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x0C 14.--15. "PHY_PMA_ISO_TX_DMPH_LO_15_14,Reserved" "0,1,2,3"
newline
bitfld.long 0x0C 8.--13. "PHY_PMA_ISO_TX_DMPH_LO_13_8,Drives tx_deemphasis[11:6] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x0C 6.--7. "PHY_PMA_ISO_TX_DMPH_LO_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x0C 0.--5. "PHY_PMA_ISO_TX_DMPH_LO_5_0,Drives tx_deemphasis[5:0] PMA input for the associated lane when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "PHY_PMA_ISO_TX_MGN__PHY_PMA_ISO_TX_FSLF_j,PMA TX FS LF isolation register Offset = F010h + (j * 200h); where j = 0h to 1h"
hexmask.long.byte 0x10 25.--31. 1. "PHY_PMA_ISO_TX_MGN_15_9,Reserved"
newline
bitfld.long 0x10 24. "PHY_PMA_ISO_TX_MGN_8,Drives tx_low_power_swing_en PMA input for the associated lane when in PHY macro and PMA isolation mode" "0,1"
newline
rbitfld.long 0x10 19.--23. "PHY_PMA_ISO_TX_MGN_7_3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--18. "PHY_PMA_ISO_TX_MGN_2_0,Drives tx_vmargin PMA input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 14.--15. "PHY_PMA_ISO_TX_FSLF_15_14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x10 8.--13. "PHY_PMA_ISO_TX_FSLF_13_8,Current value of tx_local_fs PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 6.--7. "PHY_PMA_ISO_TX_FSLF_7_6,Reserved" "0,1,2,3"
newline
rbitfld.long 0x10 0.--5. "PHY_PMA_ISO_TX_FSLF_5_0,Current value of tx_local_lf PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "PHY_PMA_ISO_PWRST_CTRL__PHY_PMA_ISO_LINK_MODE_j,PMA Isolation mode control register Offset = F014h + (j * 200h); where j = 0h to 1h"
bitfld.long 0x14 31. "PHY_PMA_ISO_PWRST_CTRL_15,Drives rx_sig_det_en_ext_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
newline
bitfld.long 0x14 30. "PHY_PMA_ISO_PWRST_CTRL_14,Drives tx_common_mode_en_ext_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x14 24.--29. "PHY_PMA_ISO_PWRST_CTRL_13_8,Current value of xcvr_power_state_ack_ln_{nnnn} PMA output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x14 22.--23. "PHY_PMA_ISO_PWRST_CTRL_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 16.--21. "PHY_PMA_ISO_PWRST_CTRL_5_0,Drives xcvr_power_state_req_ln_{nnnn} PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x14 13.--15. "PHY_PMA_ISO_LINK_MODE_15_13,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 12. "PHY_PMA_ISO_LINK_MODE_12,Drives xcvr_master_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x14 7.--11. "PHY_PMA_ISO_LINK_MODE_11_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 4.--6. "PHY_PMA_ISO_LINK_MODE_6_4,Drives xcvr_standard_mode_ln_{nnnn} PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x14 3. "PHY_PMA_ISO_LINK_MODE_3,Reserved" "0,1"
newline
bitfld.long 0x14 0.--2. "PHY_PMA_ISO_LINK_MODE_2_0,Drives xcvr_data_width_ln_{nnnn} PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7"
line.long 0x18 "PHY_PMA_ISO_RX_EQ_CTRL_j,PMA RX equalization control isolation register Offset = F018h + (j * 200h); where j = 0h to 1h"
rbitfld.long 0x18 30.--31. "PHY_PMA_ISO_RX_EQ_CTRL_15_14,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 29. "PHY_PMA_ISO_RX_EQ_CTRL_13,Drives rx_eq_training_data_valid PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x18 28. "PHY_PMA_ISO_RX_EQ_CTRL_12,Drives rx_eq_training PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x18 27. "PHY_PMA_ISO_RX_EQ_CTRL_11,Drives rx_eq_eval_cnt_rst PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x18 26. "PHY_PMA_ISO_RX_EQ_CTRL_10,Reserved" "0,1"
newline
rbitfld.long 0x18 20.--25. "PHY_PMA_ISO_RX_EQ_CTRL_9_4,Current value of rx_link_eval_fb_dir_change PMA output for the associated lane when PHY_PMA_ISO_RX_EQ_CTRL[0] == 1 and PHY_PMA_ISO_RX_EQ_CTRL[1] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x18 19. "PHY_PMA_ISO_RX_EQ_CTRL_3,Current value of rx_eq_eval_complete PMA output for the associated lane when PHY_PMA_ISO_RX_EQ_CTRL[0] == 1 and PHY_PMA_ISO_RX_EQ_CTRL[1] == 1" "0,1"
newline
bitfld.long 0x18 18. "PHY_PMA_ISO_RX_EQ_CTRL_2,Drives rx_invalid_request PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x18 17. "PHY_PMA_ISO_RX_EQ_CTRL_1,Current value of rx_eq_eval_status PMA output for the associated lane" "0,1"
newline
bitfld.long 0x18 16. "PHY_PMA_ISO_RX_EQ_CTRL_0,Drives rx_eq_eval PMA input for the associated lane when in PMA isolation mode" "0,1"
line.long 0x1C "PHY_PMA_ISO_DATA_HI__PHY_PMA_ISO_DATA_LO_j,PMA low data isolation register Offset = F01Ch + (j * 200h); where j = 0h to 1h"
hexmask.long.word 0x1C 16.--31. 1. "PHY_PMA_ISO_DATA_HI_15_0,Current value of rx_rd[31:16] PMA output for the current lane"
newline
hexmask.long.word 0x1C 0.--15. 1. "PHY_PMA_ISO_DATA_LO_15_0,Current value of rx_rd[15:0] PMA output for the current lane"
line.long 0x20 "PHY_PMA_ISO_LN_MRGN_RESULT__PHY_PMA_ISO_LN_MRGN_CTRL_j,PMA RX lane margining control isolation register Offset = F020h + (j * 200h); where j = 0h to 1h"
hexmask.long.word 0x20 22.--31. 1. "PHY_PMA_ISO_LN_MRGN_RESULT_15_6,Reserved"
newline
rbitfld.long 0x20 16.--21. "PHY_PMA_ISO_LN_MRGN_RESULT_5_0,Captures rx_mrgn_errcnt PMA output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x20 15. "PHY_PMA_ISO_LN_MRGN_CTRL_15,Reserved" "0,1"
newline
hexmask.long.byte 0x20 8.--14. 1. "PHY_PMA_ISO_LN_MRGN_CTRL_14_8,Drives rx_mrgn_offset PMA input for the associated lane when in PMA isolation mode"
newline
rbitfld.long 0x20 6.--7. "PHY_PMA_ISO_LN_MRGN_CTRL_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x20 4.--5. "PHY_PMA_ISO_LN_MRGN_CTRL_5_4,Drives rx_mrgn_dir PMA input for the associated lane when in PMA isolation mode" "0,1,2,3"
newline
rbitfld.long 0x20 2.--3. "PHY_PMA_ISO_LN_MRGN_CTRL_3_2,Reserved" "0,1,2,3"
newline
rbitfld.long 0x20 1. "PHY_PMA_ISO_LN_MRGN_CTRL_1,Captures rx_mrgn_valid PMA output for the associated lane" "0,1"
newline
bitfld.long 0x20 0. "PHY_PMA_ISO_LN_MRGN_CTRL_0,Drives rx_mrgn_req PMA input for the associated lane when in PMA isolation mode" "0,1"
tree.end
repeat.end
tree.end
tree "_4_L_SerDes"
tree "SERDES_10G0"
base ad:0x5050000
rgroup.long 0x00++0x0B
line.long 0x00 "CMN_PID_TYPE,Product type ID register"
hexmask.long.word 0x00 0.--15. 1. "CMN_PID_TYPE_15_0,Product type : This field contains the ASCII codes that represent the product type sd for SerDes"
line.long 0x04 "CMN_PID_NUM,Product number ID register"
hexmask.long.word 0x04 16.--31. 1. "CMN_PID_NUM_15_0,Product number : This field contains the binary coded decimal numbers that represent the product number"
line.long 0x08 "CMN_PID_REV,Product revision ID register"
hexmask.long.word 0x08 0.--15. 1. "CMN_PID_REV_15_0,Product revision : This field contains the binary coded decimal numbers that represent the product revision"
rgroup.long 0x10++0x0B
line.long 0x00 "CMN_PID_NODE__CMN_PID_MFG,Product technology manufacturer ID register"
hexmask.long.word 0x00 16.--31. 1. "CMN_PID_NODE_15_0,Product technology process node : This field contains the binary coded decimal numbers that represent the product technology node"
hexmask.long.word 0x00 0.--15. 1. "CMN_PID_MFG_15_0,Product technology manufacturer : This field contains the ASCII codes that represent the product technology manufacturer t for TSMC"
line.long 0x04 "CMN_PID_FLV1__CMN_PID_FLV0,Product technology process flavor ID register 0"
hexmask.long.word 0x04 16.--31. 1. "CMN_PID_FLV1_15_0,Product technology flavor : This field contains the ASCII codes that represent the second two characters of the product technology flavor"
hexmask.long.word 0x04 0.--15. 1. "CMN_PID_FLV0_15_0,Product technology flavor : This field contains the ASCII codes that represent the first two characters of the product technology flavor"
line.long 0x08 "CMN_PID_LANES__CMN_PID_IOV,Product I/O voltage ID register"
hexmask.long.byte 0x08 24.--31. 1. "CMN_PID_LANES_15_8,Product SerDes lanes left of common : This field contains the binary coded decimal numbers that represent the number of lanes implemented in this SerDes product on the left side of the common module"
hexmask.long.byte 0x08 16.--23. 1. "CMN_PID_LANES_7_0,Product SerDes lanes right of common : This field contains the binary coded decimal numbers that represent the number of lanes implemented in this SerDes product on the right side of the common module"
newline
hexmask.long.word 0x08 0.--15. 1. "CMN_PID_IOV_15_0,Product I/O voltage : This field contains the binary coded decimal numbers that represent the product I/O voltage"
rgroup.long 0x20++0x0B
line.long 0x00 "CMN_PID_METAL1__CMN_PID_METAL0,Product metal layers ID register 0"
bitfld.long 0x00 28.--31. "CMN_PID_METAL1_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "CMN_PID_METAL1_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "CMN_PID_METAL1_7_4,Product xy metal layers : This field contains the binary coded decimal number that represent the number of xy metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "CMN_PID_METAL1_3_0,Product xe metal layers : This field contains the binary coded decimal number that represent the number of xe metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "CMN_PID_METAL0_15_12,Product xd metal layers : This field contains the binary coded decimal number that represent the number of xd metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CMN_PID_METAL0_11_8,Product xc metal layers : This field contains the binary coded decimal number that represent the number of xc metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "CMN_PID_METAL0_7_4,Product xa metal layers : This field contains the binary coded decimal number that represent the number of xa metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CMN_PID_METAL0_3_0,Product x metal layers : This field contains the binary coded decimal number that represent the number of x metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CMN_PID_METAL3__CMN_PID_METAL2,Product metal layers ID register 2"
bitfld.long 0x04 28.--31. "CMN_PID_METAL3_15_12,Product yz metal layers : This field contains the binary coded decimal number that represent the number of yz metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 24.--27. "CMN_PID_METAL3_11_8,Product u metal layers : This field contains the binary coded decimal number that represent the number of u metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 20.--23. "CMN_PID_METAL3_7_4,Product r metal layers : This field contains the binary coded decimal number that represent the number of r metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 16.--19. "CMN_PID_METAL3_3_0,Product z metal layers : This field contains the binary coded decimal number that represent the number of z metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 12.--15. "CMN_PID_METAL2_15_12,Product yz metal layers : This field contains the binary coded decimal number that represent the number of yz metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--11. "CMN_PID_METAL2_11_8,Product yy metal layers : This field contains the binary coded decimal number that represent the number of yy metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. "CMN_PID_METAL2_7_4,Product ya metal layers : This field contains the binary coded decimal number that represent the number of ya metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "CMN_PID_METAL2_3_0,Product y metal layers : This field contains the binary coded decimal number that represent the number of y metal layers used for this product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CMN_PID_METALD,Product metal layer direction ID register"
bitfld.long 0x08 15. "CMN_PID_METALD_15,Reserved" "0,1"
bitfld.long 0x08 14. "CMN_PID_METALD_14,Reserved" "0,1"
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bitfld.long 0x08 13. "CMN_PID_METALD_13,Reserved" "0,1"
bitfld.long 0x08 12. "CMN_PID_METALD_12,Reserved" "0,1"
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bitfld.long 0x08 11. "CMN_PID_METALD_11,Metal 11 direction (when used)" "0,1"
bitfld.long 0x08 10. "CMN_PID_METALD_10,Metal 10 direction (when used)" "0,1"
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bitfld.long 0x08 9. "CMN_PID_METALD_9,Metal 9 direction (when used)" "0,1"
bitfld.long 0x08 8. "CMN_PID_METALD_8,Metal 8 direction" "0,1"
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bitfld.long 0x08 7. "CMN_PID_METALD_7,Metal 7 direction" "0,1"
bitfld.long 0x08 6. "CMN_PID_METALD_6,Metal 6 direction" "0,1"
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bitfld.long 0x08 5. "CMN_PID_METALD_5,Metal 5 direction" "0,1"
bitfld.long 0x08 4. "CMN_PID_METALD_4,Metal 4 direction" "0,1"
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bitfld.long 0x08 3. "CMN_PID_METALD_3,Metal 3 direction" "0,1"
bitfld.long 0x08 2. "CMN_PID_METALD_2,Metal 2 direction" "0,1"
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bitfld.long 0x08 1. "CMN_PID_METALD_1,Metal 1 direction" "0,1"
bitfld.long 0x08 0. "CMN_PID_METALD_0,Metal 0 direction : This layer does not have a direction associated with it" "0,1"
group.long 0x40++0x07
line.long 0x00 "CMN_SSM_BANDGAP_TMR__CMN_SSM_SM_CTRL,Startup state machine control register"
hexmask.long.word 0x00 21.--31. 1. "CMN_SSM_BANDGAP_TMR_15_5,Reserved"
bitfld.long 0x00 16.--20. "CMN_SSM_BANDGAP_TMR_4_0,Bandgap enable state timer value : Value used for the timer when the startup state machine is in the bandgap enable state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "CMN_SSM_SM_CTRL_15_8,Reserved"
bitfld.long 0x00 7. "CMN_SSM_SM_CTRL_7,Bandgap enable override enable : When active (1'b1) the bandgap enable override bit in this register will drive the ssmda_bandgap_en pin from the SSM directly" "0,1"
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bitfld.long 0x00 6. "CMN_SSM_SM_CTRL_6,Bandgap enable override : When enabled by the bandgap enable override enable bit in this register this bit will drive the ssmda_bandgap_en pin from the SSM directly" "0,1"
bitfld.long 0x00 5. "CMN_SSM_SM_CTRL_5,Bias enable override enable : When active (1'b1) the bias enable override bit in this register will drive the ssmda_bias_en pin from the SSM directly" "0,1"
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bitfld.long 0x00 4. "CMN_SSM_SM_CTRL_4,Bias enable override : When enabled by the bias enable override enable bit in this register this bit will drive the ssmda_bias_en pin from the SSM directly" "0,1"
rbitfld.long 0x00 2.--3. "CMN_SSM_SM_CTRL_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x00 1. "CMN_SSM_SM_CTRL_1,Skip post bandgap enable re-calibration : When this bit is active (1'b1) the post bandgap enable calibration state will be skipped if it was previously run unless the macro is disabled or reset" "0,1"
bitfld.long 0x00 0. "CMN_SSM_SM_CTRL_0,Skip auto re-calibration : When this bit is active (1'b1) the auto calibration state will be skipped if it was previously run unless the macro is disabled or reset" "0,1"
line.long 0x04 "CMN_SSM_BIAS_TMR,Bias enable timer register"
hexmask.long.word 0x04 7.--15. 1. "CMN_SSM_BIAS_TMR_15_7,Reserved"
hexmask.long.byte 0x04 0.--6. 1. "CMN_SSM_BIAS_TMR_6_0,Bias enable state timer value : Value used for the timer when the startup state machine is in the bias enable state"
group.long 0x4C++0x23
line.long 0x00 "CMN_SSM_USER_DEF_CTRL,Startup state machine user defined control register"
hexmask.long.byte 0x00 24.--31. 1. "CMN_SSM_USER_DEF_CTRL_15_8,Reserved"
bitfld.long 0x00 18.--23. "CMN_SSM_USER_DEF_CTRL_7_2,Reserved - spare" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 17. "CMN_SSM_USER_DEF_CTRL_1,Force SSM gated clock on: Setting this bit to 1'b1 will force the SSM gated clock on independent of the internal SSM state machine clock gate controls" "0,1"
bitfld.long 0x00 16. "CMN_SSM_USER_DEF_CTRL_0,Bandgap enable hold enable: This bit enables the bandgap enable hold function which holds the bandgap enable active in the common suspend state until the signal detect function is switched off" "0,1"
line.long 0x04 "CMN_PLLSM0_PLLEN_TMR__CMN_PLLSM0_SM_CTRL,PLL 0 control state machine control register"
hexmask.long.word 0x04 20.--31. 1. "CMN_PLLSM0_PLLEN_TMR_15_4,Reserved"
bitfld.long 0x04 16.--19. "CMN_PLLSM0_PLLEN_TMR_3_0,PLL enable state timer value : Value used for the timer when the startup state machine is in the PLL enable state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 10.--15. "CMN_PLLSM0_SM_CTRL_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "CMN_PLLSM0_SM_CTRL_9,PLL enable override enable : When active (1'b1) the PLL enable override bit in this register will drive the pllsmda_pll_en pin from the PLLSM directly" "0,1"
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bitfld.long 0x04 8. "CMN_PLLSM0_SM_CTRL_8,PLL enable override : When enabled by the PLL enable override enable bit in this register this bit will drive the pllsmda_pll_en pin from the PLLSM directly" "0,1"
bitfld.long 0x04 7. "CMN_PLLSM0_SM_CTRL_7,PLL reset override enable : When active (1'b1) the PLL reset override bit in this register will drive" "0,1"
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bitfld.long 0x04 6. "CMN_PLLSM0_SM_CTRL_6,PLL reset override : When enabled by the PLL reset override enable bit in this register this bit will drive the pllsmda_pll_rst_n pin from the PLLSM directly" "0,1"
bitfld.long 0x04 5. "CMN_PLLSM0_SM_CTRL_5,PLL pre charge override enable : When active (1'b1) the PLL pre charge override bit in this register will drive the pllsmda_pll_pre_charge pin from the PLLSM directly" "0,1"
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bitfld.long 0x04 4. "CMN_PLLSM0_SM_CTRL_4,PLL pre charge override : When enabled by the PLL pre charge override enable bit in this register this bit will drive the pllsmda_pll_pre_charge pin from the PLLSM directly" "0,1"
rbitfld.long 0x04 1.--3. "CMN_PLLSM0_SM_CTRL_3_1,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0. "CMN_PLLSM0_SM_CTRL_0,Skip PLL re-calibration : When this bit is active (1'b1) the PLL calibration state will be skipped if it was previously run unless the PLL is disabled or resetting the state machine" "0,1"
line.long 0x08 "CMN_PLLSM0_PLLVREF_TMR__CMN_PLLSM0_PLLPRE_TMR,PLL 0 pre-charge timer register"
hexmask.long.word 0x08 20.--31. 1. "CMN_PLLSM0_PLLVREF_TMR_15_4,Reserved"
bitfld.long 0x08 16.--19. "CMN_PLLSM0_PLLVREF_TMR_3_0,PLL VREF delay state timer value : Value used for the timer when the startup state machine is in the PLL VREF delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "CMN_PLLSM0_PLLPRE_TMR_15_8,Reserved"
hexmask.long.byte 0x08 0.--7. 1. "CMN_PLLSM0_PLLPRE_TMR_7_0,PLL pre-charge state timer value : Value used for the timer when the startup state machine is in the PLL pre-charge state"
line.long 0x0C "CMN_PLLSM0_PLLCLKDIS_TMR__CMN_PLLSM0_PLLLOCK_TMR,PLL 0 lock delay timer register"
hexmask.long.word 0x0C 18.--31. 1. "CMN_PLLSM0_PLLCLKDIS_TMR_15_2,Reserved"
bitfld.long 0x0C 16.--17. "CMN_PLLSM0_PLLCLKDIS_TMR_1_0,PLL clock disable delay state timer value : Value used for the timer when the startup state machine is in the PLL clock disable delay state" "0,1,2,3"
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rbitfld.long 0x0C 10.--15. "CMN_PLLSM0_PLLLOCK_TMR_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "CMN_PLLSM0_PLLLOCK_TMR_9_0,PLL lock delay state timer value : Value used for the timer when the startup state machine is in the PLL lock delay state"
line.long 0x10 "CMN_PLLSM0_USER_DEF_CTRL,PLL 0 control state machine user defined control register"
hexmask.long.byte 0x10 24.--31. 1. "CMN_PLLSM0_USER_DEF_CTRL_15_8,Reserved"
hexmask.long.byte 0x10 17.--23. 1. "CMN_PLLSM0_USER_DEF_CTRL_7_1,Reserved - spare"
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bitfld.long 0x10 16. "CMN_PLLSM0_USER_DEF_CTRL_0,PLL lock override: When active (1'b1) this bit will force the PLL lock indication active" "0,1"
line.long 0x14 "CMN_PLLSM1_PLLEN_TMR__CMN_PLLSM1_SM_CTRL,PLL 1 control state machine control register"
hexmask.long.word 0x14 20.--31. 1. "CMN_PLLSM1_PLLEN_TMR_15_4,Reserved"
bitfld.long 0x14 16.--19. "CMN_PLLSM1_PLLEN_TMR_3_0,PLL enable state timer value : Value used for the timer when the startup state machine is in the PLL enable state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 10.--15. "CMN_PLLSM1_SM_CTRL_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 9. "CMN_PLLSM1_SM_CTRL_9,PLL enable override enable : When active (1'b1) the PLL enable override bit in this register will drive the pllsmda_pll_en pin from the PLLSM directly" "0,1"
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bitfld.long 0x14 8. "CMN_PLLSM1_SM_CTRL_8,PLL enable override : When enabled by the PLL enable override enable bit in this register this bit will drive the pllsmda_pll_en pin from the PLLSM directly" "0,1"
bitfld.long 0x14 7. "CMN_PLLSM1_SM_CTRL_7,PLL reset override enable : When active (1'b1) the PLL reset override bit in this register will drive" "0,1"
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bitfld.long 0x14 6. "CMN_PLLSM1_SM_CTRL_6,PLL reset override : When enabled by the PLL reset override enable bit in this register this bit will drive the pllsmda_pll_rst_n pin from the PLLSM directly" "0,1"
bitfld.long 0x14 5. "CMN_PLLSM1_SM_CTRL_5,PLL pre charge override enable : When active (1'b1) the PLL pre charge override bit in this register will drive the pllsmda_pll_pre_charge pin from the PLLSM directly" "0,1"
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bitfld.long 0x14 4. "CMN_PLLSM1_SM_CTRL_4,PLL pre charge override : When enabled by the PLL pre charge override enable bit in this register this bit will drive the pllsmda_pll_pre_charge pin from the PLLSM directly" "0,1"
rbitfld.long 0x14 1.--3. "CMN_PLLSM1_SM_CTRL_3_1,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 0. "CMN_PLLSM1_SM_CTRL_0,Skip PLL re-calibration : When this bit is active (1'b1) the PLL calibration state will be skipped if it was previously run unless the PLL is disabled or resetting the state machine" "0,1"
line.long 0x18 "CMN_PLLSM1_PLLVREF_TMR__CMN_PLLSM1_PLLPRE_TMR,PLL 1 pre-charge timer register"
hexmask.long.word 0x18 20.--31. 1. "CMN_PLLSM1_PLLVREF_TMR_15_4,Reserved"
bitfld.long 0x18 16.--19. "CMN_PLLSM1_PLLVREF_TMR_3_0,PLL VREF delay state timer value : Value used for the timer when the startup state machine is in the PLL VREF delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "CMN_PLLSM1_PLLPRE_TMR_15_8,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "CMN_PLLSM1_PLLPRE_TMR_7_0,PLL pre-charge state timer value : Value used for the timer when the startup state machine is in the PLL pre-charge state"
line.long 0x1C "CMN_PLLSM1_PLLCLKDIS_TMR__CMN_PLLSM1_PLLLOCK_TMR,PLL 1 lock delay timer register"
hexmask.long.word 0x1C 18.--31. 1. "CMN_PLLSM1_PLLCLKDIS_TMR_15_2,Reserved"
bitfld.long 0x1C 16.--17. "CMN_PLLSM1_PLLCLKDIS_TMR_1_0,PLL clock disable delay state timer value : Value used for the timer when the startup state machine is in the PLL clock disable delay state" "0,1,2,3"
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rbitfld.long 0x1C 10.--15. "CMN_PLLSM1_PLLLOCK_TMR_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x1C 0.--9. 1. "CMN_PLLSM1_PLLLOCK_TMR_9_0,PLL lock delay state timer value : Value used for the timer when the startup state machine is in the PLL lock delay state"
line.long 0x20 "CMN_PLLSM1_USER_DEF_CTRL,PLL 1 control state machine user defined control register"
hexmask.long.byte 0x20 24.--31. 1. "CMN_PLLSM1_USER_DEF_CTRL_15_8,Reserved"
hexmask.long.byte 0x20 17.--23. 1. "CMN_PLLSM1_USER_DEF_CTRL_7_1,Reserved - spare"
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bitfld.long 0x20 16. "CMN_PLLSM1_USER_DEF_CTRL_0,PLL lock override: When active (1'b1) this bit will force the PLL lock indication active" "0,1"
group.long 0x80++0x23
line.long 0x00 "CMN_CDIAG_CDB_PWRI_OVRD__CMN_CDIAG_PWRI_TMR,Common power island control timer register"
bitfld.long 0x00 31. "CMN_CDIAG_CDB_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x00 30. "CMN_CDIAG_CDB_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1"
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rbitfld.long 0x00 28.--29. "CMN_CDIAG_CDB_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x00 27. "CMN_CDIAG_CDB_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x00 26. "CMN_CDIAG_CDB_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x00 25. "CMN_CDIAG_CDB_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x00 24. "CMN_CDIAG_CDB_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "CMN_CDIAG_CDB_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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rbitfld.long 0x00 11.--15. "CMN_CDIAG_PWRI_TMR_15_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "CMN_CDIAG_PWRI_TMR_10_8,Power enable phase 2 timer value: This specifies the number of reference clock cycles the power island control state machines in common will wait in the power phase 2 enable states in order to allow enough time for the second.." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3.--7. "CMN_CDIAG_PWRI_TMR_7_3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "CMN_CDIAG_PWRI_TMR_2_0,Power enable phase 1 timer value: This specifies the number of reference clock cycles the power island control state machines in common will wait in the power phase 1 enable states in order to allow enough time for the first phase.." "0,1,2,3,4,5,6,7"
line.long 0x04 "CMN_CDIAG_PLLC_PWRI_OVRD__CMN_CDIAG_CDB_PWRI_STAT,Common CDB power island control status register"
bitfld.long 0x04 31. "CMN_CDIAG_PLLC_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x04 30. "CMN_CDIAG_PLLC_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1"
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rbitfld.long 0x04 28.--29. "CMN_CDIAG_PLLC_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x04 27. "CMN_CDIAG_PLLC_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x04 26. "CMN_CDIAG_PLLC_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x04 25. "CMN_CDIAG_PLLC_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x04 24. "CMN_CDIAG_PLLC_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x04 16.--23. 1. "CMN_CDIAG_PLLC_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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hexmask.long.byte 0x04 8.--15. 1. "CMN_CDIAG_CDB_PWRI_STAT_15_8,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "CMN_CDIAG_CDB_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x08 "CMN_CDIAG_CCAL_PWRI_OVRD__CMN_CDIAG_PLLC_PWRI_STAT,Common PLL controller power island control status register"
bitfld.long 0x08 31. "CMN_CDIAG_CCAL_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x08 30. "CMN_CDIAG_CCAL_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1"
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rbitfld.long 0x08 28.--29. "CMN_CDIAG_CCAL_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x08 27. "CMN_CDIAG_CCAL_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x08 26. "CMN_CDIAG_CCAL_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x08 25. "CMN_CDIAG_CCAL_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x08 24. "CMN_CDIAG_CCAL_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CMN_CDIAG_CCAL_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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hexmask.long.byte 0x08 8.--15. 1. "CMN_CDIAG_PLLC_PWRI_STAT_15_8,Reserved"
hexmask.long.byte 0x08 0.--7. 1. "CMN_CDIAG_PLLC_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x0C "CMN_CDIAG_XCVRC_PWRI_OVRD__CMN_CDIAG_CCAL_PWRI_STAT,Common common calibration power island control status register"
bitfld.long 0x0C 31. "CMN_CDIAG_XCVRC_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x0C 30. "CMN_CDIAG_XCVRC_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control.." "0,1"
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rbitfld.long 0x0C 28.--29. "CMN_CDIAG_XCVRC_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x0C 27. "CMN_CDIAG_XCVRC_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x0C 26. "CMN_CDIAG_XCVRC_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x0C 25. "CMN_CDIAG_XCVRC_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x0C 24. "CMN_CDIAG_XCVRC_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x0C 16.--23. 1. "CMN_CDIAG_XCVRC_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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hexmask.long.byte 0x0C 8.--15. 1. "CMN_CDIAG_CCAL_PWRI_STAT_15_8,Reserved"
hexmask.long.byte 0x0C 0.--7. 1. "CMN_CDIAG_CCAL_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x10 "CMN_CDIAG_DIAG_PWRI_OVRD__CMN_CDIAG_XCVRC_PWRI_STAT,Common transceiver controller power island control status register"
bitfld.long 0x10 31. "CMN_CDIAG_DIAG_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x10 30. "CMN_CDIAG_DIAG_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1"
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rbitfld.long 0x10 28.--29. "CMN_CDIAG_DIAG_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x10 27. "CMN_CDIAG_DIAG_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x10 26. "CMN_CDIAG_DIAG_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x10 25. "CMN_CDIAG_DIAG_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x10 24. "CMN_CDIAG_DIAG_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x10 16.--23. 1. "CMN_CDIAG_DIAG_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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hexmask.long.byte 0x10 8.--15. 1. "CMN_CDIAG_XCVRC_PWRI_STAT_15_8,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "CMN_CDIAG_XCVRC_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x14 "CMN_CDIAG_PRATECLK_CTRL__CMN_CDIAG_DIAG_PWRI_STAT,Common diagnostic power island control status register"
hexmask.long.word 0x14 18.--31. 1. "CMN_CDIAG_PRATECLK_CTRL_15_2,Reserved"
bitfld.long 0x14 17. "CMN_CDIAG_PRATECLK_CTRL_1,Common PLL 1 full rate and data rate source clock select: Selects the PLL source clock to use when generating the cmn_pll1_clk_fullrt cmn_pll1_clk_datart0 and cmn_pll1_clk_datart1 clocks" "0,1"
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bitfld.long 0x14 16. "CMN_CDIAG_PRATECLK_CTRL_0,Common PLL 0 full rate and data rate source clock select: Selects the PLL source clock to use when generating the cmn_pll0_clk_fullrt cmn_pll0_clk_datart0 and cmn_pll0_clk_datart1 clocks" "0,1"
hexmask.long.byte 0x14 8.--15. 1. "CMN_CDIAG_DIAG_PWRI_STAT_15_8,Reserved"
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hexmask.long.byte 0x14 0.--7. 1. "CMN_CDIAG_DIAG_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x18 "CMN_CDIAG_REFCLK_TEST__CMN_CDIAG_REFCLK_OVRD,Reference clock receiver override register"
rbitfld.long 0x18 26.--31. "CMN_CDIAG_REFCLK_TEST_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x18 24.--25. "CMN_CDIAG_REFCLK_TEST_9_8,Reserved - spare" "0,1,2,3"
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rbitfld.long 0x18 22.--23. "CMN_CDIAG_REFCLK_TEST_7_6,Reserved" "0,1,2,3"
bitfld.long 0x18 21. "CMN_CDIAG_REFCLK_TEST_5,Reference clock driver 0 test mode enable: Enables the reference clock driver DC test mode by controlling the cmnda_ref_clk0_drv_test_en signal going into the analog" "0,1"
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bitfld.long 0x18 20. "CMN_CDIAG_REFCLK_TEST_4,Reference clock driver 0 test mode value: When enabled by the reference clock driver 0 test mode enable bit in this register the value in this bit will be driven by the reference clock driver by controlling the.." "0,1"
rbitfld.long 0x18 19. "CMN_CDIAG_REFCLK_TEST_3,Reserved" "0,1"
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bitfld.long 0x18 18. "CMN_CDIAG_REFCLK_TEST_2,Reference clock receiver test mode enable: Enables the reference clock receiver DC test mode by controlling the cmnda_ref_clk_rcv_test_en signal going into the analog" "0,1"
rbitfld.long 0x18 17. "CMN_CDIAG_REFCLK_TEST_1,Reference clock receiver test mode PLL value: When enabled by the reference clock receiver test mode enable bit in this register the value in this bit will be the value present on the PLL reference clock receiver" "0,1"
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rbitfld.long 0x18 16. "CMN_CDIAG_REFCLK_TEST_0,Reference clock receiver test mode digital value: When enabled by the reference clock receiver test mode enable bit in this register the value in this bit will be the value present on the digital reference clock receiver" "0,1"
rbitfld.long 0x18 13.--15. "CMN_CDIAG_REFCLK_OVRD_15_13,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 12. "CMN_CDIAG_REFCLK_OVRD_12,Derived reference clock source select: Selects which PLL is the source for the derived reference clock by driving the cmnda_ref_clk_der_src_sel signal to the analog" "0,1"
rbitfld.long 0x18 10.--11. "CMN_CDIAG_REFCLK_OVRD_11_10,Reserved" "0,1,2,3"
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bitfld.long 0x18 8.--9. "CMN_CDIAG_REFCLK_OVRD_9_8,Digital reference clock receiver hysteresis adjust: Control the amount of hysteresis used for the digital reference clock receiver by driving the cmnda_ref_clk_dig_hyst_adj signal to the analog" "0,1,2,3"
rbitfld.long 0x18 7. "CMN_CDIAG_REFCLK_OVRD_7,Reserved" "0,1"
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bitfld.long 0x18 6. "CMN_CDIAG_REFCLK_OVRD_6,Analog reference clock enable override: This bit can be used to force the cmnda_ref_clk_en signal going to the analog to the active state" "0,1"
bitfld.long 0x18 5. "CMN_CDIAG_REFCLK_OVRD_5,Reference clock AC coupling cap bypass: Controls the bypassing of the AC coupling caps in the differential receiver" "0,1"
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bitfld.long 0x18 4. "CMN_CDIAG_REFCLK_OVRD_4,Derived reference clock enable: Enables the derived reference clock function by driving the cmnda_ref_clk_der_en signal to the analog" "0,1"
bitfld.long 0x18 2.--3. "CMN_CDIAG_REFCLK_OVRD_3_2,Reference clock high pass filter control: Controls the cutoff frequency of the high pass filter in the reference clock receiver input" "0,1,2,3"
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rbitfld.long 0x18 1. "CMN_CDIAG_REFCLK_OVRD_1,Reserved" "0,1"
bitfld.long 0x18 0. "CMN_CDIAG_REFCLK_OVRD_0,Reference clock receiver circuit clock control" "0,1"
line.long 0x1C "CMN_CDIAG_SDOSC_CTRL__CMN_CDIAG_PSMCLK_CTRL,Power state machine clock receiver control register"
hexmask.long.word 0x1C 18.--31. 1. "CMN_CDIAG_SDOSC_CTRL_15_2,Reserved"
bitfld.long 0x1C 17. "CMN_CDIAG_SDOSC_CTRL_1,Oscillator Enable Override Enable: This bit enables the oscillator enable override bit in this register to directly control the signal detect oscillator" "0,1"
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bitfld.long 0x1C 16. "CMN_CDIAG_SDOSC_CTRL_0,Oscillator Enable Override: When enabled by the oscillator enable override enable bit in this register this bit can be used to directly control the enable of the signal detect oscillator" "0,1"
hexmask.long.word 0x1C 4.--15. 1. "CMN_CDIAG_PSMCLK_CTRL_15_4,Reserved"
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bitfld.long 0x1C 0.--3. "CMN_CDIAG_PSMCLK_CTRL_3_0,PSM clock divider value: The value of this field is used to control the divider setting of the PSM clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CMN_CDIAG_REFCLK_DRV0_CTRL,Reference clock bump driver 0 control register"
rbitfld.long 0x20 10.--15. "CMN_CDIAG_REFCLK_DRV0_CTRL_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x20 8.--9. "CMN_CDIAG_REFCLK_DRV0_CTRL_9_8,Clock driver drive current tune: Controls the amplitude of the reference clock driver by controlling the cmnda_ref_clk0_itune signal going to the analog" "0,1,2,3"
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rbitfld.long 0x20 7. "CMN_CDIAG_REFCLK_DRV0_CTRL_7,Reserved" "0,1"
bitfld.long 0x20 6. "CMN_CDIAG_REFCLK_DRV0_CTRL_6,Reference clock driver high Z: When the reference clock driver is disabled this controls if the driver outputs are high Z or pulled low by controlling the cmnda_ref_clk0_drv_highz signal going to the analog" "0,1"
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bitfld.long 0x20 5. "CMN_CDIAG_REFCLK_DRV0_CTRL_5,Clock driver termination: Enables the termination in the reference clock driver by controlling the cmnda_ref_clk0_termination signal going to the analog" "0,1"
bitfld.long 0x20 4. "CMN_CDIAG_REFCLK_DRV0_CTRL_4,Clock select: Selects which reference clock that will be driven by the reference clock driver by controlling the cmnda_ref_clk0_clk_select signal going to the analog" "0,1"
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bitfld.long 0x20 3. "CMN_CDIAG_REFCLK_DRV0_CTRL_3,Clock gate enable override enable: This bit enables the clock gate enable override bit in this register to override the clock gate of the reference clock driver" "0,1"
bitfld.long 0x20 2. "CMN_CDIAG_REFCLK_DRV0_CTRL_2,Clock gate enable override: When enabled by the clock gate enable override enable bit in this register this bit can be used to directly control the clock gate enable of the reference clock driver by controlling the.." "0,1"
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bitfld.long 0x20 1. "CMN_CDIAG_REFCLK_DRV0_CTRL_1,Driver enable override enable: This bit enables the driver enable override bit in this register to override the enable of the reference clock driver" "0,1"
bitfld.long 0x20 0. "CMN_CDIAG_REFCLK_DRV0_CTRL_0,Driver enable override: When enabled by the driver enable override enable bit in this register this bit can be used to directly control the enable of the reference clock driver by controlling the cmnda_ref_clk0_drv_en signal.." "0,1"
rgroup.long 0xB8++0x13
line.long 0x00 "CMN_CDIAG_RST_DIAG__CMN_CDIAG_CDB_DIAG,Common control CDB diagnostic register"
hexmask.long.word 0x00 18.--31. 1. "CMN_CDIAG_RST_DIAG_15_2,Reserved"
bitfld.long 0x00 17. "CMN_CDIAG_RST_DIAG_1,Current state of the cdb_isl_ctrl_sm_reset_n reset" "0,1"
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bitfld.long 0x00 16. "CMN_CDIAG_RST_DIAG_0,Current state of the cmn_reset_sync_n reset" "0,1"
hexmask.long.word 0x00 1.--15. 1. "CMN_CDIAG_CDB_DIAG_15_1,Reserved"
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bitfld.long 0x00 0. "CMN_CDIAG_CDB_DIAG_0,CDB bus error: This bit will be set when the internal CDB watchdog timer expires" "0,1"
line.long 0x04 "CMN_CDIAG_DCYA,Common control cover your alternatives register"
hexmask.long.byte 0x04 24.--31. 1. "CMN_CDIAG_DCYA_15_8,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "CMN_CDIAG_DCYA_7_0,Reserved - spare"
line.long 0x08 "CMN_BGCAL_OVRD__CMN_BGCAL_CTRL,Bandgap calibration control register"
bitfld.long 0x08 31. "CMN_BGCAL_OVRD_15,Bandgap code override enable: Activation (1'b1) of this register bit allows the bandgap codes determined during the automatic calibration process to be overridden" "0,1"
bitfld.long 0x08 30. "CMN_BGCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_bias_bgcal_en enable" "0,1"
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hexmask.long.byte 0x08 22.--29. 1. "CMN_BGCAL_OVRD_13_6,Reserved"
bitfld.long 0x08 16.--21. "CMN_BGCAL_OVRD_5_0,Bandgap code override value: These bits are used to override the bandgap code determined during the automatic calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 15. "CMN_BGCAL_CTRL_15,Start bandgap calibration: Activating (1'b1) this bit will start the bandgap calibration process" "0,1"
rbitfld.long 0x08 14. "CMN_BGCAL_CTRL_14,Bandgap calibration process done: This bit will be set to 1'b1 when the bandgap calibration process is complete" "0,1"
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rbitfld.long 0x08 13. "CMN_BGCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x08 12. "CMN_BGCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_bias_bgcal_comp)" "0,1"
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rbitfld.long 0x08 6.--11. "CMN_BGCAL_CTRL_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x08 0.--5. "CMN_BGCAL_CTRL_5_0,Bandgap calibration code: This is the calibration code that was determined by the bandgap calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CMN_BGCAL_TUNE__CMN_BGCAL_START,Bandgap calibration start register"
hexmask.long.word 0x0C 22.--31. 1. "CMN_BGCAL_TUNE_15_6,Reserved"
bitfld.long 0x0C 16.--21. "CMN_BGCAL_TUNE_5_0,Bandgap calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 15. "CMN_BGCAL_START_15,Bandgap calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.word 0x0C 6.--14. 1. "CMN_BGCAL_START_14_6,Reserved"
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bitfld.long 0x0C 0.--5. "CMN_BGCAL_START_5_0,Start bandgap calibration code: This is the calibration code that the calibration process starts with when automatic calibration is run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "CMN_BGCAL_ITER_TMR__CMN_BGCAL_INIT_TMR,Bandgap calibration initialization timer register"
hexmask.long.byte 0x10 25.--31. 1. "CMN_BGCAL_ITER_TMR_15_9,Reserved"
hexmask.long.word 0x10 16.--24. 1. "CMN_BGCAL_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the bandgap calibration signals going to the analog and when the comparator value coming from the analog circuits can.."
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hexmask.long.byte 0x10 9.--15. 1. "CMN_BGCAL_INIT_TMR_15_9,Reserved"
hexmask.long.word 0x10 0.--8. 1. "CMN_BGCAL_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog bandgap calibration circuits are enabled and when the first values are placed on the bandgap calibration signals going to.."
group.long 0xE0++0x0B
line.long 0x00 "CMN_IBCAL_OVRD__CMN_IBCAL_CTRL,External bias current calibration control register"
bitfld.long 0x00 31. "CMN_IBCAL_OVRD_15,Calibration code override enable: Activation (1'b1) of this register bit allows the calibration code determined during the automatic resistor calibration process to be overridden" "0,1"
bitfld.long 0x00 30. "CMN_IBCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_ibiascal_en enable and the cmnda_ibiascal_clk clock" "0,1"
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hexmask.long.byte 0x00 23.--29. 1. "CMN_IBCAL_OVRD_13_7,Reserved"
hexmask.long.byte 0x00 16.--22. 1. "CMN_IBCAL_OVRD_6_0,Calibration code override value: These bits are used to override the calibration code determined during the automatic resistor calibration process"
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bitfld.long 0x00 15. "CMN_IBCAL_CTRL_15,Start calibration: Activating (1'b1) this bit will start the calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_IBCAL_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete" "0,1"
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rbitfld.long 0x00 13. "CMN_IBCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x00 12. "CMN_IBCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_ibiascal_comp)" "0,1"
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rbitfld.long 0x00 7.--11. "CMN_IBCAL_CTRL_11_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--6. 1. "CMN_IBCAL_CTRL_6_0,Calibration code: This is the calibration code that was determined by the calibration process"
line.long 0x04 "CMN_IBCAL_TUNE__CMN_IBCAL_START,External bias current calibration start register"
hexmask.long.word 0x04 23.--31. 1. "CMN_IBCAL_TUNE_15_7,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "CMN_IBCAL_TUNE_6_0,Calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled"
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bitfld.long 0x04 15. "CMN_IBCAL_START_15,Calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.byte 0x04 7.--14. 1. "CMN_IBCAL_START_14_7,Reserved"
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hexmask.long.byte 0x04 0.--6. 1. "CMN_IBCAL_START_6_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run"
line.long 0x08 "CMN_IBCAL_ITER_TMR__CMN_IBCAL_INIT_TMR,External bias current calibration initialization timer register"
hexmask.long.word 0x08 23.--31. 1. "CMN_IBCAL_ITER_TMR_15_7,Reserved"
hexmask.long.byte 0x08 16.--22. 1. "CMN_IBCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration selection bus going to the analog and when the comparator value coming from the analog circuits can be.."
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hexmask.long.word 0x08 7.--15. 1. "CMN_IBCAL_INIT_TMR_15_7,Reserved"
hexmask.long.byte 0x08 0.--6. 1. "CMN_IBCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first calibration selection value is placed on the calibration code bus going.."
group.long 0x100++0x13
line.long 0x00 "CMN_PLL0_VCOCAL_START__CMN_PLL0_VCOCAL_CTRL,PLL 0 VCO calibration control register"
rbitfld.long 0x00 31. "CMN_PLL0_VCOCAL_START_15,Reserved" "0,1"
bitfld.long 0x00 28.--30. "CMN_PLL0_VCOCAL_START_14_12,VCO calibration initial step size control: This field specifies the initial step size for the VCO calibration state machine" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--27. "CMN_PLL0_VCOCAL_START_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "CMN_PLL0_VCOCAL_START_7_0,VCO calibration code starting point value: This field specifies the starting VCO code that is used by the VCO calibration state machine"
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bitfld.long 0x00 15. "CMN_PLL0_VCOCAL_CTRL_15,Start VCO calibration: Activating (1'b1) this bit will start a VCO calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_PLL0_VCOCAL_CTRL_14,VCO calibration process done: This bit will be set to 1'b1 when the VCO calibration process is complete" "0,1"
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rbitfld.long 0x00 8.--13. "CMN_PLL0_VCOCAL_CTRL_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "CMN_PLL0_VCOCAL_CTRL_7_0,VCO calibration code: This is the calibration code that was determined by the VCO calibration process"
line.long 0x04 "CMN_PLL0_VCOCAL_OVRD__CMN_PLL0_VCOCAL_TCTRL,PLL 0 VCO calibration timer control register"
bitfld.long 0x04 31. "CMN_PLL0_VCOCAL_OVRD_15,VCO calibration code override enable: Activating (1'b1) this bit allows the VCO code determined during the automatic VCO calibration process to be overridden by the value driven by the VCO calibration code override value field in.." "0,1"
hexmask.long.byte 0x04 24.--30. 1. "CMN_PLL0_VCOCAL_OVRD_14_8,Reserved"
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hexmask.long.byte 0x04 16.--23. 1. "CMN_PLL0_VCOCAL_OVRD_7_0,VCO calibration code override value: This field is used to override the VCO code determined during the automatic VCO calibration process"
hexmask.long.word 0x04 3.--15. 1. "CMN_PLL0_VCOCAL_TCTRL_15_3,Reserved"
newline
bitfld.long 0x04 0.--2. "CMN_PLL0_VCOCAL_TCTRL_2_0,VCO calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the VCO calibration when running the initial step size for the calibration code if not set to 1" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMN_PLL0_VCOCAL_ITER_TMR__CMN_PLL0_VCOCAL_INIT_TMR,PLL 0 VCO calibration initialization timer register"
rbitfld.long 0x08 30.--31. "CMN_PLL0_VCOCAL_ITER_TMR_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x08 16.--29. 1. "CMN_PLL0_VCOCAL_ITER_TMR_13_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured"
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rbitfld.long 0x08 14.--15. "CMN_PLL0_VCOCAL_INIT_TMR_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x08 0.--13. 1. "CMN_PLL0_VCOCAL_INIT_TMR_13_0,Initialization wait timer value: This is the number of clocks to wait between when the analog VCO calibration circuits are enabled and when the first calibration code is driven to the analog"
line.long 0x0C "CMN_PLL0_VCOCAL_REFTIM_START,PLL 0 VCO calibration reference clock timer start value register"
rbitfld.long 0x0C 14.--15. "CMN_PLL0_VCOCAL_REFTIM_START_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x0C 0.--13. 1. "CMN_PLL0_VCOCAL_REFTIM_START_13_0,PLL VCO calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running VCO calibration"
line.long 0x10 "CMN_PLL0_VCOCAL_PLLCNT_START,PLL 0 VCO calibration PLL clock counter start value register"
rbitfld.long 0x10 14.--15. "CMN_PLL0_VCOCAL_PLLCNT_START_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x10 0.--13. 1. "CMN_PLL0_VCOCAL_PLLCNT_START_13_0,PLL VCO calibration PLL clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running VCO calibration"
group.long 0x120++0x37
line.long 0x00 "CMN_PLL0_FRACDIVL_M0__CMN_PLL0_INTDIV_M0,PLL 0 feedback divider integer register mode 0"
hexmask.long.word 0x00 16.--31. 1. "CMN_PLL0_FRACDIVL_M0_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal"
hexmask.long.byte 0x00 9.--15. 1. "CMN_PLL0_INTDIV_M0_15_9,Reserved"
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hexmask.long.word 0x00 0.--8. 1. "CMN_PLL0_INTDIV_M0_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal"
line.long 0x04 "CMN_PLL0_HIGH_THR_M0__CMN_PLL0_FRACDIVH_M0,PLL 0 feedback divider fractional high register mode 0"
hexmask.long.byte 0x04 25.--31. 1. "CMN_PLL0_HIGH_THR_M0_15_9,Reserved"
hexmask.long.word 0x04 16.--24. 1. "CMN_PLL0_HIGH_THR_M0_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal"
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hexmask.long.word 0x04 3.--15. 1. "CMN_PLL0_FRACDIVH_M0_15_3,Reserved"
bitfld.long 0x04 0.--2. "CMN_PLL0_FRACDIVH_M0_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMN_PLL0_DSM_FBH_OVRD_M0__CMN_PLL0_DSM_DIAG_M0,PLL 0 delta sigma modulator diagnostics register mode 0"
hexmask.long.byte 0x08 25.--31. 1. "CMN_PLL0_DSM_FBH_OVRD_M0_15_9,Reserved"
hexmask.long.word 0x08 16.--24. 1. "CMN_PLL0_DSM_FBH_OVRD_M0_8_0,PLL feedback divider high override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.."
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bitfld.long 0x08 15. "CMN_PLL0_DSM_DIAG_M0_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal" "0,1"
bitfld.long 0x08 14. "CMN_PLL0_DSM_DIAG_M0_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 0 delta sigma modulator feedback divider value high override register mode 0 on page 102 and PLL 0 delta sigma.." "0,1"
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hexmask.long.word 0x08 4.--13. 1. "CMN_PLL0_DSM_DIAG_M0_13_4,Reserved"
bitfld.long 0x08 0.--3. "CMN_PLL0_DSM_DIAG_M0_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll0_fb_div_high and cmnda_pll0_fb_div_low signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CMN_PLL0_DSM_FBL_OVRD_M0,PLL 0 delta sigma modulator feedback divider value low override register mode 0"
hexmask.long.byte 0x0C 9.--15. 1. "CMN_PLL0_DSM_FBL_OVRD_M0_15_9,Reserved"
hexmask.long.word 0x0C 0.--8. 1. "CMN_PLL0_DSM_FBL_OVRD_M0_8_0,PLL feedback divider low override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.."
line.long 0x10 "CMN_PLL0_SS_CTRL2_M0__CMN_PLL0_SS_CTRL1_M0,PLL 0 spread spectrum control register 1 mode 0"
rbitfld.long 0x10 31. "CMN_PLL0_SS_CTRL2_M0_15,Reserved" "0,1"
hexmask.long.word 0x10 16.--30. 1. "CMN_PLL0_SS_CTRL2_M0_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator"
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hexmask.long.word 0x10 2.--15. 1. "CMN_PLL0_SS_CTRL1_M0_15_2,Reserved"
bitfld.long 0x10 1. "CMN_PLL0_SS_CTRL1_M0_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator" "0,1"
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bitfld.long 0x10 0. "CMN_PLL0_SS_CTRL1_M0_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place" "0,1"
line.long 0x14 "CMN_PLL0_SS_CTRL4_M0__CMN_PLL0_SS_CTRL3_M0,PLL 0 spread spectrum control register 3 mode 0"
hexmask.long.word 0x14 23.--31. 1. "CMN_PLL0_SS_CTRL4_M0_15_7,Reserved"
hexmask.long.byte 0x14 16.--22. 1. "CMN_PLL0_SS_CTRL4_M0_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator"
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hexmask.long.word 0x14 7.--15. 1. "CMN_PLL0_SS_CTRL3_M0_15_7,Reserved"
hexmask.long.byte 0x14 0.--6. 1. "CMN_PLL0_SS_CTRL3_M0_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator"
line.long 0x18 "CMN_PLL0_LOCK_REFCNT_IDLE__CMN_PLL0_LOCK_REFCNT_START,PLL 0 lock reference counter start value register"
rbitfld.long 0x18 28.--31. "CMN_PLL0_LOCK_REFCNT_IDLE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 16.--27. 1. "CMN_PLL0_LOCK_REFCNT_IDLE_11_0,PLL lock reference counter idle value : This is the value used by the PLL lock detection logic to specify the number of reference clocks between each phase of counting PLL clocks"
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rbitfld.long 0x18 12.--15. "CMN_PLL0_LOCK_REFCNT_START_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--11. 1. "CMN_PLL0_LOCK_REFCNT_START_11_0,PLL lock reference counter start value : This is the value that is loaded into the PLL lock detect reference counter as the starting point for that counter when checking for PLL lock"
line.long 0x1C "CMN_PLL0_LOCK_PLLCNT_THR__CMN_PLL0_LOCK_PLLCNT_START,PLL 0 lock PLL counter start value register"
rbitfld.long 0x1C 28.--31. "CMN_PLL0_LOCK_PLLCNT_THR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 16.--27. 1. "CMN_PLL0_LOCK_PLLCNT_THR_11_0,PLL lock counter threshold value : This is the value used by the PLL lock detection logic to determine if the PLL has locked"
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rbitfld.long 0x1C 12.--15. "CMN_PLL0_LOCK_PLLCNT_START_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--11. 1. "CMN_PLL0_LOCK_PLLCNT_START_11_0,PLL lock PLL counter start value : This is the value that is loaded into the PLL lock detect PLL counter as the starting point for that counter when checking for PLL lock"
line.long 0x20 "CMN_PLL0_FRACDIVL_M1__CMN_PLL0_INTDIV_M1,PLL 0 feedback divider integer register mode 1"
hexmask.long.word 0x20 16.--31. 1. "CMN_PLL0_FRACDIVL_M1_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal"
hexmask.long.byte 0x20 9.--15. 1. "CMN_PLL0_INTDIV_M1_15_9,Reserved"
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hexmask.long.word 0x20 0.--8. 1. "CMN_PLL0_INTDIV_M1_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal"
line.long 0x24 "CMN_PLL0_HIGH_THR_M1__CMN_PLL0_FRACDIVH_M1,PLL 0 feedback divider fractional high register mode 1"
hexmask.long.byte 0x24 25.--31. 1. "CMN_PLL0_HIGH_THR_M1_15_9,Reserved"
hexmask.long.word 0x24 16.--24. 1. "CMN_PLL0_HIGH_THR_M1_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal"
newline
hexmask.long.word 0x24 3.--15. 1. "CMN_PLL0_FRACDIVH_M1_15_3,Reserved"
bitfld.long 0x24 0.--2. "CMN_PLL0_FRACDIVH_M1_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal" "0,1,2,3,4,5,6,7"
line.long 0x28 "CMN_PLL0_DSM_FBH_OVRD_M1__CMN_PLL0_DSM_DIAG_M1,PLL 0 delta sigma modulator diagnostics register mode 1"
hexmask.long.byte 0x28 25.--31. 1. "CMN_PLL0_DSM_FBH_OVRD_M1_15_9,Reserved"
hexmask.long.word 0x28 16.--24. 1. "CMN_PLL0_DSM_FBH_OVRD_M1_8_0,PLL feedback divider high override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.."
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bitfld.long 0x28 15. "CMN_PLL0_DSM_DIAG_M1_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal" "0,1"
bitfld.long 0x28 14. "CMN_PLL0_DSM_DIAG_M1_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 0 delta sigma modulator feedback divider value high override register mode 0 on page 102 and PLL 0 delta sigma.." "0,1"
newline
hexmask.long.word 0x28 4.--13. 1. "CMN_PLL0_DSM_DIAG_M1_13_4,Reserved"
bitfld.long 0x28 0.--3. "CMN_PLL0_DSM_DIAG_M1_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll0_fb_div_high and cmnda_pll0_fb_div_low signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CMN_PLL0_DSM_FBL_OVRD_M1,PLL 0 delta sigma modulator feedback divider value low override register mode 1"
hexmask.long.byte 0x2C 9.--15. 1. "CMN_PLL0_DSM_FBL_OVRD_M1_15_9,Reserved"
hexmask.long.word 0x2C 0.--8. 1. "CMN_PLL0_DSM_FBL_OVRD_M1_8_0,PLL feedback divider low override value : When enabled by the PLL feedback divider override enable bit in the PLL 0 delta sigma modulator diagnostics register mode 0 on page 102 the value in this field will be used to.."
line.long 0x30 "CMN_PLL0_SS_CTRL2_M1__CMN_PLL0_SS_CTRL1_M1,PLL 0 spread spectrum control register 1 mode 1"
rbitfld.long 0x30 31. "CMN_PLL0_SS_CTRL2_M1_15,Reserved" "0,1"
hexmask.long.word 0x30 16.--30. 1. "CMN_PLL0_SS_CTRL2_M1_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator"
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hexmask.long.word 0x30 2.--15. 1. "CMN_PLL0_SS_CTRL1_M1_15_2,Reserved"
bitfld.long 0x30 1. "CMN_PLL0_SS_CTRL1_M1_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator" "0,1"
newline
bitfld.long 0x30 0. "CMN_PLL0_SS_CTRL1_M1_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place" "0,1"
line.long 0x34 "CMN_PLL0_SS_CTRL4_M1__CMN_PLL0_SS_CTRL3_M1,PLL 0 spread spectrum control register 3 mode 1"
hexmask.long.word 0x34 23.--31. 1. "CMN_PLL0_SS_CTRL4_M1_15_7,Reserved"
hexmask.long.byte 0x34 16.--22. 1. "CMN_PLL0_SS_CTRL4_M1_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator"
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hexmask.long.word 0x34 7.--15. 1. "CMN_PLL0_SS_CTRL3_M1_15_7,Reserved"
hexmask.long.byte 0x34 0.--6. 1. "CMN_PLL0_SS_CTRL3_M1_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator"
group.long 0x180++0x13
line.long 0x00 "CMN_PLL1_VCOCAL_START__CMN_PLL1_VCOCAL_CTRL,PLL 1 VCO calibration control register"
rbitfld.long 0x00 31. "CMN_PLL1_VCOCAL_START_15,Reserved" "0,1"
bitfld.long 0x00 28.--30. "CMN_PLL1_VCOCAL_START_14_12,VCO calibration initial step size control: This field specifies the initial step size for the VCO calibration state machine" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 24.--27. "CMN_PLL1_VCOCAL_START_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "CMN_PLL1_VCOCAL_START_7_0,VCO calibration code starting point value: This field specifies the starting VCO code that is used by the VCO calibration state machine"
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bitfld.long 0x00 15. "CMN_PLL1_VCOCAL_CTRL_15,Start VCO calibration: Activating (1'b1) this bit will start a VCO calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_PLL1_VCOCAL_CTRL_14,VCO calibration process done: This bit will be set to 1'b1 when the VCO calibration process is complete" "0,1"
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rbitfld.long 0x00 8.--13. "CMN_PLL1_VCOCAL_CTRL_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "CMN_PLL1_VCOCAL_CTRL_7_0,VCO calibration code: This is the calibration code that was determined by the VCO calibration process"
line.long 0x04 "CMN_PLL1_VCOCAL_OVRD__CMN_PLL1_VCOCAL_TCTRL,PLL 1 VCO calibration timer control register"
bitfld.long 0x04 31. "CMN_PLL1_VCOCAL_OVRD_15,VCO calibration code override enable: Activating (1'b1) this bit allows the VCO code determined during the automatic VCO calibration process to be overridden by the value driven by the VCO calibration code override value field in.." "0,1"
hexmask.long.byte 0x04 24.--30. 1. "CMN_PLL1_VCOCAL_OVRD_14_8,Reserved"
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hexmask.long.byte 0x04 16.--23. 1. "CMN_PLL1_VCOCAL_OVRD_7_0,VCO calibration code override value: This field is used to override the VCO code determined during the automatic VCO calibration process"
hexmask.long.word 0x04 3.--15. 1. "CMN_PLL1_VCOCAL_TCTRL_15_3,Reserved"
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bitfld.long 0x04 0.--2. "CMN_PLL1_VCOCAL_TCTRL_2_0,VCO calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the VCO calibration when running the initial step size for the calibration code if not set to 1" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMN_PLL1_VCOCAL_ITER_TMR__CMN_PLL1_VCOCAL_INIT_TMR,PLL 1 VCO calibration initialization timer register"
rbitfld.long 0x08 30.--31. "CMN_PLL1_VCOCAL_ITER_TMR_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x08 16.--29. 1. "CMN_PLL1_VCOCAL_ITER_TMR_13_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured"
newline
rbitfld.long 0x08 14.--15. "CMN_PLL1_VCOCAL_INIT_TMR_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x08 0.--13. 1. "CMN_PLL1_VCOCAL_INIT_TMR_13_0,Initialization wait timer value: This is the number of clocks to wait between when the analog VCO calibration circuits are enabled and when the first calibration code is driven to the analog"
line.long 0x0C "CMN_PLL1_VCOCAL_REFTIM_START,PLL 1 VCO calibration reference clock timer start value register"
rbitfld.long 0x0C 14.--15. "CMN_PLL1_VCOCAL_REFTIM_START_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x0C 0.--13. 1. "CMN_PLL1_VCOCAL_REFTIM_START_13_0,PLL VCO calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running VCO calibration"
line.long 0x10 "CMN_PLL1_VCOCAL_PLLCNT_START,PLL 1 VCO calibration PLL clock counter start value register"
rbitfld.long 0x10 14.--15. "CMN_PLL1_VCOCAL_PLLCNT_START_15_14,Reserved" "0,1,2,3"
hexmask.long.word 0x10 0.--13. 1. "CMN_PLL1_VCOCAL_PLLCNT_START_13_0,PLL VCO calibration PLL clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running VCO calibration"
group.long 0x1A0++0x1F
line.long 0x00 "CMN_PLL1_FRACDIVL_M0__CMN_PLL1_INTDIV_M0,PLL 1 feedback divider integer register mode 0"
hexmask.long.word 0x00 16.--31. 1. "CMN_PLL1_FRACDIVL_M0_15_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[15:0] signal"
hexmask.long.byte 0x00 9.--15. 1. "CMN_PLL1_INTDIV_M0_15_9,Reserved"
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hexmask.long.word 0x00 0.--8. 1. "CMN_PLL1_INTDIV_M0_8_0,pll_fb_div_integer value: Value of the pll_fb_div_integer signal"
line.long 0x04 "CMN_PLL1_HIGH_THR_M0__CMN_PLL1_FRACDIVH_M0,PLL 1 feedback divider fractional high register mode 0"
hexmask.long.byte 0x04 25.--31. 1. "CMN_PLL1_HIGH_THR_M0_15_9,Reserved"
hexmask.long.word 0x04 16.--24. 1. "CMN_PLL1_HIGH_THR_M0_8_0,pll_fb_div_high_theshold: Value of the pll_fb_div_high_threshold signal"
newline
hexmask.long.word 0x04 3.--15. 1. "CMN_PLL1_FRACDIVH_M0_15_3,Reserved"
bitfld.long 0x04 0.--2. "CMN_PLL1_FRACDIVH_M0_2_0,pll_fb_div_fractional: Value of the pll_fb_div_fractional[18:16] signal" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMN_PLL1_DSM_FBH_OVRD_M0__CMN_PLL1_DSM_DIAG_M0,PLL 1 delta sigma modulator diagnostics register mode 0"
hexmask.long.byte 0x08 25.--31. 1. "CMN_PLL1_DSM_FBH_OVRD_M0_15_9,Reserved"
hexmask.long.word 0x08 16.--24. 1. "CMN_PLL1_DSM_FBH_OVRD_M0_8_0,PLL feedback divider high override value : When enabled by the PLL feedback divider override enable bit in the PLL 1 delta sigma modulator diagnostics register mode 0 on page 111 the value in this field will be used to.."
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bitfld.long 0x08 15. "CMN_PLL1_DSM_DIAG_M0_15,Delta sigma bypass enable: When set to 1'b1 the delta sigma modulator will be bypassed and the output will be the value specified for the internal pll_fb_div_integer signal" "0,1"
bitfld.long 0x08 14. "CMN_PLL1_DSM_DIAG_M0_14,PLL feedback divider override enable : When active (1'b1) the feedback divider low and high override values in the PLL 1 delta sigma modulator feedback divider value high override register mode 0 on page 111 and PLL 1 delta sigma.." "0,1"
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hexmask.long.word 0x08 4.--13. 1. "CMN_PLL1_DSM_DIAG_M0_13_4,Reserved"
bitfld.long 0x08 0.--3. "CMN_PLL1_DSM_DIAG_M0_3_0,PLL feedback divider latency adjustment: This signal specifies a value to be subtracted from the feedback divider settings before they are output on the cmnda_pll1_fb_div_high and cmnda_pll1_fb_div_low signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CMN_PLL1_DSM_FBL_OVRD_M0,PLL 1 delta sigma modulator feedback divider value low override register mode 0"
hexmask.long.byte 0x0C 9.--15. 1. "CMN_PLL1_DSM_FBL_OVRD_M0_15_9,Reserved"
hexmask.long.word 0x0C 0.--8. 1. "CMN_PLL1_DSM_FBL_OVRD_M0_8_0,PLL feedback divider low override value : When enabled by the PLL feedback divider override enable bit in the PLL 1 delta sigma modulator diagnostics register mode 0 on page 111 the value in this field will be used to.."
line.long 0x10 "CMN_PLL1_SS_CTRL2_M0__CMN_PLL1_SS_CTRL1_M0,PLL 1 spread spectrum control register 1 mode 0"
rbitfld.long 0x10 31. "CMN_PLL1_SS_CTRL2_M0_15,Reserved" "0,1"
hexmask.long.word 0x10 16.--30. 1. "CMN_PLL1_SS_CTRL2_M0_14_0,Amplitude step size: Value of the amplitude_step_size pin on the spread spectrum waveform generator"
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hexmask.long.word 0x10 2.--15. 1. "CMN_PLL1_SS_CTRL1_M0_15_2,Reserved"
bitfld.long 0x10 1. "CMN_PLL1_SS_CTRL1_M0_1,Spread spectrum waveform generator disable: Setting this bit to a 1'b1 will disable the spread spectrum waveform generator" "0,1"
newline
bitfld.long 0x10 0. "CMN_PLL1_SS_CTRL1_M0_0,Spread spectrum enable during VCO calibration : Setting this bit to a 1'b1 will enable the spread spectrum function while VCO calibration is taking place" "0,1"
line.long 0x14 "CMN_PLL1_SS_CTRL4_M0__CMN_PLL1_SS_CTRL3_M0,PLL 1 spread spectrum control register 3 mode 0"
hexmask.long.word 0x14 23.--31. 1. "CMN_PLL1_SS_CTRL4_M0_15_7,Reserved"
hexmask.long.byte 0x14 16.--22. 1. "CMN_PLL1_SS_CTRL4_M0_6_0,Time step size: Value for the time_step_size pin on the spread spectrum waveform generator"
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hexmask.long.word 0x14 7.--15. 1. "CMN_PLL1_SS_CTRL3_M0_15_7,Reserved"
hexmask.long.byte 0x14 0.--6. 1. "CMN_PLL1_SS_CTRL3_M0_6_0,Number of steps: Value of the num_steps pin on the spread spectrum waveform generator"
line.long 0x18 "CMN_PLL1_LOCK_REFCNT_IDLE__CMN_PLL1_LOCK_REFCNT_START,PLL 1 lock reference counter start value register"
rbitfld.long 0x18 28.--31. "CMN_PLL1_LOCK_REFCNT_IDLE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 16.--27. 1. "CMN_PLL1_LOCK_REFCNT_IDLE_11_0,PLL lock reference counter idle value : This is the value used by the PLL lock detection logic to specify the number of reference clocks between each phase of counting PLL clocks"
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rbitfld.long 0x18 12.--15. "CMN_PLL1_LOCK_REFCNT_START_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--11. 1. "CMN_PLL1_LOCK_REFCNT_START_11_0,PLL lock reference counter start value : This is the value that is loaded into the PLL lock detect reference counter as the starting point for that counter when checking for PLL lock"
line.long 0x1C "CMN_PLL1_LOCK_PLLCNT_THR__CMN_PLL1_LOCK_PLLCNT_START,PLL 1 lock PLL counter start value register"
rbitfld.long 0x1C 28.--31. "CMN_PLL1_LOCK_PLLCNT_THR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 16.--27. 1. "CMN_PLL1_LOCK_PLLCNT_THR_11_0,PLL lock counter threshold value : This is the value used by the PLL lock detection logic to determine if the PLL has locked"
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rbitfld.long 0x1C 12.--15. "CMN_PLL1_LOCK_PLLCNT_START_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--11. 1. "CMN_PLL1_LOCK_PLLCNT_START_11_0,PLL lock PLL counter start value : This is the value that is loaded into the PLL lock detect PLL counter as the starting point for that counter when checking for PLL lock"
group.long 0x200++0x0B
line.long 0x00 "CMN_TXPUCAL_OVRD__CMN_TXPUCAL_CTRL,TX pull-up resistor calibration control register"
bitfld.long 0x00 31. "CMN_TXPUCAL_OVRD_15,Resistor code override enable: Activation (1'b1) of this register bit allows the resistor codes determined during the automatic resistor calibration process to be overridden" "0,1"
bitfld.long 0x00 30. "CMN_TXPUCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_rescal_en_tx_useg enable and the cmnda_rescal_clk_tx_useg clock" "0,1"
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hexmask.long.byte 0x00 23.--29. 1. "CMN_TXPUCAL_OVRD_13_7,Reserved"
hexmask.long.byte 0x00 16.--22. 1. "CMN_TXPUCAL_OVRD_6_0,Resistor code override value: These bits are used to override the resistor code determined during the automatic resistor calibration process"
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bitfld.long 0x00 15. "CMN_TXPUCAL_CTRL_15,Start resistor calibration: Activating (1'b1) this bit will start the resistor calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_TXPUCAL_CTRL_14,Resistor calibration process done: This bit will be set to 1'b1 when the resistor calibration process is complete" "0,1"
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rbitfld.long 0x00 13. "CMN_TXPUCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x00 12. "CMN_TXPUCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_rescal_comp_tx_useg)" "0,1"
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rbitfld.long 0x00 7.--11. "CMN_TXPUCAL_CTRL_11_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--6. 1. "CMN_TXPUCAL_CTRL_6_0,Resistor calibration code: This is the calibration code that was determined by the resistor calibration process"
line.long 0x04 "CMN_TXPUCAL_TUNE__CMN_TXPUCAL_START,TX pull-up resistor calibration start register"
hexmask.long.word 0x04 23.--31. 1. "CMN_TXPUCAL_TUNE_15_7,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "CMN_TXPUCAL_TUNE_6_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled"
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bitfld.long 0x04 15. "CMN_TXPUCAL_START_15,Resistor calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.byte 0x04 7.--14. 1. "CMN_TXPUCAL_START_14_7,Reserved"
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hexmask.long.byte 0x04 0.--6. 1. "CMN_TXPUCAL_START_6_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run"
line.long 0x08 "CMN_TXPUCAL_ITER_TMR__CMN_TXPUCAL_INIT_TMR,TX pull-up resistor calibration initialization timer register"
hexmask.long.word 0x08 23.--31. 1. "CMN_TXPUCAL_ITER_TMR_15_7,Reserved"
hexmask.long.byte 0x08 16.--22. 1. "CMN_TXPUCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.."
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hexmask.long.word 0x08 7.--15. 1. "CMN_TXPUCAL_INIT_TMR_15_7,Reserved"
hexmask.long.byte 0x08 0.--6. 1. "CMN_TXPUCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor.."
group.long 0x210++0x0B
line.long 0x00 "CMN_TXPDCAL_OVRD__CMN_TXPDCAL_CTRL,TX pull-down resistor calibration control register"
bitfld.long 0x00 31. "CMN_TXPDCAL_OVRD_15,Resistor code override enable: Activation (1'b1) of this register bit allows the resistor codes determined during the automatic resistor calibration process to be overridden" "0,1"
bitfld.long 0x00 30. "CMN_TXPDCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_rescal_en_tx_dseg enable and the cmnda_rescal_clk_tx_dseg clock" "0,1"
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hexmask.long.byte 0x00 23.--29. 1. "CMN_TXPDCAL_OVRD_13_7,Reserved"
hexmask.long.byte 0x00 16.--22. 1. "CMN_TXPDCAL_OVRD_6_0,Resistor code override value: These bits are used to override the resistor code determined during the automatic resistor calibration process"
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bitfld.long 0x00 15. "CMN_TXPDCAL_CTRL_15,Start resistor calibration: Activating (1'b1) this bit will start the resistor calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_TXPDCAL_CTRL_14,Resistor calibration process done: This bit will be set to 1'b1 when the resistor calibration process is complete" "0,1"
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rbitfld.long 0x00 13. "CMN_TXPDCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x00 12. "CMN_TXPDCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_rescal_comp_tx_dseg)" "0,1"
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rbitfld.long 0x00 7.--11. "CMN_TXPDCAL_CTRL_11_7,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--6. 1. "CMN_TXPDCAL_CTRL_6_0,Resistor calibration code: This is the calibration code that was determined by the resistor calibration process"
line.long 0x04 "CMN_TXPDCAL_TUNE__CMN_TXPDCAL_START,TX pull-down resistor calibration start register"
hexmask.long.word 0x04 23.--31. 1. "CMN_TXPDCAL_TUNE_15_7,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "CMN_TXPDCAL_TUNE_6_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled"
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bitfld.long 0x04 15. "CMN_TXPDCAL_START_15,Resistor calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.byte 0x04 7.--14. 1. "CMN_TXPDCAL_START_14_7,Reserved"
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hexmask.long.byte 0x04 0.--6. 1. "CMN_TXPDCAL_START_6_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run"
line.long 0x08 "CMN_TXPDCAL_ITER_TMR__CMN_TXPDCAL_INIT_TMR,TX pull-down resistor calibration initialization timer register"
hexmask.long.word 0x08 23.--31. 1. "CMN_TXPDCAL_ITER_TMR_15_7,Reserved"
hexmask.long.byte 0x08 16.--22. 1. "CMN_TXPDCAL_ITER_TMR_6_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.."
newline
hexmask.long.word 0x08 7.--15. 1. "CMN_TXPDCAL_INIT_TMR_15_7,Reserved"
hexmask.long.byte 0x08 0.--6. 1. "CMN_TXPDCAL_INIT_TMR_6_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor.."
group.long 0x220++0x0B
line.long 0x00 "CMN_RXCAL_OVRD__CMN_RXCAL_CTRL,RX resistor calibration control register"
bitfld.long 0x00 31. "CMN_RXCAL_OVRD_15,Resistor code override enable: Activation (1'b1) of this register bit allows the resistor codes determined during the automatic resistor calibration process to be overridden" "0,1"
bitfld.long 0x00 30. "CMN_RXCAL_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the cmnda_rescal_en_rx enable and the cmnda_rescal_clk_rx clock" "0,1"
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hexmask.long.word 0x00 21.--29. 1. "CMN_RXCAL_OVRD_13_5,Reserved"
bitfld.long 0x00 16.--20. "CMN_RXCAL_OVRD_4_0,Resistor code override value: These bits are used to override the resistor code determined during the automatic resistor calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "CMN_RXCAL_CTRL_15,Start resistor calibration: Activating (1'b1) this bit will start the resistor calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_RXCAL_CTRL_14,Resistor calibration process done: This bit will be set to 1'b1 when the resistor calibration process is complete" "0,1"
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rbitfld.long 0x00 13. "CMN_RXCAL_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x00 12. "CMN_RXCAL_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (cmnda_rescal_comp_rx)" "0,1"
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hexmask.long.byte 0x00 5.--11. 1. "CMN_RXCAL_CTRL_11_5,Reserved"
rbitfld.long 0x00 0.--4. "CMN_RXCAL_CTRL_4_0,Resistor calibration code: This is the calibration code that was determined by the resistor calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CMN_RXCAL_TUNE__CMN_RXCAL_START,RX resistor calibration start register"
hexmask.long.word 0x04 21.--31. 1. "CMN_RXCAL_TUNE_15_5,Reserved"
bitfld.long 0x04 16.--20. "CMN_RXCAL_TUNE_4_0,Resistor calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 15. "CMN_RXCAL_START_15,Resistor calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.word 0x04 5.--14. 1. "CMN_RXCAL_START_14_5,Reserved"
newline
bitfld.long 0x04 0.--4. "CMN_RXCAL_START_4_0,Start resistor calibration code: This is the calibration code that the resistor calibration process starts with when automatic calibration is run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CMN_RXCAL_ITER_TMR__CMN_RXCAL_INIT_TMR,RX resistor calibration initialization timer register"
rbitfld.long 0x08 28.--31. "CMN_RXCAL_ITER_TMR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 16.--27. 1. "CMN_RXCAL_ITER_TMR_11_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the resistor selection bus going to the analog and when the comparator value coming from the analog circuits can be.."
newline
rbitfld.long 0x08 12.--15. "CMN_RXCAL_INIT_TMR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--11. 1. "CMN_RXCAL_INIT_TMR_11_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog resistor calibration circuits are enabled and when the first resistor selection values are placed on the resistor selection.."
group.long 0x240++0x13
line.long 0x00 "CMN_SD_CAL_START__CMN_SD_CAL_CTRL,Signal detect clock calibration control register"
rbitfld.long 0x00 31. "CMN_SD_CAL_START_15,Reserved" "0,1"
bitfld.long 0x00 28.--30. "CMN_SD_CAL_START_14_12,Calibration initial step size control: This field specifies the initial step size for the calibration state machine" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 21.--27. 1. "CMN_SD_CAL_START_11_5,Reserved"
bitfld.long 0x00 16.--20. "CMN_SD_CAL_START_4_0,Calibration code starting point value: This field specifies the starting code that is used by the calibration state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "CMN_SD_CAL_CTRL_15,Start calibration: Activating (1'b1) this bit will start a calibration process" "0,1"
rbitfld.long 0x00 14. "CMN_SD_CAL_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete" "0,1"
newline
hexmask.long.word 0x00 5.--13. 1. "CMN_SD_CAL_CTRL_13_5,Reserved"
rbitfld.long 0x00 0.--4. "CMN_SD_CAL_CTRL_4_0,Calibration code: This is the calibration code that was determined by the calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CMN_SD_CAL_OVRD__CMN_SD_CAL_TCTRL,Signal detect clock calibration timer control register"
bitfld.long 0x04 31. "CMN_SD_CAL_OVRD_15,Calibration code override enable: Activating (1'b1) this bit allows the code determined during the automatic calibration process to be overridden by the value driven by the calibration code override value field in this register" "0,1"
hexmask.long.word 0x04 21.--30. 1. "CMN_SD_CAL_OVRD_14_5,Reserved"
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bitfld.long 0x04 16.--20. "CMN_SD_CAL_OVRD_4_0,Calibration code override value: This field is used to override the code determined during the automatic calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x04 3.--15. 1. "CMN_SD_CAL_TCTRL_15_3,Reserved"
newline
bitfld.long 0x04 0.--2. "CMN_SD_CAL_TCTRL_2_0,Calibration initial time scale control: This field specifies the calibration start time scaling factor applied to the calibration when running the initial step size for the calibration code is not set to 1" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMN_SD_CAL_ITER_TMR__CMN_SD_CAL_INIT_TMR,Signal detect clock calibration initialization timer register"
hexmask.long.byte 0x08 24.--31. 1. "CMN_SD_CAL_ITER_TMR_15_8,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "CMN_SD_CAL_ITER_TMR_7_0,Iteration wait timer value: This is the number of clocks to wait between when a calibration code is driven to the analog and when the clock rates are measured"
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hexmask.long.byte 0x08 8.--15. 1. "CMN_SD_CAL_INIT_TMR_15_8,Reserved"
hexmask.long.byte 0x08 0.--7. 1. "CMN_SD_CAL_INIT_TMR_7_0,Initialization wait timer value: This is the number of clocks to wait between when the analog calibration circuits are enabled and when the first calibration code is driven to the analog"
line.long 0x0C "CMN_SD_CAL_REFTIM_START,Signal detect clock calibration reference clock timer start value register"
hexmask.long.byte 0x0C 8.--15. 1. "CMN_SD_CAL_REFTIM_START_15_8,Reserved"
hexmask.long.byte 0x0C 0.--7. 1. "CMN_SD_CAL_REFTIM_START_7_0,Calibration reference clock timer start value : This is the value that is loaded into the reference clock timer as the starting point for that timer when running calibration"
line.long 0x10 "CMN_SD_CAL_PLLCNT_START,Signal detect clock calibration PLL clock counter start value register"
rbitfld.long 0x10 10.--15. "CMN_SD_CAL_PLLCNT_START_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x10 0.--9. 1. "CMN_SD_CAL_PLLCNT_START_9_0,Calibration feedback clock counter start value : This is the value that is loaded into the PLL clock counter as the starting point for that counter when running calibration"
group.long 0x300++0x07
line.long 0x00 "CMN_CMSMT_TEST_CLK_SEL__CMN_CMSMT_CLK_FREQ_MSMT_CTRL,Clock frequency measurement control register"
hexmask.long.word 0x00 19.--31. 1. "CMN_CMSMT_TEST_CLK_SEL_15_3,Reserved"
bitfld.long 0x00 16.--18. "CMN_CMSMT_TEST_CLK_SEL_2_0,Test clock select: This field drives the test_clk_select pin in order to control an external MUX for selecting between multiple test clocks to measure" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CMN_CMSMT_CLK_FREQ_MSMT_CTRL_15,Run test clock measurement: Activating (1'b1) this bit will run the test clock measurement process" "0,1"
rbitfld.long 0x00 14. "CMN_CMSMT_CLK_FREQ_MSMT_CTRL_14,Test clock measurement done: This bit will be set to 1'b1 when the test clock measurement process is complete" "0,1"
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hexmask.long.word 0x00 0.--13. 1. "CMN_CMSMT_CLK_FREQ_MSMT_CTRL_13_0,Reserved"
line.long 0x04 "CMN_CMSMT_TEST_CLK_CNT_VALUE__CMN_CMSMT_REF_CLK_TMR_VALUE,Reference clock timer value register"
rbitfld.long 0x04 28.--31. "CMN_CMSMT_TEST_CLK_CNT_VALUE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 16.--27. 1. "CMN_CMSMT_TEST_CLK_CNT_VALUE_11_0,Test clock counter value: When the test clock measurement process is complete the value in this field specifies the number of test clock cycles that were counted in the time specified by the reference clock timer value"
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rbitfld.long 0x04 12.--15. "CMN_CMSMT_REF_CLK_TMR_VALUE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--11. 1. "CMN_CMSMT_REF_CLK_TMR_VALUE_11_0,Reference clock timer value : This specifies the amount of time in reference clock cycles to count test clock cycles"
group.long 0x340++0x0F
line.long 0x00 "CMN_PDIAG_PLL0_CLK_SEL_M0__CMN_PDIAG_PLL0_CTRL_M0,PLL 0 control register mode 0"
bitfld.long 0x00 31. "CMN_PDIAG_PLL0_CLK_SEL_M0_15,PLL 0 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll0_clk_1 from the PLL high speed clock" "0,1"
bitfld.long 0x00 28.--30. "CMN_PDIAG_PLL0_CLK_SEL_M0_14_12,PLL 0 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll0_clk_1 from the PLL high speed clock by driving the cmnda_pll0_clk_1_div_sel signal to the analog" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "CMN_PDIAG_PLL0_CLK_SEL_M0_11_8,PLL 0 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll0_clk_0 and derived reference clock from the PLL high speed clock by driving the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 18.--23. "CMN_PDIAG_PLL0_CLK_SEL_M0_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "CMN_PDIAG_PLL0_CLK_SEL_M0_1_0,PLL 0 clock select: This field selects one of 3 possible high speed output clocks from PLL 0 to drive on the high speed analog clock 0 by driving the cmnda_pll0_clk_sel signal to the analog" "0,1,2,3"
bitfld.long 0x00 12.--15. "CMN_PDIAG_PLL0_CTRL_M0_15_12,This field controls the Ring VCO Frequency drift with temperature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 9.--11. "CMN_PDIAG_PLL0_CTRL_M0_11_9,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "CMN_PDIAG_PLL0_CTRL_M0_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll0_vco_sel signal going into the common analog" "0,1"
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rbitfld.long 0x00 6.--7. "CMN_PDIAG_PLL0_CTRL_M0_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 5. "CMN_PDIAG_PLL0_CTRL_M0_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll0_fb_divider_clk by driving the cmnda_pll0_fb_divider_clk_sel signal going into the common analog" "0,1"
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bitfld.long 0x00 4. "CMN_PDIAG_PLL0_CTRL_M0_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll0_div24_sel signal going into the common analog" "0,1"
rbitfld.long 0x00 2.--3. "CMN_PDIAG_PLL0_CTRL_M0_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x00 0.--1. "CMN_PDIAG_PLL0_CTRL_M0_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD" "0,1,2,3"
line.long 0x04 "CMN_PDIAG_PLL0_ITRIM_M0__CMN_PDIAG_PLL0_OVRD_M0,PLL 0 override register mode 0"
hexmask.long.byte 0x04 24.--31. 1. "CMN_PDIAG_PLL0_ITRIM_M0_15_8,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "CMN_PDIAG_PLL0_ITRIM_M0_7_0,PLL VCO bias current trim code: Controls the tank currents in the PLL LC tank circuit"
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hexmask.long.word 0x04 4.--15. 1. "CMN_PDIAG_PLL0_OVRD_M0_15_4,Reserved"
bitfld.long 0x04 3. "CMN_PDIAG_PLL0_OVRD_M0_3,PLL VCO calibration enable override enable: When active (1'b1) the PLL VCO calibration enable override bit in this register can be used to directly control the enable of the VCO calibration function in the PLL (instead of the.." "0,1"
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bitfld.long 0x04 2. "CMN_PDIAG_PLL0_OVRD_M0_2,PLL VCO calibration enable override: When enabled by the PLL VCO calibration enable override enable bit in this register this bit will directly control the enable of the VCO calibration function in the PLL" "0,1"
bitfld.long 0x04 1. "CMN_PDIAG_PLL0_OVRD_M0_1,PLL phase lock detect enable : Enables the diagnostic PLL phase lock detect function in the analog" "0,1"
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rbitfld.long 0x04 0. "CMN_PDIAG_PLL0_OVRD_M0_0,PLL phase lock detected : When enabled by the PLL phase lock detect enable bit in this register this bit indicates that a PLL phase lock has been detected" "0,1"
line.long 0x08 "CMN_PDIAG_PLL0_CP_IADJ_M0__CMN_PDIAG_PLL0_CP_PADJ_M0,PLL 0 charge pump proportional path adjust register mode 0"
hexmask.long.byte 0x08 24.--31. 1. "CMN_PDIAG_PLL0_CP_IADJ_M0_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll0_cp_int_cap_adj signal going to the analog"
hexmask.long.byte 0x08 16.--23. 1. "CMN_PDIAG_PLL0_CP_IADJ_M0_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll0_cp_int_cur_adj signal going to the analog"
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hexmask.long.byte 0x08 8.--15. 1. "CMN_PDIAG_PLL0_CP_PADJ_M0_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll0_cp_prop_cap_adj signal going to the analog"
hexmask.long.byte 0x08 0.--7. 1. "CMN_PDIAG_PLL0_CP_PADJ_M0_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog"
line.long 0x0C "CMN_PDIAG_PLL0_CP_TUNE_M0__CMN_PDIAG_PLL0_FILT_PADJ_M0,PLL 0 proportional path filter adjust register mode 0"
hexmask.long.word 0x0C 18.--31. 1. "CMN_PDIAG_PLL0_CP_TUNE_M0_15_2,Reserved"
bitfld.long 0x0C 16.--17. "CMN_PDIAG_PLL0_CP_TUNE_M0_1_0,PLL charge pump calibration reference voltage tune: Adjusts the charge pump calibration reference voltage by driving the cmnda_pll0_cp_vref_tune signal going to the analog" "0,1,2,3"
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rbitfld.long 0x0C 12.--15. "CMN_PDIAG_PLL0_FILT_PADJ_M0_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "CMN_PDIAG_PLL0_FILT_PADJ_M0_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll0_filt_c_adj signal going to the analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 4.--7. "CMN_PDIAG_PLL0_FILT_PADJ_M0_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMN_PDIAG_PLL0_FILT_PADJ_M0_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll0_filt_r_adj signal going to the analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x360++0x0F
line.long 0x00 "CMN_PDIAG_PLL0_CLK_SEL_M1__CMN_PDIAG_PLL0_CTRL_M1,PLL 0 control register mode 1"
bitfld.long 0x00 31. "CMN_PDIAG_PLL0_CLK_SEL_M1_15,PLL 0 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll0_clk_1 from the PLL high speed clock" "0,1"
bitfld.long 0x00 28.--30. "CMN_PDIAG_PLL0_CLK_SEL_M1_14_12,PLL 0 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll0_clk_1 from the PLL high speed clock by driving the cmnda_pll0_clk_1_div_sel signal to the analog" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "CMN_PDIAG_PLL0_CLK_SEL_M1_11_8,PLL 0 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll0_clk_0 and derived reference clock from the PLL high speed clock by driving the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 18.--23. "CMN_PDIAG_PLL0_CLK_SEL_M1_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "CMN_PDIAG_PLL0_CLK_SEL_M1_1_0,PLL 0 clock select: This field selects one of 3 possible high speed output clocks from PLL 0 to drive on the high speed analog clock 0 by driving the cmnda_pll0_clk_sel signal to the analog" "0,1,2,3"
bitfld.long 0x00 12.--15. "CMN_PDIAG_PLL0_CTRL_M1_15_12,This field controls the Ring VCO Frequency drift with temperature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 9.--11. "CMN_PDIAG_PLL0_CTRL_M1_11_9,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "CMN_PDIAG_PLL0_CTRL_M1_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll0_vco_sel signal going into the common analog" "0,1"
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rbitfld.long 0x00 6.--7. "CMN_PDIAG_PLL0_CTRL_M1_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 5. "CMN_PDIAG_PLL0_CTRL_M1_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll0_fb_divider_clk driving the cmnda_pll0_fb_divider_clk_sel signal going into the common analog" "0,1"
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bitfld.long 0x00 4. "CMN_PDIAG_PLL0_CTRL_M1_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll0_div24_sel signal going into the common analog" "0,1"
rbitfld.long 0x00 2.--3. "CMN_PDIAG_PLL0_CTRL_M1_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x00 0.--1. "CMN_PDIAG_PLL0_CTRL_M1_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD" "0,1,2,3"
line.long 0x04 "CMN_PDIAG_PLL0_ITRIM_M1__CMN_PDIAG_PLL0_OVRD_M1,PLL 0 override register mode 1"
hexmask.long.byte 0x04 24.--31. 1. "CMN_PDIAG_PLL0_ITRIM_M1_15_8,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "CMN_PDIAG_PLL0_ITRIM_M1_7_0,PLL VCO bias current trim code: Controls the tank currents in the PLL LC tank circuit"
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hexmask.long.word 0x04 4.--15. 1. "CMN_PDIAG_PLL0_OVRD_M1_15_4,Reserved"
bitfld.long 0x04 3. "CMN_PDIAG_PLL0_OVRD_M1_3,PLL VCO calibration enable override enable: When active (1'b1) the PLL VCO calibration enable override bit in this register can be used to directly control the enable of the VCO calibration function in the PLL (instead of the.." "0,1"
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bitfld.long 0x04 2. "CMN_PDIAG_PLL0_OVRD_M1_2,PLL VCO calibration enable override: When enabled by the PLL VCO calibration enable override enable bit in this register this bit will directly control the enable of the VCO calibration function in the PLL" "0,1"
bitfld.long 0x04 1. "CMN_PDIAG_PLL0_OVRD_M1_1,PLL phase lock detect enable : Enables the diagnostic PLL phase lock detect function in the analog" "0,1"
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rbitfld.long 0x04 0. "CMN_PDIAG_PLL0_OVRD_M1_0,PLL phase lock detected : When enabled by the PLL phase lock detect enable bit in this register this bit indicates that a PLL phase lock has been detected" "0,1"
line.long 0x08 "CMN_PDIAG_PLL0_CP_IADJ_M1__CMN_PDIAG_PLL0_CP_PADJ_M1,PLL 0 charge pump proportional path adjust register mode 1"
hexmask.long.byte 0x08 24.--31. 1. "CMN_PDIAG_PLL0_CP_IADJ_M1_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll0_cp_int_cap_adj signal going to the analog"
hexmask.long.byte 0x08 16.--23. 1. "CMN_PDIAG_PLL0_CP_IADJ_M1_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll0_cp_int_cur_adj signal going to the analog"
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hexmask.long.byte 0x08 8.--15. 1. "CMN_PDIAG_PLL0_CP_PADJ_M1_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll0_cp_prop_cap_adj signal going to the analog"
hexmask.long.byte 0x08 0.--7. 1. "CMN_PDIAG_PLL0_CP_PADJ_M1_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll0_cp_prop_cur_adj signal going to the analog"
line.long 0x0C "CMN_PDIAG_PLL0_CP_TUNE_M1__CMN_PDIAG_PLL0_FILT_PADJ_M1,PLL 0 proportional path filter adjust register mode 1"
hexmask.long.word 0x0C 18.--31. 1. "CMN_PDIAG_PLL0_CP_TUNE_M1_15_2,Reserved"
bitfld.long 0x0C 16.--17. "CMN_PDIAG_PLL0_CP_TUNE_M1_1_0,PLL charge pump calibration reference voltage tune: Adjusts the charge pump calibration reference voltage by driving the cmnda_pll0_cp_vref_tune signal going to the analog" "0,1,2,3"
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rbitfld.long 0x0C 12.--15. "CMN_PDIAG_PLL0_FILT_PADJ_M1_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "CMN_PDIAG_PLL0_FILT_PADJ_M1_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll0_filt_c_adj signal going to the analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 4.--7. "CMN_PDIAG_PLL0_FILT_PADJ_M1_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMN_PDIAG_PLL0_FILT_PADJ_M1_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll0_filt_r_adj signal going to the analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x380++0x0F
line.long 0x00 "CMN_PDIAG_PLL1_CLK_SEL_M0__CMN_PDIAG_PLL1_CTRL_M0,PLL 1 control register mode 0"
bitfld.long 0x00 31. "CMN_PDIAG_PLL1_CLK_SEL_M0_15,PLL 1 clock 1 divider enable: This bit enables the divider used to generate the cmnda_pll1_clk_1 from the PLL high speed clock" "0,1"
bitfld.long 0x00 28.--30. "CMN_PDIAG_PLL1_CLK_SEL_M0_14_12,PLL 1 clock 1 divider select: This field selects the divider value used to generate the cmnda_pll1_clk_1 from the PLL high speed clock by driving the cmnda_pll1_clk_1_div_sel signal to the analog" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "CMN_PDIAG_PLL1_CLK_SEL_M0_11_8,PLL 1 clock 0 and derived reference clock divider select: This field selects the divider value used to generate the cmnda_pll1_clk_0 and derived reference clock from the PLL high speed clock by driving the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 18.--23. "CMN_PDIAG_PLL1_CLK_SEL_M0_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "CMN_PDIAG_PLL1_CLK_SEL_M0_1_0,PLL 1 clock select: This field selects one of 3 possible high speed output clocks from PLL 1 to drive on the high speed analog clock 1 by driving the cmnda_pll1_clk_sel signal to the analog" "0,1,2,3"
bitfld.long 0x00 12.--15. "CMN_PDIAG_PLL1_CTRL_M0_15_12,This field controls the Ring VCO Frequency drift with temperature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 9.--11. "CMN_PDIAG_PLL1_CTRL_M0_11_9,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "CMN_PDIAG_PLL1_CTRL_M0_8,PLL VCO select: Selects the VCO mode of operation by driving the cmnda_pll1_vco_sel signal going into the common analog" "0,1"
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rbitfld.long 0x00 6.--7. "CMN_PDIAG_PLL1_CTRL_M0_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 5. "CMN_PDIAG_PLL1_CTRL_M0_5,PLL feedback divider clock select: This signal selects which internal PLL clock will be used to drive the cmnda_pll1_fb_divider_clk driving the cmnda_pll1_fb_divider_clk_sel signal going into the common analog" "0,1"
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bitfld.long 0x00 4. "CMN_PDIAG_PLL1_CTRL_M0_4,PLL feedback divider pre-scale: controls the feedback divider pre-scale by driving the cmnda_pll1_div24_sel signal going into the common analog" "0,1"
rbitfld.long 0x00 2.--3. "CMN_PDIAG_PLL1_CTRL_M0_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x00 0.--1. "CMN_PDIAG_PLL1_CTRL_M0_1_0,PLL PFD reset delay: Controls the minimum reset pulse width for the PFD" "0,1,2,3"
line.long 0x04 "CMN_PDIAG_PLL1_ITRIM_M0__CMN_PDIAG_PLL1_OVRD_M0,PLL 1 override register mode 0"
hexmask.long.byte 0x04 24.--31. 1. "CMN_PDIAG_PLL1_ITRIM_M0_15_8,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "CMN_PDIAG_PLL1_ITRIM_M0_7_0,PLL VCO bias current trim code: Controls the tank currents in the PLL LC tank circuit"
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hexmask.long.word 0x04 4.--15. 1. "CMN_PDIAG_PLL1_OVRD_M0_15_4,Reserved"
bitfld.long 0x04 3. "CMN_PDIAG_PLL1_OVRD_M0_3,PLL VCO calibration enable override enable: When active (1'b1) the PLL VCO calibration enable override bit in this register can be used to directly control the enable of the VCO calibration function in the PLL (instead of the.." "0,1"
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bitfld.long 0x04 2. "CMN_PDIAG_PLL1_OVRD_M0_2,PLL VCO calibration enable override: When enabled by the PLL VCO calibration enable override enable bit in this register this bit will directly control the enable of the VCO calibration function in the PLL" "0,1"
bitfld.long 0x04 1. "CMN_PDIAG_PLL1_OVRD_M0_1,PLL phase lock detect enable : Enables the diagnostic PLL phase lock detect function in the analog" "0,1"
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rbitfld.long 0x04 0. "CMN_PDIAG_PLL1_OVRD_M0_0,PLL phase lock detected : When enabled by the PLL phase lock detect enable bit in this register this bit indicates that a PLL phase lock has been detected" "0,1"
line.long 0x08 "CMN_PDIAG_PLL1_CP_IADJ_M0__CMN_PDIAG_PLL1_CP_PADJ_M0,PLL 1 charge pump proportional path adjust register mode 0"
hexmask.long.byte 0x08 24.--31. 1. "CMN_PDIAG_PLL1_CP_IADJ_M0_15_8,PLL charge pump integral path capacitance adjust: Adjusts the charge pump integral path capacitance by driving the cmnda_pll1_cp_int_cap_adj signal going to the analog"
hexmask.long.byte 0x08 16.--23. 1. "CMN_PDIAG_PLL1_CP_IADJ_M0_7_0,PLL charge pump integral path current adjust: Adjusts the charge pump integral path current by driving the cmnda_pll1_cp_int_cur_adj signal going to the analog"
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hexmask.long.byte 0x08 8.--15. 1. "CMN_PDIAG_PLL1_CP_PADJ_M0_15_8,PLL charge pump proportional path capacitance adjust: Adjusts the charge pump proportional path capacitance by driving the cmnda_pll1_cp_prop_cap_adj signal going to the analog"
hexmask.long.byte 0x08 0.--7. 1. "CMN_PDIAG_PLL1_CP_PADJ_M0_7_0,PLL charge pump proportional path current adjust: Adjusts the charge pump proportional path current by driving the cmnda_pll1_cp_prop_cur_adj signal going to the analog"
line.long 0x0C "CMN_PDIAG_PLL1_CP_TUNE_M0__CMN_PDIAG_PLL1_FILT_PADJ_M0,PLL 1 proportional path filter adjust register mode 0"
hexmask.long.word 0x0C 18.--31. 1. "CMN_PDIAG_PLL1_CP_TUNE_M0_15_2,Reserved"
bitfld.long 0x0C 16.--17. "CMN_PDIAG_PLL1_CP_TUNE_M0_1_0,PLL charge pump calibration reference voltage tune: Adjusts the charge pump calibration reference voltage by driving the cmnda_pll1_cp_vref_tune signal going to the analog" "0,1,2,3"
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rbitfld.long 0x0C 12.--15. "CMN_PDIAG_PLL1_FILT_PADJ_M0_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "CMN_PDIAG_PLL1_FILT_PADJ_M0_11_8,PLL proportional path filter capacitance adjust: Adjusts the proportional path filter capacitance by driving the cmnda_pll1_filt_c_adj signal going to the analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x0C 4.--7. "CMN_PDIAG_PLL1_FILT_PADJ_M0_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMN_PDIAG_PLL1_FILT_PADJ_M0_3_0,PLL proportional path filter resistance adjust: Adjusts the proportional path filter resistance by driving the cmnda_pll1_filt_r_adj signal going to the analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C0++0x1F
line.long 0x00 "CMN_DIAG_BIAS_OVRD1__CMN_DIAG_BANDGAP_OVRD,Bandgap override register"
rbitfld.long 0x00 31. "CMN_DIAG_BIAS_OVRD1_15,Reserved" "0,1"
bitfld.long 0x00 28.--30. "CMN_DIAG_BIAS_OVRD1_14_12,Receiver resistor calibration current adjust: This field is used to adjust the receiver resistor calibration bias current" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "CMN_DIAG_BIAS_OVRD1_11,Reserved" "0,1"
bitfld.long 0x00 24.--26. "CMN_DIAG_BIAS_OVRD1_10_8,Transmitter resistor calibration current adjust: This field is used to adjust the transmitter resistor calibration bias current" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20.--23. "CMN_DIAG_BIAS_OVRD1_7_4,Reserved - spare" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 17.--19. "CMN_DIAG_BIAS_OVRD1_3_1,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "CMN_DIAG_BIAS_OVRD1_0,Reserved - spare" "0,1"
rbitfld.long 0x00 12.--15. "CMN_DIAG_BANDGAP_OVRD_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 8.--11. "CMN_DIAG_BANDGAP_OVRD_11_8,Bandgap startup circuit startup count : Identifies the status of the bandgap startup counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 5.--7. "CMN_DIAG_BANDGAP_OVRD_7_5,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "CMN_DIAG_BANDGAP_OVRD_4,Bandgap startup circuit select : Selects the startup circuit to be used for the bias / bandgap circuits by driving the cmnda_bias_bg_start_sel signal going to the analog" "0,1"
bitfld.long 0x00 2.--3. "CMN_DIAG_BANDGAP_OVRD_3_2,Bandgap startup circuit sense voltage adjust : This field is used to adjust the bandgap startup circuit sense voltage by driving the cmnda_bias_bg_start_adj signal to the analog" "0,1,2,3"
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bitfld.long 0x00 0.--1. "CMN_DIAG_BANDGAP_OVRD_1_0,Bandgap voltage adjust : This field is used to adjust the bandgap voltage by driving the cmnda_bias_bg_adj signal to the analog" "0,1,2,3"
line.long 0x04 "CMN_DIAG_VREG_CTRL__CMN_DIAG_BIAS_OVRD2,Bias override register 2"
hexmask.long.word 0x04 17.--31. 1. "CMN_DIAG_VREG_CTRL_15_1,Reserved"
bitfld.long 0x04 16. "CMN_DIAG_VREG_CTRL_0,Voltage regulator reference voltage select: Selects the reference voltage used for the voltage regulator in common by driving the cmnda_vreg_ref_sel signal to the analog" "0,1"
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hexmask.long.word 0x04 6.--15. 1. "CMN_DIAG_BIAS_OVRD2_15_6,Reserved"
bitfld.long 0x04 5. "CMN_DIAG_BIAS_OVRD2_5,Bias filter bypass enable override enable: When active (1'b1) the bias filter bypass enable override bit in this register can be used to directly control the bias filter bypass enable function" "0,1"
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bitfld.long 0x04 4. "CMN_DIAG_BIAS_OVRD2_4,Bias filter bypass enable override: When enabled by the bias filter bypass enable override enable bit in this register this bit will directly control the bias filter bypass enable function" "0,1"
rbitfld.long 0x04 2.--3. "CMN_DIAG_BIAS_OVRD2_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x04 0.--1. "CMN_DIAG_BIAS_OVRD2_1_0,Regulator bandgap reference voltage adjust: This field is used to adjust the regulator bandgap reference voltage by driving the cmnda_bias_vreg_adj signal to the analog" "0,1,2,3"
line.long 0x08 "CMN_DIAG_SH_BANDGAP__CMN_DIAG_PM_CTRL,Common process monitor control register"
hexmask.long.word 0x08 22.--31. 1. "CMN_DIAG_SH_BANDGAP_15_6,Reserved"
rbitfld.long 0x08 21. "CMN_DIAG_SH_BANDGAP_5,Bandgap up value: Bandgap calibration up signal value as it is currently captured in the sample and hold latches" "0,1"
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rbitfld.long 0x08 16.--20. "CMN_DIAG_SH_BANDGAP_4_0,Bandgap auto zero select value: Bandgap calibration auto zero select signal value as it is currently captured in the sample and hold latches" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 5.--15. 1. "CMN_DIAG_PM_CTRL_15_5,Reserved"
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bitfld.long 0x08 4. "CMN_DIAG_PM_CTRL_4,Process monitor enable: Enables the analog process monitor by driving the cmnda_pcm_en signal to the analog" "0,1"
rbitfld.long 0x08 3. "CMN_DIAG_PM_CTRL_3,Reserved" "0,1"
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bitfld.long 0x08 0.--2. "CMN_DIAG_PM_CTRL_2_0,Process monitor mode select: Selects the mode of the analog process monitor by driving the cmnda_pcm_sel signal to the analog" "0,1,2,3,4,5,6,7"
line.long 0x0C "CMN_DIAG_SH_SDCLK__CMN_DIAG_SH_RESISTOR,Sample and hold resistor calibration code register"
hexmask.long.word 0x0C 21.--31. 1. "CMN_DIAG_SH_SDCLK_15_5,Reserved"
bitfld.long 0x0C 16.--20. "CMN_DIAG_SH_SDCLK_4_0,Signal detect clock code: Signal detect clock calibration code signal value as it is currently captured in the sample and hold latches" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 14.--15. "CMN_DIAG_SH_RESISTOR_15_14,Reserved" "0,1,2,3"
bitfld.long 0x0C 8.--13. "CMN_DIAG_SH_RESISTOR_13_8,TX resistor code: TX resistor calibration code signal value as it is currently captured in the sample and hold latches" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 4.--7. "CMN_DIAG_SH_RESISTOR_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMN_DIAG_SH_RESISTOR_3_0,RX resistor code: RX resistor calibration code signal value as it is currently captured in the sample and hold latches" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CMN_DIAG_ATB_CTRL2__CMN_DIAG_ATB_CTRL1,ATB control register 1"
rbitfld.long 0x10 29.--31. "CMN_DIAG_ATB_CTRL2_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 27.--28. "CMN_DIAG_ATB_CTRL2_12_11,ATB component type select: These bits specify which component type is currently selected by the ATB as specified below" "0,1,2,3"
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bitfld.long 0x10 22.--26. "CMN_DIAG_ATB_CTRL2_10_6,ATB component sub address: Specifies the sub address of the component being selected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--21. "CMN_DIAG_ATB_CTRL2_5_0,ATB test point address: Specifies the exact point in the selected analog component to be observed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x10 2.--15. 1. "CMN_DIAG_ATB_CTRL1_15_2,Reserved"
bitfld.long 0x10 1. "CMN_DIAG_ATB_CTRL1_1,Core side ATB enable: When active (1'b) and the ATB enable bit in this register is also active the ATB signals will be driven on the core side ATB signals" "0,1"
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bitfld.long 0x10 0. "CMN_DIAG_ATB_CTRL1_0,ATB enable: When active (1'b1) the ATB test function is enabled" "0,1"
line.long 0x14 "CMN_DIAG_ATB_ADC_CTRL1__CMN_DIAG_ATB_ADC_CTRL0,ATB ADC control register 0"
rbitfld.long 0x14 30.--31. "CMN_DIAG_ATB_ADC_CTRL1_15_14,Reserved" "0,1,2,3"
bitfld.long 0x14 29. "CMN_DIAG_ATB_ADC_CTRL1_13,ATB ADC offset correction enable : Enables internal auto generated offset correction mode by driving the cmnda_atba2d_en_off_cor signal to the analog" "0,1"
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bitfld.long 0x14 28. "CMN_DIAG_ATB_ADC_CTRL1_12,ATB ADC force cap values : Forces a positive or negative voltage on the internal cap by driving the cmnda_atba2d_frc_val signal to the analog" "0,1"
bitfld.long 0x14 27. "CMN_DIAG_ATB_ADC_CTRL1_11,ATB ADC enable manual offset correction : When this signal is active the value in the ATB ADC manual offset correction value field of this register is used to manually control the offset correction by driving the.." "0,1"
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rbitfld.long 0x14 25.--26. "CMN_DIAG_ATB_ADC_CTRL1_10_9,Reserved" "0,1,2,3"
bitfld.long 0x14 20.--24. "CMN_DIAG_ATB_ADC_CTRL1_8_4,ATB ADC manual offset correction value : When the ATB ADC enable manual offset correction bit in this register is active this field is used to manually control the offset correction by driving the cmnda_atba2d_off_adj_byp.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 16.--19. "CMN_DIAG_ATB_ADC_CTRL1_3_0,ATB ADC mode : This field indicates the mode the analog to digital converter is in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. "CMN_DIAG_ATB_ADC_CTRL0_15,ATB analog ADC enable: This enables the analog ADC function by driving the cmnda_atba2d_en signal to the analog" "0,1"
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bitfld.long 0x14 14. "CMN_DIAG_ATB_ADC_CTRL0_14,Start ATB ADC process: Activating (1'b1) this bit will start the ATB ADC process" "0,1"
rbitfld.long 0x14 13. "CMN_DIAG_ATB_ADC_CTRL0_13,ATB ADC process done: This bit will be set to 1'b1 when the ATB ADC process is complete and the data in the ATB ADC code field of this register is considered valid" "0,1"
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rbitfld.long 0x14 8.--12. "CMN_DIAG_ATB_ADC_CTRL0_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 0.--7. 1. "CMN_DIAG_ATB_ADC_CTRL0_7_0,ATB ADC data code: This is the digital code representing the level of the analog ATB signal that was digitized by the analog ADC"
line.long 0x18 "CMN_DIAG_RST_DIAG__CMN_DIAG_HSRRSM_CTRL,Common high speed reset release state machine control register"
rbitfld.long 0x18 28.--31. "CMN_DIAG_RST_DIAG_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x18 27. "CMN_DIAG_RST_DIAG_11,Current state of the cmn_sd_clk_cal_fb_clk_reset_n reset" "0,1"
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rbitfld.long 0x18 26. "CMN_DIAG_RST_DIAG_10,Current state of the cmn_sd_clk_cal_ref_clk_reset_n reset" "0,1"
rbitfld.long 0x18 25. "CMN_DIAG_RST_DIAG_9,Current state of the cmn_pll1_dsm_reset_n reset" "0,1"
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rbitfld.long 0x18 24. "CMN_DIAG_RST_DIAG_8,Current state of the cmn_pll0_dsm_reset_n reset" "0,1"
rbitfld.long 0x18 23. "CMN_DIAG_RST_DIAG_7,Current state of the cmn_pll1_vco_cal_fbdiv_clk_reset_n reset" "0,1"
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rbitfld.long 0x18 22. "CMN_DIAG_RST_DIAG_6,Current state of the cmn_pll1_lock_det_fbdiv_clk_reset_n reset" "0,1"
rbitfld.long 0x18 21. "CMN_DIAG_RST_DIAG_5,Current state of the cmn_pll1_vco_cal_ref_clk_reset_n reset" "0,1"
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rbitfld.long 0x18 20. "CMN_DIAG_RST_DIAG_4,Current state of the cmn_pll1_lock_det_ref_clk_reset_n reset" "0,1"
rbitfld.long 0x18 19. "CMN_DIAG_RST_DIAG_3,Current state of the cmn_pll0_vco_cal_fbdiv_clk_reset_n reset" "0,1"
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rbitfld.long 0x18 18. "CMN_DIAG_RST_DIAG_2,Current state of the cmn_pll0_lock_det_fbdiv_clk_reset_n reset" "0,1"
rbitfld.long 0x18 17. "CMN_DIAG_RST_DIAG_1,Current state of the cmn_pll0_vco_cal_ref_clk_reset_n reset" "0,1"
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rbitfld.long 0x18 16. "CMN_DIAG_RST_DIAG_0,Current state of the cmn_pll0_lock_det_ref_clk_reset_n reset" "0,1"
hexmask.long.word 0x18 7.--15. 1. "CMN_DIAG_HSRRSM_CTRL_15_7,Reserved"
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bitfld.long 0x18 4.--6. "CMN_DIAG_HSRRSM_CTRL_6_4,Transceiver reset delay : Species the number of PSM clock cycles the transceiver common high speed reset state machine stays in the delay state" "0,1,2,3,4,5,6,7"
rbitfld.long 0x18 3. "CMN_DIAG_HSRRSM_CTRL_3,Reserved" "0,1"
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bitfld.long 0x18 0.--2. "CMN_DIAG_HSRRSM_CTRL_2_0,Transmitter reset delay : Species the number of PSM clock cycles the transmitter common high speed reset state machine stays in the delay state" "0,1,2,3,4,5,6,7"
line.long 0x1C "CMN_DIAG_ACYA__CMN_DIAG_DCYA,Common digital functions cover your alternatives register"
hexmask.long.byte 0x1C 24.--31. 1. "CMN_DIAG_ACYA_15_8,Reserved"
bitfld.long 0x1C 20.--23. "CMN_DIAG_ACYA_7_4,Reserved - spare" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "CMN_DIAG_ACYA_3_0,PLL charge pump proportional gain adjust: Adjusts the charge pump gain for the PLLs to help manage bandwidth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1C 8.--15. 1. "CMN_DIAG_DCYA_15_8,Reserved"
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hexmask.long.byte 0x1C 0.--7. 1. "CMN_DIAG_DCYA_7_0,Reserved - spare"
rgroup.long 0x400++0x13
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the WIZmodule"
bitfld.long 0x00 30.--31. "SCHEME,Module Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Module BU" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SERDES_CTRL,Sets the SERDES control state"
bitfld.long 0x04 31. "POR_EN,The POR_EN allows the system to place the SERDES in a reset state Access to the SERDES registers are ignored" "0,1"
line.long 0x08 "SERDES_TOP_CTRL,The SERDES Top Level Control"
bitfld.long 0x08 30.--31. "PMA_CMN_REFCLK_MODE,The PMA common differential reference clock mode - Sets the mode of operation for differential reference clock input" "0,1,2,3"
bitfld.long 0x08 28.--29. "PMA_CMN_REFCLK_INT_MODE,The PMA common internal reference clock mode - Sets the mode of operation for internal reference clock input" "0,1,2,3"
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bitfld.long 0x08 26.--27. "PMA_CMN_REFCLK_DIG_DIV,The PMA common reference clock digital divide ratio select - Must be set before the de-assertion of apb_preset_n/phy_reset_n" "0,1,2,3"
bitfld.long 0x08 23. "PHY_PMA_SUSPEND_OVERRIDE,The PHY PMA common suspend override enable" "0,1"
line.long 0x0C "SERDES_RST,The SERDES Reset Register controls the Phy reset and REFCLK selection for the SERDES"
bitfld.long 0x0C 31. "PHY_RESET_N,The PHY reset : Asserting this signal low will reset all PHY logic for the entire PHY with the exception of the APB registers and TAP controller" "0,1"
bitfld.long 0x0C 30. "PHY_EN_REFCLK,The PHY reference clock enable: When cmn_refclk_<p/m> is configured as a reference clock output " "0,1"
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bitfld.long 0x0C 29. "PLL1_REFCLK_SEL,The PMA common PLL1 reference clock source select" "0,1"
bitfld.long 0x0C 28. "PLL0_REFCLK_SEL,The PMA common PLL0 reference clock source select" "0,1"
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bitfld.long 0x0C 27. "REFCLK_TERM_DIS,The PMA common differential reference clock termination disable - enables/disables termination for difference reference clock input (cmn_refclk_<p/m>)" "0,1"
bitfld.long 0x0C 24. "REFCLK_DIG_SEL,The PMA common reference clock select - Selects the reference clock source for the digital logic between cmn_refclk_<p/m> and pma_cmn_refclk_int" "0,1"
line.long 0x10 "SERDES_TYPEC,The SERDES Type C control register allows the external lanes selection to be swapped"
bitfld.long 0x10 31. "LN23_SWAP,The~iln23_swap will swap the lanes 2 and 3" "0,1"
bitfld.long 0x10 30. "LN10_SWAP,The ~iln10_swap will swap the lanes 0 and 1" "0,1"
group.long 0x480++0x0F
line.long 0x00 "LANECTL0,The Lane Control Register sets the lane specific modes of operation"
bitfld.long 0x00 31. "P0_ENABLE,The p0_enable is AND'd with the IPx_LNy_reset_n to enable the lane" "0,1"
bitfld.long 0x00 30. "P0_FORCE_ENABLE,The p0_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane" "0,1"
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bitfld.long 0x00 29. "P0_ALIGN,The p0_align will auto align the RAW interface to 8B10B comma characters" "0,1"
bitfld.long 0x00 28. "P0_RAW_AUTO_START,The p0_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1"
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bitfld.long 0x00 24.--25. "P0_STANDARD_MODE,Standard Mode" "0,1,2,3"
bitfld.long 0x00 22.--23. "P0_FULLRT_DIV,Full Rate divider for 2x MAC speed mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. "P0_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*" "0,1,2,3"
bitfld.long 0x00 18.--19. "P0_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal" "0,1,2,3"
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bitfld.long 0x00 8.--9. "P0_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal" "0,1,2,3"
bitfld.long 0x00 6.--7. "P0_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal" "0,1,2,3"
line.long 0x04 "LANEDIV0,The Lane Divider Register sets the lane specific dividers of"
hexmask.long.byte 0x04 16.--22. 1. "P0_MAC_DIV_SEL0,The reg_p0_mac_div_sel0 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*"
hexmask.long.word 0x04 0.--8. 1. "P0_MAC_DIV_SEL1,The reg_p0_mac_div_sel1 controls the divider for lane 0 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*"
line.long 0x08 "LANALIGN0,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode"
bitfld.long 0x08 0.--5. "P0_ALIGN_RX_DELAY,The reg_p0_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "LANESTS0,The lane Status reports the lane state information for debug purposes"
bitfld.long 0x0C 1. "P0_MASTER,The reg_p0_master indicates the lane is a base lane for a multi lane link" "0,1"
group.long 0x4C0++0x0F
line.long 0x00 "LANECTL1,The Lane Control Register sets the lane specific modes of operation"
bitfld.long 0x00 31. "P1_ENABLE,The p1_enable is AND'd with the IPx_LNy_reset_n to enable the lane" "0,1"
bitfld.long 0x00 30. "P1_FORCE_ENABLE,The p1_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane" "0,1"
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bitfld.long 0x00 29. "P1_ALIGN,The p1_align will auto align the RAW interface to 8B10B comma characters" "0,1"
bitfld.long 0x00 28. "P1_RAW_AUTO_START,The p1_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1"
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bitfld.long 0x00 24.--25. "P1_STANDARD_MODE,Standard Mode" "0,1,2,3"
bitfld.long 0x00 22.--23. "P1_FULLRT_DIV,Full Rate divider for 2x MAC speed mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. "P1_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*" "0,1,2,3"
bitfld.long 0x00 18.--19. "P1_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal" "0,1,2,3"
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bitfld.long 0x00 8.--9. "P1_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal" "0,1,2,3"
bitfld.long 0x00 6.--7. "P1_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal" "0,1,2,3"
line.long 0x04 "LANEDIV1,The Lane Divider Register sets the lane specific dividers of"
hexmask.long.byte 0x04 16.--22. 1. "P1_MAC_DIV_SEL0,The reg_p1_mac_div_sel0 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*"
hexmask.long.word 0x04 0.--8. 1. "P1_MAC_DIV_SEL1,The reg_p1_mac_div_sel1 controls the divider for lane 1 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*"
line.long 0x08 "LANALIGN1,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode"
bitfld.long 0x08 0.--5. "P1_ALIGN_RX_DELAY,The reg_p1_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "LANESTS1,The lane Status reports the lane state information for debug purposes"
bitfld.long 0x0C 1. "P1_MASTER,The reg_p1_master indicates the lane is a base lane for a multi lane link" "0,1"
group.long 0x500++0x0F
line.long 0x00 "LANECTL2,The Lane Control Register sets the lane specific modes of operation"
bitfld.long 0x00 31. "P2_ENABLE,The p2_enable is AND'd with the IPx_LNy_reset_n to enable the lane" "0,1"
bitfld.long 0x00 30. "P2_FORCE_ENABLE,The p2_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane" "0,1"
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bitfld.long 0x00 29. "P2_ALIGN,The p2_align will auto align the RAW interface to 8B10B comma characters" "0,1"
bitfld.long 0x00 28. "P2_RAW_AUTO_START,The p2_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1"
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bitfld.long 0x00 24.--25. "P2_STANDARD_MODE,Standard Mode" "0,1,2,3"
bitfld.long 0x00 22.--23. "P2_FULLRT_DIV,Full Rate divider for 2x MAC speed mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. "P2_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*" "0,1,2,3"
bitfld.long 0x00 18.--19. "P2_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal" "0,1,2,3"
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bitfld.long 0x00 8.--9. "P2_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal" "0,1,2,3"
bitfld.long 0x00 6.--7. "P2_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal" "0,1,2,3"
line.long 0x04 "LANEDIV2,The Lane Divider Register sets the lane specific dividers of"
hexmask.long.byte 0x04 16.--22. 1. "P2_MAC_DIV_SEL0,The reg_p2_mac_div_sel0 controls the divider for lane 2 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*"
hexmask.long.word 0x04 0.--8. 1. "P2_MAC_DIV_SEL1,The reg_p2_mac_div_sel1 controls the divider for lane 2 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*"
line.long 0x08 "LANALIGN2,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode"
bitfld.long 0x08 0.--5. "P2_ALIGN_RX_DELAY,The reg_p2_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "LANESTS2,The lane Status reports the lane state information for debug purposes"
bitfld.long 0x0C 1. "P2_MASTER,The reg_p2_master indicates the lane is a base lane for a multi lane link" "0,1"
group.long 0x540++0x0F
line.long 0x00 "LANECTL3,The Lane Control Register sets the lane specific modes of operation"
bitfld.long 0x00 31. "P3_ENABLE,The p3_enable is AND'd with the IPx_LNy_reset_n to enable the lane" "0,1"
bitfld.long 0x00 30. "P3_FORCE_ENABLE,The p3_force_enable is OR'd with the IPx_LNy_reset_n to force enable the lane" "0,1"
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bitfld.long 0x00 29. "P3_ALIGN,The p3_align will auto align the RAW interface to 8B10B comma characters" "0,1"
bitfld.long 0x00 28. "P3_RAW_AUTO_START,The p3_raw_auto_start will auto sequence the RAW interface according to the configuration settings" "0,1"
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bitfld.long 0x00 24.--25. "P3_STANDARD_MODE,Standard Mode" "0,1,2,3"
bitfld.long 0x00 22.--23. "P3_FULLRT_DIV,Full Rate divider for 2x MAC speed mode" "0,1,2,3"
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bitfld.long 0x00 20.--21. "P3_MAC_SRC_SEL,MAC clock source select : Selects which PMA clock to use as clock souse for pcs_mac_clk*_ln_*" "0,1,2,3"
bitfld.long 0x00 18.--19. "P3_REFCLK_SEL,Refclk Select determines which clocks will be used for the IP refclk signal" "0,1,2,3"
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bitfld.long 0x00 8.--9. "P3_TXFCLK_SEL,Fclk Select determines which clocks will be used for the IP txfclk signal" "0,1,2,3"
bitfld.long 0x00 6.--7. "P3_RXFCLK_SEL,Fclk Select determines which clocks will be used for the IP rxfclk signal" "0,1,2,3"
line.long 0x04 "LANEDIV3,The Lane Divider Register sets the lane specific dividers of"
hexmask.long.byte 0x04 16.--22. 1. "P3_MAC_DIV_SEL0,The reg_p3_mac_div_sel0 controls the divider for lane 3 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx0_ln_*"
hexmask.long.word 0x04 0.--8. 1. "P3_MAC_DIV_SEL1,The reg_p3_mac_div_sel1 controls the divider for lane 3 MAC clock divider ratio select : Selects the divider ratio for pcs_mac_clk_divx1_ln_*"
line.long 0x08 "LANALIGN3,The Lane Align reports the 8B10B alignment delay from the Comma aligner when 8B10B protocol is used in RAW mode"
bitfld.long 0x08 0.--5. "P3_ALIGN_RX_DELAY,The reg_p3_align_rx_delay indicates the number of bits that are added to align the data to an 8B10B alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "LANESTS3,The lane Status reports the lane state information for debug purposes"
bitfld.long 0x0C 1. "P3_MASTER,The reg_p3_master indicates the lane is a base lane for a multi lane link" "0,1"
group.long 0x5F8++0x07
line.long 0x00 "DTB_MUX_SEL,The digital test bus mux select determines the value on the test bus"
bitfld.long 0x00 0.--4. "DTB_MUX_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DIAG_TEST,The Diagnostic Test Register allows the system to validate the read and write of all data bits"
group.long 0x4000++0x2B
line.long 0x00 "XCVR_PSM_RCTRL__XCVR_PSM_CTRL_j,Power state machine control register Offset = 4000h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "XCVR_PSM_RCTRL_15,RX reset active ready : Controls the state the receiver reset is changed to when in the ready power state" "0,1"
bitfld.long 0x00 30. "XCVR_PSM_RCTRL_14,RX reset active calibration : Controls the state the receiver reset is changed to when in the calibration power state" "0,1"
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bitfld.long 0x00 29. "XCVR_PSM_RCTRL_13,RX reset active A5 : Controls the state the receiver reset is changed to when in the A5 entry power state" "0,1"
bitfld.long 0x00 28. "XCVR_PSM_RCTRL_12,RX reset active A4 : Controls the state the receiver reset is changed to when in the A4 entry power state" "0,1"
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bitfld.long 0x00 27. "XCVR_PSM_RCTRL_11,RX reset active A3 : Controls the state the receiver reset is changed to when in the A3 entry power state" "0,1"
bitfld.long 0x00 26. "XCVR_PSM_RCTRL_10,RX reset active A2 : Controls the state the receiver reset is changed to when in the A2 entry power state" "0,1"
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bitfld.long 0x00 25. "XCVR_PSM_RCTRL_9,RX reset active A1 : Controls the state the receiver reset is changed to when in the A1 entry power state" "0,1"
bitfld.long 0x00 24. "XCVR_PSM_RCTRL_8,RX reset active A0 : Controls the state the receiver reset is changed to when in the A0 entry power state" "0,1"
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bitfld.long 0x00 23. "XCVR_PSM_RCTRL_7,TX reset active ready : Controls the state the transmitter reset is changed to when in the ready power state" "0,1"
bitfld.long 0x00 22. "XCVR_PSM_RCTRL_6,TX reset active calibration : Controls the state the transmitter reset is changed to when in the calibration power state" "0,1"
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bitfld.long 0x00 21. "XCVR_PSM_RCTRL_5,TX reset active A5 : Controls the state the transmitter reset is changed to when in the A5 entry power state" "0,1"
bitfld.long 0x00 20. "XCVR_PSM_RCTRL_4,TX reset active A4 : Controls the state the transmitter reset is changed to when in the A4 entry power state" "0,1"
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bitfld.long 0x00 19. "XCVR_PSM_RCTRL_3,TX reset active A3 : Controls the state the transmitter reset is changed to when in the A3 entry power state" "0,1"
bitfld.long 0x00 18. "XCVR_PSM_RCTRL_2,TX reset active A2 : Controls the state the transmitter reset is changed to when in the A2 entry power state" "0,1"
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bitfld.long 0x00 17. "XCVR_PSM_RCTRL_1,TX reset active A1 : Controls the state the transmitter reset is changed to when in the A1 entry power state" "0,1"
bitfld.long 0x00 16. "XCVR_PSM_RCTRL_0,TX reset active A0 : Controls the state the transmitter reset is changed to when in the A0 entry power state" "0,1"
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rbitfld.long 0x00 15. "XCVR_PSM_CTRL_15,Reserved" "0,1"
bitfld.long 0x00 14. "XCVR_PSM_CTRL_14,Bypass A0 in delay from PSM ready : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the PSM ready state to the A0 power state" "0,1"
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bitfld.long 0x00 13. "XCVR_PSM_CTRL_13,Bypass A0 in delay from A5 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A5 to the A0 power state" "0,1"
bitfld.long 0x00 12. "XCVR_PSM_CTRL_12,Bypass A0 in delay from A4 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A4 to the A0 power state" "0,1"
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bitfld.long 0x00 11. "XCVR_PSM_CTRL_11,Bypass A0 in delay from A3 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A3 to the A0 power state" "0,1"
bitfld.long 0x00 10. "XCVR_PSM_CTRL_10,Bypass A0 in delay from A2 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A2 to the A0 power state" "0,1"
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bitfld.long 0x00 9. "XCVR_PSM_CTRL_9,Bypass A0 in delay from A1 : When this bit is active (1'b1) the A0 input delay is bypassed when transitioning from the A1 to the A0 power state" "0,1"
rbitfld.long 0x00 8. "XCVR_PSM_CTRL_8,Reserved" "0,1"
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hexmask.long.byte 0x00 1.--7. 1. "XCVR_PSM_CTRL_7_1,Reserved"
bitfld.long 0x00 0. "XCVR_PSM_CTRL_0,Reserved - spare (must remain set to 1'b1)" "0,1"
line.long 0x04 "XCVR_PSM_A0IN_TMR__XCVR_PSM_CALIN_TMR_j,PSM calibration in delay timer register Offset = 4004h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 28.--31. "XCVR_PSM_A0IN_TMR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 16.--27. 1. "XCVR_PSM_A0IN_TMR_11_0,A0 in delay state timer value : Value used for the timer when the power state machine is in the A0 in delay state unless the timer is bypassed under the control of the bypass A0 bits in the Power state machine control register"
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rbitfld.long 0x04 12.--15. "XCVR_PSM_CALIN_TMR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--11. 1. "XCVR_PSM_CALIN_TMR_11_0,PSM calibration in delay state timer value : Value used for the timer when the power state machine is in the PSM calibration in delay state"
line.long 0x08 "XCVR_PSM_A1IN_TMR__XCVR_PSM_A0BYP_TMR_j,A0 in bypass timer register Offset = 4008h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 22.--31. 1. "XCVR_PSM_A1IN_TMR_15_6,Reserved"
bitfld.long 0x08 16.--21. "XCVR_PSM_A1IN_TMR_5_0,A1 in delay state timer value : Value used for the timer when the power state machine is in the A1 in delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 6.--15. 1. "XCVR_PSM_A0BYP_TMR_15_6,Reserved"
bitfld.long 0x08 0.--5. "XCVR_PSM_A0BYP_TMR_5_0,A0 in delay state bypass timer value : Value used for the timer when the power state machine is in the A0 in delay state and the timer is bypassed under the control of the bypass A0 bits in the Power state machine control register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "XCVR_PSM_A3IN_TMR__XCVR_PSM_A2IN_TMR_j,A2 in delay timer register Offset = 400Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x0C 22.--31. 1. "XCVR_PSM_A3IN_TMR_15_6,Reserved"
bitfld.long 0x0C 16.--21. "XCVR_PSM_A3IN_TMR_5_0,A3 in delay state timer value : Value used for the timer when the power state machine is in the A3 in delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x0C 6.--15. 1. "XCVR_PSM_A2IN_TMR_15_6,Reserved"
bitfld.long 0x0C 0.--5. "XCVR_PSM_A2IN_TMR_5_0,A2 in delay state timer value : Value used for the timer when the power state machine is in the A2 in delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "XCVR_PSM_A5IN_TMR__XCVR_PSM_A4IN_TMR_j,A4 in delay timer register Offset = 4010h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x10 22.--31. 1. "XCVR_PSM_A5IN_TMR_15_6,Reserved"
bitfld.long 0x10 16.--21. "XCVR_PSM_A5IN_TMR_5_0,A5 in delay state timer value : Value used for the timer when the power state machine is in the A5 in delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x10 6.--15. 1. "XCVR_PSM_A4IN_TMR_15_6,Reserved"
bitfld.long 0x10 0.--5. "XCVR_PSM_A4IN_TMR_5_0,A4 in delay state timer value : Value used for the timer when the power state machine is in the A4 in delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "XCVR_PSM_A0OUT_TMR__XCVR_PSM_CALOUT_TMR_j,PSM calibration out delay timer register Offset = 4014h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x14 22.--31. 1. "XCVR_PSM_A0OUT_TMR_15_6,Reserved"
bitfld.long 0x14 16.--21. "XCVR_PSM_A0OUT_TMR_5_0,A0 out delay state timer value : Value used for the timer when the power state machine is in the A0 out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x14 6.--15. 1. "XCVR_PSM_CALOUT_TMR_15_6,Reserved"
bitfld.long 0x14 0.--5. "XCVR_PSM_CALOUT_TMR_5_0,PSM calibration out delay state timer value : Value used for the timer when the power state machine is in the PSM calibration out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "XCVR_PSM_A2OUT_TMR__XCVR_PSM_A1OUT_TMR_j,A1 out delay timer register Offset = 4018h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x18 22.--31. 1. "XCVR_PSM_A2OUT_TMR_15_6,Reserved"
bitfld.long 0x18 16.--21. "XCVR_PSM_A2OUT_TMR_5_0,A2 out delay state timer value : Value used for the timer when the power state machine is in the A2 out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x18 6.--15. 1. "XCVR_PSM_A1OUT_TMR_15_6,Reserved"
bitfld.long 0x18 0.--5. "XCVR_PSM_A1OUT_TMR_5_0,A1 out delay state timer value : Value used for the timer when the power state machine is in the A1 out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "XCVR_PSM_A4OUT_TMR__XCVR_PSM_A3OUT_TMR_j,A3 out delay timer register Offset = 401Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x1C 22.--31. 1. "XCVR_PSM_A4OUT_TMR_15_6,Reserved"
bitfld.long 0x1C 16.--21. "XCVR_PSM_A4OUT_TMR_5_0,A4 out delay state timer value : Value used for the timer when the power state machine is in the A4 out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x1C 6.--15. 1. "XCVR_PSM_A3OUT_TMR_15_6,Reserved"
bitfld.long 0x1C 0.--5. "XCVR_PSM_A3OUT_TMR_5_0,A3 out delay state timer value : Value used for the timer when the power state machine is in the A3 out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "XCVR_PSM_RDY_TMR__XCVR_PSM_A5OUT_TMR_j,A5 out delay timer register Offset = 4020h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x20 22.--31. 1. "XCVR_PSM_RDY_TMR_15_6,Reserved"
bitfld.long 0x20 16.--21. "XCVR_PSM_RDY_TMR_5_0,Ready delay state timer value : Value used for the timer when the power state machine is in the ready state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x20 6.--15. 1. "XCVR_PSM_A5OUT_TMR_15_6,Reserved"
bitfld.long 0x20 0.--5. "XCVR_PSM_A5OUT_TMR_5_0,A5 out delay state timer value : Value used for the timer when the power state machine is in the A5 out delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "XCVR_PSM_ST_0__XCVR_PSM_DIAG_j,Power state machine diagnostic register Offset = 4024h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x24 16.--31. 1. "XCVR_PSM_ST_0_15_0,PSM current state [15:0] : Indicates bits 15:0 of the current state of the power state machine"
rbitfld.long 0x24 15. "XCVR_PSM_DIAG_15,Reserved" "0,1"
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bitfld.long 0x24 14. "XCVR_PSM_DIAG_14,Force calibration exit acknowledge : Setting this bit to 1'b1 forces the psm_cal_exit_ack pin of the power state machine active" "0,1"
bitfld.long 0x24 13. "XCVR_PSM_DIAG_13,Force A5 exit acknowledge : Setting this bit to 1'b1 forces the psm_a5_exit_ack pin of the power state machine active" "0,1"
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bitfld.long 0x24 12. "XCVR_PSM_DIAG_12,Force A4 exit acknowledge : Setting this bit to 1'b1 forces the psm_a4_exit_ack pin of the power state machine active" "0,1"
bitfld.long 0x24 11. "XCVR_PSM_DIAG_11,Force A3 exit acknowledge : Setting this bit to 1'b1 forces the psm_a3_exit_ack pin of the power state machine active" "0,1"
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bitfld.long 0x24 10. "XCVR_PSM_DIAG_10,Force A2 exit acknowledge : Setting this bit to 1'b1 forces the psm_a2_exit_ack pin of the power state machine active" "0,1"
bitfld.long 0x24 9. "XCVR_PSM_DIAG_9,Force A1 exit acknowledge : Setting this bit to 1'b1 forces the psm_a1_exit_ack pin of the power state machine active" "0,1"
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bitfld.long 0x24 8. "XCVR_PSM_DIAG_8,Force A0 exit acknowledge : Setting this bit to 1'b1 forces the psm_a0_exit_ack pin of the power state machine active" "0,1"
rbitfld.long 0x24 7. "XCVR_PSM_DIAG_7,Reserved" "0,1"
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bitfld.long 0x24 6. "XCVR_PSM_DIAG_6,Force calibration entry acknowledge : Setting this bit to 1'b1 forces the psm_cal_entry_ack pin of the power state machine active" "0,1"
bitfld.long 0x24 5. "XCVR_PSM_DIAG_5,Force A5 entry acknowledge : Setting this bit to 1'b1 forces the psm_a5_entry_ack pin of the power state machine active" "0,1"
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bitfld.long 0x24 4. "XCVR_PSM_DIAG_4,Force A4 entry acknowledge : Setting this bit to 1'b1 forces the psm_a4_entry_ack pin of the power state machine active" "0,1"
bitfld.long 0x24 3. "XCVR_PSM_DIAG_3,Force A3 entry acknowledge : Setting this bit to 1'b1 forces the psm_a3_entry_ack pin of the power state machine active" "0,1"
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bitfld.long 0x24 2. "XCVR_PSM_DIAG_2,Force A2 entry acknowledge : Setting this bit to 1'b1 forces the psm_a2_entry_ack pin of the power state machine active" "0,1"
bitfld.long 0x24 1. "XCVR_PSM_DIAG_1,Force A1 entry acknowledge : Setting this bit to 1'b1 forces the psm_a1_entry_ack pin of the power state machine active" "0,1"
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bitfld.long 0x24 0. "XCVR_PSM_DIAG_0,Force A0 entry acknowledge : Setting this bit to 1'b1 forces the psm_a0_entry_ack pin of the power state machine active" "0,1"
line.long 0x28 "XCVR_PSM_ST_1_j,PSM current state register 1 Offset = 4028h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x28 10.--15. "XCVR_PSM_ST_1_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x28 0.--9. 1. "XCVR_PSM_ST_1_9_0,PSM current state [25:16] : Indicates bits 25:16 of the current state of the power state machine"
group.long 0x403C++0x03
line.long 0x00 "XCVR_PSM_USER_DEF_CTRL_j,Power state machine user defined control register Offset = 403Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 21.--31. 1. "XCVR_PSM_USER_DEF_CTRL_15_5,Reserved - spare"
bitfld.long 0x00 20. "XCVR_PSM_USER_DEF_CTRL_4,Force PSM gated clock on: Setting this bit to 1'b1 will force the PSM gated clock on independent of the internal PSM state machine clock gate controls" "0,1"
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bitfld.long 0x00 16.--19. "XCVR_PSM_USER_DEF_CTRL_3_0,Reserved - spare" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4080++0x53
line.long 0x00 "TX_TXCC_PRE_OVRD__TX_TXCC_CTRL_j,TX coefficient controller control register Offset = 4080h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x00 25.--31. 1. "TX_TXCC_PRE_OVRD_15_9,Reserved"
bitfld.long 0x00 24. "TX_TXCC_PRE_OVRD_8,Pre-cursor override enable: When enabled the pre-cursor field in this register is used to override the pre-cursor value" "0,1"
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rbitfld.long 0x00 22.--23. "TX_TXCC_PRE_OVRD_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "TX_TXCC_PRE_OVRD_5_0,Pre-cursor override value: When enabled by the pre-cursor override enable bit in this register the value in this field is used to override the pre-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 14.--15. "TX_TXCC_CTRL_15_14,Reserved" "0,1,2,3"
bitfld.long 0x00 12.--13. "TX_TXCC_CTRL_13_12,Margin multiplier rounding control: This field controls the rounding function on the margin multiplier" "0,1,2,3"
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bitfld.long 0x00 10.--11. "TX_TXCC_CTRL_11_10,LF value multiplier rounding control: This field controls the rounding function on the LF value multiplier" "0,1,2,3"
bitfld.long 0x00 8.--9. "TX_TXCC_CTRL_9_8,Calculated post-emphasis multiplier rounding control: This field controls the rounding function on the calculated post-emphasis multiplier" "0,1,2,3"
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bitfld.long 0x00 6.--7. "TX_TXCC_CTRL_7_6,Calculated pre-emphasis multiplier rounding control: This field controls the rounding function on the pre-emphasis multiplier" "0,1,2,3"
bitfld.long 0x00 4.--5. "TX_TXCC_CTRL_5_4,Coefficient calculator multiplier rounding control: This field controls the rounding function on the coefficient calculator multiplier" "0,1,2,3"
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bitfld.long 0x00 3. "TX_TXCC_CTRL_3,De-emphasis control standard mode 3 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b11" "0,1"
bitfld.long 0x00 2. "TX_TXCC_CTRL_2,De-emphasis control standard mode 2 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b10" "0,1"
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bitfld.long 0x00 1. "TX_TXCC_CTRL_1,De-emphasis control standard mode 1 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b01" "0,1"
bitfld.long 0x00 0. "TX_TXCC_CTRL_0,De-emphasis control standard mode 0 value: This bit controls the de-emphasis mode when the xcvr_standard_mode is set to 2'b00" "0,1"
line.long 0x04 "TX_TXCC_POST_OVRD__TX_TXCC_MAIN_OVRD_j,TX main-cursor override register Offset = 4084h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x04 25.--31. 1. "TX_TXCC_POST_OVRD_15_9,Reserved"
bitfld.long 0x04 24. "TX_TXCC_POST_OVRD_8,Post-cursor override enable: When enabled the post-cursor field in this register is used to override the post-cursor value" "0,1"
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rbitfld.long 0x04 22.--23. "TX_TXCC_POST_OVRD_7_6,Reserved" "0,1,2,3"
bitfld.long 0x04 16.--21. "TX_TXCC_POST_OVRD_5_0,Post-cursor override value: When enabled by the post-cursor override enable bit in this register the value in this field is used to override the post-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 9.--15. 1. "TX_TXCC_MAIN_OVRD_15_9,Reserved"
bitfld.long 0x04 8. "TX_TXCC_MAIN_OVRD_8,Main-cursor override enable: When enabled the main-cursor field in this register is used to override the main-cursor value" "0,1"
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rbitfld.long 0x04 6.--7. "TX_TXCC_MAIN_OVRD_7_6,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "TX_TXCC_MAIN_OVRD_5_0,Main-cursor override value: When enabled by the main-cursor override enable bit in this register the value in this field is used to override the main-cursor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TX_TXCC_MAIN_CVAL__TX_TXCC_PRE_CVAL_j,TX pre-cursor current value register Offset = 4088h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 22.--31. 1. "TX_TXCC_MAIN_CVAL_15_6,Reserved"
bitfld.long 0x08 16.--21. "TX_TXCC_MAIN_CVAL_5_0,Main-cursor value: The value in this field indicates the current value of the main-cursor (C0) coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 6.--15. 1. "TX_TXCC_PRE_CVAL_15_6,Reserved"
bitfld.long 0x08 0.--5. "TX_TXCC_PRE_CVAL_5_0,Pre-cursor value: The value in this field indicates the current value of the pre-cursor (C-1) coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "TX_TXCC_LF_MULT__TX_TXCC_POST_CVAL_j,TX post-cursor current value register Offset = 408Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x0C 24.--31. 1. "TX_TXCC_LF_MULT_15_8,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "TX_TXCC_LF_MULT_7_0,LF multiplier value: The value in this field specifies the multiplier value used to generate the LF value from the FS value"
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hexmask.long.word 0x0C 6.--15. 1. "TX_TXCC_POST_CVAL_15_6,Reserved"
rbitfld.long 0x0C 0.--5. "TX_TXCC_POST_CVAL_5_0,Post-cursor value: The value in this field indicates the current value of the post-cursor (C+1) coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "TX_TXCC_CPRE_MULT_01__TX_TXCC_CPRE_MULT_00_j,Calculated pre emphasis multiplier value 00 register Offset = 4090h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x10 24.--31. 1. "TX_TXCC_CPRE_MULT_01_15_8,Reserved"
hexmask.long.byte 0x10 16.--23. 1. "TX_TXCC_CPRE_MULT_01_7_0,Calculated pre emphasis multiplier value"
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hexmask.long.byte 0x10 8.--15. 1. "TX_TXCC_CPRE_MULT_00_15_8,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "TX_TXCC_CPRE_MULT_00_7_0,Calculated pre emphasis multiplier value"
line.long 0x14 "TX_TXCC_CPRE_MULT_11__TX_TXCC_CPRE_MULT_10_j,Calculated pre emphasis multiplier value 10 register Offset = 4094h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x14 24.--31. 1. "TX_TXCC_CPRE_MULT_11_15_8,Reserved"
hexmask.long.byte 0x14 16.--23. 1. "TX_TXCC_CPRE_MULT_11_7_0,Calculated pre emphasis multiplier value"
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hexmask.long.byte 0x14 8.--15. 1. "TX_TXCC_CPRE_MULT_10_15_8,Reserved"
hexmask.long.byte 0x14 0.--7. 1. "TX_TXCC_CPRE_MULT_10_7_0,Calculated pre emphasis multiplier value"
line.long 0x18 "TX_TXCC_CPOST_MULT_01__TX_TXCC_CPOST_MULT_00_j,Calculated post emphasis multiplier value 00 register Offset = 4098h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x18 24.--31. 1. "TX_TXCC_CPOST_MULT_01_15_8,Reserved"
hexmask.long.byte 0x18 16.--23. 1. "TX_TXCC_CPOST_MULT_01_7_0,Calculated post emphasis multiplier value"
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hexmask.long.byte 0x18 8.--15. 1. "TX_TXCC_CPOST_MULT_00_15_8,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "TX_TXCC_CPOST_MULT_00_7_0,Calculated post emphasis multiplier value"
line.long 0x1C "TX_TXCC_CPOST_MULT_11__TX_TXCC_CPOST_MULT_10_j,Calculated post emphasis multiplier value 10 register Offset = 409Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x1C 24.--31. 1. "TX_TXCC_CPOST_MULT_11_15_8,Reserved"
hexmask.long.byte 0x1C 16.--23. 1. "TX_TXCC_CPOST_MULT_11_7_0,Calculated post emphasis multiplier value"
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hexmask.long.byte 0x1C 8.--15. 1. "TX_TXCC_CPOST_MULT_10_15_8,Reserved"
hexmask.long.byte 0x1C 0.--7. 1. "TX_TXCC_CPOST_MULT_10_7_0,Calculated post emphasis multiplier value"
line.long 0x20 "TX_TXCC_MGNFS_MULT_001__TX_TXCC_MGNFS_MULT_000_j,Margin full swing multiplier value 000 register Offset = 40A0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x20 24.--31. 1. "TX_TXCC_MGNFS_MULT_001_15_8,Reserved"
hexmask.long.byte 0x20 16.--23. 1. "TX_TXCC_MGNFS_MULT_001_7_0,Margin full swing multiplier value"
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hexmask.long.byte 0x20 8.--15. 1. "TX_TXCC_MGNFS_MULT_000_15_8,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "TX_TXCC_MGNFS_MULT_000_7_0,Margin full swing multiplier value"
line.long 0x24 "TX_TXCC_MGNFS_MULT_011__TX_TXCC_MGNFS_MULT_010_j,Margin full swing multiplier value 010 register Offset = 40A4h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x24 24.--31. 1. "TX_TXCC_MGNFS_MULT_011_15_8,Reserved"
hexmask.long.byte 0x24 16.--23. 1. "TX_TXCC_MGNFS_MULT_011_7_0,Margin full swing multiplier value"
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hexmask.long.byte 0x24 8.--15. 1. "TX_TXCC_MGNFS_MULT_010_15_8,Reserved"
hexmask.long.byte 0x24 0.--7. 1. "TX_TXCC_MGNFS_MULT_010_7_0,Margin full swing multiplier value"
line.long 0x28 "TX_TXCC_MGNFS_MULT_101__TX_TXCC_MGNFS_MULT_100_j,Margin full swing multiplier value 100 register Offset = 40A8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x28 24.--31. 1. "TX_TXCC_MGNFS_MULT_101_15_8,Reserved"
hexmask.long.byte 0x28 16.--23. 1. "TX_TXCC_MGNFS_MULT_101_7_0,Margin full swing multiplier value"
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hexmask.long.byte 0x28 8.--15. 1. "TX_TXCC_MGNFS_MULT_100_15_8,Reserved"
hexmask.long.byte 0x28 0.--7. 1. "TX_TXCC_MGNFS_MULT_100_7_0,Margin full swing multiplier value"
line.long 0x2C "TX_TXCC_MGNFS_MULT_111__TX_TXCC_MGNFS_MULT_110_j,Margin full swing multiplier value 110 register Offset = 40ACh + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x2C 24.--31. 1. "TX_TXCC_MGNFS_MULT_111_15_8,Reserved"
hexmask.long.byte 0x2C 16.--23. 1. "TX_TXCC_MGNFS_MULT_111_7_0,Margin full swing multiplier value"
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hexmask.long.byte 0x2C 8.--15. 1. "TX_TXCC_MGNFS_MULT_110_15_8,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "TX_TXCC_MGNFS_MULT_110_7_0,Margin full swing multiplier value"
line.long 0x30 "TX_TXCC_MGNHS_MULT_001__TX_TXCC_MGNHS_MULT_000_j,Margin half swing multiplier value 000 register Offset = 40B0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x30 24.--31. 1. "TX_TXCC_MGNHS_MULT_001_15_8,Reserved"
hexmask.long.byte 0x30 16.--23. 1. "TX_TXCC_MGNHS_MULT_001_7_0,Margin half swing multiplier value"
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hexmask.long.byte 0x30 8.--15. 1. "TX_TXCC_MGNHS_MULT_000_15_8,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "TX_TXCC_MGNHS_MULT_000_7_0,Margin half swing multiplier value"
line.long 0x34 "TX_TXCC_MGNHS_MULT_011__TX_TXCC_MGNHS_MULT_010_j,Margin half swing multiplier value 010 register Offset = 40B4h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x34 24.--31. 1. "TX_TXCC_MGNHS_MULT_011_15_8,Reserved"
hexmask.long.byte 0x34 16.--23. 1. "TX_TXCC_MGNHS_MULT_011_7_0,Margin half swing multiplier value"
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hexmask.long.byte 0x34 8.--15. 1. "TX_TXCC_MGNHS_MULT_010_15_8,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "TX_TXCC_MGNHS_MULT_010_7_0,Margin half swing multiplier value"
line.long 0x38 "TX_TXCC_MGNHS_MULT_101__TX_TXCC_MGNHS_MULT_100_j,Margin half swing multiplier value 100 register Offset = 40B8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x38 24.--31. 1. "TX_TXCC_MGNHS_MULT_101_15_8,Reserved"
hexmask.long.byte 0x38 16.--23. 1. "TX_TXCC_MGNHS_MULT_101_7_0,Margin half swing multiplier value"
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hexmask.long.byte 0x38 8.--15. 1. "TX_TXCC_MGNHS_MULT_100_15_8,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TX_TXCC_MGNHS_MULT_100_7_0,Margin half swing multiplier value"
line.long 0x3C "TX_TXCC_MGNHS_MULT_111__TX_TXCC_MGNHS_MULT_110_j,Margin half swing multiplier value 110 register Offset = 40BCh + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x3C 24.--31. 1. "TX_TXCC_MGNHS_MULT_111_15_8,Reserved"
hexmask.long.byte 0x3C 16.--23. 1. "TX_TXCC_MGNHS_MULT_111_7_0,Margin half swing multiplier value"
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hexmask.long.byte 0x3C 8.--15. 1. "TX_TXCC_MGNHS_MULT_110_15_8,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "TX_TXCC_MGNHS_MULT_110_7_0,Margin half swing multiplier value"
line.long 0x40 "TX_TXCC_P1PRE_COEF_MULT__TX_TXCC_P0PRE_COEF_MULT_j,Preset 0 pre emphasis coefficient multiplier value register Offset = 40C0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x40 24.--31. 1. "TX_TXCC_P1PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x40 16.--23. 1. "TX_TXCC_P1PRE_COEF_MULT_7_0,Preset 1 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 1 pre emphasis coefficient value from the FS value"
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hexmask.long.byte 0x40 8.--15. 1. "TX_TXCC_P0PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "TX_TXCC_P0PRE_COEF_MULT_7_0,Preset 0 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 0 pre emphasis coefficient value from the FS value"
line.long 0x44 "TX_TXCC_P3PRE_COEF_MULT__TX_TXCC_P2PRE_COEF_MULT_j,Preset 2 pre emphasis coefficient multiplier value register Offset = 40C4h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x44 24.--31. 1. "TX_TXCC_P3PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x44 16.--23. 1. "TX_TXCC_P3PRE_COEF_MULT_7_0,Preset 3 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 3 pre emphasis coefficient value from the FS value"
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hexmask.long.byte 0x44 8.--15. 1. "TX_TXCC_P2PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "TX_TXCC_P2PRE_COEF_MULT_7_0,Preset 2 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 2 pre emphasis coefficient value from the FS value"
line.long 0x48 "TX_TXCC_P5PRE_COEF_MULT__TX_TXCC_P4PRE_COEF_MULT_j,Preset 4 pre emphasis coefficient multiplier value register Offset = 40C8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x48 24.--31. 1. "TX_TXCC_P5PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x48 16.--23. 1. "TX_TXCC_P5PRE_COEF_MULT_7_0,Preset 5 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 5 pre emphasis coefficient value from the FS value"
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hexmask.long.byte 0x48 8.--15. 1. "TX_TXCC_P4PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "TX_TXCC_P4PRE_COEF_MULT_7_0,Preset 4 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 4 pre emphasis coefficient value from the FS value"
line.long 0x4C "TX_TXCC_P7PRE_COEF_MULT__TX_TXCC_P6PRE_COEF_MULT_j,Preset 6 pre emphasis coefficient multiplier value register Offset = 40CCh + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x4C 24.--31. 1. "TX_TXCC_P7PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x4C 16.--23. 1. "TX_TXCC_P7PRE_COEF_MULT_7_0,Preset 7 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 7 pre emphasis coefficient value from the FS value"
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hexmask.long.byte 0x4C 8.--15. 1. "TX_TXCC_P6PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "TX_TXCC_P6PRE_COEF_MULT_7_0,Preset 6 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 6 pre emphasis coefficient value from the FS value"
line.long 0x50 "TX_TXCC_P9PRE_COEF_MULT__TX_TXCC_P8PRE_COEF_MULT_j,Preset 8 pre emphasis coefficient multiplier value register Offset = 40D0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x50 24.--31. 1. "TX_TXCC_P9PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x50 16.--23. 1. "TX_TXCC_P9PRE_COEF_MULT_7_0,Preset 9 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 9 pre emphasis coefficient value from the FS value"
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hexmask.long.byte 0x50 8.--15. 1. "TX_TXCC_P8PRE_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "TX_TXCC_P8PRE_COEF_MULT_7_0,Preset 8 pre emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 8 pre emphasis coefficient value from the FS value"
group.long 0x40E0++0x13
line.long 0x00 "TX_TXCC_P1POST_COEF_MULT__TX_TXCC_P0POST_COEF_MULT_j,Preset 0 post emphasis coefficient multiplier value register Offset = 40E0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x00 24.--31. 1. "TX_TXCC_P1POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "TX_TXCC_P1POST_COEF_MULT_7_0,Preset 1 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 1 post emphasis coefficient value from the FS value"
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hexmask.long.byte 0x00 8.--15. 1. "TX_TXCC_P0POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "TX_TXCC_P0POST_COEF_MULT_7_0,Preset 0 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 0 post emphasis coefficient value from the FS value"
line.long 0x04 "TX_TXCC_P3POST_COEF_MULT__TX_TXCC_P2POST_COEF_MULT_j,Preset 2 post emphasis coefficient multiplier value register Offset = 40E4h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x04 24.--31. 1. "TX_TXCC_P3POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "TX_TXCC_P3POST_COEF_MULT_7_0,Preset 3 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 3 post emphasis coefficient value from the FS value"
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hexmask.long.byte 0x04 8.--15. 1. "TX_TXCC_P2POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "TX_TXCC_P2POST_COEF_MULT_7_0,Preset 2 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 2 post emphasis coefficient value from the FS value"
line.long 0x08 "TX_TXCC_P5POST_COEF_MULT__TX_TXCC_P4POST_COEF_MULT_j,Preset 4 post emphasis coefficient multiplier value register Offset = 40E8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x08 24.--31. 1. "TX_TXCC_P5POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "TX_TXCC_P5POST_COEF_MULT_7_0,Preset 5 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 5 post emphasis coefficient value from the FS value"
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hexmask.long.byte 0x08 8.--15. 1. "TX_TXCC_P4POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x08 0.--7. 1. "TX_TXCC_P4POST_COEF_MULT_7_0,Preset 4 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 4 post emphasis coefficient value from the FS value"
line.long 0x0C "TX_TXCC_P7POST_COEF_MULT__TX_TXCC_P6POST_COEF_MULT_j,Preset 6 post emphasis coefficient multiplier value register Offset = 40ECh + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x0C 24.--31. 1. "TX_TXCC_P7POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "TX_TXCC_P7POST_COEF_MULT_7_0,Preset 7 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 7 post emphasis coefficient value from the FS value"
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hexmask.long.byte 0x0C 8.--15. 1. "TX_TXCC_P6POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x0C 0.--7. 1. "TX_TXCC_P6POST_COEF_MULT_7_0,Preset 6 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 6 post emphasis coefficient value from the FS value"
line.long 0x10 "TX_TXCC_P9POST_COEF_MULT__TX_TXCC_P8POST_COEF_MULT_j,Preset 8 post emphasis coefficient multiplier value register Offset = 40F0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x10 24.--31. 1. "TX_TXCC_P9POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x10 16.--23. 1. "TX_TXCC_P9POST_COEF_MULT_7_0,Preset 9 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 9 post emphasis coefficient value from the FS value"
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hexmask.long.byte 0x10 8.--15. 1. "TX_TXCC_P8POST_COEF_MULT_15_8,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "TX_TXCC_P8POST_COEF_MULT_7_0,Preset 8 post emphasis coefficient multiplier value : The value in this field specifies the multiplier value used to generate the preset 8 post emphasis coefficient value from the FS value"
group.long 0x4180++0x0F
line.long 0x00 "DRV_DIAG_LANE_FCM_EN_SWAIT_TMR__DRV_DIAG_LANE_FCM_EN_TO_j,Lane fast common mode enable timeout register Offset = 4180h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 20.--31. 1. "DRV_DIAG_LANE_FCM_EN_SWAIT_TMR_15_4,Reserved"
bitfld.long 0x00 16.--19. "DRV_DIAG_LANE_FCM_EN_SWAIT_TMR_3_0,Lane fast common mode enable sample wait timer value: This specifies the number of reference clock cycles the fast establishment of common mode process will wait between changing the state of the signals controlling.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "DRV_DIAG_LANE_FCM_EN_TO_15,Bypass fast establishment of common mode enable: When enabled the fast establishment of common mode function will be bypassed" "0,1"
rbitfld.long 0x00 12.--14. "DRV_DIAG_LANE_FCM_EN_TO_14_12,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--11. 1. "DRV_DIAG_LANE_FCM_EN_TO_11_0,Lane fast common mode enable timeout value: The usage of the value of this field is a function of the state of the bypass fast establishment of common mode enable bit in this register"
line.long 0x04 "DRV_DIAG_LANE_FCM_EN_TUNE__DRV_DIAG_LANE_FCM_EN_MGN_TMR_j,Lane fast common mode enable margin timer register Offset = 4184h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 28.--31. "DRV_DIAG_LANE_FCM_EN_TUNE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 24.--27. "DRV_DIAG_LANE_FCM_EN_TUNE_11_8,Common mode sense reference DAC voltage initial test: This field sets the common mode detect reference voltage for the common mode detect comparator when the fast establishment of common mode function is checking the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 20.--23. "DRV_DIAG_LANE_FCM_EN_TUNE_7_4,Common mode sense reference DAC voltage high test: This field sets the common mode detect reference voltage for the common mode detect comparator when the fast establishment of common mode function is waiting for the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 16.--19. "DRV_DIAG_LANE_FCM_EN_TUNE_3_0,Common mode sense reference DAC voltage low test: This field sets the common mode detect reference voltage for the common mode detect comparator when the fast establishment of common mode function is waiting for the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 12.--15. "DRV_DIAG_LANE_FCM_EN_MGN_TMR_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--11. 1. "DRV_DIAG_LANE_FCM_EN_MGN_TMR_11_0,Lane fast common mode enable margin timer value: This specifies the number of reference clock cycles the fast establishment of common mode process will enable all the margin segments for"
line.long 0x08 "DRV_DIAG_RCVDET_TUNE__DRV_DIAG_LFPS_CTRL_j,Transmitter LFPS control register Offset = 4188h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 21.--31. 1. "DRV_DIAG_RCVDET_TUNE_15_5,Reserved"
bitfld.long 0x08 20. "DRV_DIAG_RCVDET_TUNE_4,Receiver detect comparators output and or control: This bit controls how the receiver detect comparators are used to drive the txda_rcvdet_detected_n signal to the digital" "0,1"
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bitfld.long 0x08 16.--19. "DRV_DIAG_RCVDET_TUNE_3_0,Receiver detect reference DAC voltage: This field sets the receiver detect reference voltage for the receiver detect comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x08 8.--15. 1. "DRV_DIAG_LFPS_CTRL_15_8,Reserved"
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hexmask.long.byte 0x08 0.--7. 1. "DRV_DIAG_LFPS_CTRL_7_0,LFPS half period clocks: Specifies the number of clock cycles required to implement one half of a LFPS period by the transmitter LFPS controller"
line.long 0x0C "DRV_DIAG_TX_DRV_j,TX driver diagnostic register Offset = 418Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x0C 8.--15. 1. "DRV_DIAG_TX_DRV_15_8,Reserved"
bitfld.long 0x0C 7. "DRV_DIAG_TX_DRV_7,TX boost enable: Increases the transmitter amplitude for fast data transitions by controlling the txda_drv_boost_en signal going to the analog" "0,1"
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rbitfld.long 0x0C 6. "DRV_DIAG_TX_DRV_6,Reserved" "0,1"
bitfld.long 0x0C 4.--5. "DRV_DIAG_TX_DRV_5_4,TX boost tune: Controls the transmitter boost amplitude when the transmitter boost function is enabled using the TX boost enable bit in this register by controlling the txda_drv_boost_tune signal going to the analog" "0,1,2,3"
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rbitfld.long 0x0C 2.--3. "DRV_DIAG_TX_DRV_3_2,Reserved" "0,1,2,3"
bitfld.long 0x0C 1. "DRV_DIAG_TX_DRV_1,TX pre-driver pull up control: When the pre-driver is disabled this bit controls the state of the pre-driver output by controlling the txda_drv_predrv_pullup signal going to the analog" "0,1"
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bitfld.long 0x0C 0. "DRV_DIAG_TX_DRV_0,TX driver margin type: Selects the margining type the driver will operate in by controlling the txda_drv_margin_type signal going to the analog" "0,1"
group.long 0x41C0++0x1F
line.long 0x00 "XCVR_DIAG_XCAL_PWRI_OVRD__XCVR_DIAG_PWRI_TMR_j,Transceiver power island control timer register Offset = 41C0h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "XCVR_DIAG_XCAL_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x00 30. "XCVR_DIAG_XCAL_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1"
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rbitfld.long 0x00 28.--29. "XCVR_DIAG_XCAL_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x00 27. "XCVR_DIAG_XCAL_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x00 26. "XCVR_DIAG_XCAL_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x00 25. "XCVR_DIAG_XCAL_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x00 24. "XCVR_DIAG_XCAL_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "XCVR_DIAG_XCAL_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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rbitfld.long 0x00 13.--15. "XCVR_DIAG_PWRI_TMR_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "XCVR_DIAG_PWRI_TMR_12_8,Power enable phase 2 timer value: This specifies the number of PSM clock cycles the power island control state machines in the transceiver will wait in the power phase 2 enable states in order to allow enough time for the second.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "XCVR_DIAG_PWRI_TMR_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "XCVR_DIAG_PWRI_TMR_4_0,Power enable phase 1 timer value: This specifies the number of PSM clock cycles the power island control state machines in the transceiver will wait in the power phase 1 enable states in order to allow enough time for the first.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "XCVR_DIAG_XDP_PWRI_OVRD__XCVR_DIAG_XCAL_PWRI_STAT_j,Transceiver transceiver calibration power island control status register Offset = 41C4h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x04 31. "XCVR_DIAG_XDP_PWRI_OVRD_15,Power island controller input override enable: When enabled the power island control state machine input override bits in this register will drive the power island control state machine directly and override any control from.." "0,1"
bitfld.long 0x04 30. "XCVR_DIAG_XDP_PWRI_OVRD_14,Power island controller output override enable: When enabled the power island control state machine output override bits in this register will drive the power island control state machine outputs and override any control from.." "0,1"
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rbitfld.long 0x04 28.--29. "XCVR_DIAG_XDP_PWRI_OVRD_13_12,Reserved" "0,1,2,3"
bitfld.long 0x04 27. "XCVR_DIAG_XDP_PWRI_OVRD_11,Power suspend request override: When enabled this bit will override the power_suspend_req input of the power island control state machine" "0,1"
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rbitfld.long 0x04 26. "XCVR_DIAG_XDP_PWRI_OVRD_10,Power suspend acknowledge: This is the current state of the power_suspend_ack output from the power island control state machine" "0,1"
bitfld.long 0x04 25. "XCVR_DIAG_XDP_PWRI_OVRD_9,Power recover request override: When enabled this bit will override the power_recover_req input of the power island control state machine" "0,1"
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rbitfld.long 0x04 24. "XCVR_DIAG_XDP_PWRI_OVRD_8,Power recover acknowledge: This is the current state of the power_recover_ack output from the power island control state machine" "0,1"
hexmask.long.byte 0x04 16.--23. 1. "XCVR_DIAG_XDP_PWRI_OVRD_7_0,Power island controller output override: When enabled the bits in this field will override the output signals from the power island control state machine"
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hexmask.long.byte 0x04 8.--15. 1. "XCVR_DIAG_XCAL_PWRI_STAT_15_8,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "XCVR_DIAG_XCAL_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x08 "XCVR_DIAG_PLLDRC_CTRL__XCVR_DIAG_XDP_PWRI_STAT_j,Transceiver transceiver data path power island control status register Offset = 41C8h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x08 30.--31. "XCVR_DIAG_PLLDRC_CTRL_15_14,Digital PLL clock select standard mode" "0,1,2,3"
bitfld.long 0x08 28.--29. "XCVR_DIAG_PLLDRC_CTRL_13_12,Digital PLL data rate divider standard mode 3 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3"
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bitfld.long 0x08 26.--27. "XCVR_DIAG_PLLDRC_CTRL_11_10,Digital PLL clock select standard mode" "0,1,2,3"
bitfld.long 0x08 24.--25. "XCVR_DIAG_PLLDRC_CTRL_9_8,Digital PLL data rate divider standard mode 2 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3"
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bitfld.long 0x08 22.--23. "XCVR_DIAG_PLLDRC_CTRL_7_6,Digital PLL clock select standard mode" "0,1,2,3"
bitfld.long 0x08 20.--21. "XCVR_DIAG_PLLDRC_CTRL_5_4,Digital PLL data rate divider standard mode 1 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3"
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bitfld.long 0x08 18.--19. "XCVR_DIAG_PLLDRC_CTRL_3_2,Digital PLL clock select standard mode" "0,1,2,3"
bitfld.long 0x08 16.--17. "XCVR_DIAG_PLLDRC_CTRL_1_0,Digital PLL data rate divider standard mode 0 value: This field will directly control the xcvr_pll_clk_datart_div signal which controls which divided clock is selected when generating the xcvr_pll_clk_datart clock when.." "0,1,2,3"
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hexmask.long.byte 0x08 8.--15. 1. "XCVR_DIAG_XDP_PWRI_STAT_15_8,Reserved"
hexmask.long.byte 0x08 0.--7. 1. "XCVR_DIAG_XDP_PWRI_STAT_7_0,Power island controller output status: This field indicates the current state of the output signals from the power island control state machine"
line.long 0x0C "XCVR_DIAG_HSCLK_DIV__XCVR_DIAG_HSCLK_SEL_j,Transceiver high speed clock select register Offset = 41CCh + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x0C 31. "XCVR_DIAG_HSCLK_DIV_15,Reserved" "0,1"
bitfld.long 0x0C 28.--30. "XCVR_DIAG_HSCLK_DIV_14_12,Transceiver clock divider select standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0C 27. "XCVR_DIAG_HSCLK_DIV_11,Reserved" "0,1"
bitfld.long 0x0C 24.--26. "XCVR_DIAG_HSCLK_DIV_10_8,Transceiver clock divider select standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0C 23. "XCVR_DIAG_HSCLK_DIV_7,Reserved" "0,1"
bitfld.long 0x0C 20.--22. "XCVR_DIAG_HSCLK_DIV_6_4,Transceiver clock divider select standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0C 19. "XCVR_DIAG_HSCLK_DIV_3,Reserved" "0,1"
bitfld.long 0x0C 16.--18. "XCVR_DIAG_HSCLK_DIV_2_0,Transceiver clock divider select standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0C 14.--15. "XCVR_DIAG_HSCLK_SEL_15_14,Reserved" "0,1,2,3"
bitfld.long 0x0C 12.--13. "XCVR_DIAG_HSCLK_SEL_13_12,High speed clock select standard mode" "0,1,2,3"
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rbitfld.long 0x0C 10.--11. "XCVR_DIAG_HSCLK_SEL_11_10,Reserved" "0,1,2,3"
bitfld.long 0x0C 8.--9. "XCVR_DIAG_HSCLK_SEL_9_8,High speed clock select standard mode" "0,1,2,3"
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rbitfld.long 0x0C 6.--7. "XCVR_DIAG_HSCLK_SEL_7_6,Reserved" "0,1,2,3"
bitfld.long 0x0C 4.--5. "XCVR_DIAG_HSCLK_SEL_5_4,High speed clock select standard mode" "0,1,2,3"
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rbitfld.long 0x0C 2.--3. "XCVR_DIAG_HSCLK_SEL_3_2,Reserved" "0,1,2,3"
bitfld.long 0x0C 0.--1. "XCVR_DIAG_HSCLK_SEL_1_0,High speed clock select standard mode" "0,1,2,3"
line.long 0x10 "XCVR_DIAG_RXCLK_CTRL__XCVR_DIAG_TXCLK_CTRL_j,TX clock control register Offset = 41D0h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x10 31. "XCVR_DIAG_RXCLK_CTRL_15,RX deserializer clock invert: This bit is used to optionally invert the deserializer clock (rxda_des_clk) for diagnostic purposes" "0,1"
bitfld.long 0x10 30. "XCVR_DIAG_RXCLK_CTRL_14,RX 2x clock enable: This bit enables the receiver 2x clock function by driving the rxda_des_clk_2x_en signal going to the analog" "0,1"
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bitfld.long 0x10 29. "XCVR_DIAG_RXCLK_CTRL_13,RX PI E path clock select: Controls which PI clock drives the E path clocks by driving the rxda_pi_i_drv_e_en signal going to the analog" "0,1"
rbitfld.long 0x10 24.--28. "XCVR_DIAG_RXCLK_CTRL_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 23. "XCVR_DIAG_RXCLK_CTRL_7,PI output clock divider enable standard mode" "0,1"
bitfld.long 0x10 22. "XCVR_DIAG_RXCLK_CTRL_6,PI output clock divider enable standard mode" "0,1"
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bitfld.long 0x10 21. "XCVR_DIAG_RXCLK_CTRL_5,PI output clock divider enable standard mode" "0,1"
bitfld.long 0x10 20. "XCVR_DIAG_RXCLK_CTRL_4,PI output clock divider enable standard mode" "0,1"
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rbitfld.long 0x10 16.--19. "XCVR_DIAG_RXCLK_CTRL_3_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. "XCVR_DIAG_TXCLK_CTRL_15,TX serializer clock invert: This bit is used to optionally invert the serializer clock (txda_ser_clk) for diagnostic purposes" "0,1"
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hexmask.long.word 0x10 0.--14. 1. "XCVR_DIAG_TXCLK_CTRL_14_0,Reserved"
line.long 0x14 "XCVR_DIAG_PSC_OVRD__XCVR_DIAG_BIDI_CTRL_j,Transceiver bidirectional control register Offset = 41D4h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x14 20.--31. 1. "XCVR_DIAG_PSC_OVRD_15_4,Reserved"
bitfld.long 0x14 19. "XCVR_DIAG_PSC_OVRD_3,Receiver DFE enable mask value standard mode" "0,1"
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bitfld.long 0x14 18. "XCVR_DIAG_PSC_OVRD_2,Receiver DFE enable mask value standard mode" "0,1"
bitfld.long 0x14 17. "XCVR_DIAG_PSC_OVRD_1,Receiver DFE enable mask value standard mode" "0,1"
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bitfld.long 0x14 16. "XCVR_DIAG_PSC_OVRD_0,Receiver DFE enable mask value standard mode" "0,1"
hexmask.long.byte 0x14 8.--15. 1. "XCVR_DIAG_BIDI_CTRL_15_8,Reserved"
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bitfld.long 0x14 7. "XCVR_DIAG_BIDI_CTRL_7,Receiver enable standard mode" "0,1"
bitfld.long 0x14 6. "XCVR_DIAG_BIDI_CTRL_6,Receiver enable standard mode" "0,1"
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bitfld.long 0x14 5. "XCVR_DIAG_BIDI_CTRL_5,Receiver enable standard mode" "0,1"
bitfld.long 0x14 4. "XCVR_DIAG_BIDI_CTRL_4,Receiver enable standard mode" "0,1"
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bitfld.long 0x14 3. "XCVR_DIAG_BIDI_CTRL_3,Transmitter enable standard mode" "0,1"
bitfld.long 0x14 2. "XCVR_DIAG_BIDI_CTRL_2,Transmitter enable standard mode" "0,1"
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bitfld.long 0x14 1. "XCVR_DIAG_BIDI_CTRL_1,Transmitter enable standard mode" "0,1"
bitfld.long 0x14 0. "XCVR_DIAG_BIDI_CTRL_0,Transmitter enable standard mode" "0,1"
line.long 0x18 "XCVR_DIAG_XCVR_CLK_CTRL__XCVR_DIAG_RST_DIAG_j,Transceiver control reset diagnostic register Offset = 41D8h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x18 22.--31. 1. "XCVR_DIAG_XCVR_CLK_CTRL_15_6,Reserved"
bitfld.long 0x18 16.--21. "XCVR_DIAG_XCVR_CLK_CTRL_5_0,Transceiver clock enable delay timer value: This specifies the number of xcvr_psm_clk clock cycles that the transceiver high speed clock reset release state machine will wait between when it drives the analog transceiver.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x18 3.--15. 1. "XCVR_DIAG_RST_DIAG_15_3,Reserved"
rbitfld.long 0x18 2. "XCVR_DIAG_RST_DIAG_2,Current state of the tx_coef_calc_reset_n reset" "0,1"
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rbitfld.long 0x18 1. "XCVR_DIAG_RST_DIAG_1,Current state of the xcvr_psm_reset_n reset" "0,1"
rbitfld.long 0x18 0. "XCVR_DIAG_RST_DIAG_0,Current state of the xcvr_ref_clk_reset_n reset" "0,1"
line.long 0x1C "XCVR_DIAG_DCYA_j,Transceiver digital cover your alternatives register Offset = 41DCh + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x1C 16.--31. 1. "XCVR_DIAG_DCYA_15_0,Reserved - spare"
group.long 0x4200++0x0F
line.long 0x00 "TX_PSC_A1__TX_PSC_A0_j,Transmitter A0 power state definition register Offset = 4200h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 28.--31. "TX_PSC_A1_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "TX_PSC_A1_11,TX driver common mode enable extend control" "0,1"
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bitfld.long 0x00 26. "TX_PSC_A1_10,Force txda_lfps_sel active" "0,1"
bitfld.long 0x00 25. "TX_PSC_A1_9,LFPS clock gate enable" "0,1"
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bitfld.long 0x00 24. "TX_PSC_A1_8,Reserved - spare" "0,1"
bitfld.long 0x00 23. "TX_PSC_A1_7,Transmitter low current mode" "0,1"
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bitfld.long 0x00 22. "TX_PSC_A1_6,Transmitter mission mode enable" "0,1"
bitfld.long 0x00 21. "TX_PSC_A1_5,TX driver common mode enable" "0,1"
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bitfld.long 0x00 20. "TX_PSC_A1_4,TX driver enable" "0,1"
bitfld.long 0x00 19. "TX_PSC_A1_3,TX post-emphasis enable (C+1)" "0,1"
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bitfld.long 0x00 18. "TX_PSC_A1_2,TX pre-emphasis enable (C-1)" "0,1"
bitfld.long 0x00 17. "TX_PSC_A1_1,TX pre-driver enable" "0,1"
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bitfld.long 0x00 16. "TX_PSC_A1_0,TX serializer enable" "0,1"
rbitfld.long 0x00 12.--15. "TX_PSC_A0_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "TX_PSC_A0_11,TX driver common mode enable extend control: Specifies which power states the tx_cmn_mode_en_ext signal is considered valid in and can be used to force the driver to continue to be in the common mode state" "0,1"
bitfld.long 0x00 10. "TX_PSC_A0_10,Force txda_lfps_sel active: Setting this bit forces the txda_lfps_sel signal going to the analog to be driven active" "0,1"
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bitfld.long 0x00 9. "TX_PSC_A0_9,LFPS clock gate enable: Enables the LFPS clock gate when an LFPS clock is required" "0,1"
bitfld.long 0x00 8. "TX_PSC_A0_8,Reserved - spare" "0,1"
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bitfld.long 0x00 7. "TX_PSC_A0_7,Transmitter low current mode: Enables a low current consumption mode within the common mode voltage circuit in the driver via the txda_drv_idle_lowi_en signal going to the analog" "0,1"
bitfld.long 0x00 6. "TX_PSC_A0_6,Transmitter mission mode enable: Enables the analog circuits in the driver required to run in mission mode via the txda_drv_mission_en signal going to the analog" "0,1"
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bitfld.long 0x00 5. "TX_PSC_A0_5,TX driver common mode enable: Enables the common mode voltage circuits in the driver" "0,1"
bitfld.long 0x00 4. "TX_PSC_A0_4,TX driver enable: Enables the transmitter driver via the H bridge driver controller" "0,1"
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bitfld.long 0x00 3. "TX_PSC_A0_3,TX post-emphasis enable (C+1): Enables the transmitter circuits related to the post-emphasis function" "0,1"
bitfld.long 0x00 2. "TX_PSC_A0_2,TX pre-emphasis enable (C-1): Enables the transmitter circuits related to the pre-emphasis function" "0,1"
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bitfld.long 0x00 1. "TX_PSC_A0_1,TX pre-driver enable: Enables the transmitter pre-driver driver data selection MUX and receiver detect" "0,1"
bitfld.long 0x00 0. "TX_PSC_A0_0,TX serializer enable: Enables the serializer and related clock divider circuits" "0,1"
line.long 0x04 "TX_PSC_A3__TX_PSC_A2_j,Transmitter A2 power state definition register Offset = 4204h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 28.--31. "TX_PSC_A3_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 27. "TX_PSC_A3_11,TX driver common mode enable extend control" "0,1"
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bitfld.long 0x04 26. "TX_PSC_A3_10,Force txda_lfps_sel active" "0,1"
bitfld.long 0x04 25. "TX_PSC_A3_9,LFPS clock gate enable" "0,1"
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bitfld.long 0x04 24. "TX_PSC_A3_8,Reserved - spare" "0,1"
bitfld.long 0x04 23. "TX_PSC_A3_7,Transmitter low current mode" "0,1"
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bitfld.long 0x04 22. "TX_PSC_A3_6,Transmitter mission mode enable" "0,1"
bitfld.long 0x04 21. "TX_PSC_A3_5,TX driver common mode enable" "0,1"
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bitfld.long 0x04 20. "TX_PSC_A3_4,TX driver enable" "0,1"
bitfld.long 0x04 19. "TX_PSC_A3_3,TX post-emphasis enable (C+1)" "0,1"
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bitfld.long 0x04 18. "TX_PSC_A3_2,TX pre-emphasis enable (C-1)" "0,1"
bitfld.long 0x04 17. "TX_PSC_A3_1,TX pre-driver enable" "0,1"
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bitfld.long 0x04 16. "TX_PSC_A3_0,TX serializer enable" "0,1"
rbitfld.long 0x04 12.--15. "TX_PSC_A2_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 11. "TX_PSC_A2_11,TX driver common mode enable extend control" "0,1"
bitfld.long 0x04 10. "TX_PSC_A2_10,Force txda_lfps_sel active" "0,1"
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bitfld.long 0x04 9. "TX_PSC_A2_9,LFPS clock gate enable" "0,1"
bitfld.long 0x04 8. "TX_PSC_A2_8,Reserved - spare" "0,1"
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bitfld.long 0x04 7. "TX_PSC_A2_7,Transmitter low current mode" "0,1"
bitfld.long 0x04 6. "TX_PSC_A2_6,Transmitter mission mode enable" "0,1"
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bitfld.long 0x04 5. "TX_PSC_A2_5,TX driver common mode enable" "0,1"
bitfld.long 0x04 4. "TX_PSC_A2_4,TX driver enable" "0,1"
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bitfld.long 0x04 3. "TX_PSC_A2_3,TX post-emphasis enable (C+1)" "0,1"
bitfld.long 0x04 2. "TX_PSC_A2_2,TX pre-emphasis enable (C-1)" "0,1"
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bitfld.long 0x04 1. "TX_PSC_A2_1,TX pre-driver enable" "0,1"
bitfld.long 0x04 0. "TX_PSC_A2_0,TX serializer enable" "0,1"
line.long 0x08 "TX_PSC_A5__TX_PSC_A4_j,Transmitter A4 power state definition register Offset = 4208h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x08 28.--31. "TX_PSC_A5_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 27. "TX_PSC_A5_11,TX driver common mode enable extend control" "0,1"
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bitfld.long 0x08 26. "TX_PSC_A5_10,Force txda_lfps_sel active" "0,1"
bitfld.long 0x08 25. "TX_PSC_A5_9,LFPS clock gate enable" "0,1"
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bitfld.long 0x08 24. "TX_PSC_A5_8,Reserved - spare" "0,1"
bitfld.long 0x08 23. "TX_PSC_A5_7,Transmitter low current mode" "0,1"
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bitfld.long 0x08 22. "TX_PSC_A5_6,Transmitter mission mode enable" "0,1"
bitfld.long 0x08 21. "TX_PSC_A5_5,TX driver common mode enable" "0,1"
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bitfld.long 0x08 20. "TX_PSC_A5_4,TX driver enable" "0,1"
bitfld.long 0x08 19. "TX_PSC_A5_3,TX post-emphasis enable (C+1)" "0,1"
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bitfld.long 0x08 18. "TX_PSC_A5_2,TX pre-emphasis enable (C-1)" "0,1"
bitfld.long 0x08 17. "TX_PSC_A5_1,TX pre-driver enable" "0,1"
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bitfld.long 0x08 16. "TX_PSC_A5_0,TX serializer enable" "0,1"
rbitfld.long 0x08 12.--15. "TX_PSC_A4_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "TX_PSC_A4_11,TX driver common mode enable extend control" "0,1"
bitfld.long 0x08 10. "TX_PSC_A4_10,Force txda_lfps_sel active" "0,1"
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bitfld.long 0x08 9. "TX_PSC_A4_9,LFPS clock gate enable" "0,1"
bitfld.long 0x08 8. "TX_PSC_A4_8,Reserved - spare" "0,1"
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bitfld.long 0x08 7. "TX_PSC_A4_7,Transmitter low current mode" "0,1"
bitfld.long 0x08 6. "TX_PSC_A4_6,Transmitter mission mode enable" "0,1"
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bitfld.long 0x08 5. "TX_PSC_A4_5,TX driver common mode enable" "0,1"
bitfld.long 0x08 4. "TX_PSC_A4_4,TX driver enable" "0,1"
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bitfld.long 0x08 3. "TX_PSC_A4_3,TX post-emphasis enable (C+1)" "0,1"
bitfld.long 0x08 2. "TX_PSC_A4_2,TX pre-emphasis enable (C-1)" "0,1"
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bitfld.long 0x08 1. "TX_PSC_A4_1,TX pre-driver enable" "0,1"
bitfld.long 0x08 0. "TX_PSC_A4_0,TX serializer enable" "0,1"
line.long 0x0C "TX_PSC_RDY__TX_PSC_CAL_j,Transmitter calibration power state definition register Offset = 420Ch + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x0C 28.--31. "TX_PSC_RDY_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 27. "TX_PSC_RDY_11,TX driver common mode enable extend control" "0,1"
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bitfld.long 0x0C 26. "TX_PSC_RDY_10,Force txda_lfps_sel active" "0,1"
bitfld.long 0x0C 25. "TX_PSC_RDY_9,LFPS clock gate enable" "0,1"
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bitfld.long 0x0C 24. "TX_PSC_RDY_8,Reserved - spare" "0,1"
bitfld.long 0x0C 23. "TX_PSC_RDY_7,Transmitter low current mode" "0,1"
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bitfld.long 0x0C 22. "TX_PSC_RDY_6,Transmitter mission mode enable" "0,1"
bitfld.long 0x0C 21. "TX_PSC_RDY_5,TX driver common mode enable" "0,1"
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bitfld.long 0x0C 20. "TX_PSC_RDY_4,TX driver enable" "0,1"
bitfld.long 0x0C 19. "TX_PSC_RDY_3,TX post-emphasis enable (C+1)" "0,1"
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bitfld.long 0x0C 18. "TX_PSC_RDY_2,TX pre-emphasis enable (C-1)" "0,1"
bitfld.long 0x0C 17. "TX_PSC_RDY_1,TX pre-driver enable" "0,1"
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bitfld.long 0x0C 16. "TX_PSC_RDY_0,TX serializer enable" "0,1"
rbitfld.long 0x0C 12.--15. "TX_PSC_CAL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 11. "TX_PSC_CAL_11,TX driver common mode enable extend control" "0,1"
bitfld.long 0x0C 10. "TX_PSC_CAL_10,Force txda_lfps_sel active" "0,1"
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bitfld.long 0x0C 9. "TX_PSC_CAL_9,LFPS clock gate enable" "0,1"
bitfld.long 0x0C 8. "TX_PSC_CAL_8,Reserved - spare" "0,1"
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bitfld.long 0x0C 7. "TX_PSC_CAL_7,Transmitter low current mode" "0,1"
bitfld.long 0x0C 6. "TX_PSC_CAL_6,Transmitter mission mode enable" "0,1"
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bitfld.long 0x0C 5. "TX_PSC_CAL_5,TX driver common mode enable" "0,1"
bitfld.long 0x0C 4. "TX_PSC_CAL_4,TX driver enable" "0,1"
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bitfld.long 0x0C 3. "TX_PSC_CAL_3,TX post-emphasis enable (C+1)" "0,1"
bitfld.long 0x0C 2. "TX_PSC_CAL_2,TX pre-emphasis enable (C-1)" "0,1"
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bitfld.long 0x0C 1. "TX_PSC_CAL_1,TX pre-driver enable" "0,1"
bitfld.long 0x0C 0. "TX_PSC_CAL_0,TX serializer enable" "0,1"
group.long 0x4240++0x07
line.long 0x00 "TX_RCVDET_OVRD__TX_RCVDET_CTRL_j,Transmit receiver detect control register Offset = 4240h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "TX_RCVDET_OVRD_15,Receiver detect override enable: Activation (1'b1) of this register bit enables the tx_rcv_detected output from the receiver detect state machine to be driven directly by the receiver detect override bit in this register" "0,1"
bitfld.long 0x00 30. "TX_RCVDET_OVRD_14,Receiver detect override: When the receiver detect override enable bit in this register is active (1'b1) this bit will directly control the tx_rcv_detected output from the receiver detect state machine" "0,1"
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hexmask.long.word 0x00 16.--29. 1. "TX_RCVDET_OVRD_13_0,Reserved"
bitfld.long 0x00 15. "TX_RCVDET_CTRL_15,Start receiver detect: Activating (1'b1) this bit will start the receiver detect process" "0,1"
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rbitfld.long 0x00 14. "TX_RCVDET_CTRL_14,Receiver detect process done: This bit will be set to 1'b1 when the receiver detect process is complete" "0,1"
rbitfld.long 0x00 13. "TX_RCVDET_CTRL_13,Receiver detected: When the receiver detect process is complete this register bit will indicate the current state of the tx_rcv_detected pin" "0,1"
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hexmask.long.word 0x00 0.--12. 1. "TX_RCVDET_CTRL_12_0,Reserved"
line.long 0x04 "TX_RCVDET_ST_TMR__TX_RCVDET_EN_TMR_j,Transmit receiver detect enable timer register Offset = 4244h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "TX_RCVDET_ST_TMR_15_0,Start wait time value: This is the number of clocks the receiver detect state machine waits between driving the txda_rcvdet_start signal active and checking the results on the txda_rcvdet_detected_n signal coming from the analog"
hexmask.long.word 0x04 0.--15. 1. "TX_RCVDET_EN_TMR_15_0,Enable wait time value: This is the number of clocks the receiver detect state machine waits between driving the txda_rcvdet_en signal active and driving the txda_rcvdet_start signal active going to the analog"
group.long 0x4280++0x07
line.long 0x00 "TX_BIST_UDDWR__TX_BIST_CTRL_j,Transmit BIST control register Offset = 4280h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 26.--31. "TX_BIST_UDDWR_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "TX_BIST_UDDWR_9_0,Transmitter BIST user defined data: Writing a data word to this field will result in that data word being placed in the next available position in the transmitter BIST user defined data FIFO"
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rbitfld.long 0x00 12.--15. "TX_BIST_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "TX_BIST_CTRL_11_8,Transmitter BIST mode: Controls which mode the BIST will operate in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 5.--7. "TX_BIST_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "TX_BIST_CTRL_4,Transmitter BIST force error: When this bit transitions from 1'b0 to 1'b1 the transmit BIST controller will force an error to be transmitted from the BIST logic by inverting one of the parallel data bits" "0,1"
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rbitfld.long 0x00 2.--3. "TX_BIST_CTRL_3_2,Reserved" "0,1,2,3"
bitfld.long 0x00 1. "TX_BIST_CTRL_1,Transmitter BIST user defined data FIFO clear: Writing a 1'b1 to this bit will clear the transmitter BIST user defined data FIFO" "0,1"
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bitfld.long 0x00 0. "TX_BIST_CTRL_0,Transmitter BIST enable: This bit enables the transmitter BIST function" "0,1"
line.long 0x04 "TX_BIST_SEED1__TX_BIST_SEED0_j,Transmit BIST PRBS seed 0 register Offset = 4284h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 31. "TX_BIST_SEED1_15,Reserved" "0,1"
hexmask.long.word 0x04 16.--30. 1. "TX_BIST_SEED1_14_0,Transmitter BIST PRBS seed (30:16): When the BIST is in PRBS mode this field provides a seed for the PRBS such that different lanes can have different BIST patterns"
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hexmask.long.word 0x04 0.--15. 1. "TX_BIST_SEED0_15_0,Transmitter BIST PRBS seed (15:0): When the BIST is in PRBS mode this field provides a seed for the PRBS such that different lanes can have different BIST patterns"
group.long 0x43C0++0x0F
line.long 0x00 "TX_DIAG_SFIFO_TMR__TX_DIAG_SFIFO_CTRL_j,TX sync FIFO diagnostic control register Offset = 43C0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 30.--31. "TX_DIAG_SFIFO_TMR_15_14,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "TX_DIAG_SFIFO_TMR_13_8,FIFO alignment settle delay: This field specifies the number of clocks to wait for a prior change to the enqueue pointer to complete before initiating the check phase of the alignment procedure in the sync FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 22.--23. "TX_DIAG_SFIFO_TMR_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "TX_DIAG_SFIFO_TMR_5_0,FIFO alignment detect delay: This field specifies the number of clocks to wait in the delay state for each phase of the alignment procedure in the sync FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 5.--15. 1. "TX_DIAG_SFIFO_CTRL_15_5,Reserved"
bitfld.long 0x00 4. "TX_DIAG_SFIFO_CTRL_4,FIFO enqueue pointer bump: This bit can be used to decrement the enqueue pointer relative to the dequeue pointer for diagnostic purposes" "0,1"
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rbitfld.long 0x00 3. "TX_DIAG_SFIFO_CTRL_3,FIFO pointers overlapping: This bit indicates that the current enqueue and dequeue pointers have been detected as overlapping" "0,1"
rbitfld.long 0x00 2. "TX_DIAG_SFIFO_CTRL_2,FIFO alignment acknowledge: This bit indicates that the FIFO alignment process is complete as initiated either automatically by the hardware of the FIFO alignment enable override bits in this register" "0,1"
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bitfld.long 0x00 1. "TX_DIAG_SFIFO_CTRL_1,FIFO alignment enable override enable: This bit enables the FIFO alignment enable override register to drive the fifo_align_en pin of the FIFO directly for diagnostic purposes" "0,1"
bitfld.long 0x00 0. "TX_DIAG_SFIFO_CTRL_0,FIFO alignment enable override: When enabled by the FIFO alignment enable override enable bit in this register this bit directly controls the fifo_align_en pin of the FIFO to provide a means of running the FIFO alignment function.." "0,1"
line.long 0x04 "TX_DIAG_ELEC_IDLE_j,TX electrical idle diagnostic register Offset = 43C4h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x04 12.--15. "TX_DIAG_ELEC_IDLE_15_12,TX electrical idle exit delay 16 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when exiting the electrical idle state for 16 bit data width modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--11. "TX_DIAG_ELEC_IDLE_11_8,TX electrical idle entry delay 16 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when entering the electrical idle state for 16 bit data width modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. "TX_DIAG_ELEC_IDLE_7_4,TX electrical idle exit delay 20 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when exiting the electrical idle state for 20 bit data width modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TX_DIAG_ELEC_IDLE_3_0,TX electrical idle entry delay 20 bit data width : This field controls the amount of additional delay added to the electrical idle signal after the sync FIFO when entering the electrical idle state for 20 bit data width modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "TX_DIAG_RST_DIAG_j,Transmitter control reset diagnostic register Offset = 43C8h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 21.--31. 1. "TX_DIAG_RST_DIAG_15_5,Reserved"
bitfld.long 0x08 20. "TX_DIAG_RST_DIAG_4,Current state of the txda_tx_clk_reset_n reset" "0,1"
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bitfld.long 0x08 19. "TX_DIAG_RST_DIAG_3,Current state of the tx_dig_reset_n reset" "0,1"
bitfld.long 0x08 18. "TX_DIAG_RST_DIAG_2,Current state of the tx_sync_fifo_deq_rst_n reset" "0,1"
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bitfld.long 0x08 17. "TX_DIAG_RST_DIAG_1,Current state of the tx_sync_fifo_enq_rst_n reset" "0,1"
bitfld.long 0x08 16. "TX_DIAG_RST_DIAG_0,Current state of the tx_lfps_reset_n reset" "0,1"
line.long 0x0C "TX_DIAG_ACYA__TX_DIAG_DCYA_j,Transmitter digital cover your alternatives register Offset = 43CCh + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x0C 17.--31. 1. "TX_DIAG_ACYA_15_1,Reserved - spare"
bitfld.long 0x0C 16. "TX_DIAG_ACYA_0,HBDC latch control: Controls the state of the latches associated with the H bridge driver controller related signals in the H bridge driver encoder logic digital in the transmitter analog as well as the boost enable and level control.." "0,1"
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hexmask.long.word 0x0C 0.--15. 1. "TX_DIAG_DCYA_15_0,Reserved - spare"
group.long 0x8000++0x0F
line.long 0x00 "RX_PSC_A1__RX_PSC_A0_j,Receiver A0 power state definition register Offset = 8000h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 29.--31. "RX_PSC_A1_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 28. "RX_PSC_A1_12,RX signal detect enable extend control" "0,1"
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bitfld.long 0x00 27. "RX_PSC_A1_11,RX signal detect filter enable" "0,1"
bitfld.long 0x00 26. "RX_PSC_A1_10,RX LFPS detect filter enable" "0,1"
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bitfld.long 0x00 25. "RX_PSC_A1_9,Reserved - spare" "0,1"
bitfld.long 0x00 24. "RX_PSC_A1_8,RX signal detect enable" "0,1"
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bitfld.long 0x00 21.--23. "RX_PSC_A1_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20. "RX_PSC_A1_4,RX equalizer engine enable" "0,1"
newline
bitfld.long 0x00 19. "RX_PSC_A1_3,RX DFE equalization enable" "0,1"
bitfld.long 0x00 18. "RX_PSC_A1_2,RX PI enable" "0,1"
newline
bitfld.long 0x00 17. "RX_PSC_A1_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x00 16. "RX_PSC_A1_0,RX enable" "0,1"
newline
rbitfld.long 0x00 13.--15. "RX_PSC_A0_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "RX_PSC_A0_12,RX signal detect enable extend control: Specifies which power states the rx_sig_det_en_ext signal is considered valid in and can be used to force the signal detect functions to remain on" "0,1"
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bitfld.long 0x00 11. "RX_PSC_A0_11,RX signal detect filter enable: Enables the receiver signal detect filter function in the digital receiver controller" "0,1"
bitfld.long 0x00 10. "RX_PSC_A0_10,RX LFPS detect filter enable: Enables the receiver LFPS detect filter function in the digital receiver controller" "0,1"
newline
bitfld.long 0x00 9. "RX_PSC_A0_9,Reserved - spare" "0,1"
bitfld.long 0x00 8. "RX_PSC_A0_8,RX signal detect enable: Enables the receiver signal detect function" "0,1"
newline
bitfld.long 0x00 5.--7. "RX_PSC_A0_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RX_PSC_A0_4,RX equalizer engine enable: Specifies which power state the REE runs in" "0,1"
newline
bitfld.long 0x00 3. "RX_PSC_A0_3,RX DFE equalization enable: Enables the receiver DFE equalization circuits via the rxda_dfe_eq_enable signal" "0,1"
bitfld.long 0x00 2. "RX_PSC_A0_2,RX PI enable: Enables the receiver circuits related to the PI and associated clocking components" "0,1"
newline
bitfld.long 0x00 1. "RX_PSC_A0_1,RX e path enable (calibration and eye surf only) : Enables the receiver circuits related to the eye plot PI and e path deserializer for calibration and eye surf" "0,1"
bitfld.long 0x00 0. "RX_PSC_A0_0,RX enable: Enables the receiver circuits related to the CDRLF Sampler FE and Deserializer" "0,1"
line.long 0x04 "RX_PSC_A3__RX_PSC_A2_j,Receiver A2 power state definition register Offset = 8004h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 29.--31. "RX_PSC_A3_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 28. "RX_PSC_A3_12,RX signal detect enable extend control" "0,1"
newline
bitfld.long 0x04 27. "RX_PSC_A3_11,RX signal detect filter enable" "0,1"
bitfld.long 0x04 26. "RX_PSC_A3_10,RX LFPS detect filter enable" "0,1"
newline
bitfld.long 0x04 25. "RX_PSC_A3_9,Reserved - spare" "0,1"
bitfld.long 0x04 24. "RX_PSC_A3_8,RX signal detect enable" "0,1"
newline
bitfld.long 0x04 21.--23. "RX_PSC_A3_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 20. "RX_PSC_A3_4,RX equalizer engine enable" "0,1"
newline
bitfld.long 0x04 19. "RX_PSC_A3_3,RX DFE equalization enable" "0,1"
bitfld.long 0x04 18. "RX_PSC_A3_2,RX PI enable" "0,1"
newline
bitfld.long 0x04 17. "RX_PSC_A3_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x04 16. "RX_PSC_A3_0,RX enable" "0,1"
newline
rbitfld.long 0x04 13.--15. "RX_PSC_A2_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 12. "RX_PSC_A2_12,RX signal detect enable extend control" "0,1"
newline
bitfld.long 0x04 11. "RX_PSC_A2_11,RX signal detect filter enable" "0,1"
bitfld.long 0x04 10. "RX_PSC_A2_10,RX LFPS detect filter enable" "0,1"
newline
bitfld.long 0x04 9. "RX_PSC_A2_9,Reserved - spare" "0,1"
bitfld.long 0x04 8. "RX_PSC_A2_8,RX signal detect enable" "0,1"
newline
bitfld.long 0x04 5.--7. "RX_PSC_A2_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 4. "RX_PSC_A2_4,RX equalizer engine enable" "0,1"
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bitfld.long 0x04 3. "RX_PSC_A2_3,RX DFE equalization enable" "0,1"
bitfld.long 0x04 2. "RX_PSC_A2_2,RX PI enable" "0,1"
newline
bitfld.long 0x04 1. "RX_PSC_A2_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x04 0. "RX_PSC_A2_0,RX enable" "0,1"
line.long 0x08 "RX_PSC_A5__RX_PSC_A4_j,Receiver A4 power state definition register Offset = 8008h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x08 29.--31. "RX_PSC_A5_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 28. "RX_PSC_A5_12,RX signal detect enable extend control" "0,1"
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bitfld.long 0x08 27. "RX_PSC_A5_11,RX signal detect filter enable" "0,1"
bitfld.long 0x08 26. "RX_PSC_A5_10,RX LFPS detect filter enable" "0,1"
newline
bitfld.long 0x08 25. "RX_PSC_A5_9,Reserved - spare" "0,1"
bitfld.long 0x08 24. "RX_PSC_A5_8,RX signal detect enable" "0,1"
newline
bitfld.long 0x08 21.--23. "RX_PSC_A5_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "RX_PSC_A5_4,RX equalizer engine enable" "0,1"
newline
bitfld.long 0x08 19. "RX_PSC_A5_3,RX DFE equalization enable" "0,1"
bitfld.long 0x08 18. "RX_PSC_A5_2,RX PI enable" "0,1"
newline
bitfld.long 0x08 17. "RX_PSC_A5_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x08 16. "RX_PSC_A5_0,RX enable" "0,1"
newline
rbitfld.long 0x08 13.--15. "RX_PSC_A4_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 12. "RX_PSC_A4_12,RX signal detect enable extend control" "0,1"
newline
bitfld.long 0x08 11. "RX_PSC_A4_11,RX signal detect filter enable" "0,1"
bitfld.long 0x08 10. "RX_PSC_A4_10,RX LFPS detect filter enable" "0,1"
newline
bitfld.long 0x08 9. "RX_PSC_A4_9,Reserved - spare" "0,1"
bitfld.long 0x08 8. "RX_PSC_A4_8,RX signal detect enable" "0,1"
newline
bitfld.long 0x08 5.--7. "RX_PSC_A4_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 4. "RX_PSC_A4_4,RX equalizer engine enable" "0,1"
newline
bitfld.long 0x08 3. "RX_PSC_A4_3,RX DFE equalization enable" "0,1"
bitfld.long 0x08 2. "RX_PSC_A4_2,RX PI enable" "0,1"
newline
bitfld.long 0x08 1. "RX_PSC_A4_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x08 0. "RX_PSC_A4_0,RX enable" "0,1"
line.long 0x0C "RX_PSC_RDY__RX_PSC_CAL_j,Receiver calibration power state definition register Offset = 800Ch + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x0C 29.--31. "RX_PSC_RDY_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 28. "RX_PSC_RDY_12,RX signal detect enable extend control" "0,1"
newline
bitfld.long 0x0C 27. "RX_PSC_RDY_11,RX signal detect filter enable" "0,1"
bitfld.long 0x0C 26. "RX_PSC_RDY_10,RX LFPS detect filter enable" "0,1"
newline
bitfld.long 0x0C 25. "RX_PSC_RDY_9,Reserved - spare" "0,1"
bitfld.long 0x0C 24. "RX_PSC_RDY_8,RX signal detect enable" "0,1"
newline
bitfld.long 0x0C 21.--23. "RX_PSC_RDY_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 20. "RX_PSC_RDY_4,RX equalizer engine enable" "0,1"
newline
bitfld.long 0x0C 19. "RX_PSC_RDY_3,RX DFE equalization enable" "0,1"
bitfld.long 0x0C 18. "RX_PSC_RDY_2,RX PI enable" "0,1"
newline
bitfld.long 0x0C 17. "RX_PSC_RDY_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x0C 16. "RX_PSC_RDY_0,RX enable" "0,1"
newline
rbitfld.long 0x0C 13.--15. "RX_PSC_CAL_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 12. "RX_PSC_CAL_12,RX signal detect enable extend control" "0,1"
newline
bitfld.long 0x0C 11. "RX_PSC_CAL_11,RX signal detect filter enable" "0,1"
bitfld.long 0x0C 10. "RX_PSC_CAL_10,RX LFPS detect filter enable" "0,1"
newline
bitfld.long 0x0C 9. "RX_PSC_CAL_9,Reserved - spare" "0,1"
bitfld.long 0x0C 8. "RX_PSC_CAL_8,RX signal detect enable" "0,1"
newline
bitfld.long 0x0C 5.--7. "RX_PSC_CAL_7_5,Reserved - spare" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "RX_PSC_CAL_4,RX equalizer engine enable" "0,1"
newline
bitfld.long 0x0C 3. "RX_PSC_CAL_3,RX DFE equalization enable" "0,1"
bitfld.long 0x0C 2. "RX_PSC_CAL_2,RX PI enable" "0,1"
newline
bitfld.long 0x0C 1. "RX_PSC_CAL_1,RX e path enable (calibration and eye surf only)" "0,1"
bitfld.long 0x0C 0. "RX_PSC_CAL_0,RX enable" "0,1"
group.long 0x8080++0x0B
line.long 0x00 "RX_SDCAL0_OVRD__RX_SDCAL0_CTRL_j,Signal detect calibration 0 control register Offset = 8080h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_SDCAL0_OVRD_15,Calibration code override enable: Activation (1'b1) of this register bit allows the codes determined during the automatic calibration process to be overridden" "0,1"
bitfld.long 0x00 30. "RX_SDCAL0_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the rxda_sd_cal_0_en enable and the rxda_sd_cal_0_clk clock" "0,1"
newline
hexmask.long.word 0x00 21.--29. 1. "RX_SDCAL0_OVRD_13_5,Reserved"
bitfld.long 0x00 16.--20. "RX_SDCAL0_OVRD_4_0,Calibration code override value: These bits are used to override the calibration code determined during the automatic calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "RX_SDCAL0_CTRL_15,Start calibration: Activating (1'b1) this bit will start the calibration process" "0,1"
rbitfld.long 0x00 14. "RX_SDCAL0_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete" "0,1"
newline
rbitfld.long 0x00 13. "RX_SDCAL0_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x00 12. "RX_SDCAL0_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (rxda_sd_cal_0_comp)" "0,1"
newline
hexmask.long.byte 0x00 5.--11. 1. "RX_SDCAL0_CTRL_11_5,Reserved"
rbitfld.long 0x00 0.--4. "RX_SDCAL0_CTRL_4_0,Calibration code: This is the calibration code that was determined by the calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "RX_SDCAL0_TUNE__RX_SDCAL0_START_j,Signal detect calibration 0 start register Offset = 8084h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 21.--31. 1. "RX_SDCAL0_TUNE_15_5,Reserved"
bitfld.long 0x04 16.--20. "RX_SDCAL0_TUNE_4_0,Calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 15. "RX_SDCAL0_START_15,Calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.word 0x04 5.--14. 1. "RX_SDCAL0_START_14_5,Reserved"
newline
bitfld.long 0x04 0.--4. "RX_SDCAL0_START_4_0,Start calibration code: This is the calibration code that the calibration process starts with when automatic calibration is run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "RX_SDCAL0_ITER_TMR__RX_SDCAL0_INIT_TMR_j,Signal detect calibration 0 initialization timer register Offset = 8088h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x08 25.--31. 1. "RX_SDCAL0_ITER_TMR_15_9,Reserved"
hexmask.long.word 0x08 16.--24. 1. "RX_SDCAL0_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration code signals going to the analog and when the comparator value coming from the analog circuits can be.."
newline
hexmask.long.byte 0x08 9.--15. 1. "RX_SDCAL0_INIT_TMR_15_9,Reserved"
hexmask.long.word 0x08 0.--8. 1. "RX_SDCAL0_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first values are placed on the calibration code signals going to the analog"
group.long 0x8090++0x0B
line.long 0x00 "RX_SDCAL1_OVRD__RX_SDCAL1_CTRL_j,Signal detect calibration 1 control register Offset = 8090h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_SDCAL1_OVRD_15,Calibration code override enable: Activation (1'b1) of this register bit allows the calibration code determined during the automatic calibration process to be overridden" "0,1"
bitfld.long 0x00 30. "RX_SDCAL1_OVRD_14,Analog calibration enable override: Activation (1'b1) of this register bit will force the analog calibration circuits to be enabled by activating the rxda_sd_cal_1_en enable and the rxda_sd_cal_1_clk clock" "0,1"
newline
hexmask.long.word 0x00 21.--29. 1. "RX_SDCAL1_OVRD_13_5,Reserved"
bitfld.long 0x00 16.--20. "RX_SDCAL1_OVRD_4_0,Calibration code override value: These bits are used to override the calibration code determined during the automatic calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "RX_SDCAL1_CTRL_15,Start calibration: Activating (1'b1) this bit will start the calibration process" "0,1"
rbitfld.long 0x00 14. "RX_SDCAL1_CTRL_14,Calibration process done: This bit will be set to 1'b1 when the calibration process is complete" "0,1"
newline
rbitfld.long 0x00 13. "RX_SDCAL1_CTRL_13,No analog calibration response : This signal indicates that the calibration function has gone through the entire calibration process reached the final calibration value and the analog has not responded indicating that a valid.." "0,1"
rbitfld.long 0x00 12. "RX_SDCAL1_CTRL_12,Current analog comparator response: This is the current state of the analog comparator response signal (rxda_sd_cal_0_comp)" "0,1"
newline
hexmask.long.byte 0x00 5.--11. 1. "RX_SDCAL1_CTRL_11_5,Reserved"
rbitfld.long 0x00 0.--4. "RX_SDCAL1_CTRL_4_0,Calibration code: This is the calibration code that was determined by the calibration process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "RX_SDCAL1_TUNE__RX_SDCAL1_START_j,Signal detect calibration 1 start register Offset = 8094h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 21.--31. 1. "RX_SDCAL1_TUNE_15_5,Reserved"
bitfld.long 0x04 16.--20. "RX_SDCAL1_TUNE_4_0,Calibration tune value: The value of this field is added to the automatically calibrated code or the override code if override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 15. "RX_SDCAL1_START_15,Calibration direction: This controls the direction that the automatic calibration process steps the calibration codes in" "0,1"
hexmask.long.word 0x04 5.--14. 1. "RX_SDCAL1_START_14_5,Reserved"
newline
bitfld.long 0x04 0.--4. "RX_SDCAL1_START_4_0,Start calibration code: This is the calibration code that the calibration process starts with when automatic calibration is run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "RX_SDCAL1_ITER_TMR__RX_SDCAL1_INIT_TMR_j,Signal detect calibration 1 initialization timer register Offset = 8098h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x08 25.--31. 1. "RX_SDCAL1_ITER_TMR_15_9,Reserved"
hexmask.long.word 0x08 16.--24. 1. "RX_SDCAL1_ITER_TMR_8_0,Iteration wait timer value: This is the number of cmn_ref_clk clocks to wait between when a value is placed on the calibration code signals going to the analog and when the comparator value coming from the analog circuits can be.."
newline
hexmask.long.byte 0x08 9.--15. 1. "RX_SDCAL1_INIT_TMR_15_9,Reserved"
hexmask.long.word 0x08 0.--8. 1. "RX_SDCAL1_INIT_TMR_8_0,Initialization wait timer value: This is the number of cmn_ref_clk clocks to wait between when the analog calibration circuits are enabled and when the first values are placed on the calibration code signals going to the analog"
group.long 0x80B0++0x03
line.long 0x00 "RX_SAMP_DAC_CTRL_j,Sampler error DAC control register Offset = 80B0h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 6.--15. 1. "RX_SAMP_DAC_CTRL_15_6,Reserved"
bitfld.long 0x00 0.--5. "RX_SAMP_DAC_CTRL_5_0,Sampler error DAC value: Specifies the input value to the sampler error DAC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80C0++0x23
line.long 0x00 "RX_SLC_IPP_STAT__RX_SLC_CTRL_j,RX sampler latch calibration control register Offset = 80C0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 31. "RX_SLC_IPP_STAT_15,Reserved" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "RX_SLC_IPP_STAT_14_8,I even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I even latch in the analog.."
newline
rbitfld.long 0x00 23. "RX_SLC_IPP_STAT_7,Reserved" "0,1"
hexmask.long.byte 0x00 16.--22. 1. "RX_SLC_IPP_STAT_6_0,I odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I odd latch in the analog.."
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bitfld.long 0x00 15. "RX_SLC_CTRL_15,Start RX sampler latch calibration: Activating (1'b1) this bit will start the RX sampler latch calibration process" "0,1"
rbitfld.long 0x00 14. "RX_SLC_CTRL_14,RX sampler latch calibration process done: This bit will be set to 1'b1 when the RX sampler latch calibration process is complete" "0,1"
newline
hexmask.long.word 0x00 2.--13. 1. "RX_SLC_CTRL_13_2,Reserved"
bitfld.long 0x00 0.--1. "RX_SLC_CTRL_1_0,RX sampler latch calibration scaler: This field specifies the scaler value used for the input data accumulator" "0,1,2,3"
line.long 0x04 "RX_SLC_IPM_STAT__RX_SLC_IPP_OVRD_j,RX sampler latch calibration I predictive positive override register Offset = 80C4h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 31. "RX_SLC_IPM_STAT_15,Reserved" "0,1"
hexmask.long.byte 0x04 24.--30. 1. "RX_SLC_IPM_STAT_14_8,I even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I even latch in the analog.."
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rbitfld.long 0x04 23. "RX_SLC_IPM_STAT_7,Reserved" "0,1"
hexmask.long.byte 0x04 16.--22. 1. "RX_SLC_IPM_STAT_6_0,I odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the I odd latch in the analog.."
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bitfld.long 0x04 15. "RX_SLC_IPP_OVRD_15,I even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1"
hexmask.long.byte 0x04 8.--14. 1. "RX_SLC_IPP_OVRD_14_8,I even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I even sampler latch"
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bitfld.long 0x04 7. "RX_SLC_IPP_OVRD_7,I odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1"
hexmask.long.byte 0x04 0.--6. 1. "RX_SLC_IPP_OVRD_6_0,I odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I odd sampler latch"
line.long 0x08 "RX_SLC_QPP_STAT__RX_SLC_IPM_OVRD_j,RX sampler latch calibration I predictive negative override register Offset = 80C8h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x08 31. "RX_SLC_QPP_STAT_15,Reserved" "0,1"
hexmask.long.byte 0x08 24.--30. 1. "RX_SLC_QPP_STAT_14_8,Q even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q even latch in the analog.."
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rbitfld.long 0x08 23. "RX_SLC_QPP_STAT_7,Reserved" "0,1"
hexmask.long.byte 0x08 16.--22. 1. "RX_SLC_QPP_STAT_6_0,Q odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q odd latch in the analog.."
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bitfld.long 0x08 15. "RX_SLC_IPM_OVRD_15,I eve latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1"
hexmask.long.byte 0x08 8.--14. 1. "RX_SLC_IPM_OVRD_14_8,I even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I even sampler latch"
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bitfld.long 0x08 7. "RX_SLC_IPM_OVRD_7,I odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the I odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1"
hexmask.long.byte 0x08 0.--6. 1. "RX_SLC_IPM_OVRD_6_0,I odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the I odd sampler latch"
line.long 0x0C "RX_SLC_QPM_STAT__RX_SLC_QPP_OVRD_j,RX sampler latch calibration Q predictive positive override register Offset = 80CCh + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x0C 31. "RX_SLC_QPM_STAT_15,Reserved" "0,1"
hexmask.long.byte 0x0C 24.--30. 1. "RX_SLC_QPM_STAT_14_8,Q even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q even latch in the analog.."
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rbitfld.long 0x0C 23. "RX_SLC_QPM_STAT_7,Reserved" "0,1"
hexmask.long.byte 0x0C 16.--22. 1. "RX_SLC_QPM_STAT_6_0,Q odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the Q odd latch in the analog.."
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bitfld.long 0x0C 15. "RX_SLC_QPP_OVRD_15,Q even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1"
hexmask.long.byte 0x0C 8.--14. 1. "RX_SLC_QPP_OVRD_14_8,Q even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q even sampler latch"
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bitfld.long 0x0C 7. "RX_SLC_QPP_OVRD_7,Q odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "RX_SLC_QPP_OVRD_6_0,Q odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q odd sampler latch"
line.long 0x10 "RX_SLC_EPP_STAT__RX_SLC_QPM_OVRD_j,RX sampler latch calibration Q predictive negative override register Offset = 80D0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x10 31. "RX_SLC_EPP_STAT_15,Reserved" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "RX_SLC_EPP_STAT_14_8,e even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e even latch in the analog.."
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rbitfld.long 0x10 23. "RX_SLC_EPP_STAT_7,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "RX_SLC_EPP_STAT_6_0,e odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e odd latch in the analog.."
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bitfld.long 0x10 15. "RX_SLC_QPM_OVRD_15,Q even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1"
hexmask.long.byte 0x10 8.--14. 1. "RX_SLC_QPM_OVRD_14_8,Q even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q even sampler latch"
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bitfld.long 0x10 7. "RX_SLC_QPM_OVRD_7,Q odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the Q odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1"
hexmask.long.byte 0x10 0.--6. 1. "RX_SLC_QPM_OVRD_6_0,Q odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the Q odd sampler latch"
line.long 0x14 "RX_SLC_EPM_STAT__RX_SLC_EPP_OVRD_j,RX sampler latch calibration e predictive positive override register Offset = 80D4h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x14 31. "RX_SLC_EPM_STAT_15,Reserved" "0,1"
hexmask.long.byte 0x14 24.--30. 1. "RX_SLC_EPM_STAT_14_8,e even latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e even latch in the analog.."
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rbitfld.long 0x14 23. "RX_SLC_EPM_STAT_7,Reserved" "0,1"
hexmask.long.byte 0x14 16.--22. 1. "RX_SLC_EPM_STAT_6_0,e odd latch receiver sampler calibration DAC value: This field contains the current value that the RX sampler latch calibration module has calculated to drive to the DAC that controls the offset for the e odd latch in the analog.."
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bitfld.long 0x14 15. "RX_SLC_EPP_OVRD_15,e even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1"
hexmask.long.byte 0x14 8.--14. 1. "RX_SLC_EPP_OVRD_14_8,e even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e even sampler latch"
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bitfld.long 0x14 7. "RX_SLC_EPP_OVRD_7,e odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1"
hexmask.long.byte 0x14 0.--6. 1. "RX_SLC_EPP_OVRD_6_0,e odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e odd sampler latch"
line.long 0x18 "RX_SLC_INIT_TMR__RX_SLC_EPM_OVRD_j,RX sampler latch calibration e predictive negative override register Offset = 80D8h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x18 16.--31. 1. "RX_SLC_INIT_TMR_15_0,RX sampler latch calibration initialization timer value : This is the value that will be used for the RX sampler latch calibration initialization timer which controls the time the rxda_sampler_latch_cal_en is held active prior to.."
bitfld.long 0x18 15. "RX_SLC_EPM_OVRD_15,e even latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e even latch receiver sampler calibration DAC override value field of this register will override the calibrated value for.." "0,1"
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hexmask.long.byte 0x18 8.--14. 1. "RX_SLC_EPM_OVRD_14_8,e even latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e even sampler latch"
bitfld.long 0x18 7. "RX_SLC_EPM_OVRD_7,e odd latch receiver sampler calibration DAC override enable: When this bit is active (1'b1) the value in the e odd latch receiver sampler calibration DAC override value field of this register will override the calibrated value for the.." "0,1"
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hexmask.long.byte 0x18 0.--6. 1. "RX_SLC_EPM_OVRD_6_0,e odd latch receiver sampler calibration DAC override value: This field contains the value that can be used to override the calibrated value for the e odd sampler latch"
line.long 0x1C "RX_SLC_DIAG_CTRL__RX_SLC_RUN_TMR_j,RX sampler latch calibration run timer value register Offset = 80DCh + (j * 400h); where j = 0h to 3h"
bitfld.long 0x1C 31. "RX_SLC_DIAG_CTRL_15,Diagnostic control enable : This bit enables the selected RX sampler latch calibration data sub module for diagnostic purposes" "0,1"
hexmask.long.byte 0x1C 23.--30. 1. "RX_SLC_DIAG_CTRL_14_7,Reserved"
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bitfld.long 0x1C 22. "RX_SLC_DIAG_CTRL_6,Voter override neg : When enabled using the voter override enable bit in this register writing a 1'b1 in this register bit will force the voter in the selected RX sampler latch calibration data sub module to activate the voter neg.." "0,1"
bitfld.long 0x1C 21. "RX_SLC_DIAG_CTRL_5,Voter override pos : When enabled using the voter override enable bit in this register writing a 1'b1 in this register bit will force the voter in the selected RX sampler latch calibration data sub module to activate the voter pos.." "0,1"
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bitfld.long 0x1C 20. "RX_SLC_DIAG_CTRL_4,Voter override enable : Setting this bit to a 1'b1 will enable the voter override function in the selected RX sampler latch calibration data sub module" "0,1"
bitfld.long 0x1C 16.--19. "RX_SLC_DIAG_CTRL_3_0,Diagnostic control override select : Selects the RX sampler latch calibration data sub module to enable for diagnostic and verification purposes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x1C 0.--15. 1. "RX_SLC_RUN_TMR_15_0,RX sampler latch calibration run timer value : This is the value that will be used for the RX sampler latch calibration run timer which controls the run time for each calibration process"
line.long 0x20 "RX_SLC_DIS_j,RX sampler latch calibration disable register Offset = 80E0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x20 15. "RX_SLC_DIS_15,Reserved" "0,1"
bitfld.long 0x20 14. "RX_SLC_DIS_14,e even negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e even negative coefficient RX sampler latch calibration data sub module" "0,1"
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bitfld.long 0x20 13. "RX_SLC_DIS_13,q even negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q even negative coefficient RX sampler latch calibration data sub module" "0,1"
bitfld.long 0x20 12. "RX_SLC_DIS_12,i even negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i even negative coefficient RX sampler latch calibration data sub module" "0,1"
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rbitfld.long 0x20 11. "RX_SLC_DIS_11,Reserved" "0,1"
bitfld.long 0x20 10. "RX_SLC_DIS_10,e even positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e even positive coefficient RX sampler latch calibration data sub module" "0,1"
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bitfld.long 0x20 9. "RX_SLC_DIS_9,q even positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q even positive coefficient RX sampler latch calibration data sub module" "0,1"
bitfld.long 0x20 8. "RX_SLC_DIS_8,i even positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i even positive coefficient RX sampler latch calibration data sub module" "0,1"
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rbitfld.long 0x20 7. "RX_SLC_DIS_7,Reserved" "0,1"
bitfld.long 0x20 6. "RX_SLC_DIS_6,e odd negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e odd negative coefficient RX sampler latch calibration data sub module" "0,1"
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bitfld.long 0x20 5. "RX_SLC_DIS_5,q odd negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q odd negative coefficient RX sampler latch calibration data sub module" "0,1"
bitfld.long 0x20 4. "RX_SLC_DIS_4,i odd negative coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i odd negative coefficient RX sampler latch calibration data sub module" "0,1"
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rbitfld.long 0x20 3. "RX_SLC_DIS_3,Reserved" "0,1"
bitfld.long 0x20 2. "RX_SLC_DIS_2,e odd positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the e odd positive coefficient RX sampler latch calibration data sub module" "0,1"
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bitfld.long 0x20 1. "RX_SLC_DIS_1,q odd positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the q odd positive coefficient RX sampler latch calibration data sub module" "0,1"
bitfld.long 0x20 0. "RX_SLC_DIS_0,i odd positive coefficient disable : Writing a 1'b1 to this bit will disable auto calibration for the i odd positive coefficient RX sampler latch calibration data sub module" "0,1"
group.long 0x8100++0x0B
line.long 0x00 "RX_CDRLF_CNFG2__RX_CDRLF_CNFG_j,CDRLF configuration register Offset = 8100h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 31. "RX_CDRLF_CNFG2_15,Reserved" "0,1"
bitfld.long 0x00 30. "RX_CDRLF_CNFG2_14,CDRLF second order loop integrator max clear enable: This signal enables the function in the CDRLF where the second order loop integrator is cleared when it reaches the maximum value" "0,1"
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rbitfld.long 0x00 29. "RX_CDRLF_CNFG2_13,CDRLF fast phase lock locked detected: This register bit is the current status of the fphl_locked pin on the CDRLF and indicates the fast phase lock process is complete" "0,1"
bitfld.long 0x00 28. "RX_CDRLF_CNFG2_12,CDRLF fast phase lock diagnostic enable: This register bit can control the fphl_start pin on the CDRLF" "0,1"
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bitfld.long 0x00 27. "RX_CDRLF_CNFG2_11,CDRLF fast phase lock enabled by signal detect: When active signal detect will control the fphl_start pin on the CDRLF" "0,1"
bitfld.long 0x00 26. "RX_CDRLF_CNFG2_10,CDRLF reset on CDRLF PM Accumulator Max: Activating (1'b1) this bit will force the CDRLF to be reset when the PM accumulator in the CDRLF reaches is maximum absolute value (the largest positive or negative value)" "0,1"
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bitfld.long 0x00 25. "RX_CDRLF_CNFG2_9,CDRLF freeze on electrical idle detect: Activating (1'b1) this bit will force the CDRLF to be freeze in its current state when the receiver signal detect detects an electrical idle" "0,1"
bitfld.long 0x00 24. "RX_CDRLF_CNFG2_8,CDRLF reset on electrical idle detect: Activating (1'b1) this bit will force the CDRLF to be reset when the receiver signal detect detects an electrical idle" "0,1"
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rbitfld.long 0x00 22.--23. "RX_CDRLF_CNFG2_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "RX_CDRLF_CNFG2_5_0,CDRLF second order loop integrator threshold : This value is the maximum magnitude the CDRLF second order loop integrator will be allowed to go to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "RX_CDRLF_CNFG_15,CDLRF reset hold: When active (1'b1) the CDRLF will be held in reset beyond the time that it would normally be released by its asynchronous release signals" "0,1"
bitfld.long 0x00 12.--14. "RX_CDRLF_CNFG_14_12,CDRLF diagnostic mode control: This field controls the information driven on the rx_pi_val_ln_{15:0}[7:0] signal when in diagnostics mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 11. "RX_CDRLF_CNFG_11,CDRLF second order loop disable: Activating (1'b1) this bit will disable the CDRLF second order loop" "0,1"
bitfld.long 0x00 6.--10. "RX_CDRLF_CNFG_10_6,CDRLF second order loop sigma delta update rate: This is the value that is added to or subtracted from the second order loop accumulator register when the serial data sample clock is detected as being out of phase with the serial data.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "RX_CDRLF_CNFG_5,CDRLF first order loop disable: Activating (1'b1) this bit will disable the CDRLF first order loop" "0,1"
bitfld.long 0x00 0.--4. "RX_CDRLF_CNFG_4_0,CDRLF first order loop sigma delta update rate: This is the value that is added to or subtracted from the first order loop accumulator register when the serial data sample clock is detected as being out of phase with the serial data on.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "RX_CDRLF_MGN_DIAG__RX_CDRLF_CNFG3_j,CDRLF configuration register 3 Offset = 8104h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 19.--31. 1. "RX_CDRLF_MGN_DIAG_15_3,Reserved"
bitfld.long 0x04 18. "RX_CDRLF_MGN_DIAG_2,CDRLF PI override down : When the CDRLF PI override enable function is enabled writing a 1'b1 to this bit will force a down to be generated in the CDRLF PI interface logic" "0,1"
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bitfld.long 0x04 17. "RX_CDRLF_MGN_DIAG_1,CDRLF PI override up : When the CDRLF PI override enable function is enabled writing a 1'b1 to this bit will force an up to be generated in the CDRLF PI interface logic" "0,1"
bitfld.long 0x04 16. "RX_CDRLF_MGN_DIAG_0,CDRLF PI override enable : Setting this bit to 1'b1 will enable the CDRLF PI override function which will allow ups and downs to be forced to the CDRLF PI interface logic from the up and down override bits in this register" "0,1"
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hexmask.long.word 0x04 4.--15. 1. "RX_CDRLF_CNFG3_15_4,Reserved"
bitfld.long 0x04 3. "RX_CDRLF_CNFG3_3,CDRLF data filter enable standard mode" "0,1"
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bitfld.long 0x04 2. "RX_CDRLF_CNFG3_2,CDRLF data filter enable standard mode" "0,1"
bitfld.long 0x04 1. "RX_CDRLF_CNFG3_1,CDRLF data filter enable standard mode" "0,1"
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bitfld.long 0x04 0. "RX_CDRLF_CNFG3_0,CDRLF data filter enable standard mode" "0,1"
line.long 0x08 "RX_CDRLF_FPL_TMR1__RX_CDRLF_FPL_TMR0_j,CDRLF fast phase lock timer value register 0 Offset = 8108h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x08 28.--31. "RX_CDRLF_FPL_TMR1_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "RX_CDRLF_FPL_TMR1_11_8,Fast phase lock timer trigger 1 state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the trigger state the first time it is in that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "RX_CDRLF_FPL_TMR1_7_4,Fast phase lock timer trigger 2 state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the trigger state the second time it is in that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "RX_CDRLF_FPL_TMR1_3_0,Fast phase lock timer trigger 3 state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the trigger state the third time it is in that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "RX_CDRLF_FPL_TMR0_15_8,Reserved"
bitfld.long 0x08 4.--7. "RX_CDRLF_FPL_TMR0_7_4,Fast phase lock timer accumulate state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the accumulate state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "RX_CDRLF_FPL_TMR0_3_0,Fast phase lock timer delay state time value : Specifies the number of clock cycles minus 1 that the fast phase lock state machine will remain in the delay state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8120++0x1B
line.long 0x00 "RX_SIGDET_HL_DLY_TMR__RX_SIGDET_HL_FILT_TMR_j,Receiver signal detect filter high to low filter timer register Offset = 8120h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 22.--31. 1. "RX_SIGDET_HL_DLY_TMR_15_6,Reserved"
bitfld.long 0x00 16.--21. "RX_SIGDET_HL_DLY_TMR_5_0,Signal detect filter high to low delay timer value: This is the value loaded into the delay timer in the signal detect high to low filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 6.--15. 1. "RX_SIGDET_HL_FILT_TMR_15_6,Reserved"
bitfld.long 0x00 0.--5. "RX_SIGDET_HL_FILT_TMR_5_0,Signal detect filter high to low filter timer value: This is the value loaded into the filter timer in the signal detect high to low filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "RX_SIGDET_HL_INIT_TMR__RX_SIGDET_HL_MIN_TMR_j,Receiver signal detect filter high to low min timer register Offset = 8124h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 22.--31. 1. "RX_SIGDET_HL_INIT_TMR_15_6,Reserved"
bitfld.long 0x04 16.--21. "RX_SIGDET_HL_INIT_TMR_5_0,Signal detect init timer value: This is the value loaded into the initialization timer in the signal detect filter high to low filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x04 6.--15. 1. "RX_SIGDET_HL_MIN_TMR_15_6,Reserved"
bitfld.long 0x04 0.--5. "RX_SIGDET_HL_MIN_TMR_5_0,Signal detect filter high to low min timer value: This is the value loaded into the min timer in the signal detect high to low filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "RX_SIGDET_LH_DLY_TMR__RX_SIGDET_LH_FILT_TMR_j,Receiver signal detect filter low to high filter timer register Offset = 8128h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 22.--31. 1. "RX_SIGDET_LH_DLY_TMR_15_6,Reserved"
bitfld.long 0x08 16.--21. "RX_SIGDET_LH_DLY_TMR_5_0,Signal detect filter low to high min timer value: This is the value loaded into the min timer in the signal detect low to high filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 6.--15. 1. "RX_SIGDET_LH_FILT_TMR_15_6,Reserved"
bitfld.long 0x08 0.--5. "RX_SIGDET_LH_FILT_TMR_5_0,Signal detect filter low to high filter timer value: This is the value loaded into the filter timer in the signal detect low to high filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "RX_SIGDET_LH_INIT_TMR__RX_SIGDET_LH_MIN_TMR_j,Receiver signal detect filter low to high min timer register Offset = 812Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x0C 22.--31. 1. "RX_SIGDET_LH_INIT_TMR_15_6,Reserved"
bitfld.long 0x0C 16.--21. "RX_SIGDET_LH_INIT_TMR_5_0,Signal detect init timer value: This is the value loaded into the initialization timer in the signal detect filter high to low filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x0C 6.--15. 1. "RX_SIGDET_LH_MIN_TMR_15_6,Reserved"
bitfld.long 0x0C 0.--5. "RX_SIGDET_LH_MIN_TMR_5_0,Signal detect filter high to low min timer value: This is the value loaded into the min timer in the signal detect high to low filter circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "RX_LFPSDET_NS_CNT__RX_LFPSDET_MD_CNT_j,Receiver LFPS detect minimum pulse distance counter register Offset = 8130h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x10 18.--31. 1. "RX_LFPSDET_NS_CNT_15_2,Reserved"
bitfld.long 0x10 16.--17. "RX_LFPSDET_NS_CNT_1_0,No signal counter value (NS): Specifies the number of clock cycles where pulse_high and pulse_low are inactive before declaring no signal" "0,1,2,3"
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hexmask.long.word 0x10 4.--15. 1. "RX_LFPSDET_MD_CNT_15_4,Reserved"
bitfld.long 0x10 0.--3. "RX_LFPSDET_MD_CNT_3_0,Minimum pulse distance counter value (MD): Specifies the minimum pulse distance for a valid LFPS sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RX_LFPSDET_MP_CNT__RX_LFPSDET_RD_CNT_j,Receiver LFPS detect ramp down counter register Offset = 8134h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x14 19.--31. 1. "RX_LFPSDET_MP_CNT_15_3,Reserved"
bitfld.long 0x14 16.--18. "RX_LFPSDET_MP_CNT_2_0,Minimum pulse duration (MP): Specifies the minimum number of clock cycles required for a given LFPS pulse to be driven active to be considered part of a valid LFPS burst" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x14 4.--15. 1. "RX_LFPSDET_RD_CNT_15_4,Reserved"
bitfld.long 0x14 0.--3. "RX_LFPSDET_RD_CNT_3_0,Ramp down counter value (RD): Species the number of clock cycles that are used in the LFPS detect ramp down process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RX_LFPSDET_DIAG_CTRL_j,Receiver LFPS detect diagnostic control register Offset = 8138h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x18 3.--15. 1. "RX_LFPSDET_DIAG_CTRL_15_3,Reserved"
bitfld.long 0x18 2. "RX_LFPSDET_DIAG_CTRL_2,Disable pulse none MD" "0,1"
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bitfld.long 0x18 1. "RX_LFPSDET_DIAG_CTRL_1,LFPS detect override enable: When active (1'b1) the LFPS detect override bit in this register will drive the LFPS detect output directly" "0,1"
bitfld.long 0x18 0. "RX_LFPSDET_DIAG_CTRL_0,LFPS detect override: When enabled by the LFPS detect override enable bit in this register this bit will drive the LFPS detect output directly" "0,1"
group.long 0x8140++0x03
line.long 0x00 "RX_EYESURF_CTRL_j,Eye surf control register Offset = 8140h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 15. "RX_EYESURF_CTRL_15,Eye surf run: Setting this bit to 1'b1 will initiate the eye surf process" "0,1"
rbitfld.long 0x00 14. "RX_EYESURF_CTRL_14,Eye surf done: When this bit is set to 1'b1 the eye surf process has completed" "0,1"
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hexmask.long.word 0x00 0.--13. 1. "RX_EYESURF_CTRL_13_0,Reserved"
group.long 0x8148++0x0F
line.long 0x00 "RX_EYESURF_TMR_DELHIGH__RX_EYESURF_TMR_DELLOW_j,Eye surf timer delay low register Offset = 8148h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 16.--31. 1. "RX_EYESURF_TMR_DELHIGH_15_0,Most significant 16 bits of the delay time: The delay time specifies the number of clock cycles to wait between when a coordinate test point is set and when to start testing the i and e data"
hexmask.long.word 0x00 0.--15. 1. "RX_EYESURF_TMR_DELLOW_15_0,Least significant 16 bits of the delay time: The delay time specifies the number of clock cycles to wait between when a coordinate test point is set and when to start testing the i and e data"
line.long 0x04 "RX_EYESURF_TMR_TESTHIGH__RX_EYESURF_TMR_TESTLOW_j,Eye surf timer test low register Offset = 814Ch + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_EYESURF_TMR_TESTHIGH_15_0,Most significant 16 bits of the test time: The test time specifies the number of clock cycles to test the i and e data at a given coordinate test point"
hexmask.long.word 0x04 0.--15. 1. "RX_EYESURF_TMR_TESTLOW_15_0,Least significant 16 bits of the test time: The test time specifies the number of clock cycles to test the i and e data at a given coordinate test point"
line.long 0x08 "RX_EYESURF_EW_COORD__RX_EYESURF_NS_COORD_j,Eye surf north south test point coordinate register Offset = 8150h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x08 25.--31. 1. "RX_EYESURF_EW_COORD_15_9,Reserved"
bitfld.long 0x08 24. "RX_EYESURF_EW_COORD_8,Test point coordinate east west direction : Indicates whether the desired test point is in" "0,1"
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rbitfld.long 0x08 21.--23. "RX_EYESURF_EW_COORD_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--20. "RX_EYESURF_EW_COORD_4_0,Test point coordinate east west offset : Indicates how many steps in the east or west" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x08 9.--15. 1. "RX_EYESURF_NS_COORD_15_9,Reserved"
bitfld.long 0x08 8. "RX_EYESURF_NS_COORD_8,Test point coordinate north south direction : Indicates whether the desired test point is in the north or the south direction relative to the origin" "0,1"
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rbitfld.long 0x08 7. "RX_EYESURF_NS_COORD_7,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "RX_EYESURF_NS_COORD_6_0,Test point coordinate north south offset : Indicates how many steps in the north or south direction the desired test point is relative to the origin"
line.long 0x0C "RX_EYESURF_ERRCNT_j,Eye surf bit error count register Offset = 8154h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x0C 0.--15. 1. "RX_EYESURF_ERRCNT_15_0,Test point bit error count : The total number of bit errors that were detected for a given run of the eye surf function"
group.long 0x8160++0x07
line.long 0x00 "RX_BIST_SYNCCNT__RX_BIST_CTRL_j,Receiver BIST control register Offset = 8160h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 16.--31. 1. "RX_BIST_SYNCCNT_15_0,Receiver BIST sync count: This field controls the value of the RX BIST sync count"
rbitfld.long 0x00 12.--15. "RX_BIST_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "RX_BIST_CTRL_11_8,Receiver BIST mode: Controls which mode the BIST will operate in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 5.--7. "RX_BIST_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "RX_BIST_CTRL_4,Receiver BIST error reset: Writing this bit is set to a 1'b1 will hold the error indicators in the receive BIST logic in reset" "0,1"
rbitfld.long 0x00 2.--3. "RX_BIST_CTRL_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x00 1. "RX_BIST_CTRL_1,Receiver BIST user defined data FIFO clear: Writing a 1'b1 to this bit will clear the receiver BIST user defined data FIFO" "0,1"
bitfld.long 0x00 0. "RX_BIST_CTRL_0,Receiver BIST enable: This bit enables the receiver BIST function" "0,1"
line.long 0x04 "RX_BIST_ERRCNT__RX_BIST_UDDWR_j,Receiver BIST user defined data write register Offset = 8164h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_BIST_ERRCNT_15_0,Receiver BIST error count: Indicates the number of BIST errors that have been observed by the receive BIST logic since the last time the BIST error indicator logic was reset or restarted"
rbitfld.long 0x04 10.--15. "RX_BIST_UDDWR_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x04 0.--9. 1. "RX_BIST_UDDWR_9_0,Receiver BIST user defined data: Writing a data word to this field will result in that data word being placed in the next available position in the receiver BIST user defined data FIFO"
group.long 0x8200++0x0B
line.long 0x00 "RX_REE_PTXEQSM_EQENM_EVAL__RX_REE_PTXEQSM_CTRL_j,REE PCIe TX equalization control state machine control register Offset = 8200h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_REE_PTXEQSM_EQENM_EVAL_15,Reserved - spare" "0,1"
bitfld.long 0x00 30. "RX_REE_PTXEQSM_EQENM_EVAL_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 29. "RX_REE_PTXEQSM_EQENM_EVAL_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x00 28. "RX_REE_PTXEQSM_EQENM_EVAL_12,TX post cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 27. "RX_REE_PTXEQSM_EQENM_EVAL_11,TX pre cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x00 26. "RX_REE_PTXEQSM_EQENM_EVAL_10,Short channel correction : When set to 1'b1 this function is enabled when the TX equalization general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 25. "RX_REE_PTXEQSM_EQENM_EVAL_9,RX attenuation : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x00 24. "RX_REE_PTXEQSM_EQENM_EVAL_8,RX VGA gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 23. "RX_REE_PTXEQSM_EQENM_EVAL_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x00 22. "RX_REE_PTXEQSM_EQENM_EVAL_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 21. "RX_REE_PTXEQSM_EQENM_EVAL_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x00 20. "RX_REE_PTXEQSM_EQENM_EVAL_4,Reserved - spare" "0,1"
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bitfld.long 0x00 19. "RX_REE_PTXEQSM_EQENM_EVAL_3,Reserved - spare" "0,1"
bitfld.long 0x00 18. "RX_REE_PTXEQSM_EQENM_EVAL_2,RX tap3 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 17. "RX_REE_PTXEQSM_EQENM_EVAL_1,RX tap2 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x00 16. "RX_REE_PTXEQSM_EQENM_EVAL_0,RX tap1 : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "RX_REE_PTXEQSM_CTRL_15_0,Reserved"
line.long 0x04 "RX_REE_PTXEQSM_PEVAL_TMR__RX_REE_PTXEQSM_EQENM_PEVAL_j,REE PCIe TX equalization control state machine equalization enable mask for PCIe post evaluation equalization register Offset = 8204h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_REE_PTXEQSM_PEVAL_TMR_15_0,Run post evaluation equalization timer value : This specifies number of clock cycles the state machine will wait in the Post Evaluation Equalization state"
bitfld.long 0x04 15. "RX_REE_PTXEQSM_EQENM_PEVAL_15,Reserved - spare" "0,1"
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bitfld.long 0x04 14. "RX_REE_PTXEQSM_EQENM_PEVAL_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x04 13. "RX_REE_PTXEQSM_EQENM_PEVAL_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 12. "RX_REE_PTXEQSM_EQENM_PEVAL_12,TX post cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x04 11. "RX_REE_PTXEQSM_EQENM_PEVAL_11,TX pre cursor control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 10. "RX_REE_PTXEQSM_EQENM_PEVAL_10,Short channel correction : When set to 1'b1 this function is enabled when the TX equalization general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 9. "RX_REE_PTXEQSM_EQENM_PEVAL_9,RX attenuation : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 8. "RX_REE_PTXEQSM_EQENM_PEVAL_8,RX VGA gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x04 7. "RX_REE_PTXEQSM_EQENM_PEVAL_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 6. "RX_REE_PTXEQSM_EQENM_PEVAL_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
bitfld.long 0x04 5. "RX_REE_PTXEQSM_EQENM_PEVAL_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the PCIe TX equalization control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 4. "RX_REE_PTXEQSM_EQENM_PEVAL_4,Reserved - spare" "0,1"
bitfld.long 0x04 3. "RX_REE_PTXEQSM_EQENM_PEVAL_3,Reserved - spare" "0,1"
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bitfld.long 0x04 2. "RX_REE_PTXEQSM_EQENM_PEVAL_2,RX tap" "0,1"
bitfld.long 0x04 1. "RX_REE_PTXEQSM_EQENM_PEVAL_1,RX tap" "0,1"
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bitfld.long 0x04 0. "RX_REE_PTXEQSM_EQENM_PEVAL_0,RX tap" "0,1"
line.long 0x08 "RX_REE_PTXEQSM_MAX_EVAL_CNT__RX_REE_PTXEQSM_TIMEOUT_TMR_j,REE PCIe TX equalization control state machine time-out timer value register Offset = 8208h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 22.--31. 1. "RX_REE_PTXEQSM_MAX_EVAL_CNT_15_6,Reserved"
bitfld.long 0x08 16.--21. "RX_REE_PTXEQSM_MAX_EVAL_CNT_5_0,Incremental evaluation counter load value: This is the maximum number of incremental evaluations that will be performed plus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x08 0.--15. 1. "RX_REE_PTXEQSM_TIMEOUT_TMR_15_0,Time-out timer load value: This specifies the number of clocks to run a PCIe evaluation before a time-out is indicated"
group.long 0x8210++0x0B
line.long 0x00 "RX_REE_GCSM1_EQENM_PH1__RX_REE_GCSM1_CTRL_j,REE general control state machine 1 control register Offset = 8210h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_REE_GCSM1_EQENM_PH1_15,Reserved - spare" "0,1"
bitfld.long 0x00 30. "RX_REE_GCSM1_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x00 29. "RX_REE_GCSM1_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x00 28. "RX_REE_GCSM1_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x00 27. "RX_REE_GCSM1_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x00 26. "RX_REE_GCSM1_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x00 25. "RX_REE_GCSM1_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x00 24. "RX_REE_GCSM1_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x00 23. "RX_REE_GCSM1_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x00 22. "RX_REE_GCSM1_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x00 21. "RX_REE_GCSM1_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x00 20. "RX_REE_GCSM1_EQENM_PH1_4,Reserved - spare" "0,1"
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bitfld.long 0x00 19. "RX_REE_GCSM1_EQENM_PH1_3,Reserved - spare" "0,1"
bitfld.long 0x00 18. "RX_REE_GCSM1_EQENM_PH1_2,RX tap" "0,1"
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bitfld.long 0x00 17. "RX_REE_GCSM1_EQENM_PH1_1,RX tap" "0,1"
bitfld.long 0x00 16. "RX_REE_GCSM1_EQENM_PH1_0,RX tap" "0,1"
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hexmask.long.word 0x00 4.--15. 1. "RX_REE_GCSM1_CTRL_15_4,Reserved"
bitfld.long 0x00 3. "RX_REE_GCSM1_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n signal when the equalization mode changes" "0,1"
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bitfld.long 0x00 2. "RX_REE_GCSM1_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously" "0,1"
bitfld.long 0x00 1. "RX_REE_GCSM1_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization" "0,1"
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bitfld.long 0x00 0. "RX_REE_GCSM1_CTRL_0,Enable: This bit enables the general control state machine function" "0,1"
line.long 0x04 "RX_REE_GCSM1_START_TMR__RX_REE_GCSM1_EQENM_PH2_j,REE general control state machine 1 phase 2 equalization enable mask register Offset = 8214h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_REE_GCSM1_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state"
bitfld.long 0x04 15. "RX_REE_GCSM1_EQENM_PH2_15,Reserved - spare" "0,1"
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bitfld.long 0x04 14. "RX_REE_GCSM1_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x04 13. "RX_REE_GCSM1_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x04 12. "RX_REE_GCSM1_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x04 11. "RX_REE_GCSM1_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x04 10. "RX_REE_GCSM1_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x04 9. "RX_REE_GCSM1_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x04 8. "RX_REE_GCSM1_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x04 7. "RX_REE_GCSM1_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x04 6. "RX_REE_GCSM1_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
bitfld.long 0x04 5. "RX_REE_GCSM1_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 1 is controlling the REE" "0,1"
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bitfld.long 0x04 4. "RX_REE_GCSM1_EQENM_PH2_4,Reserved - spare" "0,1"
bitfld.long 0x04 3. "RX_REE_GCSM1_EQENM_PH2_3,Reserved - spare" "0,1"
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bitfld.long 0x04 2. "RX_REE_GCSM1_EQENM_PH2_2,RX tap" "0,1"
bitfld.long 0x04 1. "RX_REE_GCSM1_EQENM_PH2_1,RX tap" "0,1"
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bitfld.long 0x04 0. "RX_REE_GCSM1_EQENM_PH2_0,RX tap" "0,1"
line.long 0x08 "RX_REE_GCSM1_RUN_PH2_TMR__RX_REE_GCSM1_RUN_PH1_TMR_j,REE general control state machine 1 run phase 1 timer value register Offset = 8218h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 16.--31. 1. "RX_REE_GCSM1_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state"
hexmask.long.word 0x08 0.--15. 1. "RX_REE_GCSM1_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state"
group.long 0x8220++0x0B
line.long 0x00 "RX_REE_GCSM2_EQENM_PH1__RX_REE_GCSM2_CTRL_j,REE general control state machine 2 control register Offset = 8220h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_REE_GCSM2_EQENM_PH1_15,Reserved - spare" "0,1"
bitfld.long 0x00 30. "RX_REE_GCSM2_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x00 29. "RX_REE_GCSM2_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x00 28. "RX_REE_GCSM2_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x00 27. "RX_REE_GCSM2_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x00 26. "RX_REE_GCSM2_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x00 25. "RX_REE_GCSM2_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x00 24. "RX_REE_GCSM2_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x00 23. "RX_REE_GCSM2_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x00 22. "RX_REE_GCSM2_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x00 21. "RX_REE_GCSM2_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x00 20. "RX_REE_GCSM2_EQENM_PH1_4,Reserved - spare" "0,1"
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bitfld.long 0x00 19. "RX_REE_GCSM2_EQENM_PH1_3,Reserved - spare" "0,1"
bitfld.long 0x00 18. "RX_REE_GCSM2_EQENM_PH1_2,RX tap" "0,1"
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bitfld.long 0x00 17. "RX_REE_GCSM2_EQENM_PH1_1,RX tap" "0,1"
bitfld.long 0x00 16. "RX_REE_GCSM2_EQENM_PH1_0,RX tap" "0,1"
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hexmask.long.word 0x00 4.--15. 1. "RX_REE_GCSM2_CTRL_15_4,Reserved"
bitfld.long 0x00 3. "RX_REE_GCSM2_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n signal when the equalization mode changes" "0,1"
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bitfld.long 0x00 2. "RX_REE_GCSM2_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously" "0,1"
bitfld.long 0x00 1. "RX_REE_GCSM2_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization" "0,1"
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bitfld.long 0x00 0. "RX_REE_GCSM2_CTRL_0,Enable: This bit enables the general control state machine function" "0,1"
line.long 0x04 "RX_REE_GCSM2_START_TMR__RX_REE_GCSM2_EQENM_PH2_j,REE general control state machine 2 phase 2 equalization enable mask register Offset = 8224h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_REE_GCSM2_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state"
bitfld.long 0x04 15. "RX_REE_GCSM2_EQENM_PH2_15,Reserved - spare" "0,1"
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bitfld.long 0x04 14. "RX_REE_GCSM2_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x04 13. "RX_REE_GCSM2_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x04 12. "RX_REE_GCSM2_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x04 11. "RX_REE_GCSM2_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x04 10. "RX_REE_GCSM2_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x04 9. "RX_REE_GCSM2_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x04 8. "RX_REE_GCSM2_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x04 7. "RX_REE_GCSM2_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x04 6. "RX_REE_GCSM2_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
bitfld.long 0x04 5. "RX_REE_GCSM2_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the general control state machine 2 is controlling the REE" "0,1"
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bitfld.long 0x04 4. "RX_REE_GCSM2_EQENM_PH2_4,Reserved - spare" "0,1"
bitfld.long 0x04 3. "RX_REE_GCSM2_EQENM_PH2_3,Reserved - spare" "0,1"
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bitfld.long 0x04 2. "RX_REE_GCSM2_EQENM_PH2_2,RX tap" "0,1"
bitfld.long 0x04 1. "RX_REE_GCSM2_EQENM_PH2_1,RX tap" "0,1"
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bitfld.long 0x04 0. "RX_REE_GCSM2_EQENM_PH2_0,RX tap" "0,1"
line.long 0x08 "RX_REE_GCSM2_RUN_PH2_TMR__RX_REE_GCSM2_RUN_PH1_TMR_j,REE general control state machine 2 run phase 1 timer value register Offset = 8228h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 16.--31. 1. "RX_REE_GCSM2_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state"
hexmask.long.word 0x08 0.--15. 1. "RX_REE_GCSM2_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state"
group.long 0x8230++0x0B
line.long 0x00 "RX_REE_PERGCSM_EQENM_PH1__RX_REE_PERGCSM_CTRL_j,REE periodic general control state machine control register Offset = 8230h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_REE_PERGCSM_EQENM_PH1_15,Reserved - spare" "0,1"
bitfld.long 0x00 30. "RX_REE_PERGCSM_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 29. "RX_REE_PERGCSM_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 28. "RX_REE_PERGCSM_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 27. "RX_REE_PERGCSM_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 26. "RX_REE_PERGCSM_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 25. "RX_REE_PERGCSM_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 24. "RX_REE_PERGCSM_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 23. "RX_REE_PERGCSM_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 22. "RX_REE_PERGCSM_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 21. "RX_REE_PERGCSM_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 20. "RX_REE_PERGCSM_EQENM_PH1_4,Reserved - spare" "0,1"
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bitfld.long 0x00 19. "RX_REE_PERGCSM_EQENM_PH1_3,Reserved - spare" "0,1"
bitfld.long 0x00 18. "RX_REE_PERGCSM_EQENM_PH1_2,RX tap" "0,1"
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bitfld.long 0x00 17. "RX_REE_PERGCSM_EQENM_PH1_1,RX tap" "0,1"
bitfld.long 0x00 16. "RX_REE_PERGCSM_EQENM_PH1_0,RX tap" "0,1"
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hexmask.long.word 0x00 4.--15. 1. "RX_REE_PERGCSM_CTRL_15_4,Reserved"
bitfld.long 0x00 3. "RX_REE_PERGCSM_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n pin when the equalization mode changes" "0,1"
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bitfld.long 0x00 2. "RX_REE_PERGCSM_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously" "0,1"
bitfld.long 0x00 1. "RX_REE_PERGCSM_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization" "0,1"
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bitfld.long 0x00 0. "RX_REE_PERGCSM_CTRL_0,Enable: This bit enables the general control state machine function" "0,1"
line.long 0x04 "RX_REE_PERGCSM_START_TMR__RX_REE_PERGCSM_EQENM_PH2_j,REE periodic general control state machine phase 2 equalization enable mask register Offset = 8234h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_REE_PERGCSM_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state"
bitfld.long 0x04 15. "RX_REE_PERGCSM_EQENM_PH2_15,Reserved - spare" "0,1"
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bitfld.long 0x04 14. "RX_REE_PERGCSM_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 13. "RX_REE_PERGCSM_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 12. "RX_REE_PERGCSM_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 11. "RX_REE_PERGCSM_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 10. "RX_REE_PERGCSM_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 9. "RX_REE_PERGCSM_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 8. "RX_REE_PERGCSM_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 7. "RX_REE_PERGCSM_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 6. "RX_REE_PERGCSM_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 5. "RX_REE_PERGCSM_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the periodic general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 4. "RX_REE_PERGCSM_EQENM_PH2_4,Reserved - spare" "0,1"
bitfld.long 0x04 3. "RX_REE_PERGCSM_EQENM_PH2_3,Reserved - spare" "0,1"
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bitfld.long 0x04 2. "RX_REE_PERGCSM_EQENM_PH2_2,RX tap" "0,1"
bitfld.long 0x04 1. "RX_REE_PERGCSM_EQENM_PH2_1,RX tap" "0,1"
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bitfld.long 0x04 0. "RX_REE_PERGCSM_EQENM_PH2_0,RX tap" "0,1"
line.long 0x08 "RX_REE_PERGCSM_RUN_PH2_TMR__RX_REE_PERGCSM_RUN_PH1_TMR_j,REE periodic general control state machine run phase 1 timer value register Offset = 8238h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 16.--31. 1. "RX_REE_PERGCSM_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state"
hexmask.long.word 0x08 0.--15. 1. "RX_REE_PERGCSM_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state"
group.long 0x8240++0x0B
line.long 0x00 "RX_REE_U3GCSM_EQENM_PH1__RX_REE_U3GCSM_CTRL_j,REE USB 3 general control state machine control register Offset = 8240h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x00 31. "RX_REE_U3GCSM_EQENM_PH1_15,Reserved - spare" "0,1"
bitfld.long 0x00 30. "RX_REE_U3GCSM_EQENM_PH1_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 29. "RX_REE_U3GCSM_EQENM_PH1_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 28. "RX_REE_U3GCSM_EQENM_PH1_12,TX post cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 27. "RX_REE_U3GCSM_EQENM_PH1_11,TX pre cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 26. "RX_REE_U3GCSM_EQENM_PH1_10,Short channel correction : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 25. "RX_REE_U3GCSM_EQENM_PH1_9,RX attenuation : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 24. "RX_REE_U3GCSM_EQENM_PH1_8,RX VGA gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 23. "RX_REE_U3GCSM_EQENM_PH1_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 22. "RX_REE_U3GCSM_EQENM_PH1_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x00 21. "RX_REE_U3GCSM_EQENM_PH1_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x00 20. "RX_REE_U3GCSM_EQENM_PH1_4,Reserved - spare" "0,1"
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bitfld.long 0x00 19. "RX_REE_U3GCSM_EQENM_PH1_3,Reserved - spare" "0,1"
bitfld.long 0x00 18. "RX_REE_U3GCSM_EQENM_PH1_2,RX tap" "0,1"
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bitfld.long 0x00 17. "RX_REE_U3GCSM_EQENM_PH1_1,RX tap" "0,1"
bitfld.long 0x00 16. "RX_REE_U3GCSM_EQENM_PH1_0,RX tap" "0,1"
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hexmask.long.word 0x00 4.--15. 1. "RX_REE_U3GCSM_CTRL_15_4,Reserved"
bitfld.long 0x00 3. "RX_REE_U3GCSM_CTRL_3,Equalization function reset enable: Enables the reset of the functions controlled by this state machine using the rx_ree_fcn_reset_n pin when the equalization mode changes" "0,1"
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bitfld.long 0x00 2. "RX_REE_U3GCSM_CTRL_2,Loop enable: Controls when the equalization functions in this state machine are run one time or loop continuously" "0,1"
bitfld.long 0x00 1. "RX_REE_U3GCSM_CTRL_1,Force run equalization: Setting this bit to a 1'b1 will force the general control state machine to run independent of the macro functions that normally run the equalization" "0,1"
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bitfld.long 0x00 0. "RX_REE_U3GCSM_CTRL_0,Enable: This bit enables the general control state machine function" "0,1"
line.long 0x04 "RX_REE_U3GCSM_START_TMR__RX_REE_U3GCSM_EQENM_PH2_j,REE USB 3 general control state machine phase 2 equalization enable mask register Offset = 8244h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "RX_REE_U3GCSM_START_TMR_15_0,Start timer value : The number of clock cycles the state machine will wait in the Start Delay state"
bitfld.long 0x04 15. "RX_REE_U3GCSM_EQENM_PH2_15,Reserved - spare" "0,1"
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bitfld.long 0x04 14. "RX_REE_U3GCSM_EQENM_PH2_14,Ignore 1010 controller : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 13. "RX_REE_U3GCSM_EQENM_PH2_13,TX equalization evaluator : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 12. "RX_REE_U3GCSM_EQENM_PH2_12,TX post cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 11. "RX_REE_U3GCSM_EQENM_PH2_11,TX pre cursor control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 10. "RX_REE_U3GCSM_EQENM_PH2_10,Short channel correction : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 9. "RX_REE_U3GCSM_EQENM_PH2_9,RX attenuation : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 8. "RX_REE_U3GCSM_EQENM_PH2_8,RX VGA gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 7. "RX_REE_U3GCSM_EQENM_PH2_7,RX offset correction coefficient : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 6. "RX_REE_U3GCSM_EQENM_PH2_6,RX peaking amp gain : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
bitfld.long 0x04 5. "RX_REE_U3GCSM_EQENM_PH2_5,RX low frequency equalizer adaptive control : When set to 1'b1 this function is enabled when the USB 3.0 general control state machine is controlling the REE" "0,1"
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bitfld.long 0x04 4. "RX_REE_U3GCSM_EQENM_PH2_4,Reserved - spare" "0,1"
bitfld.long 0x04 3. "RX_REE_U3GCSM_EQENM_PH2_3,Reserved - spare" "0,1"
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bitfld.long 0x04 2. "RX_REE_U3GCSM_EQENM_PH2_2,RX tap" "0,1"
bitfld.long 0x04 1. "RX_REE_U3GCSM_EQENM_PH2_1,RX tap" "0,1"
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bitfld.long 0x04 0. "RX_REE_U3GCSM_EQENM_PH2_0,RX tap" "0,1"
line.long 0x08 "RX_REE_U3GCSM_RUN_PH2_TMR__RX_REE_U3GCSM_RUN_PH1_TMR_j,REE USB 3 general control state machine run phase 1 timer value register Offset = 8248h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x08 16.--31. 1. "RX_REE_U3GCSM_RUN_PH2_TMR_15_0,Run phase 2 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 2 state"
hexmask.long.word 0x08 0.--15. 1. "RX_REE_U3GCSM_RUN_PH1_TMR_15_0,Run phase 1 timer value : This specifies the number of clock cycles the state machine will wait in the Run Equalization Phase 1 state"
group.long 0x8250++0x03
line.long 0x00 "RX_REE_ANAENSM_DEL_TMR_j,REE analog enable control state machine delay timer value register Offset = 8250h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 0.--15. 1. "RX_REE_ANAENSM_DEL_TMR_15_0,Analog enable delay timer value : The number of clock cycles the state machine will wait in the Analog Enable Delay state"
group.long 0x8260++0x17
line.long 0x00 "RX_REE_TXPOST_CODE_CTRL__RX_REE_TXPOST_CTRL_j,REE TX post cursor control register Offset = 8260h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 30.--31. "RX_REE_TXPOST_CODE_CTRL_15_14,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "RX_REE_TXPOST_CODE_CTRL_13_8,Peaking amp code maximum value: This is the maximum value that the peaking amp code will be allowed to increase to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 22.--23. "RX_REE_TXPOST_CODE_CTRL_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "RX_REE_TXPOST_CODE_CTRL_5_0,Peaking amp initial code: Initial value the peaking amp code is set to when training starts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 12.--15. "RX_REE_TXPOST_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "RX_REE_TXPOST_CTRL_11,Peaking amp feedback path enable: Enables the peaking amp feedback path" "0,1"
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bitfld.long 0x00 8.--10. "RX_REE_TXPOST_CTRL_10_8,Peaking amp feedback scaler value: Specifies the amount to scale the peaking amp feedback by" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RX_REE_TXPOST_CTRL_7,Reserved" "0,1"
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bitfld.long 0x00 4.--6. "RX_REE_TXPOST_CTRL_6_4,Peaking amp integrator accumulator scaler value: Specifies the amount to scale the input to the peaking amp integrator accumulator by" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "RX_REE_TXPOST_CTRL_3_0,Peaking amp sigma delta accumulator scaler value: Specifies the amount to scale the input to the peaking amp sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "RX_REE_TXPOST_LTHR__RX_REE_TXPOST_UTHR_j,REE TX post cursor upper threshold register Offset = 8264h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x04 25.--31. 1. "RX_REE_TXPOST_LTHR_15_9,Reserved"
hexmask.long.word 0x04 16.--24. 1. "RX_REE_TXPOST_LTHR_8_0,Peaking amp algorithm lower threshold: This is the lower threshold value used in the peaking amp algorithm"
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hexmask.long.byte 0x04 9.--15. 1. "RX_REE_TXPOST_UTHR_15_9,Reserved"
hexmask.long.word 0x04 0.--8. 1. "RX_REE_TXPOST_UTHR_8_0,Peaking amp algorithm upper threshold: This is the upper threshold value used in the peaking amp algorithm"
line.long 0x08 "RX_REE_TXPOST_COVRD0__RX_REE_TXPOST_IOVRD_j,REE TX post cursor input override register Offset = 8268h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x08 30.--31. "RX_REE_TXPOST_COVRD0_15_14,Reserved" "0,1,2,3"
bitfld.long 0x08 24.--29. "RX_REE_TXPOST_COVRD0_13_8,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x08 22.--23. "RX_REE_TXPOST_COVRD0_7_6,Reserved" "0,1,2,3"
bitfld.long 0x08 16.--21. "RX_REE_TXPOST_COVRD0_5_0,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 15. "RX_REE_TXPOST_IOVRD_15,Peaking amp tap accumulator input override enable: Setting this bit to a 1'b1 will allow the tap accumulator input in the peaking amp gain algorithm to be overridden by the peaking amp tap accumulator input override field in this.." "0,1"
hexmask.long.byte 0x08 8.--14. 1. "RX_REE_TXPOST_IOVRD_14_8,Reserved"
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hexmask.long.byte 0x08 0.--7. 1. "RX_REE_TXPOST_IOVRD_7_0,Peaking amp tap accumulator input override : Value that will override the tap accumulator input in the peaking amp gain algorithm when the Peaking amp tap accumulator input override enable bit is active"
line.long 0x0C "RX_REE_TXPOST_DIAG__RX_REE_TXPOST_COVRD1_j,REE TX post cursor code override 1 register Offset = 826Ch + (j * 400h); where j = 0h to 3h"
bitfld.long 0x0C 31. "RX_REE_TXPOST_DIAG_15,Peaking amp code override enable: Setting this bit to a 1'b1 will allow the peaking amp code to be overridden by the peaking amp code override value fields in the REE TX post cursor code override 0 register on page 258 and REE TX.." "0,1"
bitfld.long 0x0C 30. "RX_REE_TXPOST_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x0C 29. "RX_REE_TXPOST_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x0C 28. "RX_REE_TXPOST_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the peaking amp" "0,1"
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rbitfld.long 0x0C 24.--27. "RX_REE_TXPOST_DIAG_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x0C 22.--23. "RX_REE_TXPOST_DIAG_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x0C 16.--21. "RX_REE_TXPOST_DIAG_5_0,Current peaking amp integrator accumulator: Current value of the tap integrator accumulator without the unused sign bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x0C 14.--15. "RX_REE_TXPOST_COVRD1_15_14,Reserved" "0,1,2,3"
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bitfld.long 0x0C 8.--13. "RX_REE_TXPOST_COVRD1_13_8,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x0C 6.--7. "RX_REE_TXPOST_COVRD1_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x0C 0.--5. "RX_REE_TXPOST_COVRD1_5_0,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "RX_REE_TXPRE_OVRD__RX_REE_TXPRE_CTRL_j,REE TX pre cursor control register Offset = 8270h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x10 24.--31. 1. "RX_REE_TXPRE_OVRD_15_8,Reserved"
bitfld.long 0x10 23. "RX_REE_TXPRE_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions" "0,1"
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rbitfld.long 0x10 22. "RX_REE_TXPRE_OVRD_6,Reserved" "0,1"
bitfld.long 0x10 16.--21. "RX_REE_TXPRE_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x10 12.--15. "RX_REE_TXPRE_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 11. "RX_REE_TXPRE_CTRL_11,Tap coefficient combinational logic zero crossing enable" "0,1"
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bitfld.long 0x10 10. "RX_REE_TXPRE_CTRL_10,Tap coefficient combinational logic non zero crossing enable" "0,1"
bitfld.long 0x10 9. "RX_REE_TXPRE_CTRL_9,Tap coefficient combinational logic bit 0 only enable" "0,1"
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bitfld.long 0x10 8. "RX_REE_TXPRE_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal" "0,1"
rbitfld.long 0x10 7. "RX_REE_TXPRE_CTRL_7,Reserved" "0,1"
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bitfld.long 0x10 4.--6. "RX_REE_TXPRE_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--3. "RX_REE_TXPRE_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RX_REE_TXPRE_DIAG_j,REE TX pre cursor diagnostics register Offset = 8274h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x14 15. "RX_REE_TXPRE_DIAG_15,Reserved" "0,1"
bitfld.long 0x14 14. "RX_REE_TXPRE_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x14 13. "RX_REE_TXPRE_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x14 12. "RX_REE_TXPRE_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap" "0,1"
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rbitfld.long 0x14 6.--11. "RX_REE_TXPRE_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x14 0.--5. "RX_REE_TXPRE_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8280++0x1B
line.long 0x00 "RX_REE_PEAK_CODE_CTRL__RX_REE_PEAK_CTRL_j,REE peaking amp control register Offset = 8280h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 30.--31. "RX_REE_PEAK_CODE_CTRL_15_14,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "RX_REE_PEAK_CODE_CTRL_13_8,Peaking amp code maximum value: This is the maximum value that the peaking amp code will be allowed to increase to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 22.--23. "RX_REE_PEAK_CODE_CTRL_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "RX_REE_PEAK_CODE_CTRL_5_0,Peaking amp initial code: Initial value the peaking amp code is set to when training starts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 12.--15. "RX_REE_PEAK_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "RX_REE_PEAK_CTRL_11,Peaking amp feedback path enable: Enables the peaking amp feedback path" "0,1"
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bitfld.long 0x00 8.--10. "RX_REE_PEAK_CTRL_10_8,Peaking amp feedback scaler value: Specifies the amount to scale the peaking amp feedback by" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 7. "RX_REE_PEAK_CTRL_7,Reserved" "0,1"
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bitfld.long 0x00 4.--6. "RX_REE_PEAK_CTRL_6_4,Peaking amp integrator accumulator scaler value: Specifies the amount to scale the input to the peaking amp integrator accumulator by" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "RX_REE_PEAK_CTRL_3_0,Peaking amp sigma delta accumulator scaler value: Specifies the amount to scale the input to the peaking amp sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "RX_REE_PEAK_LTHR__RX_REE_PEAK_UTHR_j,REE peaking amp upper threshold register Offset = 8284h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x04 25.--31. 1. "RX_REE_PEAK_LTHR_15_9,Reserved"
hexmask.long.word 0x04 16.--24. 1. "RX_REE_PEAK_LTHR_8_0,Peaking amp algorithm lower threshold: This is the lower threshold value used in the peaking amp algorithm"
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hexmask.long.byte 0x04 9.--15. 1. "RX_REE_PEAK_UTHR_15_9,Reserved"
hexmask.long.word 0x04 0.--8. 1. "RX_REE_PEAK_UTHR_8_0,Peaking amp algorithm upper threshold: This is the upper threshold value used in the peaking amp algorithm"
line.long 0x08 "RX_REE_PEAK_COVRD0__RX_REE_PEAK_IOVRD_j,REE peaking amp input override register Offset = 8288h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x08 30.--31. "RX_REE_PEAK_COVRD0_15_14,Reserved" "0,1,2,3"
bitfld.long 0x08 24.--29. "RX_REE_PEAK_COVRD0_13_8,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x08 22.--23. "RX_REE_PEAK_COVRD0_7_6,Reserved" "0,1,2,3"
bitfld.long 0x08 16.--21. "RX_REE_PEAK_COVRD0_5_0,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 15. "RX_REE_PEAK_IOVRD_15,Peaking amp tap accumulator input override enable: Setting this bit to a 1'b1 will allow the tap accumulator input in the peaking amp gain algorithm to be overridden by the peaking amp tap accumulator input override field in this.." "0,1"
hexmask.long.byte 0x08 8.--14. 1. "RX_REE_PEAK_IOVRD_14_8,Reserved"
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hexmask.long.byte 0x08 0.--7. 1. "RX_REE_PEAK_IOVRD_7_0,Peaking amp tap accumulator input override : Value that will override the tap accumulator input in the peaking amp gain algorithm when the Peaking amp tap accumulator input override enable bit is active"
line.long 0x0C "RX_REE_PEAK_DIAG__RX_REE_PEAK_COVRD1_j,REE peaking amp code override 1 register Offset = 828Ch + (j * 400h); where j = 0h to 3h"
bitfld.long 0x0C 31. "RX_REE_PEAK_DIAG_15,Peaking amp code override enable: Setting this bit to a 1'b1 will allow the peaking amp code to be overridden by the peaking amp code override value fields in the REE peaking amp code override 0 register on page 263 and REE peaking.." "0,1"
bitfld.long 0x0C 30. "RX_REE_PEAK_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x0C 29. "RX_REE_PEAK_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the peaking amp voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x0C 28. "RX_REE_PEAK_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the peaking amp" "0,1"
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rbitfld.long 0x0C 24.--27. "RX_REE_PEAK_DIAG_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x0C 22.--23. "RX_REE_PEAK_DIAG_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x0C 16.--21. "RX_REE_PEAK_DIAG_5_0,Current peaking amp integrator accumulator: Current value of the tap integrator accumulator without the unused sign bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x0C 14.--15. "RX_REE_PEAK_COVRD1_15_14,Reserved" "0,1,2,3"
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bitfld.long 0x0C 8.--13. "RX_REE_PEAK_COVRD1_13_8,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x0C 6.--7. "RX_REE_PEAK_COVRD1_7_6,Reserved" "0,1,2,3"
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bitfld.long 0x0C 0.--5. "RX_REE_PEAK_COVRD1_5_0,Peaking amp code override value mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "RX_REE_ATTEN_THR__RX_REE_ATTEN_CTRL_j,REE attenuation control register Offset = 8290h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x10 29.--31. "RX_REE_ATTEN_THR_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--28. "RX_REE_ATTEN_THR_12_8,Attenuation high threshold value: High threshold value to compare against the VGA gain accumulator value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x10 21.--23. "RX_REE_ATTEN_THR_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--20. "RX_REE_ATTEN_THR_4_0,Attenuation low threshold value: Low threshold value to compare against the VGA gain accumulator value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x10 5.--15. 1. "RX_REE_ATTEN_CTRL_15_5,Reserved"
bitfld.long 0x10 0.--4. "RX_REE_ATTEN_CTRL_4_0,Receiver DFE attenuation maximum value: The maximum value the rxda_dfe_attenuation_bin will increase to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "RX_REE_ATTEN_OVRD__RX_REE_ATTEN_CNT_j,REE attenuation counter register Offset = 8294h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x14 25.--31. 1. "RX_REE_ATTEN_OVRD_15_9,Reserved"
bitfld.long 0x14 24. "RX_REE_ATTEN_OVRD_8,Attenuation override enable: Setting this bit to a 1'b1 will allow the rxda_dfe_attenuation_bin signal to be overridden by the attenuation override value signal in this register" "0,1"
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rbitfld.long 0x14 21.--23. "RX_REE_ATTEN_OVRD_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 16.--20. "RX_REE_ATTEN_OVRD_4_0,Attenuation override value: When enabled by the attenuation override enable bit in this register this value will override the current attenuation value on the rxda_dfe_attenuation_bin output pin and also force a corresponding.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x14 0.--15. 1. "RX_REE_ATTEN_CNT_15_0,Attenuation counter max: Value used to specify the maximum number of consecutive words above or below the specified thresholds which will result in triggering an increase or decrease in the rxda_dfe_attenuation_bin signal"
line.long 0x18 "RX_REE_ATTEN_DIAG_j,REE attenuation diagnostics register Offset = 8298h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x18 5.--15. 1. "RX_REE_ATTEN_DIAG_15_5,Reserved"
bitfld.long 0x18 0.--4. "RX_REE_ATTEN_DIAG_4_0,Current attenuation value: Current value of the attenuation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x82A0++0x33
line.long 0x00 "RX_REE_TAP1_OVRD__RX_REE_TAP1_CTRL_j,REE tap 1 control register Offset = 82A0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x00 24.--31. 1. "RX_REE_TAP1_OVRD_15_8,Reserved"
bitfld.long 0x00 23. "RX_REE_TAP1_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions" "0,1"
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rbitfld.long 0x00 22. "RX_REE_TAP1_OVRD_6,Reserved" "0,1"
bitfld.long 0x00 16.--21. "RX_REE_TAP1_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 12.--15. "RX_REE_TAP1_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "RX_REE_TAP1_CTRL_11,Tap coefficient combinational logic zero crossing enable" "0,1"
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bitfld.long 0x00 10. "RX_REE_TAP1_CTRL_10,Tap coefficient combinational logic non zero crossing enable" "0,1"
bitfld.long 0x00 9. "RX_REE_TAP1_CTRL_9,Tap coefficient combinational logic bit 0 only enable" "0,1"
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bitfld.long 0x00 8. "RX_REE_TAP1_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal" "0,1"
rbitfld.long 0x00 7. "RX_REE_TAP1_CTRL_7,Reserved" "0,1"
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bitfld.long 0x00 4.--6. "RX_REE_TAP1_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "RX_REE_TAP1_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "RX_REE_TAP1_DIAG_j,REE tap 1 diagnostics register Offset = 82A4h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 15. "RX_REE_TAP1_DIAG_15,Reserved" "0,1"
bitfld.long 0x04 14. "RX_REE_TAP1_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x04 13. "RX_REE_TAP1_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x04 12. "RX_REE_TAP1_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap" "0,1"
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rbitfld.long 0x04 6.--11. "RX_REE_TAP1_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x04 0.--5. "RX_REE_TAP1_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "RX_REE_TAP2_OVRD__RX_REE_TAP2_CTRL_j,REE tap 2 control register Offset = 82A8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x08 24.--31. 1. "RX_REE_TAP2_OVRD_15_8,Reserved"
bitfld.long 0x08 23. "RX_REE_TAP2_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions" "0,1"
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rbitfld.long 0x08 22. "RX_REE_TAP2_OVRD_6,Reserved" "0,1"
bitfld.long 0x08 16.--21. "RX_REE_TAP2_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x08 12.--15. "RX_REE_TAP2_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 11. "RX_REE_TAP2_CTRL_11,Tap coefficient combinational logic zero crossing enable" "0,1"
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bitfld.long 0x08 10. "RX_REE_TAP2_CTRL_10,Tap coefficient combinational logic non zero crossing enable" "0,1"
bitfld.long 0x08 9. "RX_REE_TAP2_CTRL_9,Tap coefficient combinational logic bit 0 only enable" "0,1"
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bitfld.long 0x08 8. "RX_REE_TAP2_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal" "0,1"
rbitfld.long 0x08 7. "RX_REE_TAP2_CTRL_7,Reserved" "0,1"
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bitfld.long 0x08 4.--6. "RX_REE_TAP2_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--3. "RX_REE_TAP2_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "RX_REE_TAP2_DIAG_j,REE tap 2 diagnostics register Offset = 82ACh + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x0C 15. "RX_REE_TAP2_DIAG_15,Reserved" "0,1"
bitfld.long 0x0C 14. "RX_REE_TAP2_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x0C 13. "RX_REE_TAP2_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x0C 12. "RX_REE_TAP2_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap" "0,1"
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rbitfld.long 0x0C 6.--11. "RX_REE_TAP2_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x0C 0.--5. "RX_REE_TAP2_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "RX_REE_TAP3_OVRD__RX_REE_TAP3_CTRL_j,REE tap 3 control register Offset = 82B0h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x10 24.--31. 1. "RX_REE_TAP3_OVRD_15_8,Reserved"
bitfld.long 0x10 23. "RX_REE_TAP3_OVRD_7,Tap override enable: Setting this bit to a 1'b1 will enable the tap override field in this register to override the tap integrator accumulator functions" "0,1"
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rbitfld.long 0x10 22. "RX_REE_TAP3_OVRD_6,Reserved" "0,1"
bitfld.long 0x10 16.--21. "RX_REE_TAP3_OVRD_5_0,Tap override value: When the tap override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x10 12.--15. "RX_REE_TAP3_CTRL_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 11. "RX_REE_TAP3_CTRL_11,Tap coefficient combinational logic zero crossing enable" "0,1"
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bitfld.long 0x10 10. "RX_REE_TAP3_CTRL_10,Tap coefficient combinational logic non zero crossing enable" "0,1"
bitfld.long 0x10 9. "RX_REE_TAP3_CTRL_9,Tap coefficient combinational logic bit 0 only enable" "0,1"
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bitfld.long 0x10 8. "RX_REE_TAP3_CTRL_8,Receiver DFE tap coefficient disable: This bit disables the rxda_dfe_tap_coef output signal" "0,1"
rbitfld.long 0x10 7. "RX_REE_TAP3_CTRL_7,Reserved" "0,1"
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bitfld.long 0x10 4.--6. "RX_REE_TAP3_CTRL_6_4,Tap integrator accumulator scaler value: Specifies the amount to scale the input to the tap integrator accumulator by" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--3. "RX_REE_TAP3_CTRL_3_0,Tap sigma delta accumulator scaler value: Specifies the amount to scale the input to the tap sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RX_REE_TAP3_DIAG_j,REE tap 3 diagnostics register Offset = 82B4h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x14 15. "RX_REE_TAP3_DIAG_15,Reserved" "0,1"
bitfld.long 0x14 14. "RX_REE_TAP3_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x14 13. "RX_REE_TAP3_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the tap voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x14 12. "RX_REE_TAP3_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the tap" "0,1"
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rbitfld.long 0x14 6.--11. "RX_REE_TAP3_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x14 0.--5. "RX_REE_TAP3_DIAG_5_0,Current tap integrator accumulator: Current value of the tap integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "RX_REE_LFEQ_OVRD__RX_REE_LFEQ_CTRL_j,REE low frequency equalizer control register Offset = 82B8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x18 24.--31. 1. "RX_REE_LFEQ_OVRD_15_8,Reserved"
bitfld.long 0x18 23. "RX_REE_LFEQ_OVRD_7,Override enable: Setting this bit to a 1'b1 will enable the override field in this register to override the integrator accumulator functions" "0,1"
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rbitfld.long 0x18 22. "RX_REE_LFEQ_OVRD_6,Reserved" "0,1"
bitfld.long 0x18 16.--21. "RX_REE_LFEQ_OVRD_5_0,Override value: When the override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x18 9.--15. 1. "RX_REE_LFEQ_CTRL_15_9,Reserved"
bitfld.long 0x18 8. "RX_REE_LFEQ_CTRL_8,Receiver DFE coefficient disable: This bit disables the rxda_dfe_coef output signal" "0,1"
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rbitfld.long 0x18 7. "RX_REE_LFEQ_CTRL_7,Reserved" "0,1"
bitfld.long 0x18 4.--6. "RX_REE_LFEQ_CTRL_6_4,Integrator accumulator scaler value: Specifies the amount to scale the input to the integrator accumulator by" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 0.--3. "RX_REE_LFEQ_CTRL_3_0,Sigma delta accumulator scaler value: Specifies the amount to scale the input to the sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "RX_REE_LFEQ_DIAG_j,REE low frequency equalizer diagnostics register Offset = 82BCh + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x1C 15. "RX_REE_LFEQ_DIAG_15,Reserved" "0,1"
bitfld.long 0x1C 14. "RX_REE_LFEQ_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x1C 13. "RX_REE_LFEQ_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the voter function to activate the voter pos signal for a single cycle" "0,1"
bitfld.long 0x1C 12. "RX_REE_LFEQ_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter" "0,1"
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rbitfld.long 0x1C 6.--11. "RX_REE_LFEQ_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x1C 0.--5. "RX_REE_LFEQ_DIAG_5_0,Current integrator accumulator: Current value of the integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "RX_REE_VGA_GAIN_OVRD__RX_REE_VGA_GAIN_CTRL_j,REE VGA gain control register Offset = 82C0h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x20 31. "RX_REE_VGA_GAIN_OVRD_15,VGA gain target adjust override enable: Setting this bit to a 1'b1 will enable the VGA gain target adjust override field in this register to override the VGA gain target adjust accumulator functions" "0,1"
rbitfld.long 0x20 29.--30. "RX_REE_VGA_GAIN_OVRD_14_13,Reserved" "0,1,2,3"
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bitfld.long 0x20 24.--28. "RX_REE_VGA_GAIN_OVRD_12_8,VGA gain target adjust override value: When the VGA gain target adjust override enable bit in this register is active the value in this field will override the accumulator value used to drive the vga_gain_tgt_adj signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 23. "RX_REE_VGA_GAIN_OVRD_7,VGA gain override enable: Setting this bit to a 1'b1 will enable the VGA gain override field in this register to override the VGA gain integrator accumulator functions" "0,1"
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rbitfld.long 0x20 21.--22. "RX_REE_VGA_GAIN_OVRD_6_5,Reserved" "0,1,2,3"
bitfld.long 0x20 16.--20. "RX_REE_VGA_GAIN_OVRD_4_0,VGA gain override value: When the VGA gain override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer encoder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x20 13.--15. "RX_REE_VGA_GAIN_CTRL_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 8.--12. "RX_REE_VGA_GAIN_CTRL_12_8,VGA gain max: Specifies the maximum value of the VGA gain integrator accumulator and therefore also the maximum number of bits in the rxda_dfe_vga_gain thermometer code that will be set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x20 7. "RX_REE_VGA_GAIN_CTRL_7,Reserved" "0,1"
bitfld.long 0x20 4.--6. "RX_REE_VGA_GAIN_CTRL_6_4,VGA gain integrator accumulator scaler value: Specifies the amount to scale the input to the VGA gain integrator accumulator by" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 0.--3. "RX_REE_VGA_GAIN_CTRL_3_0,VGA gain sigma delta accumulator scaler value: Specifies the amount to scale the input to the VGA gain sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "RX_REE_VGA_GAIN_TGT_DIAG__RX_REE_VGA_GAIN_DIAG_j,REE VGA gain diagnostics register Offset = 82C4h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x24 21.--31. 1. "RX_REE_VGA_GAIN_TGT_DIAG_15_5,Reserved"
rbitfld.long 0x24 16.--20. "RX_REE_VGA_GAIN_TGT_DIAG_4_0,Current VGA gain integrator accumulator: Current value of the VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x24 15. "RX_REE_VGA_GAIN_DIAG_15,Reserved" "0,1"
bitfld.long 0x24 14. "RX_REE_VGA_GAIN_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the VGA gain voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x24 13. "RX_REE_VGA_GAIN_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the VGA gain voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x24 12. "RX_REE_VGA_GAIN_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the VGA gain" "0,1"
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rbitfld.long 0x24 6.--11. "RX_REE_VGA_GAIN_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x24 0.--5. "RX_REE_VGA_GAIN_DIAG_5_0,Current VGA gain integrator accumulator: Current value of the VGA gain integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "RX_REE_OFF_COR_OVRD__RX_REE_OFF_COR_CTRL_j,REE offset correction control register Offset = 82C8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x28 24.--31. 1. "RX_REE_OFF_COR_OVRD_15_8,Reserved"
bitfld.long 0x28 23. "RX_REE_OFF_COR_OVRD_7,Offset correction override enable: Setting this bit to a 1'b1 will enable the offset correction override field in this register to override the offset correction integrator accumulator functions" "0,1"
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rbitfld.long 0x28 22. "RX_REE_OFF_COR_OVRD_6,Reserved" "0,1"
bitfld.long 0x28 16.--21. "RX_REE_OFF_COR_OVRD_5_0,Offset correction override value: When the offset correction override enable bit in this register is active the value in this field will override the integrator accumulator value as well as the input to the binary to thermometer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x28 7.--15. 1. "RX_REE_OFF_COR_CTRL_15_7,Reserved"
bitfld.long 0x28 4.--6. "RX_REE_OFF_COR_CTRL_6_4,Offset correction integrator accumulator scaler value: Specifies the amount to scale the input to the offset correction integrator accumulator by" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 0.--3. "RX_REE_OFF_COR_CTRL_3_0,Offset correction sigma delta accumulator scaler value: Specifies the amount to scale the input to the offset correction sigma delta accumulator by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "RX_REE_OFF_COR_DIAG_j,REE offset correction diagnostics register Offset = 82CCh + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x2C 15. "RX_REE_OFF_COR_DIAG_15,Reserved" "0,1"
bitfld.long 0x2C 14. "RX_REE_OFF_COR_DIAG_14,Voter override neg : Writing a 1'b1 in this register bit will force the offset correction voter function to activate the voter neg signal for a single clock cycle" "0,1"
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bitfld.long 0x2C 13. "RX_REE_OFF_COR_DIAG_13,Voter override pos : Writing a 1'b1 in this register bit will force the offset correction voter function to activate the voter pos signal for a single clock cycle" "0,1"
bitfld.long 0x2C 12. "RX_REE_OFF_COR_DIAG_12,Voter override enable : Setting this bit to a 1'b1 will allow only the voter override pos and voter override neg bits in this register to control the voter in the offset correction" "0,1"
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rbitfld.long 0x2C 6.--11. "RX_REE_OFF_COR_DIAG_11_6,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x2C 0.--5. "RX_REE_OFF_COR_DIAG_5_0,Current offset correction integrator accumulator: Current value of the offset correction integrator accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "RX_REE_SC_COR_TCNT__RX_REE_SC_COR_WCNT_j,REE short channel correction valid word counter register Offset = 82D0h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x30 22.--31. 1. "RX_REE_SC_COR_TCNT_15_6,Reserved"
bitfld.long 0x30 16.--21. "RX_REE_SC_COR_TCNT_5_0,Threshold counter start value : Value used for the starting value when counting the number of bits that are below the error threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x30 6.--15. 1. "RX_REE_SC_COR_WCNT_15_6,Reserved"
bitfld.long 0x30 0.--5. "RX_REE_SC_COR_WCNT_5_0,Valid word counter start value : Value used for the starting value when counting the number of valid words" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x82E0++0x17
line.long 0x00 "RX_REE_TAP1_CLIP__RX_REE_ADDR_CFG_j,REE adder configuration register Offset = 82E0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 27.--31. "RX_REE_TAP1_CLIP_15_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "RX_REE_TAP1_CLIP_10_8,VGA target gain adjust multiplier: Controls how much to multiply the VGA target gain adjust by when calculating the tap threshold" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 21.--23. "RX_REE_TAP1_CLIP_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "RX_REE_TAP1_CLIP_4_0,Threshold adjust: Controls how much the threshold can be adjusted by after multiplying the VGA target gain adjust multiplier with the VGA target gain adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 11.--15. "RX_REE_ADDR_CFG_15_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "RX_REE_ADDR_CFG_10,TX post cursor tap 3 adder enable: Setting this bit to 1'b1 enables the results of tap 3 to be added to the TX post cursor controller input" "0,1"
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bitfld.long 0x00 9. "RX_REE_ADDR_CFG_9,TX post cursor tap 2 adder enable: Setting this bit to 1'b1 enables the results of tap 2 to be added to the TX post cursor controller input" "0,1"
bitfld.long 0x00 8. "RX_REE_ADDR_CFG_8,TX post cursor tap 1 adder enable: Setting this bit to 1'b1 enables the results of tap 1 to be added to the TX post cursor controller input" "0,1"
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rbitfld.long 0x00 3.--7. "RX_REE_ADDR_CFG_7_3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "RX_REE_ADDR_CFG_2,RX peaking tap 3 adder enable: Setting this bit to 1'b1 enables the results of tap 3 to be added to the RX peaking amp gain input" "0,1"
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bitfld.long 0x00 1. "RX_REE_ADDR_CFG_1,RX peaking tap 2 adder enable: Setting this bit to 1'b1 enables the results of tap 2 to be added to the RX peaking amp gain input" "0,1"
bitfld.long 0x00 0. "RX_REE_ADDR_CFG_0,RX peaking tap 1 adder enable: Setting this bit to 1'b1 enables the results of tap 1 to be added to the RX peaking amp gain input" "0,1"
line.long 0x04 "RX_REE_CTRL_DATA_MASK__RX_REE_TAP2TON_CLIP_j,REE taps 2 and 3 clip control register Offset = 82E4h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 31. "RX_REE_CTRL_DATA_MASK_15,Reserved" "0,1"
rbitfld.long 0x04 30. "RX_REE_CTRL_DATA_MASK_14,Ignore 1010 controller - Note that this is read only" "0,1"
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bitfld.long 0x04 29. "RX_REE_CTRL_DATA_MASK_13,TX equalization evaluator: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data.." "0,1"
bitfld.long 0x04 28. "RX_REE_CTRL_DATA_MASK_12,TX post cursor control: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals.." "0,1"
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bitfld.long 0x04 27. "RX_REE_CTRL_DATA_MASK_11,TX pre cursor control: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals.." "0,1"
bitfld.long 0x04 26. "RX_REE_CTRL_DATA_MASK_10,Short channel correction: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data.." "0,1"
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bitfld.long 0x04 25. "RX_REE_CTRL_DATA_MASK_9,RX attenuation: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the REE" "0,1"
bitfld.long 0x04 24. "RX_REE_CTRL_DATA_MASK_8,RX VGA gain: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by the REE" "0,1"
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bitfld.long 0x04 23. "RX_REE_CTRL_DATA_MASK_7,RX offset correction coefficient: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the.." "0,1"
bitfld.long 0x04 22. "RX_REE_CTRL_DATA_MASK_6,RX peaking amp gain: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected on the data signals by.." "0,1"
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bitfld.long 0x04 21. "RX_REE_CTRL_DATA_MASK_5,RX low frequency equalizer adaptive control: When set to 1'b0 this REE component will be turned off when control data is being received when either the rx_eq_training_data_valid signal going inactive or a 1010 pattern is detected.." "0,1"
rbitfld.long 0x04 20. "RX_REE_CTRL_DATA_MASK_4,Reserved" "0,1"
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rbitfld.long 0x04 19. "RX_REE_CTRL_DATA_MASK_3,Reserved" "0,1"
bitfld.long 0x04 18. "RX_REE_CTRL_DATA_MASK_2,RX tap" "0,1"
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bitfld.long 0x04 17. "RX_REE_CTRL_DATA_MASK_1,RX tap" "0,1"
bitfld.long 0x04 16. "RX_REE_CTRL_DATA_MASK_0,RX tap" "0,1"
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rbitfld.long 0x04 11.--15. "RX_REE_TAP2TON_CLIP_15_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--10. "RX_REE_TAP2TON_CLIP_10_8,VGA target gain adjust multiplier: Controls how much to multiply the VGA target gain adjust by when calculating the tap threshold" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 5.--7. "RX_REE_TAP2TON_CLIP_7_5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--4. "RX_REE_TAP2TON_CLIP_4_0,Threshold adjust: Controls how much the threshold can be adjusted by after multiplying the VGA target gain adjust multiplier with the VGA target gain adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "RX_REE_DIAG_CTRL__RX_REE_FIFO_DIAG_j,REE coefficient FIFO diagnostic register Offset = 82E8h + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x08 24.--31. 1. "RX_REE_DIAG_CTRL_15_8,Reserved"
bitfld.long 0x08 23. "RX_REE_DIAG_CTRL_7,Analog tap disable: When this bit is set to 1'b1 the rxda_dfe_tap_1_coef rxda_dfe_tap_2_coef and rxda_dfe_tap_3_coef signals being driven to the analog will be forced to all 0s" "0,1"
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bitfld.long 0x08 22. "RX_REE_DIAG_CTRL_6,Hold periodic equalization while RX idle: When this bit is set to 1'b1 a detection of electrical idle on the receiver (rx_signal_detect is set to 1'b0) will disable the periodic REE general control state machine and as a result freeze.." "0,1"
bitfld.long 0x08 21. "RX_REE_DIAG_CTRL_5,Hold general control state machine 2 equalization while RX idle: When this bit is set to 1'b1 a detection of electrical idle on the receiver (rx_signal_detect is set to 1'b0) will disable the REE general control state machine 2 and as.." "0,1"
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bitfld.long 0x08 20. "RX_REE_DIAG_CTRL_4,Hold general control state machine 1 equalization while RX idle: When this bit is set to 1'b1 a detection of electrical idle on the receiver (rx_signal_detect is set to 1'b0) will disable the REE general control state machine 1 and as.." "0,1"
rbitfld.long 0x08 18.--19. "RX_REE_DIAG_CTRL_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x08 17. "RX_REE_DIAG_CTRL_1,Enable REE control clock on : Enables the REE control clock" "0,1"
bitfld.long 0x08 16. "RX_REE_DIAG_CTRL_0,Force REE function clock on : When active the REE function clock gate will allow the clock to run" "0,1"
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rbitfld.long 0x08 15. "RX_REE_FIFO_DIAG_15,FIFO underflow : Indicates when a FIFO underflow condition has occurred" "0,1"
rbitfld.long 0x08 14. "RX_REE_FIFO_DIAG_14,FIFO empty :Indicates that the FIFO is empty" "0,1"
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bitfld.long 0x08 13. "RX_REE_FIFO_DIAG_13,FIFO output dequeue : Writing a 1'b1 to this bit will dequeue the current values from the output of the FIFO" "0,1"
bitfld.long 0x08 12. "RX_REE_FIFO_DIAG_12,FIFO output override enable : Enables the FIFO output override functions" "0,1"
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rbitfld.long 0x08 11. "RX_REE_FIFO_DIAG_11,FIFO output data pre cursor increment : Current value on the pre cursor increment bit on the FIFO output" "0,1"
rbitfld.long 0x08 10. "RX_REE_FIFO_DIAG_10,FIFO output data pre cursor decrement : Current value on the pre cursor decrement bit on the FIFO output" "0,1"
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rbitfld.long 0x08 9. "RX_REE_FIFO_DIAG_9,FIFO output data post cursor increment : Current value on the post cursor increment bit on the FIFO output" "0,1"
rbitfld.long 0x08 8. "RX_REE_FIFO_DIAG_8,FIFO output data post cursor decrement : Current value on the post cursor decrement bit on the FIFO output" "0,1"
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rbitfld.long 0x08 7. "RX_REE_FIFO_DIAG_7,FIFO overflow :Indicates when a FIFO overflow condition has occurred" "0,1"
rbitfld.long 0x08 6. "RX_REE_FIFO_DIAG_6,FIFO full :Indicates that the FIFO is full" "0,1"
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bitfld.long 0x08 5. "RX_REE_FIFO_DIAG_5,FIFO input enqueue : Writing a 1'b1 to this bit will enqueue the values of the FIFO input data bits in this register to their respective FIFO bits" "0,1"
bitfld.long 0x08 4. "RX_REE_FIFO_DIAG_4,FIFO input override enable : Enables the FIFO input override functions" "0,1"
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bitfld.long 0x08 3. "RX_REE_FIFO_DIAG_3,FIFO input data pre cursor increment : Pre cursor increment value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register" "0,1"
bitfld.long 0x08 2. "RX_REE_FIFO_DIAG_2,FIFO input data pre cursor decrement : Pre cursor decrement value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register" "0,1"
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bitfld.long 0x08 1. "RX_REE_FIFO_DIAG_1,FIFO input data post cursor increment : Post cursor increment value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register" "0,1"
bitfld.long 0x08 0. "RX_REE_FIFO_DIAG_0,FIFO input data post cursor decrement : Post cursor decrement value that will be enqueued to the FIFO by the FIFO input enqueue bit in this register" "0,1"
line.long 0x0C "RX_REE_SMGM_CTRL1__RX_REE_TXEQEVAL_CTRL_j,REE TX equalization evaluator control register Offset = 82ECh + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x0C 28.--31. "RX_REE_SMGM_CTRL1_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 27. "RX_REE_SMGM_CTRL1_11,REE Periodic general control state machine enable standard mode" "0,1"
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bitfld.long 0x0C 26. "RX_REE_SMGM_CTRL1_10,REE Periodic general control state machine enable standard mode" "0,1"
bitfld.long 0x0C 25. "RX_REE_SMGM_CTRL1_9,REE Periodic general control state machine enable standard mode" "0,1"
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bitfld.long 0x0C 24. "RX_REE_SMGM_CTRL1_8,REE Periodic general control state machine enable standard mode" "0,1"
bitfld.long 0x0C 23. "RX_REE_SMGM_CTRL1_7,REE general control state machine 2 enable standard mode" "0,1"
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bitfld.long 0x0C 22. "RX_REE_SMGM_CTRL1_6,REE general control state machine 2 enable standard mode" "0,1"
bitfld.long 0x0C 21. "RX_REE_SMGM_CTRL1_5,REE general control state machine 2 enable standard mode" "0,1"
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bitfld.long 0x0C 20. "RX_REE_SMGM_CTRL1_4,REE general control state machine 2 enable standard mode" "0,1"
bitfld.long 0x0C 19. "RX_REE_SMGM_CTRL1_3,REE general control state machine 1 enable standard mode" "0,1"
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bitfld.long 0x0C 18. "RX_REE_SMGM_CTRL1_2,REE general control state machine 1 enable standard mode" "0,1"
bitfld.long 0x0C 17. "RX_REE_SMGM_CTRL1_1,REE general control state machine 1 enable standard mode" "0,1"
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bitfld.long 0x0C 16. "RX_REE_SMGM_CTRL1_0,REE general control state machine 1 enable standard mode" "0,1"
hexmask.long.word 0x0C 2.--15. 1. "RX_REE_TXEQEVAL_CTRL_15_2,Reserved"
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bitfld.long 0x0C 1. "RX_REE_TXEQEVAL_CTRL_1,TX equalization evaluation counter reset on gen mode" "0,1"
bitfld.long 0x0C 0. "RX_REE_TXEQEVAL_CTRL_0,TX main coefficient direction change control: This bit controls the function of the main coefficient direction change" "0,1"
line.long 0x10 "RX_REE_TXEQEVAL_PRE__RX_REE_SMGM_CTRL2_j,REE control state machine gen mode control register 2 Offset = 82F0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x10 30.--31. "RX_REE_TXEQEVAL_PRE_15_14,Reserved" "0,1,2,3"
rbitfld.long 0x10 24.--29. "RX_REE_TXEQEVAL_PRE_13_8,TX equalization evaluator pre-emphasis increment count: Contains a count of the total number of pre-emphasis increment responses that have taken place during the TX equalization evaluator process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x10 22.--23. "RX_REE_TXEQEVAL_PRE_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x10 16.--21. "RX_REE_TXEQEVAL_PRE_5_0,TX equalization evaluator pre-emphasis decrement count: Contains a count of the total number of pre-emphasis decrement responses that have taken place during the TX equalization evaluator process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 15. "RX_REE_SMGM_CTRL2_15,REE PCIe Gen 3 TX equalization state machine E path en standard mode" "0,1"
bitfld.long 0x10 14. "RX_REE_SMGM_CTRL2_14,REE PCIe Gen 3 TX equalization state machine E path en standard mode" "0,1"
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bitfld.long 0x10 13. "RX_REE_SMGM_CTRL2_13,REE PCIe Gen 3 TX equalization state machine E path en standard mode" "0,1"
bitfld.long 0x10 12. "RX_REE_SMGM_CTRL2_12,REE PCIe Gen 3 TX equalization state machine E path en standard mode" "0,1"
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bitfld.long 0x10 11. "RX_REE_SMGM_CTRL2_11,REE Periodic general control state machine E path en standard mode" "0,1"
bitfld.long 0x10 10. "RX_REE_SMGM_CTRL2_10,REE Periodic general control state machine E path en standard mode" "0,1"
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bitfld.long 0x10 9. "RX_REE_SMGM_CTRL2_9,REE Periodic general control state machine E path en standard mode" "0,1"
bitfld.long 0x10 8. "RX_REE_SMGM_CTRL2_8,REE Periodic general control state machine E path en standard mode" "0,1"
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bitfld.long 0x10 7. "RX_REE_SMGM_CTRL2_7,REE general control state machine 2 E path en standard mode" "0,1"
bitfld.long 0x10 6. "RX_REE_SMGM_CTRL2_6,REE general control state machine 2 E path en standard mode" "0,1"
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bitfld.long 0x10 5. "RX_REE_SMGM_CTRL2_5,REE general control state machine 2 E path en standard mode" "0,1"
bitfld.long 0x10 4. "RX_REE_SMGM_CTRL2_4,REE general control state machine 2 E path en standard mode" "0,1"
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bitfld.long 0x10 3. "RX_REE_SMGM_CTRL2_3,REE general control state machine 1 E path en standard mode" "0,1"
bitfld.long 0x10 2. "RX_REE_SMGM_CTRL2_2,REE general control state machine 1 E path en standard mode" "0,1"
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bitfld.long 0x10 1. "RX_REE_SMGM_CTRL2_1,REE general control state machine 1 E path en standard mode" "0,1"
bitfld.long 0x10 0. "RX_REE_SMGM_CTRL2_0,REE general control state machine 1 E path en standard mode" "0,1"
line.long 0x14 "RX_REE_TXEQEVAL_POST_j,REE TX equalization evaluator post-emphasis register Offset = 82F4h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x14 14.--15. "RX_REE_TXEQEVAL_POST_15_14,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "RX_REE_TXEQEVAL_POST_13_8,TX equalization evaluator post-emphasis increment count: Contains a count of the total number of post-emphasis increment responses that have taken place during the TX equalization evaluator process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 6.--7. "RX_REE_TXEQEVAL_POST_7_6,Reserved" "0,1,2,3"
bitfld.long 0x14 0.--5. "RX_REE_TXEQEVAL_POST_5_0,TX equalization evaluator post-emphasis decrement count: Contains a count of the total number of post-emphasis decrement responses that have taken place during the TX equalization evaluator process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8380++0x07
line.long 0x00 "XCVR_CMSMT_TEST_CLK_SEL__XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_j,Clock frequency measurement control register Offset = 8380h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 19.--31. 1. "XCVR_CMSMT_TEST_CLK_SEL_15_3,Reserved"
bitfld.long 0x00 16.--18. "XCVR_CMSMT_TEST_CLK_SEL_2_0,Test clock select: This field drives the test_clk_select pin in order to control an external MUX for selecting between multiple test clocks to measure" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_15,Run test clock measurement: Activating (1'b1) this bit will run the test clock measurement process" "0,1"
rbitfld.long 0x00 14. "XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_14,Test clock measurement done: This bit will be set to 1'b1 when the test clock measurement process is complete" "0,1"
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hexmask.long.word 0x00 0.--13. 1. "XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_13_0,Reserved"
line.long 0x04 "XCVR_CMSMT_TEST_CLK_CNT_VALUE__XCVR_CMSMT_REF_CLK_TMR_VALUE_j,Reference clock timer value register Offset = 8384h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x04 28.--31. "XCVR_CMSMT_TEST_CLK_CNT_VALUE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 16.--27. 1. "XCVR_CMSMT_TEST_CLK_CNT_VALUE_11_0,Test clock counter value: When the test clock measurement process is complete the value in this field specifies the number of test clock cycles that were counted in the time specified by the reference clock timer value"
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rbitfld.long 0x04 12.--15. "XCVR_CMSMT_REF_CLK_TMR_VALUE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--11. 1. "XCVR_CMSMT_REF_CLK_TMR_VALUE_11_0,Reference clock timer value : This specifies the amount of time in reference clock cycles to count test clock cycles"
group.long 0x83C0++0x33
line.long 0x00 "RX_DIAG_DFE_AMP_TUNE__RX_DIAG_DFE_CTRL_j,Receiver DFE control register Offset = 83C0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x00 31. "RX_DIAG_DFE_AMP_TUNE_15,Reserved" "0,1"
bitfld.long 0x00 28.--30. "RX_DIAG_DFE_AMP_TUNE_14_12,DFE constant gm bias tune: Adjusts the constant gm bias" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 27. "RX_DIAG_DFE_AMP_TUNE_11,DFE VGA constant gm bias enable: Enables the VGA constant gm bias" "0,1"
bitfld.long 0x00 24.--26. "RX_DIAG_DFE_AMP_TUNE_10_8,DFE VGA amp current adjust: Adjusts the current for the DFE VGA amp using the rxda_vga_current_adj signal as specified below" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 23. "RX_DIAG_DFE_AMP_TUNE_7,DFE peaking constant gm bias enable: Enables the peaking constant gm bias" "0,1"
bitfld.long 0x00 20.--22. "RX_DIAG_DFE_AMP_TUNE_6_4,DFE peaking amp current adjust: Adjusts the current for the DFE peaking amp using the rxda_peak_current_adj signal as specified below" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RX_DIAG_DFE_AMP_TUNE_3,DFE summing constant gm bias enable: Enables the summing constant gm bias" "0,1"
bitfld.long 0x00 16.--18. "RX_DIAG_DFE_AMP_TUNE_2_0,DFE summing amp current adjust: Adjusts the current for the DFE summing amp using the rxda_sum_current_adj signal as specified below" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 4.--15. 1. "RX_DIAG_DFE_CTRL_15_4,Reserved"
bitfld.long 0x00 3. "RX_DIAG_DFE_CTRL_3,Receiver DFE low frequency equalization enable value standard mode" "0,1"
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bitfld.long 0x00 2. "RX_DIAG_DFE_CTRL_2,Receiver DFE low frequency equalization enable value standard mode" "0,1"
bitfld.long 0x00 1. "RX_DIAG_DFE_CTRL_1,Receiver DFE low frequency equalization enable value standard mode" "0,1"
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bitfld.long 0x00 0. "RX_DIAG_DFE_CTRL_0,Receiver DFE low frequency equalization enable value standard mode" "0,1"
line.long 0x04 "RX_DIAG_DFE_AMP_TUNE_3__RX_DIAG_DFE_AMP_TUNE_2_j,DFE amp fine tuning 2 register Offset = 83C4h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x04 20.--31. 1. "RX_DIAG_DFE_AMP_TUNE_3_15_4,Reserved"
bitfld.long 0x04 19. "RX_DIAG_DFE_AMP_TUNE_3_3,DFE VGA stage 1 boost standard mode" "0,1"
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bitfld.long 0x04 18. "RX_DIAG_DFE_AMP_TUNE_3_2,DFE VGA stage 1 boost standard mode" "0,1"
bitfld.long 0x04 17. "RX_DIAG_DFE_AMP_TUNE_3_1,DFE VGA stage 1 boost standard mode" "0,1"
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bitfld.long 0x04 16. "RX_DIAG_DFE_AMP_TUNE_3_0,DFE VGA stage 1 boost standard mode" "0,1"
rbitfld.long 0x04 14.--15. "RX_DIAG_DFE_AMP_TUNE_2_15_14,Reserved" "0,1,2,3"
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bitfld.long 0x04 12.--13. "RX_DIAG_DFE_AMP_TUNE_2_13_12,Receiver peaking amp common mode adjust: Adjusts the common mode voltage for the receiver peaking amp by driving the rxda_fe_pkamp_cm_adj signal to the analog" "0,1,2,3"
bitfld.long 0x04 11. "RX_DIAG_DFE_AMP_TUNE_2_11,DFE low frequency equalizer constant gm bias enable: Enables the low frequency equalizer constant gm bias" "0,1"
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bitfld.long 0x04 8.--10. "RX_DIAG_DFE_AMP_TUNE_2_10_8,DFE low frequency equalizer current adjust: Adjusts the current for the DFE low frequency equalizer using the rxda_lfeq_current_adj signal as specified below" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RX_DIAG_DFE_AMP_TUNE_2_7,DFE peaking amp boost: Enables the active inductors boost function in the peaking amp for high data rates" "0,1"
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bitfld.long 0x04 6. "RX_DIAG_DFE_AMP_TUNE_2_6,Reserved - Spare" "0,1"
bitfld.long 0x04 5. "RX_DIAG_DFE_AMP_TUNE_2_5,DFE VGA stage 2 boost: Enables the active inductors boost function in stage 2 of the VGA for high data rates" "0,1"
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bitfld.long 0x04 4. "RX_DIAG_DFE_AMP_TUNE_2_4,DFE RX Tap 1 DAC Range Select: Controls the tap 1 DAC range in the analog DFE" "0,1"
rbitfld.long 0x04 2.--3. "RX_DIAG_DFE_AMP_TUNE_2_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x04 0.--1. "RX_DIAG_DFE_AMP_TUNE_2_1_0,DFE RX amp current adjust: Adjusts the mix of constant-gm and External Current for RX front end amplifiers" "0,1,2,3"
line.long 0x08 "RX_DIAG_NQST_CTRL__RX_DIAG_REE_DAC_CTRL_j,REE DAC control register Offset = 83C8h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x08 28.--31. "RX_DIAG_NQST_CTRL_15_12,RX nyquist select value standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "RX_DIAG_NQST_CTRL_11_8,RX nyquist select value standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "RX_DIAG_NQST_CTRL_7_4,RX nyquist select value standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "RX_DIAG_NQST_CTRL_3_0,RX nyquist select value standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x08 3.--15. 1. "RX_DIAG_REE_DAC_CTRL_15_3,Reserved"
bitfld.long 0x08 2. "RX_DIAG_REE_DAC_CTRL_2,DFE Offset DAC enable: Enables the DFE offset DAC associated with the VGA amp" "0,1"
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bitfld.long 0x08 1. "RX_DIAG_REE_DAC_CTRL_1,DFE Offset DAC attenuation: Adds attenuation to the DFE offset DAC associated with the VGA amp" "0,1"
bitfld.long 0x08 0. "RX_DIAG_REE_DAC_CTRL_0,DFE DAC attenuation: Adds attenuation to the DFE DACs associated with the summing amp" "0,1"
line.long 0x0C "RX_DIAG_LFEQ_TUNE_j,Low frequency equalizer tuning register Offset = 83CCh + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x0C 8.--15. 1. "RX_DIAG_LFEQ_TUNE_15_8,Reserved"
bitfld.long 0x0C 6.--7. "RX_DIAG_LFEQ_TUNE_7_6,RX low frequency equalization zero frequency value standard mode" "0,1,2,3"
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bitfld.long 0x0C 4.--5. "RX_DIAG_LFEQ_TUNE_5_4,RX low frequency equalization zero frequency value standard mode" "0,1,2,3"
bitfld.long 0x0C 2.--3. "RX_DIAG_LFEQ_TUNE_3_2,RX low frequency equalization zero frequency value standard mode" "0,1,2,3"
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bitfld.long 0x0C 0.--1. "RX_DIAG_LFEQ_TUNE_1_0,RX low frequency equalization zero frequency value standard mode" "0,1,2,3"
line.long 0x10 "RX_DIAG_SH_SIGDET__RX_DIAG_SIGDET_TUNE_j,RX signal detect tuning and control register Offset = 83D0h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x10 29.--31. "RX_DIAG_SH_SIGDET_15_13,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x10 28. "RX_DIAG_SH_SIGDET_12,Signal detect 1 up: Signal detect 1 calibration up signal value as it is currently captured in the sample and hold latches" "0,1"
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rbitfld.long 0x10 24.--27. "RX_DIAG_SH_SIGDET_11_8,Signal detect 1 code: Signal detect 1 calibration code signal value as it is currently captured in the sample and hold latches" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x10 21.--23. "RX_DIAG_SH_SIGDET_7_5,Reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x10 20. "RX_DIAG_SH_SIGDET_4,Signal detect 0 up: Signal detect 0 calibration up signal value as it is currently captured in the sample and hold latches" "0,1"
rbitfld.long 0x10 16.--19. "RX_DIAG_SH_SIGDET_3_0,Signal detect 0 code: Signal detect 0 calibration code signal value as it is currently captured in the sample and hold latches" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 15. "RX_DIAG_SIGDET_TUNE_15,Reserved" "0,1"
bitfld.long 0x10 14. "RX_DIAG_SIGDET_TUNE_14,Signal detect calibration half gain select: Controls the resolution of each step in the signal detect calibration code by adjusting the gain of signal detect offset correction by driving the rxda_sd_cal_halfgain signal going to.." "0,1"
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bitfld.long 0x10 12.--13. "RX_DIAG_SIGDET_TUNE_13_12,Signal detect filter function select: Selects which of the two RX signal detect filter functions are enabled" "0,1,2,3"
rbitfld.long 0x10 8.--11. "RX_DIAG_SIGDET_TUNE_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 7. "RX_DIAG_SIGDET_TUNE_7,Receiver signal detect invert samplers: Inverts the behavior of the rxda_sd_pulse_high and rxda_sd_pulse_low samplers by driving the rxda_sd_invert_samplers signal to the analog" "0,1"
bitfld.long 0x10 6. "RX_DIAG_SIGDET_TUNE_6,Receiver signal detect squelch pulse none: Enable the squelch function for the rxda_sd_pulse_none signal by driving the rxda_sd_squelch_pulse_none signal to the analog" "0,1"
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bitfld.long 0x10 5. "RX_DIAG_SIGDET_TUNE_5,Receiver signal detect one comparator mode: Enables one comparator mode as a power reduction option by driving the rxda_sd_onecomp_mode_en signal to the analog" "0,1"
bitfld.long 0x10 4. "RX_DIAG_SIGDET_TUNE_4,Receiver signal detect DC coupled path enable: Enables a DC coupled path to the signal detect for verification and testability purposes by driving the rxda_sd_dcpath_en signal to the analog" "0,1"
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rbitfld.long 0x10 3. "RX_DIAG_SIGDET_TUNE_3,Reserved" "0,1"
bitfld.long 0x10 0.--2. "RX_DIAG_SIGDET_TUNE_2_0,Signal detect level: Sets the reference voltage level at which the comparators will detect a signal by driving the rxda_sd_siglvl_n signal going to the analog" "0,1,2,3,4,5,6,7"
line.long 0x14 "RX_DIAG_SD_TEST_j,Signal detect test register Offset = 83D4h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x14 4.--15. 1. "RX_DIAG_SD_TEST_15_4,Reserved"
bitfld.long 0x14 3. "RX_DIAG_SD_TEST_3,LFPS detected low test bit: This bit can be used to detect if the rx_lfps_detect is driven to a low state" "0,1"
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bitfld.long 0x14 2. "RX_DIAG_SD_TEST_2,LFPS detected high test bit: This bit can be used to detect if the rx_lfps_detect is driven to a high state" "0,1"
bitfld.long 0x14 1. "RX_DIAG_SD_TEST_1,Signal detected low test bit: This bit can be used to detect if the rx_signal_detect is driven to a low state" "0,1"
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bitfld.long 0x14 0. "RX_DIAG_SD_TEST_0,Signal detected high test bit: This bit can be used to detect if the rx_signal_detect is driven to a high state" "0,1"
line.long 0x18 "RX_DIAG_SH_SLC_IPP__RX_DIAG_SAMP_CTRL_j,RX sampler diagnostic control register Offset = 83D8h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x18 31. "RX_DIAG_SH_SLC_IPP_15,Reserved" "0,1"
hexmask.long.byte 0x18 24.--30. 1. "RX_DIAG_SH_SLC_IPP_14_8,RX sampler latch calibration I even positive code: RX sampler latch calibration I even positive code signal value as it is currently captured in the sample and hold latches"
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rbitfld.long 0x18 23. "RX_DIAG_SH_SLC_IPP_7,Reserved" "0,1"
hexmask.long.byte 0x18 16.--22. 1. "RX_DIAG_SH_SLC_IPP_6_0,RX sampler latch calibration I odd positive code: RX sampler latch calibration I odd positive code signal value as it is currently captured in the sample and hold latches"
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hexmask.long.word 0x18 2.--15. 1. "RX_DIAG_SAMP_CTRL_15_2,Reserved"
bitfld.long 0x18 1. "RX_DIAG_SAMP_CTRL_1,RX sampler latch range extend: Controls the range of the RX sampler calibration by driving the rxda_sampler_latch_cal_range_ext signal to the analog" "0,1"
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bitfld.long 0x18 0. "RX_DIAG_SAMP_CTRL_0,Analog sampler rxda_dfe_0p5ui_mode_en signal control: Selects which delayed I data is to be used to unroll the Q data in the sampler" "0,1"
line.long 0x1C "RX_DIAG_SH_SLC_QPP__RX_DIAG_SH_SLC_IPM_j,Sample and hold RX sampler latch calibration I predictive negative code register Offset = 83DCh + (j * 400h); where j = 0h to 3h"
bitfld.long 0x1C 31. "RX_DIAG_SH_SLC_QPP_15,Reserved" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. "RX_DIAG_SH_SLC_QPP_14_8,RX sampler latch calibration Q even positive code: RX sampler latch calibration Q even positive code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x1C 23. "RX_DIAG_SH_SLC_QPP_7,Reserved" "0,1"
hexmask.long.byte 0x1C 16.--22. 1. "RX_DIAG_SH_SLC_QPP_6_0,RX sampler latch calibration Q odd positive code: RX sampler latch calibration Q odd positive code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x1C 15. "RX_DIAG_SH_SLC_IPM_15,Reserved" "0,1"
hexmask.long.byte 0x1C 8.--14. 1. "RX_DIAG_SH_SLC_IPM_14_8,RX sampler latch calibration I even negative code: RX sampler latch calibration I even negative code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x1C 7. "RX_DIAG_SH_SLC_IPM_7,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "RX_DIAG_SH_SLC_IPM_6_0,RX sampler latch calibration I odd negative code: RX sampler latch calibration I odd negative code signal value as it is currently captured in the sample and hold latches"
line.long 0x20 "RX_DIAG_SH_SLC_EPP__RX_DIAG_SH_SLC_QPM_j,Sample and hold RX sampler latch calibration Q predictive negative code register Offset = 83E0h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x20 31. "RX_DIAG_SH_SLC_EPP_15,Reserved" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "RX_DIAG_SH_SLC_EPP_14_8,RX sampler latch calibration E even positive code: RX sampler latch calibration E even positive code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x20 23. "RX_DIAG_SH_SLC_EPP_7,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "RX_DIAG_SH_SLC_EPP_6_0,RX sampler latch calibration E odd positive code: RX sampler latch calibration E odd positive code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x20 15. "RX_DIAG_SH_SLC_QPM_15,Reserved" "0,1"
hexmask.long.byte 0x20 8.--14. 1. "RX_DIAG_SH_SLC_QPM_14_8,RX sampler latch calibration Q even negative code: RX sampler latch calibration Q even negative code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x20 7. "RX_DIAG_SH_SLC_QPM_7,Reserved" "0,1"
hexmask.long.byte 0x20 0.--6. 1. "RX_DIAG_SH_SLC_QPM_6_0,RX sampler latch calibration Q odd negative code: RX sampler latch calibration Q odd negative code signal value as it is currently captured in the sample and hold latches"
line.long 0x24 "RX_DIAG_SH_SLC_EPM_j,Sample and hold RX sampler latch calibration E predictive negative code register Offset = 83E4h + (j * 400h); where j = 0h to 3h"
bitfld.long 0x24 15. "RX_DIAG_SH_SLC_EPM_15,Reserved" "0,1"
hexmask.long.byte 0x24 8.--14. 1. "RX_DIAG_SH_SLC_EPM_14_8,RX sampler latch calibration E even negative code: RX sampler latch calibration E even negative code signal value as it is currently captured in the sample and hold latches"
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bitfld.long 0x24 7. "RX_DIAG_SH_SLC_EPM_7,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "RX_DIAG_SH_SLC_EPM_6_0,RX sampler latch calibration E odd negative code: RX sampler latch calibration E odd negative code signal value as it is currently captured in the sample and hold latches"
line.long 0x28 "RX_DIAG_PI_CAP__RX_DIAG_PI_RATE_j,PI rate selection register Offset = 83E8h + (j * 400h); where j = 0h to 3h"
rbitfld.long 0x28 31. "RX_DIAG_PI_CAP_15,Reserved" "0,1"
bitfld.long 0x28 28.--30. "RX_DIAG_PI_CAP_14_12,PI capacitor selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 27. "RX_DIAG_PI_CAP_11,Reserved" "0,1"
bitfld.long 0x28 24.--26. "RX_DIAG_PI_CAP_10_8,PI capacitor selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 23. "RX_DIAG_PI_CAP_7,Reserved" "0,1"
bitfld.long 0x28 20.--22. "RX_DIAG_PI_CAP_6_4,PI capacitor selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 19. "RX_DIAG_PI_CAP_3,Reserved" "0,1"
bitfld.long 0x28 16.--18. "RX_DIAG_PI_CAP_2_0,PI capacitor selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 15. "RX_DIAG_PI_RATE_15,Reserved" "0,1"
bitfld.long 0x28 12.--14. "RX_DIAG_PI_RATE_14_12,PI rate selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 11. "RX_DIAG_PI_RATE_11,Reserved" "0,1"
bitfld.long 0x28 8.--10. "RX_DIAG_PI_RATE_10_8,PI rate selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 7. "RX_DIAG_PI_RATE_7,Reserved" "0,1"
bitfld.long 0x28 4.--6. "RX_DIAG_PI_RATE_6_4,PI rate selection standard mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 3. "RX_DIAG_PI_RATE_3,Reserved" "0,1"
bitfld.long 0x28 0.--2. "RX_DIAG_PI_RATE_2_0,PI rate selection standard mode" "0,1,2,3,4,5,6,7"
line.long 0x2C "RX_DIAG_PI_TUNE_j,PI tuning register Offset = 83ECh + (j * 400h); where j = 0h to 3h"
hexmask.long.byte 0x2C 8.--15. 1. "RX_DIAG_PI_TUNE_15_8,Reserved"
bitfld.long 0x2C 7. "RX_DIAG_PI_TUNE_7,Receiver CML to CMOS rate select value standard mode" "0,1"
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bitfld.long 0x2C 6. "RX_DIAG_PI_TUNE_6,Receiver CML to CMOS rate select value standard mode" "0,1"
bitfld.long 0x2C 5. "RX_DIAG_PI_TUNE_5,Receiver CML to CMOS rate select value standard mode" "0,1"
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bitfld.long 0x2C 4. "RX_DIAG_PI_TUNE_4,Receiver CML to CMOS rate select value standard mode" "0,1"
rbitfld.long 0x2C 1.--3. "RX_DIAG_PI_TUNE_3_1,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x2C 0. "RX_DIAG_PI_TUNE_0,PI current select: Selects either the external based bias or the poly based bias for the PI by driving the rxda_pi_cur_sel signal going into the analog" "0,1"
line.long 0x30 "RX_DIAG_RST_DIAG__RX_DIAG_LPBK_CTRL_j,RX loopback controller register Offset = 83F0h + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x30 22.--31. 1. "RX_DIAG_RST_DIAG_15_6,Reserved"
rbitfld.long 0x30 21. "RX_DIAG_RST_DIAG_5,Current state of the rxda_clk_reset_n reset" "0,1"
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rbitfld.long 0x30 20. "RX_DIAG_RST_DIAG_4,Current state of the rx_dig_reset_n reset" "0,1"
rbitfld.long 0x30 19. "RX_DIAG_RST_DIAG_3,Current state of the rxda_cdrlf_reset_n reset" "0,1"
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rbitfld.long 0x30 18. "RX_DIAG_RST_DIAG_2,Current state of the rx_ree_fcn_reset_n reset" "0,1"
rbitfld.long 0x30 17. "RX_DIAG_RST_DIAG_1,Current state of the rx_ree_ctrl_reset_n reset" "0,1"
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rbitfld.long 0x30 16. "RX_DIAG_RST_DIAG_0,Current state of the rx_lfps_det_filter_reset_n reset" "0,1"
hexmask.long.word 0x30 6.--15. 1. "RX_DIAG_LPBK_CTRL_15_6,Reserved"
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bitfld.long 0x30 4.--5. "RX_DIAG_LPBK_CTRL_5_4,Recovered clock loopback select: Selects which recovered clock to use when recovered clock loopback is enabled" "0,1,2,3"
bitfld.long 0x30 0.--3. "RX_DIAG_LPBK_CTRL_3_0,Attenuation settings: Sets the attenuation for the ISI generation loopback filter as specified below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x83FC++0x03
line.long 0x00 "RX_DIAG_ACYA__RX_DIAG_DCYA_j,Receiver digital cover your alternatives register Offset = 83FCh + (j * 400h); where j = 0h to 3h"
hexmask.long.word 0x00 16.--31. 1. "RX_DIAG_ACYA_15_0,Reserved - spare"
hexmask.long.word 0x00 0.--15. 1. "RX_DIAG_DCYA_15_0,Reserved - spare"
group.long 0xC000++0x17
line.long 0x00 "PHY_PIPE_CMN_CTRL2__PHY_PIPE_CMN_CTRL1,PIPE common control1 register"
bitfld.long 0x00 28.--31. "PHY_PIPE_CMN_CTRL2_15_12,USB SuperSpeed Tx LFPS Stretch : Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeed rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PHY_PIPE_CMN_CTRL2_11_8,USB SuperSpeedPlus Tx LFPS Stretch : Minimum number of data rate clock cycles in which PMA tx_lfps_en signal is asserted for USB SuperSpeedPlus rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "PHY_PIPE_CMN_CTRL2_7,Reserved" "0,1"
bitfld.long 0x00 22. "PHY_PIPE_CMN_CTRL2_6,PCIe PCS TX electrical idle pre release:When this bit is set the TX electrical idle release to the PMA is advanced 1" "0,1"
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bitfld.long 0x00 21. "PHY_PIPE_CMN_CTRL2_5,RX equaliser complete mask: When this bit is cleared the PHY will return direction change of 0 when PMA indicates evaluation complete" "0,1"
bitfld.long 0x00 20. "PHY_PIPE_CMN_CTRL2_4,PCIe PCS EIOS cycle error mask: When this bit is enabled and the pipe rx interface is outputting an EIOS symbol decode errors will be masked out" "0,1"
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bitfld.long 0x00 19. "PHY_PIPE_CMN_CTRL2_3,USB Gen 2 Bit Error Correction Disable: When this bit is high bit error correction on SKP and SDS symbols is disabled" "0,1"
bitfld.long 0x00 18. "PHY_PIPE_CMN_CTRL2_2,USB PIPE3 Compatibility Mode enable : When this bit is set to 1 USB PIPE3 compatibility mode is enabled" "0,1"
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bitfld.long 0x00 17. "PHY_PIPE_CMN_CTRL2_1,USB Loopback Slave Error Count disable: When this bit is set to 1 disables the error count for US loopback slave such that the error count is not inserted into the BCNT OS" "0,1"
bitfld.long 0x00 16. "PHY_PIPE_CMN_CTRL2_0,USB Elasticity Buffer Re-align enable: When this bit is set to 1 when Rx for a USB link is initially started the elasticity buffer is re-aligned to its idle point upon seeing 3 consecutive COMMAs (i.e" "0,1"
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rbitfld.long 0x00 13.--15. "PHY_PIPE_CMN_CTRL1_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "PHY_PIPE_CMN_CTRL1_12,PHY APB access timeout: When set an APB read/write request to PHY registers failed (i.e. timed out)" "0,1"
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rbitfld.long 0x00 11. "PHY_PIPE_CMN_CTRL1_11,Reserved" "0,1"
bitfld.long 0x00 10. "PHY_PIPE_CMN_CTRL1_10,PCIe PCS Comma realign: This field controls the comma alignment state machine to re-align to new bit position without going to loss of sync state" "0,1"
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bitfld.long 0x00 9. "PHY_PIPE_CMN_CTRL1_9,Block alignment clear on EIOS : When set upon receiving a PCIe EIOS 128b/130b block alignment is reset regardless of Rx signal detect from the PMA (applies for PCIe Gen 3 only)" "0,1"
bitfld.long 0x00 8. "PHY_PIPE_CMN_CTRL1_8,Comma alignment clear on EIOS : When set upon receiving a PCIe EIOS Comma Alignment is reset regardless of Rx signal detect from the PMA (applies for PCIe Gen 1/2 only)" "0,1"
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bitfld.long 0x00 7. "PHY_PIPE_CMN_CTRL1_7,Block alignment ignore Rx SigDetect : When set 128b/13xb block alignment will not be reset due to loss of signal detection from the PMA (applies for PCIe Gen 3 and USB3.1 Gen 2 only)" "0,1"
bitfld.long 0x00 6. "PHY_PIPE_CMN_CTRL1_6,Comma alignment ignore Rx SigDetect : When set Comma alignment will not be reset due to loss of signal detection from the PMA (applies for PCIe Gen 1/2 and USB3.1 Gen 1 only)" "0,1"
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bitfld.long 0x00 4.--5. "PHY_PIPE_CMN_CTRL1_5_4,Rx signal detect delay : Selects the number of clock cycles of delay to add to the PMA signal detect when the bit alignment blocks should be reset after losing signal" "0,1,2,3"
rbitfld.long 0x00 2.--3. "PHY_PIPE_CMN_CTRL1_3_2,Reserved" "0,1,2,3"
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bitfld.long 0x00 1. "PHY_PIPE_CMN_CTRL1_1,RefClk disable override" "0,1"
bitfld.long 0x00 0. "PHY_PIPE_CMN_CTRL1_0,PHY RefClk enable input ingnore" "0,1"
line.long 0x04 "PHY_PIPE_COM_LOCK_CFG2__PHY_PIPE_COM_LOCK_CFG1,PIPE comma lock configuration1 register"
hexmask.long.byte 0x04 24.--31. 1. "PHY_PIPE_COM_LOCK_CFG2_15_8,PCIe PCS Comma lock count fast: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock"
hexmask.long.byte 0x04 16.--23. 1. "PHY_PIPE_COM_LOCK_CFG2_7_0,PCIe PCS Comma lock count: The number of COMMA symbols that needs to be seen in the same bit position for the comma state machine to lock"
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bitfld.long 0x04 12.--15. "PHY_PIPE_COM_LOCK_CFG1_15_12,PCIe PCS Comma unlock count: The number of COMMA symbols that need to be seen in the wrong bit position before the comma alignment state machine will transition to RESYNC or LOS state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--11. 1. "PHY_PIPE_COM_LOCK_CFG1_11_0,PCIe PCS Comma full lock count: The number of COMMA symbols that need to be seen in the same bit position for the comma alignment state machine to lock"
line.long 0x08 "PHY_PIPE_LANE_DSBL__PHY_PIPE_EIE_LOCK_CFG,PIPE EIEOS lock configuration register"
hexmask.long.byte 0x08 24.--31. 1. "PHY_PIPE_LANE_DSBL_15_8,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "PHY_PIPE_LANE_DSBL_7_0,PIPE lane disable: Each bit corresponds to a lane (i.e. bit [0] -X lane 0 bit [1] -X lane 1 etc)"
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bitfld.long 0x08 12.--15. "PHY_PIPE_EIE_LOCK_CFG_15_12,EIE lock count fast: The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "PHY_PIPE_EIE_LOCK_CFG_11_8,EIE lock count : The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 0.--7. 1. "PHY_PIPE_EIE_LOCK_CFG_7_0,EIE full lock count: The number of EIEOS blocks that need to be seen in the same bit postion for the alignment state machine to lock for Gen3/4"
line.long 0x0C "PHY_PIPE_RX_ELEC_IDLE_DLY__PHY_PIPE_RCV_DET_INH,PIPE receiver detect inhibit register"
bitfld.long 0x0C 26.--31. "PHY_PIPE_RX_ELEC_IDLE_DLY_15_10,PCIe PCS L1.x exit Rx electrical idle force fast count : Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 16.--25. 1. "PHY_PIPE_RX_ELEC_IDLE_DLY_9_0,PCIe PCS L1.x exit Rx electrical idle force full count : Counter load value to hold PIPE Rx Electrical Idle high upon exit from L1.x when the PMA common was powered down"
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hexmask.long.word 0x0C 0.--15. 1. "PHY_PIPE_RCV_DET_INH_15_0,PCS Receiver Detect Inhibit Counter Load Value: Counter load value to delay receiver detection request to PMA until PMA common mode is within the required range"
line.long 0x10 "PHY_ISO_CMN_CTRL,PHY common control signal isolation register"
rbitfld.long 0x10 13.--15. "PHY_ISO_CMN_CTRL_15_13,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x10 12. "PHY_ISO_CMN_CTRL_12,Current value of phy_refclk_reqd PHY output" "0,1"
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rbitfld.long 0x10 9.--11. "PHY_ISO_CMN_CTRL_11_9,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8. "PHY_ISO_CMN_CTRL_8,Drives phy_refclk_en PHY input when in PHY macro and PMA isolation mode" "0,1"
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rbitfld.long 0x10 6.--7. "PHY_ISO_CMN_CTRL_7_6,Reserved" "0,1,2,3"
bitfld.long 0x10 5. "PHY_ISO_CMN_CTRL_5,Drives phy_pma_suspend_override PHY input when in PHY macro and PMA isolation mode" "0,1"
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bitfld.long 0x10 4. "PHY_ISO_CMN_CTRL_4,Drives refclk_rcvr_pwrdn internal PHY signal when in PHY macro and PMA isolation mode (1 = powers down the reference clock receiver)" "0,1"
rbitfld.long 0x10 1.--3. "PHY_ISO_CMN_CTRL_3_1,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 0. "PHY_ISO_CMN_CTRL_0,Drives phy_reset_n PHY input when in PHY macro and PMA isolation mode" "0,1"
line.long 0x14 "PHY_STATE_CHG_TIMEOUT,PHY state change monitor timeout"
hexmask.long.word 0x14 0.--15. 1. "PHY_STATE_CHG_TIMEOUT_15_0,State change timeout: Bits [19:4] of the state change timeout (bits [3:0] are zero)"
group.long 0xC01C++0x0F
line.long 0x00 "PHY_AUTO_CFG_SPDUP,PHY speedup control register"
hexmask.long.word 0x00 20.--31. 1. "PHY_AUTO_CFG_SPDUP_15_4,Reserved"
rbitfld.long 0x00 19. "PHY_AUTO_CFG_SPDUP_3,Speedup configuration complete" "0,1"
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bitfld.long 0x00 18. "PHY_AUTO_CFG_SPDUP_2,Speedup configuration stall" "0,1"
bitfld.long 0x00 17. "PHY_AUTO_CFG_SPDUP_1,Speedup configuration enable: If set to 1 upon de-assertion (high) of phy_reset_n the PHY will be configured for simulation speedup" "0,1"
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rbitfld.long 0x00 16. "PHY_AUTO_CFG_SPDUP_0,Reserved" "0,1"
hexmask.long.word 0x00 2.--15. 1. "PHY_PLL_CFG_15_2,Reserved"
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bitfld.long 0x00 1. "PHY_PLL_CFG_1,PLL configuration" "0,1"
bitfld.long 0x00 0. "PHY_PLL_CFG_0,Single link PCIe configuration" "0,1"
line.long 0x04 "PHY_REFCLK_DET_THRES_HIGH__PHY_REFCLK_DET_THRES_LOW,PHY external reference clock detect low threshold register"
hexmask.long.word 0x04 16.--31. 1. "PHY_REFCLK_DET_THRES_HIGH_15_0,External Reference Clock Active Detect High Threshold: This is the maximum number of external reference clock cycles which must be counted during the measurement interval to indicate a valid clock detected"
hexmask.long.word 0x04 0.--15. 1. "PHY_REFCLK_DET_THRES_LOW_15_0,External Reference Clock Active Detect Low Threshold: This is the minimum number of external reference clock cycles which must be counted during the measurement interval to indicate a valid clock detected"
line.long 0x08 "PHY_REFCLK_DET_OP_DELAY__PHY_REFCLK_DET_INTERVAL,PHY external reference clock detect measurement interval register"
hexmask.long.byte 0x08 24.--31. 1. "PHY_REFCLK_DET_OP_DELAY_15_8,External Reference Clock Active Detect End Delay: This is the number of apb_pclk cycles to wait upon completion of measurement interval before capturing the result (accounts for synchronization delays)"
hexmask.long.byte 0x08 16.--23. 1. "PHY_REFCLK_DET_OP_DELAY_7_0,External Reference Clock Active Detect Start Delay: This is the number of apb_pclk cycles to wait prior to start of measurement interval (accounts for enable delay of reference clock in PMA)"
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hexmask.long.word 0x08 0.--15. 1. "PHY_REFCLK_DET_INTERVAL_15_0,External Reference Clock Active Detect Measurement Interval: This is the number of apb_pclk cycles in which to count external reference clock cycles"
line.long 0x0C "PHY_REFCLK_DET_ISO_CTRL,PHY external reference clock detect isolation control register"
rbitfld.long 0x0C 13.--15. "PHY_REFCLK_DET_ISO_CTRL_15_13,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0C 12. "PHY_REFCLK_DET_ISO_CTRL_12,Captures the current value of the pma_cmn_ext_refclk_detected_cfg PHY input" "0,1"
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rbitfld.long 0x0C 10.--11. "PHY_REFCLK_DET_ISO_CTRL_11_10,Reserved" "0,1,2,3"
rbitfld.long 0x0C 9. "PHY_REFCLK_DET_ISO_CTRL_9,Current value of pma_cmn_ext_refclk_detected PHY output" "0,1"
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rbitfld.long 0x0C 8. "PHY_REFCLK_DET_ISO_CTRL_8,Current value of pma_cmn_ext_refclk_detected_valid PHY output" "0,1"
hexmask.long.byte 0x0C 1.--7. 1. "PHY_REFCLK_DET_ISO_CTRL_7_1,Reserved"
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bitfld.long 0x0C 0. "PHY_REFCLK_DET_ISO_CTRL_0,External Reference Clock Active Detect Start: Write with 1 to initiate an external reference clock active detect operation" "0,1"
group.long 0xD000++0x27
line.long 0x00 "PHY_PIPE_ISO_TX_LPC_LO__PHY_PIPE_ISO_TX_CTRL_j,PIPE TX control signal isolation register Offset = D000h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x00 30.--31. "PHY_PIPE_ISO_TX_LPC_LO_15_14,Reserved" "0,1,2,3"
rbitfld.long 0x00 24.--29. "PHY_PIPE_ISO_TX_LPC_LO_13_8,Current value of pipe_tx_local_tx_preset_coefficients [11:6] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 22.--23. "PHY_PIPE_ISO_TX_LPC_LO_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x00 16.--21. "PHY_PIPE_ISO_TX_LPC_LO_5_0,Current value of pipe_tx_local_tx_preset_coefficients [5:0] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 12.--15. "PHY_PIPE_ISO_TX_CTRL_15_12,Drives pipe_tx_data_k PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 9.--11. "PHY_PIPE_ISO_TX_CTRL_11_9,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "PHY_PIPE_ISO_TX_CTRL_8,Drives pipe_tx_ones_zeros input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
rbitfld.long 0x00 5.--7. "PHY_PIPE_ISO_TX_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "PHY_PIPE_ISO_TX_CTRL_4,Drives pipe_tx_elec_idle PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
bitfld.long 0x00 3. "PHY_PIPE_ISO_TX_CTRL_3,Drives pipe_tx_128b_enc_byp PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x00 2. "PHY_PIPE_ISO_TX_CTRL_2,Drives pipe_tx_compliance PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
bitfld.long 0x00 0.--1. "PHY_PIPE_ISO_TX_CTRL_1_0,Drives pipe_tx_pattern PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3"
line.long 0x04 "PHY_PCS_ISO_TX_DMPH_LO__PHY_PIPE_ISO_TX_LPC_HI_j,PIPE TX local preset coefficients high isolation register Offset = D004h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x04 30.--31. "PHY_PCS_ISO_TX_DMPH_LO_15_14,Reserved" "0,1,2,3"
bitfld.long 0x04 24.--29. "PHY_PCS_ISO_TX_DMPH_LO_13_8,Drives pipe_tx_deemph[11:6] PHY input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x04 22.--23. "PHY_PCS_ISO_TX_DMPH_LO_7_6,Reserved" "0,1,2,3"
bitfld.long 0x04 16.--21. "PHY_PCS_ISO_TX_DMPH_LO_5_0,Drives pipe_tx_deemph[5:0] PHY input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x04 15. "PHY_PIPE_ISO_TX_LPC_HI_15,Set upon assertion of pipe_tx_local_tx_coeff_vld PHY output for the associated lane" "0,1"
rbitfld.long 0x04 13.--14. "PHY_PIPE_ISO_TX_LPC_HI_14_13,Reserved" "0,1,2,3"
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bitfld.long 0x04 12. "PHY_PIPE_ISO_TX_LPC_HI_12,Drives pipe_tx_get_local_preset_coef PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1"
bitfld.long 0x04 8.--11. "PHY_PIPE_ISO_TX_LPC_HI_11_8,Drives pipe_tx_local_preset_index PHY output for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x04 6.--7. "PHY_PIPE_ISO_TX_LPC_HI_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x04 0.--5. "PHY_PIPE_ISO_TX_LPC_HI_5_0,Current value of pipe_tx_local_tx_preset_coefficients[17:12] for the associated lane when PHY_PCS_ISO_TX_LPC_HI[15] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PHY_PIPE_ISO_TX_FSLF__PHY_PIPE_ISO_TX_DMPH_HI_j,PIPE TX deemphasis high isolation register Offset = D008h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x08 30.--31. "PHY_PIPE_ISO_TX_FSLF_15_14,Reserved" "0,1,2,3"
rbitfld.long 0x08 24.--29. "PHY_PIPE_ISO_TX_FSLF_13_8,Current value of pipe_tx_local_fs PHY output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x08 22.--23. "PHY_PIPE_ISO_TX_FSLF_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x08 16.--21. "PHY_PIPE_ISO_TX_FSLF_5_0,Current value of pipe_tx_local_lf PHY output for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x08 6.--15. 1. "PHY_PIPE_ISO_TX_DMPH_HI_15_6,Reserved"
bitfld.long 0x08 0.--5. "PHY_PIPE_ISO_TX_DMPH_HI_5_0,Drives pipe_tx_deemph[17:12] PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "PHY_PCS_ISO_TX_DATA_HI__PHY_PCS_ISO_TX_DATA_LO_j,PCS TX PIPE data low isolation register Offset = D00Ch + (j * 200h); where j = 0h to 3h"
hexmask.long.word 0x0C 16.--31. 1. "PHY_PCS_ISO_TX_DATA_HI_15_0,Drives pipe_tx_data[31:16] PHY input for the associated lane when in PHY macro and PMA isolation mode"
hexmask.long.word 0x0C 0.--15. 1. "PHY_PCS_ISO_TX_DATA_LO_15_0,Drives pipe_tx_data[15:0] PHY input for the associated lane when in PHY macro and PMA isolation mode"
line.long 0x10 "PHY_PIPE_ISO_RX_EQ_EVAL__PHY_PCS_ISO_RX_CTRL_j,PCS RX control signal isolation register Offset = D010h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x10 29.--31. "PHY_PIPE_ISO_RX_EQ_EVAL_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 28. "PHY_PIPE_ISO_RX_EQ_EVAL_12,Drives pipe_invalid_request for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x10 27. "PHY_PIPE_ISO_RX_EQ_EVAL_11,pipe_link_eval_dir_change[5:4] bit reversal enable" "0,1"
bitfld.long 0x10 26. "PHY_PIPE_ISO_RX_EQ_EVAL_10,pipe_link_eval_dir_change[3:2] bit reversal enable" "0,1"
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bitfld.long 0x10 25. "PHY_PIPE_ISO_RX_EQ_EVAL_9,pipe_link_eval_dir_change[1:0] bit reversal enable" "0,1"
bitfld.long 0x10 24. "PHY_PIPE_ISO_RX_EQ_EVAL_8,Drives pipe_rx_eval PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x10 23. "PHY_PIPE_ISO_RX_EQ_EVAL_7,Reserved" "0,1"
rbitfld.long 0x10 22. "PHY_PIPE_ISO_RX_EQ_EVAL_6,Captures pipe_phy_status for Rx equalization evaluation PHY output for the associated lane (does not include power state change signaling)" "0,1"
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rbitfld.long 0x10 16.--21. "PHY_PIPE_ISO_RX_EQ_EVAL_5_0,pipe_link_eval_dir_change PHY output for the associated lane (prior to bit reversal logic) upon completion of Rx equalization evaluation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x10 12.--15. "PHY_PCS_ISO_RX_CTRL_15_12,Current value of pipe_rx_data_k PHY output for the associated lane when PHY_PCS_ISO_RX_CTRL[5] == 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x10 10.--11. "PHY_PCS_ISO_RX_CTRL_11_10,Reserved" "0,1,2,3"
bitfld.long 0x10 9. "PHY_PCS_ISO_RX_CTRL_9,Drives pipe_rx_eq_training PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x10 8. "PHY_PCS_ISO_RX_CTRL_8,Drives pipe_rx_termination PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
bitfld.long 0x10 7. "PHY_PCS_ISO_RX_CTRL_7,Drives pipe_rx_polarity PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x10 6. "PHY_PCS_ISO_RX_CTRL_6,Reserved" "0,1"
rbitfld.long 0x10 5. "PHY_PCS_ISO_RX_CTRL_5,Current value of pipe_rx_valid PHY output for the associated lane" "0,1"
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rbitfld.long 0x10 4. "PHY_PCS_ISO_RX_CTRL_4,Current value of pipe_rx_elec_idle PHY output for the associated lane" "0,1"
rbitfld.long 0x10 3. "PHY_PCS_ISO_RX_CTRL_3,Current value of pipe_align_detect PHY output for the associated lane" "0,1"
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rbitfld.long 0x10 0.--2. "PHY_PCS_ISO_RX_CTRL_2_0,Current value of pipe_rx_status PHY output for the associated lane" "0,1,2,3,4,5,6,7"
line.long 0x14 "PHY_PCS_ISO_LINK_CTRL__PHY_ISO_LINK_CFG_j,PHY link configuration isolation register Offset = D014h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x14 30.--31. "PHY_PCS_ISO_LINK_CTRL_15_14,Reserved" "0,1,2,3"
rbitfld.long 0x14 29. "PHY_PCS_ISO_LINK_CTRL_13,Current value of phy_l*_ack_l1_x PHY output for the associated lane" "0,1"
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bitfld.long 0x14 28. "PHY_PCS_ISO_LINK_CTRL_12,Drives the phy_l*_ent_l1_x PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
bitfld.long 0x14 27. "PHY_PCS_ISO_LINK_CTRL_11,Drives the phy_l*_rx_elec_idle_det_en PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
newline
bitfld.long 0x14 26. "PHY_PCS_ISO_LINK_CTRL_10,Drives the phy_l*_tx_cmn_mode_en PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
bitfld.long 0x14 24.--25. "PHY_PCS_ISO_LINK_CTRL_9_8,Drives the pipe_l*_rate PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3"
newline
rbitfld.long 0x14 23. "PHY_PCS_ISO_LINK_CTRL_7,Reserved" "0,1"
bitfld.long 0x14 20.--22. "PHY_PCS_ISO_LINK_CTRL_6_4,Drives the pipe_l*_powerdown PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x14 19. "PHY_PCS_ISO_LINK_CTRL_3,Reserved" "0,1"
bitfld.long 0x14 18. "PHY_PCS_ISO_LINK_CTRL_2,Drives the pipe_l*_tx_det_rx_lpbk PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
newline
rbitfld.long 0x14 17. "PHY_PCS_ISO_LINK_CTRL_1,Captures pipe_l*_phy_status (for power state and rate change) PHY output for the associated lane" "0,1"
bitfld.long 0x14 16. "PHY_PCS_ISO_LINK_CTRL_0,Drives the phy_l*_reset_n PHY input for the associated lane when in PHY macro and PMA isolation modes" "0,1"
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bitfld.long 0x14 15. "PHY_ISO_LINK_CFG_15,Drives phy_link_cfg_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes" "0,1"
rbitfld.long 0x14 13.--14. "PHY_ISO_LINK_CFG_14_13,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 12. "PHY_ISO_LINK_CFG_12,Drives pipe_l{nnnn}_32bit_sel PHY input when in PHY macro and PMA isolation modes" "0,1"
rbitfld.long 0x14 10.--11. "PHY_ISO_LINK_CFG_11_10,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 8.--9. "PHY_ISO_LINK_CFG_9_8,Drives pma_fullrt_div_ln_{nnnn} PHY input when in PHY macro and PMA isolation modes" "0,1,2,3"
rbitfld.long 0x14 6.--7. "PHY_ISO_LINK_CFG_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 5. "PHY_ISO_LINK_CFG_5,Drives pipe_l{nnnn}_pcie_l1_ss_sel PHY input when in PHY macro and PMA isolation mode" "0,1"
bitfld.long 0x14 4. "PHY_ISO_LINK_CFG_4,Drives pipe_l{nnnn}_eb_mode PHY input when in PHY macro and PMA isolation modes" "0,1"
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rbitfld.long 0x14 2.--3. "PHY_ISO_LINK_CFG_3_2,Reserved" "0,1,2,3"
bitfld.long 0x14 0.--1. "PHY_ISO_LINK_CFG_1_0,Drives phy_l{nnnn}_mode PHY input when in PHY macro and PMA isolation modes" "0,1,2,3"
line.long 0x18 "PHY_PIPE_ISO_USB_BER_CNT_j,PIPE USB Gen 1 loopback slave BER count register Offset = D018h + (j * 200h); where j = 0h to 3h"
hexmask.long.byte 0x18 8.--15. 1. "PHY_PIPE_ISO_USB_BER_CNT_15_8,Reerved"
hexmask.long.byte 0x18 0.--7. 1. "PHY_PIPE_ISO_USB_BER_CNT_7_0,Current value of USB 3.1 Gen 1 loopback slave Bit Error Count from the PCS"
line.long 0x1C "PHY_PCS_ISO_RX_DATA_HI__PHY_PCS_ISO_RX_DATA_LO_j,PCS RX data low isolation register Offset = D01Ch + (j * 200h); where j = 0h to 3h"
hexmask.long.word 0x1C 16.--31. 1. "PHY_PCS_ISO_RX_DATA_HI_15_0,Current value of pipe_rx_data[31:16] PHY output"
hexmask.long.word 0x1C 0.--15. 1. "PHY_PCS_ISO_RX_DATA_LO_15_0,Current value of pipe_rx_data[15:0] PHY output"
line.long 0x20 "PHY_ETH_ISO_MAC_CLK_DIV__PHY_ETH_ISO_MAC_CLK_CFG_j,Ethernet MAC clock configuration isolation register Offset = D020h + (j * 200h); where j = 0h to 3h"
hexmask.long.word 0x20 23.--31. 1. "PHY_ETH_ISO_MAC_CLK_DIV_15_7,Drives mac_div_sel1 PHY input for the associated lane when in PHY macro and PMA isolation mode"
hexmask.long.byte 0x20 16.--22. 1. "PHY_ETH_ISO_MAC_CLK_DIV_6_0,Drives mac_div_sel0 PHY input for the associated lane when in PHY macro and PMA isolation mode"
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hexmask.long.word 0x20 2.--15. 1. "PHY_ETH_ISO_MAC_CLK_CFG_15_2,Reserved"
bitfld.long 0x20 0.--1. "PHY_ETH_ISO_MAC_CLK_CFG_1_0,Drives mac_src_sel PHY input for the associated lane when in PHY macro and PMA isolation mode" "0,1,2,3"
line.long 0x24 "PHY_INTERRUPT_STS_j,PHY interrupt status register Offset = D024h + (j * 200h); where j = 0h to 3h"
bitfld.long 0x24 15. "PHY_INTERRUPT_STS_15,State change monitor enable" "0,1"
rbitfld.long 0x24 11.--14. "PHY_INTERRUPT_STS_14_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x24 8.--10. "PHY_INTERRUPT_STS_10_8,Next power state/data rate - Only valid when one of the interrupt status bits is set" "0,1,2,3,4,5,6,7"
rbitfld.long 0x24 7. "PHY_INTERRUPT_STS_7,Reserved" "0,1"
newline
rbitfld.long 0x24 4.--6. "PHY_INTERRUPT_STS_6_4,Current power state/data rate - Only valid when one of the interrupt status bits is set" "0,1,2,3,4,5,6,7"
rbitfld.long 0x24 2.--3. "PHY_INTERRUPT_STS_3_2,Reserved" "0,1,2,3"
newline
bitfld.long 0x24 1. "PHY_INTERRUPT_STS_1,Data rate state change interrupt status - Set to 1 upon data rate change timeout" "0,1"
bitfld.long 0x24 0. "PHY_INTERRUPT_STS_0,Power state change interrupt status - Set to 1 upon power state change timeout" "0,1"
group.long 0xE000++0x0F
line.long 0x00 "PHY_PMA_CMN_CTRL2__PHY_PMA_CMN_CTRL1,PMA common control1 register"
hexmask.long.byte 0x00 24.--31. 1. "PHY_PMA_CMN_CTRL2_15_8,Reserved"
rbitfld.long 0x00 23. "PHY_PMA_CMN_CTRL2_7,Current value of cmn_pll1_locked PMA output" "0,1"
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rbitfld.long 0x00 22. "PHY_PMA_CMN_CTRL2_6,Current value of cmn_pll0_locked PMA output" "0,1"
rbitfld.long 0x00 21. "PHY_PMA_CMN_CTRL2_5,Current value of cmn_pll1_clk_en_ack PMA output" "0,1"
newline
rbitfld.long 0x00 20. "PHY_PMA_CMN_CTRL2_4,Current value of cmn_pll0_clk_en_ack PMA output" "0,1"
rbitfld.long 0x00 19. "PHY_PMA_CMN_CTRL2_3,Current value of cmn_pll1_disabled PMA output" "0,1"
newline
rbitfld.long 0x00 18. "PHY_PMA_CMN_CTRL2_2,Current value of cmn_pll0_disabled PMA output" "0,1"
rbitfld.long 0x00 17. "PHY_PMA_CMN_CTRL2_1,Current value of cmn_pll1_ready PMA output" "0,1"
newline
rbitfld.long 0x00 16. "PHY_PMA_CMN_CTRL2_0,Current value of cmn_pll0_ready PMA output" "0,1"
hexmask.long.word 0x00 7.--15. 1. "PHY_PMA_CMN_CTRL1_15_7,Reserved"
newline
bitfld.long 0x00 6. "PHY_PMA_CMN_CTRL1_6,Drives cmn_refclk_rcv_out_en PMA input" "0,1"
rbitfld.long 0x00 5. "PHY_PMA_CMN_CTRL1_5,Current value of cmn_macro_suspend_ack PMA output" "0,1"
newline
rbitfld.long 0x00 4. "PHY_PMA_CMN_CTRL1_4,Current value of cmn_refclk_active PMA output" "0,1"
rbitfld.long 0x00 1.--3. "PHY_PMA_CMN_CTRL1_3_1,Reserved" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 0. "PHY_PMA_CMN_CTRL1_0,Current value of cmn_ready pin PMA output" "0,1"
line.long 0x04 "PHY_PMA_PLL_RAW_CTRL__PHY_PMA_SSM_STATE,PMA SSM current state register"
hexmask.long.word 0x04 18.--31. 1. "PHY_PMA_PLL_RAW_CTRL_15_2,Reserved"
bitfld.long 0x04 17. "PHY_PMA_PLL_RAW_CTRL_1,Raw SerDes PLL1 control : When set to 1 cmn_pll1_en PMA input is controlled by PHY logic" "0,1"
newline
bitfld.long 0x04 16. "PHY_PMA_PLL_RAW_CTRL_0,Raw SerDes PLL0 control : When set to 1 cmn_pll0_en PMA input is controlled by PHY logic" "0,1"
hexmask.long.byte 0x04 9.--15. 1. "PHY_PMA_SSM_STATE_15_9,Reserved"
newline
hexmask.long.word 0x04 0.--8. 1. "PHY_PMA_SSM_STATE_8_0,PMA SSM : Current state of the PMA startup state machine"
line.long 0x08 "PHY_PMA_ISO_PLL_CTRL0__PHY_PMA_ISO_CMN_CTRL,PMA common control signal isolation register"
hexmask.long.byte 0x08 24.--31. 1. "PHY_PMA_ISO_PLL_CTRL0_15_8,Reserved"
bitfld.long 0x08 23. "PHY_PMA_ISO_PLL_CTRL0_7,Drives cmn_pll1_ref_clk_sel PMA input when in PHY macro or PMA isolation mode" "0,1"
newline
bitfld.long 0x08 22. "PHY_PMA_ISO_PLL_CTRL0_6,Drives cmn_pll0_ref_clk_sel PMA input when in PHY macro or PMA isolation mode" "0,1"
bitfld.long 0x08 21. "PHY_PMA_ISO_PLL_CTRL0_5,Drives cmn_pll1_mode_sel PMA input when in PMA isolation mode" "0,1"
newline
bitfld.long 0x08 20. "PHY_PMA_ISO_PLL_CTRL0_4,Drives cmn_pll0_mode_sel PMA input when in PMA isolation mode" "0,1"
bitfld.long 0x08 19. "PHY_PMA_ISO_PLL_CTRL0_3,Drives cmn_pll1_clk_en PMA input when in PMA isolation mode" "0,1"
newline
bitfld.long 0x08 18. "PHY_PMA_ISO_PLL_CTRL0_2,Drives cmn_pll0_clk_en PMA input when in PMA isolation mode" "0,1"
bitfld.long 0x08 17. "PHY_PMA_ISO_PLL_CTRL0_1,Drives cmn_pll1_en PMA input when in PMA isolation mode" "0,1"
newline
bitfld.long 0x08 16. "PHY_PMA_ISO_PLL_CTRL0_0,Drives cmn_pll0_en PMA input when in PMA isolation mode" "0,1"
bitfld.long 0x08 15. "PHY_PMA_ISO_CMN_CTRL_15,Drives cmn_ref_clk_term_en PMA input when in PHY macro or PMA isolation modes" "0,1"
newline
bitfld.long 0x08 14. "PHY_PMA_ISO_CMN_CTRL_14,Drives cmn_ref_clk_dig_sel PMA input when in PHY macro or PMA isolation modes" "0,1"
bitfld.long 0x08 12.--13. "PHY_PMA_ISO_CMN_CTRL_13_12,Drives cmn_ref_clk_dig_div PMA input when in PHY macro or PMA isolation modes" "0,1,2,3"
newline
bitfld.long 0x08 10.--11. "PHY_PMA_ISO_CMN_CTRL_11_10,Drives cmn_ref_clk_int_mode PMA input when in PHY macro and PMA isolation modes" "0,1,2,3"
bitfld.long 0x08 8.--9. "PHY_PMA_ISO_CMN_CTRL_9_8,Drives cmn_ref_clk0_mode PMA input when in PHY macro and PMA isolation modes" "0,1,2,3"
newline
rbitfld.long 0x08 7. "PHY_PMA_ISO_CMN_CTRL_7,Current value of cmn_clock_stop_ack PMA output" "0,1"
bitfld.long 0x08 6. "PHY_PMA_ISO_CMN_CTRL_6,Drives cmn_clock_stop_req PMA input when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x08 5. "PHY_PMA_ISO_CMN_CTRL_5,Reserved" "0,1"
bitfld.long 0x08 4. "PHY_PMA_ISO_CMN_CTRL_4,Drives cmn_ref_clk0_clk_gate_en PMA input when in PMA isolation mode" "0,1"
newline
bitfld.long 0x08 3. "PHY_PMA_ISO_CMN_CTRL_3,Drives cmn_refclk_disable PMA input when in PMA isolation mode" "0,1"
bitfld.long 0x08 2. "PHY_PMA_ISO_CMN_CTRL_2,Drives cmn_macro_suspend_req PMA input when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x08 1. "PHY_PMA_ISO_CMN_CTRL_1,Reserved" "0,1"
bitfld.long 0x08 0. "PHY_PMA_ISO_CMN_CTRL_0,Drives cmn_reset_n PMA input when in PMA isolation mode" "0,1"
line.long 0x0C "PHY_PMA_ISO_PLL_CTRL1,PMA PLL control1 isolation register"
bitfld.long 0x0C 12.--15. "PHY_PMA_ISO_PLL_CTRL1_15_12,Drives cmn_pll1_clk_datart1_div PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "PHY_PMA_ISO_PLL_CTRL1_11_8,Drives cmn_pll1_clk_datart0_div PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 4.--7. "PHY_PMA_ISO_PLL_CTRL1_7_4,Drives cmn_pll0_clk_datart1_div PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "PHY_PMA_ISO_PLL_CTRL1_3_0,Drives cmn_pll0_clk_datart0_div PMA input when in PMA isolation mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xE014++0x0B
line.long 0x00 "PHY_PMA_PLL0_SM_STATE,PMA PLL0 State Machine current state register"
bitfld.long 0x00 28.--31. "PHY_PMA_PLL0_SM_STATE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "PHY_PMA_PLL0_SM_STATE_11_0,Current value of cmn_pllsm0_state[11:0]"
line.long 0x04 "PHY_PMA_PLL1_SM_STATE,PMA PLL1 State Machine current state register"
bitfld.long 0x04 12.--15. "PHY_PMA_PLL1_SM_STATE_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--11. 1. "PHY_PMA_PLL1_SM_STATE_11_0,Current value of cmn_pllsm1_state[11:0]"
line.long 0x08 "PHY_PMA_ISOLATION_CTRL,PMA Isolation control register"
bitfld.long 0x08 31. "PHY_PMA_ISOLATION_CTRL_15,PHY/PMA isolation enable (isolation_en) - When set enables isolation (PHY or PMA)" "0,1"
bitfld.long 0x08 30. "PHY_PMA_ISOLATION_CTRL_14,PHY/PMA common isolation enable (cmn_isolation_en) - When in PHY Macro Isolation Mode the PHY common isolation register(s) are selected" "0,1"
newline
rbitfld.long 0x08 29. "PHY_PMA_ISOLATION_CTRL_13,Reserved" "0,1"
bitfld.long 0x08 28. "PHY_PMA_ISOLATION_CTRL_12,PHY/PMA isolation mode select (isolation_mode_sel) - When isolation_en is set this bit selects between PHY isolation mode and PMA isolation mode" "0,1"
newline
rbitfld.long 0x08 24.--27. "PHY_PMA_ISOLATION_CTRL_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x08 16.--23. 1. "PHY_PMA_ISOLATION_CTRL_7_0,PHY/PMA lane isolation enable (ln_isolation_en) - When in PHY Macro Isolation Mode the selected PHY lane(s) isolation registers are selected"
group.long 0xF000++0x23
line.long 0x00 "PHY_PMA_XCVR_LPBK__PHY_PMA_XCVR_CTRL_j,PMA transceiver control register Offset = F000h + (j * 200h); where j = 0h to 3h"
hexmask.long.byte 0x00 25.--31. 1. "PHY_PMA_XCVR_LPBK_15_9,Reserved"
bitfld.long 0x00 24. "PHY_PMA_XCVR_LPBK_8,Drives the tx_bist_hold PMA input for all lanes in the associated link (i.e. the bit associated with the master lane of the link drives all lanes in the link)" "0,1"
newline
rbitfld.long 0x00 22.--23. "PHY_PMA_XCVR_LPBK_7_6,Reserved" "0,1,2,3"
bitfld.long 0x00 21. "PHY_PMA_XCVR_LPBK_5,Drives the xcvr_lpbk_fe_parallel_en PMA input for the associated lane" "0,1"
newline
bitfld.long 0x00 20. "PHY_PMA_XCVR_LPBK_4,Drives the xcvr_lpbk_ne_parallel_en PMA input for the associated lane" "0,1"
bitfld.long 0x00 19. "PHY_PMA_XCVR_LPBK_3,Drives the xcvr_lpbk_recovered_clk_en PMA input for the associated lane" "0,1"
newline
bitfld.long 0x00 18. "PHY_PMA_XCVR_LPBK_2,Drives the xcvr_lpbk_line_en PMA input for the associated lane" "0,1"
bitfld.long 0x00 17. "PHY_PMA_XCVR_LPBK_1,Drives the xcvr_lpbk_isi_gen_en PMA input for the associated lane" "0,1"
newline
bitfld.long 0x00 16. "PHY_PMA_XCVR_LPBK_0,Drives the xcvr_lpbk_serial_en PMA input for the associated lane" "0,1"
hexmask.long.byte 0x00 9.--15. 1. "PHY_PMA_XCVR_CTRL_15_9,Reserved"
newline
bitfld.long 0x00 8. "PHY_PMA_XCVR_CTRL_8,Drives the tx_differential_invert PMA input for the associated lane" "0,1"
rbitfld.long 0x00 5.--7. "PHY_PMA_XCVR_CTRL_7_5,Reserved" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 4. "PHY_PMA_XCVR_CTRL_4,Current value of rx_cdrlf_fphl_locked PMA output for the associated lane" "0,1"
rbitfld.long 0x00 3. "PHY_PMA_XCVR_CTRL_3,Current value of rx_bist_status PMA output for the associated lane" "0,1"
newline
rbitfld.long 0x00 2. "PHY_PMA_XCVR_CTRL_2,Current value of rx_bist_err_toggle PMA output for the associated lane" "0,1"
rbitfld.long 0x00 1. "PHY_PMA_XCVR_CTRL_1,Current value of rx_bist_sync PMA output for the associated lane" "0,1"
newline
bitfld.long 0x00 0. "PHY_PMA_XCVR_CTRL_0,Drives the rx_differential_invert PMA input for the associated lane" "0,1"
line.long 0x04 "PHY_PMA_ISO_XCVR_CTRL_j,PMA Transceiver control isolation register Offset = F004h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x04 31. "PHY_PMA_ISO_XCVR_CTRL_15,Current value of xcvr_pll_clk_en_ack PMA output for the associated lane" "0,1"
rbitfld.long 0x04 30. "PHY_PMA_ISO_XCVR_CTRL_14,Reserved" "0,1"
newline
bitfld.long 0x04 29. "PHY_PMA_ISO_XCVR_CTRL_13,Drives tx_lfps_en PMA input for the associated lane when in PMA isolation mode" "0,1"
bitfld.long 0x04 28. "PHY_PMA_ISO_XCVR_CTRL_12,Drives tx_elec_idle PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
newline
rbitfld.long 0x04 27. "PHY_PMA_ISO_XCVR_CTRL_11,Current value of tx_rcv_detected PMA output for the associated lane" "0,1"
rbitfld.long 0x04 26. "PHY_PMA_ISO_XCVR_CTRL_10,Current value of tx_rcv_detect_done PMA ouptut for the associated lane" "0,1"
newline
bitfld.long 0x04 25. "PHY_PMA_ISO_XCVR_CTRL_9,Drives tx_rcv_detect_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
bitfld.long 0x04 24. "PHY_PMA_ISO_XCVR_CTRL_8,Drives xcvr_link_reset_n PMA input for the associated lane when in PMA isolation mode" "0,1"
newline
bitfld.long 0x04 23. "PHY_PMA_ISO_XCVR_CTRL_7,Drives xcvr_pll_clk_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
rbitfld.long 0x04 22. "PHY_PMA_ISO_XCVR_CTRL_6,Reserved" "0,1"
newline
bitfld.long 0x04 21. "PHY_PMA_ISO_XCVR_CTRL_5,Drives xcvr_lane_suspend PMA input for the associated lane when in PMA isolation mode" "0,1"
rbitfld.long 0x04 20. "PHY_PMA_ISO_XCVR_CTRL_4,Current value of rx_lfps_detect PMA output for the associated lane" "0,1"
newline
rbitfld.long 0x04 19. "PHY_PMA_ISO_XCVR_CTRL_3,Current value of rx_signal_detect PMA output for the associated lane" "0,1"
rbitfld.long 0x04 18. "PHY_PMA_ISO_XCVR_CTRL_2,Reserved" "0,1"
newline
bitfld.long 0x04 17. "PHY_PMA_ISO_XCVR_CTRL_1,Drives rx_termination PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
rbitfld.long 0x04 16. "PHY_PMA_ISO_XCVR_CTRL_0,Reserved" "0,1"
newline
hexmask.long.byte 0x04 8.--15. 1. "PHY_PMA_PI_POS_15_8,Current value of rx_pi_val PMA output for the associated lane"
hexmask.long.byte 0x04 0.--7. 1. "PHY_PMA_PI_POS_7_0,Current value of rx_eye_plot_pi_val PMA output for the associated lane"
line.long 0x08 "PHY_PMA_ISO_TX_LPC_HI__PHY_PMA_ISO_TX_LPC_LO_j,PMA transmitter local preset coefficient low isolation register Offset = F008h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x08 31. "PHY_PMA_ISO_TX_LPC_HI_15,Current value of tx_local_preset_coef_valid PMA output for the associated lane" "0,1"
rbitfld.long 0x08 29.--30. "PHY_PMA_ISO_TX_LPC_HI_14_13,Reserved" "0,1,2,3"
newline
bitfld.long 0x08 28. "PHY_PMA_ISO_TX_LPC_HI_12,Drives tx_get_local_preset_coef PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
bitfld.long 0x08 24.--27. "PHY_PMA_ISO_TX_LPC_HI_11_8,Drives tx_local_preset_index PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 22.--23. "PHY_PMA_ISO_TX_LPC_HI_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x08 16.--21. "PHY_PMA_ISO_TX_LPC_HI_5_0,Value of tx_local_tx_preset_coef[17:12] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x08 14.--15. "PHY_PMA_ISO_TX_LPC_LO_15_14,Reserved" "0,1,2,3"
rbitfld.long 0x08 8.--13. "PHY_PMA_ISO_TX_LPC_LO_13_8,Value of tx_local_tx_preset_coef[11:6] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x08 6.--7. "PHY_PMA_ISO_TX_LPC_LO_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x08 0.--5. "PHY_PMA_ISO_TX_LPC_LO_5_0,Value of tx_local_tx_preset_coef[5:0] PMA output for the associated lane captured upon assertion of tx_local_preset_coef_valid for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "PHY_PMA_ISO_TX_DMPH_HI__PHY_PMA_ISO_TX_DMPH_LO_j,PMA Tx de-emphasis low isolation register Offset = F00Ch + (j * 200h); where j = 0h to 3h"
hexmask.long.word 0x0C 22.--31. 1. "PHY_PMA_ISO_TX_DMPH_HI_15_6,Reserved"
bitfld.long 0x0C 16.--21. "PHY_PMA_ISO_TX_DMPH_HI_5_0,Drives tx_deemphasis [17:12] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x0C 14.--15. "PHY_PMA_ISO_TX_DMPH_LO_15_14,Reserved" "0,1,2,3"
bitfld.long 0x0C 8.--13. "PHY_PMA_ISO_TX_DMPH_LO_13_8,Drives tx_deemphasis [11:6] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x0C 6.--7. "PHY_PMA_ISO_TX_DMPH_LO_7_6,Reserved" "0,1,2,3"
bitfld.long 0x0C 0.--5. "PHY_PMA_ISO_TX_DMPH_LO_5_0,Drives tx_deemphasis [5:0] PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "PHY_PMA_ISO_TX_MGN__PHY_PMA_ISO_TX_FSLF_j,PMA Tx FS/LF isolation register Offset = F010h + (j * 200h); where j = 0h to 3h"
hexmask.long.byte 0x10 25.--31. 1. "PHY_PMA_ISO_TX_MGN_15_9,Reserved"
bitfld.long 0x10 24. "PHY_PMA_ISO_TX_MGN_8,Drives tx_low_power_swing_en PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
newline
rbitfld.long 0x10 19.--23. "PHY_PMA_ISO_TX_MGN_7_3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--18. "PHY_PMA_ISO_TX_MGN_2_0,Drives tx_vmargin PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 14.--15. "PHY_PMA_ISO_TX_FSLF_15_14,Reserved" "0,1,2,3"
rbitfld.long 0x10 8.--13. "PHY_PMA_ISO_TX_FSLF_13_8,Current value of tx_local_fs PMA ouptut for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 6.--7. "PHY_PMA_ISO_TX_FSLF_7_6,Reserved" "0,1,2,3"
rbitfld.long 0x10 0.--5. "PHY_PMA_ISO_TX_FSLF_5_0,Current value of tx_local_lf PMA ouptut for the associated lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "PHY_PMA_ISO_PWRST_CTRL__PHY_PMA_ISO_LINK_MODE_j,PMA Isolation mode control register Offset = F014h + (j * 200h); where j = 0h to 3h"
bitfld.long 0x14 31. "PHY_PMA_ISO_PWRST_CTRL_15,rx_sig_det_en_ext_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
bitfld.long 0x14 30. "PHY_PMA_ISO_PWRST_CTRL_14,tx_cmn_mode_en_ext_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
newline
rbitfld.long 0x14 24.--29. "PHY_PMA_ISO_PWRST_CTRL_13_8,Current value of xcvr_power_state_ack_ln_{nnnn} PMA output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x14 22.--23. "PHY_PMA_ISO_PWRST_CTRL_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 16.--21. "PHY_PMA_ISO_PWRST_CTRL_5_0,Drives xcvr_power_state_req_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 15. "PHY_PMA_ISO_LINK_MODE_15,tx_reset_n_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
newline
bitfld.long 0x14 14. "PHY_PMA_ISO_LINK_MODE_14,rx_reset_n_ln_{nnnn} PMA input when in PMA isolation mode" "0,1"
hexmask.long.byte 0x14 6.--13. 1. "PHY_PMA_ISO_LINK_MODE_13_6,Reserved"
newline
bitfld.long 0x14 4.--5. "PHY_PMA_ISO_LINK_MODE_5_4,Drives xcvr_standard_mode_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3"
rbitfld.long 0x14 3. "PHY_PMA_ISO_LINK_MODE_3,Reserved" "0,1"
newline
bitfld.long 0x14 0.--2. "PHY_PMA_ISO_LINK_MODE_2_0,Drives xcvr_data_width_ln_{nnnn} PMA input when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1,2,3,4,5,6,7"
line.long 0x18 "PHY_PMA_ISO_RX_EQ_CTRL_j,PMA RX equalization control isolation register Offset = F018h + (j * 200h); where j = 0h to 3h"
rbitfld.long 0x18 30.--31. "PHY_PMA_ISO_RX_EQ_CTRL_15_14,Reserved" "0,1,2,3"
bitfld.long 0x18 29. "PHY_PMA_ISO_RX_EQ_CTRL_13,Drives rx_eq_training_data_valid PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
newline
bitfld.long 0x18 28. "PHY_PMA_ISO_RX_EQ_CTRL_12,Drives rx_eq_training PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
rbitfld.long 0x18 26.--27. "PHY_PMA_ISO_RX_EQ_CTRL_11_10,Reserved" "0,1,2,3"
newline
rbitfld.long 0x18 20.--25. "PHY_PMA_ISO_RX_EQ_CTRL_9_4,The value of rx_link_eval_fb_dir_change PMA output for the associated lane upon assertion of rx_eq_eval_status to PMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x18 19. "PHY_PMA_ISO_RX_EQ_CTRL_3,The value of rx_eq_eval_complete PMA output for the associated lane upon assertion of rx_eq_eval_status" "0,1"
newline
bitfld.long 0x18 18. "PHY_PMA_ISO_RX_EQ_CTRL_2,Drives rx_invalid_request PMA input for the associated lane when in PMA isolation mode" "0,1"
rbitfld.long 0x18 17. "PHY_PMA_ISO_RX_EQ_CTRL_1,Current value of rx_eq_eval_status PMA output for the associated lane" "0,1"
newline
bitfld.long 0x18 16. "PHY_PMA_ISO_RX_EQ_CTRL_0,Drives rx_eq_eval PMA input for the associated lane when in PMA isolation mode or PHY isolation mode and lane is configured for Raw SerDes mode" "0,1"
line.long 0x1C "PHY_PMA_ISO_DATA_HI__PHY_PMA_ISO_DATA_LO_j,PMA low data isolation register Offset = F01Ch + (j * 200h); where j = 0h to 3h"
hexmask.long.word 0x1C 20.--31. 1. "PHY_PMA_ISO_DATA_HI_15_4,Reserved"
bitfld.long 0x1C 16.--19. "PHY_PMA_ISO_DATA_HI_3_0,Current value of rx_rd[19:16] PMA output for the current lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "PHY_PMA_ISO_DATA_LO_15_0,Current value of rx_rd[15:0] PMA output for the current lane"
line.long 0x20 "PHY_PMA_PSM_STATE_HI__PHY_PMA_PSM_STATE_LO_j,PMA PSM current state lower register Offset = F020h + (j * 200h); where j = 0h to 3h"
bitfld.long 0x20 29.--31. "PHY_PMA_PSM_STATE_HI_15_13,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 28. "PHY_PMA_PSM_STATE_HI_12,Current value of xcvr_psm_ready for the associated lane" "0,1"
newline
bitfld.long 0x20 26.--27. "PHY_PMA_PSM_STATE_HI_11_10,Reserved" "0,1,2,3"
hexmask.long.word 0x20 16.--25. 1. "PHY_PMA_PSM_STATE_HI_9_0,Current value of xcvr_psm_state[25:16] for the associated lane - PMA power state machine state"
newline
hexmask.long.word 0x20 0.--15. 1. "PHY_PMA_PSM_STATE_LO_15_0,Current value of xcvr_psm_state[15:0] for the associated lane - PMA power state machine state"
tree.end
tree.end
tree "AASRC"
tree "AASRC0_CFG"
base ad:0x2D00000
rgroup.long 0x00++0x03
line.long 0x00 "AASRC_PID,"
group.long 0x10++0x03
line.long 0x00 "AASRC_SYSCONFIG,"
bitfld.long 0x00 1. "DATA_FORMAT_DISABLE,If this bit is enabled data formatting needs to be done outside" "0,1"
newline
bitfld.long 0x00 0. "SOFTRESET,Write 1'b1 for reset assertion and 1'b1 for reset deassertion" "0,1"
group.long 0x20++0x53
line.long 0x00 "AASRC_IRQEOI,The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
abitfld.long 0x00 0.--7. "EOI_VECTOR,Number associated with the ipgenericirq for intr output" "0x00=Write to input_intr,0x01=Write to output_intr,0x02=Write to ingroup_intr,0x03=Write to outgroup_intr,0x04=Write to error_intr Any other write value.."
line.long 0x04 "AASRC_IFIRQRAW,"
bitfld.long 0x04 15. "CHANNEL_15_INPUT_FIFO_THRESHOLD_RAW,Channel 15 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 14. "CHANNEL_14_INPUT_FIFO_THRESHOLD_RAW,Channel 14 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 13. "CHANNEL_13_INPUT_FIFO_THRESHOLD_RAW,Channel 13 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 12. "CHANNEL_12_INPUT_FIFO_THRESHOLD_RAW,Channel 12 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 11. "CHANNEL_11_INPUT_FIFO_THRESHOLD_RAW,Channel 11 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 10. "CHANNEL_10_INPUT_FIFO_THRESHOLD_RAW,Channel 10 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 9. "CHANNEL_9_INPUT_FIFO_THRESHOLD_RAW,Channel 9 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 8. "CHANNEL_8_INPUT_FIFO_THRESHOLD_RAW,Channel 8 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 7. "CHANNEL_7_INPUT_FIFO_THRESHOLD_RAW,Channel 7 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 6. "CHANNEL_6_INPUT_FIFO_THRESHOLD_RAW,Channel 6 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 5. "CHANNEL_5_INPUT_FIFO_THRESHOLD_RAW,Channel 5 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 4. "CHANNEL_4_INPUT_FIFO_THRESHOLD_RAW,Channel 4 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 3. "CHANNEL_3_INPUT_FIFO_THRESHOLD_RAW,Channel 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 2. "CHANNEL_2_INPUT_FIFO_THRESHOLD_RAW,Channel 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 1. "CHANNEL_1_INPUT_FIFO_THRESHOLD_RAW,Channel 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x04 0. "CHANNEL_0_INPUT_FIFO_THRESHOLD_RAW,Channel 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x08 "AASRC_IFIRQENSTS,"
bitfld.long 0x08 15. "CHANNEL_15_INPUT_FIFO_THRESHOLD_ENABLED,Channel 15 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 14. "CHANNEL_14_INPUT_FIFO_THRESHOLD_ENABLED,Channel 14 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 13. "CHANNEL_13_INPUT_FIFO_THRESHOLD_ENABLED,Channel 13 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 12. "CHANNEL_12_INPUT_FIFO_THRESHOLD_ENABLED,Channel 12 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 11. "CHANNEL_11_INPUT_FIFO_THRESHOLD_ENABLED,Channel 11 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 10. "CHANNEL_10_INPUT_FIFO_THRESHOLD_ENABLED,Channel 10 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 9. "CHANNEL_9_INPUT_FIFO_THRESHOLD_ENABLED,Channel 9 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 8. "CHANNEL_8_INPUT_FIFO_THRESHOLD_ENABLED,Channel 8 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 7. "CHANNEL_7_INPUT_FIFO_THRESHOLD_ENABLED,Channel 7 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 6. "CHANNEL_6_INPUT_FIFO_THRESHOLD_ENABLED,Channel 6 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 5. "CHANNEL_5_INPUT_FIFO_THRESHOLD_ENABLED,Channel 5 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 4. "CHANNEL_4_INPUT_FIFO_THRESHOLD_ENABLED,Channel 4 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 3. "CHANNEL_3_INPUT_FIFO_THRESHOLD_ENABLED,Channel 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 2. "CHANNEL_2_INPUT_FIFO_THRESHOLD_ENABLED,Channel 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 1. "CHANNEL_1_INPUT_FIFO_THRESHOLD_ENABLED,Channel 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x08 0. "CHANNEL_0_INPUT_FIFO_THRESHOLD_ENABLED,Channel 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x0C "AASRC_IFIRQENSET,"
bitfld.long 0x0C 15. "CHANNEL_15_INPUT_FIFO_THRESHOLD_ENABLE,Channel 15 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 14. "CHANNEL_14_INPUT_FIFO_THRESHOLD_ENABLE,Channel 14 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 13. "CHANNEL_13_INPUT_FIFO_THRESHOLD_ENABLE,Channel 13 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 12. "CHANNEL_12_INPUT_FIFO_THRESHOLD_ENABLE,Channel 12 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 11. "CHANNEL_11_INPUT_FIFO_THRESHOLD_ENABLE,Channel 11 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 10. "CHANNEL_10_INPUT_FIFO_THRESHOLD_ENABLE,Channel 10 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 9. "CHANNEL_9_INPUT_FIFO_THRESHOLD_ENABLE,Channel 9 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 8. "CHANNEL_8_INPUT_FIFO_THRESHOLD_ENABLE,Channel 8 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 7. "CHANNEL_7_INPUT_FIFO_THRESHOLD_ENABLE,Channel 7 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 6. "CHANNEL_6_INPUT_FIFO_THRESHOLD_ENABLE,Channel 6 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 5. "CHANNEL_5_INPUT_FIFO_THRESHOLD_ENABLE,Channel 5 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 4. "CHANNEL_4_INPUT_FIFO_THRESHOLD_ENABLE,Channel 4 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 3. "CHANNEL_3_INPUT_FIFO_THRESHOLD_ENABLE,Channel 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 2. "CHANNEL_2_INPUT_FIFO_THRESHOLD_ENABLE,Channel 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 1. "CHANNEL_1_INPUT_FIFO_THRESHOLD_ENABLE,Channel 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x0C 0. "CHANNEL_0_INPUT_FIFO_THRESHOLD_ENABLE,Channel 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x10 "AASRC_IFIRQENCLR,"
bitfld.long 0x10 15. "CHANNEL_15_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 15 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 14. "CHANNEL_14_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 14 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 13. "CHANNEL_13_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 13 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 12. "CHANNEL_12_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 12 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 11. "CHANNEL_11_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 11 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 10. "CHANNEL_10_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 10 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 9. "CHANNEL_9_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 9 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 8. "CHANNEL_8_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 8 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 7. "CHANNEL_7_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 7 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 6. "CHANNEL_6_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 6 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 5. "CHANNEL_5_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 5 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 4. "CHANNEL_4_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 4 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 3. "CHANNEL_3_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 2. "CHANNEL_2_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 1. "CHANNEL_1_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x10 0. "CHANNEL_0_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x14 "AASRC_OFIRQRAW,"
bitfld.long 0x14 15. "CHANNEL_15_OUTPUT_FIFO_THRESHOLD_RAW,Channel 15 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 14. "CHANNEL_14_OUTPUT_FIFO_THRESHOLD_RAW,Channel 14 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 13. "CHANNEL_13_OUTPUT_FIFO_THRESHOLD_RAW,Channel 13 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 12. "CHANNEL_12_OUTPUT_FIFO_THRESHOLD_RAW,Channel 12 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 11. "CHANNEL_11_OUTPUT_FIFO_THRESHOLD_RAW,Channel 11 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 10. "CHANNEL_10_OUTPUT_FIFO_THRESHOLD_RAW,Channel 10 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 9. "CHANNEL_9_OUTPUT_FIFO_THRESHOLD_RAW,Channel 9 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 8. "CHANNEL_8_OUTPUT_FIFO_THRESHOLD_RAW,Channel 8 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 7. "CHANNEL_7_OUTPUT_FIFO_THRESHOLD_RAW,Channel 7 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 6. "CHANNEL_6_OUTPUT_FIFO_THRESHOLD_RAW,Channel 6 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 5. "CHANNEL_5_OUTPUT_FIFO_THRESHOLD_RAW,Channel 5 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 4. "CHANNEL_4_OUTPUT_FIFO_THRESHOLD_RAW,Channel 4 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 3. "CHANNEL_3_OUTPUT_FIFO_THRESHOLD_RAW,Channel 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 2. "CHANNEL_2_OUTPUT_FIFO_THRESHOLD_RAW,Channel 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 1. "CHANNEL_1_OUTPUT_FIFO_THRESHOLD_RAW,Channel 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x14 0. "CHANNEL_0_OUTPUT_FIFO_THRESHOLD_RAW,Channel 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x18 "AASRC_OFIRQENSTS,"
bitfld.long 0x18 15. "CHANNEL_15_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 15 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 14. "CHANNEL_14_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 14 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 13. "CHANNEL_13_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 13 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 12. "CHANNEL_12_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 12 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 11. "CHANNEL_11_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 11 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 10. "CHANNEL_10_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 10 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 9. "CHANNEL_9_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 9 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 8. "CHANNEL_8_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 8 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 7. "CHANNEL_7_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 7 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 6. "CHANNEL_6_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 6 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 5. "CHANNEL_5_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 5 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 4. "CHANNEL_4_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 4 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 3. "CHANNEL_3_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 2. "CHANNEL_2_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 1. "CHANNEL_1_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x18 0. "CHANNEL_0_OUTPUT_FIFO_THRESHOLD_ENABLED,Channel 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x1C "AASRC_OFIRQENSET,"
bitfld.long 0x1C 15. "CHANNEL_15_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 15 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 14. "CHANNEL_14_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 14 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 13. "CHANNEL_13_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 13 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 12. "CHANNEL_12_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 12 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 11. "CHANNEL_11_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 11 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 10. "CHANNEL_10_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 10 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 9. "CHANNEL_9_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 9 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 8. "CHANNEL_8_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 8 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 7. "CHANNEL_7_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 7 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 6. "CHANNEL_6_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 6 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 5. "CHANNEL_5_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 5 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 4. "CHANNEL_4_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 4 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 3. "CHANNEL_3_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 2. "CHANNEL_2_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 1. "CHANNEL_1_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x1C 0. "CHANNEL_0_OUTPUT_FIFO_THRESHOLD_ENABLE,Channel 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x20 "AASRC_OFIRQENCLR,"
bitfld.long 0x20 15. "CHANNEL_15_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 15 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 14. "CHANNEL_14_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 14 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 13. "CHANNEL_13_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 13 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 12. "CHANNEL_12_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 12 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 11. "CHANNEL_11_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 11 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 10. "CHANNEL_10_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 10 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 9. "CHANNEL_9_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 9 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 8. "CHANNEL_8_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 8 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 7. "CHANNEL_7_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 7 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 6. "CHANNEL_6_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 6 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 5. "CHANNEL_5_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 5 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 4. "CHANNEL_4_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 4 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 3. "CHANNEL_3_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 2. "CHANNEL_2_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 1. "CHANNEL_1_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x20 0. "CHANNEL_0_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Channel 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x24 "AASRC_IGIRQRAW,"
bitfld.long 0x24 3. "GROUP_3_INPUT_FIFO_THRESHOLD_RAW,Group 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x24 2. "GROUP_2_INPUT_FIFO_THRESHOLD_RAW,Group 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x24 1. "GROUP_1_INPUT_FIFO_THRESHOLD_RAW,Group 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x24 0. "GROUP_0_INPUT_FIFO_THRESHOLD_RAW,Group 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x28 "AASRC_IGIRQENSTS,"
bitfld.long 0x28 3. "GROUP_3_INPUT_FIFO_THRESHOLD_ENABLED,Group 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x28 2. "GROUP_2_INPUT_FIFO_THRESHOLD_ENABLED,Group 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x28 1. "GROUP_1_INPUT_FIFO_THRESHOLD_ENABLED,Group 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x28 0. "GROUP_0_INPUT_FIFO_THRESHOLD_ENABLED,Group 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x2C "AASRC_IGIRQENSET,"
bitfld.long 0x2C 3. "GROUP_3_INPUT_FIFO_THRESHOLD_ENABLE,Group 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x2C 2. "GROUP_2_INPUT_FIFO_THRESHOLD_ENABLE,Group 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x2C 1. "GROUP_1_INPUT_FIFO_THRESHOLD_ENABLE,Group 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x2C 0. "GROUP_0_INPUT_FIFO_THRESHOLD_ENABLE,Group 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x30 "AASRC_IGIRQENCLR,"
bitfld.long 0x30 3. "GROUP_3_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 3 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x30 2. "GROUP_2_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 2 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x30 1. "GROUP_1_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 1 Input FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x30 0. "GROUP_0_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 0 Input FIFO Threshold Interrupt" "inactive,active"
line.long 0x34 "AASRC_OGIRQRAW,"
bitfld.long 0x34 3. "GROUP_3_OUTPUT_FIFO_THRESHOLD_RAW,Group 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x34 2. "GROUP_2_OUTPUT_FIFO_THRESHOLD_RAW,Group 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x34 1. "GROUP_1_OUTPUT_FIFO_THRESHOLD_RAW,Group 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x34 0. "GROUP_0_OUTPUT_FIFO_THRESHOLD_RAW,Group 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x38 "AASRC_OGIRQENSTS,"
bitfld.long 0x38 3. "GROUP_3_OUTPUT_FIFO_THRESHOLD_ENABLED,Group 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x38 2. "GROUP_2_OUTPUT_FIFO_THRESHOLD_ENABLED,Group 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x38 1. "GROUP_1_OUTPUT_FIFO_THRESHOLD_ENABLED,Group 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x38 0. "GROUP_0_OUTPUT_FIFO_THRESHOLD_ENABLED,Group 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x3C "AASRC_OGIRQENSET,"
bitfld.long 0x3C 3. "GROUP_3_OUTPUT_FIFO_THRESHOLD_ENABLE,Group 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x3C 2. "GROUP_2_OUTPUT_FIFO_THRESHOLD_ENABLE,Group 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x3C 1. "GROUP_1_OUTPUT_FIFO_THRESHOLD_ENABLE,Group 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x3C 0. "GROUP_0_OUTPUT_FIFO_THRESHOLD_ENABLE,Group 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x40 "AASRC_OGIRQENCLR,"
bitfld.long 0x40 3. "GROUP_3_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 3 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x40 2. "GROUP_2_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 2 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x40 1. "GROUP_1_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 1 Output FIFO Threshold Interrupt" "inactive,active"
newline
bitfld.long 0x40 0. "GROUP_0_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR,Group 0 Output FIFO Threshold Interrupt" "inactive,active"
line.long 0x44 "AASRC_ERIRQRAW,"
bitfld.long 0x44 15. "CHANNEL_15_ERROR_RAW,Channel 15 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 14. "CHANNEL_14_ERROR_RAW,Channel 14 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 13. "CHANNEL_13_ERROR_RAW,Channel 13 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 12. "CHANNEL_12_ERROR_RAW,Channel 12 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 11. "CHANNEL_11_ERROR_RAW,Channel 11 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 10. "CHANNEL_10_ERROR_RAW,Channel 10 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 9. "CHANNEL_9_ERROR_RAW,Channel 9 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 8. "CHANNEL_8_ERROR_RAW,Channel 8 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 7. "CHANNEL_7_ERROR_RAW,Channel 7 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 6. "CHANNEL_6_ERROR_RAW,Channel 6 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 5. "CHANNEL_5_ERROR_RAW,Channel 5 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 4. "CHANNEL_4_ERROR_RAW,Channel 4 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 3. "CHANNEL_3_ERROR_RAW,Channel 3 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 2. "CHANNEL_2_ERROR_RAW,Channel 2 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 1. "CHANNEL_1_ERROR_RAW,Channel 1 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
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bitfld.long 0x44 0. "CHANNEL_0_ERROR_RAW,Channel 0 FIFOs Error Interrupt Read indicates raw status" "inactive,active Writing 1 will.."
line.long 0x48 "AASRC_ERIRQENSTS,"
bitfld.long 0x48 15. "CHANNEL_15_ERROR_ENABLED,Channel 15 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 14. "CHANNEL_14_ERROR_ENABLED,Channel 14 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 13. "CHANNEL_13_ERROR_ENABLED,Channel 13 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 12. "CHANNEL_12_ERROR_ENABLED,Channel 12 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 11. "CHANNEL_11_ERROR_ENABLED,Channel 11 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 10. "CHANNEL_10_ERROR_ENABLED,Channel 10 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 9. "CHANNEL_9_ERROR_ENABLED,Channel 9 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 8. "CHANNEL_8_ERROR_ENABLED,Channel 8 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 7. "CHANNEL_7_ERROR_ENABLED,Channel 7 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 6. "CHANNEL_6_ERROR_ENABLED,Channel 6 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 5. "CHANNEL_5_ERROR_ENABLED,Channel 5 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 4. "CHANNEL_4_ERROR_ENABLED,Channel 4 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 3. "CHANNEL_3_ERROR_ENABLED,Channel 3 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 2. "CHANNEL_2_ERROR_ENABLED,Channel 2 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 1. "CHANNEL_1_ERROR_ENABLED,Channel 1 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
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bitfld.long 0x48 0. "CHANNEL_0_ERROR_ENABLED,Channel 0 FIFOs Error Interrupt Read indicates enabled status" "inactive,active Writing 1 will.."
line.long 0x4C "AASRC_ERIRQENSET,"
bitfld.long 0x4C 15. "CHANNEL_15_ERROR_ENABLE,Channel 15 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 14. "CHANNEL_14_ERROR_ENABLE,Channel 14 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 13. "CHANNEL_13_ERROR_ENABLE,Channel 13 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 12. "CHANNEL_12_ERROR_ENABLE,Channel 12 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 11. "CHANNEL_11_ERROR_ENABLE,Channel 11 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 10. "CHANNEL_10_ERROR_ENABLE,Channel 10 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 9. "CHANNEL_9_ERROR_ENABLE,Channel 9 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 8. "CHANNEL_8_ERROR_ENABLE,Channel 8 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 7. "CHANNEL_7_ERROR_ENABLE,Channel 7 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 6. "CHANNEL_6_ERROR_ENABLE,Channel 6 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 5. "CHANNEL_5_ERROR_ENABLE,Channel 5 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 4. "CHANNEL_4_ERROR_ENABLE,Channel 4 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 3. "CHANNEL_3_ERROR_ENABLE,Channel 3 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 2. "CHANNEL_2_ERROR_ENABLE,Channel 2 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 1. "CHANNEL_1_ERROR_ENABLE,Channel 1 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x4C 0. "CHANNEL_0_ERROR_ENABLE,Channel 10 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
line.long 0x50 "AASRC_ERIRQENCLR,"
bitfld.long 0x50 15. "CHANNEL_15_ERROR_ENABLE_CLEAR,Channel 15 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 14. "CHANNEL_14_ERROR_ENABLE_CLEAR,Channel 14 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 13. "CHANNEL_13_ERROR_ENABLE_CLEAR,Channel 13 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 12. "CHANNEL_12_ERROR_ENABLE_CLEAR,Channel 12 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 11. "CHANNEL_11_ERROR_ENABLE_CLEAR,Channel 11 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 10. "CHANNEL_10_ERROR_ENABLE_CLEAR,Channel 10 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 9. "CHANNEL_9_ERROR_ENABLE_CLEAR,Channel 9 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 8. "CHANNEL_8_ERROR_ENABLE_CLEAR,Channel 8 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 7. "CHANNEL_7_ERROR_ENABLE_CLEAR,Channel 7 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 6. "CHANNEL_6_ERROR_ENABLE_CLEAR,Channel 6 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 5. "CHANNEL_5_ERROR_ENABLE_CLEAR,Channel 5 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 4. "CHANNEL_4_ERROR_ENABLE_CLEAR,Channel 4 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 3. "CHANNEL_3_ERROR_ENABLE_CLEAR,Channel 3 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 2. "CHANNEL_2_ERROR_ENABLE_CLEAR,Channel 2 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 1. "CHANNEL_1_ERROR_ENABLE_CLEAR,Channel 1 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
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bitfld.long 0x50 0. "CHANNEL_0_ERROR_ENABLE_CLEAR,Channel 0 FIFOs Error Interrupt Read indicates interrupt enable" "inactive,active Writing 1 will.."
group.long 0x100++0x0B
line.long 0x00 "AASRC_SRCFFCTRL_0,"
rbitfld.long 0x00 27. "R_CHANNEL_OUTFIFO_UNDERFLOW,This signal is set to 1 when Right Channel OUTFIFO for SRC0 is underflowed" "0,1"
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rbitfld.long 0x00 26. "L_CHANNEL_OUTFIFO_UNDERFLOW,This signal is set to 1 when Left Channel OUTFIFO for SRC0 is underflowed" "0,1"
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rbitfld.long 0x00 25. "R_CHANNEL_OUTFIFO_OVERFLOW,This signal is set to 1 when Right Channel OUTFIFO for SRC0 is overflowed" "0,1"
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rbitfld.long 0x00 24. "L_CHANNEL_OUTFIFO_OVERFLOW,This signal is set to 1 when Left Channel OUTFIFO for SRC0 is overflowed" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "OUTFIFO_THRESHOLD,This is the number of samples that must be available for the interrupt and SRC0 OUTFIFOs event to fire"
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rbitfld.long 0x00 11. "R_CHANNEL_INFIFO_UNDERFLOW,This signal is set to 1 when Right Channel INFIFO for SRC0 is underflowed" "0,1"
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rbitfld.long 0x00 10. "L_CHANNEL_INFIFO_UNDERFLOW,This signal is set to 1 when Left Channel INFIFO for SRC0 is underflowed" "0,1"
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rbitfld.long 0x00 9. "R_CHANNEL_INFIFO_OVERFLOW,This signal is set to 1 when Right Channel INFIFO for SRC0 is overflowed" "0,1"
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rbitfld.long 0x00 8. "L_CHANNEL_INFIFO_OVERFLOW,This signal is set to 1 when Left Channel INFIFO for SRC0 is overflowed" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "INFIFO_THRESHOLD,This is the number of samples that must be available for the interrupt and SRC0 INFIFOs event to fire"
line.long 0x04 "AASRC_SRCCTRL_0,"
bitfld.long 0x04 30.--31. "CHANNEL_ENABLE,Setting this enables the Channels of SRC0" "No channel enabled,Only Right Channel enabled,Only Left Channel enabled,Both channels enabled Clearing this register.."
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bitfld.long 0x04 28.--29. "OUTPUT_WORD_LENGTH,These bits select the word length for the SRC0 output data" "24 Bits (Default),20 Bits,18 Bits,16 Bits"
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bitfld.long 0x04 26.--27. "GROUP_DELAY,These bits select the interpolation filter group delay by configuring the number of samples which are pre-buffered prior to the re-sampler function" "64 Samples (Default),32 Samples,16 Samples,8 Samples"
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bitfld.long 0x04 24.--25. "DE_EMPHASIS_MODE,These bits are utilized to enable or disable the digital de-emphasis filter manually" "De-Emphasis Disabled (Default),De-Emphasis Enabled for fS = 48kHz,De-Emphasis Enabled for fS = 44.1kHz,De-Emphasis Enabled for fS = 32kHz"
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hexmask.long.byte 0x04 16.--23. 1. "ATTENUATION,These bits are utilized to configure the SRC digital output attenuation for the stream Output Attenuation (dB) = N 0.5 where N = Attenuation[7:0]DEC"
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bitfld.long 0x04 10. "DIRECT_DOWN_SAMPLE,This bit selects the mode of the decimation function either true decimation filter or direct down-sampling without filtering" "0,1"
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bitfld.long 0x04 9. "MUTE,This bit enables or disables the SRC output soft mute function" "Mute Disabled (Default),Mute enabled; output data set to all zeros"
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bitfld.long 0x04 8. "DITHER_ENABLE,This bit enables or disables the SRC filter s dithering" "Dithering Disabled (Default),Dithering enabled"
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bitfld.long 0x04 6.--7. "INPUT_WORD_LENGTH,These bits select the word length for the SRC0 input data" "24 Bits (Default),20 Bits,18 Bits,16 Bits"
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bitfld.long 0x04 3.--5. "OUTPUT_CLOCK_ZONE_SELECT,This selects the output clock zone for the stream0" "This selects the Clock Recovery loop 0,This selects the Clock Recovery loop 1,This selects the Clock Recovery loop 2,This selects the Clock Recovery loop 3,?..."
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bitfld.long 0x04 0.--2. "INPUT_CLOCK_ZONE_SELECT,This selects the input clock zone for the stream0" "This selects the Clock Recovery loop 0,This selects the Clock Recovery loop 1,This selects the Clock Recovery loop 2,This selects the Clock Recovery loop 3,?..."
line.long 0x08 "AASRC_SRCSTS_0,"
bitfld.long 0x08 16. "UPSAMPLE,This signal becomes high when Output sampling rate is greater than Input sampling ratio" "0,1"
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hexmask.long.word 0x08 0.--15. 1. "RATE_RATIO,Input to Output sampling ratio for SRC0"
group.long 0x180++0x07
line.long 0x00 "AASRC_GFFCTRL_0,"
rbitfld.long 0x00 27. "R_CHANNEL_OUTFIFO_UNDERFLOW,This signal is set to 1 when any of the Right Channel OUTFIFO for Group0 SRCs is underflowed" "0,1"
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rbitfld.long 0x00 26. "L_CHANNEL_OUTFIFO_UNDERFLOW,This signal is set to 1 when any of the Left Channel OUTFIFO for Group0 SRCs is underflowed" "0,1"
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rbitfld.long 0x00 25. "R_CHANNEL_OUTFIFO_OVERFLOW,This signal is set to 1 when any of the Right Channel OUTFIFO for Group0 SRCs is overflowed" "0,1"
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rbitfld.long 0x00 24. "L_CHANNEL_OUTFIFO_OVERFLOW,This signal is set to 1 when any of the Left Channel OUTFIFO for Group0 SRCs is overflowed" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "OUTFIFO_THRESHOLD,This is the number of samples that must be available for the interrupt and Group0 SRCs OUTFIFOs event to fire"
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rbitfld.long 0x00 11. "R_CHANNEL_INFIFO_UNDERFLOW,This signal is set to 1 when any of the Right Channel INFIFO for Group0 SRCs is underflowed" "0,1"
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rbitfld.long 0x00 10. "L_CHANNEL_INFIFO_UNDERFLOW,This signal is set to 1 when any of the Left Channel INFIFO for Group0 SRCs is underflowed" "0,1"
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rbitfld.long 0x00 9. "R_CHANNEL_INFIFO_OVERFLOW,This signal is set to 1 when any of the Right Channel INFIFO for Group0 SRCs is overflowed" "0,1"
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rbitfld.long 0x00 8. "L_CHANNEL_INFIFO_OVERFLOW,This signal is set to 1 when any of the Left Channel INFIFO for Group0 SRCs is overflowed" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "INFIFO_THRESHOLD,This is the number of samples that must be available for the interrupt and Group0 SRCs INFIFOs event to fire"
line.long 0x04 "AASRC_GSRCCTRL_0,"
bitfld.long 0x04 30.--31. "CHANNEL_ENABLE,Setting this enables the Channels of Group0 SRCs" "No channel enabled,Only Right Channel enabled,Only Left Channel enabled,Both channels enabled Clearing this register.."
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bitfld.long 0x04 28.--29. "OUTPUT_WORD_LENGTH,These bits select the word length for the Group0 SRC output data" "24 Bits (Default),20 Bits,18 Bits,16 Bits"
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bitfld.long 0x04 26.--27. "GROUP_DELAY,These bits select the interpolation filter group delay by configuring the number of samples which are pre-buffered prior to the re-sampler function" "64 Samples (Default),32 Samples,16 Samples,8 Samples"
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bitfld.long 0x04 24.--25. "DE_EMPHASIS_MODE,These bits are utilized to enable or disable the digital de-emphasis filter manually" "De-Emphasis Disabled (Default),De-Emphasis Enabled for fS = 48kHz,De-Emphasis Enabled for fS = 44.1kHz,De-Emphasis Enabled for fS = 32kHz"
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hexmask.long.byte 0x04 16.--23. 1. "ATTENUATION,These bits are utilized to configure the Group0 SRC digital output attenuation for the stream Output Attenuation (dB) = N 0.5 where N = Attenuation[7:0]DEC"
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bitfld.long 0x04 10. "DIRECT_DOWN_SAMPLE,This bit selects the mode of the decimation function either true decimation filter or direct down-sampling without filtering" "0,1"
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bitfld.long 0x04 9. "MUTE,This bit enables or disables the Group0 SRC output soft mute function" "Mute Disabled (Default),Mute enabled; output data set to all zeros"
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bitfld.long 0x04 8. "DITHER_ENABLE,This bit enables or disables the Group0 SRC filter s dithering" "Dithering Disabled (Default),Dithering enabled"
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bitfld.long 0x04 6.--7. "INPUT_WORD_LENGTH,These bits select the word length for the SRC0 input data" "24 Bits (Default),20 Bits,18 Bits,16 Bits"
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bitfld.long 0x04 3.--5. "OUTPUT_CLOCK_ZONE_SELECT,This selects the output clock zone for the Group0 SRCs" "This selects the Clock Recovery loop 0,This selects the Clock Recovery loop 1,This selects the Clock Recovery loop 2,This selects the Clock Recovery loop 3,?..."
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bitfld.long 0x04 0.--2. "INPUT_CLOCK_ZONE_SELECT,This selects the input clock zone for the Group0 SRCs" "This selects the Clock Recovery loop 0,This selects the Clock Recovery loop 1,This selects the Clock Recovery loop 2,This selects the Clock Recovery loop 3,?..."
group.long 0x200++0x57
line.long 0x00 "AASRC_ICKGENSTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x00 24.--31. 1. "STAMP_INT_LO,This is the lower 8 bits of the integer multiple of the next timestamp for the clock source"
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hexmask.long.tbyte 0x00 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the next timestamp for the clock source"
line.long 0x04 "AASRC_ICKGENSTH_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.word 0x04 0.--15. 1. "STAMP_INT_HI,This is the upper 16 bits of the integer multiple of the next timestamp for the clock source"
line.long 0x08 "AASRC_ICKGENRTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x08 24.--31. 1. "RATE_INT_LO,This is the lower 8 bits of the integer multiple of the rate for the clock source"
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hexmask.long.tbyte 0x08 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the rate for the clock source"
line.long 0x0C "AASRC_ICKGENRTH_0,The functions controlled by this register are not supported in this family of devices"
bitfld.long 0x0C 31. "INPUT_CLK_GEN_EN,This signal enables the Input Clock Generator 0" "Disable,Enable"
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hexmask.long.word 0x0C 0.--15. 1. "RATE_INT_HI,This is the lower 8 bits of the integer multiple of the rate for the clock source"
line.long 0x10 "AASRC_ICKLPRTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x10 24.--31. 1. "_0,This is the lower 8 bits of the integer multiple of the rate for the intput clock recovery loop 0"
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hexmask.long.tbyte 0x10 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the rate for the intput clock recovery loop 0"
line.long 0x14 "AASRC_ICKPRTH_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.word 0x14 0.--15. 1. "RATE_INT_HI,This is the upper 16 bits of the integer multiple of the rate for the intput clock recovery loop 0"
line.long 0x18 "AASRC_ICKZCNT_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.tbyte 0x18 0.--23. 1. "INPUT_CLOCK_ZONE_COUNT,This gives the value of free running counter at every posedge of sync signal"
line.long 0x1C "AASRC_ICKZCTRL_0,"
bitfld.long 0x1C 18. "OVERRIDE_SETTLE_VALUE,Value written to this field will be used as settle if override settle signal is set" "0,1"
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bitfld.long 0x1C 17. "OVERRIDE_SETTLE,This signal override the settle of input clock zone 0 clock recovery loop" "settle from clock recovery will be used,value written to override settle value will be.."
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hexmask.long.byte 0x1C 9.--16. 1. "LOOP_SETUP,This is the setting for input clock recovery loop for zone 0 8 h00: Fast loop 8 h40: Medium1 loop 8 h80: Medium2 loop 8 hC0: Slow loop"
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rbitfld.long 0x1C 8. "SETTLE,This signals sets to 1 when clock recovery loop is settled" "0,1"
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rbitfld.long 0x1C 4.--7. "LOOP_STATE,Loop debug State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 0.--3. "INPUT_CLOCK_ZONE_CLOCK_SOURCE_SELECT,This selects the 8x1 and 2x1 mux structure for input clock zone 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "AASRC_OCKGENSTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x20 24.--31. 1. "STAMP_INT_LO,This is the lower 8 bits of the integer multiple of the next timestamp for the clock source"
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hexmask.long.tbyte 0x20 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the next timestamp for the clock source"
line.long 0x24 "AASRC_OCKGENSTH_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.word 0x24 0.--15. 1. "STAMP_INT_HI,This is the upper 16 bits of the integer multiple of the next timestamp for the clock source"
line.long 0x28 "AASRC_OCKGENRTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x28 24.--31. 1. "RATE_INT_LO,This is the lower 8 bits of the integer multiple of the rate for the clock source"
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hexmask.long.tbyte 0x28 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the rate for the clock source"
line.long 0x2C "AASRC_OCKGENRTH_0,The functions controlled by this register are not supported in this family of devices"
bitfld.long 0x2C 31. "OUTPUT_CLOCK_GEN_EN,This signal enables the Output Clock Generator 0" "Disable,Enable"
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hexmask.long.word 0x2C 0.--15. 1. "RATE_INT_HI,This is the lower 8 bits of the integer multiple of the rate for the clock source"
line.long 0x30 "AASRC_OCKLPRTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x30 24.--31. 1. "RATE_INT_LO,This is the lower 8 bits of the integer multiple of the rate for the outtput clock recovery loop 0"
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hexmask.long.tbyte 0x30 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the rate for the outtput clock recovery loop 0"
line.long 0x34 "AASRC_OCKLPRTH_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.word 0x34 0.--15. 1. "RATE_INT_HI,This is the Upper 16 bits of the integer multiple of the rate for the outtput clock recovery loop 0"
line.long 0x38 "AASRC_OCKLPSTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x38 24.--31. 1. "STAMP_INT_LO,This is the lower 8 bits of the integer multiple of the next timestamp for the clock source"
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hexmask.long.tbyte 0x38 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the next timestamp for the clock source"
line.long 0x3C "AASRC_OCKLPSTH_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.word 0x3C 0.--15. 1. "STAMP_INT_HI,This is the upper 16 bits of the integer multiple of the next timestamp for the clock recovery loop"
line.long 0x40 "AASRC_OCKZCNT_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.tbyte 0x40 0.--23. 1. "OUTPUT_CLOCK_ZONE_COUNT,This gives the value of free running counter at every posedge of sync signal"
line.long 0x44 "AASRC_OCKZCTRL_0,"
bitfld.long 0x44 18. "OVERRIDE_SETTLE_VALUE,Value written to this field will be used as settle if override settle signal is set" "0,1"
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bitfld.long 0x44 17. "OVERRIDE_SETTLE,This signal override the settle of output clock zone 0 clock recovery loop" "settle from clock recovery will be used,value written to override settle value will be.."
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hexmask.long.byte 0x44 9.--16. 1. "LOOP_SETUP,This is the setting for input clock recovery loop for zone 0 8 h00: Fast loop 8 h40: Medium1 loop 8 h80: Medium2 loop 8 hC0: Slow loop"
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rbitfld.long 0x44 8. "SETTLE,This signals sets to 1 when clock recovery loop is settled" "0,1"
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rbitfld.long 0x44 4.--7. "LOOP_STATE,Loop debug state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x44 0.--3. "OUTPUT_CLOCK_ZONE_CLOCK_SOURCE_SELECT,This selects the 8x1 and 2x1 mux structure for output clock zone 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "AASRC_ICKLPORTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x48 24.--31. 1. "RATE_INT_LO,This is the lower 8 bits of the integer multiple of the rate for the override clock recovery loop 0"
newline
hexmask.long.tbyte 0x48 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the rate for the override clock recovery loop 0"
line.long 0x4C "AASRC_ICKLPORTH_0,The functions controlled by this register are not supported in this family of devices"
bitfld.long 0x4C 16. "OVERRIDE_RATE,This is the upper 16 bits of the integer multiple of the rate for the override clock recovery loop 0" "0,1"
newline
hexmask.long.word 0x4C 0.--15. 1. "RATE_INT_HI,This is the upper 16 bits of the integer multiple of the rate for the override clock recovery loop 0"
line.long 0x50 "AASRC_OCKLPORTL_0,The functions controlled by this register are not supported in this family of devices"
hexmask.long.byte 0x50 24.--31. 1. "RATE_INT_LO,This is the lower 8 bits of the integer multiple of the rate for the output override clock recovery loop 0"
newline
hexmask.long.tbyte 0x50 0.--23. 1. "FRACTIONAL_STAMP,This is the fractional portion of the rate for the output override clock recovery loop 0"
line.long 0x54 "AASRC_OCKLPORTH_0,The functions controlled by this register are not supported in this family of devices"
bitfld.long 0x54 16. "OVERRIDE_RATE,This is the upper 16 bits of the integer multiple of the rate for the output override clock recovery loop 0" "0,1"
newline
hexmask.long.word 0x54 0.--15. 1. "RATE_INT_HI,This is the Upper 16 bits of the integer multiple of the rate for the output override clock recovery loop 0"
group.long 0x400++0x07
line.long 0x00 "AASRC_ICKDIV,"
bitfld.long 0x00 30. "CLOCK_ZONE1_DIVIDE_EN,Clock zone 1 divider enable" "Divider logic disable,Divider logic enable"
newline
hexmask.long.word 0x00 16.--29. 1. "CLOCK_ZONE1_DIVIDE,This is the setting for input clock zone1 sync signal division value"
newline
bitfld.long 0x00 14. "CLOCK_ZONE0_DIVIDE_EN,Clock zone 0 divider enable" "Divider logic disable,Divider logic enable"
newline
hexmask.long.word 0x00 0.--13. 1. "CLOCK_ZONE0_DIVIDE,This is the setting for input clock zone0 sync signal division value"
line.long 0x04 "AASRC_OCKDIV,"
bitfld.long 0x04 30. "CLOCK_ZONE1_DIVIDE_EN,Clock zone 1 divider enable" "Divider logic disable,Divider logic enable"
newline
hexmask.long.word 0x04 16.--29. 1. "CLOCK_ZONE1_DIVIDE,This is the setting for output clock zone1 sync signal division value"
newline
bitfld.long 0x04 14. "CLOCK_ZONE0_DIVIDE_EN,Clock zone 0 divider enable" "Divider logic disable,Divider logic enable"
newline
hexmask.long.word 0x04 0.--13. 1. "CLOCK_ZONE0_DIVIDE,This is the setting for output clock zone0 sync signal division value"
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x94)++0x03
line.long 0x00 "AASRC_OGRPSEL_$1,"
bitfld.long 0x00 15. "CHANNEL_15_GROUP_ENABLE,Output Channel 15 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 14. "CHANNEL_14_GROUP_ENABLE,Output Channel 14 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 13. "CHANNEL_13_GROUP_ENABLE,Output Channel 13 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 12. "CHANNEL_12_GROUP_ENABLE,Output Channel 12 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 11. "CHANNEL_11_GROUP_ENABLE,Output Channel 11 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 10. "CHANNEL_10_GROUP_ENABLE,Output Channel 10 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 9. "CHANNEL_9_GROUP_ENABLE,Output Channel 9 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 8. "CHANNEL_8_GROUP_ENABLE,Output Channel 8 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 7. "CHANNEL_7_GROUP_ENABLE,Output Channel 7 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 6. "CHANNEL_6_GROUP_ENABLE,Output Channel 6 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 5. "CHANNEL_5_GROUP_ENABLE,Output Channel 5 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 4. "CHANNEL_4_GROUP_ENABLE,Output Channel 4 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 3. "CHANNEL_3_GROUP_ENABLE,Output Channel 3 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 2. "CHANNEL_2_GROUP_ENABLE,Output Channel 2 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 1. "CHANNEL_1_GROUP_ENABLE,Output Channel 1 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 0. "CHANNEL_0_GROUP_ENABLE,Output Channel 0 Group Enable indicates if the Output Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x74)++0x03
line.long 0x00 "AASRC_IGRPSEL_$1,"
bitfld.long 0x00 15. "CHANNEL_15_GROUP_ENABLE,Input Channel 15 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 14. "CHANNEL_14_GROUP_ENABLE,Input Channel 14 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 13. "CHANNEL_13_GROUP_ENABLE,Input Channel 13 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 12. "CHANNEL_12_GROUP_ENABLE,Input Channel 12 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 11. "CHANNEL_11_GROUP_ENABLE,Input Channel 11 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 10. "CHANNEL_10_GROUP_ENABLE,Input Channel 10 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 9. "CHANNEL_9_GROUP_ENABLE,Input Channel 9 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 8. "CHANNEL_8_GROUP_ENABLE,Input Channel 8 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 7. "CHANNEL_7_GROUP_ENABLE,Input Channel 7 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 6. "CHANNEL_6_GROUP_ENABLE,Input Channel 6 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 5. "CHANNEL_5_GROUP_ENABLE,Input Channel 5 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 4. "CHANNEL_4_GROUP_ENABLE,Input Channel 4 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 3. "CHANNEL_3_GROUP_ENABLE,Input Channel 3 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 2. "CHANNEL_2_GROUP_ENABLE,Input Channel 2 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
newline
bitfld.long 0x00 1. "CHANNEL_1_GROUP_ENABLE,Input Channel 1 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
bitfld.long 0x00 0. "CHANNEL_0_GROUP_ENABLE,Input Channel 0 Group Enable indicates if the Input Channel is part of the group0 for the group settings and interrupt event generation" "inactive,active Writing 1 will.."
repeat.end
tree.end
tree "AASRC0_DATA_R0"
base ad:0x2D10000
group.long 0x00++0x07
line.long 0x00 "AASRC_GIFDATAL_0,"
line.long 0x04 "AASRC_GIFDATAR_0,"
rgroup.long 0x80++0x07
line.long 0x00 "AASRC_GOFDATAL_0,"
line.long 0x04 "AASRC_GOFDATAR_0,"
tree.end
tree "AASRC0_DATA_R1"
base ad:0x2D20000
group.long 0x00++0x03
line.long 0x00 "AASRC_SIFDATAL_0,"
group.long 0x100++0x03
line.long 0x00 "AASRC_SIFDATAR_0,"
rgroup.long 0x1000++0x03
line.long 0x00 "AASRC_SOFDATAL_0,"
rgroup.long 0x1100++0x03
line.long 0x00 "AASRC_SOFDATAR_0,"
tree.end
tree.end
tree "ADC"
repeat 2. (list 0. 1. )(list ad:0x40200000 ad:0x40210000 )
tree "MCU_ADC$1"
base $2
group.long 0x00++0x03
line.long 0x00 "ADC_CONFIG_j,The user should write the appropriate value to this register that is required to configure the various functions of each step"
bitfld.long 0x00 27. "RANGECHECK," "0,1"
bitfld.long 0x00 26. "FIFOSEL,Sampled data will be stored in FIFO" "FIFO0,FIFO1"
newline
bitfld.long 0x00 25. "DIFF_CNTRL,DifferentialADC_CONTROL" "Single ended input SEL_INM_SWM must be 8h,Differential input"
bitfld.long 0x00 19.--22. "SEL_INP_SWC,Select source for positive ADC input (INP)" "Input..,Input..,Input..,Input..,Input..,Input..,Input..,Input..,REFN,?..."
newline
bitfld.long 0x00 15.--18. "SEL_INM_SWM,Select source for negative ADC input (INM)" "Input..,Input..,Input..,Input..,Input..,Input..,Input..,Input..,REFN,?..."
bitfld.long 0x00 2.--4. "AVERAGING,Number of samplings to average" "no average,2 samples average,4 samples average,8 samples average,16 samples average,?..."
newline
bitfld.long 0x00 0.--1. "MODE," "?,SW enabled continuous,HW synchronized one-shot,HW synchronized continuous"
group.long 0x00++0x03
line.long 0x00 "ADC_DELAY_j,Controls number of SMPL_CLK periods to sample and delay"
hexmask.long.byte 0x00 24.--31. 1. "SAMPLEDELAY,This register will control the number of SMPL_CLK cycles to sample the input signal (hold SOC high)"
hexmask.long.tbyte 0x00 0.--17. 1. "OPENDELAY,Program the number of SMPL_CLK cycles to wait after applying the step configuration registers and before sending the start of ADC conversion"
rgroup.long 0x00++0x03
line.long 0x00 "ADC_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTLADC_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20++0x13
line.long 0x00 "ADC_EOI,The End of Interrupt () Register allows the CPU to acknowledge completion of an interrupt by writing to the for interrupt sources"
bitfld.long 0x00 0. "LINENUMEOI,Software End Of Interrupt (EOI) control" "0,1"
line.long 0x04 "ADC_STATUS_RAW,The register allows the MCU_ADC0/1 interrupt sources to be manually set when writing a 1 to a specific bit"
bitfld.long 0x04 8. "OUTOFRANGE,Status raw for out of range interrupt" "0,1"
bitfld.long 0x04 7. "FIFO1UNFL,Status raw for FIFO1 under-flow interrupt" "0,1"
newline
bitfld.long 0x04 6. "FIFO1OVFL,Status raw for FIFO1 over-flow interrupt" "0,1"
bitfld.long 0x04 5. "FIFO1THRS,Status raw for FIFO1 threshold interrupt" "0,1"
newline
bitfld.long 0x04 4. "FIFO0UNFL,Status raw for FIFO0 under-flow interrupt" "0,1"
bitfld.long 0x04 3. "FIFO0OVFL,Status raw for FIFO0 over-flow interrupt" "0,1"
newline
bitfld.long 0x04 2. "FIFO0THRS,Status raw for FIFO0 threshold interrupt" "0,1"
bitfld.long 0x04 1. "ENDOFEQUENCE,Status raw for end of sequence interrupt" "0,1"
newline
bitfld.long 0x04 0. "AFE_EOC_MISSING,Status raw for missing AFE EOC interrupt" "0,1"
line.long 0x08 "ADC_STATUS,The register allows the MCU_ADC0/1 interrupt sources to be manually cleared when writing a 1 to a specific bit"
bitfld.long 0x08 8. "OUTOFRANGE,Enabled status for out of range interrupt" "0,1"
bitfld.long 0x08 7. "FIFO1UNFL,Enabled status for FIFO1 under-flow interrupt" "0,1"
newline
bitfld.long 0x08 6. "FIFO1OVFL,Enabled status for FIFO1 over-flow interrupt" "0,1"
bitfld.long 0x08 5. "FIFO1THRS,Enabled status for FIFO1 threshold interrupt" "0,1"
newline
bitfld.long 0x08 4. "FIFO0UNFL,Enabled status for FIFO0 under-flow interrupt" "0,1"
bitfld.long 0x08 3. "FIFO0OVFL,Enabled status for FIFO0 over-flow interrupt" "0,1"
newline
bitfld.long 0x08 2. "FIFO0THRS,Enabled status for FIFO0 threshold interrupt" "0,1"
bitfld.long 0x08 1. "ENDOFEQUENCE,Enabled status for end of sequence interrupt" "0,1"
newline
bitfld.long 0x08 0. "AFE_EOC_MISSING,Enable status for missing AFE EOC interrupt" "0,1"
line.long 0x0C "ADC_ENABLE_SET,The register allows the MCU_ADC0/1 interrupt sources to be manually enabled when writing a 1 to a specific bit"
bitfld.long 0x0C 8. "OUTOFRANGE,Out of range interrupt enable" "0,1"
bitfld.long 0x0C 7. "FIFO1UNFL,FIFO1 under-flow interrupt enable" "0,1"
newline
bitfld.long 0x0C 6. "FIFO1OVFL,FIFO1 over-flow interrupt enable" "0,1"
bitfld.long 0x0C 5. "FIFO1THRS,FIFO1 threshold interrupt enable" "0,1"
newline
bitfld.long 0x0C 4. "FIFO0UNFL,FIFO0 under-flow interrupt enable" "0,1"
bitfld.long 0x0C 3. "FIFO0OVFL,FIFO0 over-flow interrupt enable" "0,1"
newline
bitfld.long 0x0C 2. "FIFO0THRS,FIFO0 threshold interrupt enable" "0,1"
bitfld.long 0x0C 1. "ENDOFEQUENCE,End of sequence interrupt enable" "0,1"
newline
bitfld.long 0x0C 0. "AFE_EOC_MISSING,Missing AFE EOC interrupt enable" "0,1"
line.long 0x10 "ADC_ENABLE_CLR,The register allows the MCU_ADC0/1 interrupt sources to be manually disabled when writing a 1 to a specific bit"
bitfld.long 0x10 8. "OUTOFRANGE,Out of range interrupt disable" "0,1"
bitfld.long 0x10 7. "FIFO1UNFL,FIFO1 under-flow interrupt disable" "0,1"
newline
bitfld.long 0x10 6. "FIFO1OVFL,FIFO1 over-flow interrupt disable" "0,1"
bitfld.long 0x10 5. "FIFO1THRS,FIFO1 threshold interrupt disable" "0,1"
newline
bitfld.long 0x10 4. "FIFO0UNFL,FIFO0 under-flow interrupt disable" "0,1"
bitfld.long 0x10 3. "FIFO0OVFL,FIFO0 over-flow interrupt disable" "0,1"
newline
bitfld.long 0x10 2. "FIFO0THRS,FIFO0 threshold interrupt disable" "0,1"
bitfld.long 0x10 1. "ENDOFEQUENCE,End of sequence interrupt disable" "0,1"
newline
bitfld.long 0x10 0. "AFE_EOC_MISSING,Missing AFE EOC interrupt disable" "0,1"
group.long 0x38++0x13
line.long 0x00 "ADC_DMAENABLE_SET,The register allows the enabling of DMA requests"
bitfld.long 0x00 1. "ENABLE1,Enable DMA event to FIFO1" "0,1"
bitfld.long 0x00 0. "ENABLE0,Enable DMA event to FIFO0" "0,1"
line.long 0x04 "ADC_DMAENABLE_CLR,The register allows the disabling of DMA requests"
bitfld.long 0x04 1. "ENABLE1,Clears the enable of the DMA event to FIFO1" "DMA event disabled,DMA event enabled"
bitfld.long 0x04 0. "ENABLE0,Clears the enable of the DMA event to FIFO0" "DMA event disabled,DMA event enabled"
line.long 0x08 "ADC_CONTROL,Controls various parameters of the cotroller state"
bitfld.long 0x08 11. "HI_MID_SEL,Reference select for functionalinternal diagnostic debug mode" "VMID,REFP"
bitfld.long 0x08 10. "HI_MID_EN,Functionalinternal diagnostic debug mode" "disabled,enabled"
newline
bitfld.long 0x08 9. "HW_PREEMPT," "0,1"
bitfld.long 0x08 8. "HW_MAP," "0,1"
newline
bitfld.long 0x08 4. "PD,ADC Power Down control" "AFE is powered up,AFE is powered down (default) At default AFE is.."
bitfld.long 0x08 1. "STEP_ID_EN,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO" "Write zeros,Store the input (channel) ID tag"
newline
bitfld.long 0x08 0. "MODULE_ENABLE,ADC module enable bit" "0,1"
line.long 0x0C "ADC_SEQUENCER_STAT,SW can read this register to find out the currently scheduled step id being converted on the ADC port"
bitfld.long 0x0C 6. "MEM_INIT_DONE,ADC_STATUS of RAM initialization for ECC" "0,1"
bitfld.long 0x0C 5. "FSM_BUSY,ADC_STATUS of FSM" "Idle,Conversion.."
newline
bitfld.long 0x0C 0.--4. "STEP_IDLE," "Fh = Corresponds to..,Step 16,?..."
line.long 0x10 "ADC_RANGE,This feature requires the check interrupt bit to be enabled first"
hexmask.long.word 0x10 16.--27. 1. "HIRANGE,Sampled ADC data is compared to this value"
hexmask.long.word 0x10 0.--11. 1. "LOWRANGE,Sampled ADC data is compared to this value"
group.long 0x50++0x07
line.long 0x00 "ADC_MISC,Spare inputs of the AFE are driven by this register. spare outputs from the AFE are read"
rbitfld.long 0x00 8.--11. "AFE_SPARE_OUT,Connected to AFE Spare Output pins reserved in normal operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "AFE_SPARE_IN,Connected to AFE Spare Input pins reserved in normal operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ADC_STEPENABLE,Contains the enable bit for each step in the sequencer"
bitfld.long 0x04 16. "STEP16,Enable step 16" "0,1"
bitfld.long 0x04 15. "STEP15,Enable step 15" "0,1"
newline
bitfld.long 0x04 14. "STEP14,Enable step 14" "0,1"
bitfld.long 0x04 13. "STEP13,Enable step 13" "0,1"
newline
bitfld.long 0x04 12. "STEP12,Enable step 12" "0,1"
bitfld.long 0x04 11. "STEP11,Enable step 11" "0,1"
newline
bitfld.long 0x04 10. "STEP10,Enable step 10" "0,1"
bitfld.long 0x04 9. "STEP9,Enable step 9" "0,1"
newline
bitfld.long 0x04 8. "STEP8,Enable step 8" "0,1"
bitfld.long 0x04 7. "STEP7,Enable step 7" "0,1"
newline
bitfld.long 0x04 6. "STEP6,Enable step 6" "0,1"
bitfld.long 0x04 5. "STEP5,Enable step 5" "0,1"
newline
bitfld.long 0x04 4. "STEP4,Enable step 4" "0,1"
bitfld.long 0x04 3. "STEP3,Enable step 3" "0,1"
newline
bitfld.long 0x04 2. "STEP2,Enable step 2" "0,1"
bitfld.long 0x04 1. "STEP1,Enable step 1" "0,1"
rgroup.long 0xE4++0x17
line.long 0x00 "ADC_FIFO0WC,FIFO word count"
hexmask.long.word 0x00 0.--8. 1. "NUMWDS,Number of words currently in the FIFO0"
line.long 0x04 "ADC_FIFO0THRESHOLD,FIFO threshold"
hexmask.long.byte 0x04 0.--7. 1. "THRESHOLD,Program the desired FIFO0 data sample level minus 1 to reach before generating interrupt to CPU"
line.long 0x08 "ADC_FIFO0DMAREQ,DMA request"
hexmask.long.byte 0x08 0.--7. 1. "DMAREQLEVEL,Number of words in FIFO0 before generating a DMA request"
line.long 0x0C "ADC_FIFO1WC,FIFO word count"
hexmask.long.word 0x0C 0.--8. 1. "NUMWDS,Number of words currently in the FIFO1"
line.long 0x10 "ADC_FIFO1THRESHOLD,FIFO threshold"
hexmask.long.byte 0x10 0.--7. 1. "THRESHOLD,Program the desired FIFO1 data sample level minus 1 to reach before generating interrupt to CPU"
line.long 0x14 "ADC_FIFO1DMAREQ,DMA request"
hexmask.long.byte 0x14 0.--7. 1. "DMAREQLEVEL,Number of words in FIFO1 before generating a DMA request"
rgroup.long 0x100++0x03
line.long 0x00 "ADC_FIFO0DATA,A read from this register will auto increment the FIFO read pointer"
bitfld.long 0x00 16.--19. "ADCCHANLID,Optional ID tag of input (channel) that captured the data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO0"
rgroup.long 0x200++0x03
line.long 0x00 "ADC_FIFO1DATA,A read from this register will auto increment the FIFO read pointer"
bitfld.long 0x00 16.--19. "ADCCHANLID,Optional ID tag of input (channel) that captured the data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO1"
tree.end
repeat.end
tree "MCU_ADC0_ECC"
base ad:0x40707000
rgroup.long 0x00++0x03
line.long 0x00 "ADC_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x1F
line.long 0x00 "ADC_ECC_VECTOR,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS," "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for"
line.long 0x04 "ADC_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ADC_ECC_WRAP_REV,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ADC_ECC_CTRL,ECC Control Register"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
newline
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "ADC_ECC_ERR_CTRL1,ECC Error Control1 Register"
line.long 0x14 "ADC_ECC_ERR_CTRL2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "ADC_ECC_ERR_STAT1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 10. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 9. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1"
bitfld.long 0x18 8. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1"
bitfld.long 0x18 2. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
newline
bitfld.long 0x18 1. "ECC_DED,Level Double Bit Error Status" "0,1"
bitfld.long 0x18 0. "ECC_SEC,Level Single Bit Error Status" "0,1"
line.long 0x1C "ADC_ECC_ERR_STAT2,ECC Error Status1 Register"
group.long 0x3C++0x07
line.long 0x00 "ADC_ECC_SEC_EOI_REG,Register"
bitfld.long 0x00 0. "EOI_WR," "0,1"
line.long 0x04 "ADC_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x04 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ADC_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ADC_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ADC_ECC_DED_EOI_REG,Register"
bitfld.long 0x00 0. "EOI_WR," "0,1"
line.long 0x04 "ADC_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x04 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ADC_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ADC_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1"
tree.end
tree "MCU_ADC1_ECC"
base ad:0x40708000
rgroup.long 0x00++0x03
line.long 0x00 "ADC_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x1F
line.long 0x00 "ADC_ECC_VECTOR,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS," "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for"
line.long 0x04 "ADC_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ADC_ECC_WRAP_REV,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ADC_ECC_CTRL,ECC Control Register"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
newline
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "ADC_ECC_ERR_CTRL1,ECC Error Control1 Register"
line.long 0x14 "ADC_ECC_ERR_CTRL2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "ADC_ECC_ERR_STAT1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 10. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 9. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1"
bitfld.long 0x18 8. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1"
bitfld.long 0x18 2. "ECC_OTHER,Successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
newline
bitfld.long 0x18 1. "ECC_DED,Level Double Bit Error Status" "0,1"
bitfld.long 0x18 0. "ECC_SEC,Level Single Bit Error Status" "0,1"
line.long 0x1C "ADC_ECC_ERR_STAT2,ECC Error Status1 Register"
group.long 0x3C++0x07
line.long 0x00 "ADC_ECC_SEC_EOI_REG,Register"
bitfld.long 0x00 0. "EOI_WR," "0,1"
line.long 0x04 "ADC_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x04 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ADC_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ADC_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ADC_ECC_DED_EOI_REG,Register"
bitfld.long 0x00 0. "EOI_WR," "0,1"
line.long 0x04 "ADC_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 1. "RAM1_PEND,Interrupt Pending Status for ram1_pend" "0,1"
bitfld.long 0x04 0. "RAM0_PEND,Interrupt Pending Status for ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ADC_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_SET,Interrupt Enable Set Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_SET,Interrupt Enable Set Register for ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ADC_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "RAM1_ENABLE_CLR,Interrupt Enable Clear Register for ram1_pend" "0,1"
bitfld.long 0x00 0. "RAM0_ENABLE_CLR,Interrupt Enable Clear Register for ram0_pend" "0,1"
tree.end
tree "MCU_ADC0_FIFO"
base ad:0x40208000
repeat 2. (list 0. 1. )(list 0x00 0x100 )
rgroup.long ($2+0x100)++0x03
line.long 0x00 "ADC_DATA$1,DMA sample FIFO"
bitfld.long 0x00 16.--19. "ADCCHANLID,Optional ID tag of input (channel) that captured the data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO0"
repeat.end
tree.end
tree "MCU_ADC1_FIFO"
base ad:0x40218000
repeat 2. (list 0. 1. )(list 0x00 0x100 )
rgroup.long ($2+0x100)++0x03
line.long 0x00 "ADC_DATA$1,DMA sample FIFO"
bitfld.long 0x00 16.--19. "ADCCHANLID,Optional ID tag of input (channel) that captured the data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "ADCDATA,Sampled ADC converted data value stored in FIFO0"
repeat.end
tree.end
tree.end
tree "ATL"
tree "ATL0_REG"
base ad:0x31F0000
rgroup.long 0x00++0x03
line.long 0x00 "ATL_REVISION,Return to"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x200++0x0B
line.long 0x00 "ATL0_PPMR,Return to"
bitfld.long 0x00 15. "PPM_SD," "0,1"
hexmask.long.word 0x00 0.--8. 1. "PPM_SET,This is"
line.long 0x04 "ATL0_BBSR,Return to"
hexmask.long.word 0x04 0.--15. 1. "SMP_CNT,This is"
line.long 0x08 "ATL0_ATLCR,Return to"
bitfld.long 0x08 5. "CLK_DIV_SEL," "0,1"
bitfld.long 0x08 0.--4. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x210++0x0F
line.long 0x00 "ATL0_SWEN,Return to"
bitfld.long 0x00 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL0_BWSMUX,Return to"
bitfld.long 0x04 0.--3. "SELECT,BWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ATL0_AWSMUX,Return to"
bitfld.long 0x08 0.--3. "SELECT,AWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ATL0_PCLKMUX,Return to"
bitfld.long 0x0C 0. "SELECT,ATL" "0,1"
group.long 0x280++0x0B
line.long 0x00 "ATL1_PPMR,Return to"
bitfld.long 0x00 15. "PPM_SD," "0,1"
hexmask.long.word 0x00 0.--8. 1. "PPM_SET,This is"
line.long 0x04 "ATL1_BBSR,Return to"
hexmask.long.word 0x04 0.--15. 1. "SMP_CNT,This is"
line.long 0x08 "ATL1_ATLCR,Return to"
bitfld.long 0x08 5. "CLK_DIV_SEL," "0,1"
bitfld.long 0x08 0.--4. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x290++0x0F
line.long 0x00 "ATL1_SWEN,Return to"
bitfld.long 0x00 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL1_BWSMUX,Return to"
bitfld.long 0x04 0.--3. "SELECT,BWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ATL1_AWSMUX,Return to"
bitfld.long 0x08 0.--3. "SELECT,AWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ATL1_PCLKMUX,Return to"
bitfld.long 0x0C 0. "SELECT,Non-functional" "0,1"
group.long 0x300++0x0B
line.long 0x00 "ATL2_PPMR,Return to"
bitfld.long 0x00 15. "PPM_SD," "0,1"
hexmask.long.word 0x00 0.--8. 1. "PPM_SET,This is"
line.long 0x04 "ATL2_BBSR,Return to"
hexmask.long.word 0x04 0.--15. 1. "SMP_CNT,This is"
line.long 0x08 "ATL2_ATLCR,Return to"
bitfld.long 0x08 5. "CLK_DIV_SEL," "0,1"
bitfld.long 0x08 0.--4. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x310++0x0F
line.long 0x00 "ATL2_SWEN,Return to"
bitfld.long 0x00 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL2_BWSMUX,Return to"
bitfld.long 0x04 0.--3. "SELECT,BWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ATL2_AWSMUX,Return to"
bitfld.long 0x08 0.--3. "SELECT,AWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ATL2_PCLKMUX,Return to"
bitfld.long 0x0C 0. "SELECT,Non-functional" "0,1"
group.long 0x380++0x0B
line.long 0x00 "ATL3_PPMR,Return to"
bitfld.long 0x00 15. "PPM_SD," "0,1"
hexmask.long.word 0x00 0.--8. 1. "PPM_SET,This is"
line.long 0x04 "ATL3_BBSR,Return to"
hexmask.long.word 0x04 0.--15. 1. "SMP_CNT,This is"
line.long 0x08 "ATL3_ATLCR,Return to"
bitfld.long 0x08 5. "CLK_DIV_SEL," "0,1"
bitfld.long 0x08 0.--4. "INT_DIV,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x390++0x0F
line.long 0x00 "ATL3_SWEN,Return to"
bitfld.long 0x00 0. "ENABLE,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL3_BWSMUX,Return to"
bitfld.long 0x04 0.--3. "SELECT,BWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ATL3_AWSMUX,Return to"
bitfld.long 0x08 0.--3. "SELECT,AWS input select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ATL3_PCLKMUX,Return to"
bitfld.long 0x0C 0. "SELECT,Non-functional" "0,1"
tree.end
tree.end
tree "C66x_DSP_Subsystem"
tree "C66_COREPAC_C66_RATCFG"
base ad:0x7FF0000
rgroup.long 0x00++0x07
line.long 0x00 "C66_RAT_PID,This register contains the major and minor revisions for the module"
line.long 0x04 "C66_RAT_CONFIG,This register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "C66_RAT_CTRL_j,This region controls the size and the enable for a region"
bitfld.long 0x00 31. "EN,Enable for the region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the region in address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "C66_RAT_BASE_j,This register is used for the base address for a region"
line.long 0x08 "C66_RAT_TRANS_L_j,This register contains the translated lower address bits for a region"
line.long 0x0C "C66_RAT_TRANS_U_j,This register contains the translated upper address bits for a region"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated upper address bits for the region"
group.long 0x804++0x03
line.long 0x00 "C66_RAT_DESTINATION_ID,This register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
group.long 0x820++0x1B
line.long 0x00 "C66_RAT_EXCEPTION_LOGGING_CONTROL,This register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "C66_RAT_EXCEPTION_LOGGING_HEADER0,This register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "C66_RAT_EXCEPTION_LOGGING_HEADER1,This register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "C66_RAT_EXCEPTION_LOGGING_DATA0,This register contains the first word of the data"
line.long 0x10 "C66_RAT_EXCEPTION_LOGGING_DATA1,This register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "C66_RAT_EXCEPTION_LOGGING_DATA2,This register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "C66_RAT_EXCEPTION_LOGGING_DATA3,This register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "C66_RAT_EXCEPTION_PEND_SET,This register allows to set the exception pending signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pending signal" "0,1"
line.long 0x04 "C66_RAT_EXCEPTION_PEND_CLEAR,This register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pending signal" "0,1"
line.long 0x08 "C66_RAT_EXCEPTION_ENABLE_SET,This register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "C66_RAT_EXCEPTION_ENABLE_CLEAR,This register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "C66_RAT_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI value"
tree.end
tree.end
tree "C71SS_ECC_AGGR"
tree "COMPUTE_CLUSTER0_C71SS0_ECC_AGGR"
base ad:0x4D20050000
rgroup.long 0x00++0x03
line.long 0x00 "C71SS_ECC_REV,IP revision register"
group.long 0x08++0x07
line.long 0x00 "C71SS_ECC_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "C71SS_ECC_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "C71SS_ECC_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "C71SS_ECC_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 18. "PMC_BUSECC_PEND,Interrupt pending status for PMC_BUSECC_PEND" "0,1"
newline
bitfld.long 0x04 17. "SE_1_BUSECC_PEND,Interrupt pending status for SE_1_BUSECC_PEND" "0,1"
newline
bitfld.long 0x04 16. "SE_0_BUSECC_PEND,Interrupt pending status for SE_0_BUSECC_PEND" "0,1"
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bitfld.long 0x04 15. "BUSECC_TAGRAM_DMC_PEND,Interrupt pending status for BUSECC_TAGRAM_DMC_PEND" "0,1"
newline
bitfld.long 0x04 14. "BUSECC_DMC_PEND,Interrupt pending status for BUSECC_DMC_PEND" "0,1"
newline
bitfld.long 0x04 13. "BUSECC_PIPE3_P2_PEND,Interrupt pending status for BUSECC_PIPE3_P2_PEND" "0,1"
newline
bitfld.long 0x04 12. "BUSECC_PIPE3_DP_PEND,Interrupt pending status for BUSECC_PIPE3_DP_PEND" "0,1"
newline
bitfld.long 0x04 11. "BUSECC_PIPE2_P2_PEND,Interrupt pending status for BUSECC_PIPE2_P2_PEND" "0,1"
newline
bitfld.long 0x04 10. "BUSECC_PIPE2_DP_PEND,Interrupt pending status for BUSECC_PIPE2_DP_PEND" "0,1"
newline
bitfld.long 0x04 9. "BUSECC_PIPE1_P2_PEND,Interrupt pending status for BUSECC_PIPE1_P2_PEND" "0,1"
newline
bitfld.long 0x04 8. "BUSECC_PIPE1_DP_PEND,Interrupt pending status for BUSECC_PIPE1_DP_PEND" "0,1"
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bitfld.long 0x04 7. "BUSECC_PIPE0_P2_PEND,Interrupt pending status for BUSECC_PIPE0_P2_PEND" "0,1"
newline
bitfld.long 0x04 6. "BUSECC_PIPE0_DP_PEND,Interrupt pending status for BUSECC_PIPE0_DP_PEND" "0,1"
newline
bitfld.long 0x04 5. "DMSC_FW_CBASS_BUSECC_DUMMY1_PEND,Interrupt pending status for DMSC_FW_CBASS_BUSECC_DUMMY1_PEND" "0,1"
newline
bitfld.long 0x04 4. "DMSC_FW_CBASS_BUSECC_DUMMY0_PEND,Interrupt pending status for DMSC_FW_CBASS_BUSECC_DUMMY0_PEND" "0,1"
newline
bitfld.long 0x04 3. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt pending status for.." "0,1"
newline
bitfld.long 0x04 2. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt pending status for.." "0,1"
newline
bitfld.long 0x04 1. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt pending status for.." "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR_COREPAC_PEND,Interrupt pending status for EDC_CTRL_ECCAGGR_COREPAC_PEND" "0,1"
group.long 0x80++0x03
line.long 0x00 "C71SS_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0"
bitfld.long 0x00 18. "PMC_BUSECC_ENABLE_SET,Interrupt enable set for PMC_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 17. "SE_1_BUSECC_ENABLE_SET,Interrupt enable set for SE_1_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 16. "SE_0_BUSECC_ENABLE_SET,Interrupt enable set for SE_0_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 15. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt enable set for BUSECC_TAGRAM_DMC_PEND" "0,1"
newline
bitfld.long 0x00 14. "BUSECC_DMC_ENABLE_SET,Interrupt enable set for BUSECC_DMC_PEND" "0,1"
newline
bitfld.long 0x00 13. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE3_P2_PEND" "0,1"
newline
bitfld.long 0x00 12. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE3_DP_PEND" "0,1"
newline
bitfld.long 0x00 11. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE2_P2_PEND" "0,1"
newline
bitfld.long 0x00 10. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE2_DP_PEND" "0,1"
newline
bitfld.long 0x00 9. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE1_P2_PEND" "0,1"
newline
bitfld.long 0x00 8. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE1_DP_PEND" "0,1"
newline
bitfld.long 0x00 7. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE0_P2_PEND" "0,1"
newline
bitfld.long 0x00 6. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE0_DP_PEND" "0,1"
newline
bitfld.long 0x00 5. "DMSC_FW_CBASS_BUSECC_DUMMY1_ENABLE_SET,Interrupt enable set for DMSC_FW_CBASS_BUSECC_DUMMY1_PEND" "0,1"
newline
bitfld.long 0x00 4. "DMSC_FW_CBASS_BUSECC_DUMMY0_ENABLE_SET,Interrupt enable set for DMSC_FW_CBASS_BUSECC_DUMMY0_PEND" "0,1"
newline
bitfld.long 0x00 3. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt enable set for.." "0,1"
newline
bitfld.long 0x00 2. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt enable set for.." "0,1"
newline
bitfld.long 0x00 1. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for.." "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET,Interrupt enable set for EDC_CTRL_ECCAGGR_COREPAC_PEND" "0,1"
group.long 0xC0++0x03
line.long 0x00 "C71SS_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0"
bitfld.long 0x00 18. "PMC_BUSECC_ENABLE_CLR,Interrupt enable clear for PMC_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 17. "SE_1_BUSECC_ENABLE_CLR,Interrupt enable clear for SE_1_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 16. "SE_0_BUSECC_ENABLE_CLR,Interrupt enable clear for SE_0_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 15. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt enable clear for BUSECC_TAGRAM_DMC_PEND" "0,1"
newline
bitfld.long 0x00 14. "BUSECC_DMC_ENABLE_CLR,Interrupt enable clear for BUSECC_DMC_PEND" "0,1"
newline
bitfld.long 0x00 13. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE3_P2_PEND" "0,1"
newline
bitfld.long 0x00 12. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE3_DP_PEND" "0,1"
newline
bitfld.long 0x00 11. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE2_P2_PEND" "0,1"
newline
bitfld.long 0x00 10. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE2_DP_PEND" "0,1"
newline
bitfld.long 0x00 9. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE1_P2_PEND" "0,1"
newline
bitfld.long 0x00 8. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE1_DP_PEND" "0,1"
newline
bitfld.long 0x00 7. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE0_P2_PEND" "0,1"
newline
bitfld.long 0x00 6. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE0_DP_PEND" "0,1"
newline
bitfld.long 0x00 5. "DMSC_FW_CBASS_BUSECC_DUMMY1_ENABLE_CLR,Interrupt enable clear for DMSC_FW_CBASS_BUSECC_DUMMY1_PEND" "0,1"
newline
bitfld.long 0x00 4. "DMSC_FW_CBASS_BUSECC_DUMMY0_ENABLE_CLR,Interrupt enable clear for DMSC_FW_CBASS_BUSECC_DUMMY0_PEND" "0,1"
newline
bitfld.long 0x00 3. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt enable clear for.." "0,1"
newline
bitfld.long 0x00 2. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt enable clear for.." "0,1"
newline
bitfld.long 0x00 1. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for.." "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR,Interrupt enable clear for EDC_CTRL_ECCAGGR_COREPAC_PEND" "0,1"
group.long 0x13C++0x07
line.long 0x00 "C71SS_ECC_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "C71SS_ECC_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 18. "PMC_BUSECC_PEND,Interrupt pending status for PMC_BUSECC_PEND" "0,1"
newline
bitfld.long 0x04 17. "SE_1_BUSECC_PEND,Interrupt pending status for SE_1_BUSECC_PEND" "0,1"
newline
bitfld.long 0x04 16. "SE_0_BUSECC_PEND,Interrupt pending status for SE_0_BUSECC_PEND" "0,1"
newline
bitfld.long 0x04 15. "BUSECC_TAGRAM_DMC_PEND,Interrupt pending status for BUSECC_TAGRAM_DMC_PEND" "0,1"
newline
bitfld.long 0x04 14. "BUSECC_DMC_PEND,Interrupt pending status for BUSECC_DMC_PEND" "0,1"
newline
bitfld.long 0x04 13. "BUSECC_PIPE3_P2_PEND,Interrupt pending status for BUSECC_PIPE3_P2_PEND" "0,1"
newline
bitfld.long 0x04 12. "BUSECC_PIPE3_DP_PEND,Interrupt pending status for BUSECC_PIPE3_DP_PEND" "0,1"
newline
bitfld.long 0x04 11. "BUSECC_PIPE2_P2_PEND,Interrupt pending status for BUSECC_PIPE2_P2_PEND" "0,1"
newline
bitfld.long 0x04 10. "BUSECC_PIPE2_DP_PEND,Interrupt pending status for BUSECC_PIPE2_DP_PEND" "0,1"
newline
bitfld.long 0x04 9. "BUSECC_PIPE1_P2_PEND,Interrupt pending status for BUSECC_PIPE1_P2_PEND" "0,1"
newline
bitfld.long 0x04 8. "BUSECC_PIPE1_DP_PEND,Interrupt pending status for BUSECC_PIPE1_DP_PEND" "0,1"
newline
bitfld.long 0x04 7. "BUSECC_PIPE0_P2_PEND,Interrupt pending status for BUSECC_PIPE0_P2_PEND" "0,1"
newline
bitfld.long 0x04 6. "BUSECC_PIPE0_DP_PEND,Interrupt pending status for BUSECC_PIPE0_DP_PEND" "0,1"
newline
bitfld.long 0x04 5. "DMSC_FW_CBASS_BUSECC_DUMMY1_PEND,Interrupt pending status for DMSC_FW_CBASS_BUSECC_DUMMY1_PEND" "0,1"
newline
bitfld.long 0x04 4. "DMSC_FW_CBASS_BUSECC_DUMMY0_PEND,Interrupt pending status for DMSC_FW_CBASS_BUSECC_DUMMY0_PEND" "0,1"
newline
bitfld.long 0x04 3. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_PEND,Interrupt pending status for.." "0,1"
newline
bitfld.long 0x04 2. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt pending status for.." "0,1"
newline
bitfld.long 0x04 1. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_PEND,Interrupt pending status for.." "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR_COREPAC_PEND,Interrupt pending status for EDC_CTRL_ECCAGGR_COREPAC_PEND" "0,1"
group.long 0x180++0x03
line.long 0x00 "C71SS_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 18. "PMC_BUSECC_ENABLE_SET,Interrupt enable set for PMC_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 17. "SE_1_BUSECC_ENABLE_SET,Interrupt enable set for SE_1_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 16. "SE_0_BUSECC_ENABLE_SET,Interrupt enable set for SE_0_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 15. "BUSECC_TAGRAM_DMC_ENABLE_SET,Interrupt enable set for BUSECC_TAGRAM_DMC_PEND" "0,1"
newline
bitfld.long 0x00 14. "BUSECC_DMC_ENABLE_SET,Interrupt enable set for BUSECC_DMC_PEND" "0,1"
newline
bitfld.long 0x00 13. "BUSECC_PIPE3_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE3_P2_PEND" "0,1"
newline
bitfld.long 0x00 12. "BUSECC_PIPE3_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE3_DP_PEND" "0,1"
newline
bitfld.long 0x00 11. "BUSECC_PIPE2_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE2_P2_PEND" "0,1"
newline
bitfld.long 0x00 10. "BUSECC_PIPE2_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE2_DP_PEND" "0,1"
newline
bitfld.long 0x00 9. "BUSECC_PIPE1_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE1_P2_PEND" "0,1"
newline
bitfld.long 0x00 8. "BUSECC_PIPE1_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE1_DP_PEND" "0,1"
newline
bitfld.long 0x00 7. "BUSECC_PIPE0_P2_ENABLE_SET,Interrupt enable set for BUSECC_PIPE0_P2_PEND" "0,1"
newline
bitfld.long 0x00 6. "BUSECC_PIPE0_DP_ENABLE_SET,Interrupt enable set for BUSECC_PIPE0_DP_PEND" "0,1"
newline
bitfld.long 0x00 5. "DMSC_FW_CBASS_BUSECC_DUMMY1_ENABLE_SET,Interrupt enable set for DMSC_FW_CBASS_BUSECC_DUMMY1_PEND" "0,1"
newline
bitfld.long 0x00 4. "DMSC_FW_CBASS_BUSECC_DUMMY0_ENABLE_SET,Interrupt enable set for DMSC_FW_CBASS_BUSECC_DUMMY0_PEND" "0,1"
newline
bitfld.long 0x00 3. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_SET,Interrupt enable set for.." "0,1"
newline
bitfld.long 0x00 2. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt enable set for.." "0,1"
newline
bitfld.long 0x00 1. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_SET,Interrupt enable set for.." "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET,Interrupt enable set for EDC_CTRL_ECCAGGR_COREPAC_PEND" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "C71SS_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 18. "PMC_BUSECC_ENABLE_CLR,Interrupt enable clear for PMC_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 17. "SE_1_BUSECC_ENABLE_CLR,Interrupt enable clear for SE_1_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 16. "SE_0_BUSECC_ENABLE_CLR,Interrupt enable clear for SE_0_BUSECC_PEND" "0,1"
newline
bitfld.long 0x00 15. "BUSECC_TAGRAM_DMC_ENABLE_CLR,Interrupt enable clear for BUSECC_TAGRAM_DMC_PEND" "0,1"
newline
bitfld.long 0x00 14. "BUSECC_DMC_ENABLE_CLR,Interrupt enable clear for BUSECC_DMC_PEND" "0,1"
newline
bitfld.long 0x00 13. "BUSECC_PIPE3_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE3_P2_PEND" "0,1"
newline
bitfld.long 0x00 12. "BUSECC_PIPE3_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE3_DP_PEND" "0,1"
newline
bitfld.long 0x00 11. "BUSECC_PIPE2_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE2_P2_PEND" "0,1"
newline
bitfld.long 0x00 10. "BUSECC_PIPE2_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE2_DP_PEND" "0,1"
newline
bitfld.long 0x00 9. "BUSECC_PIPE1_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE1_P2_PEND" "0,1"
newline
bitfld.long 0x00 8. "BUSECC_PIPE1_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE1_DP_PEND" "0,1"
newline
bitfld.long 0x00 7. "BUSECC_PIPE0_P2_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE0_P2_PEND" "0,1"
newline
bitfld.long 0x00 6. "BUSECC_PIPE0_DP_ENABLE_CLR,Interrupt enable clear for BUSECC_PIPE0_DP_PEND" "0,1"
newline
bitfld.long 0x00 5. "DMSC_FW_CBASS_BUSECC_DUMMY1_ENABLE_CLR,Interrupt enable clear for DMSC_FW_CBASS_BUSECC_DUMMY1_PEND" "0,1"
newline
bitfld.long 0x00 4. "DMSC_FW_CBASS_BUSECC_DUMMY0_ENABLE_CLR,Interrupt enable clear for DMSC_FW_CBASS_BUSECC_DUMMY0_PEND" "0,1"
newline
bitfld.long 0x00 3. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_CBASS_INT_CLK1_CLK_BUSECC_ENABLE_CLR,Interrupt enable clear for.." "0,1"
newline
bitfld.long 0x00 2. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt enable clear for.." "0,1"
newline
bitfld.long 0x00 1. "C711_COREPAC_CFG_CBASS_CFG_CBASS_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_VBUSP_ECCAGGR_CFG_BRIDGE_BUSECC_ENABLE_CLR,Interrupt enable clear for.." "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR,Interrupt enable clear for EDC_CTRL_ECCAGGR_COREPAC_PEND" "0,1"
group.long 0x200++0x0F
line.long 0x00 "C71SS_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "C71SS_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "C71SS_ECC_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "C71SS_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "CCMR5"
tree "MCU_R5FSS0_COMPARE_CFG"
base ad:0x400F0000
group.long 0x00++0x07
line.long 0x00 "CCMSR1,This register shows the error and self-test status of the CPU output compare block"
bitfld.long 0x00 16. "CMPE1,Compare error for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 8. "STC1,Self-test complete for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 1. "STET1,Self-test error type for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 0. "STE1,Self-test error for CPU output compare diagnostic" "0,1"
line.long 0x04 "CCMKEYR1,This register is used to select the operating mode of the CPU output compare block"
bitfld.long 0x04 0.--3. "MKEY1,Mode key to select operation for CPU output compare diagnostic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x0B
line.long 0x00 "CCMSR3,This register shows the error and self-test status of the inactivity monitor block"
bitfld.long 0x00 16. "CMPE3,Compare error for inactivity monitor" "0,1"
bitfld.long 0x00 8. "STC3,Self-test complete for inactivity monitor" "0,1"
bitfld.long 0x00 1. "STET3,Self-test error type for inactivity monitor" "0,1"
bitfld.long 0x00 0. "STE3,Self-test error for inactivity monitor" "0,1"
line.long 0x04 "CCMKEYR3,This register is used to select the operating mode of the inactivity monitor block"
bitfld.long 0x04 0.--3. "MKEY3,Mode key to select operation for CPU output compare diagnostic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CCMPOLCNTRL,This register is used for polarity inversion of CPU compare signals"
hexmask.long.byte 0x08 0.--7. 1. "POL_INV,Polarity inversion"
tree.end
tree "R5FSS0_COMPARE_CFG"
base ad:0x5B00000
group.long 0x00++0x07
line.long 0x00 "CCMSR1,This register shows the error and self-test status of the CPU output compare block"
bitfld.long 0x00 16. "CMPE1,Compare error for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 8. "STC1,Self-test complete for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 1. "STET1,Self-test error type for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 0. "STE1,Self-test error for CPU output compare diagnostic" "0,1"
line.long 0x04 "CCMKEYR1,This register is used to select the operating mode of the CPU output compare block"
bitfld.long 0x04 0.--3. "MKEY1,Mode key to select operation for CPU output compare diagnostic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x0B
line.long 0x00 "CCMSR3,This register shows the error and self-test status of the inactivity monitor block"
bitfld.long 0x00 16. "CMPE3,Compare error for inactivity monitor" "0,1"
bitfld.long 0x00 8. "STC3,Self-test complete for inactivity monitor" "0,1"
bitfld.long 0x00 1. "STET3,Self-test error type for inactivity monitor" "0,1"
bitfld.long 0x00 0. "STE3,Self-test error for inactivity monitor" "0,1"
line.long 0x04 "CCMKEYR3,This register is used to select the operating mode of the inactivity monitor block"
bitfld.long 0x04 0.--3. "MKEY3,Mode key to select operation for CPU output compare diagnostic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CCMPOLCNTRL,This register is used for polarity inversion of CPU compare signals"
hexmask.long.byte 0x08 0.--7. 1. "POL_INV,Polarity inversion"
tree.end
tree "R5FSS1_COMPARE_CFG"
base ad:0x5B20000
group.long 0x00++0x07
line.long 0x00 "CCMSR1,This register shows the error and self-test status of the CPU output compare block"
bitfld.long 0x00 16. "CMPE1,Compare error for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 8. "STC1,Self-test complete for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 1. "STET1,Self-test error type for CPU output compare diagnostic" "0,1"
bitfld.long 0x00 0. "STE1,Self-test error for CPU output compare diagnostic" "0,1"
line.long 0x04 "CCMKEYR1,This register is used to select the operating mode of the CPU output compare block"
bitfld.long 0x04 0.--3. "MKEY1,Mode key to select operation for CPU output compare diagnostic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x0B
line.long 0x00 "CCMSR3,This register shows the error and self-test status of the inactivity monitor block"
bitfld.long 0x00 16. "CMPE3,Compare error for inactivity monitor" "0,1"
bitfld.long 0x00 8. "STC3,Self-test complete for inactivity monitor" "0,1"
bitfld.long 0x00 1. "STET3,Self-test error type for inactivity monitor" "0,1"
bitfld.long 0x00 0. "STE3,Self-test error for inactivity monitor" "0,1"
line.long 0x04 "CCMKEYR3,This register is used to select the operating mode of the inactivity monitor block"
bitfld.long 0x04 0.--3. "MKEY3,Mode key to select operation for CPU output compare diagnostic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CCMPOLCNTRL,This register is used for polarity inversion of CPU compare signals"
hexmask.long.byte 0x08 0.--7. 1. "POL_INV,Polarity inversion"
tree.end
tree.end
tree "CLEC"
tree "COMPUTE_CLUSTER0_CLEC_REGS"
base ad:0x78000000
rgroup.long 0x00++0x03
line.long 0x00 "CLEC_PID,Peripheral identification register"
rgroup.long 0xA000++0x03
line.long 0x00 "CLEC_EFR_k,Event flag register"
rgroup.long 0xB000++0x03
line.long 0x00 "CLEC_EDR_k,Event drop register"
group.long 0xC000++0x03
line.long 0x00 "CLEC_GELRS,Global event lock register for secure claims"
bitfld.long 0x00 0. "LOCK,Global event lock bit for secure claims" "0,1"
group.long 0xD000++0x03
line.long 0x00 "CLEC_GELRNS,Global event lock register for non-secure claims"
bitfld.long 0x00 0. "LOCK,Global event lock bit for secure claims" "0,1"
group.long 0x11000++0x03
line.long 0x00 "CLEC_MRR_j,Map and routing register"
bitfld.long 0x00 31. "S,Secure claim" "0,1"
bitfld.long 0x00 30. "ESE,Event send enable" "0,1"
rbitfld.long 0x00 25. "EVTPF,Event pending flag" "0,1"
bitfld.long 0x00 24. "IS_LVL,Indicates if input event is level (1) or pulse (0)" "0,1"
bitfld.long 0x00 16.--21. "RTMAP,Routing table map.Bit [16] controls the disable/enable of the event routing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 8.--15. 1. "EXT_EVTNUM,Encoded external event number to send when this event is triggered"
bitfld.long 0x00 0.--5. "C7X_EVTNUM,C7x event number to send when this event is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hgroup.long 0x13000++0x03
hide.long 0x00 "CLEC_ESR_j,Event send register"
group.long 0x14000++0x03
line.long 0x00 "CLEC_ECR_j,Event clear register"
bitfld.long 0x00 1. "ECR_PFLAG,Writing 1 to this bit clears associated" "0,1"
bitfld.long 0x00 0. "ECR_FLAG,Writing 1 to this bit clears event and associated" "0,1"
tree.end
tree.end
tree "Compute_Cluster"
tree "COMPUTE_CLUSTER0_DMSC_BOOT"
base ad:0x45A00000
rgroup.long 0x00++0x0B
line.long 0x00 "CC_REVISION,Compute Cluster Revision Register"
line.long 0x04 "CC_MSMC_DEF,MSMC Definition Register"
hexmask.long.byte 0x04 0.--7. 1. "NUM_COREPAC,Denotes the number of corepacs connected to compute"
line.long 0x08 "CC_GIC_CONFIG,GIC Configuration Register"
bitfld.long 0x08 12.--15. "CP1_CPU_ACTIVE,C71SS0 Cores activeBits [15-13]: ReservedBit [12]:0h - C71x DSP Core 0 is in software-transparent low-power mode such as retention1h - C71x DSP Core0 is active and available for shared SPIs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "CP0_CPU_ACTIVE,A72SS0 Cores activeBits [11-10]: ReservedBit [9]:0h - A72SS0 Core 1 is in software-transparent low-power mode such as retention1h - A72SS0 Core 1 is active and available for shared SPIsBit [8]:0h - A72SS0 Core 0 is in software-transparent.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0. "GIC_SECURE,Not used on this SoC" "0,1"
rgroup.long 0x1000++0x17
line.long 0x00 "CC_DEF_j,Compute Cluster Definition Register for MSMC port j Offset = 1000h*(j + 1); where j = 0h and 4h"
bitfld.long 0x00 24.--27. "SRAM_SIZE,SRAM size (if present in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--17. "NUM_CORES,Number of cores in" "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "COREPAC_TYPE_DSP,MSMC port 'j'"
hexmask.long.byte 0x00 0.--7. 1. "COREPAC_TYPE_ARM,MSMC port 'j'"
line.long 0x04 "CC_CP_CONFIG_j,Compute Cluster Configuration Register for MSMC port j Offset = 1004h*(j + 1); where j = 0h and 4h"
bitfld.long 0x04 31. "ENDIAN,Reset value of Endian control" "0,1"
bitfld.long 0x04 25.--28. "L2ACCESS_LAT,L2 access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 21.--24. "L2PIPELINE_LAT,L2 pipeline latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--11. "CP15DISABLE,Disable write access to some secure CP15 registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "CONFIGTE,Enable T32 exceptions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "AARCH,Arm Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CC_RST_VEC_LO_CP0_j,Core 0 Boot Vector Register (Low) for MSMC port j Offset = 1008h*(j + 1); where j = 0h and 4h"
line.long 0x0C "CC_RST_VEC_HI_CP0_j,Core 0 Boot Vector Register (High) for MSMC port j Offset = 100Ch*(j + 1); where j = 0h and 4h"
hexmask.long.tbyte 0x0C 0.--16. 1. "RESET_BASE_VECTOR_HI,High reset base vector (bits [39-34]) for Core 0 of a corepac connected to MSMC port j"
line.long 0x10 "CC_RST_VEC_LO_CP1_j,Core 1 Boot Vector Register (Low) for MSMC port j"
line.long 0x14 "CC_RST_VEC_HI_CP1_j,Core 1 Boot Vector Register (High) for MSMC port j"
hexmask.long.tbyte 0x14 0.--16. 1. "RESET_BASE_VECTOR_HI,High reset base vector (bits [39-34]) for Core 1 of a corepac connected to MSMC port j"
group.long 0x1028++0x07
line.long 0x00 "CC_PM_CONFIG_j,Power Management Configuration Register for MSMC port j"
bitfld.long 0x00 8.--11. "DBGPWRUP0,Core power upBits [11-10]: ReservedBit [9]:0h - A72SSj Core 1 is powered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "DBGL1RSTDISABLE0,Disable L1 data cache automatic invalidate on reset" "0,1"
bitfld.long 0x00 6. "CLEAR_MON0,Request to clear the external global exclusive monitor" "0,1"
bitfld.long 0x00 5. "L2_FLUSHREQ0,ARM L2 hardware flush request" "0,1"
bitfld.long 0x00 4. "BROADCAST_INNER0,Enable broadcasting of inner shareable and outer sharable transactions0h - Broadcasting" "0,1"
newline
bitfld.long 0x00 3. "CACHE_BROADCAST0,Enable Broadcasting of cache maintenance transactions0h - Broadcasting" "0,1"
bitfld.long 0x00 2. "SYS_BARR0,Disable broadcasting of" "0,1"
bitfld.long 0x00 1. "ACP_MASTER0,ACP master is inactive and is not participating in" "0,1"
bitfld.long 0x00 0. "SNOOP_IF0,Snoop interface is inactive and not participating in" "0,1"
line.long 0x04 "CC_PM_STATUS_j,Power Management Status Register for MSMC port j"
bitfld.long 0x04 14. "CLEAR_MONITOR_ACK0,Clearing of the external global exclusive monitor acknowledge" "0,1"
bitfld.long 0x04 13. "STANDBY_WFI_L20,L2 in WFI low power state indication" "0,1"
bitfld.long 0x04 12. "L2_HW_FLUSH0,L2 hardware flush complete" "0,1"
bitfld.long 0x04 8.--10. "SMPEN0,Corepac taking part in coherency indication" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "CPU3_WFE0,Reserved" "0,1"
newline
bitfld.long 0x04 6. "CPU2_WFE0,Reserved" "0,1"
bitfld.long 0x04 5. "CPU1_WFE0,CPU in WFE state" "0,1"
bitfld.long 0x04 4. "CPU0_WFE0,CPU in WFE state" "0,1"
bitfld.long 0x04 3. "CPU3_WFI0,Reserved" "0,1"
bitfld.long 0x04 2. "CPU2_WFI0,Reserved" "0,1"
newline
bitfld.long 0x04 1. "CPU1_WFI0,CPU in WFI state" "0,1"
bitfld.long 0x04 0. "CPU0_WFI0,CPU in WFI state" "0,1"
tree.end
tree.end
tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR0"
tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR0"
base ad:0x4D20000000
rgroup.long 0x00++0x03
line.long 0x00 "MSMC_WRAP_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "MSMC_WRAP_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSMC_WRAP_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSMC_WRAP_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x13
line.long 0x00 "MSMC_WRAP_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu1_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 30. "CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu1_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 28. "CPU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 27. "EMIF0_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_mst_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x04 26. "EMIF0_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_slv_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x04 25. "DRU1_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 24. "DRU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 23. "DRU1_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 22. "DRU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 21. "POSTARB_PIPE_CFG_BUSECC_PEND,Interrupt Pending Status for postarb_pipe_cfg_busecc_pend" "0,1"
newline
bitfld.long 0x04 20. "MSMC_MMR_BUSECC_PEND,Interrupt Pending Status for msmc_mmr_busecc_pend" "0,1"
newline
bitfld.long 0x04 19. "DRU_RD_BUF_EDC_PEND,Interrupt Pending Status for dru_rd_buf_edc_pend" "0,1"
newline
bitfld.long 0x04 18. "DRU_QUEUE_EDC_PEND,Interrupt Pending Status for dru_queue_edc_pend" "0,1"
newline
bitfld.long 0x04 17. "DRU_ENG_EDC_PEND,Interrupt Pending Status for dru_eng_edc_pend" "0,1"
newline
bitfld.long 0x04 16. "DRU_ATTR_EDC_DUMMY_PEND,Interrupt Pending Status for dru_attr_edc_dummy_pend" "0,1"
newline
bitfld.long 0x04 15. "DRU_1_EDC_PEND,Interrupt Pending Status for dru_1_edc_pend" "0,1"
newline
bitfld.long 0x04 14. "DRU_0_EDC_PEND,Interrupt Pending Status for dru_0_edc_pend" "0,1"
newline
bitfld.long 0x04 13. "DRU_PSI_EDC_PEND,Interrupt Pending Status for dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x04 12. "DRU_CBASS_SLV_BRDG_ECC_EDC_PEND,Interrupt Pending Status for dru_cbass_slv_brdg_ecc_edc_pend" "0,1"
newline
bitfld.long 0x04 11. "DRU_CBASS_SCR_EDC_PEND,Interrupt Pending Status for dru_cbass_scr_edc_pend" "0,1"
newline
bitfld.long 0x04 10. "DRU_CBASS_MMR_FW_CH_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_fw_ch_edc_pend" "0,1"
newline
bitfld.long 0x04 9. "DRU_CBASS_MMR_FW_CH_BR_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_fw_ch_br_edc_pend" "0,1"
newline
bitfld.long 0x04 8. "DRU_CBASS_MMR_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_edc_pend" "0,1"
newline
bitfld.long 0x04 7. "DRU_CBASS_MMR_CFG_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_cfg_edc_pend" "0,1"
newline
bitfld.long 0x04 6. "DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_PEND,Interrupt Pending Status for dru_cbass_mmr_bridge_edc_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "DRU_CBASS_MMR_BRDG_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_brdg_edc_pend" "0,1"
newline
bitfld.long 0x04 4. "DRU_CBASS_MMR_BRDG_CFG_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_brdg_cfg_edc_pend" "0,1"
newline
bitfld.long 0x04 3. "DRU_CBASS_EDC_CTRL_PEND,Interrupt Pending Status for dru_cbass_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x04 2. "DRU_CBASS_DMSC_SLV_BRDG_EDC_PEND,Interrupt Pending Status for dru_cbass_dmsc_slv_brdg_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "DRU_CBASS_DMSC_SCR_EDC_PEND,Interrupt Pending Status for dru_cbass_dmsc_scr_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR0_PEND,Interrupt Pending Status for edc_ctrl_eccaggr0_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_SEC_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 31. "EN_MSMC_P3_BUSECC_DUMMY_DATA_PEND,Interrupt Pending Status for en_msmc_p3_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x08 30. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 29. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 28. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 27. "EN_MSMC_P2_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 26. "EN_MSMC_P2_BUSECC_DUMMY_DATA_PEND,Interrupt Pending Status for en_msmc_p2_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x08 25. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 24. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 23. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 22. "EN_MSMC_P1_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 21. "EN_MSMC_P1_BUSECC_DUMMY_DATA_PEND,Interrupt Pending Status for en_msmc_p1_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x08 20. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 19. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 17. "EN_MSMC_P0_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_busecc_pend" "0,1"
newline
bitfld.long 0x08 16. "EN_MSMC_P0_BUSECC_DATA_PEND,Interrupt Pending Status for en_msmc_p0_busecc_data_pend" "0,1"
newline
bitfld.long 0x08 15. "CPU9_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 14. "CPU9_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 13. "CPU8_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 12. "CPU8_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 11. "CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu7_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 10. "CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu7_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 9. "CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu6_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 8. "CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu6_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 7. "CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu5_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 6. "CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu5_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 5. "CPU4_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "CPU4_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 3. "CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu3_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 2. "CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu3_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu2_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu2_slv_local_arb_busecc_dummy_pend" "0,1"
line.long 0x0C "MSMC_WRAP_ECC_SEC_STATUS_REG2,Interrupt Status Register 2"
bitfld.long 0x0C 31. "RMW3_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw3_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 30. "RMW3_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw3_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 29. "RMW3_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 28. "RMW3_BUSECC_PEND,Interrupt Pending Status for rmw3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 27. "DATARAM_BANK2_BUSECC_PEND,Interrupt Pending Status for dataram_bank2_busecc_pend" "0,1"
newline
bitfld.long 0x0C 26. "SRAM2_BUSECC_PEND,Interrupt Pending Status for sram2_busecc_pend" "0,1"
newline
bitfld.long 0x0C 25. "RMW2_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 24. "RMW2_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw2_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x0C 23. "RMW2_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw2_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 22. "RMW2_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw2_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 21. "RMW2_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 20. "RMW2_BUSECC_PEND,Interrupt Pending Status for rmw2_busecc_pend" "0,1"
newline
bitfld.long 0x0C 19. "DATARAM_BANK1_BUSECC_PEND,Interrupt Pending Status for dataram_bank1_busecc_pend" "0,1"
newline
bitfld.long 0x0C 18. "SRAM1_BUSECC_PEND,Interrupt Pending Status for sram1_busecc_pend" "0,1"
newline
bitfld.long 0x0C 17. "RMW1_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 16. "RMW1_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw1_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x0C 15. "RMW1_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw1_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 14. "RMW1_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw1_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 13. "RMW1_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 12. "RMW1_BUSECC_PEND,Interrupt Pending Status for rmw1_busecc_pend" "0,1"
newline
bitfld.long 0x0C 11. "DATARAM_BANK0_BUSECC_PEND,Interrupt Pending Status for dataram_bank0_busecc_pend" "0,1"
newline
bitfld.long 0x0C 10. "SRAM0_BUSECC_PEND,Interrupt Pending Status for sram0_busecc_pend" "0,1"
newline
bitfld.long 0x0C 9. "RMW0_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 8. "RMW0_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw0_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x0C 7. "RMW0_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw0_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 6. "RMW0_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw0_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 5. "RMW0_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 4. "RMW0_BUSECC_PEND,Interrupt Pending Status for rmw0_busecc_pend" "0,1"
newline
bitfld.long 0x0C 3. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 2. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 0. "EN_MSMC_P3_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_busecc_dummy_pend" "0,1"
line.long 0x10 "MSMC_WRAP_ECC_SEC_STATUS_REG3,Interrupt Status Register 3"
bitfld.long 0x10 11. "CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for clec_clec_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x10 10. "EMIF_0_VSAFE_SI_PEND,Interrupt Pending Status for emif_0_vsafe_si_pend" "0,1"
newline
bitfld.long 0x10 9. "VBUSP_CFG_DSP4_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dsp4_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x10 8. "EMIF1_MST_PIPE_BUSECC_DUMMY_PEND,Interrupt Pending Status for emif1_mst_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x10 7. "EMIF1_SLV_PIPE_BUSECC_DUMMY_PEND,Interrupt Pending Status for emif1_slv_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x10 6. "VBUSP_CFG_ECC_AGGR0_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr0_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x10 5. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr0_p2p_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x10 4. "CLEC_SRAM_RAMECC_PEND,Interrupt Pending Status for clec_sram_ramecc_pend" "0,1"
newline
bitfld.long 0x10 3. "DATARAM_BANK3_BUSECC_PEND,Interrupt Pending Status for dataram_bank3_busecc_pend" "0,1"
newline
bitfld.long 0x10 2. "SRAM3_BUSECC_PEND,Interrupt Pending Status for sram3_busecc_pend" "0,1"
newline
bitfld.long 0x10 1. "RMW3_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x10 0. "RMW3_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw3_rmw_tag_update_busecc_pend" "0,1"
group.long 0x80++0x0F
line.long 0x00 "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu1_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 30. "CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu1_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 28. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 27. "EMIF0_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_mst_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 26. "EMIF0_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_slv_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 25. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 24. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 23. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 22. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 21. "POSTARB_PIPE_CFG_BUSECC_ENABLE_SET,Interrupt Enable Set Register for postarb_pipe_cfg_busecc_pend" "0,1"
newline
bitfld.long 0x00 20. "MSMC_MMR_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_mmr_busecc_pend" "0,1"
newline
bitfld.long 0x00 19. "DRU_RD_BUF_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_rd_buf_edc_pend" "0,1"
newline
bitfld.long 0x00 18. "DRU_QUEUE_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_edc_pend" "0,1"
newline
bitfld.long 0x00 17. "DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_eng_edc_pend" "0,1"
newline
bitfld.long 0x00 16. "DRU_ATTR_EDC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for dru_attr_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 15. "DRU_1_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_1_edc_pend" "0,1"
newline
bitfld.long 0x00 14. "DRU_0_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_0_edc_pend" "0,1"
newline
bitfld.long 0x00 13. "DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 12. "DRU_CBASS_SLV_BRDG_ECC_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_slv_brdg_ecc_edc_pend" "0,1"
newline
bitfld.long 0x00 11. "DRU_CBASS_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 10. "DRU_CBASS_MMR_FW_CH_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_fw_ch_edc_pend" "0,1"
newline
bitfld.long 0x00 9. "DRU_CBASS_MMR_FW_CH_BR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_fw_ch_br_edc_pend" "0,1"
newline
bitfld.long 0x00 8. "DRU_CBASS_MMR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "DRU_CBASS_MMR_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 6. "DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_bridge_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 5. "DRU_CBASS_MMR_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 4. "DRU_CBASS_MMR_BRDG_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_brdg_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_CBASS_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 2. "DRU_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_dmsc_slv_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRU_CBASS_DMSC_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_dmsc_scr_edc_pend" "0,1"
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bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR0_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr0_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 31. "EN_MSMC_P3_BUSECC_DUMMY_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 30. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 29. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 28. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 27. "EN_MSMC_P2_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 26. "EN_MSMC_P2_BUSECC_DUMMY_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 25. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 24. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 23. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 22. "EN_MSMC_P1_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 21. "EN_MSMC_P1_BUSECC_DUMMY_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 20. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 19. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 17. "EN_MSMC_P0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_pend" "0,1"
newline
bitfld.long 0x04 16. "EN_MSMC_P0_BUSECC_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_data_pend" "0,1"
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bitfld.long 0x04 15. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 14. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_slv_local_arb_busecc_pend" "0,1"
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bitfld.long 0x04 13. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_mst_local_arb_busecc_pend" "0,1"
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bitfld.long 0x04 12. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_slv_local_arb_busecc_pend" "0,1"
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bitfld.long 0x04 11. "CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu7_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 10. "CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu7_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu6_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 8. "CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu6_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu5_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 6. "CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu5_slv_local_arb_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 5. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_mst_local_arb_busecc_pend" "0,1"
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bitfld.long 0x04 4. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_slv_local_arb_busecc_pend" "0,1"
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bitfld.long 0x04 3. "CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu3_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 2. "CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu3_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu2_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu2_slv_local_arb_busecc_dummy_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG2,Interrupt Enable Set Register 2"
bitfld.long 0x08 31. "RMW3_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_1_pend" "0,1"
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bitfld.long 0x08 30. "RMW3_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_0_pend" "0,1"
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bitfld.long 0x08 29. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_cache_tag_pipe_busecc_pend" "0,1"
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bitfld.long 0x08 28. "RMW3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_busecc_pend" "0,1"
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bitfld.long 0x08 27. "DATARAM_BANK2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank2_busecc_pend" "0,1"
newline
bitfld.long 0x08 26. "SRAM2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram2_busecc_pend" "0,1"
newline
bitfld.long 0x08 25. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 24. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_rmw_tag_update_busecc_pend" "0,1"
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bitfld.long 0x08 23. "RMW2_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_1_pend" "0,1"
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bitfld.long 0x08 22. "RMW2_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_0_pend" "0,1"
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bitfld.long 0x08 21. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_cache_tag_pipe_busecc_pend" "0,1"
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bitfld.long 0x08 20. "RMW2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_busecc_pend" "0,1"
newline
bitfld.long 0x08 19. "DATARAM_BANK1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank1_busecc_pend" "0,1"
newline
bitfld.long 0x08 18. "SRAM1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram1_busecc_pend" "0,1"
newline
bitfld.long 0x08 17. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 16. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 15. "RMW1_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 14. "RMW1_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 13. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_cache_tag_pipe_busecc_pend" "0,1"
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bitfld.long 0x08 12. "RMW1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_busecc_pend" "0,1"
newline
bitfld.long 0x08 11. "DATARAM_BANK0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank0_busecc_pend" "0,1"
newline
bitfld.long 0x08 10. "SRAM0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram0_busecc_pend" "0,1"
newline
bitfld.long 0x08 9. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 8. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 7. "RMW0_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 6. "RMW0_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 5. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "RMW0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_busecc_pend" "0,1"
newline
bitfld.long 0x08 3. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 2. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "EN_MSMC_P3_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_busecc_dummy_pend" "0,1"
line.long 0x0C "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG3,Interrupt Enable Set Register 3"
bitfld.long 0x0C 11. "CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for clec_clec_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0C 10. "EMIF_0_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_0_vsafe_si_pend" "0,1"
newline
bitfld.long 0x0C 9. "VBUSP_CFG_DSP4_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dsp4_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 8. "EMIF1_MST_PIPE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for emif1_mst_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 7. "EMIF1_SLV_PIPE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for emif1_slv_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 6. "VBUSP_CFG_ECC_AGGR0_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr0_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 5. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 4. "CLEC_SRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clec_sram_ramecc_pend" "0,1"
newline
bitfld.long 0x0C 3. "DATARAM_BANK3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 2. "SRAM3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 1. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 0. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_rmw_tag_update_busecc_pend" "0,1"
group.long 0xC0++0x0F
line.long 0x00 "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 30. "CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 28. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 27. "EMIF0_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_mst_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 26. "EMIF0_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_slv_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 25. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 24. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 23. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 22. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 21. "POSTARB_PIPE_CFG_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for postarb_pipe_cfg_busecc_pend" "0,1"
newline
bitfld.long 0x00 20. "MSMC_MMR_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_mmr_busecc_pend" "0,1"
newline
bitfld.long 0x00 19. "DRU_RD_BUF_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_rd_buf_edc_pend" "0,1"
newline
bitfld.long 0x00 18. "DRU_QUEUE_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_edc_pend" "0,1"
newline
bitfld.long 0x00 17. "DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_eng_edc_pend" "0,1"
newline
bitfld.long 0x00 16. "DRU_ATTR_EDC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for dru_attr_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 15. "DRU_1_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_1_edc_pend" "0,1"
newline
bitfld.long 0x00 14. "DRU_0_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_0_edc_pend" "0,1"
newline
bitfld.long 0x00 13. "DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 12. "DRU_CBASS_SLV_BRDG_ECC_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_slv_brdg_ecc_edc_pend" "0,1"
newline
bitfld.long 0x00 11. "DRU_CBASS_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 10. "DRU_CBASS_MMR_FW_CH_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_fw_ch_edc_pend" "0,1"
newline
bitfld.long 0x00 9. "DRU_CBASS_MMR_FW_CH_BR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_fw_ch_br_edc_pend" "0,1"
newline
bitfld.long 0x00 8. "DRU_CBASS_MMR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "DRU_CBASS_MMR_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 6. "DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_bridge_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 5. "DRU_CBASS_MMR_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 4. "DRU_CBASS_MMR_BRDG_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_brdg_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_CBASS_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 2. "DRU_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_dmsc_slv_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRU_CBASS_DMSC_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_dmsc_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR0_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr0_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 31. "EN_MSMC_P3_BUSECC_DUMMY_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 30. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 29. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 28. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 27. "EN_MSMC_P2_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 26. "EN_MSMC_P2_BUSECC_DUMMY_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 25. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 24. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 23. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 22. "EN_MSMC_P1_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 21. "EN_MSMC_P1_BUSECC_DUMMY_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 20. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 19. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 17. "EN_MSMC_P0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_pend" "0,1"
newline
bitfld.long 0x04 16. "EN_MSMC_P0_BUSECC_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_data_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 14. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 12. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu7_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 10. "CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu7_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu6_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 8. "CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu6_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 6. "CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 2. "CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_slv_local_arb_busecc_dummy_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG2,Interrupt Enable Clear Register 2"
bitfld.long 0x08 31. "RMW3_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 30. "RMW3_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 29. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 28. "RMW3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_busecc_pend" "0,1"
newline
bitfld.long 0x08 27. "DATARAM_BANK2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank2_busecc_pend" "0,1"
newline
bitfld.long 0x08 26. "SRAM2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram2_busecc_pend" "0,1"
newline
bitfld.long 0x08 25. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 24. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 23. "RMW2_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 22. "RMW2_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 21. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 20. "RMW2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_busecc_pend" "0,1"
newline
bitfld.long 0x08 19. "DATARAM_BANK1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank1_busecc_pend" "0,1"
newline
bitfld.long 0x08 18. "SRAM1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram1_busecc_pend" "0,1"
newline
bitfld.long 0x08 17. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 16. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 15. "RMW1_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 14. "RMW1_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 13. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 12. "RMW1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_busecc_pend" "0,1"
newline
bitfld.long 0x08 11. "DATARAM_BANK0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank0_busecc_pend" "0,1"
newline
bitfld.long 0x08 10. "SRAM0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram0_busecc_pend" "0,1"
newline
bitfld.long 0x08 9. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 8. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 7. "RMW0_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 6. "RMW0_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 5. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "RMW0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_busecc_pend" "0,1"
newline
bitfld.long 0x08 3. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 2. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "EN_MSMC_P3_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_busecc_dummy_pend" "0,1"
line.long 0x0C "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG3,Interrupt Enable Clear Register 3"
bitfld.long 0x0C 11. "CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_clec_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0C 10. "EMIF_0_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_0_vsafe_si_pend" "0,1"
newline
bitfld.long 0x0C 9. "VBUSP_CFG_DSP4_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dsp4_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 8. "EMIF1_MST_PIPE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for emif1_mst_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 7. "EMIF1_SLV_PIPE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for emif1_slv_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 6. "VBUSP_CFG_ECC_AGGR0_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr0_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 5. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 4. "CLEC_SRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_sram_ramecc_pend" "0,1"
newline
bitfld.long 0x0C 3. "DATARAM_BANK3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 2. "SRAM3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 1. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 0. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_rmw_tag_update_busecc_pend" "0,1"
group.long 0x13C++0x13
line.long 0x00 "MSMC_WRAP_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu1_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 30. "CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu1_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 28. "CPU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 27. "EMIF0_MST_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_mst_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x04 26. "EMIF0_SLV_PIPE_BUSECC_PEND,Interrupt Pending Status for emif0_slv_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x04 25. "DRU1_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 24. "DRU0_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 23. "DRU1_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru1_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 22. "DRU0_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for dru0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 21. "POSTARB_PIPE_CFG_BUSECC_PEND,Interrupt Pending Status for postarb_pipe_cfg_busecc_pend" "0,1"
newline
bitfld.long 0x04 20. "MSMC_MMR_BUSECC_PEND,Interrupt Pending Status for msmc_mmr_busecc_pend" "0,1"
newline
bitfld.long 0x04 19. "DRU_RD_BUF_EDC_PEND,Interrupt Pending Status for dru_rd_buf_edc_pend" "0,1"
newline
bitfld.long 0x04 18. "DRU_QUEUE_EDC_PEND,Interrupt Pending Status for dru_queue_edc_pend" "0,1"
newline
bitfld.long 0x04 17. "DRU_ENG_EDC_PEND,Interrupt Pending Status for dru_eng_edc_pend" "0,1"
newline
bitfld.long 0x04 16. "DRU_ATTR_EDC_DUMMY_PEND,Interrupt Pending Status for dru_attr_edc_dummy_pend" "0,1"
newline
bitfld.long 0x04 15. "DRU_1_EDC_PEND,Interrupt Pending Status for dru_1_edc_pend" "0,1"
newline
bitfld.long 0x04 14. "DRU_0_EDC_PEND,Interrupt Pending Status for dru_0_edc_pend" "0,1"
newline
bitfld.long 0x04 13. "DRU_PSI_EDC_PEND,Interrupt Pending Status for dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x04 12. "DRU_CBASS_SLV_BRDG_ECC_EDC_PEND,Interrupt Pending Status for dru_cbass_slv_brdg_ecc_edc_pend" "0,1"
newline
bitfld.long 0x04 11. "DRU_CBASS_SCR_EDC_PEND,Interrupt Pending Status for dru_cbass_scr_edc_pend" "0,1"
newline
bitfld.long 0x04 10. "DRU_CBASS_MMR_FW_CH_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_fw_ch_edc_pend" "0,1"
newline
bitfld.long 0x04 9. "DRU_CBASS_MMR_FW_CH_BR_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_fw_ch_br_edc_pend" "0,1"
newline
bitfld.long 0x04 8. "DRU_CBASS_MMR_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_edc_pend" "0,1"
newline
bitfld.long 0x04 7. "DRU_CBASS_MMR_CFG_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_cfg_edc_pend" "0,1"
newline
bitfld.long 0x04 6. "DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_PEND,Interrupt Pending Status for dru_cbass_mmr_bridge_edc_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "DRU_CBASS_MMR_BRDG_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_brdg_edc_pend" "0,1"
newline
bitfld.long 0x04 4. "DRU_CBASS_MMR_BRDG_CFG_EDC_PEND,Interrupt Pending Status for dru_cbass_mmr_brdg_cfg_edc_pend" "0,1"
newline
bitfld.long 0x04 3. "DRU_CBASS_EDC_CTRL_PEND,Interrupt Pending Status for dru_cbass_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x04 2. "DRU_CBASS_DMSC_SLV_BRDG_EDC_PEND,Interrupt Pending Status for dru_cbass_dmsc_slv_brdg_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "DRU_CBASS_DMSC_SCR_EDC_PEND,Interrupt Pending Status for dru_cbass_dmsc_scr_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR0_PEND,Interrupt Pending Status for edc_ctrl_eccaggr0_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_DED_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 31. "EN_MSMC_P3_BUSECC_DUMMY_DATA_PEND,Interrupt Pending Status for en_msmc_p3_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x08 30. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 29. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 28. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 27. "EN_MSMC_P2_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 26. "EN_MSMC_P2_BUSECC_DUMMY_DATA_PEND,Interrupt Pending Status for en_msmc_p2_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x08 25. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 24. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 23. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 22. "EN_MSMC_P1_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 21. "EN_MSMC_P1_BUSECC_DUMMY_DATA_PEND,Interrupt Pending Status for en_msmc_p1_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x08 20. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 19. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 17. "EN_MSMC_P0_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_busecc_pend" "0,1"
newline
bitfld.long 0x08 16. "EN_MSMC_P0_BUSECC_DATA_PEND,Interrupt Pending Status for en_msmc_p0_busecc_data_pend" "0,1"
newline
bitfld.long 0x08 15. "CPU9_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 14. "CPU9_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu9_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 13. "CPU8_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 12. "CPU8_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu8_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 11. "CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu7_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 10. "CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu7_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 9. "CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu6_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 8. "CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu6_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 7. "CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu5_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 6. "CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu5_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 5. "CPU4_MST_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "CPU4_SLV_LOCAL_ARB_BUSECC_PEND,Interrupt Pending Status for cpu4_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x08 3. "CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu3_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 2. "CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu3_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu2_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_PEND,Interrupt Pending Status for cpu2_slv_local_arb_busecc_dummy_pend" "0,1"
line.long 0x0C "MSMC_WRAP_ECC_DED_STATUS_REG2,Interrupt Status Register 2"
bitfld.long 0x0C 31. "RMW3_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw3_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 30. "RMW3_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw3_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 29. "RMW3_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 28. "RMW3_BUSECC_PEND,Interrupt Pending Status for rmw3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 27. "DATARAM_BANK2_BUSECC_PEND,Interrupt Pending Status for dataram_bank2_busecc_pend" "0,1"
newline
bitfld.long 0x0C 26. "SRAM2_BUSECC_PEND,Interrupt Pending Status for sram2_busecc_pend" "0,1"
newline
bitfld.long 0x0C 25. "RMW2_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 24. "RMW2_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw2_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x0C 23. "RMW2_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw2_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 22. "RMW2_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw2_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 21. "RMW2_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw2_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 20. "RMW2_BUSECC_PEND,Interrupt Pending Status for rmw2_busecc_pend" "0,1"
newline
bitfld.long 0x0C 19. "DATARAM_BANK1_BUSECC_PEND,Interrupt Pending Status for dataram_bank1_busecc_pend" "0,1"
newline
bitfld.long 0x0C 18. "SRAM1_BUSECC_PEND,Interrupt Pending Status for sram1_busecc_pend" "0,1"
newline
bitfld.long 0x0C 17. "RMW1_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 16. "RMW1_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw1_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x0C 15. "RMW1_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw1_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 14. "RMW1_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw1_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 13. "RMW1_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw1_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 12. "RMW1_BUSECC_PEND,Interrupt Pending Status for rmw1_busecc_pend" "0,1"
newline
bitfld.long 0x0C 11. "DATARAM_BANK0_BUSECC_PEND,Interrupt Pending Status for dataram_bank0_busecc_pend" "0,1"
newline
bitfld.long 0x0C 10. "SRAM0_BUSECC_PEND,Interrupt Pending Status for sram0_busecc_pend" "0,1"
newline
bitfld.long 0x0C 9. "RMW0_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 8. "RMW0_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw0_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x0C 7. "RMW0_QUEUE_BUSECC_1_PEND,Interrupt Pending Status for rmw0_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x0C 6. "RMW0_QUEUE_BUSECC_0_PEND,Interrupt Pending Status for rmw0_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x0C 5. "RMW0_CACHE_TAG_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw0_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 4. "RMW0_BUSECC_PEND,Interrupt Pending Status for rmw0_busecc_pend" "0,1"
newline
bitfld.long 0x0C 3. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 2. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 0. "EN_MSMC_P3_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_busecc_dummy_pend" "0,1"
line.long 0x10 "MSMC_WRAP_ECC_DED_STATUS_REG3,Interrupt Status Register 3"
bitfld.long 0x10 11. "CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for clec_clec_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x10 10. "EMIF_0_VSAFE_SI_PEND,Interrupt Pending Status for emif_0_vsafe_si_pend" "0,1"
newline
bitfld.long 0x10 9. "VBUSP_CFG_DSP4_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dsp4_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x10 8. "EMIF1_MST_PIPE_BUSECC_DUMMY_PEND,Interrupt Pending Status for emif1_mst_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x10 7. "EMIF1_SLV_PIPE_BUSECC_DUMMY_PEND,Interrupt Pending Status for emif1_slv_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x10 6. "VBUSP_CFG_ECC_AGGR0_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr0_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x10 5. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr0_p2p_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x10 4. "CLEC_SRAM_RAMECC_PEND,Interrupt Pending Status for clec_sram_ramecc_pend" "0,1"
newline
bitfld.long 0x10 3. "DATARAM_BANK3_BUSECC_PEND,Interrupt Pending Status for dataram_bank3_busecc_pend" "0,1"
newline
bitfld.long 0x10 2. "SRAM3_BUSECC_PEND,Interrupt Pending Status for sram3_busecc_pend" "0,1"
newline
bitfld.long 0x10 1. "RMW3_SRAM_SF_PIPE_BUSECC_PEND,Interrupt Pending Status for rmw3_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x10 0. "RMW3_RMW_TAG_UPDATE_BUSECC_PEND,Interrupt Pending Status for rmw3_rmw_tag_update_busecc_pend" "0,1"
group.long 0x180++0x0F
line.long 0x00 "MSMC_WRAP_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu1_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 30. "CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu1_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 28. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 27. "EMIF0_MST_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_mst_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 26. "EMIF0_SLV_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for emif0_slv_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 25. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 24. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 23. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru1_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 22. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dru0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 21. "POSTARB_PIPE_CFG_BUSECC_ENABLE_SET,Interrupt Enable Set Register for postarb_pipe_cfg_busecc_pend" "0,1"
newline
bitfld.long 0x00 20. "MSMC_MMR_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_mmr_busecc_pend" "0,1"
newline
bitfld.long 0x00 19. "DRU_RD_BUF_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_rd_buf_edc_pend" "0,1"
newline
bitfld.long 0x00 18. "DRU_QUEUE_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_edc_pend" "0,1"
newline
bitfld.long 0x00 17. "DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_eng_edc_pend" "0,1"
newline
bitfld.long 0x00 16. "DRU_ATTR_EDC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for dru_attr_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 15. "DRU_1_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_1_edc_pend" "0,1"
newline
bitfld.long 0x00 14. "DRU_0_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_0_edc_pend" "0,1"
newline
bitfld.long 0x00 13. "DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 12. "DRU_CBASS_SLV_BRDG_ECC_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_slv_brdg_ecc_edc_pend" "0,1"
newline
bitfld.long 0x00 11. "DRU_CBASS_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 10. "DRU_CBASS_MMR_FW_CH_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_fw_ch_edc_pend" "0,1"
newline
bitfld.long 0x00 9. "DRU_CBASS_MMR_FW_CH_BR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_fw_ch_br_edc_pend" "0,1"
newline
bitfld.long 0x00 8. "DRU_CBASS_MMR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "DRU_CBASS_MMR_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 6. "DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_bridge_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 5. "DRU_CBASS_MMR_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 4. "DRU_CBASS_MMR_BRDG_CFG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_mmr_brdg_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_CBASS_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 2. "DRU_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_dmsc_slv_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRU_CBASS_DMSC_SCR_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_cbass_dmsc_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR0_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr0_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 31. "EN_MSMC_P3_BUSECC_DUMMY_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 30. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 29. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 28. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 27. "EN_MSMC_P2_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 26. "EN_MSMC_P2_BUSECC_DUMMY_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 25. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 24. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 23. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 22. "EN_MSMC_P1_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 21. "EN_MSMC_P1_BUSECC_DUMMY_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 20. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 19. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 17. "EN_MSMC_P0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_pend" "0,1"
newline
bitfld.long 0x04 16. "EN_MSMC_P0_BUSECC_DATA_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_busecc_data_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 14. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu9_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 12. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu8_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu7_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 10. "CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu7_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu6_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 8. "CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu6_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu5_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 6. "CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu5_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_SET,Interrupt Enable Set Register for cpu4_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu3_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 2. "CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu3_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu2_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for cpu2_slv_local_arb_busecc_dummy_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_DED_ENABLE_SET_REG2,Interrupt Enable Set Register 2"
bitfld.long 0x08 31. "RMW3_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 30. "RMW3_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw3_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 29. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 28. "RMW3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_busecc_pend" "0,1"
newline
bitfld.long 0x08 27. "DATARAM_BANK2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank2_busecc_pend" "0,1"
newline
bitfld.long 0x08 26. "SRAM2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram2_busecc_pend" "0,1"
newline
bitfld.long 0x08 25. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 24. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 23. "RMW2_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 22. "RMW2_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw2_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 21. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 20. "RMW2_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw2_busecc_pend" "0,1"
newline
bitfld.long 0x08 19. "DATARAM_BANK1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank1_busecc_pend" "0,1"
newline
bitfld.long 0x08 18. "SRAM1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram1_busecc_pend" "0,1"
newline
bitfld.long 0x08 17. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 16. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 15. "RMW1_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 14. "RMW1_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw1_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 13. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 12. "RMW1_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw1_busecc_pend" "0,1"
newline
bitfld.long 0x08 11. "DATARAM_BANK0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank0_busecc_pend" "0,1"
newline
bitfld.long 0x08 10. "SRAM0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram0_busecc_pend" "0,1"
newline
bitfld.long 0x08 9. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 8. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 7. "RMW0_QUEUE_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 6. "RMW0_QUEUE_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for rmw0_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 5. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "RMW0_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw0_busecc_pend" "0,1"
newline
bitfld.long 0x08 3. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 2. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "EN_MSMC_P3_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_busecc_dummy_pend" "0,1"
line.long 0x0C "MSMC_WRAP_ECC_DED_ENABLE_SET_REG3,Interrupt Enable Set Register 3"
bitfld.long 0x0C 11. "CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for clec_clec_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0C 10. "EMIF_0_VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for emif_0_vsafe_si_pend" "0,1"
newline
bitfld.long 0x0C 9. "VBUSP_CFG_DSP4_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dsp4_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 8. "EMIF1_MST_PIPE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for emif1_mst_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 7. "EMIF1_SLV_PIPE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for emif1_slv_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 6. "VBUSP_CFG_ECC_AGGR0_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr0_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 5. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 4. "CLEC_SRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clec_sram_ramecc_pend" "0,1"
newline
bitfld.long 0x0C 3. "DATARAM_BANK3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dataram_bank3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 2. "SRAM3_BUSECC_ENABLE_SET,Interrupt Enable Set Register for sram3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 1. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x0C 0. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for rmw3_rmw_tag_update_busecc_pend" "0,1"
group.long 0x1C0++0x0F
line.long 0x00 "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 30. "CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 28. "CPU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 27. "EMIF0_MST_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_mst_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 26. "EMIF0_SLV_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for emif0_slv_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x00 25. "DRU1_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 24. "DRU0_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 23. "DRU1_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru1_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 22. "DRU0_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dru0_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x00 21. "POSTARB_PIPE_CFG_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for postarb_pipe_cfg_busecc_pend" "0,1"
newline
bitfld.long 0x00 20. "MSMC_MMR_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_mmr_busecc_pend" "0,1"
newline
bitfld.long 0x00 19. "DRU_RD_BUF_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_rd_buf_edc_pend" "0,1"
newline
bitfld.long 0x00 18. "DRU_QUEUE_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_edc_pend" "0,1"
newline
bitfld.long 0x00 17. "DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_eng_edc_pend" "0,1"
newline
bitfld.long 0x00 16. "DRU_ATTR_EDC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for dru_attr_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 15. "DRU_1_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_1_edc_pend" "0,1"
newline
bitfld.long 0x00 14. "DRU_0_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_0_edc_pend" "0,1"
newline
bitfld.long 0x00 13. "DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 12. "DRU_CBASS_SLV_BRDG_ECC_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_slv_brdg_ecc_edc_pend" "0,1"
newline
bitfld.long 0x00 11. "DRU_CBASS_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 10. "DRU_CBASS_MMR_FW_CH_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_fw_ch_edc_pend" "0,1"
newline
bitfld.long 0x00 9. "DRU_CBASS_MMR_FW_CH_BR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_fw_ch_br_edc_pend" "0,1"
newline
bitfld.long 0x00 8. "DRU_CBASS_MMR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "DRU_CBASS_MMR_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 6. "DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_bridge_edc_dummy_pend" "0,1"
newline
bitfld.long 0x00 5. "DRU_CBASS_MMR_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 4. "DRU_CBASS_MMR_BRDG_CFG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_mmr_brdg_cfg_edc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_CBASS_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 2. "DRU_CBASS_DMSC_SLV_BRDG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_dmsc_slv_brdg_edc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRU_CBASS_DMSC_SCR_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_cbass_dmsc_scr_edc_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR0_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr0_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 31. "EN_MSMC_P3_BUSECC_DUMMY_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 30. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 29. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 28. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 27. "EN_MSMC_P2_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 26. "EN_MSMC_P2_BUSECC_DUMMY_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 25. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 24. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 23. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 22. "EN_MSMC_P1_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 21. "EN_MSMC_P1_BUSECC_DUMMY_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_busecc_dummy_data_pend" "0,1"
newline
bitfld.long 0x04 20. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 19. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 17. "EN_MSMC_P0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_pend" "0,1"
newline
bitfld.long 0x04 16. "EN_MSMC_P0_BUSECC_DATA_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_busecc_data_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU9_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 14. "CPU9_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu9_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU8_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 12. "CPU8_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu8_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu7_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 10. "CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu7_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu6_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 8. "CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu6_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 6. "CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu5_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU4_MST_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_mst_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "CPU4_SLV_LOCAL_ARB_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu4_slv_local_arb_busecc_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 2. "CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_slv_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_mst_local_arb_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_slv_local_arb_busecc_dummy_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG2,Interrupt Enable Clear Register 2"
bitfld.long 0x08 31. "RMW3_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 30. "RMW3_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 29. "RMW3_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 28. "RMW3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_busecc_pend" "0,1"
newline
bitfld.long 0x08 27. "DATARAM_BANK2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank2_busecc_pend" "0,1"
newline
bitfld.long 0x08 26. "SRAM2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram2_busecc_pend" "0,1"
newline
bitfld.long 0x08 25. "RMW2_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 24. "RMW2_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 23. "RMW2_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 22. "RMW2_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_queue_busecc_0_pend" "0,1"
newline
bitfld.long 0x08 21. "RMW2_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 20. "RMW2_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw2_busecc_pend" "0,1"
newline
bitfld.long 0x08 19. "DATARAM_BANK1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank1_busecc_pend" "0,1"
newline
bitfld.long 0x08 18. "SRAM1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram1_busecc_pend" "0,1"
newline
bitfld.long 0x08 17. "RMW1_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 16. "RMW1_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_rmw_tag_update_busecc_pend" "0,1"
newline
bitfld.long 0x08 15. "RMW1_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_1_pend" "0,1"
newline
bitfld.long 0x08 14. "RMW1_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_queue_busecc_0_pend" "0,1"
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bitfld.long 0x08 13. "RMW1_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_cache_tag_pipe_busecc_pend" "0,1"
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bitfld.long 0x08 12. "RMW1_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw1_busecc_pend" "0,1"
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bitfld.long 0x08 11. "DATARAM_BANK0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank0_busecc_pend" "0,1"
newline
bitfld.long 0x08 10. "SRAM0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram0_busecc_pend" "0,1"
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bitfld.long 0x08 9. "RMW0_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_sram_sf_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 8. "RMW0_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_rmw_tag_update_busecc_pend" "0,1"
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bitfld.long 0x08 7. "RMW0_QUEUE_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_1_pend" "0,1"
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bitfld.long 0x08 6. "RMW0_QUEUE_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_queue_busecc_0_pend" "0,1"
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bitfld.long 0x08 5. "RMW0_CACHE_TAG_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_cache_tag_pipe_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "RMW0_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw0_busecc_pend" "0,1"
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bitfld.long 0x08 3. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 2. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "EN_MSMC_P3_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_busecc_dummy_pend" "0,1"
line.long 0x0C "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG3,Interrupt Enable Clear Register 3"
bitfld.long 0x0C 11. "CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_clec_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x0C 10. "EMIF_0_VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for emif_0_vsafe_si_pend" "0,1"
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bitfld.long 0x0C 9. "VBUSP_CFG_DSP4_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dsp4_p2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x0C 8. "EMIF1_MST_PIPE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for emif1_mst_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 7. "EMIF1_SLV_PIPE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for emif1_slv_pipe_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x0C 6. "VBUSP_CFG_ECC_AGGR0_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr0_p2p_dst_busecc_pend" "0,1"
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bitfld.long 0x0C 5. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_dummy_pend" "0,1"
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bitfld.long 0x0C 4. "CLEC_SRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clec_sram_ramecc_pend" "0,1"
newline
bitfld.long 0x0C 3. "DATARAM_BANK3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dataram_bank3_busecc_pend" "0,1"
newline
bitfld.long 0x0C 2. "SRAM3_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for sram3_busecc_pend" "0,1"
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bitfld.long 0x0C 1. "RMW3_SRAM_SF_PIPE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_sram_sf_pipe_busecc_pend" "0,1"
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bitfld.long 0x0C 0. "RMW3_RMW_TAG_UPDATE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for rmw3_rmw_tag_update_busecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MSMC_WRAP_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSMC_WRAP_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR1"
tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR1"
base ad:0x4D20000400
rgroup.long 0x400++0x03
line.long 0x00 "MSMC_WRAP_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x408++0x0B
line.long 0x00 "MSMC_WRAP_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSMC_WRAP_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSMC_WRAP_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x43C++0x0B
line.long 0x00 "MSMC_WRAP_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 30. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x04 29. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr0_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 28. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 27. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 26. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 25. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 24. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 23. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 22. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 21. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 20. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x04 19. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 17. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1"
newline
bitfld.long 0x04 16. "VBUSP_DMSC_CBASS_EDC_CTRL_CBASS_INT_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_cbass_int_busecc_pend" "0,1"
newline
bitfld.long 0x04 15. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x04 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x04 13. "MSMC_J7ES_CFG_WRAP_CBASS_VBUSP4_CFG_MSMC_PBIST_P2P_BRIDGE_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x04 12. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_1_DUMMY_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x04 11. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_scr1_scr_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 10. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1"
newline
bitfld.long 0x04 9. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1"
newline
bitfld.long 0x04 8. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1"
newline
bitfld.long 0x04 7. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1"
newline
bitfld.long 0x04 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_1_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_busecc_1_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_busecc_0_pend" "0,1"
newline
bitfld.long 0x04 4. "VBUSP_DMSC_CBASS_DRU_FW_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru_fw_bridge_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 3. "VBUSP_DMSC_CBASS_DRU_MMR_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru_mmr_fw_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 2. "VBUSP_DMSC_CBASS_CPAC1_FW_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac1_fw_bridge_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR1_PEND,Interrupt Pending Status for edc_ctrl_eccaggr1_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_SEC_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x08 13. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x08 12. "VBUSP_CFG_DSP4_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dsp4_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x08 11. "MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x08 10. "MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x08 9. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x08 8. "DDRSS0_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_busecc_pend" "0,1"
newline
bitfld.long 0x08 7. "DDRSS0_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss0_m2m_src_vbuss_pend" "0,1"
newline
bitfld.long 0x08 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_2_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_busecc_2_dummy_pend" "0,1"
newline
bitfld.long 0x08 5. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x08 4. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_2_DUMMY_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x08 3. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x08 2. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x08 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x08 0. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
group.long 0x480++0x07
line.long 0x00 "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 30. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x00 29. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 28. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 27. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 26. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 25. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 24. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 23. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 22. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 21. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 20. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 19. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1"
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bitfld.long 0x00 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1"
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bitfld.long 0x00 17. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1"
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bitfld.long 0x00 16. "VBUSP_DMSC_CBASS_EDC_CTRL_CBASS_INT_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_cbass_int_busecc_pend" "0,1"
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bitfld.long 0x00 15. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 13. "MSMC_J7ES_CFG_WRAP_CBASS_VBUSP4_CFG_MSMC_PBIST_P2P_BRIDGE_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 12. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 11. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_scr1_scr_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 10. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1"
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bitfld.long 0x00 9. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 8. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 7. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_busecc_1_dummy_pend" "0,1"
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bitfld.long 0x00 5. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x00 4. "VBUSP_DMSC_CBASS_DRU_FW_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 3. "VBUSP_DMSC_CBASS_DRU_MMR_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru_mmr_fw_bridge_busecc_pend" "0,1"
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bitfld.long 0x00 2. "VBUSP_DMSC_CBASS_CPAC1_FW_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac1_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR1_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr1_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x04 13. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x04 12. "VBUSP_CFG_DSP4_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dsp4_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x04 11. "MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 10. "MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 9. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1"
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bitfld.long 0x04 8. "DDRSS0_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_busecc_pend" "0,1"
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bitfld.long 0x04 7. "DDRSS0_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss0_m2m_src_vbuss_pend" "0,1"
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bitfld.long 0x04 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_busecc_2_dummy_pend" "0,1"
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bitfld.long 0x04 5. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1"
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bitfld.long 0x04 4. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x04 3. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x04 2. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc_pend" "0,1"
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bitfld.long 0x04 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 0. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
group.long 0x4C0++0x07
line.long 0x00 "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 30. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1"
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bitfld.long 0x00 29. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x00 28. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 27. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 26. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 25. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 24. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 23. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 22. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 21. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 20. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 19. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1"
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bitfld.long 0x00 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1"
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bitfld.long 0x00 17. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1"
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bitfld.long 0x00 16. "VBUSP_DMSC_CBASS_EDC_CTRL_CBASS_INT_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_cbass_int_busecc_pend" "0,1"
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bitfld.long 0x00 15. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x00 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x00 13. "MSMC_J7ES_CFG_WRAP_CBASS_VBUSP4_CFG_MSMC_PBIST_P2P_BRIDGE_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x00 12. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x00 11. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_scr1_scr_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 10. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1"
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bitfld.long 0x00 9. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 8. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 7. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_busecc_1_dummy_pend" "0,1"
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bitfld.long 0x00 5. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x00 4. "VBUSP_DMSC_CBASS_DRU_FW_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 3. "VBUSP_DMSC_CBASS_DRU_MMR_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru_mmr_fw_bridge_busecc_pend" "0,1"
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bitfld.long 0x00 2. "VBUSP_DMSC_CBASS_CPAC1_FW_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac1_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR1_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr1_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x04 13. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x04 12. "VBUSP_CFG_DSP4_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dsp4_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x04 11. "MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 10. "MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 9. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1"
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bitfld.long 0x04 8. "DDRSS0_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_busecc_pend" "0,1"
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bitfld.long 0x04 7. "DDRSS0_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_m2m_src_vbuss_pend" "0,1"
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bitfld.long 0x04 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_busecc_2_dummy_pend" "0,1"
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bitfld.long 0x04 5. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1"
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bitfld.long 0x04 4. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x04 3. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x04 2. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc_pend" "0,1"
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bitfld.long 0x04 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 0. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
group.long 0x53C++0x0B
line.long 0x00 "MSMC_WRAP_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 30. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1"
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bitfld.long 0x04 29. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr0_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x04 28. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 27. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 26. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 25. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 24. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 23. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 22. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 21. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 20. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_PEND,Interrupt Pending Status for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x04 19. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1"
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bitfld.long 0x04 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1"
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bitfld.long 0x04 17. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_PEND,Interrupt Pending Status for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1"
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bitfld.long 0x04 16. "VBUSP_DMSC_CBASS_EDC_CTRL_CBASS_INT_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_cbass_int_busecc_pend" "0,1"
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bitfld.long 0x04 15. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x04 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x04 13. "MSMC_J7ES_CFG_WRAP_CBASS_VBUSP4_CFG_MSMC_PBIST_P2P_BRIDGE_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x04 12. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_1_DUMMY_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x04 11. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_scr1_scr_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 10. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1"
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bitfld.long 0x04 9. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x04 8. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x04 7. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_PEND,Interrupt Pending Status for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x04 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_1_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_busecc_1_dummy_pend" "0,1"
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bitfld.long 0x04 5. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 4. "VBUSP_DMSC_CBASS_DRU_FW_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 3. "VBUSP_DMSC_CBASS_DRU_MMR_FW_BRIDGE_BUSECC_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_dru_mmr_fw_bridge_busecc_pend" "0,1"
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bitfld.long 0x04 2. "VBUSP_DMSC_CBASS_CPAC1_FW_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac1_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_BUSECC_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_cpac0_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR1_PEND,Interrupt Pending Status for edc_ctrl_eccaggr1_pend" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_DED_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x08 13. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x08 12. "VBUSP_CFG_DSP4_P2P_SRC_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_dsp4_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x08 11. "MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 10. "MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 9. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_reassembly_busecc_pend" "0,1"
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bitfld.long 0x08 8. "DDRSS0_SRC_P2M_BUSECC_PEND,Interrupt Pending Status for ddrss0_src_p2m_busecc_pend" "0,1"
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bitfld.long 0x08 7. "DDRSS0_M2M_SRC_VBUSS_PEND,Interrupt Pending Status for ddrss0_m2m_src_vbuss_pend" "0,1"
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bitfld.long 0x08 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_2_DUMMY_PEND,Interrupt Pending Status for vbusp_dmsc_cbass_edc_ctrl_busecc_2_dummy_pend" "0,1"
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bitfld.long 0x08 5. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1"
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bitfld.long 0x08 4. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_2_DUMMY_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x08 3. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_REASSEMBLY_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_reassembly_busecc_pend" "0,1"
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bitfld.long 0x08 2. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_BUSECC_PEND,Interrupt Pending Status for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc_pend" "0,1"
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bitfld.long 0x08 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p3_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
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bitfld.long 0x08 0. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_PEND,Interrupt Pending Status for en_msmc_p2_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
group.long 0x580++0x07
line.long 0x00 "MSMC_WRAP_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 30. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1"
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bitfld.long 0x00 29. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x00 28. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 27. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 26. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 25. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 24. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 23. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 22. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 21. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 20. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
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bitfld.long 0x00 19. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1"
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bitfld.long 0x00 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1"
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bitfld.long 0x00 17. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1"
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bitfld.long 0x00 16. "VBUSP_DMSC_CBASS_EDC_CTRL_CBASS_INT_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_cbass_int_busecc_pend" "0,1"
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bitfld.long 0x00 15. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 13. "MSMC_J7ES_CFG_WRAP_CBASS_VBUSP4_CFG_MSMC_PBIST_P2P_BRIDGE_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 12. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x00 11. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_scr1_scr_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 10. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1"
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bitfld.long 0x00 9. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 8. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 7. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1"
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bitfld.long 0x00 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_busecc_1_dummy_pend" "0,1"
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bitfld.long 0x00 5. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x00 4. "VBUSP_DMSC_CBASS_DRU_FW_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 3. "VBUSP_DMSC_CBASS_DRU_MMR_FW_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_dru_mmr_fw_bridge_busecc_pend" "0,1"
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bitfld.long 0x00 2. "VBUSP_DMSC_CBASS_CPAC1_FW_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac1_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_cpac0_fw_bridge_busecc_dummy_pend" "0,1"
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bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR1_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr1_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x04 13. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1"
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bitfld.long 0x04 12. "VBUSP_CFG_DSP4_P2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_dsp4_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 11. "MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 10. "MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 9. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x04 8. "DDRSS0_SRC_P2M_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddrss0_src_p2m_busecc_pend" "0,1"
newline
bitfld.long 0x04 7. "DDRSS0_M2M_SRC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ddrss0_m2m_src_vbuss_pend" "0,1"
newline
bitfld.long 0x04 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_SET,Interrupt Enable Set Register for vbusp_dmsc_cbass_edc_ctrl_busecc_2_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x04 3. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x04 2. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p3_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_SET,Interrupt Enable Set Register for en_msmc_p2_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
group.long 0x5C0++0x07
line.long 0x00 "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 30. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x00 29. "VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr0_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 28. "EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 27. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 26. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 25. "EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 24. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 23. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 22. "EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_m2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 21. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_src_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 20. "EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY1_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc_dummy1_pend" "0,1"
newline
bitfld.long 0x00 19. "EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_m2m_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 18. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 17. "EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 16. "VBUSP_DMSC_CBASS_EDC_CTRL_CBASS_INT_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_cbass_int_busecc_pend" "0,1"
newline
bitfld.long 0x00 15. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR1_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x00 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x00 13. "MSMC_J7ES_CFG_WRAP_CBASS_VBUSP4_CFG_MSMC_PBIST_P2P_BRIDGE_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_VBUSP4_CFG_MSMC_PBIST_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x00 12. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x00 11. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_scr1_scr_msmc_cfg_wrap_cbass_scr1_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 10. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_CBASS_INT_CLK4_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc_pend" "0,1"
newline
bitfld.long 0x00 9. "DMSC_MMR_PRIVID_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_privid_edc_ctrl_busecc_busecc_pend" "0,1"
newline
bitfld.long 0x00 8. "DMSC_MMR_EMULATION_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_emulation_edc_ctrl_busecc_busecc_pend" "0,1"
newline
bitfld.long 0x00 7. "DMSC_MMR_BOOT_EDC_CTRL_BUSECC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dmsc_mmr_boot_edc_ctrl_busecc_busecc_pend" "0,1"
newline
bitfld.long 0x00 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_1_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_busecc_1_dummy_pend" "0,1"
newline
bitfld.long 0x00 5. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_busecc_0_pend" "0,1"
newline
bitfld.long 0x00 4. "VBUSP_DMSC_CBASS_DRU_FW_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru_fw_bridge_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 3. "VBUSP_DMSC_CBASS_DRU_MMR_FW_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_dru_mmr_fw_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "VBUSP_DMSC_CBASS_CPAC1_FW_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac1_fw_bridge_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 1. "VBUSP_DMSC_CBASS_CPAC0_FW_BRIDGE_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_cpac0_fw_bridge_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR1_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr1_pend" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 14. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_VBUSP_MSMC_ECC_AGGR2_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x04 13. "VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 12. "VBUSP_CFG_DSP4_P2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_dsp4_p2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 11. "MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 10. "MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 9. "DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_reassembly_busecc_pend" "0,1"
newline
bitfld.long 0x04 8. "DDRSS0_SRC_P2M_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_src_p2m_busecc_pend" "0,1"
newline
bitfld.long 0x04 7. "DDRSS0_M2M_SRC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_m2m_src_vbuss_pend" "0,1"
newline
bitfld.long 0x04 6. "VBUSP_DMSC_CBASS_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_dmsc_cbass_edc_ctrl_busecc_2_dummy_pend" "0,1"
newline
bitfld.long 0x04 5. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_VBUSP_DDRSS0_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_p2p_bridge_vbusp_ddrss0_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_2_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x04 3. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_REASSEMBLY_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x04 2. "MSMC_J7ES_CFG_WRAP_CBASS_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_VBUSP_GICSS_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "EN_MSMC_P3_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p3_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
newline
bitfld.long 0x04 0. "EN_MSMC_P2_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_DUMMY_ENABLE_CLR,Interrupt Enable Clear Register for en_msmc_p2_vbusp_cfg_src_p2m_reassembly_busecc_dummy_pend" "0,1"
group.long 0x600++0x0F
line.long 0x00 "MSMC_WRAP_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSMC_WRAP_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR2"
tree "COMPUTE_CLUSTER0_MSMC_ECC_AGGR2"
base ad:0x4D20000800
rgroup.long 0x800++0x03
line.long 0x00 "MSMC_WRAP_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x808++0x0B
line.long 0x00 "MSMC_WRAP_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSMC_WRAP_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSMC_WRAP_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x83C++0x07
line.long 0x00 "MSMC_WRAP_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 2. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1"
bitfld.long 0x04 1. "DDRSS0_ASAFE_SI_PEND,Interrupt Pending Status for ddrss0_asafe_si_pend" "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR2_PEND,Interrupt Pending Status for edc_ctrl_eccaggr2_pend" "0,1"
group.long 0x880++0x03
line.long 0x00 "MSMC_WRAP_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1"
bitfld.long 0x00 1. "DDRSS0_ASAFE_SI_ENABLE_SET,Interrupt Enable Set Register for ddrss0_asafe_si_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR2_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr2_pend" "0,1"
group.long 0x8C0++0x03
line.long 0x00 "MSMC_WRAP_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1"
bitfld.long 0x00 1. "DDRSS0_ASAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_asafe_si_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR2_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr2_pend" "0,1"
group.long 0x93C++0x07
line.long 0x00 "MSMC_WRAP_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 2. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_PEND,Interrupt Pending Status for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1"
bitfld.long 0x04 1. "DDRSS0_ASAFE_SI_PEND,Interrupt Pending Status for ddrss0_asafe_si_pend" "0,1"
newline
bitfld.long 0x04 0. "EDC_CTRL_ECCAGGR2_PEND,Interrupt Pending Status for edc_ctrl_eccaggr2_pend" "0,1"
group.long 0x980++0x03
line.long 0x00 "MSMC_WRAP_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1"
bitfld.long 0x00 1. "DDRSS0_ASAFE_SI_ENABLE_SET,Interrupt Enable Set Register for ddrss0_asafe_si_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR2_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_eccaggr2_pend" "0,1"
group.long 0x9C0++0x03
line.long 0x00 "MSMC_WRAP_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for vbusp_cfg_ecc_aggr2_p2p_dst_busecc_pend" "0,1"
bitfld.long 0x00 1. "DDRSS0_ASAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for ddrss0_asafe_si_pend" "0,1"
newline
bitfld.long 0x00 0. "EDC_CTRL_ECCAGGR2_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_eccaggr2_pend" "0,1"
group.long 0xA00++0x0F
line.long 0x00 "MSMC_WRAP_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSMC_WRAP_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSMC_WRAP_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSMC_WRAP_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "CPSW0_ALE"
tree "CPSW0_NUSS_ALE"
base ad:0xC000000
rgroup.long 0x3E000++0x17
line.long 0x00 "CPSW_ALE_MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE module"
hexmask.long.word 0x00 16.--31. 1. "MODULE_ID,ALE module ID"
bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_ALE_STATUS,The ALE status provides information on the ALE configuration and state"
bitfld.long 0x04 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table" "0,1"
bitfld.long 0x04 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table" "0,1"
newline
hexmask.long.byte 0x04 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8"
bitfld.long 0x04 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
newline
bitfld.long 0x04 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
bitfld.long 0x04 0.--4. "KLUENTRIES,This is the number of table entries total divided by 1024" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports"
bitfld.long 0x08 31. "ENABLE_ALE,Enable ALE" "0,1"
bitfld.long 0x08 30. "CLEAR_TABLE,Clear ALE address table" "0,1"
newline
bitfld.long 0x08 29. "AGE_OUT_NOW,Age Out Address Table Now" "0,1"
bitfld.long 0x08 24.--27. "MIRROR_DP,Mirror Destination Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 21.--23. "UPD_BW_CTRL,The UPD_BW_CTRL field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--19. "MIRROR_TOP,Mirror To Port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 15. "UPD_STATIC,Update Static Entries" "0,1"
bitfld.long 0x08 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn" "0,1"
newline
bitfld.long 0x08 12. "MIRROR_MEN,Mirror Match Entry Enable" "0,1"
bitfld.long 0x08 11. "MIRROR_DEN,Mirror Destination Port Enable" "0,1"
newline
bitfld.long 0x08 10. "MIRROR_SEN,Mirror Source Port Enable" "0,1"
bitfld.long 0x08 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host" "0,1"
newline
bitfld.long 0x08 7. "LEARN_NO_VLANID,Learn No VID" "0,1"
bitfld.long 0x08 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode" "0,1"
bitfld.long 0x08 4. "ENABLE_BYPASS,ALE Bypass" "0,1"
newline
bitfld.long 0x08 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode" "0,1"
bitfld.long 0x08 2. "ALE_VLAN_AWARE,ALE VLAN Aware" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode" "0,1"
bitfld.long 0x08 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "0,1"
line.long 0x0C "CPSW_ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports"
bitfld.long 0x0C 31. "TRK_EN_DST,Trunk Enable Destination Address" "0,1"
bitfld.long 0x0C 30. "TRK_EN_SRC,Trunk Enable Source Address" "0,1"
newline
bitfld.long 0x0C 29. "TRK_EN_PRI,Trunk Enable Priority" "0,1"
bitfld.long 0x0C 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN" "0,1"
newline
bitfld.long 0x0C 25. "TRK_EN_SIP,Trunk Enable Source IP Address" "0,1"
bitfld.long 0x0C 24. "TRK_EN_DIP,Trunk Enable Destination IP Address" "0,1"
newline
bitfld.long 0x0C 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet" "0,1"
bitfld.long 0x0C 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set" "0,1"
newline
bitfld.long 0x0C 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found" "0,1"
bitfld.long 0x0C 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match" "0,1"
newline
bitfld.long 0x0C 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0C 0.--9. 1. "MIRROR_MIDX,Mirror Index"
line.long 0x10 "CPSW_ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value"
hexmask.long.tbyte 0x10 0.--19. 1. "ALE_PRESCALE,ALE Prescale"
line.long 0x14 "CPSW_ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur"
bitfld.long 0x14 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable" "0,1"
bitfld.long 0x14 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable" "0,1"
newline
hexmask.long.tbyte 0x14 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer"
group.long 0x3E01C++0x07
line.long 0x00 "CPSW_ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header"
hexmask.long.byte 0x00 24.--31. 1. "IP_NXT_HDR3,The IP_NXT_HDR3 is the forth protocol or next header compared when enabled"
hexmask.long.byte 0x00 16.--23. 1. "IP_NXT_HDR2,The IP_NXT_HDR2 is the third protocol or next header compared when enabled"
newline
hexmask.long.byte 0x00 8.--15. 1. "IP_NXT_HDR1,The IP_NXT_HDR1 is the second protocol or next header compared when enabled"
hexmask.long.byte 0x00 0.--7. 1. "IP_NXT_HDR0,The IP_NXT_HDR0 is the first protocol or next header compared when enabled"
line.long 0x04 "CPSW_ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries"
bitfld.long 0x04 31. "TABLEWR,Table" "0,1"
hexmask.long.word 0x04 0.--9. 1. "TABLEIDX,The table index is used to determine which lookup table entry is read or written"
group.long 0x3E034++0x0F
line.long 0x00 "CPSW_ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry"
hexmask.long.word 0x00 0.--10. 1. "TABLEWRD2,Table Entry bits [75:64]"
line.long 0x04 "CPSW_ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry"
line.long 0x08 "CPSW_ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry"
line.long 0x0C "CPSW_Iy_ALE_PORTCTL0_y,The ALE Port Control Register sets the port specific modes of operation"
hexmask.long.byte 0x0C 24.--31. 1. "Iy_REG_Py_BCAST_LIMIT,Broadcast Packet Rate Limit"
hexmask.long.byte 0x0C 16.--23. 1. "Iy_REG_Py_MCAST_LIMIT,Multicast Packet Rate Limit"
newline
bitfld.long 0x0C 15. "Iy_REG_Py_DROP_DOUBLE_VLAN,Drop Double VLAN" "0,1"
bitfld.long 0x0C 14. "Iy_REG_Py_DROP_DUAL_VLAN,Drop Dual VLAN" "0,1"
newline
bitfld.long 0x0C 13. "Iy_REG_Py_MACONLY_CAF,Mac Only Copy All Frames" "0,1"
bitfld.long 0x0C 12. "Iy_REG_Py_DIS_PAUTHMOD,Disable Port authorization" "0,1"
newline
bitfld.long 0x0C 11. "Iy_REG_Py_MACONLY,MAC Only" "0,1"
bitfld.long 0x0C 10. "Iy_REG_Py_TRUNKEN,Trunk Enable" "0,1"
newline
bitfld.long 0x0C 8.--9. "Iy_REG_Py_TRUNKNUM,Trunk Number" "0,1,2,3"
bitfld.long 0x0C 7. "Iy_REG_Py_MIRROR_SP,Mirror Source Port" "0,1"
newline
bitfld.long 0x0C 5. "Iy_REG_Py_NO_SA_UPDATE,No Source Address Update" "0,1"
bitfld.long 0x0C 4. "Iy_REG_Py_NO_LEARN,No Learn" "0,1"
newline
bitfld.long 0x0C 3. "Iy_REG_Py_VID_INGRESS_CHECK,VLAN Ingress Check" "0,1"
bitfld.long 0x0C 2. "Iy_REG_Py_DROP_UN_TAGGED,If Drop Untagged" "0,1"
newline
bitfld.long 0x0C 0.--1. "Iy_REG_Py_PORTSTATE,Port State" "0,1,2,3"
group.long 0x3E090++0x0F
line.long 0x00 "CPSW_ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID"
hexmask.long.word 0x00 0.--8. 1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List"
line.long 0x04 "CPSW_ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID"
hexmask.long.word 0x04 0.--8. 1. "UVLAN_UNREG_MCAST_FLOOD_MASK,Unknown VLAN Unregister Multicast Flood Mask"
line.long 0x08 "CPSW_ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID"
hexmask.long.word 0x08 0.--8. 1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask"
line.long 0x0C "CPSW_ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed"
hexmask.long.word 0x0C 0.--8. 1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask"
group.long 0x3E0B8++0x07
line.long 0x00 "CPSW_ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters"
bitfld.long 0x00 15. "PBCAST_DIAG,When set and the PORT_DIAG is set to zero will allow all ports to see the same stat diagnostic increment" "0,1"
bitfld.long 0x00 8.--11. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CPSW_ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port"
hexmask.long.word 0x04 0.--8. 1. "OAM_LB_CTRL,The OAM_LB_CTRL bit field allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an"
group.long 0x3E0FC++0x17
line.long 0x00 "CPSW_ALE_EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions"
abitfld.long 0x00 24.--31. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations" "0x00=NOP,0xFF=Swaps source address (SA) and destination.."
bitfld.long 0x00 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions" "0,1"
hexmask.long.word 0x00 0.--8. 1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to"
line.long 0x04 "CPSW_ALE_POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching"
bitfld.long 0x04 31. "PORT_MEN,Port Match Enable" "0,1"
bitfld.long 0x04 30. "TRUNKID,Trunk ID" "0,1"
newline
bitfld.long 0x04 25.--28. "PORT_NUM,Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 19. "PRI_MEN,Priority Match Enable" "0,1"
newline
bitfld.long 0x04 16.--18. "PRI_VAL,Priority Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "ONU_MEN,OUI Match Enable" "0,1"
newline
hexmask.long.word 0x04 0.--9. 1. "ONU_INDEX,OUI Table Entry Index"
line.long 0x08 "CPSW_ALE_POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses"
bitfld.long 0x08 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1"
hexmask.long.word 0x08 16.--25. 1. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry"
newline
bitfld.long 0x08 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1"
hexmask.long.word 0x08 0.--9. 1. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry"
line.long 0x0C "CPSW_ALE_POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses"
bitfld.long 0x0C 31. "OVLAN_MEN,Outer VLAN Match Enable" "0,1"
hexmask.long.word 0x0C 16.--25. 1. "OVLAN_INDEX,Outer VLAN Table Entry Index"
newline
bitfld.long 0x0C 15. "IVLAN_MEN,Inner VLAN Match Enable" "0,1"
hexmask.long.word 0x0C 0.--9. 1. "IVLAN_INDEX,Inner VLAN Table Entry Index"
line.long 0x10 "CPSW_ALE_POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address"
bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable" "0,1"
hexmask.long.word 0x10 16.--25. 1. "ETHERTYPE_INDEX,EtherType Table Entry Index"
newline
bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable" "0,1"
hexmask.long.word 0x10 0.--9. 1. "IPSRC_INDEX,IP Source Address Table Entry Index"
line.long 0x14 "CPSW_ALE_POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address"
bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable" "0,1"
hexmask.long.word 0x14 16.--25. 1. "IPDST_INDEX,IP Destination Address Table Entry Index"
group.long 0x3E118++0x17
line.long 0x00 "CPSW_ALE_POLICECFG6,If the counter is negative the packet will be marked RED. else it can be YELLOW or GREEN based on the CIR counter"
line.long 0x04 "CPSW_ALE_POLICECFG7,If the counter is positive the packet will be marked GREEN. else it can be YELLOW or RED based on the PIR counter"
line.long 0x08 "CPSW_ALE_POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry"
bitfld.long 0x08 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written"
line.long 0x0C "CPSW_ALE_POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules"
bitfld.long 0x0C 31. "POLICING_EN,Policing Enable" "0,1"
bitfld.long 0x0C 29. "RED_DROP_EN,RED Drop Enable" "0,1"
newline
bitfld.long 0x0C 28. "YELLOW_DROP_EN,WELLOW Drop Enable" "0,1"
bitfld.long 0x0C 24.--26. "YELLOWTHRESH,Yellow Threshold" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 22.--23. "POLMCHMODE,Policing Match Mode" "0,1,2,3"
bitfld.long 0x0C 21. "PRIORITY_THREAD_EN,Priority Thread Enable" "0,1"
newline
bitfld.long 0x0C 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable" "0,1"
line.long 0x10 "CPSW_ALE_POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition"
bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear" "0,1"
bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED" "0,1"
newline
bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW" "0,1"
bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected" "0,1"
newline
hexmask.long.byte 0x10 0.--6. 1. "POL_TEST_IDX,Policer Test Index"
line.long 0x14 "CPSW_ALE_POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier"
bitfld.long 0x14 31. "POL_HIT,Policer Hit" "0,1"
bitfld.long 0x14 30. "POL_REDHIT,Policer Hit RED" "0,1"
newline
bitfld.long 0x14 29. "POL_YELLOWHIT,Policer Hit YELLOW" "0,1"
group.long 0x3E134++0x0B
line.long 0x00 "CPSW_ALE_THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched"
bitfld.long 0x00 15. "DEFTHREAD_EN,Default Tread Enable" "0,1"
bitfld.long 0x00 0.--5. "DEFTHREADVAL,Default Thread Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_ALE_THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host"
hexmask.long.byte 0x04 0.--6. 1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the Classifier Index"
line.long 0x08 "CPSW_ALE_THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry"
bitfld.long 0x08 15. "THREAD_EN,Thread Enable" "0,1"
bitfld.long 0x08 0.--5. "THREADVAL,Thread Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "CPSW0_CONTROL"
tree "CPSW0_NUSS_CONTROL"
base ad:0xC000000
rgroup.long 0x20000++0x07
line.long 0x00 "CPSW_ID_VER_REG,CPSW ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification Value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_VER,Minor Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_CONTROL_REG,CPSW Switch Control"
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
bitfld.long 0x04 18. "EST_ENABLE,Enhanced Scheduled Traffic enable (EST)" "0,1"
bitfld.long 0x04 17. "IET_ENABLE,Intersperced Express Traffic enable (IET)" "0,1"
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bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
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bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
bitfld.long 0x04 12. "P0_TX_CRC_TYPE," "0,1"
bitfld.long 0x04 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
bitfld.long 0x04 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
bitfld.long 0x04 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
bitfld.long 0x04 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
bitfld.long 0x04 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
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bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
bitfld.long 0x04 0. "S_CN_SWITCH,Service or Customer VLAN switch" "0,1"
group.long 0x20010++0x37
line.long 0x00 "CPSW_EM_CONTROL_REG,CPSW Emulation Control Register"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "CPSW_STAT_PORT_EN_REG,CPSW Statistics Port Enable Register"
bitfld.long 0x04 8. "P8_STAT_EN,Port 8 Statistics Enable (if N > 8)" "0,1"
bitfld.long 0x04 7. "P7_STAT_EN,Port 7 Statistics Enable (if N > 7)" "0,1"
bitfld.long 0x04 6. "P6_STAT_EN,Port 6 Statistics Enable (if N > 6)" "0,1"
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bitfld.long 0x04 5. "P5_STAT_EN,Port 5 Statistics Enable (if N > 5)" "0,1"
bitfld.long 0x04 4. "P4_STAT_EN,Port 4 Statistics Enable (if N > 4)" "0,1"
bitfld.long 0x04 3. "P3_STAT_EN,Port 3 Statistics Enable (if N > 3)" "0,1"
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bitfld.long 0x04 2. "P2_STAT_EN,Port 2 Statistics Enable (if N > 2)" "0,1"
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x08 "CPSW_PTYPE_REG,CPSW Transmit Priority Type"
bitfld.long 0x08 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate (if N > 8)" "0,1"
bitfld.long 0x08 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate (if N > 7)" "0,1"
bitfld.long 0x08 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate (if N > 6)" "0,1"
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bitfld.long 0x08 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate (if N > 5)" "0,1"
bitfld.long 0x08 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate (if N > 4)" "0,1"
bitfld.long 0x08 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate (if N > 3)" "0,1"
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bitfld.long 0x08 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate (if N > 2)" "0,1"
bitfld.long 0x08 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
bitfld.long 0x08 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
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bitfld.long 0x08 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_SOFT_IDLE_REG,CPSW Software Idle Register"
bitfld.long 0x0C 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "CPSW_THRU_RATE_REG,CPSW Thru Rate Register"
bitfld.long 0x10 12.--15. "SL_RX_THRU_RATE,Ethernet Port Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "P0_RX_THRU_RATE,CPPI FIFO (port 0) receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CPSW_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold Register"
bitfld.long 0x14 0.--4. "GAP_THRESH,Ethernet Port Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "CPSW_TX_START_WDS_REG,CPSW Transmit FIFO Start Words Register"
hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words"
line.long 0x1C "CPSW_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value Register"
hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x20 "CPSW_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x20 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "CPSW_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear Register"
bitfld.long 0x24 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "CPSW_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low Register"
hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
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hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x2C "CPSW_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High Register"
hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
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hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x30 "CPSW_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low Register"
hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
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hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x34 "CPSW_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High Register"
hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
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hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x07
line.long 0x00 "CPSW_VLAN_LTYPE_REG,VLAN LTYPE Outer and Inner Register"
hexmask.long.word 0x00 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
hexmask.long.word 0x00 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
line.long 0x04 "CPSW_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain Register"
hexmask.long.byte 0x04 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
group.long 0x20100++0x1F
line.long 0x00 "CPSW_TX_PRI0_MAXLEN_REG,Priority 0 Maximum Transmit Packet Length Register"
hexmask.long.word 0x00 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Packet Length"
line.long 0x04 "CPSW_TX_PRI1_MAXLEN_REG,Priority 1 Maximum Transmit Packet Length Register"
hexmask.long.word 0x04 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Packet Length"
line.long 0x08 "CPSW_TX_PRI2_MAXLEN_REG,Priority 2 Maximum Transmit Packet Length Register"
hexmask.long.word 0x08 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Packet Length"
line.long 0x0C "CPSW_TX_PRI3_MAXLEN_REG,Priority 3 Maximum Transmit Packet Length Register"
hexmask.long.word 0x0C 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Packet Length"
line.long 0x10 "CPSW_TX_PRI4_MAXLEN_REG,Priority 4 Maximum Transmit Packet Length Register"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Packet Length"
line.long 0x14 "CPSW_TX_PRI5_MAXLEN_REG,Priority 5 Maximum Transmit Packet Length Register"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Packet Length"
line.long 0x18 "CPSW_TX_PRI6_MAXLEN_REG,Priority 6 Maximum Transmit Packet Length Register"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Packet Length"
line.long 0x1C "CPSW_TX_PRI7_MAXLEN_REG,Priority 7 Maximum Transmit Packet Length Register"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Packet Length"
group.long 0x21004++0x07
line.long 0x00 "CPSW_P0_CONTROL_REG,CPPI Port 0 Control Register"
bitfld.long 0x00 18. "RX_REMAP_DSCP_V6,Port 0 receive remap thread to DSCP IPV6 priority" "0,1"
bitfld.long 0x00 17. "RX_REMAP_DSCP_V4,Port 0 receive remap thread to DSCP IPV6 priority" "0,1"
bitfld.long 0x00 16. "RX_REMAP_VLAN,Port 0 receive remap thread to VLAN" "0,1"
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bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port 0 receive ECC Error Enable" "0,1"
bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port 0 transmit ECC Error Enable" "0,1"
bitfld.long 0x00 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
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bitfld.long 0x00 1. "DSCP_IPV4_EN,Port 0 IPV4 DSCP enable" "0,1"
bitfld.long 0x00 0. "RX_CHECKSUM_EN,Port 0 Receive (port 0 ingress) Checksum Enable" "0,1"
line.long 0x04 "CPSW_P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset Register"
hexmask.long.word 0x04 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
rgroup.long 0x21010++0x1B
line.long 0x00 "CPSW_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count Register"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "RX_BLK_CNT,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_P0_PORT_VLAN_REG,CPPI Port 0 VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "CPSW_P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPSW_P0_PRI_CTL_REG,CPPI Port 0 Priority Control"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
bitfld.long 0x0C 8. "RX_PTYPE,Receive Priority Type" "0,1"
line.long 0x10 "CPSW_P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "CPSW_P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length"
line.long 0x18 "CPSW_P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority Register"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21030++0x0B
line.long 0x00 "CPSW_P0_IDLE2LPI_REG,Port 0 EEE LPI to wake counter load value"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value"
line.long 0x04 "CPSW_P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter"
hexmask.long.tbyte 0x04 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value"
line.long 0x08 "CPSW_P0_EEE_STATUS_REG,Port 0 EEE status"
bitfld.long 0x08 6. "TX_FIFO_EMPTY,CPPI (Port 0) Transmit FIFO packet count zero" "0,1"
bitfld.long 0x08 5. "RX_FIFO_EMPTY,CPPI (Port 0) Receive FIFO packet count zero" "0,1"
bitfld.long 0x08 4. "TX_FIFO_HOLD,CPPI (Port 0) Transmit FIFO hold" "0,1"
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bitfld.long 0x08 3. "TX_WAKE,CPPI (Port 0) Receive Wake Time" "0,1"
bitfld.long 0x08 2. "TX_LPI,CPPI (Port 0) transmit LPI state" "0,1"
bitfld.long 0x08 1. "RX_LPI,CPPI (Port 0) receive LPI state" "0,1"
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bitfld.long 0x08 0. "WAIT_IDLE2LPI,CPPI (Port 0) Transmit Wait Idle to LPI" "0,1"
rgroup.long 0x21050++0x03
line.long 0x00 "CPSW_P0_FIFO_STATUS_REG,Port 0 FIFO Status"
hexmask.long.byte 0x00 0.--7. 1. "TX_PRI_ACTIVE,Port 0 Transmit FIFO Priority Active"
group.long 0x21120++0x03
line.long 0x00 "CPSW_P0_RX_DSCP_MAP_REG_y,CPPI Port 0 Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
group.long 0x21140++0x03
line.long 0x00 "CPSW_P0_PRI_CIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Committed Information Rate Registers"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority 'y' Committed Information Rate Count Value"
group.long 0x21160++0x03
line.long 0x00 "CPSW_P0_PRI_EIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Excess Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N EIR"
group.long 0x21180++0x1F
line.long 0x00 "CPSW_P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CPSW_P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "CPSW_P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CPSW_P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "CPSW_P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "CPSW_P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21300++0x07
line.long 0x00 "CPSW_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
hexmask.long.byte 0x00 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x00 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x00 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
line.long 0x04 "CPSW_P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B"
hexmask.long.byte 0x04 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x04 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value"
hexmask.long.byte 0x04 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x04 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value"
group.long 0x21320++0x03
line.long 0x00 "CPSW_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
bitfld.long 0x00 28.--31. "PRI7,Priority 7 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PRI6,Priority 6 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "PRI5,Priority 5 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PRI4,Priority 4 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "PRI3,Priority 3 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PRI2,Priority 2 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PRI1,Priority 1 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PRI0,Priority 0 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x22000++0x03
hide.long 0x00 "CPSW_PN_RESERVED_REG_k,Reserved"
group.long 0x22004++0x07
line.long 0x00 "CPSW_PN_CONTROL_REG_k,Enet Port N Control"
bitfld.long 0x00 17. "EST_PORT_EN,EST Port Enable" "0,1"
bitfld.long 0x00 16. "IET_PORT_EN,Intersperced Express Traffic (IET) Port Enable" "0,1"
bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port N receive ECC Error Enable" "0,1"
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bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port N transmit ECC Error Enable" "0,1"
bitfld.long 0x00 12. "TX_LPI_CLKSTOP_EN,Transmit LPI Clock Stop Enable" "0,1"
bitfld.long 0x00 2. "DSCP_IPV6_EN,IPV6 DSCP enable" "0,1"
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bitfld.long 0x00 1. "DSCP_IPV4_EN,IPV4 DSCP enable" "0,1"
line.long 0x04 "CPSW_PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
hexmask.long.byte 0x04 8.--15. 1. "TX_MAX_BLKS,Transmit Max Blocks"
hexmask.long.byte 0x04 0.--7. 1. "RX_MAX_BLKS,Receive Max Blocks"
rgroup.long 0x22010++0x1B
line.long 0x00 "CPSW_PN_BLK_CNT_REG_k,Enet Port N FIFO Block Usage Count Offset = 00022010h + (N * 1000h); where k = 0h to 1h"
bitfld.long 0x00 16.--21. "RX_BLK_CNT_P,Receive Express Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "RX_BLK_CNT_E,Receive Express Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_PN_PORT_VLAN_REG_k,Enet Port N VLAN Offset = 00022014h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "CPSW_PN_TX_PRI_MAP_REG_k,Enet Port N Tx Header Pri to Switch Pri Mapping Offset = 00022018h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPSW_PN_PRI_CTL_REG_k,Enet Port N Priority Control Offset = 0002201Ch + (k * 1000h); where k = 0h to 1h"
hexmask.long.byte 0x0C 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
bitfld.long 0x0C 12.--15. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CPSW_PN_RX_PRI_MAP_REG_k,Enet Port N RX Pkt Pri to Header Pri Map Offset = 00022020h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "CPSW_PN_RX_MAXLEN_REG_k,Enet Port N Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length"
line.long 0x18 "CPSW_PN_TX_BLKS_PRI_REG_k,Enet Port N Transmit Block Sub Per Priority Offset = 00022028h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x22030++0x0B
line.long 0x00 "CPSW_PN_IDLE2LPI_REG_k,Enet Port N EEE Idle to LPI counter Offset = 00022030h + (k * 1000h); where k = 0h to 1h"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,EEE Idle to LPI counter load value"
line.long 0x04 "CPSW_PN_LPI2WAKE_REG_k,Enet Port N EEE LPI to wake counter Offset = 00022034h + (k * 1000h); where k = 0h to 1h"
hexmask.long.tbyte 0x04 0.--23. 1. "COUNT,EEE LPI to wake counter load value"
line.long 0x08 "CPSW_PN_EEE_STATUS_REG_k,Enet Port N EEE status Offset = 00022038h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x08 6. "TX_FIFO_EMPTY,Port N Transmit FIFO packet count zero" "0,1"
bitfld.long 0x08 5. "RX_FIFO_EMPTY,Port N Receive FIFO packet count zero" "0,1"
bitfld.long 0x08 4. "TX_FIFO_HOLD,Port N Transmit FIFO hold" "0,1"
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bitfld.long 0x08 3. "TX_WAKE,Port N Receive Wake Time" "0,1"
bitfld.long 0x08 2. "TX_LPI,Port N Transmit LPI" "0,1"
bitfld.long 0x08 1. "RX_LPI,Port N Receive LPI" "0,1"
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bitfld.long 0x08 0. "WAIT_IDLE2LPI,Transmit Wait Idle to LPI" "0,1"
group.long 0x22040++0x0B
line.long 0x00 "CPSW_PN_IET_CONTROL_REG_k,Enet Port N IET Control Offset = 00022040h + (k * 1000h); where k = 0h to 1h"
hexmask.long.byte 0x00 16.--23. 1. "MAC_PREMPT,Mac Preempt Queue - Indicates which transmit FIFO queues are sent to the preempt MAC"
bitfld.long 0x00 8.--10. "MAC_ADDFRAGSIZE,Mac Fragment Size - An integer in the range 0:7 indicating as a multiple of 64 the minimum additional length for nonfinal mPackets" "64,128,192,256,320,384,448,512"
bitfld.long 0x00 3. "MAC_LINKFAIL,Mac Link Fail - Link Fail Indicator to reset the verify state machine" "0,1"
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bitfld.long 0x00 2. "MAC_DISABLEVERIFY,Mac Disable Verify - Disables verification on the port when set" "0,1"
bitfld.long 0x00 1. "MAC_HOLD,Mac Hold - Hold Preemption on the port" "0,1"
bitfld.long 0x00 0. "MAC_PENABLE,Mac Preemption Enable - Port Preemption Enable" "0,1"
line.long 0x04 "CPSW_PN_IET_STATUS_REG_k,Enet Port N IET Status Offset = 00022044h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x04 3. "MAC_VERIFY_ERR,Mac Received Verify Packet with Errors - Set when a verify packet with errors is received" "0,1"
bitfld.long 0x04 2. "MAC_RESPOND_ERR,Mac Received Respond Packet with Errors - Set when a respond packet with errors is received" "0,1"
bitfld.long 0x04 1. "MAC_VERIFY_FAIL,Mac Verification Failed - Indication that verification was unsuccessful" "0,1"
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bitfld.long 0x04 0. "MAC_VERIFIED,Mac Verified - Indication that verification was successful" "0,1"
line.long 0x08 "CPSW_PN_IET_VERIFY_REG_k,Enet Port N IET VERIFY Offset = 00022048h + (k * 1000h); where k = 0h to 1h"
hexmask.long.tbyte 0x08 0.--23. 1. "MAC_VERIFY_CNT,Mac Verify Timeout Count - The number of wireside clocks contained in the verify timeout counter"
rgroup.long 0x22050++0x03
line.long 0x00 "CPSW_PN_FIFO_STATUS_REG_k,Enet Port N FIFO STATUS Offset = 00022050h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x00 18. "EST_BUFACT,EST RAM active buffer" "0,1"
bitfld.long 0x00 17. "EST_ADD_ERR,EST Address Error" "0,1"
bitfld.long 0x00 16. "EST_CNT_ERR,EST Fetch Count Error" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "TX_E_MAC_ALLOW,EST transmit MAC allow"
hexmask.long.byte 0x00 0.--7. 1. "TX_PRI_ACTIVE,EST Transmit Priority Active"
group.long 0x22060++0x03
line.long 0x00 "CPSW_PN_EST_CONTROL_REG_k,Enet Port N EST CONTROL Offset = 00022060h + (k * 1000h); where k = 0h to 1h"
hexmask.long.word 0x00 16.--25. 1. "EST_FILL_MARGIN,EST Fill Margin"
bitfld.long 0x00 8. "EST_FILL_EN,EST Fill Enable" "0,1"
bitfld.long 0x00 5.--7. "EST_TS_PRI,EST Timestamp Express Priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "EST_TS_ONEPRI,EST Timestamp One Express Priority" "0,1"
bitfld.long 0x00 3. "EST_TS_FIRST,EST Timestamp First Express Packet only" "0,1"
bitfld.long 0x00 2. "EST_TS_EN,EST Timestamp Enable" "0,1"
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bitfld.long 0x00 1. "EST_BUFSEL,EST Buffer Select" "0,1"
bitfld.long 0x00 0. "EST_ONEBUF,EST One Fetch Buffer" "0,1"
group.long 0x22120++0x03
line.long 0x00 "CPSW_PN_RX_DSCP_MAP_REG_k_y,Enet Port N Receive IPV4/IPV6 DSCP Map M Offset = 00022120h + (k * 1000h) + (y * 4h); where k = 0h to 1h. y = 0h to 7h"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
group.long 0x22140++0x03
line.long 0x00 "CPSW_PN_PRI_CIR_REG_k_y,Enet Port N Rx Priority P Committed Information Rate Value Offset = 00022140h + (k * 1000h) + (y * 4h); where k = 0h to 1h. y = 0h to 7h"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N committed information rate"
group.long 0x22160++0x03
line.long 0x00 "CPSW_PN_PRI_EIR_REG_k,Enet Port N Rx Priority P Excess Informatoin Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count"
group.long 0x22180++0x1F
line.long 0x00 "CPSW_PN_TX_D_THRESH_SET_L_REG_k,Enet Port N Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CPSW_PN_TX_D_THRESH_SET_H_REG_k,Enet Port N Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_PN_TX_D_THRESH_CLR_L_REG_k,Enet Port N Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_PN_TX_D_THRESH_CLR_H_REG_k,Enet Port N Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "CPSW_PN_TX_G_BUF_THRESH_SET_L_REG_k,Enet Port N Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CPSW_PN_TX_G_BUF_THRESH_SET_H_REG_k,Enet Port N Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "CPSW_PN_TX_G_BUF_THRESH_CLR_L_REG_k,Enet Port N Tx PFC Global Buffer Threshold Clr Low Offset = 00022198h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "CPSW_PN_TX_G_BUF_THRESH_CLR_H_REG_k,Enet Port N Tx PFC Global Buffer Threshold Clr High Offset = 0002219Ch + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22300++0x23
line.long 0x00 "CPSW_PN_TX_D_OFLOW_ADDVAL_L_REG_k,Enet Port N Tx Destination Out Flow Add Values Low"
bitfld.long 0x00 24.--28. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CPSW_PN_TX_D_OFLOW_ADDVAL_H_REG_k,Enet Port N Tx Destination Out Flow Add Values High"
bitfld.long 0x04 24.--28. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_PN_SA_L_REG_k,Enet Port N Tx Pause Frame Source Address Low Offset = 00022308h + (k * 1000h); where k = 0h to 1h"
hexmask.long.byte 0x08 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)"
hexmask.long.byte 0x08 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15-8 (byte 1)"
line.long 0x0C "CPSW_PN_SA_H_REG_k,Enet Port N Tx Pause Frame Source Address High"
hexmask.long.byte 0x0C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23-16 (byte 2)"
hexmask.long.byte 0x0C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31-24 (byte 3)"
hexmask.long.byte 0x0C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39-32 (byte 4)"
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hexmask.long.byte 0x0C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47-40 (byte 5)"
line.long 0x10 "CPSW_PN_TS_CTL_REG_k,Enet Port N Time Sync Control Offset = 00022310h + (k * 1000h); where k = 0h to 1h"
hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable"
bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Sync Transmit Annex E enable" "0,1"
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bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Sync Receive Annex E enable" "0,1"
bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable (transmit and receive)" "0,1"
bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Sync Transmit Annex D enable" "0,1"
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bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Sync Transmit Annex F enable" "0,1"
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bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Sync Receive Annex D enable" "0,1"
bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Sync Receive Annex F Enable" "0,1"
line.long 0x14 "CPSW_PN_TS_SEQ_LTYPE_REG_k,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
bitfld.long 0x14 16.--21. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
line.long 0x18 "CPSW_PN_TS_VLAN_LTYPE_REG_k,Enet Port N Time Sync VLAN2 and VLAN2"
hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
line.long 0x1C "CPSW_PN_TS_CTL_LTYPE2_REG_k,Enet Port N Time Sync Control and LTYPE 2"
bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
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bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
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bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
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hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
line.long 0x20 "CPSW_PN_TS_CTL2_REG_k,Enet Port N Time Sync Control 2"
bitfld.long 0x20 16.--21. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
group.long 0x22330++0x13
line.long 0x00 "CPSW_PN_MAC_CONTROL_REG_k,Enet Port N Mac Control"
bitfld.long 0x00 25. "EXT_EN_XGIG,10G External Enable" "0,1"
bitfld.long 0x00 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1"
bitfld.long 0x00 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1"
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bitfld.long 0x00 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1"
bitfld.long 0x00 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1"
bitfld.long 0x00 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
bitfld.long 0x00 18. "EXT_EN,External Control Enable" "0,1"
bitfld.long 0x00 17. "GIG_FORCE,Gigabit Mode Force" "0,1"
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bitfld.long 0x00 16. "IFCTL_B,Interface Control B" "0,1"
bitfld.long 0x00 15. "IFCTL_A,Interface Control A" "0,1"
bitfld.long 0x00 13. "XGMII_EN,XGMII Enable" "0,1"
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bitfld.long 0x00 12. "CRC_TYPE,Port CRC Type" "0,1"
bitfld.long 0x00 11. "CMD_IDLE,Command Idle" "0,1"
bitfld.long 0x00 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1"
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rbitfld.long 0x00 8. "XGIG,10 Gigabit Mode" "0,1"
bitfld.long 0x00 7. "GIG,Gigabit Mode" "0,1"
bitfld.long 0x00 6. "TX_PACE,Transmit Pacing Enable" "0,1"
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bitfld.long 0x00 5. "GMII_EN,GMII Enable" "0,1"
bitfld.long 0x00 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1"
bitfld.long 0x00 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
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bitfld.long 0x00 2. "MTEST,Manufacturing Test mode" "0,1"
bitfld.long 0x00 1. "LOOPBACK,Loop Back Mode" "0,1"
bitfld.long 0x00 0. "FULLDUPLEX,Full Duplex mode" "0,1"
line.long 0x04 "CPSW_PN_MAC_STATUS_REG_k,Enet Port N Mac Status Offset = 00022334h + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x04 31. "IDLE,Enet IDLE" "0,1"
bitfld.long 0x04 30. "E_IDLE,Express MAC is Idle" "0,1"
bitfld.long 0x04 29. "P_IDLE,Prempt MAC is Idle" "0,1"
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bitfld.long 0x04 28. "MAC_TX_IDLE,Mac Transmit Idle" "0,1"
bitfld.long 0x04 27. "TORF,Top of receive FIFO flow control trigger occurred" "0,1"
bitfld.long 0x04 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x04 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
hexmask.long.byte 0x04 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)"
bitfld.long 0x04 6. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
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bitfld.long 0x04 5. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
bitfld.long 0x04 4. "EXT_GIG,External GIG" "0,1"
bitfld.long 0x04 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1"
newline
bitfld.long 0x04 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1"
bitfld.long 0x04 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1"
line.long 0x08 "CPSW_PN_MAC_SOFT_RESET_REG_k,Enet Port N Mac Soft Reset"
bitfld.long 0x08 0. "SOFT_RESET,Software reset" "0,1"
line.long 0x0C "CPSW_PN_MAC_BOFFTEST_REG_k,Enet Port N Mac Backoff Test Offset = 0002233Ch + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x0C 26.--30. "PACEVAL,Pacing Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 16.--25. 1. "RNDNUM,Backoff Random Number Generator"
rbitfld.long 0x0C 12.--15. "COLL_COUNT,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--9. 1. "TX_BACKOFF,Backoff Count"
line.long 0x10 "CPSW_PN_MAC_RX_PAUSETIMER_REG_k,Enet Port N 802.3 Receive Pause Timer Offset = 00022340h + (k * 1000h); where k = 0h to 1h"
hexmask.long.word 0x10 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
group.long 0x22350++0x03
line.long 0x00 "CPSW_PN_MAC_RXN_PAUSETIMER_REG_k_y,Ethernet Port N PFC Priority 0 to Priority 7 Rx Pause Timer Registers"
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSETIMER,Rx 'y' Pause Timer Value"
group.long 0x22370++0x03
line.long 0x00 "CPSW_PN_MAC_TX_PAUSETIMER_REG_k,Enet Port N 802.3 Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,802.3 Tx Pause Timer Value"
group.long 0x22380++0x03
line.long 0x00 "CPSW_PN_MAC_TXN_PAUSETIMER_REG_k,Ethernet Port N PFC Priority 0 to Priority 7 Tx Pause Timer Registers"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,PFC Tx 'y' Pause Timer Value"
group.long 0x223A0++0x07
line.long 0x00 "CPSW_PN_MAC_EMCONTROL_REG_k,Enet Port N Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "CPSW_PN_MAC_TX_GAP_REG_k,Enet Port N Tx Inter Packet Gap"
hexmask.long.word 0x04 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap"
group.long 0x223AC++0x13
line.long 0x00 "CPSW_PN_INTERVLAN_OPX_POINTER_REG_k,Enet Port N Tx Egress InterVLAN Operation Pointer Offset = 000223ACh + (k * 1000h); where k = 0h to 1h"
bitfld.long 0x00 0.--2. "INTERVLAN_OPX_POINTER,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7"
line.long 0x04 "CPSW_PN_INTERVLAN_OPX_A_REG_k,Enet Port N Tx Egress InterVLAN A Offset = 000223B0h + (k * 1000h); where k = 0h to 1h"
hexmask.long.byte 0x04 24.--31. 1. "DA_23_16,Destination Address bits 23-16 - DA byte 4 on wire"
hexmask.long.byte 0x04 16.--23. 1. "DA_31_24,Destination Address bits 31-24 - DA byte 3 on wire"
hexmask.long.byte 0x04 8.--15. 1. "DA_39_32,Destination Address bits 39-32 - DA byte 2 on wire"
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hexmask.long.byte 0x04 0.--7. 1. "DA_47_40,Destination Address bits 47-40 - DA byte 1 on wire"
line.long 0x08 "CPSW_PN_INTERVLAN_OPX_B_REG_k,Enet Port N Tx Egress InterVLAN B Offset = 000223B4h + (k * 1000h); where k = 0h to 1h"
hexmask.long.byte 0x08 24.--31. 1. "SA_39_32,Source Address bits 39-32 - SA byte 2 on wire"
hexmask.long.byte 0x08 16.--23. 1. "SA_47_40,Source Address bits 47-40 - SA byte 1 on wire"
hexmask.long.byte 0x08 8.--15. 1. "DA_7_0,Destination Address bits 7-0 - DA byte 6 on wire"
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hexmask.long.byte 0x08 0.--7. 1. "DA_15_8,Destination Address bits 15-8 - DA byte 5 on wire"
line.long 0x0C "CPSW_PN_INTERVLAN_OPX_C_REG_k,Enet Port N Tx Egress InterVLAN C Offset = 000223B8h + (k * 1000h); where k = 0h to 1h"
hexmask.long.byte 0x0C 24.--31. 1. "SA_7_0,Source Address bits 7-0 - SA byte 6 on wire"
hexmask.long.byte 0x0C 16.--23. 1. "SA_15_8,Source Address bits 15-8 - SA byte 5 on wire"
hexmask.long.byte 0x0C 8.--15. 1. "SA_23_16,Source Address bits 23-16 - SA byte 4 on wire"
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hexmask.long.byte 0x0C 0.--7. 1. "SA_31_24,Source Address bits 31-24 - SA byte 3 on wire"
line.long 0x10 "CPSW_PN_INTERVLAN_OPX_D_REG_k,Enet Port N Tx Egress InterVLAN D"
hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D"
tree.end
tree.end
tree "CPSW0_CPINT"
tree "CPSW0_NUSS_CPINT"
base ad:0xC000000
rgroup.long 0x1000++0x03
line.long 0x00 "CPSW_INT_REVISION,Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1010++0x07
line.long 0x00 "CPSW_INT_EOI_REG,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CPSW_INT_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x1100++0x03
line.long 0x00 "CPSW_INT_ENABLE_REG_OUT_PULSE_0,Enable Register 0"
bitfld.long 0x00 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1"
bitfld.long 0x00 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1"
group.long 0x1300++0x03
line.long 0x00 "CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0,Enable Clear Register 0"
bitfld.long 0x00 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1"
bitfld.long 0x00 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1500++0x03
line.long 0x00 "CPSW_INT_STATUS_REG_OUT_PULSE_0,Status Register 0"
bitfld.long 0x00 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1"
bitfld.long 0x00 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x00 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1A80++0x03
line.long 0x00 "CPSW_INT_INTR_VECTOR_REG_OUT_PULSE,Interrupt Vector for out_pulse"
tree.end
tree.end
tree "CPSW0_CPTS"
tree "CPSW0_NUSS_CPTS"
base ad:0xC000000
rgroup.long 0x3D000++0x5B
line.long 0x00 "CPSW_CPTS_IDVER_REG,CPSW0_NUSS CPTS Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output time stamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 17. "TX_GENF_CLR_EN,GENF (and ESTF) Clear Enable" "A CPTS_GENFn output is not cleared when the..,A CPTS_GENFn output is cleared when the.."
newline
bitfld.long 0x04 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events" "0,1"
newline
bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
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bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
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bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
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bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
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bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
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bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
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bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
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bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
newline
bitfld.long 0x04 7. "TS_PPM_DIR,PPM Correction Direction" "0,1"
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bitfld.long 0x04 6. "TS_COMP_TOG,Time Stamp Compare Toggle mode" "0,1"
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bitfld.long 0x04 5. "MODE,64-Bit Mode" "0,1"
newline
bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable" "0,1"
newline
bitfld.long 0x04 3. "TSTAMP_EN,Host Receive Time Stamp Enable" "0,1"
newline
bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP Polarity" "0,1"
newline
bitfld.long 0x04 1. "INT_TEST,Interrupt Test" "0,1"
newline
bitfld.long 0x04 0. "CPTS_EN,Time Sync Enable" "0,1"
line.long 0x08 "CPSW_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select" "Selects CPSWHSDIV_CLKOUT2 clock,Selects MAINHSDIV_CLKOUT3 clock,Selects MCU_CPTS0_RFT_CLK I/O pin,Selects CPTS0_RFT_CLK I/O pin,Selects MCU_EXT_REFCLK0 I/O pin,Selects EXT_REFCLK1 I/O pin,Selects PCIE0_TXI0_CLK clock,Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL..,?..."
line.long 0x0C "CPSW_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x10 "CPSW_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x14 "CPSW_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x14 0. "TS_LOAD_EN,Time Stamp Load Enable" "0,1"
line.long 0x18 "CPSW_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value (lower 32-bits) Register"
line.long 0x1C "CPSW_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x20 "CPSW_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x24 "CPSW_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x28 "CPSW_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x2C "CPSW_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Value Register"
hexmask.long.byte 0x2C 0.--7. 1. "NUDGE,Time stamp Comparison Nudge Value"
line.long 0x30 "CPSW_CPTS_EVENT_POP_REG,Event Interrupt Pop Register"
bitfld.long 0x30 0. "EVENT_POP,Event Pop" "0,1"
line.long 0x34 "CPSW_CPTS_EVENT_0_REG,Lower 32-bits of the Event Value Register"
line.long 0x38 "CPSW_CPTS_EVENT_1_REG,Lower Middle 32-bits of the Event Value Register"
bitfld.long 0x38 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
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bitfld.long 0x38 24.--28. "PORT_NUMBER,Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x38 20.--23. "EVENT_TYPE,Time Sync Event Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x3C "CPSW_CPTS_EVENT_2_REG,Upper Middle 32-bits of the Event Value Register"
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,Domain"
line.long 0x40 "CPSW_CPTS_EVENT_3_REG,Upper 32-bits of the Event Value Register"
line.long 0x44 "CPSW_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value (upper 32-bits) Register"
line.long 0x48 "CPSW_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value (upper 32-bits) Register"
line.long 0x4C "CPSW_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x4C 0.--2. "ADD_VAL,The ts_add_value[2:0] is added to 1 to comprise the time stamp increment value" "0,1,2,3,4,5,6,7"
line.long 0x50 "CPSW_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Load Low Value (lower 32-bits) Register"
line.long 0x54 "CPSW_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM Load High Value (upper 32-bits) Register"
hexmask.long.word 0x54 0.--9. 1. "TS_PPM_HIGH_VAL,Time Stamp PPM High Value"
line.long 0x58 "CPSW_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x58 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge Value"
group.long 0x3D0E0++0x1B
line.long 0x00 "CPSW_GENF0_COMP_LOW_REG,Time Stamp Generate Function (GENF0) Comparison Low Value (lower 32-bits)"
line.long 0x04 "CPSW_GENF0_COMP_HIGH_REG,Time Stamp Generate Function (GENF0) Comparison high Value (upper 32-bits)"
line.long 0x08 "CPSW_GENF0_CONTROL_REG,Time Stamp Generate Function (GENF0) Control Registers"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
newline
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
line.long 0x0C "CPSW_GENF0_LENGTH_REG,Time Stamp Generate Function (GENF0) Length Value"
line.long 0x10 "CPSW_GENF0_PPM_LOW_REG,Time Stamp Generate Function (GENF0) PPM Low Value (lower 32-bits)"
line.long 0x14 "CPSW_GENF0_PPM_HIGH_REG,Time Stamp Generate Function (GENF0) PPM High Value (upper 32-bits)"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "CPSW_GENF0_NUDGE_REG,Time Stamp Generate Function (GENF0) Nudge Value Registers"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
group.long 0x3D100++0x1B
line.long 0x00 "CPSW_GENF1_COMP_LOW_REG,Time Stamp Generate Function (GENF1) Comparison Low Value"
line.long 0x04 "CPSW_GENF1_COMP_HIGH_REG,Time Stamp Generate Function (GENF1) Comparison high Value (upper 32-bits)"
line.long 0x08 "CPSW_GENF1_CONTROL_REG,Time Stamp Generate Function (GENF1) Control Register"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function (GENF1) Polarity Invert" "0,1"
newline
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function (GENF1) PPM Direction" "0,1"
line.long 0x0C "CPSW_GENF1_LENGTH_REG,Time Stamp Generate Function (GENF1) Length Value"
line.long 0x10 "CPSW_GENF1_PPM_LOW_REG,Time Stamp Generate Function (GENF1) PPM Low Value (lower 32-bits)"
line.long 0x14 "CPSW_GENF1_PPM_HIGH_REG,Time Stamp Generate Function (GENF1) PPM High Value (upper 32-bits)"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function (GENF1) PPM High Value"
line.long 0x18 "CPSW_GENF1_NUDGE_REG,Time Stamp Generate Function (GENF1) Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function (GENF1) Nudge Value"
group.long 0x3D200++0x1B
line.long 0x00 "CPSW_ESTF_COMP_LOW_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) Comparison Low Value"
line.long 0x04 "CPSW_ESTF_COMP_HIGH_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) Comparison high Value (upper 32-bits)"
line.long 0x08 "CPSW_ESTF_CONTROL_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) Control Register"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function (ESTFn where n = 1 to 8) Polarity Invert" "0,1"
newline
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function (ESTFn where n = 1 to 8) PPM Direction" "0,1"
line.long 0x0C "CPSW_ESTF_LENGTH_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) Length Value"
line.long 0x10 "CPSW_ESTF_PPM_LOW_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) PPM Low Value (lower 32-bits)"
line.long 0x14 "CPSW_ESTF_PPM_HIGH_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) PPM High Value (upper 32-bits)"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTFn (n = 1 to 8) Generate Function PPM High Value"
line.long 0x18 "CPSW_ESTF_NUDGE_REG_l,Time Stamp Generate Function (ESTFn. where n = 1 to 8) Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTFn (n = 1 to 8) Generate Function Nudge Value"
tree.end
tree.end
tree "CPSW0_ECC"
tree "CPSW0_ECC"
base ad:0x2A21000
rgroup.long 0x00++0x03
line.long 0x00 "CPSW_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CPSW_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPSW_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CPSW_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CPSW_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CPSW_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
newline
bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CPSW_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CPSW_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CPSW_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CPSW_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
newline
bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CPSW_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CPSW_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPSW_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for SVBUS timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPSW_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for SVBUS timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPSW_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for SVBUS timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPSW_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for SVBUS timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "CPSW0_MDIO"
tree "CPSW0_NUSS_MDIO"
base ad:0xC000000
rgroup.long 0xF00++0x47
line.long 0x00 "CPSW_MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_MDIO_CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
line.long 0x08 "CPSW_MDIO_ALIVE_REG,MDIO Alive Register"
line.long 0x0C "CPSW_MDIO_LINK_REG,MDIO Link Register"
line.long 0x10 "CPSW_MDIO_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "CPSW_MDIO_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "CPSW_MDIO_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "CPSW_MDIO_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "CPSW_MDIO_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
line.long 0x24 "CPSW_MDIO_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
line.long 0x28 "CPSW_MDIO_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for" "0,1,2,3"
line.long 0x2C "CPSW_MDIO_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for" "0,1,2,3"
line.long 0x30 "CPSW_MDIO_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin Value" "0,1"
line.long 0x34 "CPSW_MDIO_POLL_REG,MDIO Poll Register"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "IPG,Polling Inter Packet Gap Value"
line.long 0x38 "CPSW_MDIO_POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "CPSW_MDIO_CLAUS45_REG,MDIO Clause45 Enable Register"
line.long 0x40 "CPSW_MDIO_USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO User Address 0"
line.long 0x44 "CPSW_MDIO_USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO User Address 1"
group.long 0xF80++0x07
line.long 0x00 "CPSW_MDIO_USER_ACCESS_REG_k,MDIO User Access Register"
bitfld.long 0x00 31. "GO,Go" "0,1"
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "CPSW_MDIO_USER_PHY_SEL_REG_k,MDIO User PHY Select Register Offset = F84h + (k * 8h); where k = 0h to 1h"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "CPSW0_NUSS_Subsystem__SS_"
tree "CPSW0_NUSS_SS"
base ad:0xC000000
rgroup.long 0x00++0x17
line.long 0x00 "CPSW_SS_CPSW_NUSS_IDVER_REG,ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_SS_SYNCE_COUNT_REG,SyncE Count Register"
line.long 0x08 "CPSW_SS_SYNCE_MUX_REG,SyncE Mux Register"
bitfld.long 0x08 0.--5. "SYNCE_SEL,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CPSW_SS_CONTROL_REG,Control Register"
bitfld.long 0x0C 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode" "0,1"
bitfld.long 0x0C 0. "EEE_EN,Energy Efficient Ethernet Enable" "0,1"
line.long 0x10 "CPSW_SS_SGMII_NON_FIBER_MODE_REG,SGMII NON FIBER Mode Register"
hexmask.long.byte 0x10 0.--7. 1. "SGMII_NON_FIBER_MODE,This register bit goes to the CPSGMII mode input only"
line.long 0x14 "CPSW_SS_SERDES_RESET_ISO_REG,SyncE Mux Register"
hexmask.long.byte 0x14 0.--7. 1. "SERDES_RESET_ISO,These bits control whether the SERDES ignores the hard reset for isolation or not"
rgroup.long 0x1C++0x03
line.long 0x00 "CPSW_SS_SUBSSYSTEM_STATUS_REG,Subsystem Status Register"
bitfld.long 0x00 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
rgroup.long 0x30++0x1F
line.long 0x00 "CPSW_SS_RGMII1_STATUS_REG,RGMII Port 1 Status Register"
bitfld.long 0x00 3. "FULLDUPLEX,RGMII Port 1 full duplex" "0,1"
bitfld.long 0x00 1.--2. "SPEED,RGMII Port 1 speed" "0,1,2,3"
bitfld.long 0x00 0. "LINK,RGMII Port 1 link indicator" "0,1"
line.long 0x04 "CPSW_SS_RGMII2_STATUS_REG,RGMII Port 2 Status Register"
bitfld.long 0x04 3. "FULLDUPLEX,RGMII Port 2 full dulex" "0,1"
bitfld.long 0x04 1.--2. "SPEED,RGMII Port 2 speed" "0,1,2,3"
bitfld.long 0x04 0. "LINK,RGMII Port 2 link indicator" "0,1"
line.long 0x08 "CPSW_SS_RGMII3_STATUS_REG,RGMII 3 Port Status Register"
bitfld.long 0x08 3. "FULLDUPLEX,RGMII Port 3 full dulex" "0,1"
bitfld.long 0x08 1.--2. "SPEED,RGMII Port 3 speed" "0,1,2,3"
bitfld.long 0x08 0. "LINK,RGMII Port 3 link indicator" "0,1"
line.long 0x0C "CPSW_SS_RGMII4_STATUS_REG,RGMII Port 4 Status Register"
bitfld.long 0x0C 3. "FULLDUPLEX,RGMII Port 4 full dulex" "0,1"
bitfld.long 0x0C 1.--2. "SPEED,RGMII Port 4 speed" "0,1,2,3"
bitfld.long 0x0C 0. "LINK,RGMII Port 4 link indicator" "0,1"
line.long 0x10 "CPSW_SS_RGMII5_STATUS_REG,RGMII Port 5 Status Register"
bitfld.long 0x10 3. "FULLDUPLEX,RGMII Port 5 full dulex" "0,1"
bitfld.long 0x10 1.--2. "SPEED,RGMII Port 5 speed" "0,1,2,3"
bitfld.long 0x10 0. "LINK,RGMII Port 5 link indicator" "0,1"
line.long 0x14 "CPSW_SS_RGMII6_STATUS_REG,RGMII Port 6 Status Register"
bitfld.long 0x14 3. "FULLDUPLEX,RGMII Port 6 full dulex" "0,1"
bitfld.long 0x14 1.--2. "SPEED,RGMII Port 6 speed" "0,1,2,3"
bitfld.long 0x14 0. "LINK,RGMII Port 6 link indicator" "0,1"
line.long 0x18 "CPSW_SS_RGMII7_STATUS_REG,RGMII Port 7 Status Register"
bitfld.long 0x18 3. "FULLDUPLEX,RGMII Port 7 full dulex" "0,1"
bitfld.long 0x18 1.--2. "SPEED,RGMII Port 7 speed" "0,1,2,3"
bitfld.long 0x18 0. "LINK,RGMII Port 7 link indicator" "0,1"
line.long 0x1C "CPSW_SS_RGMII8_STATUS_REG,RGMII Port 8 Status Register"
bitfld.long 0x1C 3. "FULLDUPLEX,RGMII Port 8 full dulex" "0,1"
bitfld.long 0x1C 1.--2. "SPEED,RGMII Port 8 speed" "0,1,2,3"
bitfld.long 0x1C 0. "LINK,RGMII Port 8 link indicator" "0,1"
group.long 0x60++0x07
line.long 0x00 "CPSW_SS_QSGMII_CONTROL_REG,QSGMII Control Register"
bitfld.long 0x00 1. "Q1_RDCD,QSGMII1 Running Disparity Check Disable" "0,1"
bitfld.long 0x00 0. "Q0_RDCD,QSGMII0 Running Disparity Check Disable" "0,1"
line.long 0x04 "CPSW_SS_QSGMII_STATUS_REG,QSGMII Status Register"
bitfld.long 0x04 1. "Q1_RDCD,QSGMII1 RX Sync Detected" "0,1"
bitfld.long 0x04 0. "Q0_RDCD,QSGMII0 RX Sync Detected" "0,1"
rgroup.long 0x74++0x07
line.long 0x00 "CPSW_SS_STATUS_XGMII_LINK_REG,XGMII Link Status Register"
bitfld.long 0x00 1. "XGMII2_LINK,Port 2 XGMII Link Indicator" "0,1"
bitfld.long 0x00 0. "XGMII1_LINK,Port 1 XGMII Link Indicator" "0,1"
line.long 0x04 "CPSW_SS_STATUS_SGMII_LINK_REG,SGMII Link Status Register"
bitfld.long 0x04 1. "SGMII2_LINK,Port 2 SGMII Link Indicator" "0,1"
bitfld.long 0x04 0. "SGMII1_LINK,Port 1 SGMII Link Indicator" "0,1"
tree.end
tree.end
tree "CPSW0_PCSR"
tree "CPSW0_NUSS_PCSR"
base ad:0xC000000
group.long 0x2100++0x2F
line.long 0x00 "CPSW_PCSR_TX_CTL_REG_j,PCSR Transmit Control Register"
bitfld.long 0x00 8. "TX_DATAPATH_EN,PCSR Transmit Datapath Enable" "0,1"
bitfld.long 0x00 7. "TX_SCR_BPYASS,PCSR Transmit SCR Bypass" "0,1"
bitfld.long 0x00 6. "TX_TEST_EN,PCSR Transmit Test Enable" "0,1"
bitfld.long 0x00 5. "TX_TEST_SEL,PCSR Transmit Test Select" "0,1"
bitfld.long 0x00 4. "TX_TEST_DAT_SEL,PCSR Transmit Test Data Select" "0,1"
newline
bitfld.long 0x00 3. "TX_PRBS31_EN,PCSR Transmit PRBS31 Enable" "0,1"
bitfld.long 0x00 2. "TX_PRBS9_EN,PCSR Transmit PRBS9 Enable" "0,1"
bitfld.long 0x00 1. "TX_LOOPBACK_EN,PCSR Transmit Loopback Enable" "0,1"
bitfld.long 0x00 0. "TX_SCR_LOOPBK_EN,PCSR Transmit SCR Loopback Enable" "0,1"
line.long 0x04 "CPSW_PCSR_TX_STATUS_REG_j,PCSR Transmit Status Register"
bitfld.long 0x04 8. "TX_FAULT,PCSR Transmit Fault Hold Register - write 1 to clear" "0,1"
line.long 0x08 "CPSW_PCSR_RX_CTL_REG_j,PCSR Receive Control Register"
bitfld.long 0x08 8. "RX_PRBS9_EN,PCSR Receive PRBS9 Enable" "0,1"
bitfld.long 0x08 7. "RX_TEST_EN,PCSR Receive Test Enable" "0,1"
bitfld.long 0x08 6. "RX_TEST_DAT_SEL,PCSR Receive Test Data Select" "0,1"
bitfld.long 0x08 5. "RX_PRBS31_EN,PCSR Receive PRBS31 Enable" "0,1"
bitfld.long 0x08 4. "RX_ERR_BLK_CNT_RST,PCSR Receive Error Block Count Reset" "0,1"
newline
bitfld.long 0x08 3. "RX_BER_CNT_RST,PCSR Receive BER Count Reset" "0,1"
bitfld.long 0x08 2. "RX_TEST_CNT_PRE,PCSR Receive Test Count Pre" "0,1"
bitfld.long 0x08 1. "RX_TEST_CNT_125US,PCSR Receive Test Count 125us" "0,1"
bitfld.long 0x08 0. "RX_TPTER_CNT_RST,PCSR Receive TPTER Count Reset" "0,1"
line.long 0x0C "CPSW_PCSR_RX_STATUS_REG_j,PCSR Receive Status Register"
bitfld.long 0x0C 31. "RX_HI_BER,PCSR Receive High BER" "0,1"
bitfld.long 0x0C 30. "RX_BLOCK_LOCK,PCSR Receive Block Lock" "0,1"
bitfld.long 0x0C 24.--29. "RX_BER_COUNT,PCSR Receive BER Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 16.--23. 1. "RX_ERR_BLK_CNT,PCSR Error Block Count"
hexmask.long.word 0x0C 0.--15. 1. "RX_TPT_ERR_CNT,PCSR TPT Error Count"
line.long 0x10 "CPSW_PCSR_SEED_A_LO_REG_J,PCSR Seed A Low Register"
line.long 0x14 "CPSW_PCSR_SEED_A_HI_REG_j,PCSR Seed A High Register"
hexmask.long 0x14 0.--25. 1. "SEED_A_HI,PCSR Seed A High"
line.long 0x18 "CPSW_PCSR_SEED_B_LO_REG_J,PCSR Seed B Low Register"
line.long 0x1C "CPSW_PCSR_SEED_B_HI_REG_j,PCSR Seed B High Register"
hexmask.long 0x1C 0.--25. 1. "SEED_B_HI,PCSR Seed B High"
line.long 0x20 "CPSW_PCSR_FEC_REG_j,PCSR FEC Register"
bitfld.long 0x20 1. "FEC_ENA_ERR_IND,PCSR FEC ENA Error Ind" "0,1"
bitfld.long 0x20 0. "FEC_ENABLE,PCSR FEC Enable" "0,1"
line.long 0x24 "CPSW_PCSR_CTL_REG_j,PCSR Control Register"
bitfld.long 0x24 1. "SIGNAL_OK_EN,PCSR Signal OK Enable" "0,1"
bitfld.long 0x24 0. "SIGNAL_OK,PCSR Signal OK" "0,1"
line.long 0x28 "CPSW_PCSR_FEC_CNT_REG_j,PCSR FEC Count Register"
hexmask.long.word 0x28 16.--31. 1. "FEC_CORR_CNT,PCSR FEC Corrected Error Count"
hexmask.long.word 0x28 0.--15. 1. "FEC_UNCORRCNT,PCSR FEC Uncorrected Error Count"
line.long 0x2C "CPSW_PCSR_ERROR_FIFO_REG_j,PCSR Error FIFO Register"
bitfld.long 0x2C 0. "ERROR_FIFO_CTC,PCSR Error FIFO CTC" "0,1"
tree.end
tree.end
tree "CPSW0_RAM"
tree "CPSW0_NUSS_RAM"
base ad:0xC000000
group.long 0x32000++0x03
line.long 0x00 "CPSW_FETCH_LOC_y,These are the RAM locations for one Ethernet port"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
tree.end
tree.end
tree "CPSW0_SGMII"
tree "CPSW0_NUSS_SGMII"
base ad:0xC000000
rgroup.long 0x100++0x07
line.long 0x00 "CPSW_SGMII_IDVER_REG_j,SGMII IDVER register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,MODULE value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_SGMII_SOFT_RESET_REG_j,SGMII Soft Reset Register"
bitfld.long 0x04 1. "RT_SOFT_RESET,Transmit and Receive Software Reset.This bit is intended to be used when changing between loopback mode and normal mode of operation" "0,1"
bitfld.long 0x04 0. "SOFT_RESET,Software Reset" "0,1"
group.long 0x110++0x17
line.long 0x00 "CPSW_SGMII_CONTROL_REG_j,SGMII Control Register Offset = 110h + (j * 100h); where j = 0h to 7h"
bitfld.long 0x00 6. "TEST_PATTERN_EN,Test Pattern Enable" "0,1"
bitfld.long 0x00 5. "MASTER,Master Mode" "0,1"
bitfld.long 0x00 4. "LOOPBACK,Loopback mode" "0,1"
bitfld.long 0x00 3. "MR_NP_LOADED,Next Page Loaded" "0,1"
bitfld.long 0x00 2. "FAST_LINK_TIMER,Fast Link Timer" "0,1"
newline
bitfld.long 0x00 1. "MR_AN_RESTART,Auto Negotiation Restart" "0,1"
bitfld.long 0x00 0. "MR_AN_ENABLE,Auto Negotiation Enable" "0,1"
line.long 0x04 "CPSW_SGMII_STATUS_REG_j,SGMII Status Register Offset = 114h + (j * 100h); where j = 0h to 7h"
bitfld.long 0x04 5. "FIB_SIG_DETECT,Fiber Signal Detect" "0,1"
bitfld.long 0x04 4. "LOCK,Lock" "0,1"
bitfld.long 0x04 3. "MR_PAGE_RX,Next Page Received" "0,1"
bitfld.long 0x04 2. "MR_AN_COMPLETE,Auto negotiation complete" "0,1"
bitfld.long 0x04 1. "AN_ERROR,Auto negotiation error" "0,1"
newline
bitfld.long 0x04 0. "LINK,Link indicator" "0,1"
line.long 0x08 "CPSW_SGMII_MR_ADV_ABILITY_REG_j,SGMII MR Advertized Ability Register"
hexmask.long.word 0x08 0.--15. 1. "MR_ADV_ABILITY,Advertised Ability"
line.long 0x0C "CPSW_SGMII_MR_NP_TX_REG_j,SGMII Next Pate Transmit Register"
hexmask.long.word 0x0C 0.--15. 1. "MR_NP_TX,Next Page Transmit"
line.long 0x10 "CPSW_SGMII_MR_LP_ADV_ABILITY_REG_j,SGMII Link Partner Advertized Ability Register"
hexmask.long.word 0x10 0.--15. 1. "MR_LP_ADV_ABILITY,Link Partner Advertised Ability"
line.long 0x14 "CPSW_SGMII_MR_LP_NP_RX_REG_j,SGMII Link Partner Next Page Receive Register Offset = 124h + (j * 100h); where j = 0h to 7h"
hexmask.long.word 0x14 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received"
group.long 0x130++0x0B
line.long 0x00 "CPSW_SGMII_TX_CFG_REG_j,SGMII Transmit Configuration Register Offset = 130h + (j * 100h); where j = 0h to 7h"
line.long 0x04 "CPSW_SGMII_RX_CFG_REG_j,SGMII Receive Configuration Register Offset = 134h + (j * 100h); where j = 0h to 7h"
line.long 0x08 "CPSW_SGMII_AUX_CFG_REG_j,SGMII Auxiliary Configuration Register"
group.long 0x140++0x0B
line.long 0x00 "CPSW_SGMII_DIAG_CLEAR_REG_j,SGMII Diagnostics Clear Register Offset = 140h + (j * 100h); where j = 0h to 7h"
bitfld.long 0x00 0. "DIAG_CLEAR,Diagnostics Clear" "0,1"
line.long 0x04 "CPSW_SGMII_DIAG_CONTROL_REG_j,SGMII Diagnostics Control Register Offset = 144h + (j * 100h); where j = 0h to 7h"
bitfld.long 0x04 4.--6. "DIAG_SM_SEL,Diagnostic Select" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--1. "DIAG_EDGE_SEL,Diagnostis Hold Signals Edge Select" "0,1,2,3"
line.long 0x08 "CPSW_SGMII_DIAG_STATUS_REG_j,SGMII Diagnostics Status Register Offset = 148h + (j * 100h); where j = 0h to 7h"
hexmask.long.word 0x08 0.--15. 1. "DIAG_STATUS,Diagnostics status"
tree.end
tree.end
tree "CPSW0_STAT"
tree "CPSW0_NUSS_STAT"
base ad:0xC000000
group.long 0x3A000++0xDF
line.long 0x00 "CPSW_STAT_RXGOODFRAMES_k,The total number of good frames received on the port"
line.long 0x04 "CPSW_STAT_RXBROADCASTFRAMES_k,The total number of good broadcast frames received on the port"
line.long 0x08 "CPSW_STAT_RXMULTICASTFRAMES_k,The total number of good multicast frames received on the port"
line.long 0x0C "CPSW_STAT_RXPAUSEFRAMES_k,Total number of pause frames received Offset = 0003A00Ch + (k * 200h); where k = 0h to 8h"
line.long 0x10 "CPSW_STAT_RXCRCERRORS_k,The total number of frames received on the port that experienced a CRC error"
line.long 0x14 "CPSW_STAT_RXALIGNCODEERRORS_k,Total number of alignment/code errors received Offset = 0003A014h + (k * 200h); where k = 0h to 8h"
line.long 0x18 "CPSW_STAT_RXOVERSIZEDFRAMES_k,The total number of oversized frames received on the port"
line.long 0x1C "CPSW_STAT_RXJABBERFRAMES_k,Total number of jabber frames received Offset = 0003A01Ch + (k * 200h); where k = 0h to 8h"
line.long 0x20 "CPSW_STAT_RXUNDERSIZEDFRAMES_k,The total number of undersized frames received on the port"
line.long 0x24 "CPSW_STAT_RXFRAGMENTS_k,The total number of frame fragments received on the port"
line.long 0x28 "CPSW_STAT_ALE_DROP_k,Total number of frames dropped by the ALE"
line.long 0x2C "CPSW_STAT_ALE_OVERRUN_DROP_k,Total number of overrun frames dropped by the ALE"
line.long 0x30 "CPSW_STAT_RXOCTETS_k,The total number of bytes in all good frames received on the port"
line.long 0x34 "CPSW_STAT_TXGOODFRAMES_k,The total number of good frames transmitted on the port"
line.long 0x38 "CPSW_STAT_TXBROADCASTFRAMES_k,The total number of good broadcast frames transmitted on the port"
line.long 0x3C "CPSW_STAT_TXMULTICASTFRAMES_k,The total number of good multicast frames transmitted on the port"
line.long 0x40 "CPSW_STAT_TXPAUSEFRAMES_k,Total number of pause frames transmitted Offset = 0003A040h + (k * 200h); where k = 0h to 8h"
line.long 0x44 "CPSW_STAT_TXDEFERREDFRAMES_k,Total number of deferred frames transmitted Offset = 0003A044h + (k * 200h); where k = 0h to 8h"
line.long 0x48 "CPSW_STAT_TXCOLLISIONFRAMES_k,Total number of transmitted frames experiencing a collision Offset = 0003A048h + (k * 200h); where k = 0h to 8h"
line.long 0x4C "CPSW_STAT_TXSINGLECOLLFRAMES_k,Total number of transmitted frames experiencing a single collision Offset = 0003A04Ch + (k * 200h); where k = 0h to 8h"
line.long 0x50 "CPSW_STAT_TXMULTCOLLFRAMES_k,Total number of transmitted frames experiencing multiple collisions Offset = 0003A050h + (k * 200h); where k = 0h to 8h"
line.long 0x54 "CPSW_STAT_TXEXCESSIVECOLLISIONS_k,Total number of transmitted frames abandoned due to excessive collisions Offset = 0003A054h + (k * 200h); where k = 0h to 8h"
line.long 0x58 "CPSW_STAT_TXLATECOLLISIONS_k,Total number of transmitted frames abandoned due to a late collision Offset = 0003A058h + (k * 200h); where k = 0h to 8h"
line.long 0x5C "CPSW_STAT_RXIPGERROR_k,Total number of receive inter-packet gap errors (10G only) Offset = 0003A05Ch + (k * 200h); where k = 0h to 8h"
line.long 0x60 "CPSW_STAT_TXCARRIERSENSEERRORS_k,Total number of transmitted frames that experienced a carrier loss Offset = 0003A060h + (k * 200h); where k = 0h to 8h"
line.long 0x64 "CPSW_STAT_TXOCTETS_k,The total number of bytes in all good frames transmitted on the port"
line.long 0x68 "CPSW_STAT_OCTETFRAMES64_k,The total number of 64-byte frames received and transmitted on the port"
line.long 0x6C "CPSW_STAT_OCTETFRAMES65T127_k,The total number of frames of size 65 to 127 bytes received and transmitted on the port"
line.long 0x70 "CPSW_STAT_OCTETFRAMES128T255_k,The total number of frames of size 128 to 255 bytes received and transmitted on the port"
line.long 0x74 "CPSW_STAT_OCTETFRAMES256T511_k,The total number of frames of size 256 to 511 bytes received and transmitted on the port"
line.long 0x78 "CPSW_STAT_OCTETFRAMES512T1023_k,The total number of frames of size 512 to 1023 bytes received and transmitted on the port"
line.long 0x7C "CPSW_STAT_OCTETFRAMES1024TUP_k,The total number of frames of size 1024 to [13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port"
line.long 0x80 "CPSW_STAT_NETOCTETS_k,The total number of bytes of frame data received and transmitted on the port"
line.long 0x84 "CPSW_STAT_RX_BOTTOM_OF_FIFO_DROP_k,Receive Bottom of FIFO Drop"
line.long 0x88 "CPSW_STAT_PORTMASK_DROP_k,Total number of dropped frames received due to portmask"
line.long 0x8C "CPSW_STAT_RX_TOP_OF_FIFO_DROP_k,Receive Top of FIFO Drop"
line.long 0x90 "CPSW_STAT_ALE_RATE_LIMIT_DROP_k,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x94 "CPSW_STAT_ALE_VID_INGRESS_DROP_k,Total number of dropped frames due to ALE VID Ingress"
line.long 0x98 "CPSW_STAT_ALE_DA_EQ_SA_DROP_k,Total number of dropped frames due to DA=SA"
line.long 0x9C "CPSW_STAT_ALE_BLOCK_DROP_k,Total number of dropped frames due to ALE Block Mode"
line.long 0xA0 "CPSW_STAT_ALE_SECURE_DROP_k,Total number of dropped frames due to ALE Secure Mode"
line.long 0xA4 "CPSW_STAT_ALE_AUTH_DROP_k,Total number of dropped frames due to ALE Authentication"
line.long 0xA8 "CPSW_STAT_ALE_UNKN_UNI_k,ALE Receive Unknown Unicast"
line.long 0xAC "CPSW_STAT_ALE_UNKN_UNI_BCNT_k,ALE Receive Unknown Unicast Bytecount"
line.long 0xB0 "CPSW_STAT_ALE_UNKN_MLT_K,ALE Receive Unknown Multicast"
line.long 0xB4 "CPSW_STAT_ALE_UNKN_MLT_BCNT_k,ALE Receive Unknown Multicast Bytecount"
line.long 0xB8 "CPSW_STAT_ALE_UNKN_BRD_k,ALE Receive Unknown Broadcast"
line.long 0xBC "CPSW_STAT_ALE_UNKN_BRD_BCNT_k,ALE Receive Unknown Broadcast Bytecount"
line.long 0xC0 "CPSW_STAT_ALE_POL_MATCH_k,ALE Policer Matched"
line.long 0xC4 "CPSW_STAT_ALE_POL_MATCH_RED_k,ALE Policer Matched and Condition Red"
line.long 0xC8 "CPSW_STAT_ALE_POL_MATCH_YELLOW_k,ALE Policer Matched and Condition Yellow"
line.long 0xCC "CPSW_STAT_ALE_MULT_SA_DROP_k,ALE Multicast Source Address Drop"
line.long 0xD0 "CPSW_STAT_ALE_DUAL_VLAN_DROP_k,ALE Dual VLAN Drop"
line.long 0xD4 "CPSW_STAT_ALE_LEN_ERROR_DROP_k,ALE Length Error Drop"
line.long 0xD8 "CPSW_STAT_ALE_IP_NEXT_HDR_DROP_k,ALE IP Next Header Drop"
line.long 0xDC "CPSW_STAT_ALE_IPV4_FRAG_DROP_k,ALE IPV4 Frag Drop"
group.long 0x3A140++0x17
line.long 0x00 "CPSW_STAT_IET_RX_ASSEMBLY_ERROR_REG_k,IET Receive Assembly Error"
line.long 0x04 "CPSW_STAT_IET_RX_ASSEMBLY_OK_REG_k,IET Receive Assembly Ok"
line.long 0x08 "CPSW_STAT_IET_RX_SMD_ERROR_REG_k,IET Receive Smd Error"
line.long 0x0C "CPSW_STAT_IET_RX_FRAG_REG_k,IET Receive Frag"
line.long 0x10 "CPSW_STAT_IET_TX_HOLD_REG_k,IET Transmit Hold"
line.long 0x14 "CPSW_STAT_IET_TX_FRAG_REG_k,IET Transmit Frag"
group.long 0x3A17C++0x07
line.long 0x00 "CPSW_STAT_TX_MEMORY_PROTECT_ERROR_k,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error.Note: If there is a memorry protect error then this COUNT value will increment and issue a STAT_PEND0 interrupt when this bit field is non-zero.That is different from the other stats which only issue an interrupt.."
line.long 0x04 "CPSW_STAT_ENET_PN_TX_PRI_REG_k_y,ENET Port n PRIORITY N Packet Count"
group.long 0x3A1A0++0x03
line.long 0x00 "CPSW_STAT_ENET_PN_TX_PRI_BCNT_REG_k_y,ENET Port n PRIORITY N Packet Byte Count"
group.long 0x3A1C0++0x03
line.long 0x00 "CPSW_STAT_ENET_PN_TX_PRI_DROP_REG_k_y,ENET Port n PRIORITY N Packet Drop Count"
group.long 0x3A1E0++0x03
line.long 0x00 "CPSW_STAT_ENET_PN_TX_PRI_DROP_BCNT_REG_k_y,ENET Port n PRIORITY N Packet Drop Byte Count"
tree.end
tree.end
tree "CPU0_ECC_AGGR_CFG_REGS"
tree "MCU_R5FSS0_CORE0_ECC_AGGR"
base ad:0x40080000
rgroup.long 0x00++0x03
line.long 0x00 "CPU0_REV,Revision register"
group.long 0x08++0x07
line.long 0x00 "CPU0_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPU0_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x0B
line.long 0x00 "CPU0_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU0_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1"
line.long 0x08 "CPU0_SEC_STATUS_REG1,SEC interrupt status register 1"
bitfld.long 0x08 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x08 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x08 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "CPU0_SEC_ENABLE_SET_REG0,SEC Interrupt enable set register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "CPU0_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "CPU0_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU0_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1"
line.long 0x08 "CPU0_DED_STATUS_REG1,DED interrupt status register 1"
bitfld.long 0x08 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x08 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x08 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "CPU0_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_DED_ENABLE_SET_REG1,DED interrupt enable set register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "CPU0_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPU0_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPU0_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPU0_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPU0_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "R5FSS0_CORE0_ECC_AGGR"
base ad:0x2A68000
rgroup.long 0x00++0x03
line.long 0x00 "CPU0_REV,Revision register"
group.long 0x08++0x07
line.long 0x00 "CPU0_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPU0_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x0B
line.long 0x00 "CPU0_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU0_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1"
line.long 0x08 "CPU0_SEC_STATUS_REG1,SEC interrupt status register 1"
bitfld.long 0x08 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x08 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x08 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "CPU0_SEC_ENABLE_SET_REG0,SEC Interrupt enable set register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "CPU0_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "CPU0_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU0_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1"
line.long 0x08 "CPU0_DED_STATUS_REG1,DED interrupt status register 1"
bitfld.long 0x08 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x08 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x08 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "CPU0_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_DED_ENABLE_SET_REG1,DED interrupt enable set register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "CPU0_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPU0_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPU0_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPU0_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPU0_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "R5FSS1_CORE0_ECC_AGGR"
base ad:0x2A69000
rgroup.long 0x00++0x03
line.long 0x00 "CPU0_REV,Revision register"
group.long 0x08++0x07
line.long 0x00 "CPU0_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPU0_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x0B
line.long 0x00 "CPU0_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU0_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1"
line.long 0x08 "CPU0_SEC_STATUS_REG1,SEC interrupt status register 1"
bitfld.long 0x08 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x08 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x08 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "CPU0_SEC_ENABLE_SET_REG0,SEC Interrupt enable set register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "CPU0_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "CPU0_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU0_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU0_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt pending status for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt pending status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt pending status for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt pending status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt pending status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt pending status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt pending status for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt pending status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt pending status for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt pending status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt pending status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt pending status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt pending status for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt pending status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt pending status for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt pending status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt pending status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt pending status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt pending status for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt pending status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt pending status for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt pending status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt pending status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt pending status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt pending status for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt pending status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt pending status for cpu0_itag_ram0_pend" "0,1"
line.long 0x08 "CPU0_DED_STATUS_REG1,DED interrupt status register 1"
bitfld.long 0x08 3. "CPU0_EDC_CTRL_PEND,Interrupt pending status for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x08 2. "SCRP_EDC_PEND,Interrupt pending status for scrp_edc_pend" "0,1"
newline
bitfld.long 0x08 1. "CPU0_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x08 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "CPU0_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt enable set register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt enable set register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt enable set register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt enable set register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt enable set register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt enable set register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt enable set register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_DED_ENABLE_SET_REG1,DED interrupt enable set register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_SET,Interrupt enable set register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_SET,Interrupt enable set register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "CPU0_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU0_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt enable clear register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt enable clear register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear register for cpu0_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear register for cpu0_itag_ram0_pend" "0,1"
line.long 0x04 "CPU0_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1"
bitfld.long 0x04 3. "CPU0_EDC_CTRL_ENABLE_CLR,Interrupt enable clear register for cpu0_edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "SCRP_EDC_ENABLE_CLR,Interrupt enable clear register for scrp_edc_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend" "0,1"
bitfld.long 0x04 0. "CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPU0_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPU0_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPU0_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPU0_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "CPU1_ECC_AGGR_CFG_REGS"
tree "MCU_R5FSS0_ECC_AGGR"
base ad:0x400C0000
rgroup.long 0x00++0x03
line.long 0x00 "CPU1_REV,Revision register"
group.long 0x08++0x07
line.long 0x00 "CPU1_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPU1_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x0B
line.long 0x00 "CPU1_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU1_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1"
line.long 0x08 "CPU1_SEC_STATUS_REG1,SEC interrupt status register 1"
bitfld.long 0x08 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x08 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "CPU1_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "CPU1_SEC_ENABLE_CLR_REG0,SC interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "CPU1_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU1_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1"
line.long 0x08 "CPU1_DED_STATUS_REG1,DED interrupt status register 1"
bitfld.long 0x08 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x08 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "CPU1_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_DED_ENABLE_SET_REG1,DED interrupt enable set register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "CPU1_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPU1_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPU1_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPU1_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPU1_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "R5FSS0_ECC_AGGR"
base ad:0x5B10000
rgroup.long 0x00++0x03
line.long 0x00 "CPU1_REV,Revision register"
group.long 0x08++0x07
line.long 0x00 "CPU1_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPU1_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x0B
line.long 0x00 "CPU1_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU1_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1"
line.long 0x08 "CPU1_SEC_STATUS_REG1,SEC interrupt status register 1"
bitfld.long 0x08 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x08 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "CPU1_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "CPU1_SEC_ENABLE_CLR_REG0,SC interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "CPU1_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU1_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1"
line.long 0x08 "CPU1_DED_STATUS_REG1,DED interrupt status register 1"
bitfld.long 0x08 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x08 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "CPU1_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_DED_ENABLE_SET_REG1,DED interrupt enable set register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "CPU1_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPU1_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPU1_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPU1_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPU1_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "R5FSS1_ECC_AGGR"
base ad:0x5B30000
rgroup.long 0x00++0x03
line.long 0x00 "CPU1_REV,Revision register"
group.long 0x08++0x07
line.long 0x00 "CPU1_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPU1_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x0B
line.long 0x00 "CPU1_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU1_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1"
line.long 0x08 "CPU1_SEC_STATUS_REG1,SEC interrupt status register 1"
bitfld.long 0x08 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x08 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "CPU1_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_SEC_ENABLE_SET_REG1,SEC interrupt enable set register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "CPU1_SEC_ENABLE_CLR_REG0,SC interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_SEC_ENABLE_CLR_REG1,SEC interrupt enable clear register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "CPU1_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "CPU1_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x04 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x04 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x04 28. "CPU1_VBUSM2AXI_EDC_PEND,Interrupt pending status for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt pending status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt pending status for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt pending status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt pending status for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt pending status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt pending status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt pending status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt pending status for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt pending status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt pending status for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt pending status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt pending status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt pending status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt pending status for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt pending status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt pending status for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt pending status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt pending status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt pending status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt pending status for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt pending status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt pending status for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt pending status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt pending status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt pending status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt pending status for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt pending status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt pending status for cpu1_itag_ram0_pend" "0,1"
line.long 0x08 "CPU1_DED_STATUS_REG1,DED interrupt status register 1"
bitfld.long 0x08 2. "CPU1_EDC_CTRL_PEND,Interrupt pending status for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x08 1. "CPU1_AHB2VBUSP_EDC_PEND,Interrupt pending status for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x08 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND,Interrupt pending status for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "CPU1_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_SET,Interrupt enable set for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt enable set for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt enable set for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt enable set for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt enable set for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt enable set for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt enable set for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt enable set for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt enable set for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt enable set for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt enable set for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt enable set for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt enable set for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt enable set for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt enable set for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt enable set for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt enable set for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt enable set for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_DED_ENABLE_SET_REG1,DED interrupt enable set register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_SET,Interrupt enable set for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_SET,Interrupt enable set for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET,Interrupt enable set for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "CPU1_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 31. "CPU1_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_write_edc_pend" "0,1"
bitfld.long 0x00 30. "CPU1_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_read_edc_pend" "0,1"
newline
bitfld.long 0x00 29. "CPU1_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_mem_mst_write_edc_pend" "0,1"
bitfld.long 0x00 28. "CPU1_VBUSM2AXI_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_vbusm2axi_edc_pend" "0,1"
newline
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt enable clear for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt enable clear for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt enable clear for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt enable clear for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram7_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram5_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram1_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt enable clear for cpu1_ddirty_ram_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_dtag_ram0_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank2_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt enable clear for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram2_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt enable clear for cpu1_itag_ram0_pend" "0,1"
line.long 0x04 "CPU1_DED_ENABLE_CLR_REG1,DED interrupt enable clear register 1"
bitfld.long 0x04 2. "CPU1_EDC_CTRL_ENABLE_CLR,Interrupt enable clear for cpu1_edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "CPU1_AHB2VBUSP_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_ahb2vbusp_edc_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU1_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR,Interrupt enable clear for cpu1_axi2vbusm_periph_mst_read_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPU1_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPU1_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPU1_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPU1_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "CSI_RX_IF"
tree "CSI_RX_IF0_CP_INTD_CFG_INTD_CFG"
base ad:0x4508000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_RX_IF_CP_INTD_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,MajorCSI_RX_IF_CP_INTD_REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CustomCSI_RX_IF_CP_INTD_REVISION" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,MinorCSI_RX_IF_CP_INTD_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CSI_RX_IF_CP_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_ENABLE_REG_LEVEL_0,Enable Register 0"
bitfld.long 0x00 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW,Enable Set for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM,Enable Set for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW,Enable Set for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM,Enable Set for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW,Enable Set for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_ENABLE_REG_PULSE_0,Enable Register 1"
bitfld.long 0x04 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW,Enable Set for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM,Enable Set for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW,Enable Set for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM,Enable Set for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW,Enable Set for pulse_en_fifo_overflow" "0,1"
group.long 0x300++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_ENABLE_CLR_REG_LEVEL_0,Enable Clear Register 0"
bitfld.long 0x00 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW_CLR,Enable Clear for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_ENABLE_CLR_REG_PULSE_0,Enable Clear Register 1"
bitfld.long 0x04 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW_CLR,Enable Clear for pulse_en_fifo_overflow" "0,1"
group.long 0x500++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_STATUS_REG_LEVEL_0,Status Register 0"
bitfld.long 0x00 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW,Status write 1 to set for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM,Status write 1 to set for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW,Status write 1 to set for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM,Status write 1 to set for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_FIFO_OVERFLOW,Status write 1 to set for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_STATUS_REG_PULSE_0,Status Register 1"
bitfld.long 0x04 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_FIFO_OVERFLOW,Status write 1 to set for pulse_en_fifo_overflow" "0,1"
group.long 0x700++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_STATUS_CLR_REG_LEVEL_0,Status Clear Register 0"
bitfld.long 0x00 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_FIFO_OVERFLOW_CLR,Status write 1 to clear for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_STATUS_CLR_REG_PULSE_0,Status Clear Register 1"
bitfld.long 0x04 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_FIFO_OVERFLOW_CLR,Status write 1 to clear for pulse_en_fifo_overflow" "0,1"
rgroup.long 0xA80++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_INTR_VECTOR_REG_LEVEL,Interrupt Vector for level"
line.long 0x04 "CSI_RX_IF_CP_INTD_INTR_VECTOR_REG_PULSE,Interrupt Vector for pulse"
tree.end
tree "CSI_RX_IF1_CP_INTD_CFG_INTD_CFG"
base ad:0x4518000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_RX_IF_CP_INTD_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,MajorCSI_RX_IF_CP_INTD_REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CustomCSI_RX_IF_CP_INTD_REVISION" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,MinorCSI_RX_IF_CP_INTD_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CSI_RX_IF_CP_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_ENABLE_REG_LEVEL_0,Enable Register 0"
bitfld.long 0x00 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW,Enable Set for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM,Enable Set for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW,Enable Set for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM,Enable Set for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW,Enable Set for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_ENABLE_REG_PULSE_0,Enable Register 1"
bitfld.long 0x04 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW,Enable Set for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM,Enable Set for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW,Enable Set for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM,Enable Set for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW,Enable Set for pulse_en_fifo_overflow" "0,1"
group.long 0x300++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_ENABLE_CLR_REG_LEVEL_0,Enable Clear Register 0"
bitfld.long 0x00 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW_CLR,Enable Clear for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_ENABLE_CLR_REG_PULSE_0,Enable Clear Register 1"
bitfld.long 0x04 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW_CLR,Enable Clear for pulse_en_fifo_overflow" "0,1"
group.long 0x500++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_STATUS_REG_LEVEL_0,Status Register 0"
bitfld.long 0x00 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW,Status write 1 to set for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM,Status write 1 to set for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW,Status write 1 to set for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM,Status write 1 to set for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_FIFO_OVERFLOW,Status write 1 to set for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_STATUS_REG_PULSE_0,Status Register 1"
bitfld.long 0x04 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_FIFO_OVERFLOW,Status write 1 to set for pulse_en_fifo_overflow" "0,1"
group.long 0x700++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_STATUS_CLR_REG_LEVEL_0,Status Clear Register 0"
bitfld.long 0x00 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_FIFO_OVERFLOW_CLR,Status write 1 to clear for level_en_fifo_overflow" "0,1"
line.long 0x04 "CSI_RX_IF_CP_INTD_STATUS_CLR_REG_PULSE_0,Status Clear Register 1"
bitfld.long 0x04 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_FIFO_OVERFLOW_CLR,Status write 1 to clear for pulse_en_fifo_overflow" "0,1"
rgroup.long 0xA80++0x07
line.long 0x00 "CSI_RX_IF_CP_INTD_INTR_VECTOR_REG_LEVEL,Interrupt Vector for level"
line.long 0x04 "CSI_RX_IF_CP_INTD_INTR_VECTOR_REG_PULSE,Interrupt Vector for pulse"
tree.end
tree "CSI_RX_IF0_ECC_AGGR_CFG"
base ad:0x2A30000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_RX_IF_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CSI_RX_IF_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CSI_RX_IF_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CSI_RX_IF_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CSI_RX_IF_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_RX_IF_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x04 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CSI_RX_IF_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CSI_RX_IF_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CSI_RX_IF_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_RX_IF_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x04 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CSI_RX_IF_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CSI_RX_IF_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CSI_RX_IF_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CSI_RX_IF_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CSI_RX_IF_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CSI_RX_IF_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "CSI_RX_IF1_ECC_AGGR_CFG"
base ad:0x2A31000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_RX_IF_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CSI_RX_IF_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CSI_RX_IF_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CSI_RX_IF_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CSI_RX_IF_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_RX_IF_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x04 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CSI_RX_IF_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CSI_RX_IF_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CSI_RX_IF_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_RX_IF_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x04 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CSI_RX_IF_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CSI_RX_IF_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CSI_RX_IF_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CSI_RX_IF_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CSI_RX_IF_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CSI_RX_IF_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF"
base ad:0x4500000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_RX_IF_SHIM_CSIRX_ID,nothing"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major CSI_RX_IF_SHIM_REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom CSI_RX_IF_SHIM_REVISION" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,min CSI_RX_IF_SHIM_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CSI_RX_IF_SHIM_VP0,Video Port 0 configuration"
bitfld.long 0x00 31. "EN_CFG,Video Port enable.Disable:drops pixel data Enable: start on VS captures and sends frame data" "0,1"
hexmask.long.word 0x00 16.--28. 1. "IH_CFG,(U13) input height in units of lines.Only writable when vp0_en_cfg=0"
hexmask.long.word 0x00 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples.Max usable value determined by populated line buffer RAM size"
line.long 0x04 "CSI_RX_IF_SHIM_VP1,Video Port 1 configuration"
bitfld.long 0x04 31. "EN_CFG,Video Port enable.Disable:drops pixel data Enable: start on VS captures and sends frame data" "0,1"
hexmask.long.word 0x04 16.--28. 1. "IH_CFG,(U13) input height in units of lines.Only writable when vp0_en_cfg=0"
hexmask.long.word 0x04 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples.Max usable value determined by populated line buffer RAM size"
line.long 0x08 "CSI_RX_IF_SHIM_CNTL,control register for csi rx wrapper"
rbitfld.long 0x08 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
bitfld.long 0x08 0. "PIXEL_RESET,reset for the pixeal interface.0-reset 1 not in reset" "0,1"
group.long 0x20++0x0B
line.long 0x00 "CSI_RX_IF_SHIM_DMACNTX,DMA Channel Context"
bitfld.long 0x00 31. "EN_CFG,DMA context is enabled.Will extract channel if input matches dataType and VirtualChan" "0,1"
bitfld.long 0x00 29. "RSV0,reserved" "0,1"
bitfld.long 0x00 28. "RSV1,reserved" "0,1"
bitfld.long 0x00 26.--27. "YUV422_MODE_CFG,yuv422 mode00:UYVY " "?,VYUY,YUYV,YVYU"
bitfld.long 0x00 25. "RSV2,reserved" "0,1"
bitfld.long 0x00 24. "DUAL_PCK_CFG,dual packed format extraction for 8 bits or less" "0,1"
newline
bitfld.long 0x00 20.--21. "SIZE_CFG,data size shift when unpacking 00=8 " "0,1,2,3"
bitfld.long 0x00 18. "PCK12_CFG,12-bit packing enable" "0,1"
bitfld.long 0x00 6.--9. "VIRTCH_CFG,CSI virtual channel index.Supplied by MIPI CSI protocol to DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "DATTYP_CFG,CSI data type index.Supplied by MIPI CSI protocol to DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CSI_RX_IF_SHIM_PSI_CFG0,psi configuration register0"
hexmask.long.word 0x04 16.--31. 1. "DST_TAG,psi dst tag"
hexmask.long.word 0x04 0.--15. 1. "SRC_TAG,psi source tag"
line.long 0x08 "CSI_RX_IF_SHIM_PSI_CFG1,psi configuration register1"
bitfld.long 0x08 8.--11. "PS_FLAGS,ps flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--4. "PKT_TYPE,psi packet type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "CSI_RX_IF1_RX_SHIM_VBUSP_MMR_CSI2RXIF"
base ad:0x4510000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_RX_IF_SHIM_CSIRX_ID,nothing"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major CSI_RX_IF_SHIM_REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom CSI_RX_IF_SHIM_REVISION" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,min CSI_RX_IF_SHIM_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CSI_RX_IF_SHIM_VP0,Video Port 0 configuration"
bitfld.long 0x00 31. "EN_CFG,Video Port enable.Disable:drops pixel data Enable: start on VS captures and sends frame data" "0,1"
hexmask.long.word 0x00 16.--28. 1. "IH_CFG,(U13) input height in units of lines.Only writable when vp0_en_cfg=0"
hexmask.long.word 0x00 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples.Max usable value determined by populated line buffer RAM size"
line.long 0x04 "CSI_RX_IF_SHIM_VP1,Video Port 1 configuration"
bitfld.long 0x04 31. "EN_CFG,Video Port enable.Disable:drops pixel data Enable: start on VS captures and sends frame data" "0,1"
hexmask.long.word 0x04 16.--28. 1. "IH_CFG,(U13) input height in units of lines.Only writable when vp0_en_cfg=0"
hexmask.long.word 0x04 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples.Max usable value determined by populated line buffer RAM size"
line.long 0x08 "CSI_RX_IF_SHIM_CNTL,control register for csi rx wrapper"
rbitfld.long 0x08 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
bitfld.long 0x08 0. "PIXEL_RESET,reset for the pixeal interface.0-reset 1 not in reset" "0,1"
group.long 0x20++0x0B
line.long 0x00 "CSI_RX_IF_SHIM_DMACNTX,DMA Channel Context"
bitfld.long 0x00 31. "EN_CFG,DMA context is enabled.Will extract channel if input matches dataType and VirtualChan" "0,1"
bitfld.long 0x00 29. "RSV0,reserved" "0,1"
bitfld.long 0x00 28. "RSV1,reserved" "0,1"
bitfld.long 0x00 26.--27. "YUV422_MODE_CFG,yuv422 mode00:UYVY " "?,VYUY,YUYV,YVYU"
bitfld.long 0x00 25. "RSV2,reserved" "0,1"
bitfld.long 0x00 24. "DUAL_PCK_CFG,dual packed format extraction for 8 bits or less" "0,1"
newline
bitfld.long 0x00 20.--21. "SIZE_CFG,data size shift when unpacking 00=8 " "0,1,2,3"
bitfld.long 0x00 18. "PCK12_CFG,12-bit packing enable" "0,1"
bitfld.long 0x00 6.--9. "VIRTCH_CFG,CSI virtual channel index.Supplied by MIPI CSI protocol to DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "DATTYP_CFG,CSI data type index.Supplied by MIPI CSI protocol to DPHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CSI_RX_IF_SHIM_PSI_CFG0,psi configuration register0"
hexmask.long.word 0x04 16.--31. 1. "DST_TAG,psi dst tag"
hexmask.long.word 0x04 0.--15. 1. "SRC_TAG,psi source tag"
line.long 0x08 "CSI_RX_IF_SHIM_PSI_CFG1,psi configuration register1"
bitfld.long 0x08 8.--11. "PS_FLAGS,ps flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--4. "PKT_TYPE,psi packet type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
repeat 2. (list 0. 1. )(list ad:0x4504000 ad:0x4514000 )
tree "CSI_RX_IF_VBUS2APB$1"
base $2
rgroup.long 0x00++0x0B
line.long 0x00 "CSI_RX_IF_VBUS2APB_DEVICE_CONFIG,This register provides information related to the current configuration"
bitfld.long 0x00 31. "STREAM3_MONITOR_PRESENT,Pixel stream 3 Monitor present" "0,1"
bitfld.long 0x00 29.--30. "STREAM3_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected" "0,1,2,3"
newline
bitfld.long 0x00 27.--28. "STREAM3_FIFO_MODE,Stream 3 FIFO Mode" "0,1,2,3"
bitfld.long 0x00 26. "STREAM2_MONITOR_PRESENT,Pixel stream 2 Monitor present" "0,1"
newline
bitfld.long 0x00 24.--25. "STREAM2_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected" "0,1,2,3"
bitfld.long 0x00 22.--23. "STREAM2_FIFO_MODE,Stream 2 FIFO Mode" "0,1,2,3"
newline
bitfld.long 0x00 21. "STREAM1_MONITOR_PRESENT,Pixel stream 1 Monitor present" "0,1"
bitfld.long 0x00 19.--20. "STREAM1_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected" "0,1,2,3"
newline
bitfld.long 0x00 17.--18. "STREAM1_FIFO_MODE,Stream 1 FIFO Mode" "0,1,2,3"
bitfld.long 0x00 16. "STREAM0_MONITOR_PRESENT,Pixel stream 0 Monitor present" "0,1"
newline
bitfld.long 0x00 14.--15. "STREAM0_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected" "0,1,2,3"
bitfld.long 0x00 12.--13. "STREAM0_FIFO_MODE,Stream 0 FIFO Mode" "0,1,2,3"
newline
bitfld.long 0x00 10. "ASF_CONFIG,Additional Features [ASF] Configuration" "0,1"
bitfld.long 0x00 9. "VCX_CONFIG,Extended Virtual Channel [VCX] Configuration" "0,1"
newline
bitfld.long 0x00 7.--8. "DATAPATH_SIZE,Internal Datapath width" "0,1,2,3"
bitfld.long 0x00 4.--6. "NUM_STREAMS,Number of Stream interfaces" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "CDNS_PHY_PRESENT,DPDHY present" "0,1"
bitfld.long 0x00 0.--2. "MAX_LANE_NB,Max Number of Lanes" "0,1,2,3,4,5,6,7"
line.long 0x04 "CSI_RX_IF_VBUS2APB_SOFT_RESET,CSI2 Slave Controller Individual Soft Reset for Front and Protocol blocks"
bitfld.long 0x04 1. "PROTOCOL,writing 1'b1 will apply a synchronous soft reset to the protocol module" "0,1"
bitfld.long 0x04 0. "FRONT,writing 1'b1 will apply a synchronous soft reset to the Front module" "0,1"
line.long 0x08 "CSI_RX_IF_VBUS2APB_STATIC_CFG,Configuration register to set the physical/logical DPHY lane mapping. the number of lanes being used. external DPHY selection and ECC support for CSI2RX v2.0"
bitfld.long 0x08 28.--30. "DL3_MAP,physical mapping of logical data lane 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "DL2_MAP,physical mapping of logical data lane 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "DL1_MAP,physical mapping of logical data lane 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "DL0_MAP,physical mapping of logical data lane 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "LANE_NB,The number of lanes" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 4. "V2P0_SUPPORT_ENABLE,Support extended VC up to 16 virtual channels" "0,1"
newline
bitfld.long 0x08 0.--1. "SEL,selection of DPHY used as input of CSI2RX module" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "CSI_RX_IF_VBUS2APB_ERROR_BYPASS_CFG,Error detection event flag configuration"
bitfld.long 0x00 2. "DATA_ID,Enables Data ID error bypass for stream outputs" "0,1"
bitfld.long 0x00 1. "ECC,Enables ECC error bypass for stream outputs" "0,1"
newline
bitfld.long 0x00 0. "CRC,Enables CRC error bypass for stream outputs" "0,1"
group.long 0x18++0x17
line.long 0x00 "CSI_RX_IF_VBUS2APB_MONITOR_IRQS,Information type Interrupt status (non-error conditions)"
bitfld.long 0x00 31. "STREAM3_LINE_CNT_ERROR_IRQ,Stream 3 Line count error interrupt" "0,1"
bitfld.long 0x00 30. "STREAM3_FRAME_MISMATCH_IRQ,Stream 3 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 29. "STREAM3_FRAME_CNT_ERROR_IRQ,Stream 3 Frame count error interrupt" "0,1"
bitfld.long 0x00 28. "STREAM3_FCC_STOP_IRQ,Stream 3 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 27. "STREAM3_FCC_START_IRQ,Stream 3 FCC start interrupt" "0,1"
bitfld.long 0x00 26. "STREAM3_FRAME_IRQ,Stream 3 Frame interrupt" "0,1"
newline
bitfld.long 0x00 25. "STREAM3_LB_IRQ,Stream 3 Line/byte interrupt" "0,1"
bitfld.long 0x00 24. "STREAM3_TIMER_IRQ,Stream 3 Timer interrupt" "0,1"
newline
bitfld.long 0x00 23. "STREAM2_LINE_CNT_ERROR_IRQ,Stream 2 Line count error interrupt" "0,1"
bitfld.long 0x00 22. "STREAM2_FRAME_MISMATCH_IRQ,Stream 2 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 21. "STREAM2_FRAME_CNT_ERROR_IRQ,Stream 2 Frame count error interrupt" "0,1"
bitfld.long 0x00 20. "STREAM2_FCC_STOP_IRQ,Stream 2 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 19. "STREAM2_FCC_START_IRQ,Stream 2 FCC start interrupt" "0,1"
bitfld.long 0x00 18. "STREAM2_FRAME_IRQ,Stream 2 Frame interrupt" "0,1"
newline
bitfld.long 0x00 17. "STREAM2_LB_IRQ,Stream 2 Line/byte interrupt" "0,1"
bitfld.long 0x00 16. "STREAM2_TIMER_IRQ,Stream 2 Timer interrupt" "0,1"
newline
bitfld.long 0x00 15. "STREAM1_LINE_CNT_ERROR_IRQ,Stream 1 Line count error interrupt" "0,1"
bitfld.long 0x00 14. "STREAM1_FRAME_MISMATCH_IRQ,Stream 1 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 13. "STREAM1_FRAME_CNT_ERROR_IRQ,Stream 1 Frame count error interrupt" "0,1"
bitfld.long 0x00 12. "STREAM1_FCC_STOP_IRQ,Stream 1 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 11. "STREAM1_FCC_START_IRQ,Stream 1 FCC start interrupt" "0,1"
bitfld.long 0x00 10. "STREAM1_FRAME_IRQ,Stream 1 Frame interrupt" "0,1"
newline
bitfld.long 0x00 9. "STREAM1_LB_IRQ,Stream 1 Line/byte interrupt" "0,1"
bitfld.long 0x00 8. "STREAM1_TIMER_IRQ,Stream 1 Timer interrupt" "0,1"
newline
bitfld.long 0x00 7. "STREAM0_LINE_CNT_ERROR_IRQ,Stream 0 Line count error interrupt" "0,1"
bitfld.long 0x00 6. "STREAM0_FRAME_MISMATCH_IRQ,Stream 0 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 5. "STREAM0_FRAME_CNT_ERROR_IRQ,Stream 0 Frame count error interrupt" "0,1"
bitfld.long 0x00 4. "STREAM0_FCC_STOP_IRQ,Stream 0 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 3. "STREAM0_FCC_START_IRQ,Stream 0 FCC start interrupt" "0,1"
bitfld.long 0x00 2. "STREAM0_FRAME_IRQ,Stream 0 Frame interrupt" "0,1"
newline
bitfld.long 0x00 1. "STREAM0_LB_IRQ,Stream 0 Line/byte interrupt" "0,1"
bitfld.long 0x00 0. "STREAM0_TIMER_IRQ,Stream 0 Timer interrupt" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_MONITOR_IRQS_MASK_CFG,Monitor interrupt mask"
bitfld.long 0x04 31. "STREAM3_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 3 Line count error" "0,1"
bitfld.long 0x04 30. "STREAM3_FRAME_MISMATCH_IRQM,Interrupt mask for stream 3 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 29. "STREAM3_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 3 Frame count error" "0,1"
bitfld.long 0x04 28. "STREAM3_FCC_STOP_IRQM,Interrupt mask for stream 3 FCC stop" "0,1"
newline
bitfld.long 0x04 27. "STREAM3_FCC_START_IRQM,Interrupt mask for stream 3 FCC start" "0,1"
bitfld.long 0x04 26. "STREAM3_FRAME_IRQM,Interrupt mask for stream 3 Frame" "0,1"
newline
bitfld.long 0x04 25. "STREAM3_LB_IRQM,Interrupt mask for stream 3 Line/byte" "0,1"
bitfld.long 0x04 24. "STREAM3_TIMER_IRQM,Interrupt mask stream 3 Timer" "0,1"
newline
bitfld.long 0x04 23. "STREAM2_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 2 Line count error" "0,1"
bitfld.long 0x04 22. "STREAM2_FRAME_MISMATCH_IRQM,Interrupt mask for stream 2 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 21. "STREAM2_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 2 Frame count error" "0,1"
bitfld.long 0x04 20. "STREAM2_FCC_STOP_IRQM,Interrupt mask for stream 2 FCC stop" "0,1"
newline
bitfld.long 0x04 19. "STREAM2_FCC_START_IRQM,Interrupt mask for stream 2 FCC start" "0,1"
bitfld.long 0x04 18. "STREAM2_FRAME_IRQM,Interrupt mask for stream 2 Frame" "0,1"
newline
bitfld.long 0x04 17. "STREAM2_LB_IRQM,Interrupt mask for stream 2 Line/byte" "0,1"
bitfld.long 0x04 16. "STREAM2_TIMER_IRQM,Interrupt mask stream 2 Timer" "0,1"
newline
bitfld.long 0x04 15. "STREAM1_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 1 Line count error" "0,1"
bitfld.long 0x04 14. "STREAM1_FRAME_MISMATCH_IRQM,Interrupt mask for stream 1 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 13. "STREAM1_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 1 Frame count error" "0,1"
bitfld.long 0x04 12. "STREAM1_FCC_STOP_IRQM,Interrupt mask for stream 1 FCC stop" "0,1"
newline
bitfld.long 0x04 11. "STREAM1_FCC_START_IRQM,Interrupt mask for stream 1 FCC start" "0,1"
bitfld.long 0x04 10. "STREAM1_FRAME_IRQM,Interrupt mask for stream 1 Frame" "0,1"
newline
bitfld.long 0x04 9. "STREAM1_LB_IRQM,Interrupt mask for stream 1 Line/byte" "0,1"
bitfld.long 0x04 8. "STREAM1_TIMER_IRQM,Interrupt mask stream 1 Timer" "0,1"
newline
bitfld.long 0x04 7. "STREAM0_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 0 Line count error" "0,1"
bitfld.long 0x04 6. "STREAM0_FRAME_MISMATCH_IRQM,Interrupt mask for stream 0 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 5. "STREAM0_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 0 Frame count error" "0,1"
bitfld.long 0x04 4. "STREAM0_FCC_STOP_IRQM,Interrupt mask for stream 0 FCC stop" "0,1"
newline
bitfld.long 0x04 3. "STREAM0_FCC_START_IRQM,Interrupt mask for stream 0 FCC start" "0,1"
bitfld.long 0x04 2. "STREAM0_FRAME_IRQM,Interrupt mask for stream 0 Frame" "0,1"
newline
bitfld.long 0x04 1. "STREAM0_LB_IRQM,Interrupt mask for stream 0 Line/byte" "0,1"
bitfld.long 0x04 0. "STREAM0_TIMER_IRQM,Interrupt mask stream 0 Timer" "0,1"
line.long 0x08 "CSI_RX_IF_VBUS2APB_INFO_IRQS,Information type Interrupt status (non-error conditions)"
bitfld.long 0x08 14. "STREAM3_ABORT_IRQ,Stream 3 Abort process complete" "0,1"
bitfld.long 0x08 13. "STREAM3_STOP_IRQ,Stream 3 Stop process complete" "0,1"
newline
bitfld.long 0x08 12. "STREAM2_ABORT_IRQ,Stream 2 Abort process complete" "0,1"
bitfld.long 0x08 11. "STREAM2_STOP_IRQ,Stream 2 Stop process complete" "0,1"
newline
bitfld.long 0x08 10. "STREAM1_ABORT_IRQ,Stream 1 Abort process complete" "0,1"
bitfld.long 0x08 9. "STREAM1_STOP_IRQ,Stream 1 Stop process complete" "0,1"
newline
bitfld.long 0x08 8. "STREAM0_ABORT_IRQ,Stream 0 Abort process complete" "0,1"
bitfld.long 0x08 7. "STREAM0_STOP_IRQ,Stream 0 Stop process complete" "0,1"
newline
bitfld.long 0x08 6. "SP_GENERIC_RCVD_IRQ,A generic short packet has been received" "0,1"
bitfld.long 0x08 5. "DESKEW_ENTRY_IRQ,Either clock or any datalane has entered deskew" "0,1"
newline
bitfld.long 0x08 4. "ECC_SPARES_NONZERO_IRQ,Bits" "0,1"
bitfld.long 0x08 3. "WAKEUP_IRQ,Wake-up interrupt" "0,1"
newline
bitfld.long 0x08 2. "SLEEP_IRQ,Sleep interrupt" "0,1"
bitfld.long 0x08 1. "LP_RCVD_IRQ,Long Packet received by the protocol module" "0,1"
newline
bitfld.long 0x08 0. "SP_RCVD_IRQ,Short Packet received by the protocol module" "0,1"
line.long 0x0C "CSI_RX_IF_VBUS2APB_INFO_IRQS_MASK_CFG,Information interrupt mask"
bitfld.long 0x0C 14. "STREAM3_ABORT_IRQM,Interrupt mask for stream 3 Abort process" "0,1"
bitfld.long 0x0C 13. "STREAM3_STOP_IRQM,Interrupt mask for Stream 3 Stop process complete" "0,1"
newline
bitfld.long 0x0C 12. "STREAM2_ABORT_IRQM,Interrupt mask for stream 2 Abort process" "0,1"
bitfld.long 0x0C 11. "STREAM2_STOP_IRQM,Interrupt mask for Stream 2 Stop process complete" "0,1"
newline
bitfld.long 0x0C 10. "STREAM1_ABORT_IRQM,Interrupt mask for stream 1 Abort process" "0,1"
bitfld.long 0x0C 9. "STREAM1_STOP_IRQM,Interrupt mask for Stream 1 Stop process complete" "0,1"
newline
bitfld.long 0x0C 8. "STREAM0_ABORT_IRQM,Interrupt mask for stream 0 Abort process" "0,1"
bitfld.long 0x0C 7. "STREAM0_STOP_IRQM,Interrupt mask for Stream 0 Stop process complete" "0,1"
newline
bitfld.long 0x0C 6. "SP_GENERIC_RCVD_IRQM,Interrupt mask for Generic Short Packet received" "0,1"
bitfld.long 0x0C 5. "DESKEW_ENTRY_IRQM,Interrupt mask for Deskew entry check" "0,1"
newline
bitfld.long 0x0C 4. "ECC_SPARES_NONZERO_IRQM,Interrupt mask for ECC spares check" "0,1"
bitfld.long 0x0C 3. "WAKEUP_IRQM,Interrupt mask for Wake-up interrupt" "0,1"
newline
bitfld.long 0x0C 2. "SLEEP_IRQM,Interrupt mask for Sleep interrupt" "0,1"
bitfld.long 0x0C 1. "LP_RCVD_IRQM,Interrupt mask for Long Packet received flag" "0,1"
newline
bitfld.long 0x0C 0. "SP_RCVD_IRQM,Interrupt mask for Short Packet received" "0,1"
line.long 0x10 "CSI_RX_IF_VBUS2APB_ERROR_IRQS,Datapath error interrupt status"
bitfld.long 0x10 19. "STREAM3_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected" "0,1"
bitfld.long 0x10 18. "STREAM2_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected" "0,1"
newline
bitfld.long 0x10 17. "STREAM1_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected" "0,1"
bitfld.long 0x10 16. "STREAM0_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected" "0,1"
newline
bitfld.long 0x10 12. "FRONT_TRUNC_HDR_IRQ,A truncated header [short or Long] has been received" "0,1"
bitfld.long 0x10 11. "PROT_TRUNCATED_PACKET_IRQ,A truncated Long packet has been received" "0,1"
newline
bitfld.long 0x10 10. "FRONT_LP_NO_PAYLOAD_IRQ,A truncated Long packet has been received" "0,1"
bitfld.long 0x10 9. "SP_INVALID_RCVD_IRQ,A reserved or invalid short packet has been received" "0,1"
newline
bitfld.long 0x10 8. "INVALID_ACCESS_IRQ,Invalid access to the configuration register space" "0,1"
bitfld.long 0x10 7. "DATA_ID_IRQ,Data ID error has been detected in the header packet" "0,1"
newline
bitfld.long 0x10 6. "HEADER_CORRECTED_ECC_IRQ,ECC error has been detected and corrected" "0,1"
bitfld.long 0x10 5. "HEADER_ECC_IRQ,Unrecoverable ECC error has been detected" "0,1"
newline
bitfld.long 0x10 4. "PAYLOAD_CRC_IRQ,CRC error has been detected" "0,1"
bitfld.long 0x10 0. "FRONT_FIFO_OVERFLOW_IRQ,Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks" "0,1"
line.long 0x14 "CSI_RX_IF_VBUS2APB_ERROR_IRQS_MASK_CFG,Datapath error interrupt enable Bits"
bitfld.long 0x14 19. "STREAM3_FIFO_OVERFLOW_IRQM,Interrupt enable bit for" "0,1"
bitfld.long 0x14 18. "STREAM2_FIFO_OVERFLOW_IRQM,Interrupt enable bit for" "0,1"
newline
bitfld.long 0x14 17. "STREAM1_FIFO_OVERFLOW_IRQM,Interrupt enable bit for" "0,1"
bitfld.long 0x14 16. "STREAM0_FIFO_OVERFLOW_IRQM,Interrupt enable bit for" "0,1"
newline
bitfld.long 0x14 12. "FRONT_TRUNC_HDR_IRQM,Interrupt enable bit for truncated hdr" "0,1"
bitfld.long 0x14 11. "PROT_TRUNCATED_PACKET_IRQM,Interrupt enable bit for long packet payload with too many/few bytes" "0,1"
newline
bitfld.long 0x14 10. "FRONT_LP_NO_PAYLOAD_IRQM,Interrupt enable bit for long packet header received with no payload" "0,1"
bitfld.long 0x14 9. "SP_INVALID_RCVD_IRQM,Interrupt enable bit for invalid short packet" "0,1"
newline
bitfld.long 0x14 8. "INVALID_ACCESS_IRQM,Interrupt enable bit for error_irqs_invalid_access" "0,1"
bitfld.long 0x14 7. "DATA_ID_IRQM,Interrupt enable bit for error_irqs_data_id" "0,1"
newline
bitfld.long 0x14 6. "HEADER_CORRECTED_ECC_IRQM,Interrupt enable bit for error_irqs_header_corrected_ecc" "0,1"
bitfld.long 0x14 5. "HEADER_ECC_IRQM,Interrupt enable bit for error_irqs_header_ecc" "0,1"
newline
bitfld.long 0x14 4. "PAYLOAD_CRC_IRQM,Interrupt enable bit for error_irqs_payload_crc" "0,1"
bitfld.long 0x14 0. "FRONT_FIFO_OVERFLOW_IRQM,Interrupt enable bit for error_irqs_front_fifo_overflow" "0,1"
group.long 0x40++0x03
line.long 0x00 "CSI_RX_IF_VBUS2APB_DPHY_LANE_CONTROL,DPHY lane control for data and clock lanes enables and resets"
bitfld.long 0x00 16. "CL_RESET,DPHY Clock lane Reset" "0,1"
bitfld.long 0x00 15. "DL3_RESET,DPHY data lane 3 Reset" "0,1"
newline
bitfld.long 0x00 14. "DL2_RESET,DPHY data lane 2 Reset" "0,1"
bitfld.long 0x00 13. "DL1_RESET,DPHY data lane 1 Reset" "0,1"
newline
bitfld.long 0x00 12. "DL0_RESET,DPHY data lane 0 Reset" "0,1"
bitfld.long 0x00 4. "CL_ENABLE,DPHY Clock lane Enable" "0,1"
newline
bitfld.long 0x00 3. "DL3_ENABLE,DPHY data lane 3 Enable" "0,1"
bitfld.long 0x00 2. "DL2_ENABLE,DPHY data lane 2 Enable" "0,1"
newline
bitfld.long 0x00 1. "DL1_ENABLE,DPHY data lane 1 Enable" "0,1"
bitfld.long 0x00 0. "DL0_ENABLE,DPHY data lane 0 Enable" "0,1"
rgroup.long 0x48++0x0B
line.long 0x00 "CSI_RX_IF_VBUS2APB_DPHY_STATUS,DPHY Clock and Data Lane mode status"
bitfld.long 0x00 22. "DL3_RXULPSESC,DPHY Data lane 3 ULPS Esc" "0,1"
bitfld.long 0x00 21. "DL3_ULPSACTIVENOT,DPHY Data lane 3 ULPSActiveNot" "0,1"
newline
bitfld.long 0x00 20. "DL3_STOPSTATE,DPHY Data lane 3 Stop State" "0,1"
bitfld.long 0x00 18. "DL2_RXULPSESC,DPHY Data lane 2 ULPS Esc" "0,1"
newline
bitfld.long 0x00 17. "DL2_ULPSACTIVENOT,DPHY Data lane 2 ULPSActiveNot" "0,1"
bitfld.long 0x00 16. "DL2_STOPSTATE,DPHY Data lane 2 Stop State" "0,1"
newline
bitfld.long 0x00 14. "DL1_RXULPSESC,DPHY Data lane 1 ULPS Esc" "0,1"
bitfld.long 0x00 13. "DL1_ULPSACTIVENOT,DPHY Data lane 1 ULPSActiveNot" "0,1"
newline
bitfld.long 0x00 12. "DL1_STOPSTATE,DPHY Data lane 1 Stop State" "0,1"
bitfld.long 0x00 10. "DL0_RXULPSESC,DPHY Data lane 0 ULPS Esc" "0,1"
newline
bitfld.long 0x00 9. "DL0_ULPSACTIVENOT,DPHY Data lane 0 ULPSActiveNot" "0,1"
bitfld.long 0x00 8. "DL0_STOPSTATE,DPHY Data lane 0 Stop State" "0,1"
newline
bitfld.long 0x00 2. "CL_RXULPSCLKNOT,DPHY Clock lane RxULPSClkNot" "0,1"
bitfld.long 0x00 1. "CL_ULPSACTIVENOT,DPHY Clock lane ULPSActiveNot" "0,1"
newline
bitfld.long 0x00 0. "CL_STOPSTATE,DPHY Clock lane Stop State" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_DPHY_ERR_STATUS_IRQ,DPHY error interrupt status"
bitfld.long 0x04 20. "DL3_ERRSOTHS_IRQ,DPHY Data lane 3 ErrSotHS" "0,1"
bitfld.long 0x04 16. "DL2_ERRSOTHS_IRQ,DPHY Data lane 2 ErrSotHS" "0,1"
newline
bitfld.long 0x04 12. "DL1_ERRSOTHS_IRQ,DPHY Data lane 1 ErrSotHS" "0,1"
bitfld.long 0x04 8. "DL0_ERRSOTHS_IRQ,DPHY Data lane 0 ErrSotHS" "0,1"
line.long 0x08 "CSI_RX_IF_VBUS2APB_DPHY_ERR_IRQ_MASK_CFG,DPHY error interrupt status"
bitfld.long 0x08 20. "DL3_ERRSOTHS_IRQM,DPHY Data lane 3 ErrSotHS mask" "0,1"
bitfld.long 0x08 16. "DL2_ERRSOTHS_IRQM,DPHY Data lane 2 ErrSotHS mask" "0,1"
newline
bitfld.long 0x08 12. "DL1_ERRSOTHS_IRQM,DPHY Data lane 1 ErrSotHS mask" "0,1"
bitfld.long 0x08 8. "DL0_ERRSOTHS_IRQM,DPHY Data lane 0 ErrSotHS mask" "0,1"
rgroup.long 0x60++0x03
line.long 0x00 "CSI_RX_IF_VBUS2APB_INTEGRATION_DEBUG,Used to observe the current data field. extracted by the protocol block from the last short packet data field and FSM state"
bitfld.long 0x00 28.--31. "PROT_FSM_STATE,csi2rx_fsm_state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--25. "PROT_VC,Protocol Virtual Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--21. "PROT_DT,Protocol Datatype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "PROT_WORD_COUNT,Protocol Word Count [Data Field]"
rgroup.long 0x74++0x03
line.long 0x00 "CSI_RX_IF_VBUS2APB_ERROR_DEBUG,Error condition debug"
hexmask.long.word 0x00 16.--31. 1. "DATA_FIELD,Indicates the Data Field for an invalid CRC/ECC/Data ID"
bitfld.long 0x00 6.--9. "VC,Indicates the Virtual Channel for a invalid CRC/ECC/Data ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--5. "DT,Indicates the Data Type for a invalid CRC/ECC/Data ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "CSI_RX_IF_VBUS2APB_TEST_GENERIC,Generic test control and status register that controls and reads primary I/O"
hexmask.long.word 0x00 16.--31. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain "
hexmask.long.word 0x00 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'"
group.long 0x100++0x2B
line.long 0x00 "CSI_RX_IF_VBUS2APB_STREAM0_CTRL,CSI2RX Stream Data output datapath control"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
newline
bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at" "0,1"
bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_STREAM0_STATUS,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
newline
bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "0,1,2,3"
line.long 0x08 "CSI_RX_IF_VBUS2APB_STREAM0_DATA_CFG,Secondary CSI2 Slave Controller Data outputs configuration"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed"
bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
newline
bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
newline
bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CSI_RX_IF_VBUS2APB_STREAM0_CFG,Primary CSI2 Slave Controller Data pixel outputs configuration"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO"
bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "0,1,2,3"
bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
newline
bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "CSI_RX_IF_VBUS2APB_STREAM0_MONITOR_CTRL,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
newline
bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "0,1"
newline
bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CSI_RX_IF_VBUS2APB_STREAM0_MONITOR_FRAME,Stream Monitor Frame"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "CSI_RX_IF_VBUS2APB_STREAM0_MONITOR_LB,Stream Monitor Line"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "CSI_RX_IF_VBUS2APB_STREAM0_TIMER,Stream Timer"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "CSI_RX_IF_VBUS2APB_STREAM0_FCC_CFG,Stream Frame Capture Control configuration"
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be"
hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be"
line.long 0x24 "CSI_RX_IF_VBUS2APB_STREAM0_FCC_CTRL,Stream Frame Capture Counter control"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "CSI_RX_IF_VBUS2APB_STREAM0_FIFO_FILL_LVL,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE," "0,1,2,3"
hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x200++0x2B
line.long 0x00 "CSI_RX_IF_VBUS2APB_STREAM1_CTRL,CSI2RX Stream Data output datapath control"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
newline
bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at" "0,1"
bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_STREAM1_STATUS,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
newline
bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "0,1,2,3"
line.long 0x08 "CSI_RX_IF_VBUS2APB_STREAM1_DATA_CFG,Secondary CSI2 Slave Controller Data outputs configuration"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed"
bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
newline
bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
newline
bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CSI_RX_IF_VBUS2APB_STREAM1_CFG,Primary CSI2 Slave Controller Data pixel outputs configuration"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO"
bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "0,1,2,3"
bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
newline
bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "CSI_RX_IF_VBUS2APB_STREAM1_MONITOR_CTRL,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
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bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "0,1"
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bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CSI_RX_IF_VBUS2APB_STREAM1_MONITOR_FRAME,Stream Monitor Frame"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "CSI_RX_IF_VBUS2APB_STREAM1_MONITOR_LB,Stream Monitor Line"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "CSI_RX_IF_VBUS2APB_STREAM1_TIMER,Stream Timer"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "CSI_RX_IF_VBUS2APB_STREAM1_FCC_CFG,Stream Frame Capture Control configuration"
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be"
hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be"
line.long 0x24 "CSI_RX_IF_VBUS2APB_STREAM1_FCC_CTRL,Stream Frame Capture Counter control"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "CSI_RX_IF_VBUS2APB_STREAM1_FIFO_FILL_LVL,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE," "0,1,2,3"
hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x300++0x2B
line.long 0x00 "CSI_RX_IF_VBUS2APB_STREAM2_CTRL,CSI2RX Stream Data output datapath control"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
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bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at" "0,1"
bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_STREAM2_STATUS,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
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bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "0,1,2,3"
line.long 0x08 "CSI_RX_IF_VBUS2APB_STREAM2_DATA_CFG,Secondary CSI2 Slave Controller Data outputs configuration"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed"
bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
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bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
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bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CSI_RX_IF_VBUS2APB_STREAM2_CFG,Primary CSI2 Slave Controller Data pixel outputs configuration"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO"
bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "0,1,2,3"
bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
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bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "CSI_RX_IF_VBUS2APB_STREAM2_MONITOR_CTRL,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
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bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "0,1"
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bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CSI_RX_IF_VBUS2APB_STREAM2_MONITOR_FRAME,Stream Monitor Frame"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "CSI_RX_IF_VBUS2APB_STREAM2_MONITOR_LB,Stream Monitor Line"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "CSI_RX_IF_VBUS2APB_STREAM2_TIMER,Stream Timer"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "CSI_RX_IF_VBUS2APB_STREAM2_FCC_CFG,Stream Frame Capture Control configuration"
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be"
hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be"
line.long 0x24 "CSI_RX_IF_VBUS2APB_STREAM2_FCC_CTRL,Stream Frame Capture Counter control"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "CSI_RX_IF_VBUS2APB_STREAM2_FIFO_FILL_LVL,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE," "0,1,2,3"
hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x400++0x2B
line.long 0x00 "CSI_RX_IF_VBUS2APB_STREAM3_CTRL,CSI2RX Stream Data output datapath control"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
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bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at" "0,1"
bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_STREAM3_STATUS,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
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bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "0,1,2,3"
line.long 0x08 "CSI_RX_IF_VBUS2APB_STREAM3_DATA_CFG,Secondary CSI2 Slave Controller Data outputs configuration"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed"
bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
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bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
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bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CSI_RX_IF_VBUS2APB_STREAM3_CFG,Primary CSI2 Slave Controller Data pixel outputs configuration"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO"
bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "0,1,2,3"
bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
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bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "CSI_RX_IF_VBUS2APB_STREAM3_MONITOR_CTRL,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
newline
bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "0,1"
newline
bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CSI_RX_IF_VBUS2APB_STREAM3_MONITOR_FRAME,Stream Monitor Frame"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "CSI_RX_IF_VBUS2APB_STREAM3_MONITOR_LB,Stream Monitor Line"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "CSI_RX_IF_VBUS2APB_STREAM3_TIMER,Stream Timer"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "CSI_RX_IF_VBUS2APB_STREAM3_FCC_CFG,Stream Frame Capture Control configuration"
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be"
hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be"
line.long 0x24 "CSI_RX_IF_VBUS2APB_STREAM3_FCC_CTRL,Stream Frame Capture Counter control"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "CSI_RX_IF_VBUS2APB_STREAM3_FIFO_FILL_LVL,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE," "0,1,2,3"
hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x900++0x13
line.long 0x00 "CSI_RX_IF_VBUS2APB_ASF_INT_STATUS,ASF Interrupt Status Register"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_ASF_INT_RAW_STATUS,ASF Interrupt Raw Status Register"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "CSI_RX_IF_VBUS2APB_ASF_INT_MASK,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "CSI_RX_IF_VBUS2APB_ASF_INT_TEST,The ASF interrupt test register emulate hardware even"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt" "0,1"
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bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "CSI_RX_IF_VBUS2APB_ASF_FATAL_NONFATAL_SELECT,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x920++0x0B
line.long 0x00 "CSI_RX_IF_VBUS2APB_ASF_SRAM_CORR_FAULT_STATUS,Status register for SRAM correctable fault"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "CSI_RX_IF_VBUS2APB_ASF_SRAM_UNCORR_FAULT_STATUS,Status register for SRAM uncorrectable fault"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "CSI_RX_IF_VBUS2APB_ASF_SRAM_FAULT_STATS,Statistics register for SRAM faults"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x930++0x0B
line.long 0x00 "CSI_RX_IF_VBUS2APB_ASF_TRANS_TO_CTRL,Control register to configure the ASF transaction timeout monitors"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "CSI_RX_IF_VBUS2APB_ASF_TRANS_TO_FAULT_MASK,Control register to mask out ASF transaction timeout faults from triggering interrupts"
bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
line.long 0x08 "CSI_RX_IF_VBUS2APB_ASF_TRANS_TO_FAULT_STATUS,Status register for transaction timeouts fault"
bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults" "0,1"
group.long 0x940++0x07
line.long 0x00 "CSI_RX_IF_VBUS2APB_ASF_PROTOCOL_FAULT_MASK,Control register to mask out ASF Protocol faults from triggering interrupts"
bitfld.long 0x00 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source" "0,1"
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bitfld.long 0x00 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source" "0,1"
line.long 0x04 "CSI_RX_IF_VBUS2APB_ASF_PROTOCOL_FAULT_STATUS,Status register for protocol faults"
bitfld.long 0x04 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "CSI_RX_IF_VBUS2APB_ID_PROD_VER,This register is hard-coded in order to allow software to identify the product and its release version"
hexmask.long.word 0x00 16.--31. 1. "PRODUCT_ID,Product Identification Number [IP5022/IP5022A]"
hexmask.long.word 0x00 0.--15. 1. "VERSION_ID,Product Version Number [R200]"
tree.end
repeat.end
tree.end
tree "CSI_TX_IF"
tree "CSI_TX_IF0_CP_INTD_CFG_INTD_CFG"
base ad:0x4408000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_TX_IF_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "CSI_TX_IF_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CSI_TX_IF_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x07
line.long 0x00 "CSI_TX_IF_ENABLE_REG_LEVEL_0,Enable Register 0"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_RETRANS3,Enable Set for level_en_retrans3" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_RETRANS2,Enable Set for level_en_retrans2" "0,1"
line.long 0x04 "CSI_TX_IF_ENABLE_REG_PULSE_0,Enable Register 1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_RETRANS3,Enable Set for pulse_en_retrans3" "0,1"
bitfld.long 0x04 0. "ENABLE_PULSE_EN_RETRANS2,Enable Set for pulse_en_retrans2" "0,1"
group.long 0x300++0x07
line.long 0x00 "CSI_TX_IF_ENABLE_CLR_REG_LEVEL_0,Enable Clear Register 0"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_RETRANS3_CLR,Enable Clear for level_en_retrans3" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_RETRANS2_CLR,Enable Clear for level_en_retrans2" "0,1"
line.long 0x04 "CSI_TX_IF_ENABLE_CLR_REG_PULSE_0,Enable Clear Register 1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_RETRANS3_CLR,Enable Clear for pulse_en_retrans3" "0,1"
bitfld.long 0x04 0. "ENABLE_PULSE_EN_RETRANS2_CLR,Enable Clear for pulse_en_retrans2" "0,1"
group.long 0x500++0x07
line.long 0x00 "CSI_TX_IF_STATUS_REG_LEVEL_0,Status Register 0"
bitfld.long 0x00 1. "STATUS_LEVEL_RETRANS3,Status write 1 to set for level_en_retrans3" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_RETRANS2,Status write 1 to set for level_en_retrans2" "0,1"
line.long 0x04 "CSI_TX_IF_STATUS_REG_PULSE_0,Status Register 1"
bitfld.long 0x04 1. "STATUS_PULSE_RETRANS3,Status write 1 to set for pulse_en_retrans3" "0,1"
bitfld.long 0x04 0. "STATUS_PULSE_RETRANS2,Status write 1 to set for pulse_en_retrans2" "0,1"
group.long 0x700++0x07
line.long 0x00 "CSI_TX_IF_STATUS_CLR_REG_LEVEL_0,Status Clear Register 0"
bitfld.long 0x00 1. "STATUS_LEVEL_RETRANS3_CLR,Status write 1 to clear for level_en_retrans3" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_RETRANS2_CLR,Status write 1 to clear for level_en_retrans2" "0,1"
line.long 0x04 "CSI_TX_IF_STATUS_CLR_REG_PULSE_0,Status Clear Register 1"
bitfld.long 0x04 1. "STATUS_PULSE_RETRANS3_CLR,Status write 1 to clear for pulse_en_retrans3" "0,1"
bitfld.long 0x04 0. "STATUS_PULSE_RETRANS2_CLR,Status write 1 to clear for pulse_en_retrans2" "0,1"
rgroup.long 0xA80++0x07
line.long 0x00 "CSI_TX_IF_INTR_VECTOR_REG_LEVEL,Interrupt Vector for level"
line.long 0x04 "CSI_TX_IF_INTR_VECTOR_REG_PULSE,Interrupt Vector for pulse"
tree.end
tree "CSI_TX_IF0_ECC_AGGR_BYTE_CFG"
base ad:0x2A38400
rgroup.long 0x00++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or CSI_TX_IF_ECC_AGGR_BYTE_STATUS"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_BYTE_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CSI_TX_IF_ECC_AGGR_BYTE_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_BYTE_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 3. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
newline
bitfld.long 0x04 0. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 3. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_BYTE_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 3. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
newline
bitfld.long 0x04 0. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 3. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CSI_TX_IF_ECC_AGGR_BYTE_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_BYTE_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CSI_TX_IF_ECC_AGGR_BYTE_AGGR_STATUS_SET,AGGR interrupt CSI_TX_IF_ECC_AGGR_BYTE_STATUS set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt CSI_TX_IF_ECC_AGGR_BYTE_STATUS set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt CSI_TX_IF_ECC_AGGR_BYTE_STATUS set for parity errors" "0,1,2,3"
line.long 0x0C "CSI_TX_IF_ECC_AGGR_BYTE_AGGR_STATUS_CLR,AGGR interrupt CSI_TX_IF_ECC_AGGR_BYTE_STATUS clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt CSI_TX_IF_ECC_AGGR_BYTE_STATUS clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt CSI_TX_IF_ECC_AGGR_BYTE_STATUS clear for parity errors" "0,1,2,3"
tree.end
tree "CSI_TX_IF0_ECC_AGGR_CFG"
base ad:0x2A38000
rgroup.long 0x00++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CSI_TX_IF_ECC_AGGR_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or CSI_TX_IF_ECC_AGGR_STATUS"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CSI_TX_IF_ECC_AGGR_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CSI_TX_IF_ECC_AGGR_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 2. "FDRAM_RAMECC_PEND,Interrupt Pending Status for fdram_ramecc_pend" "0,1"
bitfld.long 0x04 1. "FIFO_RAMECC_PEND,Interrupt Pending Status for fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "FDRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fdram_ramecc_pend" "0,1"
bitfld.long 0x00 1. "FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "FDRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fdram_ramecc_pend" "0,1"
bitfld.long 0x00 1. "FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CSI_TX_IF_ECC_AGGR_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 2. "FDRAM_RAMECC_PEND,Interrupt Pending Status for fdram_ramecc_pend" "0,1"
bitfld.long 0x04 1. "FIFO_RAMECC_PEND,Interrupt Pending Status for fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "FDRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fdram_ramecc_pend" "0,1"
bitfld.long 0x00 1. "FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CSI_TX_IF_ECC_AGGR_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "FDRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fdram_ramecc_pend" "0,1"
bitfld.long 0x00 1. "FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CSI_TX_IF_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CSI_TX_IF_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CSI_TX_IF_ECC_AGGR_STATUS_SET,AGGR interrupt CSI_TX_IF_ECC_AGGR_STATUS set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt CSI_TX_IF_ECC_AGGR_STATUS set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt CSI_TX_IF_ECC_AGGR_STATUS set for parity errors" "0,1,2,3"
line.long 0x0C "CSI_TX_IF_ECC_AGGR_STATUS_CLR,AGGR interrupt CSI_TX_IF_ECC_AGGR_STATUS clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt CSI_TX_IF_ECC_AGGR_STATUS clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt CSI_TX_IF_ECC_AGGR_STATUS clear for parity errors" "0,1,2,3"
tree.end
tree "CSI_TX_IF0_TX_SHIM_VBUSP_MMR_CSI2TXIF"
base ad:0x4400000
rgroup.long 0x00++0x0F
line.long 0x00 "CSI_TX_IF_CSITX_ID,PID"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINREV,min" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CSI_TX_IF_COLOR_CNTL,color bar control register"
bitfld.long 0x04 16.--19. "VCHNL,color bar virtual channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--10. "DTYPE,color bar data type data sel" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "EN," "0,1"
line.long 0x08 "CSI_TX_IF_COLOR_PARAM,color bar frame parameters"
hexmask.long.word 0x08 16.--28. 1. "IH_CFG,input height in units of pixels minus 1"
hexmask.long.word 0x08 0.--12. 1. "IW_CFG,input width in units of pixels minus 1"
line.long 0x0C "CSI_TX_IF_COLOR_START_DELAY,delay from starting first line after enabling"
group.long 0x20++0x0F
line.long 0x00 "CSI_TX_IF_COLOR_LINE_DELAY,last line start to next line start delay"
line.long 0x04 "CSI_TX_IF_COLOR_FRAME_DELAY,line start to next frame start delay"
line.long 0x08 "CSI_TX_IF_RETRANS_CNTL,retransmit control register"
bitfld.long 0x08 16.--19. "VC1,virtual channel of csi tx to send out stream4 interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "VC0,virtual channel of csi tx to send out stream3 interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CSI_TX_IF_CONTROL1,control register for csi tx wrapper"
rbitfld.long 0x0C 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x0C 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x0C 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x0C 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
bitfld.long 0x0C 0. "PIXEL_RESET,reset for the pixeal interface" "0,1"
group.long 0x40++0x03
line.long 0x00 "CSI_TX_IF_F2F_DELAY_y,last line start to next frame start"
group.long 0x100++0x07
line.long 0x00 "CSI_TX_IF_DMACNTX_j,DMA Channel Context"
bitfld.long 0x00 28. "YUV420_CFG,yuv422 format enable" "0,1"
bitfld.long 0x00 26.--27. "YUV422_MODE_CFG,yuv422 mode" "0,1,2,3"
bitfld.long 0x00 25. "YUV422_CFG,yuv422 format enable" "0,1"
bitfld.long 0x00 23. "PACK12_CFG,pack12 format enable 0" "0,1"
bitfld.long 0x00 20.--21. "SIZE_CFG,data size shift when unpacking " "0,1,2,3"
bitfld.long 0x00 6.--9. "VIRTCH_CFG,CSI virtual channel index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--5. "DATSEL_CFG,CSI data type index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CSI_TX_IF_L2L_DELAY_j,line to line delay"
tree.end
tree "CSI_TX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX"
base ad:0x4404000
rgroup.long 0x00++0x17
line.long 0x00 "CSI_TX_IF_DEVICE_CONFIG,CSI2 Transmitter Device Configuration Register"
bitfld.long 0x00 19. "ASF_PRESENT,Active Internal Diagnostic Features" "0,1"
bitfld.long 0x00 14.--18. "NUM_DTS,Number of Datatypes DT_NUMBER=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--13. "NUM_VCS,Number of Virtual Channels VC_NUMBER=16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7.--8. "DATAPATH_SIZE,Internal Datapath width" "0,1,2,3"
bitfld.long 0x00 4.--6. "NUM_STREAMS,Number of Stream interfaces" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "CDNS_PHY_PRESENT,DPHY present" "0,1"
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bitfld.long 0x00 0.--2. "MAX_LANE_NB,Max Number of Lanes" "0,1,2,3,4,5,6,7"
line.long 0x04 "CSI_TX_IF_STATUS,CSI2 Transmitter Status Register"
hexmask.long 0x04 7.--31. 1. "UNUSED,Reserved"
bitfld.long 0x04 6. "ULP_MODE_ACTIVE,Ultra Low Power Mode Active Flag When HIGH this bit indicates that ultra low power mode is active" "0,1"
bitfld.long 0x04 5. "HS_MODE_ACTIVE,High Speed Mode Active Flag When HIGH this bit indicates that high speed mode is active" "0,1"
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bitfld.long 0x04 4. "FRAME_TRANSMISSION_ACTIVE,Frame Transmission Active Flag When HIGH this bit indicates that frame transmission is active" "0,1"
bitfld.long 0x04 2. "CONFIGURATION_ACTIVE,Configuration Mode Active Flag When HIGH this bit indicates that the CSI2TX module is in the configuration mode" "0,1"
bitfld.long 0x04 1. "SOFT_RESET_ACTIVE,Soft Reset Active Flag When HIGH this bit indicates that soft reset is active" "0,1"
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bitfld.long 0x04 0. "BYPASS_MODE_ACTIVE,Bypass Mode Active Flag When HIGH this bit indicates that bypass mode is active" "0,1"
line.long 0x08 "CSI_TX_IF_IRQ,CSI2 Transmitter Interrupt Register"
bitfld.long 0x08 31. "LINE_NUMBER_ERROR3,Pixel IF 3 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred" "0,1"
bitfld.long 0x08 30. "BYTE_COUNT_MISMATCH_IRQ3,Pixel IF 3 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred" "0,1"
bitfld.long 0x08 29. "DATA_FLOW_ERR_IRQ3,Pixel IF 3 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the DPhy is not ready" "0,1"
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bitfld.long 0x08 28. "FIFO_UNDERFLOW_IRQ3,Pixel IF 3 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred" "0,1"
bitfld.long 0x08 27. "LINE_END_IRQ3,Pixel IF 3 Line End Flag - When HIGH this bit indicates that a line end occurred" "0,1"
bitfld.long 0x08 26. "LINE_START_IRQ3,Pixel IF 3 Line Start Flag - When HIGH this bit indicates that a line start occurred" "0,1"
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bitfld.long 0x08 25. "FRAME_END_IRQ3,Pixel IF 3 Frame End Flag - When HIGH this bit indicates that a frame end occurred" "0,1"
bitfld.long 0x08 24. "FRAME_START_IRQ3,Pixel IF 3 Frame Start Flag - When HIGH this bit indicates that a frame start occurred" "0,1"
bitfld.long 0x08 23. "LINE_NUMBER_ERROR2,Pixel IF 2 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred" "0,1"
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bitfld.long 0x08 22. "BYTE_COUNT_MISMATCH_IRQ2,Pixel IF 2 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred" "0,1"
bitfld.long 0x08 21. "DATA_FLOW_ERR_IRQ2,Pixel IF 2 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the DPhy is not ready" "0,1"
bitfld.long 0x08 20. "FIFO_UNDERFLOW_IRQ2,Pixel IF 2 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred" "0,1"
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bitfld.long 0x08 19. "LINE_END_IRQ2,Pixel IF 2 Line End Flag - When HIGH this bit indicates that a line end occurred" "0,1"
bitfld.long 0x08 18. "LINE_START_IRQ2,Pixel IF 2 Line Start Flag - When HIGH this bit indicates that a line start occurred" "0,1"
bitfld.long 0x08 17. "FRAME_END_IRQ2,Pixel IF 2 Frame End Flag - When HIGH this bit indicates that a frame end occurred" "0,1"
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bitfld.long 0x08 16. "FRAME_START_IRQ2,Pixel IF 2 Frame Start Flag - When HIGH this bit indicates that a frame start occurred" "0,1"
bitfld.long 0x08 15. "LINE_NUMBER_ERROR1,Pixel IF 1 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred" "0,1"
bitfld.long 0x08 14. "BYTE_COUNT_MISMATCH_IRQ1,Pixel IF 1 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred" "0,1"
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bitfld.long 0x08 13. "DATA_FLOW_ERR_IRQ1,Pixel IF 1 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the DPhy is not ready" "0,1"
bitfld.long 0x08 12. "FIFO_UNDERFLOW_IRQ1,Pixel IF 1 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred" "0,1"
bitfld.long 0x08 11. "LINE_END_IRQ1,Pixel IF 1 Line End Flag - When HIGH this bit indicates that a line end occurred" "0,1"
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bitfld.long 0x08 10. "LINE_START_IRQ1,Pixel IF 1 Line Start Flag - When HIGH this bit indicates that a line start occurred" "0,1"
bitfld.long 0x08 9. "FRAME_END_IRQ1,Pixel IF 1 Frame End Flag - When HIGH this bit indicates that a frame end occurred" "0,1"
bitfld.long 0x08 8. "FRAME_START_IRQ1,Pixel IF 1 Frame Start Flag - When HIGH this bit indicates that a frame start occurred" "0,1"
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bitfld.long 0x08 7. "LINE_NUMBER_ERROR0,Pixel IF 0 Line Number Error Flag - When HIGH this bit indicates that a line number error occurred" "0,1"
bitfld.long 0x08 6. "BYTE_COUNT_MISMATCH_IRQ0,Pixel IF 0 Byte Count Mismatch Flag - When HIGH this bit indicates that a byte count mismatch occurred" "0,1"
bitfld.long 0x08 5. "DATA_FLOW_ERR_IRQ0,Pixel IF 0 Data Flow Error Flag - When HIGH this bit indicates that data flow error has occurred caused by the Frame/Line valid being asserted when the DPhy is not ready" "0,1"
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bitfld.long 0x08 4. "FIFO_UNDERFLOW_IRQ0,Pixel IF 0 FIFO Underflow Flag - When HIGH this bit indicates that at least one internal FIFO underflow occurred" "0,1"
bitfld.long 0x08 3. "LINE_END_IRQ0,Pixel IF 0 Line End Flag - When HIGH this bit indicates that a line end occurred" "0,1"
bitfld.long 0x08 2. "LINE_START_IRQ0,Pixel IF 0 Line Start Flag - When HIGH this bit indicates that a line start occurred" "0,1"
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bitfld.long 0x08 1. "FRAME_END_IRQ0,Pixel IF 0 Frame End Flag - When HIGH this bit indicates that a frame end occurred" "0,1"
bitfld.long 0x08 0. "FRAME_START_IRQ0,Pixel IF 0 Frame Start Flag - When HIGH this bit indicates that a frame start occurred" "0,1"
line.long 0x0C "CSI_TX_IF_IRQ_MASK,CSI2 Transmitter Interrupt Mask Set Register"
bitfld.long 0x0C 31. "MASK_LINE_NUMBER_ERROR3,Pixel IF 3 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit" "0,1"
bitfld.long 0x0C 30. "MASK_BYTE_COUNT_MISMATCH_IRQ3,Pixel IF 3 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit" "0,1"
bitfld.long 0x0C 29. "MASK_DATA_FLOW_ERR_IRQ3,Pixel IF 3 FIFO Overflow Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit" "0,1"
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bitfld.long 0x0C 28. "MASK_FIFO_UNDERFLOW_IRQ3,Pixel IF 3 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit" "0,1"
bitfld.long 0x0C 27. "MASK_LINE_END_IRQ3,Pixel IF 3 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit" "0,1"
bitfld.long 0x0C 26. "MASK_LINE_START_IRQ3,Pixel IF 3 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit" "0,1"
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bitfld.long 0x0C 25. "MASK_FRAME_END_IRQ3,Pixel IF 3 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit" "0,1"
bitfld.long 0x0C 24. "MASK_FRAME_START_IRQ3,Pixel IF 3 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit" "0,1"
bitfld.long 0x0C 23. "MASK_LINE_NUMBER_ERROR2,Pixel IF 2 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit" "0,1"
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bitfld.long 0x0C 22. "MASK_BYTE_COUNT_MISMATCH_IRQ2,Pixel IF 2 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit" "0,1"
bitfld.long 0x0C 21. "MASK_DATA_FLOW_ERR_IRQ2,Pixel IF 2 FIFO Overflow Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit" "0,1"
bitfld.long 0x0C 20. "MASK_FIFO_UNDERFLOW_IRQ2,Pixel IF 2 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit" "0,1"
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bitfld.long 0x0C 19. "MASK_LINE_END_IRQ2,Pixel IF 2 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit" "0,1"
bitfld.long 0x0C 18. "MASK_LINE_START_IRQ2,Pixel IF 2 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit" "0,1"
bitfld.long 0x0C 17. "MASK_FRAME_END_IRQ2,Pixel IF 2 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit" "0,1"
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bitfld.long 0x0C 16. "MASK_FRAME_START_IRQ2,Pixel IF 2 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit" "0,1"
bitfld.long 0x0C 15. "MASK_LINE_NUMBER_ERROR1,Pixel IF 1 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit" "0,1"
bitfld.long 0x0C 14. "MASK_BYTE_COUNT_MISMATCH_IRQ1,Pixel IF 1 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit" "0,1"
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bitfld.long 0x0C 13. "MASK_DATA_FLOW_ERR_IRQ1,Pixel IF 1 FIFO Overflow Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit" "0,1"
bitfld.long 0x0C 12. "MASK_FIFO_UNDERFLOW_IRQ1,Pixel IF 1 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit" "0,1"
bitfld.long 0x0C 11. "MASK_LINE_END_IRQ1,Pixel IF 1 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit" "0,1"
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bitfld.long 0x0C 10. "MASK_LINE_START_IRQ1,Pixel IF 1 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit" "0,1"
bitfld.long 0x0C 9. "MASK_FRAME_END_IRQ1,Pixel IF 1 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit" "0,1"
bitfld.long 0x0C 8. "MASK_FRAME_START_IRQ1,Pixel IF 1 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit" "0,1"
newline
bitfld.long 0x0C 7. "MASK_LINE_NUMBER_ERROR0,Pixel IF 0 Line Number Error Mask - Writing 1 to this bit enables interrupt generation from the line_number_error_irq bit" "0,1"
bitfld.long 0x0C 6. "MASK_BYTE_COUNT_MISMATCH_IRQ0,Pixel IF 0 Byte Count Mismatch Mask - Writing 1 to this bit enables interrupt generation from the byte_count_mismatch_irq bit" "0,1"
bitfld.long 0x0C 5. "MASK_DATA_FLOW_ERR_IRQ0,Pixel IF 0 FIFO Overflow Mask - Writing 1 to this bit enables interrupt generation from the data_flow_err_irq bit" "0,1"
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bitfld.long 0x0C 4. "MASK_FIFO_UNDERFLOW_IRQ0,Pixel IF 0 FIFO Underflow Mask - Writing 1 to this bit enables interrupt generation from the fifo_underflow_irq bit" "0,1"
bitfld.long 0x0C 3. "MASK_LINE_END_IRQ0,Pixel IF 0 Line End Mask - Writing 1 to this bit enables interrupt generation from the line_en_irq bit" "0,1"
bitfld.long 0x0C 2. "MASK_LINE_START_IRQ0,Pixel IF 0 Line Start Mask - Writing 1 to this bit enables interrupt generation from the line_start_irq bit" "0,1"
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bitfld.long 0x0C 1. "MASK_FRAME_END_IRQ0,Pixel IF 0 Frame End Mask - Writing 1 to this bit enables interrupt generation from the frame_end_irq bit" "0,1"
bitfld.long 0x0C 0. "MASK_FRAME_START_IRQ0,Pixel IF 0 Frame Start Mask - Writing 1 to this bit enables interrupt generation from the frame_start_irq bit" "0,1"
line.long 0x10 "CSI_TX_IF_DPHY_IRQ,DPHY Transmitter Interrupt Status"
bitfld.long 0x10 15. "ERR_CTRL_TX3_IRQ,DPHY Transmitter Lane 3 ERR_CONTROL_IRQ" "0,1"
bitfld.long 0x10 14. "ERR_CTRL_TX2_IRQ,DPHY Transmitter Lane 2 ERR_CONTROL_IRQ" "0,1"
bitfld.long 0x10 13. "ERR_CTRL_TX1_IRQ,DPHY Transmitter Lane 1 ERR_CONTROL_IRQ" "0,1"
newline
bitfld.long 0x10 12. "ERR_CTRL_TX0_IRQ,DPHY Transmitter Lane 0 ERR_CONTROL_IRQ" "0,1"
bitfld.long 0x10 11. "ERR_ESC_TX3_IRQ,DPHY Transmitter Lane 3 ERR_ESC_IRQ" "0,1"
bitfld.long 0x10 10. "ERR_ESC_TX2_IRQ,DPHY Transmitter Lane 2 ERR_ESC_IRQ" "0,1"
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bitfld.long 0x10 9. "ERR_ESC_TX1_IRQ,DPHY Transmitter Lane 1 ERR_ESC_IRQ" "0,1"
bitfld.long 0x10 8. "ERR_ESC_TX0_IRQ,DPHY Transmitter Lane 0 ERR_ESC_IRQ" "0,1"
bitfld.long 0x10 7. "ERR_SYNC_TX3_IRQ,DPHY Transmitter Lane 3 ERR_SYNC_ESC_IRQ" "0,1"
newline
bitfld.long 0x10 6. "ERR_SYNC_TX2_IRQ,DPHY Transmitter Lane 2 ERR_SYNC_ESC_IRQ" "0,1"
bitfld.long 0x10 5. "ERR_SYNC_TX1_IRQ,DPHY Transmitter Lane 1 ERR_SYNC_ESC_IRQ" "0,1"
bitfld.long 0x10 4. "ERR_SYNC_TX0_IRQ,DPHY Transmitter Lane 0 ERR_SYNC_ESC_IRQ" "0,1"
line.long 0x14 "CSI_TX_IF_DPHY_IRQ_MASK,DPHY Transmitter Interrupt Mask"
bitfld.long 0x14 15. "MASK_ERR_CTRL_TX3_IRQ,DPHY Transmitter Mask Lane 3 ERR_CONTROL_IRQ" "0,1"
bitfld.long 0x14 14. "MASK_ERR_CTRL_TX2_IRQ,DPHY Transmitter Mask Lane 2 ERR_CONTROL_IRQ" "0,1"
bitfld.long 0x14 13. "MASK_ERR_CTRL_TX1_IRQ,DPHY Transmitter Mask Lane 1 ERR_CONTROL_IRQ" "0,1"
newline
bitfld.long 0x14 12. "MASK_ERR_CTRL_TX0_IRQ,DPHY Transmitter Mask Lane 0 ERR_CONTROL_IRQ" "0,1"
bitfld.long 0x14 11. "MASK_ERR_ESC_TX3_IRQ,DPHY Transmitter Mask Lane 3 ERR_ESC_IRQ" "0,1"
bitfld.long 0x14 10. "MASK_ERR_ESC_TX2_IRQ,DPHY Transmitter Mask Lane 2 ERR_ESC_IRQ" "0,1"
newline
bitfld.long 0x14 9. "MASK_ERR_ESC_TX1_IRQ,DPHY Transmitter Mask Lane 1 ERR_ESC_IRQ" "0,1"
bitfld.long 0x14 8. "MASK_ERR_ESC_TX0_IRQ,DPHY Transmitter Mask Lane 0 ERR_ESC_IRQ" "0,1"
bitfld.long 0x14 7. "MASK_ERR_SYNC_TX3_IRQ,DPHY Transmitter Mask Lane 3 ERR_SYNC_ESC_IRQ" "0,1"
newline
bitfld.long 0x14 6. "MASK_ERR_SYNC_TX2_IRQ,DPHY Transmitter Mask Lane 2 ERR_SYNC_ESC_IRQ" "0,1"
bitfld.long 0x14 5. "MASK_ERR_SYNC_TX1_IRQ,DPHY Transmitter Mask Lane 1 ERR_SYNC_ESC_IRQ" "0,1"
bitfld.long 0x14 4. "MASK_ERR_SYNC_TX0_IRQ,DPHY Transmitter Mask Lane 0 ERR_SYNC_ESC_IRQ" "0,1"
group.long 0x20++0x13
line.long 0x00 "CSI_TX_IF_TX_CONF,CSI2 Transmitter Configuration Register"
bitfld.long 0x00 31. "IRQ_ENABLE,Interrupt Enable - Writing 1 to this bit enables interrupts" "0,1"
bitfld.long 0x00 2. "CONFIGURATION_REQUEST,Configuration Request - Writing 1 to this bit enables configuration mode" "0,1"
bitfld.long 0x00 1. "SOFT_RESET_REQUEST,Soft Reset Request - Writing 1 to this bit enables soft reset" "0,1"
newline
bitfld.long 0x00 0. "BYPASS_MODE_ENABLE,Bypass Mode - Enable Writing 1 to this bit enables bypass mode" "0,1"
line.long 0x04 "CSI_TX_IF_WAIT_BURST_TIME,CSI2 Transmitter DPHY Wait Time configuration Register"
hexmask.long.byte 0x04 16.--23. 1. "TX_CLOCK_EXIT_TIME,Tx clock exit time - Number of tx_byte_clk cycles corresponding to the HS clock exit time"
hexmask.long.byte 0x04 0.--7. 1. "WAIT_BURST_TIME_CNT,Wait Burst Time - Number of tx_byte_clk cycles corresponding to the inter HS burst gap"
line.long 0x08 "CSI_TX_IF_DPHY_CFG,CSI2 Transmitter DPHY Lane Enable configuration Register"
bitfld.long 0x08 16. "DPHY_CLK_RESET,DPHY Clock Lane Reset - Active low reset for DPHY clock lane" "0,1"
bitfld.long 0x08 15. "DPHY_LN_3_RESET,DPHY Line 0 Reset - Active low reset for DPHY data lane 3" "0,1"
bitfld.long 0x08 14. "DPHY_LN_2_RESET,DPHY Line 0 Reset - Active low reset for DPHY data lane 2" "0,1"
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bitfld.long 0x08 13. "DPHY_LN_1_RESET,DPHY Line 0 Reset - Active low reset for DPHY data lane 1" "0,1"
bitfld.long 0x08 12. "DPHY_LN_0_RESET,DPHY Line 0 Reset - Active low reset for DPHY data lane 0" "0,1"
bitfld.long 0x08 11. "DPHY_CAL_ENABLE,DPHY Calibration Enable" "0,1"
newline
bitfld.long 0x08 10. "DPHY_CLOCK_MODE,DPHY Clock Mode" "0,1"
bitfld.long 0x08 8.--9. "DPHY_MODE,DPHY Mode" "0,1,2,3"
bitfld.long 0x08 4. "DPHY_CLK_ENABLE,DPHY Clock Lane - Active high enable for DPHY clock lane" "0,1"
newline
bitfld.long 0x08 3. "DPHY_LN_3_ENABLE,DPHY Lane 3 Enable - Active high enable for DPHY data lane 0" "0,1"
bitfld.long 0x08 2. "DPHY_LN_2_ENABLE,DPHY Lane 2 Enable - Active high enable for DPHY data lane 0" "0,1"
bitfld.long 0x08 1. "DPHY_LN_1_ENABLE,DPHY Lane 1 Enable - Active high enable for DPHY data lane 0" "0,1"
newline
bitfld.long 0x08 0. "DPHY_LN_0_ENABLE,DPHY Lane 0 Enable - Active high enable for DPHY data lane 0" "0,1"
line.long 0x0C "CSI_TX_IF_DPHY_CLK_WAKEUP,CSI2 Transmitter DPHY Clock Lane wakeup time configuration Register"
hexmask.long.word 0x0C 0.--15. 1. "ULPS_CLK_LANE_WAKEUP,DPHY clock lane wakeup time in esc_clk cycles"
line.long 0x10 "CSI_TX_IF_DPHY_ULPS_WAKEUP,CSI2 Transmitter DPHY Data Lane wakeup time configuration Register"
hexmask.long.word 0x10 0.--15. 1. "ULPS_DATA_LANE_WAKEUP,DPHY data lane wakeup time in in esc_clk cycles"
group.long 0x40++0x7F
line.long 0x00 "CSI_TX_IF_VC0_CFG,CSI2 Transmitter Virtual Channel 0 Configuration Register"
hexmask.long.word 0x00 16.--31. 1. "VC_0_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 0"
bitfld.long 0x00 0. "VC_0_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 0" "0,1"
line.long 0x04 "CSI_TX_IF_VC1_CFG,CSI2 Transmitter Virtual Channel 1 Configuration Register"
hexmask.long.word 0x04 16.--31. 1. "VC_1_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 1"
bitfld.long 0x04 0. "VC_1_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 1" "0,1"
line.long 0x08 "CSI_TX_IF_VC2_CFG,CSI2 Transmitter Virtual Channel 2 Configuration Register"
hexmask.long.word 0x08 16.--31. 1. "VC_2_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 2"
bitfld.long 0x08 0. "VC_2_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 2" "0,1"
line.long 0x0C "CSI_TX_IF_VC3_CFG,CSI2 Transmitter Virtual Channel 3 Configuration Register"
hexmask.long.word 0x0C 16.--31. 1. "VC_3_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 3"
bitfld.long 0x0C 0. "VC_3_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 3" "0,1"
line.long 0x10 "CSI_TX_IF_VC4_CFG,CSI2 Transmitter Virtual Channel 4 Configuration Register"
hexmask.long.word 0x10 16.--31. 1. "VC_4_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 4"
bitfld.long 0x10 0. "VC_4_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 4" "0,1"
line.long 0x14 "CSI_TX_IF_VC5_CFG,CSI2 Transmitter Virtual Channel 5 Configuration Register"
hexmask.long.word 0x14 16.--31. 1. "VC_5_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 5"
bitfld.long 0x14 0. "VC_5_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 5" "0,1"
line.long 0x18 "CSI_TX_IF_VC6_CFG,CSI2 Transmitter Virtual Channel 6 Configuration Register"
hexmask.long.word 0x18 16.--31. 1. "VC_6_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 6"
bitfld.long 0x18 0. "VC_6_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 6" "0,1"
line.long 0x1C "CSI_TX_IF_VC7_CFG,CSI2 Transmitter Virtual Channel 7 Configuration Register"
hexmask.long.word 0x1C 16.--31. 1. "VC_7_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 7"
bitfld.long 0x1C 0. "VC_7_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 7" "0,1"
line.long 0x20 "CSI_TX_IF_VC8_CFG,CSI2 Transmitter Virtual Channel 8 Configuration Register"
hexmask.long.word 0x20 16.--31. 1. "VC_8_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 8"
bitfld.long 0x20 0. "VC_8_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 8" "0,1"
line.long 0x24 "CSI_TX_IF_VC9_CFG,CSI2 Transmitter Virtual Channel 9 Configuration Register"
hexmask.long.word 0x24 16.--31. 1. "VC_9_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 9"
bitfld.long 0x24 0. "VC_9_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 9" "0,1"
line.long 0x28 "CSI_TX_IF_VC10_CFG,CSI2 Transmitter Virtual Channel 10 Configuration Register"
hexmask.long.word 0x28 16.--31. 1. "VC_10_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 10"
bitfld.long 0x28 0. "VC_10_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 10" "0,1"
line.long 0x2C "CSI_TX_IF_VC11_CFG,CSI2 Transmitter Virtual Channel 11 Configuration Register"
hexmask.long.word 0x2C 16.--31. 1. "VC_11_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 11"
bitfld.long 0x2C 0. "VC_11_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 11" "0,1"
line.long 0x30 "CSI_TX_IF_VC12_CFG,CSI2 Transmitter Virtual Channel 12 Configuration Register"
hexmask.long.word 0x30 16.--31. 1. "VC_12_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 12"
bitfld.long 0x30 0. "VC_12_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 12" "0,1"
line.long 0x34 "CSI_TX_IF_VC13_CFG,CSI2 Transmitter Virtual Channel 13 Configuration Register"
hexmask.long.word 0x34 16.--31. 1. "VC_13_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 13"
bitfld.long 0x34 0. "VC_13_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 13" "0,1"
line.long 0x38 "CSI_TX_IF_VC14_CFG,CSI2 Transmitter Virtual Channel 14 Configuration Register"
hexmask.long.word 0x38 16.--31. 1. "VC_14_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 14"
bitfld.long 0x38 0. "VC_14_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 14" "0,1"
line.long 0x3C "CSI_TX_IF_VC15_CFG,CSI2 Transmitter Virtual Channel 15 Configuration Register"
hexmask.long.word 0x3C 16.--31. 1. "VC_15_MAX_FRAME_NUMBER,Max Frame Number - Maximum number of frames on Virtual Channel 15"
bitfld.long 0x3C 0. "VC_15_FRAME_COUNT_EN,Frame Count Enable - Writing 1 to this bit enables frame count on Virtual Channel 15" "0,1"
line.long 0x40 "CSI_TX_IF_DT0_CFG,CSI2 Transmitter Data Type 0 Configuration Register with pixel_dt_sel[:] = 0"
bitfld.long 0x40 9. "DT_0_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 0 with pixel_dt_sel[:] = 0" "0,1"
bitfld.long 0x40 8. "DT_0_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 0 with pixel_dt_sel[:] = 0" "0,1"
bitfld.long 0x40 2.--7. "DT_0_DATA_TYPE,Data Type - Type of data on Data Type 0 with pixel_dt_sel[:] = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x40 1. "DT_0_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 0" "0,1"
bitfld.long 0x40 0. "DT_0_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 0" "0,1"
line.long 0x44 "CSI_TX_IF_DT0_FORMAT,CSI2 Transmitter Data Type 0 Format Register"
hexmask.long.word 0x44 16.--31. 1. "DT_0_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 0 with pixel_dt_sel[:] = 0"
hexmask.long.word 0x44 0.--15. 1. "DT_0_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 0 with pixel_dt_sel[:] = 0"
line.long 0x48 "CSI_TX_IF_DT1_CFG,CSI2 Transmitter Data Type 1 Configuration Register with pixel_dt_sel[:] = 1"
bitfld.long 0x48 9. "DT_1_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 1 with pixel_dt_sel[:] = 1" "0,1"
bitfld.long 0x48 8. "DT_1_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 1 with pixel_dt_sel[:] = 1" "0,1"
bitfld.long 0x48 2.--7. "DT_1_DATA_TYPE,Data Type - Type of data on Data Type 1 with pixel_dt_sel[:] = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x48 1. "DT_1_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 1" "0,1"
bitfld.long 0x48 0. "DT_1_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 1" "0,1"
line.long 0x4C "CSI_TX_IF_DT1_FORMAT,CSI2 Transmitter Data Type 1 Format Register"
hexmask.long.word 0x4C 16.--31. 1. "DT_1_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 1 with pixel_dt_sel[:] = 1"
hexmask.long.word 0x4C 0.--15. 1. "DT_1_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 1 with pixel_dt_sel[:] = 1"
line.long 0x50 "CSI_TX_IF_DT2_CFG,CSI2 Transmitter Data Type 2 Configuration Register with pixel_dt_sel[:] = 2"
bitfld.long 0x50 9. "DT_2_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 2 with pixel_dt_sel[:] = 2" "0,1"
bitfld.long 0x50 8. "DT_2_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 2 with pixel_dt_sel[:] = 2" "0,1"
bitfld.long 0x50 2.--7. "DT_2_DATA_TYPE,Data Type - Type of data on Data Type 2 with pixel_dt_sel[:] = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x50 1. "DT_2_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 2" "0,1"
bitfld.long 0x50 0. "DT_2_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 2" "0,1"
line.long 0x54 "CSI_TX_IF_DT2_FORMAT,CSI2 Transmitter Data Type 2 Format Register"
hexmask.long.word 0x54 16.--31. 1. "DT_2_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 2 with pixel_dt_sel[:] = 2"
hexmask.long.word 0x54 0.--15. 1. "DT_2_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 2 with pixel_dt_sel[:] = 2"
line.long 0x58 "CSI_TX_IF_DT3_CFG,CSI2 Transmitter Data Type 3 Configuration Register with pixel_dt_sel[:] = 3"
bitfld.long 0x58 9. "DT_3_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 3 with pixel_dt_sel[:] = 3" "0,1"
bitfld.long 0x58 8. "DT_3_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 3 with pixel_dt_sel[:] = 3" "0,1"
bitfld.long 0x58 2.--7. "DT_3_DATA_TYPE,Data Type - Type of data on Data Type 3 with pixel_dt_sel[:] = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x58 1. "DT_3_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 3" "0,1"
bitfld.long 0x58 0. "DT_3_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 3" "0,1"
line.long 0x5C "CSI_TX_IF_DT3_FORMAT,CSI2 Transmitter Data Type 3 Format Register"
hexmask.long.word 0x5C 16.--31. 1. "DT_3_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 3 with pixel_dt_sel[:] = 3"
hexmask.long.word 0x5C 0.--15. 1. "DT_3_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 3 with pixel_dt_sel[:] = 3"
line.long 0x60 "CSI_TX_IF_DT4_CFG,CSI2 Transmitter Data Type 4 Configuration Register with pixel_dt_sel[:] = 4"
bitfld.long 0x60 9. "DT_4_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 4 with pixel_dt_sel[:] = 4" "0,1"
bitfld.long 0x60 8. "DT_4_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 4 with pixel_dt_sel[:] = 4" "0,1"
bitfld.long 0x60 2.--7. "DT_4_DATA_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x60 1. "DT_4_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 4" "0,1"
bitfld.long 0x60 0. "DT_4_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 4" "0,1"
line.long 0x64 "CSI_TX_IF_DT4_FORMAT,CSI2 Transmitter Data Type 4 Format Register"
hexmask.long.word 0x64 16.--31. 1. "DT_4_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 4 with pixel_dt_sel[:] = 4"
hexmask.long.word 0x64 0.--15. 1. "DT_4_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 4 with pixel_dt_sel[:] = 4"
line.long 0x68 "CSI_TX_IF_DT5_CFG,CSI2 Transmitter Data Type 5 Configuration Register with pixel_dt_sel[:] = 5"
bitfld.long 0x68 9. "DT_5_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 5 with pixel_dt_sel[:] = 5" "0,1"
bitfld.long 0x68 8. "DT_5_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 5 with pixel_dt_sel[:] = 5" "0,1"
bitfld.long 0x68 2.--7. "DT_5_DATA_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x68 1. "DT_5_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 5" "0,1"
bitfld.long 0x68 0. "DT_5_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 5" "0,1"
line.long 0x6C "CSI_TX_IF_DT5_FORMAT,CSI2 Transmitter Data Type 5 Format Register"
hexmask.long.word 0x6C 16.--31. 1. "DT_5_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 5 with pixel_dt_sel[:] = 5"
hexmask.long.word 0x6C 0.--15. 1. "DT_5_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 5 with pixel_dt_sel[:] = 5"
line.long 0x70 "CSI_TX_IF_DT6_CFG,CSI2 Transmitter Data Type 6 Configuration Register with pixel_dt_sel[:] = 6"
bitfld.long 0x70 9. "DT_6_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 6 with pixel_dt_sel[:] = 6" "0,1"
bitfld.long 0x70 8. "DT_6_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 6 with pixel_dt_sel[:] = 6" "0,1"
bitfld.long 0x70 2.--7. "DT_6_DATA_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x70 1. "DT_6_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 6" "0,1"
bitfld.long 0x70 0. "DT_6_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 6" "0,1"
line.long 0x74 "CSI_TX_IF_DT6_FORMAT,CSI2 Transmitter Data Type 6 Format Register"
hexmask.long.word 0x74 16.--31. 1. "DT_6_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 6 with pixel_dt_sel[:] = 6"
hexmask.long.word 0x74 0.--15. 1. "DT_6_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 6 with pixel_dt_sel[:] = 6"
line.long 0x78 "CSI_TX_IF_DT7_CFG,CSI2 Transmitter Data Type 7 Configuration Register with pixel_dt_sel[:] = 7"
bitfld.long 0x78 9. "DT_7_PACKED_ENABLE,Packed Enable - data stream is prepacked in to 32bit words on the pixel interface the data is sent with the defined Data Type 7 with pixel_dt_sel[:] = 7" "0,1"
bitfld.long 0x78 8. "DT_7_EXTD_DATA_TYPE,Extended Data Type - Type of data on Data Type 7 with pixel_dt_sel[:] = 7" "0,1"
bitfld.long 0x78 2.--7. "DT_7_DATA_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x78 1. "DT_7_LSLE_GENERATION_EN,Line Start And Line End Short Packet Generation Enable - Writing 1 to this bit enables Line Start and Line End generation on Data Type 7" "0,1"
bitfld.long 0x78 0. "DT_7_LINE_COUNT_EN,Line Count Enable - Writing 1 to this bit enables line count on Data Type 7" "0,1"
line.long 0x7C "CSI_TX_IF_DT7_FORMAT,CSI2 Transmitter Data Type 7 Format Register"
hexmask.long.word 0x7C 16.--31. 1. "DT_7_BYTES_LINE_NUMBER,Bytes Per Line - Bytes per line on Data Type 7 with pixel_dt_sel[:] = 7"
hexmask.long.word 0x7C 0.--15. 1. "DT_7_MAX_LINE_NUMBER,Max Line Number - Maximum number of lines on Data Type 7 with pixel_dt_sel[:] = 7"
group.long 0x100++0x37
line.long 0x00 "CSI_TX_IF_STREAM_IF_0_CFG,CSI2 Stream 0 Configuration Register"
hexmask.long.word 0x00 0.--15. 1. "STREAM_IF_0_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 0"
line.long 0x04 "CSI_TX_IF_STREAM_IF_1_CFG,CSI2 Stream 1 Configuration Register"
bitfld.long 0x04 23. "STREAM_IF_1_SLAVE_MODE,Stream Slave Mode suppresses frame start/end packets in stream 1" "0,1"
hexmask.long.word 0x04 0.--15. 1. "STREAM_IF_1_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 1"
line.long 0x08 "CSI_TX_IF_STREAM_IF_2_CFG,CSI2 Stream 2 Configuration Register"
bitfld.long 0x08 23. "STREAM_IF_2_SLAVE_MODE,Stream Slave Mode suppresses frame start/end packets in stream 2" "0,1"
hexmask.long.word 0x08 0.--15. 1. "STREAM_IF_2_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 2"
line.long 0x0C "CSI_TX_IF_STREAM_IF_3_CFG,CSI2 Stream 3 Configuration Register"
bitfld.long 0x0C 23. "STREAM_IF_3_SLAVE_MODE,Stream Slave Mode suppresses frame start/end packets in stream 3" "0,1"
hexmask.long.word 0x0C 0.--15. 1. "STREAM_IF_3_FILL_LEVEL,Fill Level - Minimum number of packed 32 words loaded into the stream fifo before Tx will start for Stream if 3"
line.long 0x10 "CSI_TX_IF_DEBUG_CFG,CSI2 Transmitter Debug Enable Register"
bitfld.long 0x10 0. "DBG_EN,Debug Enable" "0,1"
line.long 0x14 "CSI_TX_IF_DEBUG_LN_FSM,Debug Register for Lane FSM"
bitfld.long 0x14 9. "NEW_BURST_ALLOWED,Lane Mangement FSM" "0,1"
bitfld.long 0x14 8. "PACKET_VALID_R,Lane Mangement FSM" "0,1"
bitfld.long 0x14 7. "PACKET_VALID_IN,Lane Mangement FSM" "0,1"
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bitfld.long 0x14 6. "END_OF_BURST,Lane Mangement FSM" "0,1"
bitfld.long 0x14 5. "TRANS_ACTIVE,Lane Mangement FSM" "0,1"
bitfld.long 0x14 4. "START_HS_TRANS,Lane Mangement FSM" "0,1"
newline
bitfld.long 0x14 0.--2. "LANE_MGR_FSM_ST,Lane Mangement FSM" "0,1,2,3,4,5,6,7"
line.long 0x18 "CSI_TX_IF_DEBUG_CLK_LN_FSM,Debug Register for Clock Lane FSM"
bitfld.long 0x18 13. "ULPS_ACTIVE_CLK,Clock Lane FSM" "0,1"
bitfld.long 0x18 12. "ULPS_MODE_ACTIVE,Clock Lane FSM" "0,1"
bitfld.long 0x18 11. "ULPS_EXIT_CLK_PPI,Clock Lane FSM" "0,1"
newline
bitfld.long 0x18 10. "ULPS_REQUEST_CLK_PPI,Clock Lane FSM" "0,1"
bitfld.long 0x18 9. "HS_MODE_ACTIVE_CLK,Clock Lane FSM" "0,1"
bitfld.long 0x18 8. "REQUEST_HS_CLK_PPI,Clock Lane FSM" "0,1"
newline
bitfld.long 0x18 7. "READY_HS_CLK,Clock Lane FSM" "0,1"
bitfld.long 0x18 6. "ULPS_WAKEUP_COUNT_DONE_CL,Clock Lane FSM" "0,1"
bitfld.long 0x18 5. "ULPS_REQUEST_CLK,Clock Lane FSM" "0,1"
newline
bitfld.long 0x18 4. "HS_MODE_REQ,Clock Lane FSM" "0,1"
bitfld.long 0x18 2.--3. "ULPS_CLK_FSM,Clock Lane FSM" "0,1,2,3"
bitfld.long 0x18 0.--1. "HS_CLK_FSM,Clock Lane FSM" "0,1,2,3"
line.long 0x1C "CSI_TX_IF_DEBUG_DATA_LN_FSM,Debug Register for Data Lane FSM"
bitfld.long 0x1C 16. "ULPS_ACTIVE,Data Lane FSM" "0,1"
bitfld.long 0x1C 15. "DATA_ULPS_ACTIVE,Debug Register for Data Lane FSM" "0,1"
bitfld.long 0x1C 14. "TX_ULPS_EXIT_ESC,Data Lane FSM" "0,1"
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bitfld.long 0x1C 13. "TX_ULPS_ESC,Data Lane FSM" "0,1"
bitfld.long 0x1C 12. "TX_REQUEST_ESC,Data Lane FSM" "0,1"
bitfld.long 0x1C 10. "ULPS_WAKEUP_COUNT_DONE_DL,Data Lane FSM" "0,1"
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bitfld.long 0x1C 6.--9. "ULPS_ACTIVE_N,Data Lane FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 5. "HS_MODE_REQ_SYNC,Data Lane FSM" "0,1"
bitfld.long 0x1C 4. "ULPS_REQ_SYNC,Data Lane FSM" "0,1"
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bitfld.long 0x1C 0.--1. "ULPS_DATA_LANE_FSM,Data Lane FSM" "0,1,2,3"
line.long 0x20 "CSI_TX_IF_DEBUG_PROT0_FSM,Debug Register for Pixel IF0 Protocol FSM"
bitfld.long 0x20 15.--18. "VIRTUAL_CHANNEL_IF0,Pixel IF0 Protocol FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 12.--14. "DATA_TYPE_IF0,Pixel IF0 Protocol FSM" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 11. "FRAME_VALID_IF0,Pixel IF0 Protocol FSM" "0,1"
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bitfld.long 0x20 10. "LINE_VALID_IF0,Pixel IF0 Protocol FSM" "0,1"
bitfld.long 0x20 8. "LAST_PAYLOAD_DATA_IF0,Pixel IF0 Protocol FSM" "0,1"
bitfld.long 0x20 7. "PAYLOAD_FIFO_EMPTY_IF0,Pixel IF0 Protocol FSM" "0,1"
newline
hexmask.long.byte 0x20 0.--6. 1. "PROT_FSM_IF0,Pixel IF0 Protocol FSM"
line.long 0x24 "CSI_TX_IF_DEBUG_PROT1_FSM,Debug Register for Pixel IF1 Protocol FSM"
bitfld.long 0x24 15.--18. "VIRTUAL_CHANNEL_IF1,Pixel IF1 Protocol FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 12.--14. "DATA_TYPE_IF1,Pixel IF1 Protocol FSM" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 11. "FRAME_VALID_IF1,Pixel IF1 Protocol FSM" "0,1"
newline
bitfld.long 0x24 10. "LINE_VALID_IF1,Pixel IF1 Protocol FSM" "0,1"
bitfld.long 0x24 8. "LAST_PAYLOAD_DATA_IF1,Pixel IF1 Protocol FSM" "0,1"
bitfld.long 0x24 7. "PAYLOAD_FIFO_EMPTY_IF1,Pixel IF1 Protocol FSM" "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "PROT_FSM_IF1,Pixel IF1 Protocol FSM"
line.long 0x28 "CSI_TX_IF_DEBUG_PROT2_FSM,Debug Register for Pixel IF2 Protocol FSM"
bitfld.long 0x28 15.--18. "VIRTUAL_CHANNEL_IF2,Pixel IF2 Protocol FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 12.--14. "DATA_TYPE_IF2,Pixel IF2 Protocol FSM" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 11. "FRAME_VALID_IF2,Pixel IF2 Protocol FSM" "0,1"
newline
bitfld.long 0x28 10. "LINE_VALID_IF2,Pixel IF2 Protocol FSM" "0,1"
bitfld.long 0x28 8. "LAST_PAYLOAD_DATA_IF2,Pixel IF2 Protocol FSM" "0,1"
bitfld.long 0x28 7. "PAYLOAD_FIFO_EMPTY_IF2,Pixel IF2 Protocol FSM" "0,1"
newline
hexmask.long.byte 0x28 0.--6. 1. "PROT_FSM_IF2,Pixel IF2 Protocol FSM"
line.long 0x2C "CSI_TX_IF_DEBUG_PROT3_FSM,Debug Register for Pixel IF3 Protocol FSM"
bitfld.long 0x2C 15.--18. "VIRTUAL_CHANNEL_IF3,Pixel IF3 Protocol FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 12.--14. "DATA_TYPE_IF3,Pixel IF3 Protocol FSM" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 11. "FRAME_VALID_IF3,Pixel IF3 Protocol FSM" "0,1"
newline
bitfld.long 0x2C 10. "LINE_VALID_IF3,Pixel IF3 Protocol FSM" "0,1"
bitfld.long 0x2C 8. "LAST_PAYLOAD_DATA_IF3,Pixel IF3 Protocol FSM" "0,1"
bitfld.long 0x2C 7. "PAYLOAD_FIFO_EMPTY_IF3,Pixel IF3 Protocol FSM" "0,1"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PROT_FSM_IF3,Pixel IF3 Protocol FSM"
line.long 0x30 "CSI_TX_IF_DPHY_STATUS,DPHY Transmitter Status"
bitfld.long 0x30 12. "DPHY_ULPS_ACTIVE_N_CLK,DPHY Transmitter ULPS_ACTIVE_N Clock Lane Status" "0,1"
bitfld.long 0x30 8.--11. "DPHY_ULPS_ACTIVE_N_DL,DPHY Transmitter ULPS_ACTIVE_N Data Lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 4. "DPHY_STOPSTATE_CLK,DPHY Transmitter STOP_STATE Clock Lane Status" "0,1"
newline
bitfld.long 0x30 0.--3. "DPHY_STOPSTATE_DL,DPHY Transmitter STOP_STATE Data Lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "CSI_TX_IF_DPHY_CFG1,DPHY Transmitter Configuration"
bitfld.long 0x34 25.--27. "GEN_POWERDOWN,DPHY Transmitter Power Down Common Module" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 24. "C_POWERDOWN,DPHY Transmitter Power Down TX Clock" "0,1"
bitfld.long 0x34 20.--23. "D_POWERDOWN,DPHY Transmitter Power Down TX Data Lanes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x34 8. "SWAP_DP_DN_CTX,DPHY Transmitter Swap DP_DN on Clock Lane" "0,1"
bitfld.long 0x34 4.--7. "SWAP_DP_DN_TX0,DPHY Transmitter Swap DP_DN on TX Data Lanes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 0.--3. "FORCE_STOP_MODE_TX0,DPHY Transmitter FORCE_STOP_MODE TX Data Lanes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x13C++0x03
line.long 0x00 "CSI_TX_IF_GENERIC,CSI2 Transmitter Test Register"
hexmask.long.word 0x00 16.--31. 1. "TEST_GENERIC_STATUS,CSI2 Transmitter Test Generic Status signals"
hexmask.long.word 0x00 0.--15. 1. "TEST_GENERIC_CTRL,CSI2 Transmitter Test Generic Control signals"
group.long 0x200++0x13
line.long 0x00 "CSI_TX_IF_ASF_INT_STATUS,ASF Interrupt Status Register"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
newline
bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and" "0,1"
bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "CSI_TX_IF_ASF_INT_RAW_STATUS,ASF Interrupt Raw Status Register"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
newline
bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and" "0,1"
bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "CSI_TX_IF_ASF_INT_MASK,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt register are masked"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
newline
bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and" "0,1"
bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "CSI_TX_IF_ASF_INT_TEST,The ASF interrupt test register emulate hardware even"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
newline
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for configuration and" "0,1"
bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "CSI_TX_IF_ASF_FATAL_NONFATAL_SELECT,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and" "0,1"
bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x220++0x0B
line.long 0x00 "CSI_TX_IF_ASF_SRAM_CORR_FAULT_STATUS,Status register for SRAM correctable fault"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "CSI_TX_IF_ASF_SRAM_UNCORR_FAULT_STATUS,Status register for SRAM uncorrectable fault"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "CSI_TX_IF_ASF_SRAM_FAULT_STATS,Statistics register for SRAM faults"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x230++0x0B
line.long 0x00 "CSI_TX_IF_ASF_TRANS_TO_CTRL,Control register to configure the ASF transaction timeout monitors"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "CSI_TX_IF_ASF_TRANS_TO_FAULT_MASK,Control register to mask out ASF transaction timeout faults from triggering interrupts"
bitfld.long 0x04 4. "ASF_TRANS_TO_FAULT_4_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
bitfld.long 0x04 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
bitfld.long 0x04 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
newline
bitfld.long 0x04 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
line.long 0x08 "CSI_TX_IF_ASF_TRANS_TO_FAULT_STATUS,Status register for transaction timeouts fault"
bitfld.long 0x08 4. "ASF_TRANS_TO_FAULT_4_STATUS,Status bits for transaction timeouts faults" "0,1"
bitfld.long 0x08 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for transaction timeouts faults" "0,1"
bitfld.long 0x08 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for transaction timeouts faults" "0,1"
newline
bitfld.long 0x08 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for transaction timeouts faults" "0,1"
bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults" "0,1"
group.long 0x240++0x07
line.long 0x00 "CSI_TX_IF_ASF_PROTOCOL_FAULT_MASK,Control register to mask out ASF Protocol faults from triggering interrupts"
bitfld.long 0x00 16. "ASF_PROTOCOL_FAULT_16_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 15. "ASF_PROTOCOL_FAULT_15_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 14. "ASF_PROTOCOL_FAULT_14_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source" "0,1"
line.long 0x04 "CSI_TX_IF_ASF_PROTOCOL_FAULT_STATUS,Status register for protocol faults"
bitfld.long 0x04 16. "ASF_PROTOCOL_FAULT_16_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 15. "ASF_PROTOCOL_FAULT_15_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 14. "ASF_PROTOCOL_FAULT_14_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "CSI_TX_IF_ID_PROD_VER,CSI2 Transmitter Product ID and Version Register"
hexmask.long.word 0x00 16.--31. 1. "PRODUCT_ID,CSI2 Transmitter Product Identification Number"
hexmask.long.word 0x00 0.--15. 1. "VERSION_ID,CSI2 Transmitter Product Version Number"
tree.end
tree.end
tree "CTRL_MMR0"
tree "CTRL_MMR0"
base ad:0x100000
rgroup.long 0x00++0x03
line.long 0x00 "CTRLMMR_PID,Peripheral release details"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business unit" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "R_RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CTRLMMR_MMR_CFG1,Indicates the MMR configuration"
hexmask.long.byte 0x00 0.--7. 1. "PARTITIONS,Indicates present partitions"
group.long 0x30++0x07
line.long 0x00 "CTRLMMR_MAIN_DEVSTAT,Indicates SoC bootstrap selection"
hexmask.long.byte 0x00 0.--7. 1. "BOOTMODE,Specifies the device Primary and Backup boot media"
line.long 0x04 "CTRLMMR_MAIN_BOOTCFG,Indicates SoC bootstrap selection latched at power-on reset by PORz"
hexmask.long.byte 0x04 0.--7. 1. "BOOTMODE,Specifies the device Primary and Backup boot media"
rgroup.long 0x40++0x07
line.long 0x00 "CTRLMMR_MAIN_FEATURE_STAT0,Indicates enable status of MAIN domain IP features"
bitfld.long 0x00 24. "UFS_AES_DIS,AES disabled on UFS" "0,1"
newline
bitfld.long 0x00 20. "EDP0_CRYPTO_DIS,HDCP Cryptography disabled on eDP0" "0,1"
newline
bitfld.long 0x00 18. "CRYPTO_PKA_DIS,SA2_UL Crypto Module PKA disabled" "0,1"
newline
bitfld.long 0x00 17. "CRYPTO_ENCR_DIS,SA2_UL Crypto Module AES/3DES/DBRG disabled" "0,1"
newline
bitfld.long 0x00 16. "CRYPTO_SHA_DIS,SA2_UL Crypto Module SHA/MD5 disabled" "0,1"
newline
bitfld.long 0x00 9. "DMPAC_SDE_DIS,DMPAC Stereo Disparity Engine disabled" "0,1"
newline
bitfld.long 0x00 8. "DMPAC_DOF_DIS,DMPAC Dense Optical Flow disabled" "0,1"
line.long 0x04 "CTRLMMR_MAIN_FEATURE_STAT1,Indicates enable status of MAIN domain IP features"
bitfld.long 0x04 16. "MCAN_FD_EN,FD mode is supported on MAIN MCAN interfaces when set" "0,1"
newline
bitfld.long 0x04 15. "GPU_ASTC_EN,GPU Adaptive Scalable Texture Compression is supported when set" "0,1"
newline
bitfld.long 0x04 11. "DEC_VP8_EN,VP8 Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 10. "DEC_VP6_EN,VP6 Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 9. "DEC_RV_EN,RealVideo Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 8. "DEC_SOREN_EN,Sorenson Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 7. "DEC_AVS_EN,AVS Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 6. "DEC_MPEG4_EN,MPEG4 Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 5. "DEC_MPEG2_EN,MPEG2 Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 4. "DEC_MPEG1_EN,MPEG1 Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 3. "DEC_WMV9_EN,WMV9 Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 2. "DEC_VC1_EN,VC-1 (SMPTE 421M) Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 1. "DEC_HEVC_EN,HEVC (H.265) Video decode is enabled when set" "0,1"
newline
bitfld.long 0x04 0. "DEC_H264_EN,H.264 Video decode is enabled when set" "0,1"
group.long 0x180++0x03
line.long 0x00 "CTRLMMR_IPC_CLR0,Acknowledge interprocessor communication interrupt to C71x core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
newline
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
rgroup.long 0x210++0x03
line.long 0x00 "CTRLMMR_PCI_DEVICE_ID,PCIe device ID and vendor ID register"
hexmask.long.word 0x00 16.--31. 1. "DEVICE_ID,Product ID"
newline
hexmask.long.word 0x00 0.--15. 1. "VENDOR_ID,TI Vendor ID"
rgroup.long 0x220++0x03
line.long 0x00 "CTRLMMR_USB_DEVICE_ID,USB device and vendor ID register"
hexmask.long.word 0x00 16.--31. 1. "DEVICE_ID,Product ID"
newline
hexmask.long.word 0x00 0.--15. 1. "VENDOR_ID,TI Vendor ID"
group.long 0x1008++0x2B
line.long 0x00 "CTRLMMR_LOCK0_KICK0,Lower 32-bits of Partition0 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK0_KICK1,Upper 32-bits of Partition 0 write lock key"
line.long 0x08 "CTRLMMR_INTR_RAW_STAT,Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test)"
bitfld.long 0x08 2. "LOCK_ERR,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Address violation occurred (attempt to read or write an invalid register address)" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1"
line.long 0x0C "CTRLMMR_INTR_STAT_CLR,Shows the enabled interrupt status and allows the interrupt to be cleared"
bitfld.long 0x0C 2. "EN_LOCK_ERR,Enabled lock interrupt event status" "0,1"
newline
bitfld.long 0x0C 1. "EN_ADDR_ERR,Enabled address interrupt event status" "0,1"
newline
bitfld.long 0x0C 0. "EN_PROT_ERR,Enabled protection interrupt event status" "0,1"
line.long 0x10 "CTRLMMR_INTR_EN_SET,Allows interrupt enables to be set"
bitfld.long 0x10 2. "LOCK_ERR_EN_SET,Lock interrupt enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_SET,Address interrupt enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_SET,Protection interrupt enable" "0,1"
line.long 0x14 "CTRLMMR_INTR_EN_CLR,Allows interrupt enables to be cleared"
bitfld.long 0x14 2. "LOCK_ERR_EN_CLR,Lock interrupt disable" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Address interrupt disable" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection interrupt disable" "0,1"
line.long 0x18 "CTRLMMR_EOI,EOI Vector value"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,"
line.long 0x1C "CTRLMMR_FAULT_ADDR,Indicates the address of the first transfer that caused a fault to occur"
line.long 0x20 "CTRLMMR_FAULT_TYPE,Indicates the access type of the first transfer that caused a fault to occur"
bitfld.long 0x20 0.--5. "TYPE,Type of access which faulted" "No fault,User execute access,User write access,?,User read access,?,?,?,Supervisor execute access,?,?,?,?,?,?,?,Supervisor write access,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read access,?..."
line.long 0x24 "CTRLMMR_FAULT_ATTR,Indicates the attributes of the first transfer that caused a fault to occur"
hexmask.long.word 0x24 20.--31. 1. "XID,Transaction ID"
newline
hexmask.long.word 0x24 8.--19. 1. "ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "PRIVID,Privilege ID"
line.long 0x28 "CTRLMMR_FAULT_CLR,Allows software to clear the current fault Clearing the current fault allows the . . and registers to latch the attributes of the next fault that occurs"
bitfld.long 0x28 0. "CLEAR,Fault clear" "0,1"
group.long 0x4000++0x03
line.long 0x00 "CTRLMMR_USB0_CTRL,Controls USB0 operation"
bitfld.long 0x00 27. "SERDES_SEL,Serdes Selection" "0,1"
group.long 0x4010++0x03
line.long 0x00 "CTRLMMR_USB1_CTRL,Controls USB1 operation"
bitfld.long 0x00 27. "SERDES_SEL,Serdes Selection" "0,1"
group.long 0x4044++0x1F
line.long 0x00 "CTRLMMR_ENET1_CTRL,Controls Ethernet Port1 operation"
bitfld.long 0x00 4. "RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x00 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port1 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x04 "CTRLMMR_ENET2_CTRL,Controls Ethernet Port2 operation"
bitfld.long 0x04 4. "RGMII_ID_MODE,Port2 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x04 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port2 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x08 "CTRLMMR_ENET3_CTRL,Controls Ethernet Port3 operation"
bitfld.long 0x08 4. "RGMII_ID_MODE,Port3 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x08 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port3 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x0C "CTRLMMR_ENET4_CTRL,Controls Ethernet Port4 operation"
bitfld.long 0x0C 4. "RGMII_ID_MODE,Port4 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x0C 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port4 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x10 "CTRLMMR_ENET5_CTRL,Controls Ethernet Port5 operation"
bitfld.long 0x10 4. "RGMII_ID_MODE,Port5 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x10 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port5 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x14 "CTRLMMR_ENET6_CTRL,Controls Ethernet Port6 operation"
bitfld.long 0x14 4. "RGMII_ID_MODE,Port6 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x14 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port6 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x18 "CTRLMMR_ENET7_CTRL,Controls Ethernet Port7 operation"
bitfld.long 0x18 4. "RGMII_ID_MODE,Port7 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x18 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port7 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
line.long 0x1C "CTRLMMR_ENET8_CTRL,Controls Ethernet Port8 operation"
bitfld.long 0x1C 4. "RGMII_ID_MODE,Port8 RGMII internal transmit delay selection" "0,1"
newline
bitfld.long 0x1C 0.--2. "PORT_MODE_SEL,Selects Ethernet switch Port8 interface" "GMII/MII (not supported),RMII,RGMII,SGMII,QSGMII,XFI (not supported),QSGMII_SUB,Reserved"
group.long 0x4070++0x17
line.long 0x00 "CTRLMMR_PCIE0_CTRL,Controls PCIe0 operation"
bitfld.long 0x00 8. "LANE_COUNT,Configures the PCIe lane count" "0,1"
newline
bitfld.long 0x00 7. "MODE_SEL,Selects the operating mode" "0,1"
newline
bitfld.long 0x00 0.--1. "GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list" "Reserved,Gen2 - Controller advertises Gen1 & Gen2..,Gen3 - Controller advertises Gen1 Gen2 &..,Gen4 - Controller advertises Gen1 Gen2 Gen3.."
line.long 0x04 "CTRLMMR_PCIE1_CTRL,Controls PCIe1 operation"
bitfld.long 0x04 8. "LANE_COUNT,Configures the PCIe lane count" "0,1"
newline
bitfld.long 0x04 7. "MODE_SEL,Selects the operating mode" "0,1"
newline
bitfld.long 0x04 0.--1. "GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list" "Reserved,Gen2 - Controller advertises Gen1 & Gen2..,Gen3 - Controller advertises Gen1 Gen2 &..,Gen4 - Controller advertises Gen1 Gen2 Gen3.."
line.long 0x08 "CTRLMMR_PCIE2_CTRL,Controls PCIe2 operation"
bitfld.long 0x08 8. "LANE_COUNT,Configures the PCIe lane count" "0,1"
newline
bitfld.long 0x08 7. "MODE_SEL,Selects the operating mode" "0,1"
newline
bitfld.long 0x08 0.--1. "GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list" "Reserved,Gen2 - Controller advertises Gen1 & Gen2..,Gen3 - Controller advertises Gen1 Gen2 &..,Gen4 - Controller advertises Gen1 Gen2 Gen3.."
line.long 0x0C "CTRLMMR_PCIE3_CTRL,Controls PCIe3 operation"
bitfld.long 0x0C 8. "LANE_COUNT,Configures the PCIe lane count" "0,1"
newline
bitfld.long 0x0C 7. "MODE_SEL,Selects the operating mode" "0,1"
newline
bitfld.long 0x0C 0.--1. "GENERATION_SEL,Configures the PCIe generation support in the PCIe capabilities linked-list" "Reserved,Gen2 - Controller advertises Gen1 & Gen2..,Gen3 - Controller advertises Gen1 Gen2 &..,Gen4 - Controller advertises Gen1 Gen2 Gen3.."
line.long 0x10 "CTRLMMR_SERDES0_LN0_CTRL,Controls 2-L SERDES0 lane0 selection"
bitfld.long 0x10 0.--1. "LANE_FUNC_SEL,Selects the SERDES0 lane0 function" "Enet Switch Q/SGMII Lane 1,PCIe0 Lane0,For USB0 lane swap,Not used"
line.long 0x14 "CTRLMMR_SERDES0_LN1_CTRL,Controls 2-L SERDES0 lane1 selection"
bitfld.long 0x14 0.--1. "LANE_FUNC_SEL,Selects the SERDES0 lane1 function" "IP1 - Enet Switch Q/SGMII Lane 2,IP2 - PCIe0 Lane1,IP3 - USB0,IP4 - Not Used"
group.long 0x4090++0x07
line.long 0x00 "CTRLMMR_SERDES1_LN0_CTRL,Controls 2-L SERDES1 lane0 selection"
bitfld.long 0x00 0.--1. "LANE_FUNC_SEL,Selects the SERDES1 lane0 function" "Enet Switch Q/SGMII Lane 3,PCIe1 Lane 0,For USB1 lane swap,ICSS_G1 SGMII Lane 0"
line.long 0x04 "CTRLMMR_SERDES1_LN1_CTRL,Controls 2-L SERDES1 lane1 selection"
bitfld.long 0x04 0.--1. "LANE_FUNC_SEL,Selects the SERDES1 lane1 function" "Enet Switch Q/SGMII Lane 4,PCIe1 Lane 1,USB1,ICSS_G1 SGMII Lane 1"
group.long 0x40A0++0x07
line.long 0x00 "CTRLMMR_SERDES2_LN0_CTRL,Controls 2-L SERDES2 lane0 selection"
bitfld.long 0x00 0.--1. "LANE_FUNC_SEL,Selects the SERDES2 lane0 function" "Not Used,PCIE2 Lane 0,For USB1 lane swap,ICSS_G1 SGMII Lane 0"
line.long 0x04 "CTRLMMR_SERDES2_LN1_CTRL,Controls 2-L SERDES2 lane1 selection"
bitfld.long 0x04 0.--1. "LANE_FUNC_SEL,Selects the SERDES2 lane1 function" "Not Used,PCIE2 Lane 1,USB1,ICSS_G1 SGMII Lane 1"
group.long 0x40B0++0x07
line.long 0x00 "CTRLMMR_SERDES3_LN0_CTRL,Controls 2-L SERDES3 lane0 selection"
bitfld.long 0x00 0.--1. "LANE_FUNC_SEL,Selects the SERDES3 lane0 function" "Not Used,PCIE3 Lane 0,For USB0 lane swap,Not Used"
line.long 0x04 "CTRLMMR_SERDES3_LN1_CTRL,Controls 2-L SERDES3 lane1 selection"
bitfld.long 0x04 0.--1. "LANE_FUNC_SEL,Selects the SERDES3 lane1 function" "Not Used,PCIE3 Lane 1,USB0,Not Used"
group.long 0x40C0++0x0F
line.long 0x00 "CTRLMMR_SERDES4_LN0_CTRL,Controls 4-L SERDES4 lane0 selection"
bitfld.long 0x00 0.--1. "LANE_FUNC_SEL,Selects the SERDES4 lane0 function" "eDP Lane 0,Not Used,Enet Switch Q/SGMII Lane 5,Not Used"
line.long 0x04 "CTRLMMR_SERDES4_LN1_CTRL,Controls 4-L SERDES4 lane1 selection"
bitfld.long 0x04 0.--1. "LANE_FUNC_SEL,Selects the SERDES4 lane1 function" "eDP Lane 1,Not Used,Enet Switch Q/SGMII Lane 6,Not Used"
line.long 0x08 "CTRLMMR_SERDES4_LN2_CTRL,Controls 4-L SERDES4 lane2 selection"
bitfld.long 0x08 0.--1. "LANE_FUNC_SEL,Selects the SERDES4 lane2 function" "eDP Lane 2,Not Used,Enet Switch Q/SGMII Lane 7,Not Used"
line.long 0x0C "CTRLMMR_SERDES4_LN3_CTRL,Controls 4-L SERDES4 lane3 selection"
bitfld.long 0x0C 0.--1. "LANE_FUNC_SEL,Selects the SERDES4 lane3 function" "eDP Lane 3,Not Used,Enet Switch Q/SGMII Lane 8,Not Used"
group.long 0x40E0++0x13
line.long 0x00 "CTRLMMR_SERDES0_CTRL,Controls SERDES0 operation"
bitfld.long 0x00 8. "RET_EN,Retention enable" "0,1"
line.long 0x04 "CTRLMMR_SERDES1_CTRL,Controls SERDES1 operation"
bitfld.long 0x04 8. "RET_EN,Retention enable" "0,1"
line.long 0x08 "CTRLMMR_SERDES2_CTRL,Controls SERDES2 operation"
bitfld.long 0x08 8. "RET_EN,Retention enable" "0,1"
line.long 0x0C "CTRLMMR_SERDES3_CTRL,Controls SERDES3 operation"
bitfld.long 0x0C 8. "RET_EN,Retention enable" "0,1"
line.long 0x10 "CTRLMMR_SERDES4_CTRL,Controls SERDES4 operation"
bitfld.long 0x10 12. "REF_SEL,REFCLK output select" "0,1"
newline
bitfld.long 0x10 8. "RET_EN,Retention enable" "0,1"
group.long 0x4100++0x07
line.long 0x00 "CTRLMMR_ICSSG0_CTRL0,Controls ICSS_G0 operation"
bitfld.long 0x00 24. "RGMII0_ID_MODE,Controls the ICSS_G0 RGMII0 port internal transmit delay" "0,1"
newline
hexmask.long.tbyte 0x00 0.--19. 1. "GPM_BIDI,Controls operation of the ICSS_G0 PRU0_GPO pins"
line.long 0x04 "CTRLMMR_ICSSG0_CTRL1,Controls ICSS_G0 operation"
bitfld.long 0x04 24. "RGMII1_ID_MODE,Controls the ICSS_G0 RGMII1 port internal transmit delay" "0,1"
newline
hexmask.long.tbyte 0x04 0.--19. 1. "GPM_BIDI,Controls operation of the ICSS_G0 PRU1_GPO pins"
group.long 0x4110++0x07
line.long 0x00 "CTRLMMR_ICSSG1_CTRL0,Controls ICSS_G1 operation"
bitfld.long 0x00 28. "SGMII_SERDES_SEL,SGMII0 Serdes Selection" "0,1"
newline
bitfld.long 0x00 24. "RGMII0_ID_MODE,Controls the ICSS_G1 RGMII0 port internal transmit delay" "0,1"
newline
hexmask.long.tbyte 0x00 0.--19. 1. "GPM_BIDI,Controls operation of the ICSS_G1 PRU0_GPO pins"
line.long 0x04 "CTRLMMR_ICSSG1_CTRL1,Controls ICSS_G1 operation"
bitfld.long 0x04 28. "SGMII_SERDES_SEL,SGMII1 Serdes Selection" "0,1"
newline
bitfld.long 0x04 24. "RGMII1_ID_MODE,Controls the ICSS_G1 RGMII1 port internal transmit delay" "0,1"
newline
hexmask.long.tbyte 0x04 0.--19. 1. "GPM_BIDI,Controls operation of the ICSS_G1 PRU1_GPO pins"
group.long 0x4140++0x17
line.long 0x00 "CTRLMMR_EPWM0_CTRL,Controls eHRPWM0 Operation"
bitfld.long 0x00 8.--10. "SYNCIN_SEL,Selects the source of the PWM0 synchronization input" "PWM0_SYNCIN Pin,None,None,None,ICSSG0 Host..,ICSSG1 Host..,None,None"
newline
bitfld.long 0x00 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
newline
bitfld.long 0x00 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1"
line.long 0x04 "CTRLMMR_EPWM1_CTRL,Controls eHRPWM1 Operation"
bitfld.long 0x04 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
newline
bitfld.long 0x04 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1"
line.long 0x08 "CTRLMMR_EPWM2_CTRL,Controls eHRPWM2 Operation"
bitfld.long 0x08 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
newline
bitfld.long 0x08 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1"
line.long 0x0C "CTRLMMR_EPWM3_CTRL,Controls eHRPWM3 Operation"
bitfld.long 0x0C 8.--10. "SYNCIN_SEL,Selects the source of the PWM3 synchronization input" "PWM3_SYNCIN Pin,PWM2 syncout signal daisy chained,None,None,ICSSG0 Host Interrupt 7,ICSSG1 Host Interrupt 7,None,None"
newline
bitfld.long 0x0C 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
newline
bitfld.long 0x0C 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1"
line.long 0x10 "CTRLMMR_EPWM4_CTRL,Controls eHRPWM4 Operation"
bitfld.long 0x10 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
newline
bitfld.long 0x10 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1"
line.long 0x14 "CTRLMMR_EPWM5_CTRL,Controls eHRPWM5 Operation"
bitfld.long 0x14 4. "EALLOW,Enable write access to ePWM tripzone and HRPWM config registers" "0,1"
newline
bitfld.long 0x14 0. "TB_CLKEN,Enable eHRPWM timebase clock" "0,1"
group.long 0x4160++0x07
line.long 0x00 "CTRLMMR_SOCA_SEL,Selects Start of Conversion A output signal source"
bitfld.long 0x00 0.--1. "SOCA_SEL,Selects the SOC A output source" "OR of all eHRPWM SOCA outputs,ICSSG0 Host Interrupt 1,ICSSG1 Host Interrupt 1,None"
line.long 0x04 "CTRLMMR_SOCB_SEL,Selects Start of Conversion B output signal source"
bitfld.long 0x04 0.--1. "SOCB_SEL,Selects the SOC B output source" "OR of all eHRPWM SOCB ouputs,ICSSG0 Host Interrupt 2,ICSSG1 Host Interrupt 2,None"
rgroup.long 0x41A0++0x03
line.long 0x00 "CTRLMMR_EQEP_STAT,Displays status of EQEP modules"
bitfld.long 0x00 2. "PHASE_ERR2,eQEP2 Phase error status" "0,1"
newline
bitfld.long 0x00 1. "PHASE_ERR1,eQEP1 Phase error status" "0,1"
newline
bitfld.long 0x00 0. "PHASE_ERR0,eQEP0 Phase error status" "0,1"
group.long 0x41B4++0x07
line.long 0x00 "CTRLMMR_SDIO1_CTRL,Controls drive strength of MMC1 SDIO mode pins"
bitfld.long 0x00 0.--4. "DRV_STR,Selects the SDIO drive strength" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CTRLMMR_SDIO2_CTRL,Controls drive strength of MMC2 SDIO mode pins"
bitfld.long 0x04 0.--4. "DRV_STR,Selects the SDIO drive strength" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x41C0++0x0B
line.long 0x00 "CTRLMMR_MLB_SIG_IO_CTRL,Controls the characteristics of the MLB SIG IO"
bitfld.long 0x00 24.--25. "AUXTRIM,LVDS aux drive output current ratio trim for VOD offset compenstaion" "-8% 1h -..,?,+9%,+20%"
newline
bitfld.long 0x00 16.--17. "TXTRIM,LVDS drive output current ratio trim" "-8% 1h -..,?,+9%,+20%"
newline
bitfld.long 0x00 8.--11. "TXDRV,LVDS drive current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "INT_RTERM_EN,Internal termination resistor control" "0,1"
newline
bitfld.long 0x00 0.--2. "RTERM,Selects the internal termination resistor trim value" "0,1,2,3,4,5,6,7"
line.long 0x04 "CTRLMMR_MLB_DAT_IO_CTRL,Controls the characteristics of the MLB DATA IO"
bitfld.long 0x04 24.--25. "AUXTRIM,LVDS aux drive output current ratio trim for VOD offset compenstaion" "-8% 1h -..,?,+9%,+20%"
newline
bitfld.long 0x04 16.--17. "TXTRIM,LVDS drive output current ratio trim" "-8% 1h -..,?,+9%,+20%"
newline
bitfld.long 0x04 8.--11. "TXDRV,LVDS drive current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "INT_RTERM_EN,Internal termination resistor control" "0,1"
newline
bitfld.long 0x04 0.--2. "RTERM,Selects the internal termination resistor trim value" "0,1,2,3,4,5,6,7"
line.long 0x08 "CTRLMMR_MLB_CLK_IO_CTRL,Controls the characteristics of the MLB CLK IO"
bitfld.long 0x08 16.--17. "TXTRIM,LVDS drive output current ratio trim" "-8% 1h -..,?,+9%,+20%"
newline
bitfld.long 0x08 8.--11. "TXDRV,LVDS drive current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "INT_RTERM_EN,Internal termination resistor control" "0,1"
newline
bitfld.long 0x08 0.--2. "RTERM,Selects the internal termination resistor trim value" "0,1,2,3,4,5,6,7"
group.long 0x41D0++0x03
line.long 0x00 "CTRLMMR_MLB_GPIO_CTRL,Controls the MLB GPIO operation"
bitfld.long 0x00 0. "MLB_MODE_EN,Controls operation of MLB IOs" "0,1"
group.long 0x4200++0x4F
line.long 0x00 "CTRLMMR_TIMER0_CTRL,Controls TIMER0 operation"
bitfld.long 0x00 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x04 "CTRLMMR_TIMER1_CTRL,Controls TIMER1 operation"
bitfld.long 0x04 8. "CASCADE_EN,Enables cascading of TIMER1 to TIMER0" "0,1"
newline
bitfld.long 0x04 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x08 "CTRLMMR_TIMER2_CTRL,Controls TIMER2 operation"
bitfld.long 0x08 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x0C "CTRLMMR_TIMER3_CTRL,Controls TIMER3 operation"
bitfld.long 0x0C 8. "CASCADE_EN,Enables cascading of TIMER3 to TIMER2" "0,1"
newline
bitfld.long 0x0C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x10 "CTRLMMR_TIMER4_CTRL,Controls TIMER4 operation"
bitfld.long 0x10 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x14 "CTRLMMR_TIMER5_CTRL,Controls TIMER5 operation"
bitfld.long 0x14 8. "CASCADE_EN,Enables cascading of TIMER5 to TIMER4" "0,1"
newline
bitfld.long 0x14 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x18 "CTRLMMR_TIMER6_CTRL,Controls TIMER6 operation"
bitfld.long 0x18 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x1C "CTRLMMR_TIMER7_CTRL,Controls TIMER7 operation"
bitfld.long 0x1C 8. "CASCADE_EN,Enables cascading of TIMER7 to TIMER6" "0,1"
newline
bitfld.long 0x1C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x20 "CTRLMMR_TIMER8_CTRL,Controls TIMER8 operation"
bitfld.long 0x20 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x24 "CTRLMMR_TIMER9_CTRL,Controls TIMER9 operation"
bitfld.long 0x24 8. "CASCADE_EN,Enables cascading of TIMER9 to TIMER8" "0,1"
newline
bitfld.long 0x24 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x28 "CTRLMMR_TIMER10_CTRL,Controls TIMER10 operation"
bitfld.long 0x28 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x2C "CTRLMMR_TIMER11_CTRL,Controls TIMER11 operation"
bitfld.long 0x2C 8. "CASCADE_EN,Enables cascading of TIMER11 to TIMER10" "0,1"
newline
bitfld.long 0x2C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x30 "CTRLMMR_TIMER12_CTRL,Controls TIMER12 operation"
bitfld.long 0x30 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x34 "CTRLMMR_TIMER13_CTRL,Controls TIMER13 operation"
bitfld.long 0x34 8. "CASCADE_EN,Enables cascading of TIMER13 to TIMER12" "0,1"
newline
bitfld.long 0x34 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x38 "CTRLMMR_TIMER14_CTRL,Controls TIMER14 operation"
bitfld.long 0x38 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x3C "CTRLMMR_TIMER15_CTRL,Controls TIMER15 operation"
bitfld.long 0x3C 8. "CASCADE_EN,Enables cascading of TIMER15 to TIMER14" "0,1"
newline
bitfld.long 0x3C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x40 "CTRLMMR_TIMER16_CTRL,Controls TIMER16 operation"
bitfld.long 0x40 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x44 "CTRLMMR_TIMER17_CTRL,Controls TIMER17 operation"
bitfld.long 0x44 8. "CASCADE_EN,Enables cascading of TIMER17 to TIMER16" "0,1"
newline
bitfld.long 0x44 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x48 "CTRLMMR_TIMER18_CTRL,Controls TIMER18 operation"
bitfld.long 0x48 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
line.long 0x4C "CTRLMMR_TIMER19_CTRL,Controls TIMER19 operation"
bitfld.long 0x4C 8. "CASCADE_EN,Enables cascading of TIMER19 to TIMER18" "0,1"
newline
bitfld.long 0x4C 0.--2. "CAP_SEL,Selects the TIMERIO input pin for capture input signal" "Use TIMERIO0 pin,Use TIMERIO1 pin,Use TIMERIO2 pin,Use TIMERIO3 pin,Use TIMERIO4 pin,Use TIMERIO5 pin,Use TIMERIO6 pin,Use TIMERIO7 pin"
group.long 0x4280++0x1F
line.long 0x00 "CTRLMMR_TIMERIO0_CTRL,Controls TIMER_IO0 muxing"
bitfld.long 0x00 0.--4. "OUT_SEL,Selects the source of the TIMER_IO0 output" "TIMERIO0 is driven by TIMER0 output,TIMERIO0 is driven by TIMER1 output,TIMERIO0 is driven by TIMER2 output,TIMERIO0 is driven by TIMER3 output,TIMERIO0 is driven by TIMER4 output,TIMERIO0 is driven by TIMER5 output,TIMERIO0 is driven by TIMER6 output,TIMERIO0 is driven by TIMER7 output,TIMERIO0 is driven by TIMER8 output,TIMERIO0 is driven by TIMER9 output,TIMERIO0 is driven by TIMER10 output,TIMERIO0 is driven by TIMER11 output,TIMERIO0 is driven by TIMER12 output,TIMERIO0 is driven by TIMER13 output,TIMERIO0 is driven by TIMER14 output,TIMERIO0 is driven by TIMER15 output,TIMERIO0 is driven by TIMER16 output,TIMERIO0 is driven by TIMER17 output,TIMERIO0 is driven by TIMER18 output,TIMERIO0 is driven by TIMER19 output,?..."
line.long 0x04 "CTRLMMR_TIMERIO1_CTRL,Controls TIMER_IO1 muxing"
bitfld.long 0x04 0.--4. "OUT_SEL,Selects the source of the TIMER_IO1 output" "TIMERIO1 is driven by TIMER0 output,TIMERIO1 is driven by TIMER1 output,TIMERIO1 is driven by TIMER2 output,TIMERIO1 is driven by TIMER3 output,TIMERIO1 is driven by TIMER4 output,TIMERIO1 is driven by TIMER5 output,TIMERIO1 is driven by TIMER6 output,TIMERIO1 is driven by TIMER7 output,TIMERIO1 is driven by TIMER8 output,TIMERIO1 is driven by TIMER9 output,TIMERIO1 is driven by TIMER10 output,TIMERIO1 is driven by TIMER11 output,TIMERIO1 is driven by TIMER12 output,TIMERIO1 is driven by TIMER13 output,TIMERIO1 is driven by TIMER14 output,TIMERIO1 is driven by TIMER15 output,TIMERIO1 is driven by TIMER16 output,TIMERIO1 is driven by TIMER17 output,TIMERIO1 is driven by TIMER18 output,TIMERIO1 is driven by TIMER19 output,?..."
line.long 0x08 "CTRLMMR_TIMERIO2_CTRL,Controls TIMER_IO2 muxing"
bitfld.long 0x08 0.--4. "OUT_SEL,Selects the source of the TIMER_IO2 output" "TIMERIO2 is driven by TIMER0 output,TIMERIO2 is driven by TIMER1 output,TIMERIO2 is driven by TIMER2 output,TIMERIO2 is driven by TIMER3 output,TIMERIO2 is driven by TIMER4 output,TIMERIO2 is driven by TIMER5 output,TIMERIO2 is driven by TIMER6 output,TIMERIO2 is driven by TIMER7 output,TIMERIO2 is driven by TIMER8 output,TIMERIO2 is driven by TIMER9 output,TIMERIO2 is driven by TIMER10 output,TIMERIO2 is driven by TIMER11 output,TIMERIO2 is driven by TIMER12 output,TIMERIO2 is driven by TIMER13 output,TIMERIO2 is driven by TIMER14 output,TIMERIO2 is driven by TIMER15 output,TIMERIO2 is driven by TIMER16 output,TIMERIO2 is driven by TIMER17 output,TIMERIO2 is driven by TIMER18 output,TIMERIO2 is driven by TIMER19 output,?..."
line.long 0x0C "CTRLMMR_TIMERIO3_CTRL,Controls TIMER_IO3 muxing"
bitfld.long 0x0C 0.--4. "OUT_SEL,Selects the source of the TIMER_IO3 output" "TIMERIO3 is driven by TIMER0 output,TIMERIO3 is driven by TIMER1 output,TIMERIO3 is driven by TIMER2 output,TIMERIO3 is driven by TIMER3 output,TIMERIO3 is driven by TIMER4 output,TIMERIO3 is driven by TIMER5 output,TIMERIO3 is driven by TIMER6 output,TIMERIO3 is driven by TIMER7 output,TIMERIO3 is driven by TIMER8 output,TIMERIO3 is driven by TIMER9 output,TIMERIO3 is driven by TIMER10 output,TIMERIO3 is driven by TIMER11 output,TIMERIO3 is driven by TIMER12 output,TIMERIO3 is driven by TIMER13 output,TIMERIO3 is driven by TIMER14 output,TIMERIO3 is driven by TIMER15 output,TIMERIO3 is driven by TIMER16 output,TIMERIO3 is driven by TIMER17 output,TIMERIO3 is driven by TIMER18 output,TIMERIO3 is driven by TIMER19 output,?..."
line.long 0x10 "CTRLMMR_TIMERIO4_CTRL,Controls TIMER_IO4 muxing"
bitfld.long 0x10 0.--4. "OUT_SEL,Selects the source of the TIMER_IO4 output" "TIMERIO4 is driven by TIMER0 output,TIMERIO4 is driven by TIMER1 output,TIMERIO4 is driven by TIMER2 output,TIMERIO4 is driven by TIMER3 output,TIMERIO4 is driven by TIMER4 output,TIMERIO4 is driven by TIMER5 output,TIMERIO4 is driven by TIMER6 output,TIMERIO4 is driven by TIMER7 output,TIMERIO4 is driven by TIMER8 output,TIMERIO4 is driven by TIMER9 output,TIMERIO4 is driven by TIMER10 output,TIMERIO4 is driven by TIMER11 output,TIMERIO4 is driven by TIMER12 output,TIMERIO4 is driven by TIMER13 output,TIMERIO4 is driven by TIMER14 output,TIMERIO4 is driven by TIMER15 output,TIMERIO4 is driven by TIMER16 output,TIMERIO4 is driven by TIMER17 output,TIMERIO4 is driven by TIMER18 output,TIMERIO4 is driven by TIMER19 output,?..."
line.long 0x14 "CTRLMMR_TIMERIO5_CTRL,Controls TIMER_IO5 muxing"
bitfld.long 0x14 0.--4. "OUT_SEL,Selects the source of the TIMER_IO5 output" "TIMERIO5 is driven by TIMER0 output,TIMERIO5 is driven by TIMER1 output,TIMERIO5 is driven by TIMER2 output,TIMERIO5 is driven by TIMER3 output,TIMERIO5 is driven by TIMER4 output,TIMERIO5 is driven by TIMER5 output,TIMERIO5 is driven by TIMER6 output,TIMERIO5 is driven by TIMER7 output,TIMERIO5 is driven by TIMER8 output,TIMERIO5 is driven by TIMER9 output,TIMERIO5 is driven by TIMER10 output,TIMERIO5 is driven by TIMER11 output,TIMERIO5 is driven by TIMER12 output,TIMERIO5 is driven by TIMER13 output,TIMERIO5 is driven by TIMER14 output,TIMERIO5 is driven by TIMER15 output,TIMERIO5 is driven by TIMER16 output,TIMERIO5 is driven by TIMER17 output,TIMERIO5 is driven by TIMER18 output,TIMERIO5 is driven by TIMER19 output,?..."
line.long 0x18 "CTRLMMR_TIMERIO6_CTRL,Controls TIMER_IO6 muxing"
bitfld.long 0x18 0.--4. "OUT_SEL,Selects the source of the TIMER_IO6 output" "TIMERIO6 is driven by TIMER0 output,TIMERIO6 is driven by TIMER1 output,TIMERIO6 is driven by TIMER2 output,TIMERIO6 is driven by TIMER3 output,TIMERIO6 is driven by TIMER4 output,TIMERIO6 is driven by TIMER5 output,TIMERIO6 is driven by TIMER6 output,TIMERIO6 is driven by TIMER7 output,TIMERIO6 is driven by TIMER8 output,TIMERIO6 is driven by TIMER9 output,TIMERIO6 is driven by TIMER10 output,TIMERIO6 is driven by TIMER11 output,TIMERIO6 is driven by TIMER12 output,TIMERIO6 is driven by TIMER13 output,TIMERIO6 is driven by TIMER14 output,TIMERIO6 is driven by TIMER15 output,TIMERIO6 is driven by TIMER16 output,TIMERIO6 is driven by TIMER17 output,TIMERIO6 is driven by TIMER18 output,TIMERIO6 is driven by TIMER19 output,?..."
line.long 0x1C "CTRLMMR_TIMERIO7_CTRL,Controls TIMER_IO7 muxing"
bitfld.long 0x1C 0.--4. "OUT_SEL,Selects the source of the TIMER_IO7 output" "TIMERIO7 is driven by TIMER0 output,TIMERIO7 is driven by TIMER1 output,TIMERIO7 is driven by TIMER2 output,TIMERIO7 is driven by TIMER3 output,TIMERIO7 is driven by TIMER4 output,TIMERIO7 is driven by TIMER5 output,TIMERIO7 is driven by TIMER6 output,TIMERIO7 is driven by TIMER7 output,TIMERIO7 is driven by TIMER8 output,TIMERIO7 is driven by TIMER9 output,TIMERIO7 is driven by TIMER10 output,TIMERIO7 is driven by TIMER11 output,TIMERIO7 is driven by TIMER12 output,TIMERIO7 is driven by TIMER13 output,TIMERIO7 is driven by TIMER14 output,TIMERIO7 is driven by TIMER15 output,TIMERIO7 is driven by TIMER16 output,TIMERIO7 is driven by TIMER17 output,TIMERIO7 is driven by TIMER18 output,TIMERIO7 is driven by TIMER19 output,?..."
group.long 0x42C0++0x0F
line.long 0x00 "CTRLMMR_I3C0_CTRL0,Controls I3C0 operation"
hexmask.long.word 0x00 16.--30. 1. "PID_MFR_ID,Manufacturer ID"
newline
bitfld.long 0x00 8. "ROLE,Master Role" "0,1"
newline
bitfld.long 0x00 0.--3. "PID_INSTANCE,Provisional ID Instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CTRLMMR_I3C0_CTRL1,Controls I3C0 operation"
hexmask.long.byte 0x04 24.--31. 1. "BUS_AVAIL_TIME,Indicates the number of sclk cycles in the Bus Available condition"
newline
hexmask.long.tbyte 0x04 0.--17. 1. "BUS_IDLE_TIME,Indicates the number of sclk cycles in the Bus Idle condition"
line.long 0x08 "CTRLMMR_I3C1_CTRL0,Controls I3C1 operation"
hexmask.long.word 0x08 16.--30. 1. "PID_MFR_ID,Manufacturer ID"
newline
bitfld.long 0x08 8. "ROLE,Master Role" "0,1"
newline
bitfld.long 0x08 0.--3. "PID_INSTANCE,Provisional ID Instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CTRLMMR_I3C1_CTRL1,Controls I3C1 operation"
hexmask.long.byte 0x0C 24.--31. 1. "BUS_AVAIL_TIME,Indicates the number of sclk cycles in the Bus Available condition"
newline
hexmask.long.tbyte 0x0C 0.--17. 1. "BUS_IDLE_TIME,Indicates the number of sclk cycles in the Bus Idle condition"
group.long 0x42E0++0x07
line.long 0x00 "CTRLMMR_I2C0_CTRL,Controls I2C0 operation"
bitfld.long 0x00 0. "HS_MCS_EN,HS Mode master current source enable" "0,1"
line.long 0x04 "CTRLMMR_I2C1_CTRL,Controls I2C1 operation"
bitfld.long 0x04 0. "HS_MCS_EN,HS Mode master current source enable" "0,1"
group.long 0x4300++0x03
line.long 0x00 "CTRLMMR_DPHY_TX0_CTRL,Controls DPHY_TX0 Lane 0 operation"
bitfld.long 0x00 0.--1. "LANE_FUNC_SEL,Selects the source for the 4 lanes of DPHY_TX 0" "IP1 (DSI0 PPI0),IP2 (CSI-TX0),?..."
group.long 0x43F0++0x03
line.long 0x00 "CTRLMMR_CSI_RX_LOOPBACK,Controls loopback of CSI-RX inputs to CSI-TX inputs for diagnostics"
bitfld.long 0x00 0.--3. "CSITX_LB_SEL,Selects the CSI-RX loopback source for CSI-TX0" "CSI-RX0,?,?,CSI-RX 1,?,?,CSI-RX 2,?,?,CSI-RX 3,?..."
group.long 0x4500++0x0F
line.long 0x00 "CTRLMMR_GPU_GP_IN_REQ,Generates GPIO input event to the GPU"
bitfld.long 0x00 15. "REQ,Input request" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DATA,GPIO requestor data input to the GPU"
line.long 0x04 "CTRLMMR_GPU_GP_IN_ACK,Acknowledge for GPIO input event from the GPU"
bitfld.long 0x04 15. "ACK,Input acknowledge" "0,1"
line.long 0x08 "CTRLMMR_GPU_GP_OUT_REQ,Generates GPIO output event from the GPU"
bitfld.long 0x08 15. "REQ,Output request" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "DATA,GPIO requestor data output from the GPU"
line.long 0x0C "CTRLMMR_GPU_GP_OUT_ACK,Acknowledge for GPIO output event to the GPU"
bitfld.long 0x0C 15. "ACK,Output acknowledge" "0,1"
group.long 0x5008++0x07
line.long 0x00 "CTRLMMR_LOCK1_KICK0,Lower 32-bits of Partition1 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK1_KICK1,Upper 32-bits of Partition 1 write lock key"
group.long 0x8000++0x07
line.long 0x00 "CTRLMMR_OBSCLK0_CTRL,This register controls which internal clock is made observable on the OBSCLK[2:0] output pins"
bitfld.long 0x00 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "CLK_DIV,OBSCLK0 output divider"
newline
bitfld.long 0x00 0.--4. "CLK_SEL,OBSCLK0 clock source selection" "MAIN_PLL0_HSDIV0_CLKOUT,MAIN_PLL1_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL3_HSDIV0_CLKOUT,MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL5_HSDIV0_CLKOUT,MAIN_PLL6_HSDIV0_CLKOUT,'0','0','0','0','0',MAIN_PLL12_HSDIV0_CLKOUT,OBSCLK1 OUT,MAIN_PLL14_HSDIV0_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,MAIN_PLL16_HSDIV0_CLKOUT,MAIN_PLL17_HSDIV0_CLKOUT,MAIN_PLL18_HSDIV0_CLKOUT,MAIN_PLL19_HSDIV0_CLKOUT,UFS MPHY_TX_REF_SYMBOLCLK,UFS MPHY_M31_VCO_19P2M_CLK,UFS MPHY_M31_VCO_26M_CLK,MAIN_PLL23_HSDIV0_CLKOUT,MAIN_PLL24_HSDIV0_CLKOUT,MAIN_PLL25_HSDIV0_CLKOUT,CPTS_GENF3,CLK_12M_RC,WKUP_LFOSC0_CLKOUT,PLLCTRL_OBSCLK,HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT"
line.long 0x04 "CTRLMMR_OBSCLK1_CTRL,This register controls which internal clock is made observable on the OBSCLK1_OUT internal clock signal"
bitfld.long 0x04 0.--1. "CLK_SEL,OBSCLK1_OUT signal output clock source selection" "MAIN_PLL7_HSDIV0_CLKOUT / DIV4,MAIN_PLL8_HSDIV0_CLKOUT / DIV8,MAIN_PLL13_HSDIV0_CLKOUT / DIV4,'0'"
group.long 0x8010++0x03
line.long 0x00 "CTRLMMR_CLKOUT_CTRL,Enables and selects clock source of CPSW CLKOUT pin"
bitfld.long 0x00 4. "CLK_EN,When set enables CLKOUT output" "0,1"
newline
bitfld.long 0x00 0. "CLK_SEL,Selects CLKOUT clock source" "0,1"
group.long 0x8030++0x03
line.long 0x00 "CTRLMMR_GTC_CLKSEL,Selects the timebase clock source for the Global Timebase Counter"
bitfld.long 0x00 0.--3. "CLK_SEL,Selects the GTC timebase clock source" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
group.long 0x803C++0x0B
line.long 0x00 "CTRLMMR_EFUSE_CLKSEL,Selects the functional clock source for the MAIN domain eFuse Controller"
bitfld.long 0x00 0. "CLK_SEL,Selects the clock source" "WKUP_HFOSC0_CLKOUT,MAIN_SYSCLK0 / 4"
line.long 0x04 "CTRLMMR_ICSSG0_CLKSEL,Selects the functional clock source for ICSS_G0"
bitfld.long 0x04 16.--19. "IEP_CLKSEL,Selects the ICSSG0 IEP clock source" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
newline
bitfld.long 0x04 0. "CORE_CLKSEL,Selects the ICSSG0 functional clock source" "MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL3_HSDIV1_CLKOUT"
line.long 0x08 "CTRLMMR_ICSSG1_CLKSEL,Selects the functional clock source for ICSS_G1"
bitfld.long 0x08 16.--19. "IEP_CLKSEL,Selects the ICSSG1 IEP clock source" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
newline
bitfld.long 0x08 0. "CORE_CLKSEL,Selects the ICSSG1 functional clock source" "MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL3_HSDIV1_CLKOUT"
group.long 0x8070++0x23
line.long 0x00 "CTRLMMR_PCIE_REFCLK0_CLKSEL,Selects the ACSPCIE clock source for the PCIE_REFCLK0 P/N output pins PCIE_REFCLK[1:0] P/N are driven by ACSPCIE0 PAD[1:0] and PCIE_REFCLK[3:2] P/N are driven by ACSPCIE1 PAD[1:0]"
bitfld.long 0x00 8. "OUT_CLK_EN,Enables the output of the ACSPCIE buffer to drive the PCIE0 REFCLK P/N pins" "0,1"
newline
bitfld.long 0x00 0.--1. "OUT_CLKSEL,Selects the PCIE0 REFCLK output clock source" "SERDES0_REF_DER_OUT_CLK,SERDES1_REF_DER_OUT_CLK,SERDES0_REFCLK1_OUT,SERDES1_REFCLK1_OUT"
line.long 0x04 "CTRLMMR_PCIE_REFCLK1_CLKSEL,Selects the ACSPCIE clock source for the PCIE_REFCLK1 P/N output pins PCIE_REFCLK[1:0] P/N are driven by ACSPCIE0 PAD[1:0] and PCIE_REFCLK[3:2] P/N are driven by ACSPCIE1 PAD[1:0]"
bitfld.long 0x04 8. "OUT_CLK_EN,Enables the output of the ACSPCIE buffer to drive the PCIE1 REFCLK P/N pins" "0,1"
newline
bitfld.long 0x04 0.--1. "OUT_CLKSEL,Selects the PCIE1 REFCLK output clock source" "SERDES0_REF_DER_OUT_CLK,SERDES1_REF_DER_OUT_CLK,SERDES0_REFCLK1_OUT,SERDES1_REFCLK1_OUT"
line.long 0x08 "CTRLMMR_PCIE_REFCLK2_CLKSEL,Selects the ACSPCIE clock source for the PCIE_REFCLK2 P/N output pins PCIE_REFCLK[1:0] P/N are driven by ACSPCIE0 PAD[1:0] and PCIE_REFCLK[3:2] P/N are driven by ACSPCIE1 PAD[1:0]"
bitfld.long 0x08 8. "OUT_CLK_EN,Enables the output of the ACSPCIE buffer to drive the PCIE2 REFCLK P/N pins" "0,1"
newline
bitfld.long 0x08 0.--1. "OUT_CLKSEL,Selects the PCIE2 REFCLK output clock source" "SERDES2_REF_DER_OUT_CLK,SERDES3_REF_DER_OUT_CLK,SERDES2_REFCLK1_OUT,SERDES3_REFCLK1_OUT"
line.long 0x0C "CTRLMMR_PCIE_REFCLK3_CLKSEL,Selects the ACSPCIE clock source for the PCIE_REFCLK3 P/N output pins PCIE_REFCLK[1:0] P/N are driven by ACSPCIE0 PAD[1:0] and PCIE_REFCLK[3:2] P/N are driven by ACSPCIE1 PAD[1:0]"
bitfld.long 0x0C 8. "OUT_CLK_EN,Enables the output of the ACSPCIE buffer to drive the PCIE3 REFCLK P/N pins" "0,1"
newline
bitfld.long 0x0C 0.--1. "OUT_CLKSEL,Selects the PCIE3 REFCLK output clock source" "SERDES2_REF_DER_OUT_CLK,SERDES3_REF_DER_OUT_CLK,SERDES2_REFCLK1_OUT,SERDES3_REFCLK1_OUT"
line.long 0x10 "CTRLMMR_PCIE0_CLKSEL,Selects PCIe0 functional clock sources"
bitfld.long 0x10 0.--3. "CPTS_CLKSEL,Selects the clock source for the PCIE0 Common Platform Time Stamp module" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
line.long 0x14 "CTRLMMR_PCIE1_CLKSEL,Selects PCIe1 functional clock sources"
bitfld.long 0x14 0.--3. "CPTS_CLKSEL,Selects the clock source for the PCIE1 Common Platform Time Stamp module" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
line.long 0x18 "CTRLMMR_PCIE2_CLKSEL,Selects PCIe2 functional clock sources"
bitfld.long 0x18 0.--3. "CPTS_CLKSEL,Selects the clock source for the PCIE2 Common Platform Time Stamp module" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
line.long 0x1C "CTRLMMR_PCIE3_CLKSEL,Selects PCIe3 functional clock sources"
bitfld.long 0x1C 0.--3. "CPTS_CLKSEL,Selects the clock source for the PCIE3 Common Platform Time Stamp module" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
line.long 0x20 "CTRLMMR_CPSW_CLKSEL,Selects the 9X CP Switch clock sources"
bitfld.long 0x20 0.--3. "CPTS_CLKSEL,Selects the clock source for the CPSW9x Ethernet switch Common Platform Time Stamp module" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
group.long 0x8098++0x03
line.long 0x00 "CTRLMMR_NAVSS_CLKSEL,Selects the clock source for the Nav Subsystem"
bitfld.long 0x00 0.--3. "CPTS_CLKSEL,Selects the clock source for the SoC] Common Platform Time Stamp module located within the Nav Subsystem 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin).." "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MAIN_SYSCLK0"
group.long 0x80B0++0x0B
line.long 0x00 "CTRLMMR_EMMC0_CLKSEL,Selects the functional clock source for 8-bit eMMC0"
bitfld.long 0x00 0.--1. "CLK_SEL,eMMC XIN_CLK selection" "0,1,2,3"
line.long 0x04 "CTRLMMR_EMMC1_CLKSEL,Selects the functional clock source for 4-bit eMMC1"
bitfld.long 0x04 16. "LB_CLKSEL,eMMC Loopback clock selection" "0,1"
newline
bitfld.long 0x04 0.--1. "CLK_SEL,eMMC XIN_CLK selection" "0,1,2,3"
line.long 0x08 "CTRLMMR_EMMC2_CLKSEL,Selects the functional clock source for 4-bit eMMC2"
bitfld.long 0x08 16. "LB_CLKSEL,eMMC Loopback clock selection" "0,1"
newline
bitfld.long 0x08 0.--1. "CLK_SEL,eMMC XIN_CLK selection" "0,1,2,3"
group.long 0x80C0++0x03
line.long 0x00 "CTRLMMR_UFS0_CLKSEL,Selects the clocks for Universal Flash Storage 0 interface"
bitfld.long 0x00 0.--1. "MCLK_SEL,Selects the MPHY clock source" "0,1,2,3"
group.long 0x80D0++0x03
line.long 0x00 "CTRLMMR_GPMC_CLKSEL,Selects the bus and functional clock source for the GPMC module"
bitfld.long 0x00 0.--1. "CLK_SEL,Selects the GPMC clock source" "0,1,2,3"
group.long 0x80E0++0x07
line.long 0x00 "CTRLMMR_USB0_CLKSEL,Selects the functional clock sources for USB0"
bitfld.long 0x00 0. "REFCLK_SEL,Selects the clock source for the USB0 ref_clk" "0,1"
line.long 0x04 "CTRLMMR_USB1_CLKSEL,Selects the functional clock sources for USB1"
bitfld.long 0x04 0. "REFCLK_SEL,Selects the clock source for the USB1 ref_clk" "0,1"
group.long 0x8100++0x4F
line.long 0x00 "CTRLMMR_TIMER0_CLKSEL,Timer0 functional clock selection control"
bitfld.long 0x00 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x04 "CTRLMMR_TIMER1_CLKSEL,Timer1 functional clock selection control"
bitfld.long 0x04 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x08 "CTRLMMR_TIMER2_CLKSEL,Timer2 functional clock selection control"
bitfld.long 0x08 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x0C "CTRLMMR_TIMER3_CLKSEL,Timer3 functional clock selection control"
bitfld.long 0x0C 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x10 "CTRLMMR_TIMER4_CLKSEL,Timer4 functional clock selection control"
bitfld.long 0x10 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x14 "CTRLMMR_TIMER5_CLKSEL,Timer5 functional clock selection control"
bitfld.long 0x14 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x18 "CTRLMMR_TIMER6_CLKSEL,Timer6 functional clock selection control"
bitfld.long 0x18 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x1C "CTRLMMR_TIMER7_CLKSEL,Timer7 functional clock selection control"
bitfld.long 0x1C 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x20 "CTRLMMR_TIMER8_CLKSEL,Timer8 functional clock selection control"
bitfld.long 0x20 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x24 "CTRLMMR_TIMER9_CLKSEL,Timer9 functional clock selection control"
bitfld.long 0x24 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x28 "CTRLMMR_TIMER10_CLKSEL,Timer10 functional clock selection control"
bitfld.long 0x28 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x2C "CTRLMMR_TIMER11_CLKSEL,Timer11 functional clock selection control"
bitfld.long 0x2C 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x30 "CTRLMMR_TIMER12_CLKSEL,Timer12 functional clock selection control"
bitfld.long 0x30 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x34 "CTRLMMR_TIMER13_CLKSEL,Timer13 functional clock selection control"
bitfld.long 0x34 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x38 "CTRLMMR_TIMER14_CLKSEL,Timer14 functional clock selection control"
bitfld.long 0x38 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x3C "CTRLMMR_TIMER15_CLKSEL,Timer15 functional clock selection control"
bitfld.long 0x3C 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x40 "CTRLMMR_TIMER16_CLKSEL,Timer16 functional clock selection control"
bitfld.long 0x40 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x44 "CTRLMMR_TIMER17_CLKSEL,Timer17 functional clock selection control"
bitfld.long 0x44 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x48 "CTRLMMR_TIMER18_CLKSEL,Timer18 functional clock selection control"
bitfld.long 0x48 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
line.long 0x4C "CTRLMMR_TIMER19_CLKSEL,Timer19 functional clock selection control"
bitfld.long 0x4C 0.--3. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL0_HSDIV1_CLKOUT,CLK_12M_RC,MAIN_PLL3_HSDIV3_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),LPXOSC_CLKOUT,CPTS_RFT_CLK (pin),MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,MAIN_PLL4_HSDIV2_CLKOUT,CPTS_GENF2,CPTS_GENF3,CPSW9G_CPTS_GENF0,MAIN_PLL15_HSDIV2_CLKOUT"
group.long 0x8190++0x0F
line.long 0x00 "CTRLMMR_SPI0_CLKSEL,SPI0 clock control"
bitfld.long 0x00 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
line.long 0x04 "CTRLMMR_SPI1_CLKSEL,SPI1 clock control"
bitfld.long 0x04 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
line.long 0x08 "CTRLMMR_SPI2_CLKSEL,SPI2 clock control"
bitfld.long 0x08 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
line.long 0x0C "CTRLMMR_SPI3_CLKSEL,SPI3 clock control"
bitfld.long 0x0C 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
group.long 0x81A4++0x0B
line.long 0x00 "CTRLMMR_SPI5_CLKSEL,SPI5 clock control"
bitfld.long 0x00 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
line.long 0x04 "CTRLMMR_SPI6_CLKSEL,SPI6 clock control"
bitfld.long 0x04 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
line.long 0x08 "CTRLMMR_SPI7_CLKSEL,SPI7 clock control"
bitfld.long 0x08 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
group.long 0x81C0++0x27
line.long 0x00 "CTRLMMR_USART0_CLK_CTRL,Selects the clock divider of the USART0 functional clock"
bitfld.long 0x00 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x00 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x04 "CTRLMMR_USART1_CLK_CTRL,Selects the clock divider of the USART1 functional clock"
bitfld.long 0x04 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x04 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x08 "CTRLMMR_USART2_CLK_CTRL,Selects the clock divider of the USART2 functional clock"
bitfld.long 0x08 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x08 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x0C "CTRLMMR_USART3_CLK_CTRL,Selects the clock divider of the USART3 functional clock"
bitfld.long 0x0C 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x0C 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x10 "CTRLMMR_USART4_CLK_CTRL,Selects the clock divider of the USART4 functional clock"
bitfld.long 0x10 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x10 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x14 "CTRLMMR_USART5_CLK_CTRL,Selects the clock divider of the USART5 functional clock"
bitfld.long 0x14 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x14 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x18 "CTRLMMR_USART6_CLK_CTRL,Selects the clock divider of the USART6 functional clock"
bitfld.long 0x18 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x18 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x1C "CTRLMMR_USART7_CLK_CTRL,Selects the clock divider of the USART7 functional clock"
bitfld.long 0x1C 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x1C 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x20 "CTRLMMR_USART8_CLK_CTRL,Selects the clock divider of the USART8 functional clock"
bitfld.long 0x20 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x20 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x24 "CTRLMMR_USART9_CLK_CTRL,Selects the clock divider of the USART9 functional clock"
bitfld.long 0x24 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x24 0.--1. "CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
group.long 0x8200++0x2F
line.long 0x00 "CTRLMMR_MCASP0_CLKSEL,Selects the functional clock source for McASP0"
bitfld.long 0x00 0.--2. "AUXCLK_SEL,Selects the McASP0 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x04 "CTRLMMR_MCASP1_CLKSEL,Selects the functional clock source for McASP1"
bitfld.long 0x04 0.--2. "AUXCLK_SEL,Selects the McASP1 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x08 "CTRLMMR_MCASP2_CLKSEL,Selects the functional clock source for McASP2"
bitfld.long 0x08 0.--2. "AUXCLK_SEL,Selects the McASP2 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x0C "CTRLMMR_MCASP3_CLKSEL,Selects the functional clock source for McASP3"
bitfld.long 0x0C 0.--2. "AUXCLK_SEL,Selects the McASP3 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x10 "CTRLMMR_MCASP4_CLKSEL,Selects the functional clock source for McASP4"
bitfld.long 0x10 0.--2. "AUXCLK_SEL,Selects the McASP4 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x14 "CTRLMMR_MCASP5_CLKSEL,Selects the functional clock source for McASP5"
bitfld.long 0x14 0.--2. "AUXCLK_SEL,Selects the McASP5 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x18 "CTRLMMR_MCASP6_CLKSEL,Selects the functional clock source for McASP6"
bitfld.long 0x18 0.--2. "AUXCLK_SEL,Selects the McASP6 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x1C "CTRLMMR_MCASP7_CLKSEL,Selects the functional clock source for McASP7"
bitfld.long 0x1C 0.--2. "AUXCLK_SEL,Selects the McASP7 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x20 "CTRLMMR_MCASP8_CLKSEL,Selects the functional clock source for McASP8"
bitfld.long 0x20 0.--2. "AUXCLK_SEL,Selects the McASP8 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x24 "CTRLMMR_MCASP9_CLKSEL,Selects the functional clock source for McASP9"
bitfld.long 0x24 0.--2. "AUXCLK_SEL,Selects the McASP9 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x28 "CTRLMMR_MCASP10_CLKSEL,Selects the functional clock source for McASP10"
bitfld.long 0x28 0.--2. "AUXCLK_SEL,Selects the McASP10 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
line.long 0x2C "CTRLMMR_MCASP11_CLKSEL,Selects the functional clock source for McASP11"
bitfld.long 0x2C 0.--2. "AUXCLK_SEL,Selects the McASP11 auxclk clock source" "MAIN_PLL4_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,'0',ATCLK0,ATCLK1,ATCLK2,ATCLK3"
group.long 0x8240++0x2F
line.long 0x00 "CTRLMMR_MCASP0_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP0"
bitfld.long 0x00 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP0" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x00 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP0" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x04 "CTRLMMR_MCASP1_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP1"
bitfld.long 0x04 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP1" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x04 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP1" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x08 "CTRLMMR_MCASP2_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP2"
bitfld.long 0x08 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP2" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x08 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP2" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x0C "CTRLMMR_MCASP3_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP3"
bitfld.long 0x0C 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP3" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x0C 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP3" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x10 "CTRLMMR_MCASP4_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP4"
bitfld.long 0x10 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP4" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x10 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP4" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x14 "CTRLMMR_MCASP5_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP5"
bitfld.long 0x14 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP5" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x14 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP5" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x18 "CTRLMMR_MCASP6_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP6"
bitfld.long 0x18 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP6" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x18 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP6" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x1C "CTRLMMR_MCASP7_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP7"
bitfld.long 0x1C 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP7" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x1C 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP7" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x20 "CTRLMMR_MCASP8_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP8"
bitfld.long 0x20 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP8" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x20 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP8" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x24 "CTRLMMR_MCASP9_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP9"
bitfld.long 0x24 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP9" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x24 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP9" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x28 "CTRLMMR_MCASP10_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP10"
bitfld.long 0x28 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP10" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x28 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP10" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
line.long 0x2C "CTRLMMR_MCASP11_AHCLKSEL,Selects the AHCLKX and AHCLKR clock source for McASP11"
bitfld.long 0x2C 8.--11. "AHCLKX_SEL,Selects the AHCLKX input source for McASP11" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,?..."
newline
bitfld.long 0x2C 0.--3. "AHCLKR_SEL,Selects the AHCLKR input source for McASP11" "HFOSC1_CLKOUT,WKUP_HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN,AUDIO_EXT_REFCLK2_IN,AUDIO_EXT_REFCLK3_IN,MLB_IO_CLK,MLBP_IO_CLK / 2,ATCLK0,ATCLK1,ATCLK2,ATCLK3,'0','0','0','0'"
group.long 0x8280++0x43
line.long 0x00 "CTRLMMR_ASRC_RXSYNC0_SEL,Selects the source signal for the ASRC RXSYNC0 frame sync input"
bitfld.long 0x00 0.--5. "SYNC_SEL,RXSYNC source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x04 "CTRLMMR_ASRC_RXSYNC1_SEL,Selects the source signal for the ASRC RXSYNC1 frame sync input"
bitfld.long 0x04 0.--5. "SYNC_SEL,RXSYNC source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x08 "CTRLMMR_ASRC_RXSYNC2_SEL,Selects the source signal for the ASRC RXSYNC2 frame sync input"
bitfld.long 0x08 0.--5. "SYNC_SEL,RXSYNC source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x0C "CTRLMMR_ASRC_RXSYNC3_SEL,Selects the source signal for the ASRC RXSYNC3 frame sync input"
bitfld.long 0x0C 0.--5. "SYNC_SEL,RXSYNC source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x10 "CTRLMMR_ASRC_TXSYNC0_SEL,Selects the source signal for the ASRC TXSYNC0 frame sync input"
bitfld.long 0x10 0.--5. "SYNC_SEL,TXSYNC source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x14 "CTRLMMR_ASRC_TXSYNC1_SEL,Selects the source signal for the ASRC TXSYNC1 frame sync input"
bitfld.long 0x14 0.--5. "SYNC_SEL,TXSYNC source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x18 "CTRLMMR_ASRC_TXSYNC2_SEL,Selects the source signal for the ASRC TXSYNC2 frame sync input"
bitfld.long 0x18 0.--5. "SYNC_SEL,TXSYNC source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x1C "CTRLMMR_ASRC_TXSYNC3_SEL,Selects the source signal for the ASRC TXSYNC3 frame sync input"
bitfld.long 0x1C 0.--5. "SYNC_SEL,TXSYNC source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,MAIN_PLL4_HSDIV3_CLKOUT,MAIN_PLL15_HSDIV3_CLKOUT,ADC0_CLK,ADC1_CLK,MCU_EXT_REFCLK0 Pin,EXT_REFCLK1 Pin,?..."
line.long 0x20 "CTRLMMR_ATL_BWS0_SEL,Selects the source of ATL Baseband Word Select 0"
bitfld.long 0x20 0.--4. "WD_SEL,BWS source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,?..."
line.long 0x24 "CTRLMMR_ATL_BWS1_SEL,Selects the source of ATL Baseband Word Select 1"
bitfld.long 0x24 0.--4. "WD_SEL,BWS source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,?..."
line.long 0x28 "CTRLMMR_ATL_BWS2_SEL,Selects the source of ATL Baseband Word Select 2"
bitfld.long 0x28 0.--4. "WD_SEL,BWS source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,?..."
line.long 0x2C "CTRLMMR_ATL_BWS3_SEL,Selects the source of ATL Baseband Word Select 3"
bitfld.long 0x2C 0.--4. "WD_SEL,BWS source signal" "McASP0 AFSR Pin Input,McASP1 AFSR Pin Input,McASP2 AFSR Pin Input,McASP3 AFSR Pin Input,McASP4 AFSR Pin Input,McASP5 AFSR Pin Input,McASP6 AFSR Pin Input,McASP7 AFSR Pin Input,McASP8 AFSR Pin Input,McASP9 AFSR Pin Input,McASP10 AFSR Pin Input,McASP11 AFSR Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,?..."
line.long 0x30 "CTRLMMR_ATL_AWS0_SEL,Selects the source of ATL Audio Word Select 0"
bitfld.long 0x30 0.--4. "WD_SEL,AWS source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,?..."
line.long 0x34 "CTRLMMR_ATL_AWS1_SEL,Selects the source of ATL Audio Word Select 1"
bitfld.long 0x34 0.--4. "WD_SEL,AWS source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,?..."
line.long 0x38 "CTRLMMR_ATL_AWS2_SEL,Selects the source of ATL Audio Word Select 2"
bitfld.long 0x38 0.--4. "WD_SEL,AWS source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,?..."
line.long 0x3C "CTRLMMR_ATL_AWS3_SEL,Selects the source of ATL Audio Word Select 3"
bitfld.long 0x3C 0.--4. "WD_SEL,AWS source signal" "McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,McASP0 AFSX Pin Input,McASP1 AFSX Pin Input,McASP2 AFSX Pin Input,McASP3 AFSX Pin Input,McASP4 AFSX Pin Input,McASP5 AFSX Pin Input,McASP6 AFSX Pin Input,McASP7 AFSX Pin Input,McASP8 AFSX Pin Input,McASP9 AFSX Pin Input,McASP10 AFSX Pin Input,McASP11 AFSX Pin Input,AUDIO_EXT_REFCLK0 Pin input,AUDIO_EXT_REFCLK1 Pin input,AUDIO_EXT_REFCLK2 Pin input,AUDIO_EXT_REFCLK3 Pin input,MLB_IO_CLK,MLBP_IO_CLK /2,?..."
line.long 0x40 "CTRLMMR_ATL_CLKSEL,Selects the source of the ATL PCLK"
bitfld.long 0x40 0.--3. "PCLK_SEL,Selects the PCLK clock source" "MAIN_PLL4_HSDIV1_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV1_CLKOUT,'0',MAIN_PLL0_HSDIV7_CLKOUT,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),'0',?..."
group.long 0x82E0++0x0F
line.long 0x00 "CTRLMMR_AUDIO_REFCLK0_CTRL,Selects the clock source for the AUDIO_EXT_REFCLK0 output"
bitfld.long 0x00 15. "CLKOUT_EN,AUDIO_REFCLK 0 output enable" "0,1"
newline
bitfld.long 0x00 0.--4. "CLK_SEL,Clock source" "MCASP0 AHCLKR Output,MCASP1 AHCLKR Output,MCASP2 AHCLKR Output,MCASP3 AHCLKR Output,MCASP4 AHCLKR Output,MCASP5 AHCLKR Output,MCASP6 AHCLKR Output,MCASP7 AHCLKR Output,MCASP8 AHCLKR Output,MCASP9 AHCLKR Output,MCASP10 AHCLKR Output,MCASP11 AHCLKR Output,MCASP0 AHCLKX Output,MCASP1 AHCLKX Output,MCASP2 AHCLKX Output,MCASP3 AHCLKX Output,MCASP4 AHCLKX Output,MCASP5 AHCLKX Output,MCASP6 AHCLKX Output,MCASP7 AHCLKX Output,MCASP8 AHCLKX Output,MCASP9 AHCLKX Output,MCASP10 AHCLKX Output,MCASP11 AHCLKX Output,ATCLK0,ATCLK1,ATCLK2,ATCLK3,MAIN_PLL4_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV2_CLKOUT,'0','0'"
line.long 0x04 "CTRLMMR_AUDIO_REFCLK1_CTRL,Selects the clock source for the AUDIO_EXT_REFCLK1 output"
bitfld.long 0x04 15. "CLKOUT_EN,AUDIO_REFCLK 1 output enable" "0,1"
newline
bitfld.long 0x04 0.--4. "CLK_SEL,Clock source" "MCASP0 AHCLKR Output,MCASP1 AHCLKR Output,MCASP2 AHCLKR Output,MCASP3 AHCLKR Output,MCASP4 AHCLKR Output,MCASP5 AHCLKR Output,MCASP6 AHCLKR Output,MCASP7 AHCLKR Output,MCASP8 AHCLKR Output,MCASP9 AHCLKR Output,MCASP10 AHCLKR Output,MCASP11 AHCLKR Output,MCASP0 AHCLKX Output,MCASP1 AHCLKX Output,MCASP2 AHCLKX Output,MCASP3 AHCLKX Output,MCASP4 AHCLKX Output,MCASP5 AHCLKX Output,MCASP6 AHCLKX Output,MCASP7 AHCLKX Output,MCASP8 AHCLKX Output,MCASP9 AHCLKX Output,MCASP10 AHCLKX Output,MCASP11 AHCLKX Output,ATCLK0,ATCLK1,ATCLK2,ATCLK3,MAIN_PLL4_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV2_CLKOUT,'0','0'"
line.long 0x08 "CTRLMMR_AUDIO_REFCLK2_CTRL,Selects the clock source for the AUDIO_EXT_REFCLK2 output"
bitfld.long 0x08 15. "CLKOUT_EN,AUDIO_REFCLK 2 output enable" "0,1"
newline
bitfld.long 0x08 0.--4. "CLK_SEL,Clock source" "MCASP0 AHCLKR Output,MCASP1 AHCLKR Output,MCASP2 AHCLKR Output,MCASP3 AHCLKR Output,MCASP4 AHCLKR Output,MCASP5 AHCLKR Output,MCASP6 AHCLKR Output,MCASP7 AHCLKR Output,MCASP8 AHCLKR Output,MCASP9 AHCLKR Output,MCASP10 AHCLKR Output,MCASP11 AHCLKR Output,MCASP0 AHCLKX Output,MCASP1 AHCLKX Output,MCASP2 AHCLKX Output,MCASP3 AHCLKX Output,MCASP4 AHCLKX Output,MCASP5 AHCLKX Output,MCASP6 AHCLKX Output,MCASP7 AHCLKX Output,MCASP8 AHCLKX Output,MCASP9 AHCLKX Output,MCASP10 AHCLKX Output,MCASP11 AHCLKX Output,ATCLK0,ATCLK1,ATCLK2,ATCLK3,MAIN_PLL4_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV2_CLKOUT,'0','0'"
line.long 0x0C "CTRLMMR_AUDIO_REFCLK3_CTRL,Selects the clock source for the AUDIO_EXT_REFCLK3 output"
bitfld.long 0x0C 15. "CLKOUT_EN,AUDIO_REFCLK 3 output enable" "0,1"
newline
bitfld.long 0x0C 0.--4. "CLK_SEL,Clock source" "MCASP0 AHCLKR Output,MCASP1 AHCLKR Output,MCASP2 AHCLKR Output,MCASP3 AHCLKR Output,MCASP4 AHCLKR Output,MCASP5 AHCLKR Output,MCASP6 AHCLKR Output,MCASP7 AHCLKR Output,MCASP8 AHCLKR Output,MCASP9 AHCLKR Output,MCASP10 AHCLKR Output,MCASP11 AHCLKR Output,MCASP0 AHCLKX Output,MCASP1 AHCLKX Output,MCASP2 AHCLKX Output,MCASP3 AHCLKX Output,MCASP4 AHCLKX Output,MCASP5 AHCLKX Output,MCASP6 AHCLKX Output,MCASP7 AHCLKX Output,MCASP8 AHCLKX Output,MCASP9 AHCLKX Output,MCASP10 AHCLKX Output,MCASP11 AHCLKX Output,ATCLK0,ATCLK1,ATCLK2,ATCLK3,MAIN_PLL4_HSDIV2_CLKOUT,MAIN_PLL15_HSDIV2_CLKOUT,'0','0'"
group.long 0x8300++0x07
line.long 0x00 "CTRLMMR_DPI0_CLK_CTRL,Selects the clock source for the DPI0 video output"
bitfld.long 0x00 0. "EXT_CLKSEL,Selects whether to use DSS PLL3 or an external pin as a DPI clock source" "0,1"
line.long 0x04 "CTRLMMR_DPI1_CLK_CTRL,Selects the clock source for the DPI1 video output"
bitfld.long 0x04 0. "EXT_CLKSEL,Selects whether to use DSS PLL7 or an external pin as a DPI clock source" "0,1"
group.long 0x8310++0x03
line.long 0x00 "CTRLMMR_DPHY0_CLKSEL,Selects the clock source for the DSI0 transmit PHY"
bitfld.long 0x00 0.--1. "REF_CLK_SEL,DPHY reference clock source" "0,1,2,3"
group.long 0x8324++0x0B
line.long 0x00 "CTRLMMR_DSS_DISPC0_CLKSEL1,Selects the clock source for DPI Lane 1 of Display Controller Instance 0"
bitfld.long 0x00 0.--1. "DPI1_PCLK,DPI lane 1 pixel clock source" "MAIN_PLL17_HSDIV0_CLKOUT,MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN,MAIN_PLL23_HSDIV0_CLKOUT_EXTPCLKIN,MAIN_PLL16_HSDIV1_CLKOUT"
line.long 0x04 "CTRLMMR_DSS_DISPC0_CLKSEL2,Selects the clock source for DPI Lane 2 of Display Controller Instance 0"
bitfld.long 0x04 0. "DPI2_PCLK,DPI lane 2 pixel clock source" "MAIN_PLL16_HSDIV0_CLKOUT,MAIN_PLL18_HSDIV0_CLKOUT"
line.long 0x08 "CTRLMMR_DSS_DISPC0_CLKSEL3,Selects the clock source for DPI Lane 3 of Display Controller Instance 0 Can also override the DPI Lane 0 and DPI Lane 2 clock source for certain values"
bitfld.long 0x08 0.--2. "DPI3_PCLK,DPI lane 3 pixel clock source" "MAIN_PLL16_HSDIV1_CLKOUT,MAIN_PLL17_HSDIV1_CLKOUT,MAIN_PLL18_HSDIV1_CLKOUT,MAIN_PLL19_HSDIV0_CLKOUT_EXTPCLKIN,MAIN_PLL23_HSDIV0_CLKOUT_EXTPCLKIN,MAIN_PLL23_HSDIV0_CLKOUT_EXTPCLKIN and dpi0_pclk..,MAIN_PLL23_HSDIV0_CLKOUT_EXTPCLKIN and dpi2_pclk..,MAIN_PLL23_HSDIV0_CLKOUT_EXTPCLKIN and dpi0_pclk.."
group.long 0x8340++0x03
line.long 0x00 "CTRLMMR_EDP_PHY0_CLKSEL,Selects the Phy core clock for Embedded Display Port Phy0"
bitfld.long 0x00 0.--1. "CLK_SEL,EDP PHY CORE_REFCLK clock source" "0,1,2,3"
group.long 0x8350++0x03
line.long 0x00 "CTRLMMR_EDP0_CLK_CTRL,Controls clock operation for Embedded Display Port 0"
bitfld.long 0x00 8. "DSI_CLK_DYN_SWTCH_DIS,EDP0 DSI clock dynamic switch disable" "0,1"
group.long 0x8380++0x07
line.long 0x00 "CTRLMMR_WWD0_CLKSEL,ARM MPU Core 0 Windowed watchdog timer functional clock selection control"
bitfld.long 0x00 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x00 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x04 "CTRLMMR_WWD1_CLKSEL,ARM MPU Core 1 Windowed watchdog timer functional clock selection control"
bitfld.long 0x04 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x04 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
group.long 0x83BC++0x07
line.long 0x00 "CTRLMMR_WWD15_CLKSEL,GPU Windowed watchdog timer functional clock selection control"
bitfld.long 0x00 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x00 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x04 "CTRLMMR_WWD16_CLKSEL,C71x Core 0 Windowed watchdog timer functional clock selection control"
bitfld.long 0x04 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x04 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
group.long 0x83E0++0x07
line.long 0x00 "CTRLMMR_WWD24_CLKSEL,C66x Core 0 Windowed watchdog timer functional clock selection control"
bitfld.long 0x00 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x00 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x04 "CTRLMMR_WWD25_CLKSEL,C66x Core 1 Windowed watchdog timer functional clock selection control"
bitfld.long 0x04 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x04 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
group.long 0x83F0++0x17
line.long 0x00 "CTRLMMR_WWD28_CLKSEL,Main R5 Core 0 Windowed watchdog timer functional clock selection control"
bitfld.long 0x00 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x00 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x04 "CTRLMMR_WWD29_CLKSEL,Main R5 Core 1 Windowed watchdog timer functional clock selection control"
bitfld.long 0x04 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x04 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x08 "CTRLMMR_WWD30_CLKSEL,Main R5 Core 2 Windowed watchdog timer functional clock selection control"
bitfld.long 0x08 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x08 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x0C "CTRLMMR_WWD31_CLKSEL,Main R5 Core 3 Windowed watchdog timer functional clock selection control"
bitfld.long 0x0C 31. "WRTLOCK,When set locks" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLK_SEL,Windowed watchdog timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,HFOSC1_CLKOUT,reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT),reserved (HFOSC1_CLKOUT)"
line.long 0x10 "CTRLMMR_SERDES0_CLKSEL,Selects the clock source for Lane 0 when configured as 2 single lane PHYs and Lane 0-1 when configured as a dual lane PHY"
bitfld.long 0x10 0.--1. "CORE_REFCLK_SEL,Selects the source for the core_refclk input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
line.long 0x14 "CTRLMMR_SERDES0_CLK1SEL,Selects the clock source for Lane1 when configured as 2 single lane PHYs"
bitfld.long 0x14 0.--1. "CORE_REFCLK1_SEL,Selects the source for the core_refclk1 input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
group.long 0x8410++0x07
line.long 0x00 "CTRLMMR_SERDES1_CLKSEL,Selects the clock source for Lane 0 when configured as 2 single lane PHYs and Lane 0-1 when configured as a dual lane PHY"
bitfld.long 0x00 0.--1. "CORE_REFCLK_SEL,Selects the source for the core_refclk input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
line.long 0x04 "CTRLMMR_SERDES1_CLK1SEL,Selects the clock source for Lane1 when configured as 2 single lane PHYs"
bitfld.long 0x04 0.--1. "CORE_REFCLK1_SEL,Selects the source for the core_refclk1 input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
group.long 0x8420++0x07
line.long 0x00 "CTRLMMR_SERDES2_CLKSEL,Selects the clock source for Lane 0 when configured as 2 single lane PHYs and Lane 0-1 when configured as a dual lane PHY"
bitfld.long 0x00 0.--1. "CORE_REFCLK_SEL,Selects the source for the core_refclk input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
line.long 0x04 "CTRLMMR_SERDES2_CLK1SEL,Selects the clock source for Lane1 when configured as 2 single lane PHYs"
bitfld.long 0x04 0.--1. "CORE_REFCLK1_SEL,Selects the source for the core_refclk1 input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
group.long 0x8430++0x07
line.long 0x00 "CTRLMMR_SERDES3_CLKSEL,Selects the clock source for Lane 0 when configured as 2 single lane PHYs and Lane 0-1 when configured as a dual lane PHY"
bitfld.long 0x00 0.--1. "CORE_REFCLK_SEL,Selects the source for the core_refclk input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
line.long 0x04 "CTRLMMR_SERDES3_CLK1SEL,Selects the clock source for Lane1 when configured as 2 single lane PHYs"
bitfld.long 0x04 0.--1. "CORE_REFCLK1_SEL,Selects the source for the core_refclk1 input" "WKUP_HFOSC0_CLKOUT,HFOSC1_CLKOUT,MAIN_PLL3_HSDIV4_CLKOUT,MAIN_PLL2_HSDIV4_CLKOUT"
group.long 0x8480++0x37
line.long 0x00 "CTRLMMR_MCAN0_CLKSEL,Controls the functional clock source MCAN0"
bitfld.long 0x00 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x04 "CTRLMMR_MCAN1_CLKSEL,Controls the functional clock source MCAN1"
bitfld.long 0x04 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x08 "CTRLMMR_MCAN2_CLKSEL,Controls the functional clock source MCAN2"
bitfld.long 0x08 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x0C "CTRLMMR_MCAN3_CLKSEL,Controls the functional clock source MCAN3"
bitfld.long 0x0C 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x10 "CTRLMMR_MCAN4_CLKSEL,Controls the functional clock source MCAN4"
bitfld.long 0x10 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x14 "CTRLMMR_MCAN5_CLKSEL,Controls the functional clock source MCAN5"
bitfld.long 0x14 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x18 "CTRLMMR_MCAN6_CLKSEL,Controls the functional clock source MCAN6"
bitfld.long 0x18 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x1C "CTRLMMR_MCAN7_CLKSEL,Controls the functional clock source MCAN7"
bitfld.long 0x1C 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x20 "CTRLMMR_MCAN8_CLKSEL,Controls the functional clock source MCAN8"
bitfld.long 0x20 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x24 "CTRLMMR_MCAN9_CLKSEL,Controls the functional clock source MCAN9"
bitfld.long 0x24 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x28 "CTRLMMR_MCAN10_CLKSEL,Controls the functional clock source MCAN10"
bitfld.long 0x28 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x2C "CTRLMMR_MCAN11_CLKSEL,Controls the functional clock source MCAN11"
bitfld.long 0x2C 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x30 "CTRLMMR_MCAN12_CLKSEL,Controls the functional clock source MCAN12"
bitfld.long 0x30 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
line.long 0x34 "CTRLMMR_MCAN13_CLKSEL,Controls the functional clock source MCAN13"
bitfld.long 0x34 0.--1. "CLK_SEL,MAIN MCAN_CLK selection" "0,1,2,3"
group.long 0x9008++0x07
line.long 0x00 "CTRLMMR_LOCK2_KICK0,Lower 32-bits of Partition2 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
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rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK2_KICK1,Upper 32-bits of Partition 2 write lock key"
group.long 0xC000++0x9F
line.long 0x00 "CTRLMMR_MCU0_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x00 31. "BIST_RESET,Reset LBIST macro" "0,1"
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bitfld.long 0x00 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
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bitfld.long 0x00 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x00 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CTRLMMR_MCU0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x04 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
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bitfld.long 0x04 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CTRLMMR_MCU0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x0C "CTRLMMR_MCU0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x0C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CTRLMMR_MCU0_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x10 2.--31. 1. "SPARE0,LBIST spare bits"
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bitfld.long 0x10 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
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bitfld.long 0x10 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x14 "CTRLMMR_MCU0_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x18 "CTRLMMR_MCU0_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x18 31. "BIST_DONE,LBIST is done" "0,1"
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rbitfld.long 0x18 15. "BIST_RUNNING,LBIST is running" "0,1"
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bitfld.long 0x18 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
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hexmask.long.byte 0x18 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x1C "CTRLMMR_MCU0_LBIST_MISR,Contains LBIST MISR output value"
line.long 0x20 "CTRLMMR_MCU1_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x20 31. "BIST_RESET,Reset LBIST macro" "0,1"
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bitfld.long 0x20 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
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bitfld.long 0x20 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x20 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "CTRLMMR_MCU1_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x24 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
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bitfld.long 0x24 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "CTRLMMR_MCU1_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x2C "CTRLMMR_MCU1_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x2C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x30 "CTRLMMR_MCU1_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x30 2.--31. 1. "SPARE0,LBIST spare bits"
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bitfld.long 0x30 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
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bitfld.long 0x30 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x34 "CTRLMMR_MCU1_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x38 "CTRLMMR_MCU1_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x38 31. "BIST_DONE,LBIST is done" "0,1"
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rbitfld.long 0x38 15. "BIST_RUNNING,LBIST is running" "0,1"
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bitfld.long 0x38 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
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hexmask.long.byte 0x38 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x3C "CTRLMMR_MCU1_LBIST_MISR,Contains LBIST MISR output value"
line.long 0x40 "CTRLMMR_DMPAC_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x40 31. "BIST_RESET,Reset LBIST macro" "0,1"
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bitfld.long 0x40 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x40 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x40 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
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bitfld.long 0x40 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x40 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CTRLMMR_DMPAC_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x44 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
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bitfld.long 0x44 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "CTRLMMR_DMPAC_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x4C "CTRLMMR_DMPAC_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x4C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x50 "CTRLMMR_DMPAC_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x50 2.--31. 1. "SPARE0,LBIST spare bits"
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bitfld.long 0x50 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
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bitfld.long 0x50 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x54 "CTRLMMR_DMPAC_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x58 "CTRLMMR_DMPAC_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x58 31. "BIST_DONE,LBIST is done" "0,1"
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rbitfld.long 0x58 15. "BIST_RUNNING,LBIST is running" "0,1"
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bitfld.long 0x58 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
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hexmask.long.byte 0x58 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x5C "CTRLMMR_DMPAC_LBIST_MISR,Contains LBIST MISR output value"
line.long 0x60 "CTRLMMR_VPAC_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x60 31. "BIST_RESET,Reset LBIST macro" "0,1"
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bitfld.long 0x60 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x60 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x60 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
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bitfld.long 0x60 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x60 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CTRLMMR_VPAC_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x64 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
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bitfld.long 0x64 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x64 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x64 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "CTRLMMR_VPAC_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x6C "CTRLMMR_VPAC_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x6C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x70 "CTRLMMR_VPAC_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x70 2.--31. 1. "SPARE0,LBIST spare bits"
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bitfld.long 0x70 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
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bitfld.long 0x70 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x74 "CTRLMMR_VPAC_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x78 "CTRLMMR_VPAC_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x78 31. "BIST_DONE,LBIST is done" "0,1"
newline
rbitfld.long 0x78 15. "BIST_RUNNING,LBIST is running" "0,1"
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bitfld.long 0x78 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
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hexmask.long.byte 0x78 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x7C "CTRLMMR_VPAC_LBIST_MISR,Contains LBIST MISR output value"
line.long 0x80 "CTRLMMR_DSP0_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x80 31. "BIST_RESET,Reset LBIST macro" "0,1"
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bitfld.long 0x80 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x80 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x80 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
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bitfld.long 0x80 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x80 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CTRLMMR_DSP0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x84 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
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bitfld.long 0x84 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x84 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x84 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "CTRLMMR_DSP0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x8C "CTRLMMR_DSP0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x8C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x90 "CTRLMMR_DSP0_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x90 2.--31. 1. "SPARE0,LBIST spare bits"
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bitfld.long 0x90 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
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bitfld.long 0x90 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x94 "CTRLMMR_DSP0_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x98 "CTRLMMR_DSP0_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x98 31. "BIST_DONE,LBIST is done" "0,1"
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rbitfld.long 0x98 15. "BIST_RUNNING,LBIST is running" "0,1"
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bitfld.long 0x98 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
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hexmask.long.byte 0x98 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x9C "CTRLMMR_DSP0_LBIST_MISR,Contains LBIST MISR output value"
group.long 0xC100++0x1F
line.long 0x00 "CTRLMMR_MPU0_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x00 31. "BIST_RESET,Reset LBIST macro" "0,1"
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bitfld.long 0x00 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
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bitfld.long 0x00 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x00 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CTRLMMR_MPU0_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x04 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
newline
bitfld.long 0x04 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CTRLMMR_MPU0_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x0C "CTRLMMR_MPU0_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x0C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CTRLMMR_MPU0_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x10 2.--31. 1. "SPARE0,LBIST spare bits"
newline
bitfld.long 0x10 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
newline
bitfld.long 0x10 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x14 "CTRLMMR_MPU0_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x18 "CTRLMMR_MPU0_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x18 31. "BIST_DONE,LBIST is done" "0,1"
newline
rbitfld.long 0x18 15. "BIST_RUNNING,LBIST is running" "0,1"
newline
bitfld.long 0x18 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x1C "CTRLMMR_MPU0_LBIST_MISR,Contains LBIST MISR output value"
rgroup.long 0xC280++0x13
line.long 0x00 "CTRLMMR_MCU0_LBIST_SIG,Contains expected MISR output value"
line.long 0x04 "CTRLMMR_MCU1_LBIST_SIG,Contains expected MISR output value"
line.long 0x08 "CTRLMMR_DMPAC_LBIST_SIG,Contains expected MISR output value"
line.long 0x0C "CTRLMMR_VPAC_LBIST_SIG,Contains expected MISR output value"
line.long 0x10 "CTRLMMR_DSP0_LBIST_SIG,Contains expected MISR output value"
rgroup.long 0xC2A0++0x03
line.long 0x00 "CTRLMMR_MPU0_LBIST_SIG,Contains expected MISR output value"
rgroup.long 0xC320++0x03
line.long 0x00 "CTRLMMR_FUSE_CRC_STAT,Indicates status of fuse chain CRC"
bitfld.long 0x00 15. "GRP1_CRC_ERR_7,Indicates eFuse CRC error on group1 chain 7" "0,1"
newline
bitfld.long 0x00 14. "GRP1_CRC_ERR_6,Indicates eFuse CRC error on group1 chain 6" "0,1"
newline
bitfld.long 0x00 13. "GRP1_CRC_ERR_5,Indicates eFuse CRC error on group1 chain 5" "0,1"
newline
bitfld.long 0x00 12. "GRP1_CRC_ERR_4,Indicates eFuse CRC error on group1 chain 4" "0,1"
newline
bitfld.long 0x00 11. "GRP1_CRC_ERR_3,Indicates eFuse CRC error on group1 chain 3" "0,1"
newline
bitfld.long 0x00 10. "GRP1_CRC_ERR_2,Indicates eFuse CRC error on group1 chain 2" "0,1"
newline
bitfld.long 0x00 9. "GRP1_CRC_ERR_1,Indicates eFuse CRC error on group1 chain 1" "0,1"
newline
bitfld.long 0x00 8. "GRP1_CRC_ERR_0,Indicates eFuse CRC error on group1 chain 0" "0,1"
newline
bitfld.long 0x00 7. "CRC_ERR_7,Indicates eFuse CRC error on chain 7" "0,1"
newline
bitfld.long 0x00 6. "CRC_ERR_6,Indicates eFuse CRC error on chain 6" "0,1"
newline
bitfld.long 0x00 5. "CRC_ERR_5,Indicates eFuse CRC error on chain 5" "0,1"
newline
bitfld.long 0x00 4. "CRC_ERR_4,Indicates eFuse CRC error on chain 4" "0,1"
newline
bitfld.long 0x00 3. "CRC_ERR_3,Indicates eFuse CRC error on chain 3" "0,1"
newline
bitfld.long 0x00 2. "CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1"
newline
bitfld.long 0x00 1. "CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1"
group.long 0xD008++0x07
line.long 0x00 "CTRLMMR_LOCK3_KICK0,Lower 32-bits of Partition3 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK3_KICK1,Upper 32-bits of Partition 3 write lock key"
group.long 0x14000++0x07
line.long 0x00 "CTRLMMR_CHNG_DDR4_FSP_REQ,This register is used to initiate a LPDDR4 frequency set point change to the DDR Controller"
bitfld.long 0x00 8. "REQ,Initiate FSP frequency change" "0,1"
newline
bitfld.long 0x00 0.--1. "REQ_TYPE,Frequency request type" "0,1,2,3"
line.long 0x04 "CTRLMMR_CHNG_DDR4_FSP_ACK,This register is used by the DDR Controller to acknowledge the LPDDR4 frequency set point shange request"
bitfld.long 0x04 7. "ACK,Frequency change acknowledge" "0,1"
newline
bitfld.long 0x04 0. "ERROR,Frequency change error" "0,1"
rgroup.long 0x14080++0x03
line.long 0x00 "CTRLMMR_DDR4_FSP_CLKCHNG_REQ,This register is used by the DDR Controller to request the DDR PLL clock frequency change"
bitfld.long 0x00 7. "REQ,DDR Controller FSP clock change request" "0,1"
newline
bitfld.long 0x00 0.--1. "REQ_TYPE,Frequency request type" "0,1,2,3"
group.long 0x140C0++0x03
line.long 0x00 "CTRLMMR_DDR4_FSP_CLKCHNG_ACK,This register is used to acknowledge a DDR PLL clock frequency change to the DDR Controller"
bitfld.long 0x00 0. "ACK,DDR FSP clock change ackowledge" "0,1"
group.long 0x15008++0x07
line.long 0x00 "CTRLMMR_LOCK5_KICK0,Lower 32-bits of Partition5 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK5_KICK1,Upper 32-bits of Partition 5 write lock key"
group.long 0x18090++0x07
line.long 0x00 "CTRLMMR_ACSPCIE0_CTRL,Controls the ACSPCIE0 module"
rbitfld.long 0x00 24. "BANDGAP_OK,Bandgap output okay" "0,1"
newline
bitfld.long 0x00 8. "AIPOFF,Testmode enable" "0,1"
newline
bitfld.long 0x00 1. "PWRDN1,Disable (tristate) PAD1 IO buffers" "0,1"
newline
bitfld.long 0x00 0. "PWRDN0,Disable (tristate) PAD0 IO buffers" "0,1"
line.long 0x04 "CTRLMMR_ACSPCIE1_CTRL,Controls the ACSPCIE1 module"
rbitfld.long 0x04 24. "BANDGAP_OK,Bandgap output okay when set" "0,1"
newline
bitfld.long 0x04 8. "AIPOFF,Testmode enable when set" "0,1"
newline
bitfld.long 0x04 1. "PWRDN1,Disable (tristate) PAD1 IO buffers when set" "0,1"
newline
bitfld.long 0x04 0. "PWRDN0,Disable (tristate) PAD0 IO buffers when set" "0,1"
group.long 0x19008++0x07
line.long 0x00 "CTRLMMR_LOCK6_KICK0,Lower 32-bits of Partition6 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK6_KICK1,Upper 32-bits of Partition 6 write lock key"
group.long 0x1C000++0x03
line.long 0x00 "CTRLMMR_PADCONFIG0,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
newline
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
newline
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
newline
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
newline
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
newline
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
newline
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
newline
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x1D008++0x07
line.long 0x00 "CTRLMMR_LOCK7_KICK0,Lower 32-bits of Partition7 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_LOCK7_KICK1,Upper 32-bits of Partition 7 write lock key"
group.long 0xF00100++0x03
line.long 0x00 "CTRLMMR_IPC_SET0,Generate interprocessor communication interrupt to C71x core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
newline
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat 6. (list 165. 166. 167. 168. 169. 170. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x1C294)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 4. (list 161. 162. 163. 164. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x1C284)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 14. (list 144. 145. 146. 147. 148. 149. 152. 153. 154. 155. 156. 157. 171. 172. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x20 0x24 0x28 0x2C 0x30 0x34 0x6C 0x70 )
group.long ($2+0x1C240)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
newline
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
newline
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
newline
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
newline
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 4. (list 136. 137. 138. 139. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x1C220)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
newline
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
newline
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
newline
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 129. 130. 131. 132. 133. 134. 135. 140. 141. 142. 143. 150. 151. 158. 159. 160. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x2C 0x30 0x34 0x38 0x54 0x58 0x74 0x78 0x7C )
group.long ($2+0x1C204)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C1C4)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C184)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C144)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C104)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C0C4)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C084)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C044)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C004)++0x03
line.long 0x00 "CTRLMMR_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output disable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual MAIN_GPIO instance select" "Implement GPIO in GPIO_0/1 instance,Implement GPIO in GPIO_2/3 instance,Implement GPIO in GPIO_4/5 instance,Implement GPIO in GPIO_6/7 instance"
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
repeat.end
repeat 2. (list 22. 23. )(list 0x00 0x04 )
group.long ($2+0x1D8)++0x03
line.long 0x00 "CTRLMMR_IPC_CLR$1,Acknowledge interprocessor communication interrupt to ICSSG1 PRU0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
repeat.end
repeat 2. (list 20. 21. )(list 0x00 0x04 )
group.long ($2+0x1D0)++0x03
line.long 0x00 "CTRLMMR_IPC_CLR$1,Acknowledge interprocessor communication interrupt to ICSSG0 PRU0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
repeat.end
repeat 4. (list 16. 17. 18. 19. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x1C0)++0x03
line.long 0x00 "CTRLMMR_IPC_CLR$1,Acknowledge interprocessor communication interrupt to MAIN R5 core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
repeat.end
repeat 2. (list 8. 9. )(list 0x00 0x04 )
group.long ($2+0x1A0)++0x03
line.long 0x00 "CTRLMMR_IPC_CLR$1,Acknowledge interprocessor communication interrupt to ARM MPU core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
repeat.end
repeat 2. (list 6. 7. )(list 0x00 0x04 )
group.long ($2+0x198)++0x03
line.long 0x00 "CTRLMMR_IPC_CLR$1,Acknowledge interprocessor communication interrupt to C66 core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
repeat.end
repeat 2. (list 22. 23. )(list 0x00 0x04 )
group.long ($2+0x158)++0x03
line.long 0x00 "CTRLMMR_IPC_SET$1,Generate interprocessor communication interrupt to ICSSG1 PRU0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat.end
repeat 2. (list 20. 21. )(list 0x00 0x04 )
group.long ($2+0x150)++0x03
line.long 0x00 "CTRLMMR_IPC_SET$1,Generate interprocessor communication interrupt to ICSSG0 PRU0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat.end
repeat 4. (list 16. 17. 18. 19. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x140)++0x03
line.long 0x00 "CTRLMMR_IPC_SET$1,Generate interprocessor communication interrupt to MAIN R5 core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat.end
repeat 2. (list 8. 9. )(list 0x00 0x04 )
group.long ($2+0x120)++0x03
line.long 0x00 "CTRLMMR_IPC_SET$1,Generate interprocessor communication interrupt to ARM MPU core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat.end
repeat 2. (list 6. 7. )(list 0x00 0x04 )
group.long ($2+0x118)++0x03
line.long 0x00 "CTRLMMR_IPC_SET$1,Generate interprocessor communication interrupt to C66 core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat.end
tree.end
tree.end
tree "DCC"
repeat 3. (list 0. 1. 2. )(list ad:0x40100000 ad:0x40110000 ad:0x40120000 )
tree "MCU_DCC$1"
base $2
group.long 0x00++0x37
line.long 0x00 "DCC_GCTRL,Starts / stops the counters"
bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCC_REV,Specifies the module version"
bitfld.long 0x04 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01" "0,1,2,3"
hexmask.long.word 0x04 16.--27. 1. "FUNC,Reflects software-compatability"
bitfld.long 0x04 11.--15. "RTL,Incremented for releases due to spec changes or post-release design changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--10. "MAJOR,Represents major changes to the module (e.g" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 6.--7. "CUSTOM,Indicates a special version of the module" "0,1,2,3"
bitfld.long 0x04 0.--5. "MINOR,Represents minor changes to the module (e.g" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)"
line.long 0x0C "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)"
line.long 0x14 "DCC_STATUS,Specifies the status of the DCC Module"
bitfld.long 0x14 1. "DONE,Indicates when single-shot mode is complete without error" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCC_CNT0,Value of the counter attached to clock source 0"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCC_VALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCC_CNT1,Value of the counter attached to clock source 1"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCC_CLKSRC1,Selects the clock source for counter 1"
bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection for counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--4. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "DCC_CLKSRC0,Selects the clock source for counter 0"
bitfld.long 0x28 12.--15. "KEY,This field enables or disables clock source selection for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DCC_GCTRL2,Allows configuring different modes of operation for DCC"
bitfld.long 0x2C 8.--11. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 4.--7. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "CONT_ON_ERR,Continues to next window of comparison despite the error condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "DCC_STATUS2,Specifies the status of the DCC FIFOs"
bitfld.long 0x30 5. "COUNT1_FIFO_FULL,Count1 FIFO Full" "0,1"
bitfld.long 0x30 4. "VALID0_FIFO_FULL,Valid0 FIFO Full" "0,1"
bitfld.long 0x30 3. "COUNT0_FIFO_FULL,Count0 FIFO Full" "0,1"
bitfld.long 0x30 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty" "0,1"
bitfld.long 0x30 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty" "0,1"
bitfld.long 0x30 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty" "0,1"
line.long 0x34 "DCC_ERRCNT,Counts number of errors since last clear"
hexmask.long.word 0x34 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset"
tree.end
repeat.end
repeat 13. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. )(list ad:0x800000 ad:0x804000 ad:0x808000 ad:0x80C000 ad:0x810000 ad:0x814000 ad:0x818000 ad:0x81C000 ad:0x820000 ad:0x824000 ad:0x828000 ad:0x82C000 ad:0x830000 )
tree "DCC$1"
base $2
group.long 0x00++0x37
line.long 0x00 "DCC_GCTRL,Starts / stops the counters"
bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCC_STAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCC_REV,Specifies the module version"
bitfld.long 0x04 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01" "0,1,2,3"
hexmask.long.word 0x04 16.--27. 1. "FUNC,Reflects software-compatability"
bitfld.long 0x04 11.--15. "RTL,Incremented for releases due to spec changes or post-release design changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--10. "MAJOR,Represents major changes to the module (e.g" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 6.--7. "CUSTOM,Indicates a special version of the module" "0,1,2,3"
bitfld.long 0x04 0.--5. "MINOR,Represents minor changes to the module (e.g" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DCC_CNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)"
line.long 0x0C "DCC_VALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCC_CNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)"
line.long 0x14 "DCC_STATUS,Specifies the status of the DCC Module"
bitfld.long 0x14 1. "DONE,Indicates when single-shot mode is complete without error" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCC_CNT0,Value of the counter attached to clock source 0"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCC_VALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCC_CNT1,Value of the counter attached to clock source 1"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCC_CLKSRC1,Selects the clock source for counter 1"
bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection for counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--4. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "DCC_CLKSRC0,Selects the clock source for counter 0"
bitfld.long 0x28 12.--15. "KEY,This field enables or disables clock source selection for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DCC_GCTRL2,Allows configuring different modes of operation for DCC"
bitfld.long 0x2C 8.--11. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 4.--7. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "CONT_ON_ERR,Continues to next window of comparison despite the error condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "DCC_STATUS2,Specifies the status of the DCC FIFOs"
bitfld.long 0x30 5. "COUNT1_FIFO_FULL,Count1 FIFO Full" "0,1"
bitfld.long 0x30 4. "VALID0_FIFO_FULL,Valid0 FIFO Full" "0,1"
bitfld.long 0x30 3. "COUNT0_FIFO_FULL,Count0 FIFO Full" "0,1"
bitfld.long 0x30 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty" "0,1"
bitfld.long 0x30 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty" "0,1"
bitfld.long 0x30 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty" "0,1"
line.long 0x34 "DCC_ERRCNT,Counts number of errors since last clear"
hexmask.long.word 0x34 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset"
tree.end
repeat.end
tree.end
tree "DDR_Controller"
tree "COMPUTE_CLUSTER0_CTL_CFG"
base ad:0x2990000
group.long 0x4000++0x22F
line.long 0x00 "DDRSS_PHY_0,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_0,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_0,Write data clock bypass mode slave delay setting for slice 0.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_1,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_0,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0,Write DQS bypass mode slave delay setting for slice 0"
line.long 0x08 "DDRSS_PHY_2,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for slice 0" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_0,Two_cycle_preamble for bypass mode for slice 0" "0,1,2,3"
newline
hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0,Read DQS bypass mode slave delay setting for slice 0"
line.long 0x0C "DDRSS_PHY_3,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_4,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_5,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_0,When set a register write will update parameters for all ranks at the same time in slice 0" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_0,Per-rank CS map for slice 0" "0,1,2,3"
newline
bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_6,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_0,For per-rank training indicates which rank's paramters are read/written for slice 0" "0,1"
line.long 0x1C "DDRSS_PHY_7,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0,For LPDDR4 boot frequency write path clock gating disable for slice 0" "0,1,2,3"
newline
bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_0,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_8,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_0,Loopback read only test timeout mechanism enable for slice 0" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_0,Loopback control bits for slice 0"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_0,Loopback control en for slice 0" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_9,"
line.long 0x28 "DDRSS_PHY_10,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_0,Observation register for the auto_timing_margin for slice 0"
line.long 0x2C "DDRSS_PHY_11,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_0,Read Leveling Multi-pattern enable for slice 0" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_0,PRBS7 mask signal for slice 0"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_0,PRBS7 start pattern for slice 0"
line.long 0x30 "DDRSS_PHY_12,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_0,Observation register for best vref value for slice 0"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_0,Data slice initial VREF training step size for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_0,Read Leveling read level windows disable reset for slice 0" "0,1"
line.long 0x34 "DDRSS_PHY_13,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for slice 0" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_0,Number of cycles to wait for the DQS gate to close before flagging an error for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0,Read DQS data clock bypass mode slave delay setting for slice 0"
line.long 0x38 "DDRSS_PHY_14,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_0,Indicates the type of DRAM for slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_0,Adds a cycle of delay for the slice 0 to match the address slice" "0,1"
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hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 0"
line.long 0x3C "DDRSS_PHY_15,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_0,Control the on-the-fly gate adjustment for slice 0" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 0"
line.long 0x40 "DDRSS_PHY_16,"
line.long 0x44 "DDRSS_PHY_17,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_0,Controls the read postamble extension for LPDDR4 for slice 0" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_0,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 0" "0,1"
line.long 0x48 "DDRSS_PHY_18,"
line.long 0x4C "DDRSS_PHY_19,"
line.long 0x50 "DDRSS_PHY_20,"
line.long 0x54 "DDRSS_PHY_21,"
line.long 0x58 "DDRSS_PHY_22,"
line.long 0x5C "DDRSS_PHY_23,"
line.long 0x60 "DDRSS_PHY_24,"
line.long 0x64 "DDRSS_PHY_25,"
line.long 0x68 "DDRSS_PHY_26,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_0,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_0,Disables automatic reset of the read entry FIFO pointers for slice 0" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_0,Reserved for future use for slice 0" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_27,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_0,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_0,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_0,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_0,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_28,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_0,Observation register for write leveling status for slice 0"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_0,Write leveling algorithm selection for slice 0" "0,1,2,3"
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bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_0,Allows the leveling state machine to advance (when in debug mode) for slice 0" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_0,Enables leveling debug mode for slice 0" "0,1"
line.long 0x74 "DDRSS_PHY_29,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_0,For ECC slice should set this register to do DQ bit mask for slice 0"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_30,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_0,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_0,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 0"
line.long 0x7C "DDRSS_PHY_31,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_0,Read leveling algorithm select for slice 0" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_32,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_0,Defines the minimum gap requirment for the LE and TE window for slice 0"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_0,Per-bit mask for read leveling for slice 0"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 0"
line.long 0x84 "DDRSS_PHY_33,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_0,Defines the training patterns to be used during the write data leveling sequence for slice 0" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_34,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_0,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 0" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_0,Select value to map specific information during or post periodic write data leveling for slice 0"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_35,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_0,Per-bit mask for write data leveling for slice 0"
line.long 0x90 "DDRSS_PHY_36,"
line.long 0x94 "DDRSS_PHY_37,"
line.long 0x98 "DDRSS_PHY_38,"
line.long 0x9C "DDRSS_PHY_39,"
line.long 0xA0 "DDRSS_PHY_40,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_0,Control for single pass only No-Topology training for slice 0" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_0,User-defined pattern to be used during write data leveling for slice 0"
line.long 0xA4 "DDRSS_PHY_41,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_0,Threshold Criteria of period threshold after No-Topology training is completed for slice 0"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_0,Threshold Criteria of early threshold after No-Topology training is completed for slice 0"
line.long 0xA8 "DDRSS_PHY_42,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_0,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 0"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_0,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 0"
line.long 0xAC "DDRSS_PHY_43,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_0,Observation register containing read entry FIFO pointers for slice 0"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_0,Manual reset/clear of internal logic for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_0,Indicates if slice 0 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_44,"
line.long 0xB4 "DDRSS_PHY_45,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for slice 0"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for slice 0"
line.long 0xB8 "DDRSS_PHY_46,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 0"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_0,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 0"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS base slave delay encoded value for slice 0"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_0,Observation register containing read DQ slave delay encoded values for slice 0"
line.long 0xBC "DDRSS_PHY_47,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQS base slave delay encoded value for slice 0"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS gate slave delay encoded value for slice 0"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 0"
line.long 0xC0 "DDRSS_PHY_48,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing write adder slave delay encoded value for slice 0"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQ base slave delay encoded value for slice 0"
line.long 0xC4 "DDRSS_PHY_49,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_0,Observation register containing write leveling first hard 1 DQS slave delay for slice 0"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_0,Observation register containing write leveling last hard 0 DQS slave delay for slice 0"
line.long 0xC8 "DDRSS_PHY_50,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_0,Observation register containing write leveling status for slice 0"
line.long 0xCC "DDRSS_PHY_51,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0,Observation register containing gate sample2 slave delay encoded values for slice 0"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0,Observation register containing gate sample1 slave delay encoded values for slice 0"
line.long 0xD0 "DDRSS_PHY_52,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_0,Observation register containing gate training first hard 0 DQS slave delay for slice 0"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_0,Observation register containing write leveling error status for slice 0"
line.long 0xD4 "DDRSS_PHY_53,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_0,Observation register containing gate training last hard 1 DQS slave delay for slice 0"
line.long 0xD8 "DDRSS_PHY_54,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_0,Observation register containing gate training status for slice 0"
line.long 0xDC "DDRSS_PHY_55,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0,Observation register containing read leveling data window trailing edge slave delay setting for slice 0"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0,Observation register containing read leveling data window leading edge slave delay setting for slice 0"
line.long 0xE0 "DDRSS_PHY_56,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0,Observation register containing read leveling number of windows found for slice 0" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_57,"
line.long 0xE8 "DDRSS_PHY_58,"
line.long 0xEC "DDRSS_PHY_59,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_0,Observation register containing write data leveling data window trailing edge slave delay setting for slice 0"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_0,Observation register containing write data leveling data window leading edge slave delay setting for slice 0"
line.long 0xF0 "DDRSS_PHY_60,"
line.long 0xF4 "DDRSS_PHY_61,"
line.long 0xF8 "DDRSS_PHY_62,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_0,DDL mode for slice 0"
line.long 0xFC "DDRSS_PHY_63,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_0,DDL mask for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_64,"
line.long 0x104 "DDRSS_PHY_65,"
line.long 0x108 "DDRSS_PHY_66,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_0,Manual setting of RX Calibration enable for slice 0" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_0,Manual RX Calibration start for slice 0" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_0,LPDDR4 write preamble extension enable for slice 0" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_0,Specify threshold value for PHY init update tracking for slice 0"
line.long 0x10C "DDRSS_PHY_67,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_0,RX Calibration codes for DQ0 for slice 0"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0,Data slice power reduction disable for slice 0" "0,1"
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hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_0,RX Calibration state machine wait count for slice 0"
line.long 0x110 "DDRSS_PHY_68,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_0,RX Calibration codes for DQ2 for slice 0"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_0,RX Calibration codes for DQ1 for slice 0"
line.long 0x114 "DDRSS_PHY_69,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_0,RX Calibration codes for DQ4 for slice 0"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_0,RX Calibration codes for DQ3 for slice 0"
line.long 0x118 "DDRSS_PHY_70,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_0,RX Calibration codes for DQ6 for slice 0"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_0,RX Calibration codes for DQ5 for slice 0"
line.long 0x11C "DDRSS_PHY_71,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_0,RX Calibration codes for DQ7 for slice 0"
line.long 0x120 "DDRSS_PHY_72,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_0,RX Calibration codes for DM for slice 0"
line.long 0x124 "DDRSS_PHY_73,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_0,RX Calibration codes for FDBK for slice 0"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_0,RX Calibration codes for DQS for slice 0"
line.long 0x128 "DDRSS_PHY_74,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_0,RX Calibration lock results for slice 0"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_0,RX Calibration results for slice 0"
line.long 0x12C "DDRSS_PHY_75,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_0,Expected C value from RX pad for slice 0" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_0,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_0,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_0,RX CAL disable signal for slice 0 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_76,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_0,Controls RX_BIAS_EN pin for each pad for slice 0"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_0,RX offset calibration mask of all RX pad for slice 0"
line.long 0x134 "DDRSS_PHY_77,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_0,Determines weight of average calculating for slice 0" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_0,Determines timeout number of iteration for slice 0"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_0,Determines number of cycles to wait for each sample for slice 0"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_0,Control to disable toggle during static activity for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_78,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_0,Adjust direction for slice 0" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_0,Duty cycle adjust threshold around the mid-point for slice 0"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_0,Duty cycle adjust sample count for slice 0"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_0,Duty cycle adjust starting value for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_79,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_0,Shutoff gate feedback IO to reduce power for slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_0,Rank selection for software based duty cycle correction for slice 0" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_0,Manual trigger for DCC for slice 0" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_0,Calibration polarity for slice 0" "0,1"
line.long 0x140 "DDRSS_PHY_80,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_0,Data slice power reduction disable for slice 0" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0,Data slice DCC and RX_CAL block power reduction disable for slice 0" "0,1"
newline
bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_0,Data slice read path power reduction disable for slice 0" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_0,Data slice slv_dly_control block power reduction disable for slice 0" "0,1"
line.long 0x144 "DDRSS_PHY_81,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_0,Data slice level FSM Error Info for slice 0"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_0,Inject parity error to register interface signals for slice 0"
line.long 0x148 "DDRSS_PHY_82,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0,Data slice level FSM Error Info for slice 0"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_0,Data slice level FSM Error Info Mask for slice 0"
line.long 0x14C "DDRSS_PHY_83,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0,Data slice level training/calibration Error Info for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0,Data slice level training/calibration Error Info Mask for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_0,Data slice level training/calibration Error Info for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_84,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_0,Operation type tsel enables for DQS signals for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_0,Operation type tsel select values for DQ/DM signals for slice 0"
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bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_0,Operation type tsel enables for DQ/DM signals for slice 0" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_85,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_0,Data slice initial VREF training start value for slice 0"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_0,2 cycle preamble support for slice 0" "0,1,2,3"
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hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_0,Operation type tsel select values for DQS signals for slice 0"
line.long 0x158 "DDRSS_PHY_86,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_0,Step size of WR DQ slave delay during No-Topology training for slice 0"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_0,Enable for No-Topology training for slice 0" "0,1"
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bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_0,Data slice vref training enable control for slice 0" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_0,Data slice initial VREF training stop value for slice 0"
line.long 0x15C "DDRSS_PHY_87,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_0,End of WR DQ slave delay in No-Topology training for slice 0"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_0,Starting WR DQ slave delay in No-Topology training for slice 0"
line.long 0x160 "DDRSS_PHY_88,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_0,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 0" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0"
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hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_0,Enable Bit for WR DQ during No-Topology training for slice 0"
line.long 0x164 "DDRSS_PHY_89,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_0,Controls TX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_0,Enable for fast multi-pattern window search for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_90,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_91,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_0,Controls RX_DCD pin for dm pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_92,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_0,Controls PCLK/PARK pin for pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_0,Controls RX_DCD pin for fdbk pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_0,Controls RX_DCD pin for dqs pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_93,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_0,Read DQ1 slave delay setting for slice 0"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_0,Read DQ0 slave delay setting for slice 0"
line.long 0x178 "DDRSS_PHY_94,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_0,Read DQ3 slave delay setting for slice 0"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_0,Read DQ2 slave delay setting for slice 0"
line.long 0x17C "DDRSS_PHY_95,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_0,Read DQ5 slave delay setting for slice 0"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_0,Read DQ4 slave delay setting for slice 0"
line.long 0x180 "DDRSS_PHY_96,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_0,Read DQ7 slave delay setting for slice 0"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_0,Read DQ6 slave delay setting for slice 0"
line.long 0x184 "DDRSS_PHY_97,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_0,Determines DCC CAL clock for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_0,Read DM/DBI slave delay setting for slice 0"
line.long 0x188 "DDRSS_PHY_98,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_0,Start/end timing values for DQS output enable signals for slice 0"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_0,Start/end timing values for DQ/DM write based termination enable and select signals for slice 0"
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hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_0,Start/end timing values for DQ/DM read based termination enable and select signals for slice 0"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_0,Start/end timing values for DQ/DM output enable signals for slice 0"
line.long 0x18C "DDRSS_PHY_99,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_0,Start/end timing values for DQS write based termination enable and select signals for slice 0"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_0,Start/end timing values for DQS read based OE extension for slice 0"
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hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_0,Start/end timing values for DQS read based termination enable and select signals for slice 0"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_0,Feedback pad's OPAD and IPAD delay timing for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_100,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_0,Pad VREF control settings for DQ slice 0"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_0,Number of cycles for vref settle after setting is changed for slice 0"
line.long 0x194 "DDRSS_PHY_101,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_0,Start/end timing values for DQS input enable signals for slice 0"
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hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_0,Start/end timing values for DQ/DM input enable signals for slice 0"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_0,Enables the per-rank training and read/write timing capabilities for slice 0" "0,1"
line.long 0x198 "DDRSS_PHY_102,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x198 8. "PHY_DBI_MODE_0,DBI mode for slice 0" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_0,Input enable mode bits for slice 0" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_103,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for slice 0"
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bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_0,Master delay line override settings for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_104,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_0,DQS slave delay step size during write leveling for slice 0"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_0,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 0"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for slice 0"
line.long 0x1A4 "DDRSS_PHY_105,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_0,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_0,DQS slave delay step size during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_0,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_0,DQS slave delay fine step size during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_106,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_0,Final backup step delay used in gate training algorithm for slice 0"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_0,Interim backup step delay used in gate training algorithm for slice 0"
line.long 0x1AC "DDRSS_PHY_107,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_0,DQS slave delay step size during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_0,Support the toggle read preamble for LPDDR4 for slice 0" "0,1"
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bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_0,Defines the step granularity for the logic to use once an edge is found for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_0,DQ slave delay step size during write data leveling for slice 0"
line.long 0x1B0 "DDRSS_PHY_108,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_0,The maximun rdlvl slave delay search window for read eye training for slice 0"
line.long 0x1B4 "DDRSS_PHY_109,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_0,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 0" "0,1"
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hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0"
line.long 0x1B8 "DDRSS_PHY_110,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_0,Disable duty cycle adjust at initialization for slice 0" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_0,Write path clock gating timing for slice 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_0,Write path clock gating disable for slice 0" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_111,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_0,Initial value of write DQ slave delay for slice 0"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_0,Initial value of write DQS slave delay for slice 0"
line.long 0x1C0 "DDRSS_PHY_112,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0,Clock measurement cell threshold offset for differential signals for slice 0"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_0,Clock measurement cell threshold offset for single ended signals for slice 0"
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bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_0,Enable duty cycle adjust during write DQ training for slice 0" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_0,Enable duty cycle adjust during write leveling for slice 0" "0,1"
line.long 0x1C4 "DDRSS_PHY_113,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_0,Number of cycles that the dfi_rddata_en signal is early for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_0,Data slice training step definition using phy_meas_dly_step_value for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_0,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 0"
line.long 0x1C8 "DDRSS_PHY_114,"
line.long 0x1CC "DDRSS_PHY_115,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_0,DQ/DM bit swizzling 1 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_116,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_0,Write clock slave delay setting for DQ1 for slice 0"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_0,Write clock slave delay setting for DQ0 for slice 0"
line.long 0x1D4 "DDRSS_PHY_117,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_0,Write clock slave delay setting for DQ3 for slice 0"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_0,Write clock slave delay setting for DQ2 for slice 0"
line.long 0x1D8 "DDRSS_PHY_118,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_0,Write clock slave delay setting for DQ5 for slice 0"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_0,Write clock slave delay setting for DQ4 for slice 0"
line.long 0x1DC "DDRSS_PHY_119,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_0,Write clock slave delay setting for DQ7 for slice 0"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_0,Write clock slave delay setting for DQ6 for slice 0"
line.long 0x1E0 "DDRSS_PHY_120,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_0,Write clock slave delay setting for DQS for slice 0"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_0,Write clock slave delay setting for DM for slice 0"
line.long 0x1E4 "DDRSS_PHY_121,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ0 for slice 0"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_0,Write level threshold adjust value based on those thresholds for DQS for slice 0" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_122,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ1 for slice 0"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ0 for slice 0"
line.long 0x1EC "DDRSS_PHY_123,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ2 for slice 0"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ1 for slice 0"
line.long 0x1F0 "DDRSS_PHY_124,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ3 for slice 0"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ2 for slice 0"
line.long 0x1F4 "DDRSS_PHY_125,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ4 for slice 0"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ3 for slice 0"
line.long 0x1F8 "DDRSS_PHY_126,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ5 for slice 0"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ4 for slice 0"
line.long 0x1FC "DDRSS_PHY_127,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ6 for slice 0"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ5 for slice 0"
line.long 0x200 "DDRSS_PHY_128,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ7 for slice 0"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ6 for slice 0"
line.long 0x204 "DDRSS_PHY_129,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DM for slice 0"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ7 for slice 0"
line.long 0x208 "DDRSS_PHY_130,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_0,Read DQS slave delay setting for slice 0"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DM for slice 0"
line.long 0x20C "DDRSS_PHY_131,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_0,Write level delay threshold above which will be considered in previous cycle for slice 0"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_0,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_0,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_132,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_0,Force the final write level delay value (that meets the early threshold) to 0 for slice 0" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0,Write level delay threshold below which will add a cycle of write path latency for slice 0"
line.long 0x214 "DDRSS_PHY_133,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_0,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_0,Initial read DQS gate slave delay setting during gate training for slice 0"
line.long 0x218 "DDRSS_PHY_134,"
bitfld.long 0x218 24. "PHY_NTP_PASS_0,Indicates if No-topology training found a passing result for slice 0" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_0,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_0,Initial DQ/DM slave delay setting during write data leveling for slice 0"
line.long 0x21C "DDRSS_PHY_135,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0,Read leveling starting value for the DQS/DQ slave delay settings for slice 0"
line.long 0x220 "DDRSS_PHY_136,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
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hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
line.long 0x224 "DDRSS_PHY_137,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
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hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
line.long 0x228 "DDRSS_PHY_138,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_0,Setting for boost P/N of pad for slice 0"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
newline
hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
line.long 0x22C "DDRSS_PHY_139,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_0,TX_FFE setting for DQS pad for slice 0" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_0,TX_FFE setting for DQ/DM pad for slice 0" "0,1,2,3"
newline
bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_0,Setting for RX ctle P/N of pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4400++0x22F
line.long 0x00 "DDRSS_PHY_256,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_1,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_1,Write data clock bypass mode slave delay setting for slice 1.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_257,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_1,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1,Write DQS bypass mode slave delay setting for slice 1"
line.long 0x08 "DDRSS_PHY_258,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_1,Bypass mode override setting for slice 1" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_1,Two_cycle_preamble for bypass mode for slice 1" "0,1,2,3"
newline
hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1,Read DQS bypass mode slave delay setting for slice 1"
line.long 0x0C "DDRSS_PHY_259,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_260,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_261,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_1,When set a register write will update parameters for all ranks at the same time in slice 1" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_1,Per-rank CS map for slice 1" "0,1,2,3"
newline
bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_262,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_1,For per-rank training indicates which rank's paramters are read/written for slice 1" "0,1"
line.long 0x1C "DDRSS_PHY_263,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1,For LPDDR4 boot frequency write path clock gating disable for slice 1" "0,1,2,3"
newline
bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_1,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_264,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_1,Loopback read only test timeout mechanism enable for slice 1" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_1,Loopback control bits for slice 1"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_1,Loopback control en for slice 1" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_265,"
line.long 0x28 "DDRSS_PHY_266,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_1,Observation register for the auto_timing_margin for slice 1"
line.long 0x2C "DDRSS_PHY_267,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_1,Read Leveling Multi-pattern enable for slice 1" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_1,PRBS7 mask signal for slice 1"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_1,PRBS7 start pattern for slice 1"
line.long 0x30 "DDRSS_PHY_268,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_1,Observation register for best vref value for slice 1"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_1,Data slice initial VREF training step size for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_1,Read Leveling read level windows disable reset for slice 1" "0,1"
line.long 0x34 "DDRSS_PHY_269,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_1,Initiates a snapshot of the internal observation registers for slice 1" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_1,Number of cycles to wait for the DQS gate to close before flagging an error for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1,Read DQS data clock bypass mode slave delay setting for slice 1"
line.long 0x38 "DDRSS_PHY_270,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_1,Indicates the type of DRAM for slice 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_1,Adds a cycle of delay for the slice 1 to match the address slice" "0,1"
newline
hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 1"
line.long 0x3C "DDRSS_PHY_271,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_1,Control the on-the-fly gate adjustment for slice 1" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 1"
line.long 0x40 "DDRSS_PHY_272,"
line.long 0x44 "DDRSS_PHY_273,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_1,Controls the read postamble extension for LPDDR4 for slice 1" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_1,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 1" "0,1"
line.long 0x48 "DDRSS_PHY_274,"
line.long 0x4C "DDRSS_PHY_275,"
line.long 0x50 "DDRSS_PHY_276,"
line.long 0x54 "DDRSS_PHY_277,"
line.long 0x58 "DDRSS_PHY_278,"
line.long 0x5C "DDRSS_PHY_279,"
line.long 0x60 "DDRSS_PHY_280,"
line.long 0x64 "DDRSS_PHY_281,"
line.long 0x68 "DDRSS_PHY_282,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_1,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_1,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_1,Disables automatic reset of the read entry FIFO pointers for slice 1" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_1,Reserved for future use for slice 1" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_283,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_1,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_1,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_1,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_1,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_284,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_1,Observation register for write leveling status for slice 1"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_1,Write leveling algorithm selection for slice 1" "0,1,2,3"
newline
bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_1,Allows the leveling state machine to advance (when in debug mode) for slice 1" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_1,Enables leveling debug mode for slice 1" "0,1"
line.long 0x74 "DDRSS_PHY_285,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_1,For ECC slice should set this register to do DQ bit mask for slice 1"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_286,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_1,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_1,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 1"
line.long 0x7C "DDRSS_PHY_287,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_1,Read leveling algorithm select for slice 1" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_288,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_1,Defines the minimum gap requirment for the LE and TE window for slice 1"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_1,Per-bit mask for read leveling for slice 1"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 1"
line.long 0x84 "DDRSS_PHY_289,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_1,Defines the training patterns to be used during the write data leveling sequence for slice 1" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_290,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_1,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 1" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_1,Select value to map specific information during or post periodic write data leveling for slice 1"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_291,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_1,Per-bit mask for write data leveling for slice 1"
line.long 0x90 "DDRSS_PHY_292,"
line.long 0x94 "DDRSS_PHY_293,"
line.long 0x98 "DDRSS_PHY_294,"
line.long 0x9C "DDRSS_PHY_295,"
line.long 0xA0 "DDRSS_PHY_296,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_1,Control for single pass only No-Topology training for slice 1" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_1,User-defined pattern to be used during write data leveling for slice 1"
line.long 0xA4 "DDRSS_PHY_297,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_1,Threshold Criteria of period threshold after No-Topology training is completed for slice 1"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_1,Threshold Criteria of early threshold after No-Topology training is completed for slice 1"
line.long 0xA8 "DDRSS_PHY_298,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_1,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 1"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_1,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 1"
line.long 0xAC "DDRSS_PHY_299,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_1,Observation register containing read entry FIFO pointers for slice 1"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_1,Manual reset/clear of internal logic for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_1,Indicates if slice 1 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_300,"
line.long 0xB4 "DDRSS_PHY_301,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_1,Observation register containing master delay results for slice 1"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_1,Observation register containing total number of loopback error data for slice 1"
line.long 0xB8 "DDRSS_PHY_302,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 1"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_1,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 1"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS base slave delay encoded value for slice 1"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_1,Observation register containing read DQ slave delay encoded values for slice 1"
line.long 0xBC "DDRSS_PHY_303,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQS base slave delay encoded value for slice 1"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS gate slave delay encoded value for slice 1"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 1"
line.long 0xC0 "DDRSS_PHY_304,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_1,Observation register containing automatic half cycle and cycle shift values for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing write adder slave delay encoded value for slice 1"
newline
hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQ base slave delay encoded value for slice 1"
line.long 0xC4 "DDRSS_PHY_305,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_1,Observation register containing write leveling first hard 1 DQS slave delay for slice 1"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_1,Observation register containing write leveling last hard 0 DQS slave delay for slice 1"
line.long 0xC8 "DDRSS_PHY_306,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_1,Observation register containing write leveling status for slice 1"
line.long 0xCC "DDRSS_PHY_307,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1,Observation register containing gate sample2 slave delay encoded values for slice 1"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1,Observation register containing gate sample1 slave delay encoded values for slice 1"
line.long 0xD0 "DDRSS_PHY_308,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_1,Observation register containing gate training first hard 0 DQS slave delay for slice 1"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_1,Observation register containing write leveling error status for slice 1"
line.long 0xD4 "DDRSS_PHY_309,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_1,Observation register containing gate training last hard 1 DQS slave delay for slice 1"
line.long 0xD8 "DDRSS_PHY_310,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_1,Observation register containing gate training status for slice 1"
line.long 0xDC "DDRSS_PHY_311,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1,Observation register containing read leveling data window trailing edge slave delay setting for slice 1"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1,Observation register containing read leveling data window leading edge slave delay setting for slice 1"
line.long 0xE0 "DDRSS_PHY_312,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1,Observation register containing read leveling number of windows found for slice 1" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_313,"
line.long 0xE8 "DDRSS_PHY_314,"
line.long 0xEC "DDRSS_PHY_315,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_1,Observation register containing write data leveling data window trailing edge slave delay setting for slice 1"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_1,Observation register containing write data leveling data window leading edge slave delay setting for slice 1"
line.long 0xF0 "DDRSS_PHY_316,"
line.long 0xF4 "DDRSS_PHY_317,"
line.long 0xF8 "DDRSS_PHY_318,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_1,DDL mode for slice 1"
line.long 0xFC "DDRSS_PHY_319,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_1,DDL mask for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_320,"
line.long 0x104 "DDRSS_PHY_321,"
line.long 0x108 "DDRSS_PHY_322,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_1,Manual setting of RX Calibration enable for slice 1" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_1,Manual RX Calibration start for slice 1" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_1,LPDDR4 write preamble extension enable for slice 1" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_1,Specify threshold value for PHY init update tracking for slice 1"
line.long 0x10C "DDRSS_PHY_323,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_1,RX Calibration codes for DQ0 for slice 1"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1,Data slice power reduction disable for slice 1" "0,1"
newline
hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_1,RX Calibration state machine wait count for slice 1"
line.long 0x110 "DDRSS_PHY_324,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_1,RX Calibration codes for DQ2 for slice 1"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_1,RX Calibration codes for DQ1 for slice 1"
line.long 0x114 "DDRSS_PHY_325,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_1,RX Calibration codes for DQ4 for slice 1"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_1,RX Calibration codes for DQ3 for slice 1"
line.long 0x118 "DDRSS_PHY_326,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_1,RX Calibration codes for DQ6 for slice 1"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_1,RX Calibration codes for DQ5 for slice 1"
line.long 0x11C "DDRSS_PHY_327,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_1,RX Calibration codes for DQ7 for slice 1"
line.long 0x120 "DDRSS_PHY_328,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_1,RX Calibration codes for DM for slice 1"
line.long 0x124 "DDRSS_PHY_329,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_1,RX Calibration codes for FDBK for slice 1"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_1,RX Calibration codes for DQS for slice 1"
line.long 0x128 "DDRSS_PHY_330,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_1,RX Calibration lock results for slice 1"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_1,RX Calibration results for slice 1"
line.long 0x12C "DDRSS_PHY_331,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_1,Expected C value from RX pad for slice 1" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_1,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_1,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_1,RX CAL disable signal for slice 1 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_332,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_1,Controls RX_BIAS_EN pin for each pad for slice 1"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_1,RX offset calibration mask of all RX pad for slice 1"
line.long 0x134 "DDRSS_PHY_333,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_1,Determines weight of average calculating for slice 1" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_1,Determines timeout number of iteration for slice 1"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_1,Determines number of cycles to wait for each sample for slice 1"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_1,Control to disable toggle during static activity for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_334,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_1,Adjust direction for slice 1" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_1,Duty cycle adjust threshold around the mid-point for slice 1"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_1,Duty cycle adjust sample count for slice 1"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_1,Duty cycle adjust starting value for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_335,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_1,Shutoff gate feedback IO to reduce power for slice 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_1,Rank selection for software based duty cycle correction for slice 1" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_1,Manual trigger for DCC for slice 1" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_1,Calibration polarity for slice 1" "0,1"
line.long 0x140 "DDRSS_PHY_336,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_1,Data slice power reduction disable for slice 1" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1,Data slice DCC and RX_CAL block power reduction disable for slice 1" "0,1"
newline
bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_1,Data slice read path power reduction disable for slice 1" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_1,Data slice slv_dly_control block power reduction disable for slice 1" "0,1"
line.long 0x144 "DDRSS_PHY_337,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_1,Data slice level FSM Error Info for slice 1"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_1,Inject parity error to register interface signals for slice 1"
line.long 0x148 "DDRSS_PHY_338,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1,Data slice level FSM Error Info for slice 1"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_1,Data slice level FSM Error Info Mask for slice 1"
line.long 0x14C "DDRSS_PHY_339,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1,Data slice level training/calibration Error Info for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1,Data slice level training/calibration Error Info Mask for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_1,Data slice level training/calibration Error Info for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_340,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_1,Operation type tsel enables for DQS signals for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_1,Operation type tsel select values for DQ/DM signals for slice 1"
newline
bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_1,Operation type tsel enables for DQ/DM signals for slice 1" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_341,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_1,Data slice initial VREF training start value for slice 1"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_1,2 cycle preamble support for slice 1" "0,1,2,3"
newline
hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_1,Operation type tsel select values for DQS signals for slice 1"
line.long 0x158 "DDRSS_PHY_342,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_1,Step size of WR DQ slave delay during No-Topology training for slice 1"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_1,Enable for No-Topology training for slice 1" "0,1"
newline
bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_1,Data slice vref training enable control for slice 1" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_1,Data slice initial VREF training stop value for slice 1"
line.long 0x15C "DDRSS_PHY_343,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_1,End of WR DQ slave delay in No-Topology training for slice 1"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_1,Starting WR DQ slave delay in No-Topology training for slice 1"
line.long 0x160 "DDRSS_PHY_344,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_1,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 1" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_1,Enable Bit for WR DQ during No-Topology training for slice 1"
line.long 0x164 "DDRSS_PHY_345,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_1,Controls TX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_1,Enable for fast multi-pattern window search for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_346,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_347,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_1,Controls RX_DCD pin for dm pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_348,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_1,Controls PCLK/PARK pin for pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_1,Controls RX_DCD pin for fdbk pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_1,Controls RX_DCD pin for dqs pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_349,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_1,Read DQ1 slave delay setting for slice 1"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_1,Read DQ0 slave delay setting for slice 1"
line.long 0x178 "DDRSS_PHY_350,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_1,Read DQ3 slave delay setting for slice 1"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_1,Read DQ2 slave delay setting for slice 1"
line.long 0x17C "DDRSS_PHY_351,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_1,Read DQ5 slave delay setting for slice 1"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_1,Read DQ4 slave delay setting for slice 1"
line.long 0x180 "DDRSS_PHY_352,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_1,Read DQ7 slave delay setting for slice 1"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_1,Read DQ6 slave delay setting for slice 1"
line.long 0x184 "DDRSS_PHY_353,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_1,Determines DCC CAL clock for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_1,Read DM/DBI slave delay setting for slice 1"
line.long 0x188 "DDRSS_PHY_354,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_1,Start/end timing values for DQS output enable signals for slice 1"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_1,Start/end timing values for DQ/DM write based termination enable and select signals for slice 1"
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hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_1,Start/end timing values for DQ/DM read based termination enable and select signals for slice 1"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_1,Start/end timing values for DQ/DM output enable signals for slice 1"
line.long 0x18C "DDRSS_PHY_355,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_1,Start/end timing values for DQS write based termination enable and select signals for slice 1"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_1,Start/end timing values for DQS read based OE extension for slice 1"
newline
hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_1,Start/end timing values for DQS read based termination enable and select signals for slice 1"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_1,Feedback pad's OPAD and IPAD delay timing for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_356,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_1,Pad VREF control settings for DQ slice 1"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_1,Number of cycles for vref settle after setting is changed for slice 1"
line.long 0x194 "DDRSS_PHY_357,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_1,Start/end timing values for DQS input enable signals for slice 1"
newline
hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_1,Start/end timing values for DQ/DM input enable signals for slice 1"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_1,Enables the per-rank training and read/write timing capabilities for slice 1" "0,1"
line.long 0x198 "DDRSS_PHY_358,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_1,DBI mode for slice 1" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_1,Input enable mode bits for slice 1" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_359,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_1,Incremental step size for master delay line locking algorithm for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_1,Start value for master delay line locking algorithm for slice 1"
newline
bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_1,Master delay line override settings for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_360,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_1,DQS slave delay step size during write leveling for slice 1"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_1,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_1,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 1"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_1,Wait cycles for master delay line locking algorithm for slice 1"
line.long 0x1A4 "DDRSS_PHY_361,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_1,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_1,DQS slave delay step size during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_1,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_1,DQS slave delay fine step size during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_362,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_1,Final backup step delay used in gate training algorithm for slice 1"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_1,Interim backup step delay used in gate training algorithm for slice 1"
line.long 0x1AC "DDRSS_PHY_363,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_1,DQS slave delay step size during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_1,Support the toggle read preamble for LPDDR4 for slice 1" "0,1"
newline
bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_1,Defines the step granularity for the logic to use once an edge is found for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_1,DQ slave delay step size during write data leveling for slice 1"
line.long 0x1B0 "DDRSS_PHY_364,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_1,The maximun rdlvl slave delay search window for read eye training for slice 1"
line.long 0x1B4 "DDRSS_PHY_365,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_1,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 1" "0,1"
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hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1"
line.long 0x1B8 "DDRSS_PHY_366,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_1,Disable duty cycle adjust at initialization for slice 1" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_1,Write path clock gating timing for slice 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_1,Write path clock gating disable for slice 1" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_367,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_1,Initial value of write DQ slave delay for slice 1"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_1,Initial value of write DQS slave delay for slice 1"
line.long 0x1C0 "DDRSS_PHY_368,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1,Clock measurement cell threshold offset for differential signals for slice 1"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_1,Clock measurement cell threshold offset for single ended signals for slice 1"
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bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_1,Enable duty cycle adjust during write DQ training for slice 1" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_1,Enable duty cycle adjust during write leveling for slice 1" "0,1"
line.long 0x1C4 "DDRSS_PHY_369,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_1,Number of cycles that the dfi_rddata_en signal is early for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_1,Data slice training step definition using phy_meas_dly_step_value for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_1,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 1"
line.long 0x1C8 "DDRSS_PHY_370,"
line.long 0x1CC "DDRSS_PHY_371,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_1,DQ/DM bit swizzling 1 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_372,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_1,Write clock slave delay setting for DQ1 for slice 1"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_1,Write clock slave delay setting for DQ0 for slice 1"
line.long 0x1D4 "DDRSS_PHY_373,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_1,Write clock slave delay setting for DQ3 for slice 1"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_1,Write clock slave delay setting for DQ2 for slice 1"
line.long 0x1D8 "DDRSS_PHY_374,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_1,Write clock slave delay setting for DQ5 for slice 1"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_1,Write clock slave delay setting for DQ4 for slice 1"
line.long 0x1DC "DDRSS_PHY_375,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_1,Write clock slave delay setting for DQ7 for slice 1"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_1,Write clock slave delay setting for DQ6 for slice 1"
line.long 0x1E0 "DDRSS_PHY_376,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_1,Write clock slave delay setting for DQS for slice 1"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_1,Write clock slave delay setting for DM for slice 1"
line.long 0x1E4 "DDRSS_PHY_377,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ0 for slice 1"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_1,Write level threshold adjust value based on those thresholds for DQS for slice 1" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_378,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ1 for slice 1"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ0 for slice 1"
line.long 0x1EC "DDRSS_PHY_379,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ2 for slice 1"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ1 for slice 1"
line.long 0x1F0 "DDRSS_PHY_380,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ3 for slice 1"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ2 for slice 1"
line.long 0x1F4 "DDRSS_PHY_381,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ4 for slice 1"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ3 for slice 1"
line.long 0x1F8 "DDRSS_PHY_382,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ5 for slice 1"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ4 for slice 1"
line.long 0x1FC "DDRSS_PHY_383,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ6 for slice 1"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ5 for slice 1"
line.long 0x200 "DDRSS_PHY_384,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ7 for slice 1"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ6 for slice 1"
line.long 0x204 "DDRSS_PHY_385,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DM for slice 1"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ7 for slice 1"
line.long 0x208 "DDRSS_PHY_386,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_1,Read DQS slave delay setting for slice 1"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DM for slice 1"
line.long 0x20C "DDRSS_PHY_387,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_1,Write level delay threshold above which will be considered in previous cycle for slice 1"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_1,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_1,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_388,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_1,Force the final write level delay value (that meets the early threshold) to 0 for slice 1" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1,Write level delay threshold below which will add a cycle of write path latency for slice 1"
line.long 0x214 "DDRSS_PHY_389,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_1,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_1,Initial read DQS gate slave delay setting during gate training for slice 1"
line.long 0x218 "DDRSS_PHY_390,"
bitfld.long 0x218 24. "PHY_NTP_PASS_1,Indicates if No-topology training found a passing result for slice 1" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_1,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_1,Initial DQ/DM slave delay setting during write data leveling for slice 1"
line.long 0x21C "DDRSS_PHY_391,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1,Read leveling starting value for the DQS/DQ slave delay settings for slice 1"
line.long 0x220 "DDRSS_PHY_392,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
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hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
line.long 0x224 "DDRSS_PHY_393,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
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hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
line.long 0x228 "DDRSS_PHY_394,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_1,Setting for boost P/N of pad for slice 1"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
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hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
line.long 0x22C "DDRSS_PHY_395,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_1,TX_FFE setting for DQS pad for slice 1" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_1,TX_FFE setting for DQ/DM pad for slice 1" "0,1,2,3"
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bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_1,Setting for RX ctle P/N of pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4800++0x22F
line.long 0x00 "DDRSS_PHY_512,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_2,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_2,Write data clock bypass mode slave delay setting for slice 2.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_513,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_2,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2,Write DQS bypass mode slave delay setting for slice 2"
line.long 0x08 "DDRSS_PHY_514,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_2,Bypass mode override setting for slice 2" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_2,Two_cycle_preamble for bypass mode for slice 2" "0,1,2,3"
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hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2,Read DQS bypass mode slave delay setting for slice 2"
line.long 0x0C "DDRSS_PHY_515,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_516,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_517,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_2,When set a register write will update parameters for all ranks at the same time in slice 2" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_2,Per-rank CS map for slice 2" "0,1,2,3"
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bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_518,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_2,For per-rank training indicates which rank's paramters are read/written for slice 2" "0,1"
line.long 0x1C "DDRSS_PHY_519,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2,For LPDDR4 boot frequency write path clock gating disable for slice 2" "0,1,2,3"
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bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_2,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_520,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_2,Loopback read only test timeout mechanism enable for slice 2" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_2,Loopback control bits for slice 2"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_2,Loopback control en for slice 2" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_521,"
line.long 0x28 "DDRSS_PHY_522,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_2,Observation register for the auto_timing_margin for slice 2"
line.long 0x2C "DDRSS_PHY_523,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_2,Read Leveling Multi-pattern enable for slice 2" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_2,PRBS7 mask signal for slice 2"
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hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_2,PRBS7 start pattern for slice 2"
line.long 0x30 "DDRSS_PHY_524,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_2,Observation register for best vref value for slice 2"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_2,Data slice initial VREF training step size for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_2,Read Leveling read level windows disable reset for slice 2" "0,1"
line.long 0x34 "DDRSS_PHY_525,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_2,Initiates a snapshot of the internal observation registers for slice 2" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_2,Number of cycles to wait for the DQS gate to close before flagging an error for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2,Read DQS data clock bypass mode slave delay setting for slice 2"
line.long 0x38 "DDRSS_PHY_526,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_2,Indicates the type of DRAM for slice 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_2,Adds a cycle of delay for the slice 2 to match the address slice" "0,1"
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hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_2,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 2"
line.long 0x3C "DDRSS_PHY_527,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_2,Control the on-the-fly gate adjustment for slice 2" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_2,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 2"
line.long 0x40 "DDRSS_PHY_528,"
line.long 0x44 "DDRSS_PHY_529,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_2,Controls the read postamble extension for LPDDR4 for slice 2" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_2,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 2" "0,1"
line.long 0x48 "DDRSS_PHY_530,"
line.long 0x4C "DDRSS_PHY_531,"
line.long 0x50 "DDRSS_PHY_532,"
line.long 0x54 "DDRSS_PHY_533,"
line.long 0x58 "DDRSS_PHY_534,"
line.long 0x5C "DDRSS_PHY_535,"
line.long 0x60 "DDRSS_PHY_536,"
line.long 0x64 "DDRSS_PHY_537,"
line.long 0x68 "DDRSS_PHY_538,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_2,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_2,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_2,Disables automatic reset of the read entry FIFO pointers for slice 2" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_2,Reserved for future use for slice 2" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_539,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_2,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_2,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_2,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_2,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_540,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_2,Observation register for write leveling status for slice 2"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_2,Write leveling algorithm selection for slice 2" "0,1,2,3"
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bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_2,Allows the leveling state machine to advance (when in debug mode) for slice 2" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_2,Enables leveling debug mode for slice 2" "0,1"
line.long 0x74 "DDRSS_PHY_541,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_2,For ECC slice should set this register to do DQ bit mask for slice 2"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_542,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_2,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_2,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 2"
line.long 0x7C "DDRSS_PHY_543,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_2,Read leveling algorithm select for slice 2" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_544,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_2,Defines the write/read burst length in bytes during the write data leveling sequence for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_2,Defines the minimum gap requirment for the LE and TE window for slice 2"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_2,Per-bit mask for read leveling for slice 2"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 2"
line.long 0x84 "DDRSS_PHY_545,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2,Defines the write/read burst length in bytes during the write data leveling sequence for slice 2"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_2,Defines the training patterns to be used during the write data leveling sequence for slice 2" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_546,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_2,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 2" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_2,Select value to map specific information during or post periodic write data leveling for slice 2"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_547,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_2,Per-bit mask for write data leveling for slice 2"
line.long 0x90 "DDRSS_PHY_548,"
line.long 0x94 "DDRSS_PHY_549,"
line.long 0x98 "DDRSS_PHY_550,"
line.long 0x9C "DDRSS_PHY_551,"
line.long 0xA0 "DDRSS_PHY_552,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_2,Control for single pass only No-Topology training for slice 2" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_2,User-defined pattern to be used during write data leveling for slice 2"
line.long 0xA4 "DDRSS_PHY_553,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_2,Threshold Criteria of period threshold after No-Topology training is completed for slice 2"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_2,Threshold Criteria of early threshold after No-Topology training is completed for slice 2"
line.long 0xA8 "DDRSS_PHY_554,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_2,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 2"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_2,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 2"
line.long 0xAC "DDRSS_PHY_555,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_2,Observation register containing read entry FIFO pointers for slice 2"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_2,Manual reset/clear of internal logic for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_2,Indicates if slice 2 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_556,"
line.long 0xB4 "DDRSS_PHY_557,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_2,Observation register containing master delay results for slice 2"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_2,Observation register containing total number of loopback error data for slice 2"
line.long 0xB8 "DDRSS_PHY_558,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 2"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_2,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 2"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2,Observation register containing read DQS base slave delay encoded value for slice 2"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_2,Observation register containing read DQ slave delay encoded values for slice 2"
line.long 0xBC "DDRSS_PHY_559,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2,Observation register containing write DQS base slave delay encoded value for slice 2"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2,Observation register containing read DQS gate slave delay encoded value for slice 2"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 2"
line.long 0xC0 "DDRSS_PHY_560,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_2,Observation register containing automatic half cycle and cycle shift values for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing write adder slave delay encoded value for slice 2"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2,Observation register containing write DQ base slave delay encoded value for slice 2"
line.long 0xC4 "DDRSS_PHY_561,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_2,Observation register containing write leveling first hard 1 DQS slave delay for slice 2"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_2,Observation register containing write leveling last hard 0 DQS slave delay for slice 2"
line.long 0xC8 "DDRSS_PHY_562,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_2,Observation register containing write leveling status for slice 2"
line.long 0xCC "DDRSS_PHY_563,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2,Observation register containing gate sample2 slave delay encoded values for slice 2"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2,Observation register containing gate sample1 slave delay encoded values for slice 2"
line.long 0xD0 "DDRSS_PHY_564,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_2,Observation register containing gate training first hard 0 DQS slave delay for slice 2"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_2,Observation register containing write leveling error status for slice 2"
line.long 0xD4 "DDRSS_PHY_565,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_2,Observation register containing gate training last hard 1 DQS slave delay for slice 2"
line.long 0xD8 "DDRSS_PHY_566,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_2,Observation register containing gate training status for slice 2"
line.long 0xDC "DDRSS_PHY_567,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2,Observation register containing read leveling data window trailing edge slave delay setting for slice 2"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2,Observation register containing read leveling data window leading edge slave delay setting for slice 2"
line.long 0xE0 "DDRSS_PHY_568,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2,Observation register containing read leveling number of windows found for slice 2" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_569,"
line.long 0xE8 "DDRSS_PHY_570,"
line.long 0xEC "DDRSS_PHY_571,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_2,Observation register containing write data leveling data window trailing edge slave delay setting for slice 2"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_2,Observation register containing write data leveling data window leading edge slave delay setting for slice 2"
line.long 0xF0 "DDRSS_PHY_572,"
line.long 0xF4 "DDRSS_PHY_573,"
line.long 0xF8 "DDRSS_PHY_574,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_2,DDL mode for slice 2"
line.long 0xFC "DDRSS_PHY_575,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_2,DDL mask for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_576,"
line.long 0x104 "DDRSS_PHY_577,"
line.long 0x108 "DDRSS_PHY_578,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_2,Manual setting of RX Calibration enable for slice 2" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_2,Manual RX Calibration start for slice 2" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_2,LPDDR4 write preamble extension enable for slice 2" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_2,Specify threshold value for PHY init update tracking for slice 2"
line.long 0x10C "DDRSS_PHY_579,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_2,RX Calibration codes for DQ0 for slice 2"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2,Data slice power reduction disable for slice 2" "0,1"
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hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_2,RX Calibration state machine wait count for slice 2"
line.long 0x110 "DDRSS_PHY_580,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_2,RX Calibration codes for DQ2 for slice 2"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_2,RX Calibration codes for DQ1 for slice 2"
line.long 0x114 "DDRSS_PHY_581,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_2,RX Calibration codes for DQ4 for slice 2"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_2,RX Calibration codes for DQ3 for slice 2"
line.long 0x118 "DDRSS_PHY_582,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_2,RX Calibration codes for DQ6 for slice 2"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_2,RX Calibration codes for DQ5 for slice 2"
line.long 0x11C "DDRSS_PHY_583,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_2,RX Calibration codes for DQ7 for slice 2"
line.long 0x120 "DDRSS_PHY_584,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_2,RX Calibration codes for DM for slice 2"
line.long 0x124 "DDRSS_PHY_585,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_2,RX Calibration codes for FDBK for slice 2"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_2,RX Calibration codes for DQS for slice 2"
line.long 0x128 "DDRSS_PHY_586,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_2,RX Calibration lock results for slice 2"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_2,RX Calibration results for slice 2"
line.long 0x12C "DDRSS_PHY_587,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_2,Expected C value from RX pad for slice 2" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_2,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_2,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_2,RX CAL disable signal for slice 2 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_588,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_2,Controls RX_BIAS_EN pin for each pad for slice 2"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_2,RX offset calibration mask of all RX pad for slice 2"
line.long 0x134 "DDRSS_PHY_589,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_2,Determines weight of average calculating for slice 2" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_2,Determines timeout number of iteration for slice 2"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_2,Determines number of cycles to wait for each sample for slice 2"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_2,Control to disable toggle during static activity for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_590,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_2,Adjust direction for slice 2" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_2,Duty cycle adjust threshold around the mid-point for slice 2"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_2,Duty cycle adjust sample count for slice 2"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_2,Duty cycle adjust starting value for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_591,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_2,Shutoff gate feedback IO to reduce power for slice 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_2,Rank selection for software based duty cycle correction for slice 2" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_2,Manual trigger for DCC for slice 2" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_2,Calibration polarity for slice 2" "0,1"
line.long 0x140 "DDRSS_PHY_592,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_2,Data slice power reduction disable for slice 2" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2,Data slice DCC and RX_CAL block power reduction disable for slice 2" "0,1"
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bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_2,Data slice read path power reduction disable for slice 2" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_2,Data slice slv_dly_control block power reduction disable for slice 2" "0,1"
line.long 0x144 "DDRSS_PHY_593,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_2,Data slice level FSM Error Info for slice 2"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_2,Inject parity error to register interface signals for slice 2"
line.long 0x148 "DDRSS_PHY_594,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2,Data slice level FSM Error Info for slice 2"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_2,Data slice level FSM Error Info Mask for slice 2"
line.long 0x14C "DDRSS_PHY_595,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2,Data slice level training/calibration Error Info for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2,Data slice level training/calibration Error Info Mask for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_2,Data slice level training/calibration Error Info for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_596,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_2,Operation type tsel enables for DQS signals for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_2,Operation type tsel select values for DQ/DM signals for slice 2"
newline
bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_2,Operation type tsel enables for DQ/DM signals for slice 2" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_597,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_2,Data slice initial VREF training start value for slice 2"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_2,2 cycle preamble support for slice 2" "0,1,2,3"
newline
hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_2,Operation type tsel select values for DQS signals for slice 2"
line.long 0x158 "DDRSS_PHY_598,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_2,Step size of WR DQ slave delay during No-Topology training for slice 2"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_2,Enable for No-Topology training for slice 2" "0,1"
newline
bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_2,Data slice vref training enable control for slice 2" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_2,Data slice initial VREF training stop value for slice 2"
line.long 0x15C "DDRSS_PHY_599,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_2,End of WR DQ slave delay in No-Topology training for slice 2"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_2,Starting WR DQ slave delay in No-Topology training for slice 2"
line.long 0x160 "DDRSS_PHY_600,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_2,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 2" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_2,Minimum data valid window across DQs and ranks for slice 2"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_2,Enable Bit for WR DQ during No-Topology training for slice 2"
line.long 0x164 "DDRSS_PHY_601,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_2,Controls TX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_2,Enable for fast multi-pattern window search for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_2,Peridic training start point offset for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_602,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_603,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_2,Controls RX_DCD pin for dm pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_604,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_2,Controls PCLK/PARK pin for pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_2,Controls RX_DCD pin for fdbk pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_2,Controls RX_DCD pin for dqs pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_605,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_2,Read DQ1 slave delay setting for slice 2"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_2,Read DQ0 slave delay setting for slice 2"
line.long 0x178 "DDRSS_PHY_606,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_2,Read DQ3 slave delay setting for slice 2"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_2,Read DQ2 slave delay setting for slice 2"
line.long 0x17C "DDRSS_PHY_607,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_2,Read DQ5 slave delay setting for slice 2"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_2,Read DQ4 slave delay setting for slice 2"
line.long 0x180 "DDRSS_PHY_608,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_2,Read DQ7 slave delay setting for slice 2"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_2,Read DQ6 slave delay setting for slice 2"
line.long 0x184 "DDRSS_PHY_609,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_2,Determines DCC CAL clock for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_2,Read DM/DBI slave delay setting for slice 2"
line.long 0x188 "DDRSS_PHY_610,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_2,Start/end timing values for DQS output enable signals for slice 2"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_2,Start/end timing values for DQ/DM write based termination enable and select signals for slice 2"
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hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_2,Start/end timing values for DQ/DM read based termination enable and select signals for slice 2"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_2,Start/end timing values for DQ/DM output enable signals for slice 2"
line.long 0x18C "DDRSS_PHY_611,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_2,Start/end timing values for DQS write based termination enable and select signals for slice 2"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_2,Start/end timing values for DQS read based OE extension for slice 2"
newline
hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_2,Start/end timing values for DQS read based termination enable and select signals for slice 2"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_2,Feedback pad's OPAD and IPAD delay timing for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_612,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_2,Pad VREF control settings for DQ slice 2"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_2,Number of cycles for vref settle after setting is changed for slice 2"
line.long 0x194 "DDRSS_PHY_613,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_2,Start/end timing values for DQS input enable signals for slice 2"
newline
hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_2,Start/end timing values for DQ/DM input enable signals for slice 2"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_2,Enables the per-rank training and read/write timing capabilities for slice 2" "0,1"
line.long 0x198 "DDRSS_PHY_614,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_2,DBI mode for slice 2" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_2,Input enable mode bits for slice 2" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_615,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_2,Incremental step size for master delay line locking algorithm for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_2,Start value for master delay line locking algorithm for slice 2"
newline
bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_2,Master delay line override settings for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_616,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_2,DQS slave delay step size during write leveling for slice 2"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_2,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_2,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 2"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_2,Wait cycles for master delay line locking algorithm for slice 2"
line.long 0x1A4 "DDRSS_PHY_617,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_2,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_2,DQS slave delay step size during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_2,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_2,DQS slave delay fine step size during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_618,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_2,Final backup step delay used in gate training algorithm for slice 2"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_2,Interim backup step delay used in gate training algorithm for slice 2"
line.long 0x1AC "DDRSS_PHY_619,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_2,DQS slave delay step size during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_2,Support the toggle read preamble for LPDDR4 for slice 2" "0,1"
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bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_2,Defines the step granularity for the logic to use once an edge is found for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_2,DQ slave delay step size during write data leveling for slice 2"
line.long 0x1B0 "DDRSS_PHY_620,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_2,The maximun rdlvl slave delay search window for read eye training for slice 2"
line.long 0x1B4 "DDRSS_PHY_621,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_2,Peridic training start point offset for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_2,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 2" "0,1"
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hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_2,Minimum data valid window across DQs and ranks for slice 2"
line.long 0x1B8 "DDRSS_PHY_622,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_2,Disable duty cycle adjust at initialization for slice 2" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_2,Write path clock gating timing for slice 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_2,Write path clock gating disable for slice 2" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_623,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_2,Initial value of write DQ slave delay for slice 2"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_2,Initial value of write DQS slave delay for slice 2"
line.long 0x1C0 "DDRSS_PHY_624,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2,Clock measurement cell threshold offset for differential signals for slice 2"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_2,Clock measurement cell threshold offset for single ended signals for slice 2"
newline
bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_2,Enable duty cycle adjust during write DQ training for slice 2" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_2,Enable duty cycle adjust during write leveling for slice 2" "0,1"
line.long 0x1C4 "DDRSS_PHY_625,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_2,Number of cycles that the dfi_rddata_en signal is early for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_2,Data slice training step definition using phy_meas_dly_step_value for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_2,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 2"
line.long 0x1C8 "DDRSS_PHY_626,"
line.long 0x1CC "DDRSS_PHY_627,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_2,DQ/DM bit swizzling 1 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_628,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_2,Write clock slave delay setting for DQ1 for slice 2"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_2,Write clock slave delay setting for DQ0 for slice 2"
line.long 0x1D4 "DDRSS_PHY_629,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_2,Write clock slave delay setting for DQ3 for slice 2"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_2,Write clock slave delay setting for DQ2 for slice 2"
line.long 0x1D8 "DDRSS_PHY_630,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_2,Write clock slave delay setting for DQ5 for slice 2"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_2,Write clock slave delay setting for DQ4 for slice 2"
line.long 0x1DC "DDRSS_PHY_631,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_2,Write clock slave delay setting for DQ7 for slice 2"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_2,Write clock slave delay setting for DQ6 for slice 2"
line.long 0x1E0 "DDRSS_PHY_632,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_2,Write clock slave delay setting for DQS for slice 2"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_2,Write clock slave delay setting for DM for slice 2"
line.long 0x1E4 "DDRSS_PHY_633,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ0 for slice 2"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_2,Write level threshold adjust value based on those thresholds for DQS for slice 2" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_634,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ1 for slice 2"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ0 for slice 2"
line.long 0x1EC "DDRSS_PHY_635,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ2 for slice 2"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ1 for slice 2"
line.long 0x1F0 "DDRSS_PHY_636,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ3 for slice 2"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ2 for slice 2"
line.long 0x1F4 "DDRSS_PHY_637,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ4 for slice 2"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ3 for slice 2"
line.long 0x1F8 "DDRSS_PHY_638,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ5 for slice 2"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ4 for slice 2"
line.long 0x1FC "DDRSS_PHY_639,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ6 for slice 2"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ5 for slice 2"
line.long 0x200 "DDRSS_PHY_640,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ7 for slice 2"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ6 for slice 2"
line.long 0x204 "DDRSS_PHY_641,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DM for slice 2"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ7 for slice 2"
line.long 0x208 "DDRSS_PHY_642,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_2,Read DQS slave delay setting for slice 2"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DM for slice 2"
line.long 0x20C "DDRSS_PHY_643,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_2,Write level delay threshold above which will be considered in previous cycle for slice 2"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_2,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_2,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_644,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_2,Force the final write level delay value (that meets the early threshold) to 0 for slice 2" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2,Write level delay threshold below which will add a cycle of write path latency for slice 2"
line.long 0x214 "DDRSS_PHY_645,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_2,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_2,Initial read DQS gate slave delay setting during gate training for slice 2"
line.long 0x218 "DDRSS_PHY_646,"
bitfld.long 0x218 24. "PHY_NTP_PASS_2,Indicates if No-topology training found a passing result for slice 2" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_2,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_2,Initial DQ/DM slave delay setting during write data leveling for slice 2"
line.long 0x21C "DDRSS_PHY_647,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2,Read leveling starting value for the DQS/DQ slave delay settings for slice 2"
line.long 0x220 "DDRSS_PHY_648,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
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hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
line.long 0x224 "DDRSS_PHY_649,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
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hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
line.long 0x228 "DDRSS_PHY_650,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_2,Setting for boost P/N of pad for slice 2"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
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hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
line.long 0x22C "DDRSS_PHY_651,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_2,TX_FFE setting for DQS pad for slice 2" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_2,TX_FFE setting for DQ/DM pad for slice 2" "0,1,2,3"
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bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_2,Setting for RX ctle P/N of pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4C00++0x22F
line.long 0x00 "DDRSS_PHY_768,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_3,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_3,Write data clock bypass mode slave delay setting for slice 3.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_769,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_3,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3,Write DQS bypass mode slave delay setting for slice 3"
line.long 0x08 "DDRSS_PHY_770,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_3,Bypass mode override setting for slice 3" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_3,Two_cycle_preamble for bypass mode for slice 3" "0,1,2,3"
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hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3,Read DQS bypass mode slave delay setting for slice 3"
line.long 0x0C "DDRSS_PHY_771,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_772,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_773,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_3,When set a register write will update parameters for all ranks at the same time in slice 3" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_3,Per-rank CS map for slice 3" "0,1,2,3"
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bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_774,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_3,For per-rank training indicates which rank's paramters are read/written for slice 3" "0,1"
line.long 0x1C "DDRSS_PHY_775,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3,For LPDDR4 boot frequency write path clock gating disable for slice 3" "0,1,2,3"
newline
bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_3,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_776,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_3,Loopback read only test timeout mechanism enable for slice 3" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_3,Loopback control bits for slice 3"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_3,Loopback control en for slice 3" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_777,"
line.long 0x28 "DDRSS_PHY_778,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_3,Observation register for the auto_timing_margin for slice 3"
line.long 0x2C "DDRSS_PHY_779,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_3,Read Leveling Multi-pattern enable for slice 3" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_3,PRBS7 mask signal for slice 3"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_3,PRBS7 start pattern for slice 3"
line.long 0x30 "DDRSS_PHY_780,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_3,Observation register for best vref value for slice 3"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_3,Data slice initial VREF training step size for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_3,Read Leveling read level windows disable reset for slice 3" "0,1"
line.long 0x34 "DDRSS_PHY_781,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_3,Initiates a snapshot of the internal observation registers for slice 3" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_3,Number of cycles to wait for the DQS gate to close before flagging an error for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3,Read DQS data clock bypass mode slave delay setting for slice 3"
line.long 0x38 "DDRSS_PHY_782,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_3,Indicates the type of DRAM for slice 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_3,Adds a cycle of delay for the slice 3 to match the address slice" "0,1"
newline
hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_3,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 3"
line.long 0x3C "DDRSS_PHY_783,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_3,Control the on-the-fly gate adjustment for slice 3" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_3,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 3"
line.long 0x40 "DDRSS_PHY_784,"
line.long 0x44 "DDRSS_PHY_785,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_3,Controls the read postamble extension for LPDDR4 for slice 3" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_3,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 3" "0,1"
line.long 0x48 "DDRSS_PHY_786,"
line.long 0x4C "DDRSS_PHY_787,"
line.long 0x50 "DDRSS_PHY_788,"
line.long 0x54 "DDRSS_PHY_789,"
line.long 0x58 "DDRSS_PHY_790,"
line.long 0x5C "DDRSS_PHY_791,"
line.long 0x60 "DDRSS_PHY_792,"
line.long 0x64 "DDRSS_PHY_793,"
line.long 0x68 "DDRSS_PHY_794,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_3,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_3,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_3,Disables automatic reset of the read entry FIFO pointers for slice 3" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_3,Reserved for future use for slice 3" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_795,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_3,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_3,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_3,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_3,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_796,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_3,Observation register for write leveling status for slice 3"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_3,Write leveling algorithm selection for slice 3" "0,1,2,3"
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bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_3,Allows the leveling state machine to advance (when in debug mode) for slice 3" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_3,Enables leveling debug mode for slice 3" "0,1"
line.long 0x74 "DDRSS_PHY_797,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_3,For ECC slice should set this register to do DQ bit mask for slice 3"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_798,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_3,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_3,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 3"
line.long 0x7C "DDRSS_PHY_799,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_3,Read leveling algorithm select for slice 3" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_800,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_3,Defines the write/read burst length in bytes during the write data leveling sequence for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_3,Defines the minimum gap requirment for the LE and TE window for slice 3"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_3,Per-bit mask for read leveling for slice 3"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 3"
line.long 0x84 "DDRSS_PHY_801,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3,Defines the write/read burst length in bytes during the write data leveling sequence for slice 3"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_3,Defines the training patterns to be used during the write data leveling sequence for slice 3" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_802,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_3,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 3" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_3,Select value to map specific information during or post periodic write data leveling for slice 3"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_803,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_3,Per-bit mask for write data leveling for slice 3"
line.long 0x90 "DDRSS_PHY_804,"
line.long 0x94 "DDRSS_PHY_805,"
line.long 0x98 "DDRSS_PHY_806,"
line.long 0x9C "DDRSS_PHY_807,"
line.long 0xA0 "DDRSS_PHY_808,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_3,Control for single pass only No-Topology training for slice 3" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_3,User-defined pattern to be used during write data leveling for slice 3"
line.long 0xA4 "DDRSS_PHY_809,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_3,Threshold Criteria of period threshold after No-Topology training is completed for slice 3"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_3,Threshold Criteria of early threshold after No-Topology training is completed for slice 3"
line.long 0xA8 "DDRSS_PHY_810,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_3,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 3"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_3,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 3"
line.long 0xAC "DDRSS_PHY_811,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_3,Observation register containing read entry FIFO pointers for slice 3"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_3,Manual reset/clear of internal logic for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_3,Indicates if slice 3 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_812,"
line.long 0xB4 "DDRSS_PHY_813,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_3,Observation register containing master delay results for slice 3"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_3,Observation register containing total number of loopback error data for slice 3"
line.long 0xB8 "DDRSS_PHY_814,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 3"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_3,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 3"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3,Observation register containing read DQS base slave delay encoded value for slice 3"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_3,Observation register containing read DQ slave delay encoded values for slice 3"
line.long 0xBC "DDRSS_PHY_815,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3,Observation register containing write DQS base slave delay encoded value for slice 3"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3,Observation register containing read DQS gate slave delay encoded value for slice 3"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 3"
line.long 0xC0 "DDRSS_PHY_816,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_3,Observation register containing automatic half cycle and cycle shift values for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing write adder slave delay encoded value for slice 3"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3,Observation register containing write DQ base slave delay encoded value for slice 3"
line.long 0xC4 "DDRSS_PHY_817,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_3,Observation register containing write leveling first hard 1 DQS slave delay for slice 3"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_3,Observation register containing write leveling last hard 0 DQS slave delay for slice 3"
line.long 0xC8 "DDRSS_PHY_818,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_3,Observation register containing write leveling status for slice 3"
line.long 0xCC "DDRSS_PHY_819,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3,Observation register containing gate sample2 slave delay encoded values for slice 3"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3,Observation register containing gate sample1 slave delay encoded values for slice 3"
line.long 0xD0 "DDRSS_PHY_820,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_3,Observation register containing gate training first hard 0 DQS slave delay for slice 3"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_3,Observation register containing write leveling error status for slice 3"
line.long 0xD4 "DDRSS_PHY_821,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_3,Observation register containing gate training last hard 1 DQS slave delay for slice 3"
line.long 0xD8 "DDRSS_PHY_822,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_3,Observation register containing gate training status for slice 3"
line.long 0xDC "DDRSS_PHY_823,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3,Observation register containing read leveling data window trailing edge slave delay setting for slice 3"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3,Observation register containing read leveling data window leading edge slave delay setting for slice 3"
line.long 0xE0 "DDRSS_PHY_824,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3,Observation register containing read leveling number of windows found for slice 3" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_825,"
line.long 0xE8 "DDRSS_PHY_826,"
line.long 0xEC "DDRSS_PHY_827,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_3,Observation register containing write data leveling data window trailing edge slave delay setting for slice 3"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_3,Observation register containing write data leveling data window leading edge slave delay setting for slice 3"
line.long 0xF0 "DDRSS_PHY_828,"
line.long 0xF4 "DDRSS_PHY_829,"
line.long 0xF8 "DDRSS_PHY_830,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_3,DDL mode for slice 3"
line.long 0xFC "DDRSS_PHY_831,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_3,DDL mask for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_832,"
line.long 0x104 "DDRSS_PHY_833,"
line.long 0x108 "DDRSS_PHY_834,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_3,Manual setting of RX Calibration enable for slice 3" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_3,Manual RX Calibration start for slice 3" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_3,LPDDR4 write preamble extension enable for slice 3" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_3,Specify threshold value for PHY init update tracking for slice 3"
line.long 0x10C "DDRSS_PHY_835,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_3,RX Calibration codes for DQ0 for slice 3"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3,Data slice power reduction disable for slice 3" "0,1"
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hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_3,RX Calibration state machine wait count for slice 3"
line.long 0x110 "DDRSS_PHY_836,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_3,RX Calibration codes for DQ2 for slice 3"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_3,RX Calibration codes for DQ1 for slice 3"
line.long 0x114 "DDRSS_PHY_837,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_3,RX Calibration codes for DQ4 for slice 3"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_3,RX Calibration codes for DQ3 for slice 3"
line.long 0x118 "DDRSS_PHY_838,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_3,RX Calibration codes for DQ6 for slice 3"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_3,RX Calibration codes for DQ5 for slice 3"
line.long 0x11C "DDRSS_PHY_839,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_3,RX Calibration codes for DQ7 for slice 3"
line.long 0x120 "DDRSS_PHY_840,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_3,RX Calibration codes for DM for slice 3"
line.long 0x124 "DDRSS_PHY_841,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_3,RX Calibration codes for FDBK for slice 3"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_3,RX Calibration codes for DQS for slice 3"
line.long 0x128 "DDRSS_PHY_842,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_3,RX Calibration lock results for slice 3"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_3,RX Calibration results for slice 3"
line.long 0x12C "DDRSS_PHY_843,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_3,Expected C value from RX pad for slice 3" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_3,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_3,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_3,RX CAL disable signal for slice 3 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_844,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_3,Controls RX_BIAS_EN pin for each pad for slice 3"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_3,RX offset calibration mask of all RX pad for slice 3"
line.long 0x134 "DDRSS_PHY_845,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_3,Determines weight of average calculating for slice 3" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_3,Determines timeout number of iteration for slice 3"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_3,Determines number of cycles to wait for each sample for slice 3"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_3,Control to disable toggle during static activity for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_846,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_3,Adjust direction for slice 3" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_3,Duty cycle adjust threshold around the mid-point for slice 3"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_3,Duty cycle adjust sample count for slice 3"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_3,Duty cycle adjust starting value for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_847,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_3,Shutoff gate feedback IO to reduce power for slice 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_3,Rank selection for software based duty cycle correction for slice 3" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_3,Manual trigger for DCC for slice 3" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_3,Calibration polarity for slice 3" "0,1"
line.long 0x140 "DDRSS_PHY_848,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_3,Data slice power reduction disable for slice 3" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3,Data slice DCC and RX_CAL block power reduction disable for slice 3" "0,1"
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bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_3,Data slice read path power reduction disable for slice 3" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_3,Data slice slv_dly_control block power reduction disable for slice 3" "0,1"
line.long 0x144 "DDRSS_PHY_849,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_3,Data slice level FSM Error Info for slice 3"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_3,Inject parity error to register interface signals for slice 3"
line.long 0x148 "DDRSS_PHY_850,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3,Data slice level FSM Error Info for slice 3"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_3,Data slice level FSM Error Info Mask for slice 3"
line.long 0x14C "DDRSS_PHY_851,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3,Data slice level training/calibration Error Info for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3,Data slice level training/calibration Error Info Mask for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_3,Data slice level training/calibration Error Info for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_852,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_3,Operation type tsel enables for DQS signals for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_3,Operation type tsel select values for DQ/DM signals for slice 3"
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bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_3,Operation type tsel enables for DQ/DM signals for slice 3" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_853,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_3,Data slice initial VREF training start value for slice 3"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_3,2 cycle preamble support for slice 3" "0,1,2,3"
newline
hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_3,Operation type tsel select values for DQS signals for slice 3"
line.long 0x158 "DDRSS_PHY_854,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_3,Step size of WR DQ slave delay during No-Topology training for slice 3"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_3,Enable for No-Topology training for slice 3" "0,1"
newline
bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_3,Data slice vref training enable control for slice 3" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_3,Data slice initial VREF training stop value for slice 3"
line.long 0x15C "DDRSS_PHY_855,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_3,End of WR DQ slave delay in No-Topology training for slice 3"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_3,Starting WR DQ slave delay in No-Topology training for slice 3"
line.long 0x160 "DDRSS_PHY_856,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_3,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 3" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_3,Minimum data valid window across DQs and ranks for slice 3"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_3,Enable Bit for WR DQ during No-Topology training for slice 3"
line.long 0x164 "DDRSS_PHY_857,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_3,Controls TX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_3,Enable for fast multi-pattern window search for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_3,Peridic training start point offset for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_858,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_859,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_3,Controls RX_DCD pin for dm pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_860,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_3,Controls PCLK/PARK pin for pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_3,Controls RX_DCD pin for fdbk pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_3,Controls RX_DCD pin for dqs pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_861,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_3,Read DQ1 slave delay setting for slice 3"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_3,Read DQ0 slave delay setting for slice 3"
line.long 0x178 "DDRSS_PHY_862,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_3,Read DQ3 slave delay setting for slice 3"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_3,Read DQ2 slave delay setting for slice 3"
line.long 0x17C "DDRSS_PHY_863,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_3,Read DQ5 slave delay setting for slice 3"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_3,Read DQ4 slave delay setting for slice 3"
line.long 0x180 "DDRSS_PHY_864,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_3,Read DQ7 slave delay setting for slice 3"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_3,Read DQ6 slave delay setting for slice 3"
line.long 0x184 "DDRSS_PHY_865,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_3,Determines DCC CAL clock for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_3,Read DM/DBI slave delay setting for slice 3"
line.long 0x188 "DDRSS_PHY_866,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_3,Start/end timing values for DQS output enable signals for slice 3"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_3,Start/end timing values for DQ/DM write based termination enable and select signals for slice 3"
newline
hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_3,Start/end timing values for DQ/DM read based termination enable and select signals for slice 3"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_3,Start/end timing values for DQ/DM output enable signals for slice 3"
line.long 0x18C "DDRSS_PHY_867,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_3,Start/end timing values for DQS write based termination enable and select signals for slice 3"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_3,Start/end timing values for DQS read based OE extension for slice 3"
newline
hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_3,Start/end timing values for DQS read based termination enable and select signals for slice 3"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_3,Feedback pad's OPAD and IPAD delay timing for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_868,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_3,Pad VREF control settings for DQ slice 3"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_3,Number of cycles for vref settle after setting is changed for slice 3"
line.long 0x194 "DDRSS_PHY_869,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_3,Start/end timing values for DQS input enable signals for slice 3"
newline
hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_3,Start/end timing values for DQ/DM input enable signals for slice 3"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_3,Enables the per-rank training and read/write timing capabilities for slice 3" "0,1"
line.long 0x198 "DDRSS_PHY_870,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_3,DBI mode for slice 3" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_3,Input enable mode bits for slice 3" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_871,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_3,Incremental step size for master delay line locking algorithm for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_3,Start value for master delay line locking algorithm for slice 3"
newline
bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_3,Master delay line override settings for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_872,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_3,DQS slave delay step size during write leveling for slice 3"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_3,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_3,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 3"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_3,Wait cycles for master delay line locking algorithm for slice 3"
line.long 0x1A4 "DDRSS_PHY_873,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_3,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_3,DQS slave delay step size during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_3,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_3,DQS slave delay fine step size during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_874,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_3,Final backup step delay used in gate training algorithm for slice 3"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_3,Interim backup step delay used in gate training algorithm for slice 3"
line.long 0x1AC "DDRSS_PHY_875,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_3,DQS slave delay step size during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_3,Support the toggle read preamble for LPDDR4 for slice 3" "0,1"
newline
bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_3,Defines the step granularity for the logic to use once an edge is found for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_3,DQ slave delay step size during write data leveling for slice 3"
line.long 0x1B0 "DDRSS_PHY_876,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_3,The maximun rdlvl slave delay search window for read eye training for slice 3"
line.long 0x1B4 "DDRSS_PHY_877,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_3,Peridic training start point offset for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_3,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 3" "0,1"
newline
hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_3,Minimum data valid window across DQs and ranks for slice 3"
line.long 0x1B8 "DDRSS_PHY_878,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_3,Disable duty cycle adjust at initialization for slice 3" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_3,Write path clock gating timing for slice 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_3,Write path clock gating disable for slice 3" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_879,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_3,Initial value of write DQ slave delay for slice 3"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_3,Initial value of write DQS slave delay for slice 3"
line.long 0x1C0 "DDRSS_PHY_880,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3,Clock measurement cell threshold offset for differential signals for slice 3"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_3,Clock measurement cell threshold offset for single ended signals for slice 3"
newline
bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_3,Enable duty cycle adjust during write DQ training for slice 3" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_3,Enable duty cycle adjust during write leveling for slice 3" "0,1"
line.long 0x1C4 "DDRSS_PHY_881,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_3,Number of cycles that the dfi_rddata_en signal is early for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_3,Data slice training step definition using phy_meas_dly_step_value for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_3,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 3"
line.long 0x1C8 "DDRSS_PHY_882,"
line.long 0x1CC "DDRSS_PHY_883,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_3,DQ/DM bit swizzling 1 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_884,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_3,Write clock slave delay setting for DQ1 for slice 3"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_3,Write clock slave delay setting for DQ0 for slice 3"
line.long 0x1D4 "DDRSS_PHY_885,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_3,Write clock slave delay setting for DQ3 for slice 3"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_3,Write clock slave delay setting for DQ2 for slice 3"
line.long 0x1D8 "DDRSS_PHY_886,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_3,Write clock slave delay setting for DQ5 for slice 3"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_3,Write clock slave delay setting for DQ4 for slice 3"
line.long 0x1DC "DDRSS_PHY_887,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_3,Write clock slave delay setting for DQ7 for slice 3"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_3,Write clock slave delay setting for DQ6 for slice 3"
line.long 0x1E0 "DDRSS_PHY_888,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_3,Write clock slave delay setting for DQS for slice 3"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_3,Write clock slave delay setting for DM for slice 3"
line.long 0x1E4 "DDRSS_PHY_889,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ0 for slice 3"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_3,Write level threshold adjust value based on those thresholds for DQS for slice 3" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_890,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ1 for slice 3"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ0 for slice 3"
line.long 0x1EC "DDRSS_PHY_891,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ2 for slice 3"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ1 for slice 3"
line.long 0x1F0 "DDRSS_PHY_892,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ3 for slice 3"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ2 for slice 3"
line.long 0x1F4 "DDRSS_PHY_893,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ4 for slice 3"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ3 for slice 3"
line.long 0x1F8 "DDRSS_PHY_894,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ5 for slice 3"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ4 for slice 3"
line.long 0x1FC "DDRSS_PHY_895,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ6 for slice 3"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ5 for slice 3"
line.long 0x200 "DDRSS_PHY_896,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ7 for slice 3"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ6 for slice 3"
line.long 0x204 "DDRSS_PHY_897,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DM for slice 3"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ7 for slice 3"
line.long 0x208 "DDRSS_PHY_898,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_3,Read DQS slave delay setting for slice 3"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DM for slice 3"
line.long 0x20C "DDRSS_PHY_899,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_3,Write level delay threshold above which will be considered in previous cycle for slice 3"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_3,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_3,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_900,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_3,Force the final write level delay value (that meets the early threshold) to 0 for slice 3" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3,Write level delay threshold below which will add a cycle of write path latency for slice 3"
line.long 0x214 "DDRSS_PHY_901,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_3,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_3,Initial read DQS gate slave delay setting during gate training for slice 3"
line.long 0x218 "DDRSS_PHY_902,"
bitfld.long 0x218 24. "PHY_NTP_PASS_3,Indicates if No-topology training found a passing result for slice 3" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_3,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_3,Initial DQ/DM slave delay setting during write data leveling for slice 3"
line.long 0x21C "DDRSS_PHY_903,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3,Read leveling starting value for the DQS/DQ slave delay settings for slice 3"
line.long 0x220 "DDRSS_PHY_904,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
newline
hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
line.long 0x224 "DDRSS_PHY_905,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
newline
hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
line.long 0x228 "DDRSS_PHY_906,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_3,Setting for boost P/N of pad for slice 3"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
newline
hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
line.long 0x22C "DDRSS_PHY_907,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_3,TX_FFE setting for DQS pad for slice 3" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_3,TX_FFE setting for DQ/DM pad for slice 3" "0,1,2,3"
newline
bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_3,Setting for RX ctle P/N of pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5000++0xCF
line.long 0x00 "DDRSS_PHY_1024,"
bitfld.long 0x00 24.--26. "SC_PHY_ADR_MANUAL_CLEAR_0,Manual reset/clear of internal logic for address slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "PHY_ADR_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for address slice 0" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0,Command/Address clock bypass mode slave delay setting for address slice 0"
line.long 0x04 "DDRSS_PHY_1025,"
line.long 0x08 "DDRSS_PHY_1026,"
bitfld.long 0x08 24.--27. "PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x08 16.--23. 1. "PHY_ADR_MEAS_DLY_STEP_VALUE_0,Contains the fraction of a cycle in 1 delay element numerator with demominator of 512 for address slice 0"
newline
hexmask.long.word 0x08 0.--15. 1. "PHY_ADR_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for address slice 0"
line.long 0x0C "DDRSS_PHY_1027,"
hexmask.long.byte 0x0C 24.--31. 1. "PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing addr slave delay for address slice 0"
hexmask.long.byte 0x0C 16.--22. 1. "PHY_ADR_BASE_SLV_DLY_ENC_OBS_0,Observation register containing base slave delay for address slice 0"
newline
hexmask.long.word 0x0C 0.--10. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for address slice 0"
line.long 0x10 "DDRSS_PHY_1028,"
bitfld.long 0x10 24. "PHY_ADR_TSEL_ENABLE_0,Enables tsel_en for address slice 0" "0,1"
bitfld.long 0x10 16. "SC_PHY_ADR_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for address slice 0" "0,1"
newline
bitfld.long 0x10 8.--10. "PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0,Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0,Reserved for address slice 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "DDRSS_PHY_1029,"
bitfld.long 0x14 24. "PHY_ADR_PWR_RDC_DISABLE_0,Power reduction disable for address slice 0" "0,1"
bitfld.long 0x14 16.--20. "PHY_ADR_PRBS_PATTERN_MASK_0,PRBS7 mask signal for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x14 8.--14. 1. "PHY_ADR_PRBS_PATTERN_START_0,PRBS7 start pattern for address slice 0"
hexmask.long.byte 0x14 0.--6. 1. "PHY_ADR_LPBK_CONTROL_0,Loopback control bits for address slice 0"
line.long 0x18 "DDRSS_PHY_1030,"
bitfld.long 0x18 24. "PHY_ADR_IE_MODE_0,Input enable control for address slice 0" "0,1"
rbitfld.long 0x18 16.--18. "PHY_ADR_WRADDR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for address slice 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 8.--9. "PHY_ADR_TYPE_0,DRAM type for address slice 0" "0,1,2,3"
bitfld.long 0x18 0. "PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0,Power reduction slv_dly_control block gate disable for address slice 0" "0,1"
line.long 0x1C "DDRSS_PHY_1031,"
hexmask.long 0x1C 0.--26. 1. "PHY_ADR_DDL_MODE_0,DDL mode for address slice 0"
line.long 0x20 "DDRSS_PHY_1032,"
bitfld.long 0x20 0.--5. "PHY_ADR_DDL_MASK_0,DDL mask for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "DDRSS_PHY_1033,"
line.long 0x28 "DDRSS_PHY_1034,"
line.long 0x2C "DDRSS_PHY_1035,"
hexmask.long.word 0x2C 16.--26. 1. "PHY_ADR_CALVL_COARSE_DLY_0,Coarse CA training DDL increment value for address slice 0"
hexmask.long.word 0x2C 0.--10. 1. "PHY_ADR_CALVL_START_0,CA training DDL start value for address slice 0"
line.long 0x30 "DDRSS_PHY_1036,"
hexmask.long.word 0x30 0.--10. 1. "PHY_ADR_CALVL_QTR_0,CA training DDL quarter cycle delay value for address slice 0"
line.long 0x34 "DDRSS_PHY_1037,"
hexmask.long.tbyte 0x34 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE0_0,CA training RD DQ bit swizzle map 0 for address slice 0"
line.long 0x38 "DDRSS_PHY_1038,"
bitfld.long 0x38 24.--25. "PHY_ADR_CALVL_RANK_CTRL_0,CA training rank aggregation control bits for address slice 0" "0,1,2,3"
hexmask.long.tbyte 0x38 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE1_0,CA training RD DQ bit swizzle map 1 for address slice 0"
line.long 0x3C "DDRSS_PHY_1039,"
hexmask.long.word 0x3C 16.--24. 1. "PHY_ADR_CALVL_PERIODIC_START_OFFSET_0,Relative offset to start periodic CALVL from previous result"
bitfld.long 0x3C 8.--11. "PHY_ADR_CALVL_RESP_WAIT_CNT_0,Number of samples to wait before sampling response during CA training for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x3C 0.--1. "PHY_ADR_CALVL_NUM_PATTERNS_0,Number of patterns to use during CA training for address slice 0" "0,1,2,3"
line.long 0x40 "DDRSS_PHY_1040,"
bitfld.long 0x40 24.--26. "PHY_ADR_CALVL_OBS_SELECT_0,CA bit lane to observe result from OBS0 during CA training for address slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x40 16. "SC_PHY_ADR_CALVL_ERROR_CLR_0,Clears the CA training state machine error status for address slice 0" "0,1"
newline
bitfld.long 0x40 8. "SC_PHY_ADR_CALVL_DEBUG_CONT_0,Allows the CA training state machine to advance (when in debug mode) for address slice 0" "0,1"
bitfld.long 0x40 0. "PHY_ADR_CALVL_DEBUG_MODE_0,Enables CA training debug mode for address slice 0" "0,1"
line.long 0x44 "DDRSS_PHY_1041,"
line.long 0x48 "DDRSS_PHY_1042,"
line.long 0x4C "DDRSS_PHY_1043,"
line.long 0x50 "DDRSS_PHY_1044,"
line.long 0x54 "DDRSS_PHY_1045,"
hexmask.long.tbyte 0x54 0.--19. 1. "PHY_ADR_CALVL_FG_0_0,CA training foreground pattern 0 for address slice 0"
line.long 0x58 "DDRSS_PHY_1046,"
hexmask.long.tbyte 0x58 0.--19. 1. "PHY_ADR_CALVL_BG_0_0,CA training background pattern 0 for address slice 0"
line.long 0x5C "DDRSS_PHY_1047,"
hexmask.long.tbyte 0x5C 0.--19. 1. "PHY_ADR_CALVL_FG_1_0,CA training foreground pattern 1 for address slice 0"
line.long 0x60 "DDRSS_PHY_1048,"
hexmask.long.tbyte 0x60 0.--19. 1. "PHY_ADR_CALVL_BG_1_0,CA training background pattern 1 for address slice 0"
line.long 0x64 "DDRSS_PHY_1049,"
hexmask.long.tbyte 0x64 0.--19. 1. "PHY_ADR_CALVL_FG_2_0,CA training foreground pattern 2 for address slice 0"
line.long 0x68 "DDRSS_PHY_1050,"
hexmask.long.tbyte 0x68 0.--19. 1. "PHY_ADR_CALVL_BG_2_0,CA training background pattern 2 for address slice 0"
line.long 0x6C "DDRSS_PHY_1051,"
hexmask.long.tbyte 0x6C 0.--19. 1. "PHY_ADR_CALVL_FG_3_0,CA training foreground pattern 3 for address slice 0"
line.long 0x70 "DDRSS_PHY_1052,"
hexmask.long.tbyte 0x70 0.--19. 1. "PHY_ADR_CALVL_BG_3_0,CA training background pattern 3 for address slice 0"
line.long 0x74 "DDRSS_PHY_1053,"
hexmask.long.tbyte 0x74 0.--23. 1. "PHY_ADR_ADDR_SEL_0,Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 0"
line.long 0x78 "DDRSS_PHY_1054,"
bitfld.long 0x78 24.--29. "PHY_ADR_SEG_MASK_0,Segment mask bit for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x78 16.--21. "PHY_ADR_BIT_MASK_0,Mask bit for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x78 0.--9. 1. "PHY_ADR_LP4_BOOT_SLV_DELAY_0,Address slave delay setting during the LPDDR4 boot frequency operation for address slice 0"
line.long 0x7C "DDRSS_PHY_1055,"
bitfld.long 0x7C 24.--29. "PHY_ADR_SW_TXIO_CTRL_0,Controls address pad output enable for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x7C 16.--19. "PHY_ADR_STATIC_TOG_DISABLE_0,Toggle control during static activity for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x7C 8.--13. "PHY_ADR_CSLVL_TRAIN_MASK_0,Mask bit for CS training participation for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x7C 0.--5. "PHY_ADR_CALVL_TRAIN_MASK_0,Mask bit for CA training participation for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_1056,"
hexmask.long.byte 0x80 24.--31. 1. "PHY_ADR_DC_ADR2_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 2 for address slice 0"
hexmask.long.byte 0x80 16.--23. 1. "PHY_ADR_DC_ADR1_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 1 for address slice 0"
newline
hexmask.long.byte 0x80 8.--15. 1. "PHY_ADR_DC_ADR0_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 0 for address slice 0"
bitfld.long 0x80 0.--1. "PHY_ADR_DC_INIT_DISABLE_0,Duty Cycle Corrector disable at initialization for address slice 0" "0,1,2,3"
line.long 0x84 "DDRSS_PHY_1057,"
bitfld.long 0x84 24. "PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0,DCC and RX_CAL clk gate disable for address slice 0" "0,1"
hexmask.long.byte 0x84 16.--23. 1. "PHY_ADR_DC_ADR5_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 5 for address slice 0"
newline
hexmask.long.byte 0x84 8.--15. 1. "PHY_ADR_DC_ADR4_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 4 for address slice 0"
hexmask.long.byte 0x84 0.--7. 1. "PHY_ADR_DC_ADR3_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 3 for address slice 0"
line.long 0x88 "DDRSS_PHY_1058,"
bitfld.long 0x88 24.--29. "PHY_ADR_DC_ADJUST_START_0,DCC calibration starting value for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x88 16.--17. "PHY_ADR_DC_WEIGHT_0,DCC weighting factor base value for address slice 0" "0,1,2,3"
newline
hexmask.long.byte 0x88 8.--15. 1. "PHY_ADR_DC_CAL_TIMEOUT_0,DCC number of iterations to wait before timeout for address slice 0"
hexmask.long.byte 0x88 0.--7. 1. "PHY_ADR_DC_CAL_SAMPLE_WAIT_0,DCC cycles to wait after calibration change before sampling results for address slice 0"
line.long 0x8C "DDRSS_PHY_1059,"
bitfld.long 0x8C 24. "PHY_ADR_DC_CAL_POLARITY_0,DCC calibration polarity for address slice 0" "0,1"
bitfld.long 0x8C 16. "PHY_ADR_DC_ADJUST_DIRECT_0,DCC adjust direction for address slice 0" "0,1"
newline
hexmask.long.byte 0x8C 8.--15. 1. "PHY_ADR_DC_ADJUST_THRSHLD_0,DCC adjust threshold around the mid-point for address slice 0"
hexmask.long.byte 0x8C 0.--7. 1. "PHY_ADR_DC_ADJUST_SAMPLE_CNT_0,DCC number of samples to take for address slice 0"
line.long 0x90 "DDRSS_PHY_1060,"
hexmask.long.word 0x90 16.--26. 1. "PHY_PARITY_ERROR_REGIF_ADR_0,Inject parity error to register interface signals for address slice 0"
bitfld.long 0x90 8.--13. "PHY_ADR_SW_TXPWR_CTRL_0,Disable address output enables in deep sleep mode for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x90 0. "PHY_ADR_DC_CAL_START_0,DCC Manual trigger for address slice 0" "0,1"
line.long 0x94 "DDRSS_PHY_1061,"
hexmask.long.word 0x94 16.--24. 1. "PHY_AS_FSM_ERROR_INFO_MASK_0,FSM Error Info Mask for address slice 0"
hexmask.long.word 0x94 0.--8. 1. "PHY_AS_FSM_ERROR_INFO_0,FSM Error Info for address slice 0"
line.long 0x98 "DDRSS_PHY_1062,"
bitfld.long 0x98 24. "PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0,Training/Calibration Error Info Mask for address slice 0" "0,1"
rbitfld.long 0x98 16. "PHY_AS_TRAIN_CALIB_ERROR_INFO_0,Training/Calibration Error Info for address slice 0" "0,1"
newline
hexmask.long.word 0x98 0.--8. 1. "SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0,FSM Error Info clear for address slice 0"
line.long 0x9C "DDRSS_PHY_1063,"
bitfld.long 0x9C 0. "SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0,Training/Calibration Error Info clear for address slice 0" "0,1"
line.long 0xA0 "DDRSS_PHY_1064,"
hexmask.long.word 0xA0 16.--26. 1. "PHY_PAD_ADR_IO_CFG_0,Controls I/O pads for address pad for address slice 0"
bitfld.long 0xA0 8.--10. "PHY_ADR_DC_CAL_CLK_SEL_0,DCC CAL clock for address slice 0" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xA0 0.--7. 1. "PHY_ADR_TSEL_SELECT_0,Tsel select values for address slice 0"
line.long 0xA4 "DDRSS_PHY_1065,"
bitfld.long 0xA4 24.--28. "PHY_ADR1_SW_WRADDR_SHIFT_0,Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xA4 8.--18. 1. "PHY_ADR0_CLK_WR_SLAVE_DELAY_0,CA bit 0 slave delay setting for address slice 0"
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bitfld.long 0xA4 0.--4. "PHY_ADR0_SW_WRADDR_SHIFT_0,Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA8 "DDRSS_PHY_1066,"
bitfld.long 0xA8 16.--20. "PHY_ADR2_SW_WRADDR_SHIFT_0,Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xA8 0.--10. 1. "PHY_ADR1_CLK_WR_SLAVE_DELAY_0,CA bit 1 slave delay setting for address slice 0"
line.long 0xAC "DDRSS_PHY_1067,"
bitfld.long 0xAC 16.--20. "PHY_ADR3_SW_WRADDR_SHIFT_0,Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xAC 0.--10. 1. "PHY_ADR2_CLK_WR_SLAVE_DELAY_0,CA bit 2 slave delay setting for address slice 0"
line.long 0xB0 "DDRSS_PHY_1068,"
bitfld.long 0xB0 16.--20. "PHY_ADR4_SW_WRADDR_SHIFT_0,Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xB0 0.--10. 1. "PHY_ADR3_CLK_WR_SLAVE_DELAY_0,CA bit 3 slave delay setting for address slice 0"
line.long 0xB4 "DDRSS_PHY_1069,"
bitfld.long 0xB4 16.--20. "PHY_ADR5_SW_WRADDR_SHIFT_0,Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xB4 0.--10. 1. "PHY_ADR4_CLK_WR_SLAVE_DELAY_0,CA bit 4 slave delay setting for address slice 0"
line.long 0xB8 "DDRSS_PHY_1070,"
bitfld.long 0xB8 16.--19. "PHY_ADR_SW_MASTER_MODE_0,Master delay line override settings for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0xB8 0.--10. 1. "PHY_ADR5_CLK_WR_SLAVE_DELAY_0,CA bit 5 slave delay setting for address slice 0"
line.long 0xBC "DDRSS_PHY_1071,"
hexmask.long.byte 0xBC 24.--31. 1. "PHY_ADR_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for address slice 0"
bitfld.long 0xBC 16.--21. "PHY_ADR_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0xBC 0.--10. 1. "PHY_ADR_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for address slice 0"
line.long 0xC0 "DDRSS_PHY_1072,"
bitfld.long 0xC0 24. "PHY_ADR_SW_CALVL_DVW_MIN_EN_0,Enables the software override data valid window size during CA training for address slice 0" "0,1"
hexmask.long.word 0xC0 8.--17. 1. "PHY_ADR_SW_CALVL_DVW_MIN_0,Sets the software override data valid window size during CA training for address slice 0"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_ADR_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 0"
line.long 0xC4 "DDRSS_PHY_1073,"
bitfld.long 0xC4 0.--3. "PHY_ADR_CALVL_DLY_STEP_0,Sets the delay step size plus 1 during CA training for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "DDRSS_PHY_1074,"
hexmask.long.word 0xC8 16.--25. 1. "PHY_ADR_DC_INIT_SLV_DELAY_0,DCC initialization value of write ADDR slave delay for address slice 0"
bitfld.long 0xC8 8. "PHY_ADR_MEAS_DLY_STEP_ENABLE_0,Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 0" "0,1"
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bitfld.long 0xC8 0.--3. "PHY_ADR_CALVL_CAPTURE_CNT_0,Number of samples to take at each ADDR slave delay setting during CA training for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "DDRSS_PHY_1075,"
hexmask.long.byte 0xCC 8.--15. 1. "PHY_ADR_DC_DM_CLK_THRSHLD_0,DCC clock measurement cell threshold offset for address slice 0"
bitfld.long 0xCC 0. "PHY_ADR_DC_CALVL_ENABLE_0,DCC enable duty cycle adjust during CA leveling for address slice 0" "0,1"
group.long 0x5400++0x23B
line.long 0x00 "DDRSS_PHY_1280,"
bitfld.long 0x00 0.--1. "PHY_FREQ_SEL,Specifies which copy of the frequency-dependent timing parameters will be used by the PHY" "0,1,2,3"
line.long 0x04 "DDRSS_PHY_1281,"
bitfld.long 0x04 24.--28. "PHY_SW_GRP0_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--17. "PHY_FREQ_SEL_INDEX,Selects which frequency set to update when PHY_FREQ_SEL_MULTICAST_EN is not set" "0,1,2,3"
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bitfld.long 0x04 8. "PHY_FREQ_SEL_MULTICAST_EN,When set a register write will update parameters for all frequency sets simultaneously" "0,1"
bitfld.long 0x04 0. "PHY_FREQ_SEL_FROM_REGIF,Indicates which source is used to select the frequency copy" "0,1"
line.long 0x08 "DDRSS_PHY_1282,"
bitfld.long 0x08 24.--28. "PHY_SW_GRP0_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "PHY_SW_GRP3_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--12. "PHY_SW_GRP2_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "PHY_SW_GRP1_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "DDRSS_PHY_1283,"
bitfld.long 0x0C 16.--20. "PHY_SW_GRP3_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "PHY_SW_GRP2_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0.--4. "PHY_SW_GRP1_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "DDRSS_PHY_1284,"
bitfld.long 0x10 24. "PHY_GRP_BYPASS_OVERRIDE,Address/control group slice bypass mode override setting" "0,1"
bitfld.long 0x10 16.--20. "PHY_SW_GRP_BYPASS_SHIFT,Address/control group slice bypass mode shift settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x10 0.--10. 1. "PHY_GRP_BYPASS_SLAVE_DELAY,Address/control group slice bypass mode slave delay setting"
line.long 0x14 "DDRSS_PHY_1285,"
hexmask.long.word 0x14 16.--26. 1. "PHY_CSLVL_START,Defines the CS training DDL start value"
bitfld.long 0x14 8. "PHY_MANUAL_UPDATE_PHYUPD_ENABLE,Manual update selection of all slave delay line settings" "0,1"
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bitfld.long 0x14 0. "SC_PHY_MANUAL_UPDATE,Manual update of all slave delay line settings" "0,1"
line.long 0x18 "DDRSS_PHY_1286,"
bitfld.long 0x18 24. "SC_PHY_CSLVL_DEBUG_CONT,Allows the CS training state machine to advance (when in debug mode)" "0,1"
bitfld.long 0x18 16. "PHY_CSLVL_DEBUG_MODE,Enables CS training debug mode" "0,1"
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hexmask.long.word 0x18 0.--10. 1. "PHY_CSLVL_COARSE_DLY,Defines the CS training DDL coarse cycle delay value"
line.long 0x1C "DDRSS_PHY_1287,"
bitfld.long 0x1C 0. "SC_PHY_CSLVL_ERROR_CLR,Clears the CS training state machine error status" "0,1"
line.long 0x20 "DDRSS_PHY_1288,"
line.long 0x24 "DDRSS_PHY_1289,"
line.long 0x28 "DDRSS_PHY_1290,"
line.long 0x2C "DDRSS_PHY_1291,"
bitfld.long 0x2C 24. "PHY_LP4_BOOT_DISABLE,Controls the handling of the DFI frequency" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_CSLVL_PERIODIC_START_OFFSET,Defines the relative offset from previous LE and TE to start periodic CSLVL with"
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bitfld.long 0x2C 0. "PHY_CSLVL_ENABLE,CS training enable" "0,1"
line.long 0x30 "DDRSS_PHY_1292,"
hexmask.long.word 0x30 8.--18. 1. "PHY_CSLVL_QTR,Defines the CS training DDL 1/4 cycle delay value"
bitfld.long 0x30 0.--3. "PHY_CSLVL_CS_MAP,CS training map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DDRSS_PHY_1293,"
hexmask.long.byte 0x34 24.--31. 1. "PHY_CALVL_CS_MAP,Defines the slice numbers associated with each CS during CA training"
bitfld.long 0x34 16.--19. "PHY_CSLVL_COARSE_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training coarse CA training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x34 0.--10. 1. "PHY_CSLVL_COARSE_CHK,Defines the CS training coarse CA training DDL 1/16th cycle delay value"
line.long 0x38 "DDRSS_PHY_1294,"
bitfld.long 0x38 24. "PHY_ADRCTL_LPDDR,Adds a cycle of delay for the address/control slices to match the address slice" "0,1"
bitfld.long 0x38 16.--17. "PHY_DFI_PHYUPD_TYPE,Defines the value of the dfi_phyupd_type output signal to MC" "0,1,2,3"
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bitfld.long 0x38 8. "PHY_ADRCTL_SNAP_OBS_REGS,Initiates a snapshot of the internal observation registers for the address/control block" "0,1"
bitfld.long 0x38 0.--2. "PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE,Reserved for the address/control master" "0,1,2,3,4,5,6,7"
line.long 0x3C "DDRSS_PHY_1295,"
hexmask.long.byte 0x3C 24.--31. 1. "PHY_CLK_DC_CAL_TIMEOUT,Duty cycle correction maximum iteration count"
hexmask.long.byte 0x3C 16.--23. 1. "PHY_CLK_DC_CAL_SAMPLE_WAIT,Number of cal clock cycles to wait for a sample to be taken"
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bitfld.long 0x3C 8. "PHY_LPDDR3_CS,Alters reset state polarity for LPDDR chip selects" "0,1"
bitfld.long 0x3C 0. "PHY_LP4_ACTIVE,Indicates an LPDDR4 device is connected to the PHY" "0,1"
line.long 0x40 "DDRSS_PHY_1296,"
hexmask.long.byte 0x40 24.--31. 1. "PHY_CLK_DC_ADJUST_SAMPLE_CNT,Duty cycle correction algorithm sample count per adjustment setting"
bitfld.long 0x40 16.--21. "PHY_CLK_DC_ADJUST_START,Duty cycle correction algorithm adjustment starting value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x40 8. "PHY_CLK_DC_FREQ_CHG_ADJ,Duty cycle correction during frequency change control" "0,1"
bitfld.long 0x40 0.--1. "PHY_CLK_DC_WEIGHT,Duty cycle correction weighting factor base value" "0,1,2,3"
line.long 0x44 "DDRSS_PHY_1297,"
bitfld.long 0x44 24. "PHY_CLK_DC_CAL_START,Duty cycle correction calibration manual start" "0,1"
bitfld.long 0x44 16. "PHY_CLK_DC_CAL_POLARITY,Duty cycle correction algorithm measurement polarity" "0,1"
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bitfld.long 0x44 8. "PHY_CLK_DC_ADJUST_DIRECT,Duty cycle correction algorithm adjustment direction" "0,1"
hexmask.long.byte 0x44 0.--7. 1. "PHY_CLK_DC_ADJUST_THRSHLD,Duty cycle correction algorithm threshold delta comparison"
line.long 0x48 "DDRSS_PHY_1298,"
bitfld.long 0x48 24.--27. "PHY_SW_TXIO_CTRL_1,This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x48 16.--19. "PHY_SW_TXIO_CTRL_0,This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x48 8. "PHY_CONTINUOUS_CLK_CAL_UPDATE,Continuous update of all latest PVTP PVTN and PVTR values to the CLK IO pads" "0,1"
bitfld.long 0x48 0. "SC_PHY_UPDATE_CLK_CAL_VALUES,Manual update of all latest PVTP PVTN and PVTR values to the CLK IO pads" "0,1"
line.long 0x4C "DDRSS_PHY_1299,"
bitfld.long 0x4C 24. "PHY_MEMCLK_SW_TXPWR_CTRL,This register is used to control if clk pads should be shutoff for TX mode in deep sleep mode" "0,1"
bitfld.long 0x4C 16.--19. "PHY_ADRCTL_SW_TXPWR_CTRL_1,This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x4C 8.--11. "PHY_ADRCTL_SW_TXPWR_CTRL_0,This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4C 0. "PHY_MEMCLK_SW_TXIO_CTRL,This register is used to control if clk pads should be shutoff for TX mode" "0,1"
line.long 0x50 "DDRSS_PHY_1300,"
hexmask.long.word 0x50 16.--31. 1. "PHY_STATIC_TOG_CONTROL,Clock divider to create toggle signal"
bitfld.long 0x50 8. "PHY_BYTE_DISABLE_STATIC_TOG_DISABLE,Control to disable the toggle signal for data slice during static activity when dfi_data_byte_disable is asserted" "0,1"
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bitfld.long 0x50 0. "PHY_TOP_STATIC_TOG_DISABLE,Disables the generation of the toggle for static clock based paths in the PHY to prevent assymetric aging" "0,1"
line.long 0x54 "DDRSS_PHY_1301,"
bitfld.long 0x54 16. "PHY_LP4_BOOT_PLL_BYPASS,PHY clock PLL bypass select" "0,1"
bitfld.long 0x54 8. "PHY_MEMCLK_STATIC_TOG_DISABLE,Control to disable toggle during static activity" "0,1"
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bitfld.long 0x54 0.--3. "PHY_ADRCTL_STATIC_TOG_DISABLE,Control to disable toggle during static activity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "DDRSS_PHY_1302,"
line.long 0x5C "DDRSS_PHY_1303,"
hexmask.long.word 0x5C 0.--15. 1. "PHY_PLL_WAIT,PHY clock PLL wait time after locking"
line.long 0x60 "DDRSS_PHY_1304,"
bitfld.long 0x60 0. "PHY_SW_PLL_BYPASS,PHY clock PLL bypass select" "0,1"
line.long 0x64 "DDRSS_PHY_1305,"
bitfld.long 0x64 24.--27. "PHY_CS_ACS_ALLOCATION_BIT1_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x64 16.--19. "PHY_CS_ACS_ALLOCATION_BIT0_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x64 8.--11. "PHY_SET_DFI_INPUT_1,Used to indicate the default value of the adrctl slice bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x64 0.--3. "PHY_SET_DFI_INPUT_0,Used to indicate the default value of the adrctl slice bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "DDRSS_PHY_1306,"
bitfld.long 0x68 24.--27. "PHY_CS_ACS_ALLOCATION_BIT1_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x68 16.--19. "PHY_CS_ACS_ALLOCATION_BIT0_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8.--11. "PHY_CS_ACS_ALLOCATION_BIT3_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x68 0.--3. "PHY_CS_ACS_ALLOCATION_BIT2_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DDRSS_PHY_1307,"
bitfld.long 0x6C 24. "PHY_CLK_DC_INIT_DISABLE,Disable duty cycle adjust at initialization" "0,1"
hexmask.long.byte 0x6C 16.--23. 1. "PHY_CLK_DC_ADJUST_0,Adjust value of Duty Cycle Adjuster for clock slice 0"
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bitfld.long 0x6C 8.--11. "PHY_CS_ACS_ALLOCATION_BIT3_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_CS_ACS_ALLOCATION_BIT2_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_1308,"
hexmask.long.word 0x70 8.--20. 1. "PHY_LP4_BOOT_PLL_CTRL,PHY deskew PLL controls for LPDDR4 boot frequency"
hexmask.long.byte 0x70 0.--7. 1. "PHY_CLK_DC_DM_THRSHLD,Data measurement cell threshold offset"
line.long 0x74 "DDRSS_PHY_1309,"
bitfld.long 0x74 16. "PHY_USE_PLL_DSKEWCALLOCK,Use DSKEWCALLOCK or not" "0,1"
hexmask.long.word 0x74 0.--15. 1. "PHY_PLL_CTRL_OVERRIDE,Individual PHY clock PLL control overrides"
line.long 0x78 "DDRSS_PHY_1310,"
bitfld.long 0x78 24.--25. "SC_PHY_PLL_SPO_CAL_SNAP_OBS,Register command to take a snapshot of PLL output" "0,1,2,3"
hexmask.long.tbyte 0x78 0.--18. 1. "PHY_PLL_SPO_CAL_CTRL,PLL SPO Cal controls"
line.long 0x7C "DDRSS_PHY_1311,"
bitfld.long 0x7C 16.--17. "SC_PHY_PLL_CAL_CLK_MEAS,Register command to initiate cal_clklout clock frequency measurement" "0,1,2,3"
hexmask.long.word 0x7C 0.--9. 1. "PHY_PLL_CAL_CLK_MEAS_CYCLES,Measurement cycles of cal_clkout clock"
line.long 0x80 "DDRSS_PHY_1312,"
hexmask.long.word 0x80 0.--15. 1. "PHY_PLL_OBS_0,PHY TOP level clock PLL_0 observe values"
line.long 0x84 "DDRSS_PHY_1313,"
hexmask.long.tbyte 0x84 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_0,PHY TOP level PLL_0 SPO Cal observe values"
line.long 0x88 "DDRSS_PHY_1314,"
hexmask.long.tbyte 0x88 0.--17. 1. "PHY_PLL_CAL_CLK_MEAS_OBS_0,PHY TOP level PLL_0 cal_clkout measurement observe values"
line.long 0x8C "DDRSS_PHY_1315,"
hexmask.long.word 0x8C 0.--15. 1. "PHY_PLL_OBS_1,PHY TOP level clock PLL_1 observe values"
line.long 0x90 "DDRSS_PHY_1316,"
hexmask.long.tbyte 0x90 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_1,PHY TOP level PLL_1 SPO Cal observe values"
line.long 0x94 "DDRSS_PHY_1317,"
bitfld.long 0x94 24. "PHY_LP4_BOOT_LOW_FREQ_SEL,Control the PLL domain enter/exit from the negative clock edge for LPDDR4 boot frequency" "0,1"
hexmask.long.tbyte 0x94 0.--17. 1. "PHY_PLL_CAL_CLK_MEAS_OBS_1,PHY TOP level PLL_1 cal_clkout measurement observe values"
line.long 0x98 "DDRSS_PHY_1318,"
bitfld.long 0x98 16. "PHY_LS_IDLE_EN,Indicates the Reduced Idle Power State is enabled in low power mode" "0,1"
hexmask.long.byte 0x98 8.--15. 1. "PHY_LP_WAKEUP,Specifies the number of cycles the PHY takes to wakeup in low power mode"
newline
bitfld.long 0x98 0.--3. "PHY_TCKSRE_WAIT,Specifies the number of cycles the PHY should wait before turning off the PLL for a deep sleep or DFS event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "DDRSS_PHY_1319,"
bitfld.long 0x9C 16. "PHY_TDFI_PHY_WRDELAY,DFI timing parameter TDFI_PHY_WRDELAY" "0,1"
hexmask.long.word 0x9C 0.--9. 1. "PHY_LP_CTRLUPD_CNTR_CFG,Specifies the number of cycles the PHY takes from light sleep req deassert to ack deassert in low power mode"
line.long 0xA0 "DDRSS_PHY_1320,"
hexmask.long.tbyte 0xA0 0.--17. 1. "PHY_PAD_FDBK_TERM,Controls term settings for gate feedback pads"
line.long 0xA4 "DDRSS_PHY_1321,"
hexmask.long.tbyte 0xA4 0.--16. 1. "PHY_PAD_DATA_TERM,Controls term settings for data pads"
line.long 0xA8 "DDRSS_PHY_1322,"
hexmask.long.tbyte 0xA8 0.--16. 1. "PHY_PAD_DQS_TERM,Controls term settings for dqs pads"
line.long 0xAC "DDRSS_PHY_1323,"
hexmask.long.tbyte 0xAC 0.--17. 1. "PHY_PAD_ADDR_TERM,Controls term settings for the address/control pads"
line.long 0xB0 "DDRSS_PHY_1324,"
hexmask.long.tbyte 0xB0 0.--17. 1. "PHY_PAD_CLK_TERM,Controls term settings for clock pads"
line.long 0xB4 "DDRSS_PHY_1325,"
hexmask.long.tbyte 0xB4 0.--17. 1. "PHY_PAD_CKE_TERM,Controls term settings for cke pads"
line.long 0xB8 "DDRSS_PHY_1326,"
hexmask.long.tbyte 0xB8 0.--17. 1. "PHY_PAD_RST_TERM,Controls term settings for reset_n pads"
line.long 0xBC "DDRSS_PHY_1327,"
hexmask.long.tbyte 0xBC 0.--17. 1. "PHY_PAD_CS_TERM,Controls term settings for cs pads"
line.long 0xC0 "DDRSS_PHY_1328,"
hexmask.long.tbyte 0xC0 0.--17. 1. "PHY_PAD_ODT_TERM,Controls term settings for odt pads"
line.long 0xC4 "DDRSS_PHY_1329,"
hexmask.long.word 0xC4 16.--28. 1. "PHY_ADRCTL_LP3_RX_CAL,PHY CKE/RESET_N RX calibration controls"
hexmask.long.word 0xC4 0.--9. 1. "PHY_ADRCTL_RX_CAL,PHY address/control RX calibration controls"
line.long 0xC8 "DDRSS_PHY_1330,"
bitfld.long 0xC8 24. "PHY_CAL_START_0,Manual start for the pad calibration state machine for block 0" "0,1"
bitfld.long 0xC8 16. "PHY_CAL_CLEAR_0,Clear the pad calibration state machine and results for block 0" "0,1"
newline
hexmask.long.word 0xC8 0.--12. 1. "PHY_CAL_MODE_0,Pad calibration mode bits for block 0"
line.long 0xCC "DDRSS_PHY_1331,"
line.long 0xD0 "DDRSS_PHY_1332,"
bitfld.long 0xD0 8.--10. "PHY_LP4_BOOT_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for LPDDR4 boot frequency for block 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD0 0.--7. 1. "PHY_CAL_SAMPLE_WAIT_0,Pad calibration state machine wait count in pad clock cycles for block 0"
line.long 0xD4 "DDRSS_PHY_1333,"
hexmask.long.tbyte 0xD4 0.--23. 1. "PHY_CAL_RESULT_OBS_0,Pad calibration results observation values for block 0"
line.long 0xD8 "DDRSS_PHY_1334,"
hexmask.long.tbyte 0xD8 0.--23. 1. "PHY_CAL_RESULT2_OBS_0,Pad calibration results (CKE/RESET_N) observation values for block 0"
line.long 0xDC "DDRSS_PHY_1335,"
hexmask.long.tbyte 0xDC 0.--23. 1. "PHY_CAL_RESULT4_OBS_0,Pad calibration pass1 shadow results observation values for block 0"
line.long 0xE0 "DDRSS_PHY_1336,"
hexmask.long.tbyte 0xE0 0.--23. 1. "PHY_CAL_RESULT5_OBS_0,Pad calibration pass2 shadow results observation values for block 0"
line.long 0xE4 "DDRSS_PHY_1337,"
hexmask.long.tbyte 0xE4 0.--23. 1. "PHY_CAL_RESULT6_OBS_0,Pad calibration internal results observation delta values for block 0"
line.long 0xE8 "DDRSS_PHY_1338,"
hexmask.long.byte 0xE8 24.--30. 1. "PHY_CAL_CPTR_CNT_0,defines sample capture number in pad calibration process"
hexmask.long.tbyte 0xE8 0.--23. 1. "PHY_CAL_RESULT7_OBS_0,Pad calibration internal results observation delta values for block 0"
line.long 0xEC "DDRSS_PHY_1339,"
bitfld.long 0xEC 24. "PHY_CAL_DBG_CFG_0,defines debug configuration in pad calibration process" "0,1"
hexmask.long.byte 0xEC 16.--23. 1. "PHY_CAL_RCV_FINE_ADJ_0,defines adjustment for RCV code in pad calibration process"
newline
hexmask.long.byte 0xEC 8.--15. 1. "PHY_CAL_PD_FINE_ADJ_0,defines adjustment for PD code in pad calibration process"
hexmask.long.byte 0xEC 0.--7. 1. "PHY_CAL_PU_FINE_ADJ_0,defines adjustment for PU code in pad calibration process"
line.long 0xF0 "DDRSS_PHY_1340,"
bitfld.long 0xF0 0. "SC_PHY_PAD_DBG_CONT_0,Allows the pad calibration state machine to advance (when in debug mode) for slice 0" "0,1"
line.long 0xF4 "DDRSS_PHY_1341,"
line.long 0xF8 "DDRSS_PHY_1342,"
hexmask.long.tbyte 0xF8 8.--27. 1. "PHY_CAL_SLOPE_ADJ_0,defines slope configure in pad calibration process"
hexmask.long.byte 0xF8 0.--6. 1. "PHY_ADRCTL_PVT_MAP_0,defines slope configure in pad calibration process"
line.long 0xFC "DDRSS_PHY_1343,"
hexmask.long.tbyte 0xFC 0.--19. 1. "PHY_CAL_SLOPE_ADJ_PASS2_0,defines slope configure for pass2 in pad calibration process"
line.long 0x100 "DDRSS_PHY_1344,"
hexmask.long 0x100 0.--24. 1. "PHY_CAL_TWO_PASS_CFG_0,defines cal_en configure in pad calibration process"
line.long 0x104 "DDRSS_PHY_1345,"
bitfld.long 0x104 24.--29. "PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0,Pad calibration pass1 pu results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.tbyte 0x104 0.--22. 1. "PHY_CAL_SW_CAL_CFG_0,defines firmware based pad calibration process"
line.long 0x108 "DDRSS_PHY_1346,"
bitfld.long 0x108 24.--29. "PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0,Pad calibration pass2 pd results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x108 16.--21. "PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0,Pad calibration pass2 pu results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x108 8.--12. "PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0,Pad calibration pass1 rx results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x108 0.--5. "PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0,Pad calibration pass1 pd results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10C "DDRSS_PHY_1347,"
bitfld.long 0x10C 24.--28. "PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0,Pad calibration pass1 rx results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10C 16.--21. "PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0,Pad calibration pass1 pd results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10C 8.--13. "PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0,Pad calibration pass1 pu results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10C 0.--4. "PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0,Pad calibration pass2 rx results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x110 "DDRSS_PHY_1348,"
bitfld.long 0x110 16.--20. "PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0,Pad calibration pass2 rx results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x110 8.--13. "PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0,Pad calibration pass2 pd results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x110 0.--5. "PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0,Pad calibration pass2 pu results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x114 "DDRSS_PHY_1349,"
hexmask.long.word 0x114 16.--26. 1. "PHY_PARITY_ERROR_REGIF_AC,Inject parity error to register interface signals for ac slice"
hexmask.long.word 0x114 0.--15. 1. "PHY_PAD_ATB_CTRL,Pad ATB control settings"
line.long 0x118 "DDRSS_PHY_1350,"
bitfld.long 0x118 24.--25. "PHY_AC_LPBK_ENABLE,Loopback enable for the address/control slices" "0,1,2,3"
bitfld.long 0x118 16. "PHY_AC_LPBK_OBS_SELECT,Select value to map an individual loopback address/control slice observation register to the global observation register" "0,1"
newline
bitfld.long 0x118 8. "PHY_AC_LPBK_ERR_CLEAR,Address/control loopback error clear" "0,1"
bitfld.long 0x118 0. "PHY_ADRCTL_MANUAL_UPDATE,Address/control manual update of slave delay lines" "0,1"
line.long 0x11C "DDRSS_PHY_1351,"
bitfld.long 0x11C 24.--27. "PHY_AC_PRBS_PATTERN_MASK,PRBS7 mask signal for address/control slice" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x11C 16.--22. 1. "PHY_AC_PRBS_PATTERN_START,PRBS7 start pattern for address/control slice"
newline
hexmask.long.word 0x11C 0.--8. 1. "PHY_AC_LPBK_CONTROL,Address/control slice loopback control setting"
line.long 0x120 "DDRSS_PHY_1352,"
line.long 0x124 "DDRSS_PHY_1353,"
bitfld.long 0x124 16.--21. "PHY_AC_CLK_LPBK_CONTROL,Mem clk block loopback control setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x124 8. "PHY_AC_CLK_LPBK_ENABLE,Loopback enable for mem clk blocks" "0,1"
newline
bitfld.long 0x124 0. "PHY_AC_CLK_LPBK_OBS_SELECT,Select value to map an individual loopback mem clk block observation register to the global observation register" "0,1"
line.long 0x128 "DDRSS_PHY_1354,"
bitfld.long 0x128 24. "PHY_TOP_PWR_RDC_DISABLE,top param power reduction disable" "0,1"
bitfld.long 0x128 16. "PHY_AC_PWR_RDC_DISABLE,ac slice power reduction disable" "0,1"
newline
hexmask.long.word 0x128 0.--15. 1. "PHY_AC_CLK_LPBK_RESULT_OBS,Observation register for loopback mem clk blocks"
line.long 0x12C "DDRSS_PHY_1355,"
bitfld.long 0x12C 0. "PHY_AC_SLV_DLY_CTRL_GATE_DISABLE,ac slice slv_dly_control block power reduction disable" "0,1"
line.long 0x130 "DDRSS_PHY_1356,"
line.long 0x134 "DDRSS_PHY_1357,"
bitfld.long 0x134 24.--25. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_0,Select adrctl_mstr_dly_enc for the address/control slice 0" "0,1,2,3"
bitfld.long 0x134 16.--20. "PHY_CALVL_DEVICE_MAP,Define which device's DQ feedback data bits should be used during CA training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x134 8. "PHY_LPDDR4_CONNECT,PHY is connected to LPDDR4 devices" "0,1"
hexmask.long.byte 0x134 0.--7. 1. "PHY_DATA_BYTE_ORDER_SEL_HIGH,Used to define the data slice's byte swap for CA bits"
line.long 0x138 "DDRSS_PHY_1358,"
bitfld.long 0x138 0.--1. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_1,Select adrctl_mstr_dly_enc for the address/control slice 1" "0,1,2,3"
line.long 0x13C "DDRSS_PHY_1359,"
line.long 0x140 "DDRSS_PHY_1360,"
hexmask.long 0x140 0.--25. 1. "PHY_DDL_AC_MODE,PHY Address/Control DDL BIST mode"
line.long 0x144 "DDRSS_PHY_1361,"
bitfld.long 0x144 24.--26. "PHY_ERR_MASK_EN,PHY ERROR information report mask enable" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x144 16.--23. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_AC,Specify threshold value for PHY init update tracking for AC slice"
newline
bitfld.long 0x144 8.--10. "PHY_INIT_UPDATE_CONFIG,PHY init update function configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x144 0.--5. "PHY_DDL_AC_MASK,PHY Address/Control DDL BIST mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x148 "DDRSS_PHY_1362,"
bitfld.long 0x148 0.--2. "PHY_ERR_STATUS,PHY ERROR information" "0,1,2,3,4,5,6,7"
line.long 0x14C "DDRSS_PHY_1363,"
line.long 0x150 "DDRSS_PHY_1364,"
line.long 0x154 "DDRSS_PHY_1365,"
line.long 0x158 "DDRSS_PHY_1366,"
line.long 0x15C "DDRSS_PHY_1367,"
rbitfld.long 0x15C 24.--27. "PHY_DS_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for data slice" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x15C 8.--17. 1. "PHY_AC_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for adr and ac slice"
newline
bitfld.long 0x15C 0.--1. "PHY_DLL_RST_EN,PHY DDL reset software interface enable" "0,1,2,3"
line.long 0x160 "DDRSS_PHY_1368,"
bitfld.long 0x160 24.--26. "PHY_GRP_SHIFT_OBS_SELECT,Select value to map an individual address/control group slice automatic cycle/half_cycle shift settings to the observation register" "0,1,2,3,4,5,6,7"
bitfld.long 0x160 16.--19. "PHY_GRP_SLV_DLY_ENC_OBS_SELECT,Select value to map an individual address/control group slice slave delay to the encoded value observation register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x160 8. "PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE,Memory clock bit slice DCC block power reduction disable" "0,1"
bitfld.long 0x160 0. "PHY_UPDATE_MASK,Control to disable the generation of dfi_phyupd_req and use of dfi_ctrlupd_req" "0,1"
line.long 0x164 "DDRSS_PHY_1369,"
bitfld.long 0x164 16.--18. "PHY_GRP_SHIFT_OBS,Observation register for the address/control group automatic half cycle and cycle shift values" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x164 0.--10. 1. "PHY_GRP_SLV_DLY_ENC_OBS,Observation register for all address/control group slice slave delay encoded values"
line.long 0x168 "DDRSS_PHY_1370,"
bitfld.long 0x168 24.--26. "PHY_PLL_LOCK_DEASSERT_MASK,PLL Lock de-assert Mask" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x168 8.--18. 1. "PHY_PARITY_ERROR_REGIF_PS,Injects parity error to register interface signals in param_split"
newline
bitfld.long 0x168 0. "PHY_PARITY_ERROR_INJECTION_ENABLE,Enable parity error injection" "0,1"
line.long 0x16C "DDRSS_PHY_1371,"
hexmask.long.byte 0x16C 16.--22. 1. "SC_PHY_PARITY_ERROR_INFO_WOCLR,Parity Error Info"
hexmask.long.byte 0x16C 8.--14. 1. "PHY_PARITY_ERROR_INFO_MASK,Parity Error Info Mask"
newline
hexmask.long.byte 0x16C 0.--6. 1. "PHY_PARITY_ERROR_INFO,Parity Error Info"
line.long 0x170 "DDRSS_PHY_1372,"
hexmask.long.word 0x170 16.--29. 1. "PHY_TIMEOUT_ERROR_INFO_MASK,Timeout Error Info Mask"
hexmask.long.word 0x170 0.--13. 1. "PHY_TIMEOUT_ERROR_INFO,Timeout Error Info"
line.long 0x174 "DDRSS_PHY_1373,"
bitfld.long 0x174 24.--29. "PHY_PLL_FREQUENCY_ERROR_MASK,PLL Frequency Error Info Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x174 16.--19. "PHY_PLL_FREQUENCY_ERROR,PLL Frequency Error Info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x174 0.--13. 1. "SC_PHY_TIMEOUT_ERROR_INFO_WOCLR,Timeout Error Info"
line.long 0x178 "DDRSS_PHY_1374,"
hexmask.long.word 0x178 8.--19. 1. "PHY_PLL_DSKEWCALOUT_MIN,PLL DSKEWCALOUT threshold min value"
bitfld.long 0x178 0.--5. "SC_PHY_PLL_FREQUENCY_ERROR_WOCLR,PLL_Frequency Error Info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x17C "DDRSS_PHY_1375,"
bitfld.long 0x17C 24.--25. "PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK,PLL DSKEWCALOUT threshold Error Info Mask" "0,1,2,3"
rbitfld.long 0x17C 16.--17. "PHY_PLL_DSKEWCALOUT_ERROR_INFO,PLL DSKEWCALOUT threshold Error Info" "0,1,2,3"
newline
hexmask.long.word 0x17C 0.--11. 1. "PHY_PLL_DSKEWCALOUT_MAX,PLL DSKEWCALOUT threshold max value"
line.long 0x180 "DDRSS_PHY_1376,"
hexmask.long.word 0x180 8.--16. 1. "PHY_TOP_FSM_ERROR_INFO,Top level FSM Error Info"
bitfld.long 0x180 0.--1. "SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR,PLL DSKEWCALOUT threshold Error Info" "0,1,2,3"
line.long 0x184 "DDRSS_PHY_1377,"
hexmask.long.word 0x184 16.--24. 1. "SC_PHY_TOP_FSM_ERROR_INFO_WOCLR,Top level FSM Error Info"
hexmask.long.word 0x184 0.--8. 1. "PHY_TOP_FSM_ERROR_INFO_MASK,Top level FSM Error Info Mask"
line.long 0x188 "DDRSS_PHY_1378,"
hexmask.long.word 0x188 16.--25. 1. "PHY_FSM_TRANSIENT_ERROR_INFO_MASK,Accumulated Top level FSM Error Info Mask"
hexmask.long.word 0x188 0.--9. 1. "PHY_FSM_TRANSIENT_ERROR_INFO,Accumulated Top level FSM Error Info"
line.long 0x18C "DDRSS_PHY_1379,"
bitfld.long 0x18C 24.--25. "PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK,Training/Calibration Error Info Mask for TOP" "0,1,2,3"
rbitfld.long 0x18C 16.--17. "PHY_TOP_TRAIN_CALIB_ERROR_INFO,Training/Calibration Error Info for TOP" "0,1,2,3"
newline
hexmask.long.word 0x18C 0.--9. 1. "SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR,Accumulated Top level FSM Error Info"
line.long 0x190 "DDRSS_PHY_1380,"
hexmask.long.byte 0x190 24.--30. 1. "SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR,Training/Calibration Error Info"
hexmask.long.byte 0x190 16.--22. 1. "PHY_TRAIN_CALIB_ERROR_INFO_MASK,Training/Calibration Error Info Mask"
newline
hexmask.long.byte 0x190 8.--14. 1. "PHY_TRAIN_CALIB_ERROR_INFO,Training/Calibration Error Info"
bitfld.long 0x190 0.--1. "SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR,Training/Calibration Error Info for TOP" "0,1,2,3"
line.long 0x194 "DDRSS_PHY_1381,"
bitfld.long 0x194 8.--13. "PHY_GLOBAL_ERROR_INFO_MASK,Global Error Info Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x194 0.--5. "PHY_GLOBAL_ERROR_INFO,Global Error Info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x198 "DDRSS_PHY_1382,"
hexmask.long.tbyte 0x198 0.--19. 1. "PHY_TRAINING_TIMEOUT_VALUE,Training timeout value"
line.long 0x19C "DDRSS_PHY_1383,"
hexmask.long.tbyte 0x19C 0.--19. 1. "PHY_INIT_TIMEOUT_VALUE,Init or DFS timeout value"
line.long 0x1A0 "DDRSS_PHY_1384,"
hexmask.long.word 0x1A0 0.--15. 1. "PHY_LP_TIMEOUT_VALUE,DFI LP timeout value"
line.long 0x1A4 "DDRSS_PHY_1385,"
line.long 0x1A8 "DDRSS_PHY_1386,"
bitfld.long 0x1A8 24.--28. "PHY_PLL_LOCK_0_MIN_VALUE,PLL min timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.tbyte 0x1A8 0.--19. 1. "PHY_PHYMSTR_TIMEOUT_VALUE,DFI PHYMSTR timeout value"
line.long 0x1AC "DDRSS_PHY_1387,"
bitfld.long 0x1AC 24.--27. "PHY_PLL_FREQUENCY_DELTA,Acceptable PLL frequency delta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 16.--23. 1. "PHY_RDDATA_VALID_TIMEOUT_VALUE,RDDATA VALID timeout value"
newline
hexmask.long.word 0x1AC 0.--15. 1. "PHY_PLL_LOCK_TIMEOUT_VALUE,PLL max timeout value"
line.long 0x1B0 "DDRSS_PHY_1388,"
hexmask.long.word 0x1B0 16.--29. 1. "PHY_ADRCTL_FSM_ERROR_INFO_0,ADRCTL slice level FSM Error Info"
hexmask.long.word 0x1B0 0.--15. 1. "PHY_PLL_FREQUENCY_COMPARE_INTERVAL,PLL Frequency compare interval"
line.long 0x1B4 "DDRSS_PHY_1389,"
hexmask.long.word 0x1B4 16.--29. 1. "SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0,ADRCTL Slice level FSM Error Info"
hexmask.long.word 0x1B4 0.--13. 1. "PHY_ADRCTL_FSM_ERROR_INFO_MASK_0,ADRCTL Slice level FSM Error Info Mask"
line.long 0x1B8 "DDRSS_PHY_1390,"
hexmask.long.word 0x1B8 16.--29. 1. "PHY_ADRCTL_FSM_ERROR_INFO_MASK_1,ADRCTL Slice level FSM Error Info Mask"
hexmask.long.word 0x1B8 0.--13. 1. "PHY_ADRCTL_FSM_ERROR_INFO_1,ADRCTL slice level FSM Error Info"
line.long 0x1BC "DDRSS_PHY_1391,"
hexmask.long.word 0x1BC 16.--29. 1. "PHY_MEMCLK_FSM_ERROR_INFO_0,MEMCLK slice level FSM Error Info"
hexmask.long.word 0x1BC 0.--13. 1. "SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1,ADRCTL Slice level FSM Error Info"
line.long 0x1C0 "DDRSS_PHY_1392,"
hexmask.long.word 0x1C0 16.--29. 1. "SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0,MEMCLK Slice level FSM Error Info"
hexmask.long.word 0x1C0 0.--13. 1. "PHY_MEMCLK_FSM_ERROR_INFO_MASK_0,MEMCLK Slice level FSM Error Info Mask"
line.long 0x1C4 "DDRSS_PHY_1393,"
hexmask.long.tbyte 0x1C4 0.--17. 1. "PHY_PAD_CAL_IO_CFG_0,Pad calibration Controls PCLK/PARK pin and vref switch"
line.long 0x1C8 "DDRSS_PHY_1394,"
hexmask.long.word 0x1C8 0.--13. 1. "PHY_PAD_ACS_IO_CFG,Controls PCLK/PARK pin for acs pad"
line.long 0x1CC "DDRSS_PHY_1395,"
bitfld.long 0x1CC 0. "PHY_PLL_BYPASS,PHY clock PLL bypass select" "0,1"
line.long 0x1D0 "DDRSS_PHY_1396,"
bitfld.long 0x1D0 16. "PHY_LOW_FREQ_SEL,Enables the PHY to enter/exit the PLL domain from the negative clock edge" "0,1"
hexmask.long.word 0x1D0 0.--12. 1. "PHY_PLL_CTRL,PHY clock PLL controls"
line.long 0x1D4 "DDRSS_PHY_1397,"
bitfld.long 0x1D4 24.--27. "PHY_CSLVL_DLY_STEP,Sets the delay step size plus 1 during CS training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1D4 16.--19. "PHY_CSLVL_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1D4 0.--11. 1. "PHY_PAD_VREF_CTRL_AC,Pad VREF control settings for the address/control"
line.long 0x1D8 "DDRSS_PHY_1398,"
bitfld.long 0x1D8 24. "PHY_LVL_MEAS_DLY_STEP_ENABLE,Enables the phy_adr_meas_dly_step_value to be used instead of the phy_cslvl_dly_step parameter" "0,1"
bitfld.long 0x1D8 16. "PHY_SW_CSLVL_DVW_MIN_EN,Enables the software override data valid window size during CS training" "0,1"
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hexmask.long.word 0x1D8 0.--8. 1. "PHY_SW_CSLVL_DVW_MIN,Sets the software override data valid window size during CS training"
line.long 0x1DC "DDRSS_PHY_1399,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_GRP1_SLAVE_DELAY_0,Address slice slave delay setting for address slice 1"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_0,Address slice slave delay setting for address slice 0"
line.long 0x1E0 "DDRSS_PHY_1400,"
hexmask.long.word 0x1E0 16.--26. 1. "PHY_GRP3_SLAVE_DELAY_0,Address slice slave delay setting for address slice 3"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_0,Address slice slave delay setting for address slice 2"
line.long 0x1E4 "DDRSS_PHY_1401,"
hexmask.long.word 0x1E4 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_1,Address slice slave delay setting for address slice 0"
line.long 0x1E8 "DDRSS_PHY_1402,"
hexmask.long.word 0x1E8 0.--10. 1. "PHY_GRP1_SLAVE_DELAY_1,Address slice slave delay setting for address slice 1"
line.long 0x1EC "DDRSS_PHY_1403,"
hexmask.long.word 0x1EC 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_1,Address slice slave delay setting for address slice 2"
line.long 0x1F0 "DDRSS_PHY_1404,"
hexmask.long.word 0x1F0 0.--10. 1. "PHY_GRP3_SLAVE_DELAY_1,Address slice slave delay setting for address slice 3"
line.long 0x1F4 "DDRSS_PHY_1405,"
bitfld.long 0x1F4 0.--2. "PHY_CLK_DC_CAL_CLK_SEL,Determines DCC CAL clock" "0,1,2,3,4,5,6,7"
line.long 0x1F8 "DDRSS_PHY_1406,"
hexmask.long 0x1F8 0.--29. 1. "PHY_PAD_FDBK_DRIVE,Controls drive settings for gate feedback pads"
line.long 0x1FC "DDRSS_PHY_1407,"
hexmask.long.tbyte 0x1FC 0.--17. 1. "PHY_PAD_FDBK_DRIVE2,Controls drive settings (enslice/boost) for gate feedback pads"
line.long 0x200 "DDRSS_PHY_1408,"
hexmask.long 0x200 0.--30. 1. "PHY_PAD_DATA_DRIVE,Controls drive settings for data pads"
line.long 0x204 "DDRSS_PHY_1409,"
line.long 0x208 "DDRSS_PHY_1410,"
hexmask.long 0x208 0.--29. 1. "PHY_PAD_ADDR_DRIVE,Controls drive settings for the address/control pads"
line.long 0x20C "DDRSS_PHY_1411,"
hexmask.long 0x20C 0.--26. 1. "PHY_PAD_ADDR_DRIVE2,Controls drive settings for the address/control pads"
line.long 0x210 "DDRSS_PHY_1412,"
line.long 0x214 "DDRSS_PHY_1413,"
hexmask.long.tbyte 0x214 0.--17. 1. "PHY_PAD_CLK_DRIVE2,Controls drive settings for clock pads"
line.long 0x218 "DDRSS_PHY_1414,"
hexmask.long 0x218 0.--29. 1. "PHY_PAD_CKE_DRIVE,Controls drive settings for cke pads"
line.long 0x21C "DDRSS_PHY_1415,"
hexmask.long 0x21C 0.--26. 1. "PHY_PAD_CKE_DRIVE2,Controls drive settings for cke pads"
line.long 0x220 "DDRSS_PHY_1416,"
hexmask.long 0x220 0.--29. 1. "PHY_PAD_RST_DRIVE,Controls drive settings for reset_n pads"
line.long 0x224 "DDRSS_PHY_1417,"
hexmask.long 0x224 0.--26. 1. "PHY_PAD_RST_DRIVE2,Controls drive settings for reset_n pads"
line.long 0x228 "DDRSS_PHY_1418,"
hexmask.long 0x228 0.--29. 1. "PHY_PAD_CS_DRIVE,Controls drive settings for cs pads"
line.long 0x22C "DDRSS_PHY_1419,"
hexmask.long 0x22C 0.--26. 1. "PHY_PAD_CS_DRIVE2,Controls drive settings for cs pads"
line.long 0x230 "DDRSS_PHY_1420,"
hexmask.long 0x230 0.--29. 1. "PHY_PAD_ODT_DRIVE,Controls drive settings for odt pads"
line.long 0x234 "DDRSS_PHY_1421,"
hexmask.long 0x234 0.--26. 1. "PHY_PAD_ODT_DRIVE2,Controls drive settings for odt pads"
line.long 0x238 "DDRSS_PHY_1422,"
hexmask.long.byte 0x238 24.--30. 1. "PHY_CAL_SETTLING_PRD_0,Number of clock cycles to extend dfi_phyupd_req after the ack is received for settling of final values"
hexmask.long.word 0x238 8.--23. 1. "PHY_CAL_VREF_SWITCH_TIMER_0,The settling time for a switch in VREF during IO pad calibration"
newline
bitfld.long 0x238 0.--2. "PHY_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for block 0" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "DDR_PHY"
tree "COMPUTE_CLUSTER0_CTL_CFG_PHY"
base ad:0x2990000
group.long 0x4000++0x22F
line.long 0x00 "DDRSS_PHY_0,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_0,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_0,Write data clock bypass mode slave delay setting for slice 0.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_1,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_0,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0,Write DQS bypass mode slave delay setting for slice 0"
line.long 0x08 "DDRSS_PHY_2,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for slice 0" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_0,Two_cycle_preamble for bypass mode for slice 0" "0,1,2,3"
newline
hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0,Read DQS bypass mode slave delay setting for slice 0"
line.long 0x0C "DDRSS_PHY_3,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_4,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_5,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_0,When set a register write will update parameters for all ranks at the same time in slice 0" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_0,Per-rank CS map for slice 0" "0,1,2,3"
newline
bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_0,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_6,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_0,For per-rank training indicates which rank's paramters are read/written for slice 0" "0,1"
line.long 0x1C "DDRSS_PHY_7,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0,For LPDDR4 boot frequency write path clock gating disable for slice 0" "0,1,2,3"
newline
bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_0,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_8,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_0,Loopback read only test timeout mechanism enable for slice 0" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_0,Loopback control bits for slice 0"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_0,Loopback control en for slice 0" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_9,"
line.long 0x28 "DDRSS_PHY_10,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_0,Observation register for the auto_timing_margin for slice 0"
line.long 0x2C "DDRSS_PHY_11,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_0,Read Leveling Multi-pattern enable for slice 0" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_0,PRBS7 mask signal for slice 0"
newline
hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_0,PRBS7 start pattern for slice 0"
line.long 0x30 "DDRSS_PHY_12,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_0,Observation register for best vref value for slice 0"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_0,Data slice initial VREF training step size for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_0,Read Leveling read level windows disable reset for slice 0" "0,1"
line.long 0x34 "DDRSS_PHY_13,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for slice 0" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_0,Number of cycles to wait for the DQS gate to close before flagging an error for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0,Read DQS data clock bypass mode slave delay setting for slice 0"
line.long 0x38 "DDRSS_PHY_14,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_0,Indicates the type of DRAM for slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_0,Adds a cycle of delay for the slice 0 to match the address slice" "0,1"
newline
hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 0"
line.long 0x3C "DDRSS_PHY_15,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_0,Control the on-the-fly gate adjustment for slice 0" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_0,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 0"
line.long 0x40 "DDRSS_PHY_16,"
line.long 0x44 "DDRSS_PHY_17,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_0,Controls the read postamble extension for LPDDR4 for slice 0" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_0,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 0" "0,1"
line.long 0x48 "DDRSS_PHY_18,"
line.long 0x4C "DDRSS_PHY_19,"
line.long 0x50 "DDRSS_PHY_20,"
line.long 0x54 "DDRSS_PHY_21,"
line.long 0x58 "DDRSS_PHY_22,"
line.long 0x5C "DDRSS_PHY_23,"
line.long 0x60 "DDRSS_PHY_24,"
line.long 0x64 "DDRSS_PHY_25,"
line.long 0x68 "DDRSS_PHY_26,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_0,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_0,Disables automatic reset of the read entry FIFO pointers for slice 0" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_0,Reserved for future use for slice 0" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_27,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_0,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_0,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_0,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_0,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_28,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_0,Observation register for write leveling status for slice 0"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_0,Write leveling algorithm selection for slice 0" "0,1,2,3"
newline
bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_0,Allows the leveling state machine to advance (when in debug mode) for slice 0" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_0,Enables leveling debug mode for slice 0" "0,1"
line.long 0x74 "DDRSS_PHY_29,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_0,For ECC slice should set this register to do DQ bit mask for slice 0"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_30,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_0,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_0,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 0"
line.long 0x7C "DDRSS_PHY_31,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_0,Read leveling algorithm select for slice 0" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_0,Number of samples to take at each DQS slave delay setting during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_32,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_0,Defines the minimum gap requirment for the LE and TE window for slice 0"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_0,Per-bit mask for read leveling for slice 0"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 0"
line.long 0x84 "DDRSS_PHY_33,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_0,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0,Defines the write/read burst length in bytes during the write data leveling sequence for slice 0"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_0,Defines the training patterns to be used during the write data leveling sequence for slice 0" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_34,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_0,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 0" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_0,Select value to map specific information during or post periodic write data leveling for slice 0"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_0,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_35,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_0,Per-bit mask for write data leveling for slice 0"
line.long 0x90 "DDRSS_PHY_36,"
line.long 0x94 "DDRSS_PHY_37,"
line.long 0x98 "DDRSS_PHY_38,"
line.long 0x9C "DDRSS_PHY_39,"
line.long 0xA0 "DDRSS_PHY_40,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_0,Control for single pass only No-Topology training for slice 0" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_0,User-defined pattern to be used during write data leveling for slice 0"
line.long 0xA4 "DDRSS_PHY_41,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_0,Threshold Criteria of period threshold after No-Topology training is completed for slice 0"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_0,Threshold Criteria of early threshold after No-Topology training is completed for slice 0"
line.long 0xA8 "DDRSS_PHY_42,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_0,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 0"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_0,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 0"
line.long 0xAC "DDRSS_PHY_43,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_0,Observation register containing read entry FIFO pointers for slice 0"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_0,Manual reset/clear of internal logic for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_0,Indicates if slice 0 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_44,"
line.long 0xB4 "DDRSS_PHY_45,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for slice 0"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for slice 0"
line.long 0xB8 "DDRSS_PHY_46,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 0"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_0,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 0"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS base slave delay encoded value for slice 0"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_0,Observation register containing read DQ slave delay encoded values for slice 0"
line.long 0xBC "DDRSS_PHY_47,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQS base slave delay encoded value for slice 0"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0,Observation register containing read DQS gate slave delay encoded value for slice 0"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 0"
line.long 0xC0 "DDRSS_PHY_48,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing write adder slave delay encoded value for slice 0"
newline
hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0,Observation register containing write DQ base slave delay encoded value for slice 0"
line.long 0xC4 "DDRSS_PHY_49,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_0,Observation register containing write leveling first hard 1 DQS slave delay for slice 0"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_0,Observation register containing write leveling last hard 0 DQS slave delay for slice 0"
line.long 0xC8 "DDRSS_PHY_50,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_0,Observation register containing write leveling status for slice 0"
line.long 0xCC "DDRSS_PHY_51,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0,Observation register containing gate sample2 slave delay encoded values for slice 0"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0,Observation register containing gate sample1 slave delay encoded values for slice 0"
line.long 0xD0 "DDRSS_PHY_52,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_0,Observation register containing gate training first hard 0 DQS slave delay for slice 0"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_0,Observation register containing write leveling error status for slice 0"
line.long 0xD4 "DDRSS_PHY_53,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_0,Observation register containing gate training last hard 1 DQS slave delay for slice 0"
line.long 0xD8 "DDRSS_PHY_54,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_0,Observation register containing gate training status for slice 0"
line.long 0xDC "DDRSS_PHY_55,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0,Observation register containing read leveling data window trailing edge slave delay setting for slice 0"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0,Observation register containing read leveling data window leading edge slave delay setting for slice 0"
line.long 0xE0 "DDRSS_PHY_56,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0,Observation register containing read leveling number of windows found for slice 0" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_57,"
line.long 0xE8 "DDRSS_PHY_58,"
line.long 0xEC "DDRSS_PHY_59,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_0,Observation register containing write data leveling data window trailing edge slave delay setting for slice 0"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_0,Observation register containing write data leveling data window leading edge slave delay setting for slice 0"
line.long 0xF0 "DDRSS_PHY_60,"
line.long 0xF4 "DDRSS_PHY_61,"
line.long 0xF8 "DDRSS_PHY_62,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_0,DDL mode for slice 0"
line.long 0xFC "DDRSS_PHY_63,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_0,DDL mask for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_64,"
line.long 0x104 "DDRSS_PHY_65,"
line.long 0x108 "DDRSS_PHY_66,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_0,Manual setting of RX Calibration enable for slice 0" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_0,Manual RX Calibration start for slice 0" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_0,LPDDR4 write preamble extension enable for slice 0" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_0,Specify threshold value for PHY init update tracking for slice 0"
line.long 0x10C "DDRSS_PHY_67,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_0,RX Calibration codes for DQ0 for slice 0"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0,Data slice power reduction disable for slice 0" "0,1"
newline
hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_0,RX Calibration state machine wait count for slice 0"
line.long 0x110 "DDRSS_PHY_68,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_0,RX Calibration codes for DQ2 for slice 0"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_0,RX Calibration codes for DQ1 for slice 0"
line.long 0x114 "DDRSS_PHY_69,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_0,RX Calibration codes for DQ4 for slice 0"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_0,RX Calibration codes for DQ3 for slice 0"
line.long 0x118 "DDRSS_PHY_70,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_0,RX Calibration codes for DQ6 for slice 0"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_0,RX Calibration codes for DQ5 for slice 0"
line.long 0x11C "DDRSS_PHY_71,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_0,RX Calibration codes for DQ7 for slice 0"
line.long 0x120 "DDRSS_PHY_72,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_0,RX Calibration codes for DM for slice 0"
line.long 0x124 "DDRSS_PHY_73,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_0,RX Calibration codes for FDBK for slice 0"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_0,RX Calibration codes for DQS for slice 0"
line.long 0x128 "DDRSS_PHY_74,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_0,RX Calibration lock results for slice 0"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_0,RX Calibration results for slice 0"
line.long 0x12C "DDRSS_PHY_75,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_0,Expected C value from RX pad for slice 0" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_0,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_0,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_0,RX CAL disable signal for slice 0 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_76,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_0,Controls RX_BIAS_EN pin for each pad for slice 0"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_0,RX offset calibration mask of all RX pad for slice 0"
line.long 0x134 "DDRSS_PHY_77,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_0,Determines weight of average calculating for slice 0" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_0,Determines timeout number of iteration for slice 0"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_0,Determines number of cycles to wait for each sample for slice 0"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_0,Control to disable toggle during static activity for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_78,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_0,Adjust direction for slice 0" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_0,Duty cycle adjust threshold around the mid-point for slice 0"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_0,Duty cycle adjust sample count for slice 0"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_0,Duty cycle adjust starting value for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_79,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_0,Shutoff gate feedback IO to reduce power for slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_0,Rank selection for software based duty cycle correction for slice 0" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_0,Manual trigger for DCC for slice 0" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_0,Calibration polarity for slice 0" "0,1"
line.long 0x140 "DDRSS_PHY_80,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_0,Data slice power reduction disable for slice 0" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0,Data slice DCC and RX_CAL block power reduction disable for slice 0" "0,1"
newline
bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_0,Data slice read path power reduction disable for slice 0" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_0,Data slice slv_dly_control block power reduction disable for slice 0" "0,1"
line.long 0x144 "DDRSS_PHY_81,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_0,Data slice level FSM Error Info for slice 0"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_0,Inject parity error to register interface signals for slice 0"
line.long 0x148 "DDRSS_PHY_82,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0,Data slice level FSM Error Info for slice 0"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_0,Data slice level FSM Error Info Mask for slice 0"
line.long 0x14C "DDRSS_PHY_83,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0,Data slice level training/calibration Error Info for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0,Data slice level training/calibration Error Info Mask for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_0,Data slice level training/calibration Error Info for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_84,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_0,Operation type tsel enables for DQS signals for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_0,Operation type tsel select values for DQ/DM signals for slice 0"
newline
bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_0,Operation type tsel enables for DQ/DM signals for slice 0" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_85,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_0,Data slice initial VREF training start value for slice 0"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_0,2 cycle preamble support for slice 0" "0,1,2,3"
newline
hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_0,Operation type tsel select values for DQS signals for slice 0"
line.long 0x158 "DDRSS_PHY_86,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_0,Step size of WR DQ slave delay during No-Topology training for slice 0"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_0,Enable for No-Topology training for slice 0" "0,1"
newline
bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_0,Data slice vref training enable control for slice 0" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_0,Data slice initial VREF training stop value for slice 0"
line.long 0x15C "DDRSS_PHY_87,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_0,End of WR DQ slave delay in No-Topology training for slice 0"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_0,Starting WR DQ slave delay in No-Topology training for slice 0"
line.long 0x160 "DDRSS_PHY_88,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_0,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 0" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_0,Enable Bit for WR DQ during No-Topology training for slice 0"
line.long 0x164 "DDRSS_PHY_89,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_0,Controls TX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_0,Enable for fast multi-pattern window search for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_90,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_91,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_0,Controls RX_DCD pin for dm pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_0,Controls RX_DCD pin for each pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_92,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_0,Controls PCLK/PARK pin for pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_0,Controls RX_DCD pin for fdbk pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_0,Controls RX_DCD pin for dqs pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_93,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_0,Read DQ1 slave delay setting for slice 0"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_0,Read DQ0 slave delay setting for slice 0"
line.long 0x178 "DDRSS_PHY_94,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_0,Read DQ3 slave delay setting for slice 0"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_0,Read DQ2 slave delay setting for slice 0"
line.long 0x17C "DDRSS_PHY_95,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_0,Read DQ5 slave delay setting for slice 0"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_0,Read DQ4 slave delay setting for slice 0"
line.long 0x180 "DDRSS_PHY_96,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_0,Read DQ7 slave delay setting for slice 0"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_0,Read DQ6 slave delay setting for slice 0"
line.long 0x184 "DDRSS_PHY_97,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_0,Determines DCC CAL clock for slice 0" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_0,Read DM/DBI slave delay setting for slice 0"
line.long 0x188 "DDRSS_PHY_98,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_0,Start/end timing values for DQS output enable signals for slice 0"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_0,Start/end timing values for DQ/DM write based termination enable and select signals for slice 0"
newline
hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_0,Start/end timing values for DQ/DM read based termination enable and select signals for slice 0"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_0,Start/end timing values for DQ/DM output enable signals for slice 0"
line.long 0x18C "DDRSS_PHY_99,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_0,Start/end timing values for DQS write based termination enable and select signals for slice 0"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_0,Start/end timing values for DQS read based OE extension for slice 0"
newline
hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_0,Start/end timing values for DQS read based termination enable and select signals for slice 0"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_0,Feedback pad's OPAD and IPAD delay timing for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_100,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_0,Pad VREF control settings for DQ slice 0"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_0,Number of cycles for vref settle after setting is changed for slice 0"
line.long 0x194 "DDRSS_PHY_101,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_0,Start/end timing values for DQS input enable signals for slice 0"
newline
hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_0,Start/end timing values for DQ/DM input enable signals for slice 0"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_0,Enables the per-rank training and read/write timing capabilities for slice 0" "0,1"
line.long 0x198 "DDRSS_PHY_102,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_0,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_0,DBI mode for slice 0" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_0,Input enable mode bits for slice 0" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_103,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for slice 0"
newline
bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_0,Master delay line override settings for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_104,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_0,DQS slave delay step size during write leveling for slice 0"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_0,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 0"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for slice 0"
line.long 0x1A4 "DDRSS_PHY_105,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_0,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_0,DQS slave delay step size during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_0,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_0,DQS slave delay fine step size during write leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_106,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_0,Final backup step delay used in gate training algorithm for slice 0"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_0,Interim backup step delay used in gate training algorithm for slice 0"
line.long 0x1AC "DDRSS_PHY_107,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_0,DQS slave delay step size during read leveling for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_0,Support the toggle read preamble for LPDDR4 for slice 0" "0,1"
newline
bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_0,Defines the step granularity for the logic to use once an edge is found for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_0,DQ slave delay step size during write data leveling for slice 0"
line.long 0x1B0 "DDRSS_PHY_108,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_0,The maximun rdlvl slave delay search window for read eye training for slice 0"
line.long 0x1B4 "DDRSS_PHY_109,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_0,Peridic training start point offset for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_0,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 0" "0,1"
newline
hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_0,Minimum data valid window across DQs and ranks for slice 0"
line.long 0x1B8 "DDRSS_PHY_110,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_0,Disable duty cycle adjust at initialization for slice 0" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_0,Write path clock gating timing for slice 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_0,Write path clock gating disable for slice 0" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_111,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_0,Initial value of write DQ slave delay for slice 0"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_0,Initial value of write DQS slave delay for slice 0"
line.long 0x1C0 "DDRSS_PHY_112,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0,Clock measurement cell threshold offset for differential signals for slice 0"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_0,Clock measurement cell threshold offset for single ended signals for slice 0"
newline
bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_0,Enable duty cycle adjust during write DQ training for slice 0" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_0,Enable duty cycle adjust during write leveling for slice 0" "0,1"
line.long 0x1C4 "DDRSS_PHY_113,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_0,Number of cycles that the dfi_rddata_en signal is early for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_0,Data slice training step definition using phy_meas_dly_step_value for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_0,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 0"
line.long 0x1C8 "DDRSS_PHY_114,"
line.long 0x1CC "DDRSS_PHY_115,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_0,DQ/DM bit swizzling 1 for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_116,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_0,Write clock slave delay setting for DQ1 for slice 0"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_0,Write clock slave delay setting for DQ0 for slice 0"
line.long 0x1D4 "DDRSS_PHY_117,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_0,Write clock slave delay setting for DQ3 for slice 0"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_0,Write clock slave delay setting for DQ2 for slice 0"
line.long 0x1D8 "DDRSS_PHY_118,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_0,Write clock slave delay setting for DQ5 for slice 0"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_0,Write clock slave delay setting for DQ4 for slice 0"
line.long 0x1DC "DDRSS_PHY_119,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_0,Write clock slave delay setting for DQ7 for slice 0"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_0,Write clock slave delay setting for DQ6 for slice 0"
line.long 0x1E0 "DDRSS_PHY_120,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_0,Write clock slave delay setting for DQS for slice 0"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_0,Write clock slave delay setting for DM for slice 0"
line.long 0x1E4 "DDRSS_PHY_121,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ0 for slice 0"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_0,Write level threshold adjust value based on those thresholds for DQS for slice 0" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_122,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ1 for slice 0"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ0 for slice 0"
line.long 0x1EC "DDRSS_PHY_123,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ2 for slice 0"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ1 for slice 0"
line.long 0x1F0 "DDRSS_PHY_124,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ3 for slice 0"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ2 for slice 0"
line.long 0x1F4 "DDRSS_PHY_125,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ4 for slice 0"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ3 for slice 0"
line.long 0x1F8 "DDRSS_PHY_126,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ5 for slice 0"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ4 for slice 0"
line.long 0x1FC "DDRSS_PHY_127,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ6 for slice 0"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ5 for slice 0"
line.long 0x200 "DDRSS_PHY_128,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DQ7 for slice 0"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ6 for slice 0"
line.long 0x204 "DDRSS_PHY_129,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_0,Rising edge read DQS slave delay setting for DM for slice 0"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DQ7 for slice 0"
line.long 0x208 "DDRSS_PHY_130,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_0,Read DQS slave delay setting for slice 0"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_0,Falling edge read DQS slave delay setting for DM for slice 0"
line.long 0x20C "DDRSS_PHY_131,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_0,Write level delay threshold above which will be considered in previous cycle for slice 0"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_0,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_0,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_132,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_0,Force the final write level delay value (that meets the early threshold) to 0 for slice 0" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0,Write level delay threshold below which will add a cycle of write path latency for slice 0"
line.long 0x214 "DDRSS_PHY_133,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_0,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_0,Initial read DQS gate slave delay setting during gate training for slice 0"
line.long 0x218 "DDRSS_PHY_134,"
bitfld.long 0x218 24. "PHY_NTP_PASS_0,Indicates if No-topology training found a passing result for slice 0" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_0,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_0,Initial DQ/DM slave delay setting during write data leveling for slice 0"
line.long 0x21C "DDRSS_PHY_135,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0,Read leveling starting value for the DQS/DQ slave delay settings for slice 0"
line.long 0x220 "DDRSS_PHY_136,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
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hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
line.long 0x224 "DDRSS_PHY_137,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
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hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
line.long 0x228 "DDRSS_PHY_138,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_0,Setting for boost P/N of pad for slice 0"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
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hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_0,Adjust value of Duty Cycle Adjuster for slice 0"
line.long 0x22C "DDRSS_PHY_139,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_0,TX_FFE setting for DQS pad for slice 0" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_0,TX_FFE setting for DQ/DM pad for slice 0" "0,1,2,3"
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bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_0,Setting for RX ctle P/N of pad for slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4400++0x22F
line.long 0x00 "DDRSS_PHY_256,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_1,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_1,Write data clock bypass mode slave delay setting for slice 1.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_257,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_1,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1,Write DQS bypass mode slave delay setting for slice 1"
line.long 0x08 "DDRSS_PHY_258,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_1,Bypass mode override setting for slice 1" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_1,Two_cycle_preamble for bypass mode for slice 1" "0,1,2,3"
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hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1,Read DQS bypass mode slave delay setting for slice 1"
line.long 0x0C "DDRSS_PHY_259,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_260,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_261,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_1,When set a register write will update parameters for all ranks at the same time in slice 1" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_1,Per-rank CS map for slice 1" "0,1,2,3"
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bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_1,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_262,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_1,For per-rank training indicates which rank's paramters are read/written for slice 1" "0,1"
line.long 0x1C "DDRSS_PHY_263,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1,For LPDDR4 boot frequency write path clock gating disable for slice 1" "0,1,2,3"
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bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_1,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_264,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_1,Loopback read only test timeout mechanism enable for slice 1" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_1,Loopback control bits for slice 1"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_1,Loopback control en for slice 1" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_265,"
line.long 0x28 "DDRSS_PHY_266,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_1,Observation register for the auto_timing_margin for slice 1"
line.long 0x2C "DDRSS_PHY_267,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_1,Read Leveling Multi-pattern enable for slice 1" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_1,PRBS7 mask signal for slice 1"
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hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_1,PRBS7 start pattern for slice 1"
line.long 0x30 "DDRSS_PHY_268,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_1,Observation register for best vref value for slice 1"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_1,Data slice initial VREF training step size for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_1,Read Leveling read level windows disable reset for slice 1" "0,1"
line.long 0x34 "DDRSS_PHY_269,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_1,Initiates a snapshot of the internal observation registers for slice 1" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_1,Number of cycles to wait for the DQS gate to close before flagging an error for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1,Read DQS data clock bypass mode slave delay setting for slice 1"
line.long 0x38 "DDRSS_PHY_270,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_1,Indicates the type of DRAM for slice 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_1,Adds a cycle of delay for the slice 1 to match the address slice" "0,1"
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hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 1"
line.long 0x3C "DDRSS_PHY_271,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_1,Control the on-the-fly gate adjustment for slice 1" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_1,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 1"
line.long 0x40 "DDRSS_PHY_272,"
line.long 0x44 "DDRSS_PHY_273,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_1,Controls the read postamble extension for LPDDR4 for slice 1" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_1,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 1" "0,1"
line.long 0x48 "DDRSS_PHY_274,"
line.long 0x4C "DDRSS_PHY_275,"
line.long 0x50 "DDRSS_PHY_276,"
line.long 0x54 "DDRSS_PHY_277,"
line.long 0x58 "DDRSS_PHY_278,"
line.long 0x5C "DDRSS_PHY_279,"
line.long 0x60 "DDRSS_PHY_280,"
line.long 0x64 "DDRSS_PHY_281,"
line.long 0x68 "DDRSS_PHY_282,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_1,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_1,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_1,Disables automatic reset of the read entry FIFO pointers for slice 1" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_1,Reserved for future use for slice 1" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_283,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_1,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_1,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_1,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_1,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_284,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_1,Observation register for write leveling status for slice 1"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_1,Write leveling algorithm selection for slice 1" "0,1,2,3"
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bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_1,Allows the leveling state machine to advance (when in debug mode) for slice 1" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_1,Enables leveling debug mode for slice 1" "0,1"
line.long 0x74 "DDRSS_PHY_285,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_1,For ECC slice should set this register to do DQ bit mask for slice 1"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_286,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_1,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_1,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 1"
line.long 0x7C "DDRSS_PHY_287,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_1,Read leveling algorithm select for slice 1" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_1,Number of samples to take at each DQS slave delay setting during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_288,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_1,Defines the minimum gap requirment for the LE and TE window for slice 1"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_1,Per-bit mask for read leveling for slice 1"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 1"
line.long 0x84 "DDRSS_PHY_289,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_1,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1,Defines the write/read burst length in bytes during the write data leveling sequence for slice 1"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_1,Defines the training patterns to be used during the write data leveling sequence for slice 1" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_290,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_1,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 1" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_1,Select value to map specific information during or post periodic write data leveling for slice 1"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_1,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_291,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_1,Per-bit mask for write data leveling for slice 1"
line.long 0x90 "DDRSS_PHY_292,"
line.long 0x94 "DDRSS_PHY_293,"
line.long 0x98 "DDRSS_PHY_294,"
line.long 0x9C "DDRSS_PHY_295,"
line.long 0xA0 "DDRSS_PHY_296,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_1,Control for single pass only No-Topology training for slice 1" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_1,User-defined pattern to be used during write data leveling for slice 1"
line.long 0xA4 "DDRSS_PHY_297,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_1,Threshold Criteria of period threshold after No-Topology training is completed for slice 1"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_1,Threshold Criteria of early threshold after No-Topology training is completed for slice 1"
line.long 0xA8 "DDRSS_PHY_298,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_1,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 1"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_1,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 1"
line.long 0xAC "DDRSS_PHY_299,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_1,Observation register containing read entry FIFO pointers for slice 1"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_1,Manual reset/clear of internal logic for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_1,Indicates if slice 1 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_300,"
line.long 0xB4 "DDRSS_PHY_301,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_1,Observation register containing master delay results for slice 1"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_1,Observation register containing total number of loopback error data for slice 1"
line.long 0xB8 "DDRSS_PHY_302,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 1"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_1,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 1"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS base slave delay encoded value for slice 1"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_1,Observation register containing read DQ slave delay encoded values for slice 1"
line.long 0xBC "DDRSS_PHY_303,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQS base slave delay encoded value for slice 1"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1,Observation register containing read DQS gate slave delay encoded value for slice 1"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 1"
line.long 0xC0 "DDRSS_PHY_304,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_1,Observation register containing automatic half cycle and cycle shift values for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_1,Observation register containing write adder slave delay encoded value for slice 1"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1,Observation register containing write DQ base slave delay encoded value for slice 1"
line.long 0xC4 "DDRSS_PHY_305,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_1,Observation register containing write leveling first hard 1 DQS slave delay for slice 1"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_1,Observation register containing write leveling last hard 0 DQS slave delay for slice 1"
line.long 0xC8 "DDRSS_PHY_306,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_1,Observation register containing write leveling status for slice 1"
line.long 0xCC "DDRSS_PHY_307,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1,Observation register containing gate sample2 slave delay encoded values for slice 1"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1,Observation register containing gate sample1 slave delay encoded values for slice 1"
line.long 0xD0 "DDRSS_PHY_308,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_1,Observation register containing gate training first hard 0 DQS slave delay for slice 1"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_1,Observation register containing write leveling error status for slice 1"
line.long 0xD4 "DDRSS_PHY_309,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_1,Observation register containing gate training last hard 1 DQS slave delay for slice 1"
line.long 0xD8 "DDRSS_PHY_310,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_1,Observation register containing gate training status for slice 1"
line.long 0xDC "DDRSS_PHY_311,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1,Observation register containing read leveling data window trailing edge slave delay setting for slice 1"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1,Observation register containing read leveling data window leading edge slave delay setting for slice 1"
line.long 0xE0 "DDRSS_PHY_312,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1,Observation register containing read leveling number of windows found for slice 1" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_313,"
line.long 0xE8 "DDRSS_PHY_314,"
line.long 0xEC "DDRSS_PHY_315,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_1,Observation register containing write data leveling data window trailing edge slave delay setting for slice 1"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_1,Observation register containing write data leveling data window leading edge slave delay setting for slice 1"
line.long 0xF0 "DDRSS_PHY_316,"
line.long 0xF4 "DDRSS_PHY_317,"
line.long 0xF8 "DDRSS_PHY_318,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_1,DDL mode for slice 1"
line.long 0xFC "DDRSS_PHY_319,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_1,DDL mask for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_320,"
line.long 0x104 "DDRSS_PHY_321,"
line.long 0x108 "DDRSS_PHY_322,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_1,Manual setting of RX Calibration enable for slice 1" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_1,Manual RX Calibration start for slice 1" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_1,LPDDR4 write preamble extension enable for slice 1" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_1,Specify threshold value for PHY init update tracking for slice 1"
line.long 0x10C "DDRSS_PHY_323,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_1,RX Calibration codes for DQ0 for slice 1"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1,Data slice power reduction disable for slice 1" "0,1"
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hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_1,RX Calibration state machine wait count for slice 1"
line.long 0x110 "DDRSS_PHY_324,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_1,RX Calibration codes for DQ2 for slice 1"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_1,RX Calibration codes for DQ1 for slice 1"
line.long 0x114 "DDRSS_PHY_325,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_1,RX Calibration codes for DQ4 for slice 1"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_1,RX Calibration codes for DQ3 for slice 1"
line.long 0x118 "DDRSS_PHY_326,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_1,RX Calibration codes for DQ6 for slice 1"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_1,RX Calibration codes for DQ5 for slice 1"
line.long 0x11C "DDRSS_PHY_327,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_1,RX Calibration codes for DQ7 for slice 1"
line.long 0x120 "DDRSS_PHY_328,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_1,RX Calibration codes for DM for slice 1"
line.long 0x124 "DDRSS_PHY_329,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_1,RX Calibration codes for FDBK for slice 1"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_1,RX Calibration codes for DQS for slice 1"
line.long 0x128 "DDRSS_PHY_330,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_1,RX Calibration lock results for slice 1"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_1,RX Calibration results for slice 1"
line.long 0x12C "DDRSS_PHY_331,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_1,Expected C value from RX pad for slice 1" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_1,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_1,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_1,RX CAL disable signal for slice 1 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_332,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_1,Controls RX_BIAS_EN pin for each pad for slice 1"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_1,RX offset calibration mask of all RX pad for slice 1"
line.long 0x134 "DDRSS_PHY_333,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_1,Determines weight of average calculating for slice 1" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_1,Determines timeout number of iteration for slice 1"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_1,Determines number of cycles to wait for each sample for slice 1"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_1,Control to disable toggle during static activity for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_334,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_1,Adjust direction for slice 1" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_1,Duty cycle adjust threshold around the mid-point for slice 1"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_1,Duty cycle adjust sample count for slice 1"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_1,Duty cycle adjust starting value for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_335,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_1,Shutoff gate feedback IO to reduce power for slice 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_1,Rank selection for software based duty cycle correction for slice 1" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_1,Manual trigger for DCC for slice 1" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_1,Calibration polarity for slice 1" "0,1"
line.long 0x140 "DDRSS_PHY_336,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_1,Data slice power reduction disable for slice 1" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1,Data slice DCC and RX_CAL block power reduction disable for slice 1" "0,1"
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bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_1,Data slice read path power reduction disable for slice 1" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_1,Data slice slv_dly_control block power reduction disable for slice 1" "0,1"
line.long 0x144 "DDRSS_PHY_337,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_1,Data slice level FSM Error Info for slice 1"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_1,Inject parity error to register interface signals for slice 1"
line.long 0x148 "DDRSS_PHY_338,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1,Data slice level FSM Error Info for slice 1"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_1,Data slice level FSM Error Info Mask for slice 1"
line.long 0x14C "DDRSS_PHY_339,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1,Data slice level training/calibration Error Info for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1,Data slice level training/calibration Error Info Mask for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_1,Data slice level training/calibration Error Info for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_340,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_1,Operation type tsel enables for DQS signals for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_1,Operation type tsel select values for DQ/DM signals for slice 1"
newline
bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_1,Operation type tsel enables for DQ/DM signals for slice 1" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_341,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_1,Data slice initial VREF training start value for slice 1"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_1,2 cycle preamble support for slice 1" "0,1,2,3"
newline
hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_1,Operation type tsel select values for DQS signals for slice 1"
line.long 0x158 "DDRSS_PHY_342,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_1,Step size of WR DQ slave delay during No-Topology training for slice 1"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_1,Enable for No-Topology training for slice 1" "0,1"
newline
bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_1,Data slice vref training enable control for slice 1" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_1,Data slice initial VREF training stop value for slice 1"
line.long 0x15C "DDRSS_PHY_343,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_1,End of WR DQ slave delay in No-Topology training for slice 1"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_1,Starting WR DQ slave delay in No-Topology training for slice 1"
line.long 0x160 "DDRSS_PHY_344,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_1,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 1" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_1,Enable Bit for WR DQ during No-Topology training for slice 1"
line.long 0x164 "DDRSS_PHY_345,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_1,Controls TX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_1,Enable for fast multi-pattern window search for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_346,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_347,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_1,Controls RX_DCD pin for dm pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_1,Controls RX_DCD pin for each pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_348,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_1,Controls PCLK/PARK pin for pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_1,Controls RX_DCD pin for fdbk pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_1,Controls RX_DCD pin for dqs pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_349,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_1,Read DQ1 slave delay setting for slice 1"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_1,Read DQ0 slave delay setting for slice 1"
line.long 0x178 "DDRSS_PHY_350,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_1,Read DQ3 slave delay setting for slice 1"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_1,Read DQ2 slave delay setting for slice 1"
line.long 0x17C "DDRSS_PHY_351,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_1,Read DQ5 slave delay setting for slice 1"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_1,Read DQ4 slave delay setting for slice 1"
line.long 0x180 "DDRSS_PHY_352,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_1,Read DQ7 slave delay setting for slice 1"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_1,Read DQ6 slave delay setting for slice 1"
line.long 0x184 "DDRSS_PHY_353,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_1,Determines DCC CAL clock for slice 1" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_1,Read DM/DBI slave delay setting for slice 1"
line.long 0x188 "DDRSS_PHY_354,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_1,Start/end timing values for DQS output enable signals for slice 1"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_1,Start/end timing values for DQ/DM write based termination enable and select signals for slice 1"
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hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_1,Start/end timing values for DQ/DM read based termination enable and select signals for slice 1"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_1,Start/end timing values for DQ/DM output enable signals for slice 1"
line.long 0x18C "DDRSS_PHY_355,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_1,Start/end timing values for DQS write based termination enable and select signals for slice 1"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_1,Start/end timing values for DQS read based OE extension for slice 1"
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hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_1,Start/end timing values for DQS read based termination enable and select signals for slice 1"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_1,Feedback pad's OPAD and IPAD delay timing for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_356,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_1,Pad VREF control settings for DQ slice 1"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_1,Number of cycles for vref settle after setting is changed for slice 1"
line.long 0x194 "DDRSS_PHY_357,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_1,Start/end timing values for DQS input enable signals for slice 1"
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hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_1,Start/end timing values for DQ/DM input enable signals for slice 1"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_1,Enables the per-rank training and read/write timing capabilities for slice 1" "0,1"
line.long 0x198 "DDRSS_PHY_358,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_1,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_1,DBI mode for slice 1" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_1,Input enable mode bits for slice 1" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_359,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_1,Incremental step size for master delay line locking algorithm for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_1,Start value for master delay line locking algorithm for slice 1"
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bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_1,Master delay line override settings for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_360,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_1,DQS slave delay step size during write leveling for slice 1"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_1,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_1,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 1"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_1,Wait cycles for master delay line locking algorithm for slice 1"
line.long 0x1A4 "DDRSS_PHY_361,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_1,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_1,DQS slave delay step size during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_1,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_1,DQS slave delay fine step size during write leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_362,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_1,Final backup step delay used in gate training algorithm for slice 1"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_1,Interim backup step delay used in gate training algorithm for slice 1"
line.long 0x1AC "DDRSS_PHY_363,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_1,DQS slave delay step size during read leveling for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_1,Support the toggle read preamble for LPDDR4 for slice 1" "0,1"
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bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_1,Defines the step granularity for the logic to use once an edge is found for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_1,DQ slave delay step size during write data leveling for slice 1"
line.long 0x1B0 "DDRSS_PHY_364,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_1,The maximun rdlvl slave delay search window for read eye training for slice 1"
line.long 0x1B4 "DDRSS_PHY_365,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_1,Peridic training start point offset for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_1,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 1" "0,1"
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hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_1,Minimum data valid window across DQs and ranks for slice 1"
line.long 0x1B8 "DDRSS_PHY_366,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_1,Disable duty cycle adjust at initialization for slice 1" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_1,Write path clock gating timing for slice 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_1,Write path clock gating disable for slice 1" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_367,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_1,Initial value of write DQ slave delay for slice 1"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_1,Initial value of write DQS slave delay for slice 1"
line.long 0x1C0 "DDRSS_PHY_368,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1,Clock measurement cell threshold offset for differential signals for slice 1"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_1,Clock measurement cell threshold offset for single ended signals for slice 1"
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bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_1,Enable duty cycle adjust during write DQ training for slice 1" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_1,Enable duty cycle adjust during write leveling for slice 1" "0,1"
line.long 0x1C4 "DDRSS_PHY_369,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_1,Number of cycles that the dfi_rddata_en signal is early for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_1,Data slice training step definition using phy_meas_dly_step_value for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_1,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 1"
line.long 0x1C8 "DDRSS_PHY_370,"
line.long 0x1CC "DDRSS_PHY_371,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_1,DQ/DM bit swizzling 1 for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_372,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_1,Write clock slave delay setting for DQ1 for slice 1"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_1,Write clock slave delay setting for DQ0 for slice 1"
line.long 0x1D4 "DDRSS_PHY_373,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_1,Write clock slave delay setting for DQ3 for slice 1"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_1,Write clock slave delay setting for DQ2 for slice 1"
line.long 0x1D8 "DDRSS_PHY_374,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_1,Write clock slave delay setting for DQ5 for slice 1"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_1,Write clock slave delay setting for DQ4 for slice 1"
line.long 0x1DC "DDRSS_PHY_375,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_1,Write clock slave delay setting for DQ7 for slice 1"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_1,Write clock slave delay setting for DQ6 for slice 1"
line.long 0x1E0 "DDRSS_PHY_376,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_1,Write clock slave delay setting for DQS for slice 1"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_1,Write clock slave delay setting for DM for slice 1"
line.long 0x1E4 "DDRSS_PHY_377,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ0 for slice 1"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_1,Write level threshold adjust value based on those thresholds for DQS for slice 1" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_378,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ1 for slice 1"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ0 for slice 1"
line.long 0x1EC "DDRSS_PHY_379,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ2 for slice 1"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ1 for slice 1"
line.long 0x1F0 "DDRSS_PHY_380,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ3 for slice 1"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ2 for slice 1"
line.long 0x1F4 "DDRSS_PHY_381,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ4 for slice 1"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ3 for slice 1"
line.long 0x1F8 "DDRSS_PHY_382,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ5 for slice 1"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ4 for slice 1"
line.long 0x1FC "DDRSS_PHY_383,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ6 for slice 1"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ5 for slice 1"
line.long 0x200 "DDRSS_PHY_384,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DQ7 for slice 1"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ6 for slice 1"
line.long 0x204 "DDRSS_PHY_385,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_1,Rising edge read DQS slave delay setting for DM for slice 1"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DQ7 for slice 1"
line.long 0x208 "DDRSS_PHY_386,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_1,Read DQS slave delay setting for slice 1"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_1,Falling edge read DQS slave delay setting for DM for slice 1"
line.long 0x20C "DDRSS_PHY_387,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_1,Write level delay threshold above which will be considered in previous cycle for slice 1"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_1,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_1,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_388,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_1,Force the final write level delay value (that meets the early threshold) to 0 for slice 1" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1,Write level delay threshold below which will add a cycle of write path latency for slice 1"
line.long 0x214 "DDRSS_PHY_389,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_1,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_1,Initial read DQS gate slave delay setting during gate training for slice 1"
line.long 0x218 "DDRSS_PHY_390,"
bitfld.long 0x218 24. "PHY_NTP_PASS_1,Indicates if No-topology training found a passing result for slice 1" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_1,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_1,Initial DQ/DM slave delay setting during write data leveling for slice 1"
line.long 0x21C "DDRSS_PHY_391,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1,Read leveling starting value for the DQS/DQ slave delay settings for slice 1"
line.long 0x220 "DDRSS_PHY_392,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
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hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
line.long 0x224 "DDRSS_PHY_393,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
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hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
line.long 0x228 "DDRSS_PHY_394,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_1,Setting for boost P/N of pad for slice 1"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
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hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_1,Adjust value of Duty Cycle Adjuster for slice 1"
line.long 0x22C "DDRSS_PHY_395,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_1,TX_FFE setting for DQS pad for slice 1" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_1,TX_FFE setting for DQ/DM pad for slice 1" "0,1,2,3"
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bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_1,Setting for RX ctle P/N of pad for slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4800++0x22F
line.long 0x00 "DDRSS_PHY_512,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_2,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_2,Write data clock bypass mode slave delay setting for slice 2.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_513,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_2,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2,Write DQS bypass mode slave delay setting for slice 2"
line.long 0x08 "DDRSS_PHY_514,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_2,Bypass mode override setting for slice 2" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_2,Two_cycle_preamble for bypass mode for slice 2" "0,1,2,3"
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hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2,Read DQS bypass mode slave delay setting for slice 2"
line.long 0x0C "DDRSS_PHY_515,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_516,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_517,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_2,When set a register write will update parameters for all ranks at the same time in slice 2" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_2,Per-rank CS map for slice 2" "0,1,2,3"
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bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_2,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_518,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_2,For per-rank training indicates which rank's paramters are read/written for slice 2" "0,1"
line.long 0x1C "DDRSS_PHY_519,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2,For LPDDR4 boot frequency write path clock gating disable for slice 2" "0,1,2,3"
newline
bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_2,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_520,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_2,Loopback read only test timeout mechanism enable for slice 2" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_2,Loopback control bits for slice 2"
newline
bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_2,Loopback control en for slice 2" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_521,"
line.long 0x28 "DDRSS_PHY_522,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_2,Observation register for the auto_timing_margin for slice 2"
line.long 0x2C "DDRSS_PHY_523,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_2,Read Leveling Multi-pattern enable for slice 2" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_2,PRBS7 mask signal for slice 2"
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hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_2,PRBS7 start pattern for slice 2"
line.long 0x30 "DDRSS_PHY_524,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_2,Observation register for best vref value for slice 2"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_2,Data slice initial VREF training step size for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_2,Read Leveling read level windows disable reset for slice 2" "0,1"
line.long 0x34 "DDRSS_PHY_525,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_2,Initiates a snapshot of the internal observation registers for slice 2" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_2,Number of cycles to wait for the DQS gate to close before flagging an error for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2,Read DQS data clock bypass mode slave delay setting for slice 2"
line.long 0x38 "DDRSS_PHY_526,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_2,Indicates the type of DRAM for slice 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_2,Adds a cycle of delay for the slice 2 to match the address slice" "0,1"
newline
hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_2,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 2"
line.long 0x3C "DDRSS_PHY_527,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_2,Control the on-the-fly gate adjustment for slice 2" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_2,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 2"
line.long 0x40 "DDRSS_PHY_528,"
line.long 0x44 "DDRSS_PHY_529,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_2,Controls the read postamble extension for LPDDR4 for slice 2" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_2,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 2" "0,1"
line.long 0x48 "DDRSS_PHY_530,"
line.long 0x4C "DDRSS_PHY_531,"
line.long 0x50 "DDRSS_PHY_532,"
line.long 0x54 "DDRSS_PHY_533,"
line.long 0x58 "DDRSS_PHY_534,"
line.long 0x5C "DDRSS_PHY_535,"
line.long 0x60 "DDRSS_PHY_536,"
line.long 0x64 "DDRSS_PHY_537,"
line.long 0x68 "DDRSS_PHY_538,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_2,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_2,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_2,Disables automatic reset of the read entry FIFO pointers for slice 2" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_2,Reserved for future use for slice 2" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_539,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_2,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_2,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_2,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_2,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_540,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_2,Observation register for write leveling status for slice 2"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_2,Write leveling algorithm selection for slice 2" "0,1,2,3"
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bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_2,Allows the leveling state machine to advance (when in debug mode) for slice 2" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_2,Enables leveling debug mode for slice 2" "0,1"
line.long 0x74 "DDRSS_PHY_541,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_2,For ECC slice should set this register to do DQ bit mask for slice 2"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_542,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_2,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_2,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 2"
line.long 0x7C "DDRSS_PHY_543,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_2,Read leveling algorithm select for slice 2" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_2,Number of samples to take at each DQS slave delay setting during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_544,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_2,Defines the write/read burst length in bytes during the write data leveling sequence for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_2,Defines the minimum gap requirment for the LE and TE window for slice 2"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_2,Per-bit mask for read leveling for slice 2"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 2"
line.long 0x84 "DDRSS_PHY_545,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_2,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2,Defines the write/read burst length in bytes during the write data leveling sequence for slice 2"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_2,Defines the training patterns to be used during the write data leveling sequence for slice 2" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_546,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_2,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 2" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_2,Select value to map specific information during or post periodic write data leveling for slice 2"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_2,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_547,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_2,Per-bit mask for write data leveling for slice 2"
line.long 0x90 "DDRSS_PHY_548,"
line.long 0x94 "DDRSS_PHY_549,"
line.long 0x98 "DDRSS_PHY_550,"
line.long 0x9C "DDRSS_PHY_551,"
line.long 0xA0 "DDRSS_PHY_552,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_2,Control for single pass only No-Topology training for slice 2" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_2,User-defined pattern to be used during write data leveling for slice 2"
line.long 0xA4 "DDRSS_PHY_553,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_2,Threshold Criteria of period threshold after No-Topology training is completed for slice 2"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_2,Threshold Criteria of early threshold after No-Topology training is completed for slice 2"
line.long 0xA8 "DDRSS_PHY_554,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_2,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 2"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_2,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 2"
line.long 0xAC "DDRSS_PHY_555,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_2,Observation register containing read entry FIFO pointers for slice 2"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_2,Manual reset/clear of internal logic for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_2,Indicates if slice 2 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_556,"
line.long 0xB4 "DDRSS_PHY_557,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_2,Observation register containing master delay results for slice 2"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_2,Observation register containing total number of loopback error data for slice 2"
line.long 0xB8 "DDRSS_PHY_558,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 2"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_2,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 2"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2,Observation register containing read DQS base slave delay encoded value for slice 2"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_2,Observation register containing read DQ slave delay encoded values for slice 2"
line.long 0xBC "DDRSS_PHY_559,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2,Observation register containing write DQS base slave delay encoded value for slice 2"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2,Observation register containing read DQS gate slave delay encoded value for slice 2"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 2"
line.long 0xC0 "DDRSS_PHY_560,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_2,Observation register containing automatic half cycle and cycle shift values for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_2,Observation register containing write adder slave delay encoded value for slice 2"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2,Observation register containing write DQ base slave delay encoded value for slice 2"
line.long 0xC4 "DDRSS_PHY_561,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_2,Observation register containing write leveling first hard 1 DQS slave delay for slice 2"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_2,Observation register containing write leveling last hard 0 DQS slave delay for slice 2"
line.long 0xC8 "DDRSS_PHY_562,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_2,Observation register containing write leveling status for slice 2"
line.long 0xCC "DDRSS_PHY_563,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2,Observation register containing gate sample2 slave delay encoded values for slice 2"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2,Observation register containing gate sample1 slave delay encoded values for slice 2"
line.long 0xD0 "DDRSS_PHY_564,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_2,Observation register containing gate training first hard 0 DQS slave delay for slice 2"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_2,Observation register containing write leveling error status for slice 2"
line.long 0xD4 "DDRSS_PHY_565,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_2,Observation register containing gate training last hard 1 DQS slave delay for slice 2"
line.long 0xD8 "DDRSS_PHY_566,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_2,Observation register containing gate training status for slice 2"
line.long 0xDC "DDRSS_PHY_567,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2,Observation register containing read leveling data window trailing edge slave delay setting for slice 2"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2,Observation register containing read leveling data window leading edge slave delay setting for slice 2"
line.long 0xE0 "DDRSS_PHY_568,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2,Observation register containing read leveling number of windows found for slice 2" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_569,"
line.long 0xE8 "DDRSS_PHY_570,"
line.long 0xEC "DDRSS_PHY_571,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_2,Observation register containing write data leveling data window trailing edge slave delay setting for slice 2"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_2,Observation register containing write data leveling data window leading edge slave delay setting for slice 2"
line.long 0xF0 "DDRSS_PHY_572,"
line.long 0xF4 "DDRSS_PHY_573,"
line.long 0xF8 "DDRSS_PHY_574,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_2,DDL mode for slice 2"
line.long 0xFC "DDRSS_PHY_575,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_2,DDL mask for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_576,"
line.long 0x104 "DDRSS_PHY_577,"
line.long 0x108 "DDRSS_PHY_578,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_2,Manual setting of RX Calibration enable for slice 2" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_2,Manual RX Calibration start for slice 2" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_2,LPDDR4 write preamble extension enable for slice 2" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_2,Specify threshold value for PHY init update tracking for slice 2"
line.long 0x10C "DDRSS_PHY_579,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_2,RX Calibration codes for DQ0 for slice 2"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2,Data slice power reduction disable for slice 2" "0,1"
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hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_2,RX Calibration state machine wait count for slice 2"
line.long 0x110 "DDRSS_PHY_580,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_2,RX Calibration codes for DQ2 for slice 2"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_2,RX Calibration codes for DQ1 for slice 2"
line.long 0x114 "DDRSS_PHY_581,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_2,RX Calibration codes for DQ4 for slice 2"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_2,RX Calibration codes for DQ3 for slice 2"
line.long 0x118 "DDRSS_PHY_582,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_2,RX Calibration codes for DQ6 for slice 2"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_2,RX Calibration codes for DQ5 for slice 2"
line.long 0x11C "DDRSS_PHY_583,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_2,RX Calibration codes for DQ7 for slice 2"
line.long 0x120 "DDRSS_PHY_584,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_2,RX Calibration codes for DM for slice 2"
line.long 0x124 "DDRSS_PHY_585,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_2,RX Calibration codes for FDBK for slice 2"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_2,RX Calibration codes for DQS for slice 2"
line.long 0x128 "DDRSS_PHY_586,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_2,RX Calibration lock results for slice 2"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_2,RX Calibration results for slice 2"
line.long 0x12C "DDRSS_PHY_587,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_2,Expected C value from RX pad for slice 2" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_2,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_2,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_2,RX CAL disable signal for slice 2 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_588,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_2,Controls RX_BIAS_EN pin for each pad for slice 2"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_2,RX offset calibration mask of all RX pad for slice 2"
line.long 0x134 "DDRSS_PHY_589,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_2,Determines weight of average calculating for slice 2" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_2,Determines timeout number of iteration for slice 2"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_2,Determines number of cycles to wait for each sample for slice 2"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_2,Control to disable toggle during static activity for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_590,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_2,Adjust direction for slice 2" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_2,Duty cycle adjust threshold around the mid-point for slice 2"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_2,Duty cycle adjust sample count for slice 2"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_2,Duty cycle adjust starting value for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_591,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_2,Shutoff gate feedback IO to reduce power for slice 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_2,Rank selection for software based duty cycle correction for slice 2" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_2,Manual trigger for DCC for slice 2" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_2,Calibration polarity for slice 2" "0,1"
line.long 0x140 "DDRSS_PHY_592,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_2,Data slice power reduction disable for slice 2" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2,Data slice DCC and RX_CAL block power reduction disable for slice 2" "0,1"
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bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_2,Data slice read path power reduction disable for slice 2" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_2,Data slice slv_dly_control block power reduction disable for slice 2" "0,1"
line.long 0x144 "DDRSS_PHY_593,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_2,Data slice level FSM Error Info for slice 2"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_2,Inject parity error to register interface signals for slice 2"
line.long 0x148 "DDRSS_PHY_594,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2,Data slice level FSM Error Info for slice 2"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_2,Data slice level FSM Error Info Mask for slice 2"
line.long 0x14C "DDRSS_PHY_595,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2,Data slice level training/calibration Error Info for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2,Data slice level training/calibration Error Info Mask for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_2,Data slice level training/calibration Error Info for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_596,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_2,Operation type tsel enables for DQS signals for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_2,Operation type tsel select values for DQ/DM signals for slice 2"
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bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_2,Operation type tsel enables for DQ/DM signals for slice 2" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_597,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_2,Data slice initial VREF training start value for slice 2"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_2,2 cycle preamble support for slice 2" "0,1,2,3"
newline
hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_2,Operation type tsel select values for DQS signals for slice 2"
line.long 0x158 "DDRSS_PHY_598,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_2,Step size of WR DQ slave delay during No-Topology training for slice 2"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_2,Enable for No-Topology training for slice 2" "0,1"
newline
bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_2,Data slice vref training enable control for slice 2" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_2,Data slice initial VREF training stop value for slice 2"
line.long 0x15C "DDRSS_PHY_599,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_2,End of WR DQ slave delay in No-Topology training for slice 2"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_2,Starting WR DQ slave delay in No-Topology training for slice 2"
line.long 0x160 "DDRSS_PHY_600,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_2,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 2" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_2,Minimum data valid window across DQs and ranks for slice 2"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_2,Enable Bit for WR DQ during No-Topology training for slice 2"
line.long 0x164 "DDRSS_PHY_601,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_2,Controls TX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_2,Enable for fast multi-pattern window search for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_2,Peridic training start point offset for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_602,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_603,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_2,Controls RX_DCD pin for dm pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_2,Controls RX_DCD pin for each pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_604,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_2,Controls PCLK/PARK pin for pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_2,Controls RX_DCD pin for fdbk pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_2,Controls RX_DCD pin for dqs pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_605,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_2,Read DQ1 slave delay setting for slice 2"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_2,Read DQ0 slave delay setting for slice 2"
line.long 0x178 "DDRSS_PHY_606,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_2,Read DQ3 slave delay setting for slice 2"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_2,Read DQ2 slave delay setting for slice 2"
line.long 0x17C "DDRSS_PHY_607,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_2,Read DQ5 slave delay setting for slice 2"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_2,Read DQ4 slave delay setting for slice 2"
line.long 0x180 "DDRSS_PHY_608,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_2,Read DQ7 slave delay setting for slice 2"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_2,Read DQ6 slave delay setting for slice 2"
line.long 0x184 "DDRSS_PHY_609,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_2,Determines DCC CAL clock for slice 2" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_2,Read DM/DBI slave delay setting for slice 2"
line.long 0x188 "DDRSS_PHY_610,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_2,Start/end timing values for DQS output enable signals for slice 2"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_2,Start/end timing values for DQ/DM write based termination enable and select signals for slice 2"
newline
hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_2,Start/end timing values for DQ/DM read based termination enable and select signals for slice 2"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_2,Start/end timing values for DQ/DM output enable signals for slice 2"
line.long 0x18C "DDRSS_PHY_611,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_2,Start/end timing values for DQS write based termination enable and select signals for slice 2"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_2,Start/end timing values for DQS read based OE extension for slice 2"
newline
hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_2,Start/end timing values for DQS read based termination enable and select signals for slice 2"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_2,Feedback pad's OPAD and IPAD delay timing for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_612,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_2,Pad VREF control settings for DQ slice 2"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_2,Number of cycles for vref settle after setting is changed for slice 2"
line.long 0x194 "DDRSS_PHY_613,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_2,Start/end timing values for DQS input enable signals for slice 2"
newline
hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_2,Start/end timing values for DQ/DM input enable signals for slice 2"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_2,Enables the per-rank training and read/write timing capabilities for slice 2" "0,1"
line.long 0x198 "DDRSS_PHY_614,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_2,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_2,DBI mode for slice 2" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_2,Input enable mode bits for slice 2" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_615,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_2,Incremental step size for master delay line locking algorithm for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_2,Start value for master delay line locking algorithm for slice 2"
newline
bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_2,Master delay line override settings for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_616,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_2,DQS slave delay step size during write leveling for slice 2"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_2,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_2,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 2"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_2,Wait cycles for master delay line locking algorithm for slice 2"
line.long 0x1A4 "DDRSS_PHY_617,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_2,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_2,DQS slave delay step size during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_2,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_2,DQS slave delay fine step size during write leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_618,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_2,Final backup step delay used in gate training algorithm for slice 2"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_2,Interim backup step delay used in gate training algorithm for slice 2"
line.long 0x1AC "DDRSS_PHY_619,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_2,DQS slave delay step size during read leveling for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_2,Support the toggle read preamble for LPDDR4 for slice 2" "0,1"
newline
bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_2,Defines the step granularity for the logic to use once an edge is found for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_2,DQ slave delay step size during write data leveling for slice 2"
line.long 0x1B0 "DDRSS_PHY_620,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_2,The maximun rdlvl slave delay search window for read eye training for slice 2"
line.long 0x1B4 "DDRSS_PHY_621,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_2,Peridic training start point offset for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_2,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 2" "0,1"
newline
hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_2,Minimum data valid window across DQs and ranks for slice 2"
line.long 0x1B8 "DDRSS_PHY_622,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_2,Disable duty cycle adjust at initialization for slice 2" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_2,Write path clock gating timing for slice 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_2,Write path clock gating disable for slice 2" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_623,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_2,Initial value of write DQ slave delay for slice 2"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_2,Initial value of write DQS slave delay for slice 2"
line.long 0x1C0 "DDRSS_PHY_624,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2,Clock measurement cell threshold offset for differential signals for slice 2"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_2,Clock measurement cell threshold offset for single ended signals for slice 2"
newline
bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_2,Enable duty cycle adjust during write DQ training for slice 2" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_2,Enable duty cycle adjust during write leveling for slice 2" "0,1"
line.long 0x1C4 "DDRSS_PHY_625,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_2,Number of cycles that the dfi_rddata_en signal is early for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_2,Data slice training step definition using phy_meas_dly_step_value for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_2,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 2"
line.long 0x1C8 "DDRSS_PHY_626,"
line.long 0x1CC "DDRSS_PHY_627,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_2,DQ/DM bit swizzling 1 for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_628,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_2,Write clock slave delay setting for DQ1 for slice 2"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_2,Write clock slave delay setting for DQ0 for slice 2"
line.long 0x1D4 "DDRSS_PHY_629,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_2,Write clock slave delay setting for DQ3 for slice 2"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_2,Write clock slave delay setting for DQ2 for slice 2"
line.long 0x1D8 "DDRSS_PHY_630,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_2,Write clock slave delay setting for DQ5 for slice 2"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_2,Write clock slave delay setting for DQ4 for slice 2"
line.long 0x1DC "DDRSS_PHY_631,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_2,Write clock slave delay setting for DQ7 for slice 2"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_2,Write clock slave delay setting for DQ6 for slice 2"
line.long 0x1E0 "DDRSS_PHY_632,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_2,Write clock slave delay setting for DQS for slice 2"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_2,Write clock slave delay setting for DM for slice 2"
line.long 0x1E4 "DDRSS_PHY_633,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ0 for slice 2"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_2,Write level threshold adjust value based on those thresholds for DQS for slice 2" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_634,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ1 for slice 2"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ0 for slice 2"
line.long 0x1EC "DDRSS_PHY_635,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ2 for slice 2"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ1 for slice 2"
line.long 0x1F0 "DDRSS_PHY_636,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ3 for slice 2"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ2 for slice 2"
line.long 0x1F4 "DDRSS_PHY_637,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ4 for slice 2"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ3 for slice 2"
line.long 0x1F8 "DDRSS_PHY_638,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ5 for slice 2"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ4 for slice 2"
line.long 0x1FC "DDRSS_PHY_639,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ6 for slice 2"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ5 for slice 2"
line.long 0x200 "DDRSS_PHY_640,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DQ7 for slice 2"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ6 for slice 2"
line.long 0x204 "DDRSS_PHY_641,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_2,Rising edge read DQS slave delay setting for DM for slice 2"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DQ7 for slice 2"
line.long 0x208 "DDRSS_PHY_642,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_2,Read DQS slave delay setting for slice 2"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_2,Falling edge read DQS slave delay setting for DM for slice 2"
line.long 0x20C "DDRSS_PHY_643,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_2,Write level delay threshold above which will be considered in previous cycle for slice 2"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_2,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_2,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_644,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_2,Force the final write level delay value (that meets the early threshold) to 0 for slice 2" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2,Write level delay threshold below which will add a cycle of write path latency for slice 2"
line.long 0x214 "DDRSS_PHY_645,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_2,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_2,Initial read DQS gate slave delay setting during gate training for slice 2"
line.long 0x218 "DDRSS_PHY_646,"
bitfld.long 0x218 24. "PHY_NTP_PASS_2,Indicates if No-topology training found a passing result for slice 2" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_2,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_2,Initial DQ/DM slave delay setting during write data leveling for slice 2"
line.long 0x21C "DDRSS_PHY_647,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2,Read leveling starting value for the DQS/DQ slave delay settings for slice 2"
line.long 0x220 "DDRSS_PHY_648,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
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hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
line.long 0x224 "DDRSS_PHY_649,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
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hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
line.long 0x228 "DDRSS_PHY_650,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_2,Setting for boost P/N of pad for slice 2"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
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hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_2,Adjust value of Duty Cycle Adjuster for slice 2"
line.long 0x22C "DDRSS_PHY_651,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_2,TX_FFE setting for DQS pad for slice 2" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_2,TX_FFE setting for DQ/DM pad for slice 2" "0,1,2,3"
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bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_2,Setting for RX ctle P/N of pad for slice 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4C00++0x22F
line.long 0x00 "DDRSS_PHY_768,"
bitfld.long 0x00 16.--19. "PHY_IO_PAD_DELAY_TIMING_BYPASS_3,Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "PHY_CLK_WR_BYPASS_SLAVE_DELAY_3,Write data clock bypass mode slave delay setting for slice 3.} PADDING_BEFORE"
line.long 0x04 "DDRSS_PHY_769,"
bitfld.long 0x04 16.--18. "PHY_WRITE_PATH_LAT_ADD_BYPASS_3,Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3,Write DQS bypass mode slave delay setting for slice 3"
line.long 0x08 "DDRSS_PHY_770,"
bitfld.long 0x08 24. "PHY_CLK_BYPASS_OVERRIDE_3,Bypass mode override setting for slice 3" "0,1"
bitfld.long 0x08 16.--17. "PHY_BYPASS_TWO_CYC_PREAMBLE_3,Two_cycle_preamble for bypass mode for slice 3" "0,1,2,3"
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hexmask.long.word 0x08 0.--9. 1. "PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3,Read DQS bypass mode slave delay setting for slice 3"
line.long 0x0C "DDRSS_PHY_771,"
bitfld.long 0x0C 24.--29. "PHY_SW_WRDQ3_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PHY_SW_WRDQ2_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 8.--13. "PHY_SW_WRDQ1_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PHY_SW_WRDQ0_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DDRSS_PHY_772,"
bitfld.long 0x10 24.--29. "PHY_SW_WRDQ7_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PHY_SW_WRDQ6_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 8.--13. "PHY_SW_WRDQ5_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PHY_SW_WRDQ4_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DDRSS_PHY_773,"
bitfld.long 0x14 24. "PHY_PER_CS_TRAINING_MULTICAST_EN_3,When set a register write will update parameters for all ranks at the same time in slice 3" "0,1"
bitfld.long 0x14 16.--17. "PHY_PER_RANK_CS_MAP_3,Per-rank CS map for slice 3" "0,1,2,3"
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bitfld.long 0x14 8.--11. "PHY_SW_WRDQS_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--5. "PHY_SW_WRDM_SHIFT_3,Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DDRSS_PHY_774,"
bitfld.long 0x18 24.--28. "PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PHY_LP4_BOOT_RDDATA_EN_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is early for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 8.--9. "PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3" "0,1,2,3"
bitfld.long 0x18 0. "PHY_PER_CS_TRAINING_INDEX_3,For per-rank training indicates which rank's paramters are read/written for slice 3" "0,1"
line.long 0x1C "DDRSS_PHY_775,"
bitfld.long 0x1C 24.--28. "PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3,For LPDDR4 boot frequency the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--17. "PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3,For LPDDR4 boot frequency write path clock gating disable for slice 3" "0,1,2,3"
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bitfld.long 0x1C 8.--11. "PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3,For LPDDR4 boot frequency the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PHY_LP4_BOOT_RPTR_UPDATE_3,For LPDDR4 boot frequency the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PHY_776,"
bitfld.long 0x20 24. "PHY_LPBK_DFX_TIMEOUT_EN_3,Loopback read only test timeout mechanism enable for slice 3" "0,1"
hexmask.long.word 0x20 8.--16. 1. "PHY_LPBK_CONTROL_3,Loopback control bits for slice 3"
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bitfld.long 0x20 0.--1. "PHY_CTRL_LPBK_EN_3,Loopback control en for slice 3" "0,1,2,3"
line.long 0x24 "DDRSS_PHY_777,"
line.long 0x28 "DDRSS_PHY_778,"
hexmask.long 0x28 0.--27. 1. "PHY_AUTO_TIMING_MARGIN_OBS_3,Observation register for the auto_timing_margin for slice 3"
line.long 0x2C "DDRSS_PHY_779,"
bitfld.long 0x2C 24. "PHY_RDLVL_MULTI_PATT_ENABLE_3,Read Leveling Multi-pattern enable for slice 3" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_PRBS_PATTERN_MASK_3,PRBS7 mask signal for slice 3"
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hexmask.long.byte 0x2C 0.--6. 1. "PHY_PRBS_PATTERN_START_3,PRBS7 start pattern for slice 3"
line.long 0x30 "DDRSS_PHY_780,"
hexmask.long.byte 0x30 16.--22. 1. "PHY_VREF_TRAIN_OBS_3,Observation register for best vref value for slice 3"
bitfld.long 0x30 8.--13. "PHY_VREF_INITIAL_STEPSIZE_3,Data slice initial VREF training step size for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x30 0. "PHY_RDLVL_MULTI_PATT_RST_DISABLE_3,Read Leveling read level windows disable reset for slice 3" "0,1"
line.long 0x34 "DDRSS_PHY_781,"
bitfld.long 0x34 24. "SC_PHY_SNAP_OBS_REGS_3,Initiates a snapshot of the internal observation registers for slice 3" "0,1"
bitfld.long 0x34 16.--19. "PHY_GATE_ERROR_DELAY_SELECT_3,Number of cycles to wait for the DQS gate to close before flagging an error for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x34 0.--9. 1. "PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3,Read DQS data clock bypass mode slave delay setting for slice 3"
line.long 0x38 "DDRSS_PHY_782,"
bitfld.long 0x38 24.--26. "PHY_MEM_CLASS_3,Indicates the type of DRAM for slice 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x38 16. "PHY_LPDDR_3,Adds a cycle of delay for the slice 3 to match the address slice" "0,1"
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hexmask.long.word 0x38 0.--8. 1. "PHY_GATE_SMPL1_SLAVE_DELAY_3,Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 3"
line.long 0x3C "DDRSS_PHY_783,"
bitfld.long 0x3C 16.--17. "ON_FLY_GATE_ADJUST_EN_3,Control the on-the-fly gate adjustment for slice 3" "0,1,2,3"
hexmask.long.word 0x3C 0.--8. 1. "PHY_GATE_SMPL2_SLAVE_DELAY_3,Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 3"
line.long 0x40 "DDRSS_PHY_784,"
line.long 0x44 "DDRSS_PHY_785,"
bitfld.long 0x44 8.--9. "PHY_LP4_PST_AMBLE_3,Controls the read postamble extension for LPDDR4 for slice 3" "0,1,2,3"
bitfld.long 0x44 0. "PHY_DFI40_POLARITY_3,Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 3" "0,1"
line.long 0x48 "DDRSS_PHY_786,"
line.long 0x4C "DDRSS_PHY_787,"
line.long 0x50 "DDRSS_PHY_788,"
line.long 0x54 "DDRSS_PHY_789,"
line.long 0x58 "DDRSS_PHY_790,"
line.long 0x5C "DDRSS_PHY_791,"
line.long 0x60 "DDRSS_PHY_792,"
line.long 0x64 "DDRSS_PHY_793,"
line.long 0x68 "DDRSS_PHY_794,"
bitfld.long 0x68 24.--26. "PHY_RDDQ_ENC_OBS_SELECT_3,Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 16.--19. "PHY_MASTER_DLY_LOCK_OBS_SELECT_3,Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x68 8. "PHY_SW_FIFO_PTR_RST_DISABLE_3,Disables automatic reset of the read entry FIFO pointers for slice 3" "0,1"
bitfld.long 0x68 0.--2. "PHY_SLAVE_LOOP_CNT_UPDATE_3,Reserved for future use for slice 3" "0,1,2,3,4,5,6,7"
line.long 0x6C "DDRSS_PHY_795,"
bitfld.long 0x6C 24.--27. "PHY_FIFO_PTR_OBS_SELECT_3,Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PHY_WR_SHIFT_OBS_SELECT_3,Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x6C 8.--11. "PHY_WR_ENC_OBS_SELECT_3,Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_RDDQS_DQ_ENC_OBS_SELECT_3,Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_796,"
hexmask.long.byte 0x70 24.--31. 1. "PHY_WRLVL_PER_START_3,Observation register for write leveling status for slice 3"
bitfld.long 0x70 16.--17. "PHY_WRLVL_ALGO_3,Write leveling algorithm selection for slice 3" "0,1,2,3"
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bitfld.long 0x70 8. "SC_PHY_LVL_DEBUG_CONT_3,Allows the leveling state machine to advance (when in debug mode) for slice 3" "0,1"
bitfld.long 0x70 0. "PHY_LVL_DEBUG_MODE_3,Enables leveling debug mode for slice 3" "0,1"
line.long 0x74 "DDRSS_PHY_797,"
hexmask.long.byte 0x74 16.--23. 1. "PHY_DQ_MASK_3,For ECC slice should set this register to do DQ bit mask for slice 3"
bitfld.long 0x74 8.--11. "PHY_WRLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x74 0.--5. "PHY_WRLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x78 "DDRSS_PHY_798,"
bitfld.long 0x78 24.--27. "PHY_GTLVL_UPDT_WAIT_CNT_3,Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x78 16.--21. "PHY_GTLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x78 0.--9. 1. "PHY_GTLVL_PER_START_3,Value to be added to the current gate delay position as the staring point for periodic gate training for slice 3"
line.long 0x7C "DDRSS_PHY_799,"
bitfld.long 0x7C 24.--28. "PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--17. "PHY_RDLVL_OP_MODE_3,Read leveling algorithm select for slice 3" "0,1,2,3"
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bitfld.long 0x7C 8.--11. "PHY_RDLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 0.--5. "PHY_RDLVL_CAPTURE_CNT_3,Number of samples to take at each DQS slave delay setting during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_800,"
bitfld.long 0x80 24.--29. "PHY_WDQLVL_BURST_CNT_3,Defines the write/read burst length in bytes during the write data leveling sequence for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x80 16.--23. 1. "PHY_WDQLVL_CLK_JITTER_TOLERANCE_3,Defines the minimum gap requirment for the LE and TE window for slice 3"
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hexmask.long.byte 0x80 8.--15. 1. "PHY_RDLVL_DATA_MASK_3,Per-bit mask for read leveling for slice 3"
hexmask.long.byte 0x80 0.--7. 1. "PHY_RDLVL_PERIODIC_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 3"
line.long 0x84 "DDRSS_PHY_801,"
bitfld.long 0x84 24.--27. "PHY_WDQLVL_UPDT_WAIT_CNT_3,Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x84 8.--18. 1. "PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3,Defines the write/read burst length in bytes during the write data leveling sequence for slice 3"
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bitfld.long 0x84 0.--2. "PHY_WDQLVL_PATT_3,Defines the training patterns to be used during the write data leveling sequence for slice 3" "0,1,2,3,4,5,6,7"
line.long 0x88 "DDRSS_PHY_802,"
bitfld.long 0x88 16. "SC_PHY_WDQLVL_CLR_PREV_RESULTS_3,Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 3" "0,1"
hexmask.long.byte 0x88 8.--15. 1. "PHY_WDQLVL_PERIODIC_OBS_SELECT_3,Select value to map specific information during or post periodic write data leveling for slice 3"
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bitfld.long 0x88 0.--3. "PHY_WDQLVL_DQDM_OBS_SELECT_3,Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "DDRSS_PHY_803,"
hexmask.long.word 0x8C 0.--8. 1. "PHY_WDQLVL_DATADM_MASK_3,Per-bit mask for write data leveling for slice 3"
line.long 0x90 "DDRSS_PHY_804,"
line.long 0x94 "DDRSS_PHY_805,"
line.long 0x98 "DDRSS_PHY_806,"
line.long 0x9C "DDRSS_PHY_807,"
line.long 0xA0 "DDRSS_PHY_808,"
bitfld.long 0xA0 16. "PHY_NTP_MULT_TRAIN_3,Control for single pass only No-Topology training for slice 3" "0,1"
hexmask.long.word 0xA0 0.--15. 1. "PHY_USER_PATT4_3,User-defined pattern to be used during write data leveling for slice 3"
line.long 0xA4 "DDRSS_PHY_809,"
hexmask.long.word 0xA4 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_3,Threshold Criteria of period threshold after No-Topology training is completed for slice 3"
hexmask.long.word 0xA4 0.--9. 1. "PHY_NTP_EARLY_THRESHOLD_3,Threshold Criteria of early threshold after No-Topology training is completed for slice 3"
line.long 0xA8 "DDRSS_PHY_810,"
hexmask.long.word 0xA8 16.--25. 1. "PHY_NTP_PERIOD_THRESHOLD_MAX_3,Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 3"
hexmask.long.word 0xA8 0.--9. 1. "PHY_NTP_PERIOD_THRESHOLD_MIN_3,Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary to set period threshold/early threshold after No-Topology training is completed for slice 3"
line.long 0xAC "DDRSS_PHY_811,"
hexmask.long.byte 0xAC 16.--23. 1. "PHY_FIFO_PTR_OBS_3,Observation register containing read entry FIFO pointers for slice 3"
bitfld.long 0xAC 8.--13. "SC_PHY_MANUAL_CLEAR_3,Manual reset/clear of internal logic for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0xAC 0. "PHY_CALVL_VREF_DRIVING_SLICE_3,Indicates if slice 3 is used to drive the VREF value to the device during CA training" "0,1"
line.long 0xB0 "DDRSS_PHY_812,"
line.long 0xB4 "DDRSS_PHY_813,"
hexmask.long.word 0xB4 16.--26. 1. "PHY_MASTER_DLY_LOCK_OBS_3,Observation register containing master delay results for slice 3"
hexmask.long.word 0xB4 0.--15. 1. "PHY_LPBK_ERROR_COUNT_OBS_3,Observation register containing total number of loopback error data for slice 3"
line.long 0xB8 "DDRSS_PHY_814,"
hexmask.long.byte 0xB8 24.--31. 1. "PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 3"
hexmask.long.byte 0xB8 16.--23. 1. "PHY_MEAS_DLY_STEP_VALUE_3,Observation register containing fraction of the cycle in 1 delay element numerator with demominator of 512 for slice 3"
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hexmask.long.byte 0xB8 8.--14. 1. "PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3,Observation register containing read DQS base slave delay encoded value for slice 3"
hexmask.long.byte 0xB8 0.--6. 1. "PHY_RDDQ_SLV_DLY_ENC_OBS_3,Observation register containing read DQ slave delay encoded values for slice 3"
line.long 0xBC "DDRSS_PHY_815,"
hexmask.long.byte 0xBC 24.--30. 1. "PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3,Observation register containing write DQS base slave delay encoded value for slice 3"
hexmask.long.word 0xBC 8.--18. 1. "PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3,Observation register containing read DQS gate slave delay encoded value for slice 3"
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hexmask.long.byte 0xBC 0.--7. 1. "PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 3"
line.long 0xC0 "DDRSS_PHY_816,"
bitfld.long 0xC0 16.--18. "PHY_WR_SHIFT_OBS_3,Observation register containing automatic half cycle and cycle shift values for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC0 8.--15. 1. "PHY_WR_ADDER_SLV_DLY_ENC_OBS_3,Observation register containing write adder slave delay encoded value for slice 3"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3,Observation register containing write DQ base slave delay encoded value for slice 3"
line.long 0xC4 "DDRSS_PHY_817,"
hexmask.long.word 0xC4 16.--25. 1. "PHY_WRLVL_HARD1_DELAY_OBS_3,Observation register containing write leveling first hard 1 DQS slave delay for slice 3"
hexmask.long.word 0xC4 0.--9. 1. "PHY_WRLVL_HARD0_DELAY_OBS_3,Observation register containing write leveling last hard 0 DQS slave delay for slice 3"
line.long 0xC8 "DDRSS_PHY_818,"
hexmask.long.tbyte 0xC8 0.--16. 1. "PHY_WRLVL_STATUS_OBS_3,Observation register containing write leveling status for slice 3"
line.long 0xCC "DDRSS_PHY_819,"
hexmask.long.word 0xCC 16.--25. 1. "PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3,Observation register containing gate sample2 slave delay encoded values for slice 3"
hexmask.long.word 0xCC 0.--9. 1. "PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3,Observation register containing gate sample1 slave delay encoded values for slice 3"
line.long 0xD0 "DDRSS_PHY_820,"
hexmask.long.word 0xD0 16.--29. 1. "PHY_GTLVL_HARD0_DELAY_OBS_3,Observation register containing gate training first hard 0 DQS slave delay for slice 3"
hexmask.long.word 0xD0 0.--15. 1. "PHY_WRLVL_ERROR_OBS_3,Observation register containing write leveling error status for slice 3"
line.long 0xD4 "DDRSS_PHY_821,"
hexmask.long.word 0xD4 0.--13. 1. "PHY_GTLVL_HARD1_DELAY_OBS_3,Observation register containing gate training last hard 1 DQS slave delay for slice 3"
line.long 0xD8 "DDRSS_PHY_822,"
hexmask.long.tbyte 0xD8 0.--17. 1. "PHY_GTLVL_STATUS_OBS_3,Observation register containing gate training status for slice 3"
line.long 0xDC "DDRSS_PHY_823,"
hexmask.long.word 0xDC 16.--25. 1. "PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3,Observation register containing read leveling data window trailing edge slave delay setting for slice 3"
hexmask.long.word 0xDC 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3,Observation register containing read leveling data window leading edge slave delay setting for slice 3"
line.long 0xE0 "DDRSS_PHY_824,"
bitfld.long 0xE0 0.--1. "PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3,Observation register containing read leveling number of windows found for slice 3" "0,1,2,3"
line.long 0xE4 "DDRSS_PHY_825,"
line.long 0xE8 "DDRSS_PHY_826,"
line.long 0xEC "DDRSS_PHY_827,"
hexmask.long.word 0xEC 16.--26. 1. "PHY_WDQLVL_DQDM_TE_DLY_OBS_3,Observation register containing write data leveling data window trailing edge slave delay setting for slice 3"
hexmask.long.word 0xEC 0.--10. 1. "PHY_WDQLVL_DQDM_LE_DLY_OBS_3,Observation register containing write data leveling data window leading edge slave delay setting for slice 3"
line.long 0xF0 "DDRSS_PHY_828,"
line.long 0xF4 "DDRSS_PHY_829,"
line.long 0xF8 "DDRSS_PHY_830,"
hexmask.long 0xF8 0.--30. 1. "PHY_DDL_MODE_3,DDL mode for slice 3"
line.long 0xFC "DDRSS_PHY_831,"
bitfld.long 0xFC 0.--5. "PHY_DDL_MASK_3,DDL mask for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x100 "DDRSS_PHY_832,"
line.long 0x104 "DDRSS_PHY_833,"
line.long 0x108 "DDRSS_PHY_834,"
bitfld.long 0x108 24. "PHY_RX_CAL_OVERRIDE_3,Manual setting of RX Calibration enable for slice 3" "0,1"
bitfld.long 0x108 16. "SC_PHY_RX_CAL_START_3,Manual RX Calibration start for slice 3" "0,1"
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bitfld.long 0x108 8. "PHY_LP4_WDQS_OE_EXTEND_3,LPDDR4 write preamble extension enable for slice 3" "0,1"
hexmask.long.byte 0x108 0.--7. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_3,Specify threshold value for PHY init update tracking for slice 3"
line.long 0x10C "DDRSS_PHY_835,"
hexmask.long.word 0x10C 16.--24. 1. "PHY_RX_CAL_DQ0_3,RX Calibration codes for DQ0 for slice 3"
bitfld.long 0x10C 8. "PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3,Data slice power reduction disable for slice 3" "0,1"
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hexmask.long.byte 0x10C 0.--7. 1. "PHY_RX_CAL_SAMPLE_WAIT_3,RX Calibration state machine wait count for slice 3"
line.long 0x110 "DDRSS_PHY_836,"
hexmask.long.word 0x110 16.--24. 1. "PHY_RX_CAL_DQ2_3,RX Calibration codes for DQ2 for slice 3"
hexmask.long.word 0x110 0.--8. 1. "PHY_RX_CAL_DQ1_3,RX Calibration codes for DQ1 for slice 3"
line.long 0x114 "DDRSS_PHY_837,"
hexmask.long.word 0x114 16.--24. 1. "PHY_RX_CAL_DQ4_3,RX Calibration codes for DQ4 for slice 3"
hexmask.long.word 0x114 0.--8. 1. "PHY_RX_CAL_DQ3_3,RX Calibration codes for DQ3 for slice 3"
line.long 0x118 "DDRSS_PHY_838,"
hexmask.long.word 0x118 16.--24. 1. "PHY_RX_CAL_DQ6_3,RX Calibration codes for DQ6 for slice 3"
hexmask.long.word 0x118 0.--8. 1. "PHY_RX_CAL_DQ5_3,RX Calibration codes for DQ5 for slice 3"
line.long 0x11C "DDRSS_PHY_839,"
hexmask.long.word 0x11C 0.--8. 1. "PHY_RX_CAL_DQ7_3,RX Calibration codes for DQ7 for slice 3"
line.long 0x120 "DDRSS_PHY_840,"
hexmask.long.tbyte 0x120 0.--17. 1. "PHY_RX_CAL_DM_3,RX Calibration codes for DM for slice 3"
line.long 0x124 "DDRSS_PHY_841,"
hexmask.long.word 0x124 16.--24. 1. "PHY_RX_CAL_FDBK_3,RX Calibration codes for FDBK for slice 3"
hexmask.long.word 0x124 0.--8. 1. "PHY_RX_CAL_DQS_3,RX Calibration codes for DQS for slice 3"
line.long 0x128 "DDRSS_PHY_842,"
hexmask.long.word 0x128 16.--24. 1. "PHY_RX_CAL_LOCK_OBS_3,RX Calibration lock results for slice 3"
hexmask.long.word 0x128 0.--10. 1. "PHY_RX_CAL_OBS_3,RX Calibration results for slice 3"
line.long 0x12C "DDRSS_PHY_843,"
bitfld.long 0x12C 24. "PHY_RX_CAL_COMP_VAL_3,Expected C value from RX pad for slice 3" "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "PHY_RX_CAL_DIFF_ADJUST_3,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3"
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hexmask.long.byte 0x12C 8.--14. 1. "PHY_RX_CAL_SE_ADJUST_3,Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3"
bitfld.long 0x12C 0. "PHY_RX_CAL_DISABLE_3,RX CAL disable signal for slice 3 set 1 to bypass the rx calibration" "0,1"
line.long 0x130 "DDRSS_PHY_844,"
hexmask.long.word 0x130 16.--26. 1. "PHY_PAD_RX_BIAS_EN_3,Controls RX_BIAS_EN pin for each pad for slice 3"
hexmask.long.word 0x130 0.--11. 1. "PHY_RX_CAL_INDEX_MASK_3,RX offset calibration mask of all RX pad for slice 3"
line.long 0x134 "DDRSS_PHY_845,"
bitfld.long 0x134 24.--25. "PHY_DATA_DC_WEIGHT_3,Determines weight of average calculating for slice 3" "0,1,2,3"
hexmask.long.byte 0x134 16.--23. 1. "PHY_DATA_DC_CAL_TIMEOUT_3,Determines timeout number of iteration for slice 3"
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hexmask.long.byte 0x134 8.--15. 1. "PHY_DATA_DC_CAL_SAMPLE_WAIT_3,Determines number of cycles to wait for each sample for slice 3"
bitfld.long 0x134 0.--4. "PHY_STATIC_TOG_DISABLE_3,Control to disable toggle during static activity for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x138 "DDRSS_PHY_846,"
bitfld.long 0x138 24. "PHY_DATA_DC_ADJUST_DIRECT_3,Adjust direction for slice 3" "0,1"
hexmask.long.byte 0x138 16.--23. 1. "PHY_DATA_DC_ADJUST_THRSHLD_3,Duty cycle adjust threshold around the mid-point for slice 3"
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hexmask.long.byte 0x138 8.--15. 1. "PHY_DATA_DC_ADJUST_SAMPLE_CNT_3,Duty cycle adjust sample count for slice 3"
bitfld.long 0x138 0.--5. "PHY_DATA_DC_ADJUST_START_3,Duty cycle adjust starting value for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x13C "DDRSS_PHY_847,"
bitfld.long 0x13C 24.--26. "PHY_FDBK_PWR_CTRL_3,Shutoff gate feedback IO to reduce power for slice 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x13C 16.--17. "PHY_DATA_DC_SW_RANK_3,Rank selection for software based duty cycle correction for slice 3" "0,1,2,3"
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bitfld.long 0x13C 8. "PHY_DATA_DC_CAL_START_3,Manual trigger for DCC for slice 3" "0,1"
bitfld.long 0x13C 0. "PHY_DATA_DC_CAL_POLARITY_3,Calibration polarity for slice 3" "0,1"
line.long 0x140 "DDRSS_PHY_848,"
bitfld.long 0x140 24. "PHY_SLICE_PWR_RDC_DISABLE_3,Data slice power reduction disable for slice 3" "0,1"
bitfld.long 0x140 16. "PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3,Data slice DCC and RX_CAL block power reduction disable for slice 3" "0,1"
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bitfld.long 0x140 8. "PHY_RDPATH_GATE_DISABLE_3,Data slice read path power reduction disable for slice 3" "0,1"
bitfld.long 0x140 0. "PHY_SLV_DLY_CTRL_GATE_DISABLE_3,Data slice slv_dly_control block power reduction disable for slice 3" "0,1"
line.long 0x144 "DDRSS_PHY_849,"
hexmask.long.word 0x144 16.--29. 1. "PHY_DS_FSM_ERROR_INFO_3,Data slice level FSM Error Info for slice 3"
hexmask.long.word 0x144 0.--10. 1. "PHY_PARITY_ERROR_REGIF_3,Inject parity error to register interface signals for slice 3"
line.long 0x148 "DDRSS_PHY_850,"
hexmask.long.word 0x148 16.--29. 1. "SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3,Data slice level FSM Error Info for slice 3"
hexmask.long.word 0x148 0.--13. 1. "PHY_DS_FSM_ERROR_INFO_MASK_3,Data slice level FSM Error Info Mask for slice 3"
line.long 0x14C "DDRSS_PHY_851,"
bitfld.long 0x14C 16.--20. "SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3,Data slice level training/calibration Error Info for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14C 8.--12. "PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3,Data slice level training/calibration Error Info Mask for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x14C 0.--4. "PHY_DS_TRAIN_CALIB_ERROR_INFO_3,Data slice level training/calibration Error Info for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x150 "DDRSS_PHY_852,"
bitfld.long 0x150 24.--26. "PHY_DQS_TSEL_ENABLE_3,Operation type tsel enables for DQS signals for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x150 8.--23. 1. "PHY_DQ_TSEL_SELECT_3,Operation type tsel select values for DQ/DM signals for slice 3"
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bitfld.long 0x150 0.--2. "PHY_DQ_TSEL_ENABLE_3,Operation type tsel enables for DQ/DM signals for slice 3" "0,1,2,3,4,5,6,7"
line.long 0x154 "DDRSS_PHY_853,"
hexmask.long.byte 0x154 24.--30. 1. "PHY_VREF_INITIAL_START_POINT_3,Data slice initial VREF training start value for slice 3"
bitfld.long 0x154 16.--17. "PHY_TWO_CYC_PREAMBLE_3,2 cycle preamble support for slice 3" "0,1,2,3"
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hexmask.long.word 0x154 0.--15. 1. "PHY_DQS_TSEL_SELECT_3,Operation type tsel select values for DQS signals for slice 3"
line.long 0x158 "DDRSS_PHY_854,"
hexmask.long.byte 0x158 24.--31. 1. "PHY_NTP_WDQ_STEP_SIZE_3,Step size of WR DQ slave delay during No-Topology training for slice 3"
bitfld.long 0x158 16. "PHY_NTP_TRAIN_EN_3,Enable for No-Topology training for slice 3" "0,1"
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bitfld.long 0x158 8.--9. "PHY_VREF_TRAINING_CTRL_3,Data slice vref training enable control for slice 3" "0,1,2,3"
hexmask.long.byte 0x158 0.--6. 1. "PHY_VREF_INITIAL_STOP_POINT_3,Data slice initial VREF training stop value for slice 3"
line.long 0x15C "DDRSS_PHY_855,"
hexmask.long.word 0x15C 16.--26. 1. "PHY_NTP_WDQ_STOP_3,End of WR DQ slave delay in No-Topology training for slice 3"
hexmask.long.word 0x15C 0.--10. 1. "PHY_NTP_WDQ_START_3,Starting WR DQ slave delay in No-Topology training for slice 3"
line.long 0x160 "DDRSS_PHY_856,"
bitfld.long 0x160 24. "PHY_SW_WDQLVL_DVW_MIN_EN_3,SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 3" "0,1"
hexmask.long.word 0x160 8.--17. 1. "PHY_WDQLVL_DVW_MIN_3,Minimum data valid window across DQs and ranks for slice 3"
newline
hexmask.long.byte 0x160 0.--7. 1. "PHY_NTP_WDQ_BIT_EN_3,Enable Bit for WR DQ during No-Topology training for slice 3"
line.long 0x164 "DDRSS_PHY_857,"
bitfld.long 0x164 24.--28. "PHY_PAD_RX_DCD_0_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x164 16.--20. "PHY_PAD_TX_DCD_3,Controls TX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x164 8.--11. "PHY_FAST_LVL_EN_3,Enable for fast multi-pattern window search for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x164 0.--5. "PHY_WDQLVL_PER_START_OFFSET_3,Peridic training start point offset for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x168 "DDRSS_PHY_858,"
bitfld.long 0x168 24.--28. "PHY_PAD_RX_DCD_4_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 16.--20. "PHY_PAD_RX_DCD_3_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x168 8.--12. "PHY_PAD_RX_DCD_2_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x168 0.--4. "PHY_PAD_RX_DCD_1_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x16C "DDRSS_PHY_859,"
bitfld.long 0x16C 24.--28. "PHY_PAD_DM_RX_DCD_3,Controls RX_DCD pin for dm pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 16.--20. "PHY_PAD_RX_DCD_7_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x16C 8.--12. "PHY_PAD_RX_DCD_6_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x16C 0.--4. "PHY_PAD_RX_DCD_5_3,Controls RX_DCD pin for each pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x170 "DDRSS_PHY_860,"
bitfld.long 0x170 16.--21. "PHY_PAD_DSLICE_IO_CFG_3,Controls PCLK/PARK pin for pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x170 8.--12. "PHY_PAD_FDBK_RX_DCD_3,Controls RX_DCD pin for fdbk pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x170 0.--4. "PHY_PAD_DQS_RX_DCD_3,Controls RX_DCD pin for dqs pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x174 "DDRSS_PHY_861,"
hexmask.long.word 0x174 16.--25. 1. "PHY_RDDQ1_SLAVE_DELAY_3,Read DQ1 slave delay setting for slice 3"
hexmask.long.word 0x174 0.--9. 1. "PHY_RDDQ0_SLAVE_DELAY_3,Read DQ0 slave delay setting for slice 3"
line.long 0x178 "DDRSS_PHY_862,"
hexmask.long.word 0x178 16.--25. 1. "PHY_RDDQ3_SLAVE_DELAY_3,Read DQ3 slave delay setting for slice 3"
hexmask.long.word 0x178 0.--9. 1. "PHY_RDDQ2_SLAVE_DELAY_3,Read DQ2 slave delay setting for slice 3"
line.long 0x17C "DDRSS_PHY_863,"
hexmask.long.word 0x17C 16.--25. 1. "PHY_RDDQ5_SLAVE_DELAY_3,Read DQ5 slave delay setting for slice 3"
hexmask.long.word 0x17C 0.--9. 1. "PHY_RDDQ4_SLAVE_DELAY_3,Read DQ4 slave delay setting for slice 3"
line.long 0x180 "DDRSS_PHY_864,"
hexmask.long.word 0x180 16.--25. 1. "PHY_RDDQ7_SLAVE_DELAY_3,Read DQ7 slave delay setting for slice 3"
hexmask.long.word 0x180 0.--9. 1. "PHY_RDDQ6_SLAVE_DELAY_3,Read DQ6 slave delay setting for slice 3"
line.long 0x184 "DDRSS_PHY_865,"
bitfld.long 0x184 16.--18. "PHY_DATA_DC_CAL_CLK_SEL_3,Determines DCC CAL clock for slice 3" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x184 0.--9. 1. "PHY_RDDM_SLAVE_DELAY_3,Read DM/DBI slave delay setting for slice 3"
line.long 0x188 "DDRSS_PHY_866,"
hexmask.long.byte 0x188 24.--31. 1. "PHY_DQS_OE_TIMING_3,Start/end timing values for DQS output enable signals for slice 3"
hexmask.long.byte 0x188 16.--23. 1. "PHY_DQ_TSEL_WR_TIMING_3,Start/end timing values for DQ/DM write based termination enable and select signals for slice 3"
newline
hexmask.long.byte 0x188 8.--15. 1. "PHY_DQ_TSEL_RD_TIMING_3,Start/end timing values for DQ/DM read based termination enable and select signals for slice 3"
hexmask.long.byte 0x188 0.--7. 1. "PHY_DQ_OE_TIMING_3,Start/end timing values for DQ/DM output enable signals for slice 3"
line.long 0x18C "DDRSS_PHY_867,"
hexmask.long.byte 0x18C 24.--31. 1. "PHY_DQS_TSEL_WR_TIMING_3,Start/end timing values for DQS write based termination enable and select signals for slice 3"
hexmask.long.byte 0x18C 16.--23. 1. "PHY_DQS_OE_RD_TIMING_3,Start/end timing values for DQS read based OE extension for slice 3"
newline
hexmask.long.byte 0x18C 8.--15. 1. "PHY_DQS_TSEL_RD_TIMING_3,Start/end timing values for DQS read based termination enable and select signals for slice 3"
bitfld.long 0x18C 0.--3. "PHY_IO_PAD_DELAY_TIMING_3,Feedback pad's OPAD and IPAD delay timing for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "DDRSS_PHY_868,"
hexmask.long.word 0x190 16.--27. 1. "PHY_PAD_VREF_CTRL_DQ_3,Pad VREF control settings for DQ slice 3"
hexmask.long.word 0x190 0.--15. 1. "PHY_VREF_SETTING_TIME_3,Number of cycles for vref settle after setting is changed for slice 3"
line.long 0x194 "DDRSS_PHY_869,"
bitfld.long 0x194 24.--25. "PHY_RDDATA_EN_IE_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3" "0,1,2,3"
hexmask.long.byte 0x194 16.--23. 1. "PHY_DQS_IE_TIMING_3,Start/end timing values for DQS input enable signals for slice 3"
newline
hexmask.long.byte 0x194 8.--15. 1. "PHY_DQ_IE_TIMING_3,Start/end timing values for DQ/DM input enable signals for slice 3"
bitfld.long 0x194 0. "PHY_PER_CS_TRAINING_EN_3,Enables the per-rank training and read/write timing capabilities for slice 3" "0,1"
line.long 0x198 "DDRSS_PHY_870,"
bitfld.long 0x198 24.--28. "PHY_RDDATA_EN_OE_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x198 16.--20. "PHY_RDDATA_EN_TSEL_DLY_3,Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x198 8. "PHY_DBI_MODE_3,DBI mode for slice 3" "0,1"
bitfld.long 0x198 0.--1. "PHY_IE_MODE_3,Input enable mode bits for slice 3" "0,1,2,3"
line.long 0x19C "DDRSS_PHY_871,"
bitfld.long 0x19C 24.--29. "PHY_MASTER_DELAY_STEP_3,Incremental step size for master delay line locking algorithm for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x19C 8.--18. 1. "PHY_MASTER_DELAY_START_3,Start value for master delay line locking algorithm for slice 3"
newline
bitfld.long 0x19C 0.--3. "PHY_SW_MASTER_MODE_3,Master delay line override settings for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "DDRSS_PHY_872,"
hexmask.long.byte 0x1A0 24.--31. 1. "PHY_WRLVL_DLY_STEP_3,DQS slave delay step size during write leveling for slice 3"
bitfld.long 0x1A0 16.--19. "PHY_RPTR_UPDATE_3,Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "PHY_MASTER_DELAY_HALF_MEASURE_3,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 3"
hexmask.long.byte 0x1A0 0.--7. 1. "PHY_MASTER_DELAY_WAIT_3,Wait cycles for master delay line locking algorithm for slice 3"
line.long 0x1A4 "DDRSS_PHY_873,"
bitfld.long 0x1A4 24.--28. "PHY_GTLVL_RESP_WAIT_CNT_3,Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1A4 16.--19. "PHY_GTLVL_DLY_STEP_3,DQS slave delay step size during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1A4 8.--13. "PHY_WRLVL_RESP_WAIT_CNT_3,Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1A4 0.--3. "PHY_WRLVL_DLY_FINE_STEP_3,DQS slave delay fine step size during write leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "DDRSS_PHY_874,"
hexmask.long.word 0x1A8 16.--25. 1. "PHY_GTLVL_FINAL_STEP_3,Final backup step delay used in gate training algorithm for slice 3"
hexmask.long.word 0x1A8 0.--9. 1. "PHY_GTLVL_BACK_STEP_3,Interim backup step delay used in gate training algorithm for slice 3"
line.long 0x1AC "DDRSS_PHY_875,"
bitfld.long 0x1AC 24.--27. "PHY_RDLVL_DLY_STEP_3,DQS slave delay step size during read leveling for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1AC 16. "PHY_TOGGLE_PRE_SUPPORT_3,Support the toggle read preamble for LPDDR4 for slice 3" "0,1"
newline
bitfld.long 0x1AC 8.--11. "PHY_WDQLVL_QTR_DLY_STEP_3,Defines the step granularity for the logic to use once an edge is found for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 0.--7. 1. "PHY_WDQLVL_DLY_STEP_3,DQ slave delay step size during write data leveling for slice 3"
line.long 0x1B0 "DDRSS_PHY_876,"
hexmask.long.word 0x1B0 0.--9. 1. "PHY_RDLVL_MAX_EDGE_3,The maximun rdlvl slave delay search window for read eye training for slice 3"
line.long 0x1B4 "DDRSS_PHY_877,"
bitfld.long 0x1B4 24.--29. "PHY_RDLVL_PER_START_OFFSET_3,Peridic training start point offset for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1B4 16. "PHY_SW_RDLVL_DVW_MIN_EN_3,SW override to enable use of PHY_RDLVL_DVW_MIN for slice 3" "0,1"
newline
hexmask.long.word 0x1B4 0.--9. 1. "PHY_RDLVL_DVW_MIN_3,Minimum data valid window across DQs and ranks for slice 3"
line.long 0x1B8 "DDRSS_PHY_878,"
bitfld.long 0x1B8 16.--17. "PHY_DATA_DC_INIT_DISABLE_3,Disable duty cycle adjust at initialization for slice 3" "0,1,2,3"
bitfld.long 0x1B8 8.--10. "PHY_WRPATH_GATE_TIMING_3,Write path clock gating timing for slice 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1B8 0.--1. "PHY_WRPATH_GATE_DISABLE_3,Write path clock gating disable for slice 3" "0,1,2,3"
line.long 0x1BC "DDRSS_PHY_879,"
hexmask.long.word 0x1BC 16.--26. 1. "PHY_DATA_DC_DQ_INIT_SLV_DELAY_3,Initial value of write DQ slave delay for slice 3"
hexmask.long.word 0x1BC 0.--9. 1. "PHY_DATA_DC_DQS_INIT_SLV_DELAY_3,Initial value of write DQS slave delay for slice 3"
line.long 0x1C0 "DDRSS_PHY_880,"
hexmask.long.byte 0x1C0 24.--31. 1. "PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3,Clock measurement cell threshold offset for differential signals for slice 3"
hexmask.long.byte 0x1C0 16.--23. 1. "PHY_DATA_DC_DM_CLK_SE_THRSHLD_3,Clock measurement cell threshold offset for single ended signals for slice 3"
newline
bitfld.long 0x1C0 8. "PHY_DATA_DC_WDQLVL_ENABLE_3,Enable duty cycle adjust during write DQ training for slice 3" "0,1"
bitfld.long 0x1C0 0. "PHY_DATA_DC_WRLVL_ENABLE_3,Enable duty cycle adjust during write leveling for slice 3" "0,1"
line.long 0x1C4 "DDRSS_PHY_881,"
bitfld.long 0x1C4 16.--20. "PHY_RDDATA_EN_DLY_3,Number of cycles that the dfi_rddata_en signal is early for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C4 8.--13. "PHY_MEAS_DLY_STEP_ENABLE_3,Data slice training step definition using phy_meas_dly_step_value for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x1C4 0.--6. 1. "PHY_WDQ_OSC_DELTA_3,Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 3"
line.long 0x1C8 "DDRSS_PHY_882,"
line.long 0x1CC "DDRSS_PHY_883,"
bitfld.long 0x1CC 0.--3. "PHY_DQ_DM_SWIZZLE1_3,DQ/DM bit swizzling 1 for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "DDRSS_PHY_884,"
hexmask.long.word 0x1D0 16.--26. 1. "PHY_CLK_WRDQ1_SLAVE_DELAY_3,Write clock slave delay setting for DQ1 for slice 3"
hexmask.long.word 0x1D0 0.--10. 1. "PHY_CLK_WRDQ0_SLAVE_DELAY_3,Write clock slave delay setting for DQ0 for slice 3"
line.long 0x1D4 "DDRSS_PHY_885,"
hexmask.long.word 0x1D4 16.--26. 1. "PHY_CLK_WRDQ3_SLAVE_DELAY_3,Write clock slave delay setting for DQ3 for slice 3"
hexmask.long.word 0x1D4 0.--10. 1. "PHY_CLK_WRDQ2_SLAVE_DELAY_3,Write clock slave delay setting for DQ2 for slice 3"
line.long 0x1D8 "DDRSS_PHY_886,"
hexmask.long.word 0x1D8 16.--26. 1. "PHY_CLK_WRDQ5_SLAVE_DELAY_3,Write clock slave delay setting for DQ5 for slice 3"
hexmask.long.word 0x1D8 0.--10. 1. "PHY_CLK_WRDQ4_SLAVE_DELAY_3,Write clock slave delay setting for DQ4 for slice 3"
line.long 0x1DC "DDRSS_PHY_887,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_CLK_WRDQ7_SLAVE_DELAY_3,Write clock slave delay setting for DQ7 for slice 3"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_CLK_WRDQ6_SLAVE_DELAY_3,Write clock slave delay setting for DQ6 for slice 3"
line.long 0x1E0 "DDRSS_PHY_888,"
hexmask.long.word 0x1E0 16.--25. 1. "PHY_CLK_WRDQS_SLAVE_DELAY_3,Write clock slave delay setting for DQS for slice 3"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_CLK_WRDM_SLAVE_DELAY_3,Write clock slave delay setting for DM for slice 3"
line.long 0x1E4 "DDRSS_PHY_889,"
hexmask.long.word 0x1E4 8.--17. 1. "PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ0 for slice 3"
bitfld.long 0x1E4 0.--1. "PHY_WRLVL_THRESHOLD_ADJUST_3,Write level threshold adjust value based on those thresholds for DQS for slice 3" "0,1,2,3"
line.long 0x1E8 "DDRSS_PHY_890,"
hexmask.long.word 0x1E8 16.--25. 1. "PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ1 for slice 3"
hexmask.long.word 0x1E8 0.--9. 1. "PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ0 for slice 3"
line.long 0x1EC "DDRSS_PHY_891,"
hexmask.long.word 0x1EC 16.--25. 1. "PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ2 for slice 3"
hexmask.long.word 0x1EC 0.--9. 1. "PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ1 for slice 3"
line.long 0x1F0 "DDRSS_PHY_892,"
hexmask.long.word 0x1F0 16.--25. 1. "PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ3 for slice 3"
hexmask.long.word 0x1F0 0.--9. 1. "PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ2 for slice 3"
line.long 0x1F4 "DDRSS_PHY_893,"
hexmask.long.word 0x1F4 16.--25. 1. "PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ4 for slice 3"
hexmask.long.word 0x1F4 0.--9. 1. "PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ3 for slice 3"
line.long 0x1F8 "DDRSS_PHY_894,"
hexmask.long.word 0x1F8 16.--25. 1. "PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ5 for slice 3"
hexmask.long.word 0x1F8 0.--9. 1. "PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ4 for slice 3"
line.long 0x1FC "DDRSS_PHY_895,"
hexmask.long.word 0x1FC 16.--25. 1. "PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ6 for slice 3"
hexmask.long.word 0x1FC 0.--9. 1. "PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ5 for slice 3"
line.long 0x200 "DDRSS_PHY_896,"
hexmask.long.word 0x200 16.--25. 1. "PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DQ7 for slice 3"
hexmask.long.word 0x200 0.--9. 1. "PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ6 for slice 3"
line.long 0x204 "DDRSS_PHY_897,"
hexmask.long.word 0x204 16.--25. 1. "PHY_RDDQS_DM_RISE_SLAVE_DELAY_3,Rising edge read DQS slave delay setting for DM for slice 3"
hexmask.long.word 0x204 0.--9. 1. "PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DQ7 for slice 3"
line.long 0x208 "DDRSS_PHY_898,"
hexmask.long.word 0x208 16.--25. 1. "PHY_RDDQS_GATE_SLAVE_DELAY_3,Read DQS slave delay setting for slice 3"
hexmask.long.word 0x208 0.--9. 1. "PHY_RDDQS_DM_FALL_SLAVE_DELAY_3,Falling edge read DQS slave delay setting for DM for slice 3"
line.long 0x20C "DDRSS_PHY_899,"
hexmask.long.word 0x20C 16.--25. 1. "PHY_WRLVL_DELAY_EARLY_THRESHOLD_3,Write level delay threshold above which will be considered in previous cycle for slice 3"
bitfld.long 0x20C 8.--10. "PHY_WRITE_PATH_LAT_ADD_3,Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 0.--3. "PHY_RDDQS_LATENCY_ADJUST_3,Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "DDRSS_PHY_900,"
bitfld.long 0x210 16. "PHY_WRLVL_EARLY_FORCE_ZERO_3,Force the final write level delay value (that meets the early threshold) to 0 for slice 3" "0,1"
hexmask.long.word 0x210 0.--9. 1. "PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3,Write level delay threshold below which will add a cycle of write path latency for slice 3"
line.long 0x214 "DDRSS_PHY_901,"
bitfld.long 0x214 16.--19. "PHY_GTLVL_LAT_ADJ_START_3,Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x214 0.--9. 1. "PHY_GTLVL_RDDQS_SLV_DLY_START_3,Initial read DQS gate slave delay setting during gate training for slice 3"
line.long 0x218 "DDRSS_PHY_902,"
bitfld.long 0x218 24. "PHY_NTP_PASS_3,Indicates if No-topology training found a passing result for slice 3" "0,1"
bitfld.long 0x218 16.--19. "PHY_NTP_WRLAT_START_3,Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x218 0.--10. 1. "PHY_WDQLVL_DQDM_SLV_DLY_START_3,Initial DQ/DM slave delay setting during write data leveling for slice 3"
line.long 0x21C "DDRSS_PHY_903,"
hexmask.long.word 0x21C 0.--9. 1. "PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3,Read leveling starting value for the DQS/DQ slave delay settings for slice 3"
line.long 0x220 "DDRSS_PHY_904,"
hexmask.long.byte 0x220 24.--31. 1. "PHY_DATA_DC_DQ2_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x220 16.--23. 1. "PHY_DATA_DC_DQ1_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
newline
hexmask.long.byte 0x220 8.--15. 1. "PHY_DATA_DC_DQ0_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x220 0.--7. 1. "PHY_DATA_DC_DQS_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
line.long 0x224 "DDRSS_PHY_905,"
hexmask.long.byte 0x224 24.--31. 1. "PHY_DATA_DC_DQ6_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x224 16.--23. 1. "PHY_DATA_DC_DQ5_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
newline
hexmask.long.byte 0x224 8.--15. 1. "PHY_DATA_DC_DQ4_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
hexmask.long.byte 0x224 0.--7. 1. "PHY_DATA_DC_DQ3_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
line.long 0x228 "DDRSS_PHY_906,"
hexmask.long.word 0x228 16.--31. 1. "PHY_DSLICE_PAD_BOOSTPN_SETTING_3,Setting for boost P/N of pad for slice 3"
hexmask.long.byte 0x228 8.--15. 1. "PHY_DATA_DC_DM_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
newline
hexmask.long.byte 0x228 0.--7. 1. "PHY_DATA_DC_DQ7_CLK_ADJUST_3,Adjust value of Duty Cycle Adjuster for slice 3"
line.long 0x22C "DDRSS_PHY_907,"
bitfld.long 0x22C 16.--17. "PHY_DQS_FFE_3,TX_FFE setting for DQS pad for slice 3" "0,1,2,3"
bitfld.long 0x22C 8.--9. "PHY_DQ_FFE_3,TX_FFE setting for DQ/DM pad for slice 3" "0,1,2,3"
newline
bitfld.long 0x22C 0.--5. "PHY_DSLICE_PAD_RX_CTLE_SETTING_3,Setting for RX ctle P/N of pad for slice 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5000++0xCF
line.long 0x00 "DDRSS_PHY_1024,"
bitfld.long 0x00 24.--26. "SC_PHY_ADR_MANUAL_CLEAR_0,Manual reset/clear of internal logic for address slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "PHY_ADR_CLK_BYPASS_OVERRIDE_0,Bypass mode override setting for address slice 0" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0,Command/Address clock bypass mode slave delay setting for address slice 0"
line.long 0x04 "DDRSS_PHY_1025,"
line.long 0x08 "DDRSS_PHY_1026,"
bitfld.long 0x08 24.--27. "PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0,Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x08 16.--23. 1. "PHY_ADR_MEAS_DLY_STEP_VALUE_0,Contains the fraction of a cycle in 1 delay element numerator with demominator of 512 for address slice 0"
newline
hexmask.long.word 0x08 0.--15. 1. "PHY_ADR_LPBK_ERROR_COUNT_OBS_0,Observation register containing total number of loopback error data for address slice 0"
line.long 0x0C "DDRSS_PHY_1027,"
hexmask.long.byte 0x0C 24.--31. 1. "PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0,Observation register containing addr slave delay for address slice 0"
hexmask.long.byte 0x0C 16.--22. 1. "PHY_ADR_BASE_SLV_DLY_ENC_OBS_0,Observation register containing base slave delay for address slice 0"
newline
hexmask.long.word 0x0C 0.--10. 1. "PHY_ADR_MASTER_DLY_LOCK_OBS_0,Observation register containing master delay results for address slice 0"
line.long 0x10 "DDRSS_PHY_1028,"
bitfld.long 0x10 24. "PHY_ADR_TSEL_ENABLE_0,Enables tsel_en for address slice 0" "0,1"
bitfld.long 0x10 16. "SC_PHY_ADR_SNAP_OBS_REGS_0,Initiates a snapshot of the internal observation registers for address slice 0" "0,1"
newline
bitfld.long 0x10 8.--10. "PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0,Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0,Reserved for address slice 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "DDRSS_PHY_1029,"
bitfld.long 0x14 24. "PHY_ADR_PWR_RDC_DISABLE_0,Power reduction disable for address slice 0" "0,1"
bitfld.long 0x14 16.--20. "PHY_ADR_PRBS_PATTERN_MASK_0,PRBS7 mask signal for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x14 8.--14. 1. "PHY_ADR_PRBS_PATTERN_START_0,PRBS7 start pattern for address slice 0"
hexmask.long.byte 0x14 0.--6. 1. "PHY_ADR_LPBK_CONTROL_0,Loopback control bits for address slice 0"
line.long 0x18 "DDRSS_PHY_1030,"
bitfld.long 0x18 24. "PHY_ADR_IE_MODE_0,Input enable control for address slice 0" "0,1"
rbitfld.long 0x18 16.--18. "PHY_ADR_WRADDR_SHIFT_OBS_0,Observation register containing automatic half cycle and cycle shift values for address slice 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 8.--9. "PHY_ADR_TYPE_0,DRAM type for address slice 0" "0,1,2,3"
bitfld.long 0x18 0. "PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0,Power reduction slv_dly_control block gate disable for address slice 0" "0,1"
line.long 0x1C "DDRSS_PHY_1031,"
hexmask.long 0x1C 0.--26. 1. "PHY_ADR_DDL_MODE_0,DDL mode for address slice 0"
line.long 0x20 "DDRSS_PHY_1032,"
bitfld.long 0x20 0.--5. "PHY_ADR_DDL_MASK_0,DDL mask for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "DDRSS_PHY_1033,"
line.long 0x28 "DDRSS_PHY_1034,"
line.long 0x2C "DDRSS_PHY_1035,"
hexmask.long.word 0x2C 16.--26. 1. "PHY_ADR_CALVL_COARSE_DLY_0,Coarse CA training DDL increment value for address slice 0"
hexmask.long.word 0x2C 0.--10. 1. "PHY_ADR_CALVL_START_0,CA training DDL start value for address slice 0"
line.long 0x30 "DDRSS_PHY_1036,"
hexmask.long.word 0x30 0.--10. 1. "PHY_ADR_CALVL_QTR_0,CA training DDL quarter cycle delay value for address slice 0"
line.long 0x34 "DDRSS_PHY_1037,"
hexmask.long.tbyte 0x34 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE0_0,CA training RD DQ bit swizzle map 0 for address slice 0"
line.long 0x38 "DDRSS_PHY_1038,"
bitfld.long 0x38 24.--25. "PHY_ADR_CALVL_RANK_CTRL_0,CA training rank aggregation control bits for address slice 0" "0,1,2,3"
hexmask.long.tbyte 0x38 0.--23. 1. "PHY_ADR_CALVL_SWIZZLE1_0,CA training RD DQ bit swizzle map 1 for address slice 0"
line.long 0x3C "DDRSS_PHY_1039,"
hexmask.long.word 0x3C 16.--24. 1. "PHY_ADR_CALVL_PERIODIC_START_OFFSET_0,Relative offset to start periodic CALVL from previous result"
bitfld.long 0x3C 8.--11. "PHY_ADR_CALVL_RESP_WAIT_CNT_0,Number of samples to wait before sampling response during CA training for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x3C 0.--1. "PHY_ADR_CALVL_NUM_PATTERNS_0,Number of patterns to use during CA training for address slice 0" "0,1,2,3"
line.long 0x40 "DDRSS_PHY_1040,"
bitfld.long 0x40 24.--26. "PHY_ADR_CALVL_OBS_SELECT_0,CA bit lane to observe result from OBS0 during CA training for address slice 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x40 16. "SC_PHY_ADR_CALVL_ERROR_CLR_0,Clears the CA training state machine error status for address slice 0" "0,1"
newline
bitfld.long 0x40 8. "SC_PHY_ADR_CALVL_DEBUG_CONT_0,Allows the CA training state machine to advance (when in debug mode) for address slice 0" "0,1"
bitfld.long 0x40 0. "PHY_ADR_CALVL_DEBUG_MODE_0,Enables CA training debug mode for address slice 0" "0,1"
line.long 0x44 "DDRSS_PHY_1041,"
line.long 0x48 "DDRSS_PHY_1042,"
line.long 0x4C "DDRSS_PHY_1043,"
line.long 0x50 "DDRSS_PHY_1044,"
line.long 0x54 "DDRSS_PHY_1045,"
hexmask.long.tbyte 0x54 0.--19. 1. "PHY_ADR_CALVL_FG_0_0,CA training foreground pattern 0 for address slice 0"
line.long 0x58 "DDRSS_PHY_1046,"
hexmask.long.tbyte 0x58 0.--19. 1. "PHY_ADR_CALVL_BG_0_0,CA training background pattern 0 for address slice 0"
line.long 0x5C "DDRSS_PHY_1047,"
hexmask.long.tbyte 0x5C 0.--19. 1. "PHY_ADR_CALVL_FG_1_0,CA training foreground pattern 1 for address slice 0"
line.long 0x60 "DDRSS_PHY_1048,"
hexmask.long.tbyte 0x60 0.--19. 1. "PHY_ADR_CALVL_BG_1_0,CA training background pattern 1 for address slice 0"
line.long 0x64 "DDRSS_PHY_1049,"
hexmask.long.tbyte 0x64 0.--19. 1. "PHY_ADR_CALVL_FG_2_0,CA training foreground pattern 2 for address slice 0"
line.long 0x68 "DDRSS_PHY_1050,"
hexmask.long.tbyte 0x68 0.--19. 1. "PHY_ADR_CALVL_BG_2_0,CA training background pattern 2 for address slice 0"
line.long 0x6C "DDRSS_PHY_1051,"
hexmask.long.tbyte 0x6C 0.--19. 1. "PHY_ADR_CALVL_FG_3_0,CA training foreground pattern 3 for address slice 0"
line.long 0x70 "DDRSS_PHY_1052,"
hexmask.long.tbyte 0x70 0.--19. 1. "PHY_ADR_CALVL_BG_3_0,CA training background pattern 3 for address slice 0"
line.long 0x74 "DDRSS_PHY_1053,"
hexmask.long.tbyte 0x74 0.--23. 1. "PHY_ADR_ADDR_SEL_0,Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 0"
line.long 0x78 "DDRSS_PHY_1054,"
bitfld.long 0x78 24.--29. "PHY_ADR_SEG_MASK_0,Segment mask bit for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x78 16.--21. "PHY_ADR_BIT_MASK_0,Mask bit for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x78 0.--9. 1. "PHY_ADR_LP4_BOOT_SLV_DELAY_0,Address slave delay setting during the LPDDR4 boot frequency operation for address slice 0"
line.long 0x7C "DDRSS_PHY_1055,"
bitfld.long 0x7C 24.--29. "PHY_ADR_SW_TXIO_CTRL_0,Controls address pad output enable for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x7C 16.--19. "PHY_ADR_STATIC_TOG_DISABLE_0,Toggle control during static activity for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x7C 8.--13. "PHY_ADR_CSLVL_TRAIN_MASK_0,Mask bit for CS training participation for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x7C 0.--5. "PHY_ADR_CALVL_TRAIN_MASK_0,Mask bit for CA training participation for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DDRSS_PHY_1056,"
hexmask.long.byte 0x80 24.--31. 1. "PHY_ADR_DC_ADR2_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 2 for address slice 0"
hexmask.long.byte 0x80 16.--23. 1. "PHY_ADR_DC_ADR1_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 1 for address slice 0"
newline
hexmask.long.byte 0x80 8.--15. 1. "PHY_ADR_DC_ADR0_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 0 for address slice 0"
bitfld.long 0x80 0.--1. "PHY_ADR_DC_INIT_DISABLE_0,Duty Cycle Corrector disable at initialization for address slice 0" "0,1,2,3"
line.long 0x84 "DDRSS_PHY_1057,"
bitfld.long 0x84 24. "PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0,DCC and RX_CAL clk gate disable for address slice 0" "0,1"
hexmask.long.byte 0x84 16.--23. 1. "PHY_ADR_DC_ADR5_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 5 for address slice 0"
newline
hexmask.long.byte 0x84 8.--15. 1. "PHY_ADR_DC_ADR4_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 4 for address slice 0"
hexmask.long.byte 0x84 0.--7. 1. "PHY_ADR_DC_ADR3_CLK_ADJUST_0,Adjust value of Clock Duty Cycle Adjuster lane 3 for address slice 0"
line.long 0x88 "DDRSS_PHY_1058,"
bitfld.long 0x88 24.--29. "PHY_ADR_DC_ADJUST_START_0,DCC calibration starting value for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x88 16.--17. "PHY_ADR_DC_WEIGHT_0,DCC weighting factor base value for address slice 0" "0,1,2,3"
newline
hexmask.long.byte 0x88 8.--15. 1. "PHY_ADR_DC_CAL_TIMEOUT_0,DCC number of iterations to wait before timeout for address slice 0"
hexmask.long.byte 0x88 0.--7. 1. "PHY_ADR_DC_CAL_SAMPLE_WAIT_0,DCC cycles to wait after calibration change before sampling results for address slice 0"
line.long 0x8C "DDRSS_PHY_1059,"
bitfld.long 0x8C 24. "PHY_ADR_DC_CAL_POLARITY_0,DCC calibration polarity for address slice 0" "0,1"
bitfld.long 0x8C 16. "PHY_ADR_DC_ADJUST_DIRECT_0,DCC adjust direction for address slice 0" "0,1"
newline
hexmask.long.byte 0x8C 8.--15. 1. "PHY_ADR_DC_ADJUST_THRSHLD_0,DCC adjust threshold around the mid-point for address slice 0"
hexmask.long.byte 0x8C 0.--7. 1. "PHY_ADR_DC_ADJUST_SAMPLE_CNT_0,DCC number of samples to take for address slice 0"
line.long 0x90 "DDRSS_PHY_1060,"
hexmask.long.word 0x90 16.--26. 1. "PHY_PARITY_ERROR_REGIF_ADR_0,Inject parity error to register interface signals for address slice 0"
bitfld.long 0x90 8.--13. "PHY_ADR_SW_TXPWR_CTRL_0,Disable address output enables in deep sleep mode for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x90 0. "PHY_ADR_DC_CAL_START_0,DCC Manual trigger for address slice 0" "0,1"
line.long 0x94 "DDRSS_PHY_1061,"
hexmask.long.word 0x94 16.--24. 1. "PHY_AS_FSM_ERROR_INFO_MASK_0,FSM Error Info Mask for address slice 0"
hexmask.long.word 0x94 0.--8. 1. "PHY_AS_FSM_ERROR_INFO_0,FSM Error Info for address slice 0"
line.long 0x98 "DDRSS_PHY_1062,"
bitfld.long 0x98 24. "PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0,Training/Calibration Error Info Mask for address slice 0" "0,1"
rbitfld.long 0x98 16. "PHY_AS_TRAIN_CALIB_ERROR_INFO_0,Training/Calibration Error Info for address slice 0" "0,1"
newline
hexmask.long.word 0x98 0.--8. 1. "SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0,FSM Error Info clear for address slice 0"
line.long 0x9C "DDRSS_PHY_1063,"
bitfld.long 0x9C 0. "SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0,Training/Calibration Error Info clear for address slice 0" "0,1"
line.long 0xA0 "DDRSS_PHY_1064,"
hexmask.long.word 0xA0 16.--26. 1. "PHY_PAD_ADR_IO_CFG_0,Controls I/O pads for address pad for address slice 0"
bitfld.long 0xA0 8.--10. "PHY_ADR_DC_CAL_CLK_SEL_0,DCC CAL clock for address slice 0" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xA0 0.--7. 1. "PHY_ADR_TSEL_SELECT_0,Tsel select values for address slice 0"
line.long 0xA4 "DDRSS_PHY_1065,"
bitfld.long 0xA4 24.--28. "PHY_ADR1_SW_WRADDR_SHIFT_0,Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xA4 8.--18. 1. "PHY_ADR0_CLK_WR_SLAVE_DELAY_0,CA bit 0 slave delay setting for address slice 0"
newline
bitfld.long 0xA4 0.--4. "PHY_ADR0_SW_WRADDR_SHIFT_0,Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA8 "DDRSS_PHY_1066,"
bitfld.long 0xA8 16.--20. "PHY_ADR2_SW_WRADDR_SHIFT_0,Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xA8 0.--10. 1. "PHY_ADR1_CLK_WR_SLAVE_DELAY_0,CA bit 1 slave delay setting for address slice 0"
line.long 0xAC "DDRSS_PHY_1067,"
bitfld.long 0xAC 16.--20. "PHY_ADR3_SW_WRADDR_SHIFT_0,Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xAC 0.--10. 1. "PHY_ADR2_CLK_WR_SLAVE_DELAY_0,CA bit 2 slave delay setting for address slice 0"
line.long 0xB0 "DDRSS_PHY_1068,"
bitfld.long 0xB0 16.--20. "PHY_ADR4_SW_WRADDR_SHIFT_0,Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xB0 0.--10. 1. "PHY_ADR3_CLK_WR_SLAVE_DELAY_0,CA bit 3 slave delay setting for address slice 0"
line.long 0xB4 "DDRSS_PHY_1069,"
bitfld.long 0xB4 16.--20. "PHY_ADR5_SW_WRADDR_SHIFT_0,Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0xB4 0.--10. 1. "PHY_ADR4_CLK_WR_SLAVE_DELAY_0,CA bit 4 slave delay setting for address slice 0"
line.long 0xB8 "DDRSS_PHY_1070,"
bitfld.long 0xB8 16.--19. "PHY_ADR_SW_MASTER_MODE_0,Master delay line override settings for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0xB8 0.--10. 1. "PHY_ADR5_CLK_WR_SLAVE_DELAY_0,CA bit 5 slave delay setting for address slice 0"
line.long 0xBC "DDRSS_PHY_1071,"
hexmask.long.byte 0xBC 24.--31. 1. "PHY_ADR_MASTER_DELAY_WAIT_0,Wait cycles for master delay line locking algorithm for address slice 0"
bitfld.long 0xBC 16.--21. "PHY_ADR_MASTER_DELAY_STEP_0,Incremental step size for master delay line locking algorithm for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0xBC 0.--10. 1. "PHY_ADR_MASTER_DELAY_START_0,Start value for master delay line locking algorithm for address slice 0"
line.long 0xC0 "DDRSS_PHY_1072,"
bitfld.long 0xC0 24. "PHY_ADR_SW_CALVL_DVW_MIN_EN_0,Enables the software override data valid window size during CA training for address slice 0" "0,1"
hexmask.long.word 0xC0 8.--17. 1. "PHY_ADR_SW_CALVL_DVW_MIN_0,Sets the software override data valid window size during CA training for address slice 0"
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hexmask.long.byte 0xC0 0.--7. 1. "PHY_ADR_MASTER_DELAY_HALF_MEASURE_0,Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 0"
line.long 0xC4 "DDRSS_PHY_1073,"
bitfld.long 0xC4 0.--3. "PHY_ADR_CALVL_DLY_STEP_0,Sets the delay step size plus 1 during CA training for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "DDRSS_PHY_1074,"
hexmask.long.word 0xC8 16.--25. 1. "PHY_ADR_DC_INIT_SLV_DELAY_0,DCC initialization value of write ADDR slave delay for address slice 0"
bitfld.long 0xC8 8. "PHY_ADR_MEAS_DLY_STEP_ENABLE_0,Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 0" "0,1"
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bitfld.long 0xC8 0.--3. "PHY_ADR_CALVL_CAPTURE_CNT_0,Number of samples to take at each ADDR slave delay setting during CA training for address slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "DDRSS_PHY_1075,"
hexmask.long.byte 0xCC 8.--15. 1. "PHY_ADR_DC_DM_CLK_THRSHLD_0,DCC clock measurement cell threshold offset for address slice 0"
bitfld.long 0xCC 0. "PHY_ADR_DC_CALVL_ENABLE_0,DCC enable duty cycle adjust during CA leveling for address slice 0" "0,1"
group.long 0x5400++0x23B
line.long 0x00 "DDRSS_PHY_1280,"
bitfld.long 0x00 0.--1. "PHY_FREQ_SEL,Specifies which copy of the frequency-dependent timing parameters will be used by the PHY" "0,1,2,3"
line.long 0x04 "DDRSS_PHY_1281,"
bitfld.long 0x04 24.--28. "PHY_SW_GRP0_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--17. "PHY_FREQ_SEL_INDEX,Selects which frequency set to update when PHY_FREQ_SEL_MULTICAST_EN is not set" "0,1,2,3"
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bitfld.long 0x04 8. "PHY_FREQ_SEL_MULTICAST_EN,When set a register write will update parameters for all frequency sets simultaneously" "0,1"
bitfld.long 0x04 0. "PHY_FREQ_SEL_FROM_REGIF,Indicates which source is used to select the frequency copy" "0,1"
line.long 0x08 "DDRSS_PHY_1282,"
bitfld.long 0x08 24.--28. "PHY_SW_GRP0_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "PHY_SW_GRP3_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--12. "PHY_SW_GRP2_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "PHY_SW_GRP1_SHIFT_0,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "DDRSS_PHY_1283,"
bitfld.long 0x0C 16.--20. "PHY_SW_GRP3_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "PHY_SW_GRP2_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. "PHY_SW_GRP1_SHIFT_1,Address slice slave delay setting for address slice 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "DDRSS_PHY_1284,"
bitfld.long 0x10 24. "PHY_GRP_BYPASS_OVERRIDE,Address/control group slice bypass mode override setting" "0,1"
bitfld.long 0x10 16.--20. "PHY_SW_GRP_BYPASS_SHIFT,Address/control group slice bypass mode shift settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x10 0.--10. 1. "PHY_GRP_BYPASS_SLAVE_DELAY,Address/control group slice bypass mode slave delay setting"
line.long 0x14 "DDRSS_PHY_1285,"
hexmask.long.word 0x14 16.--26. 1. "PHY_CSLVL_START,Defines the CS training DDL start value"
bitfld.long 0x14 8. "PHY_MANUAL_UPDATE_PHYUPD_ENABLE,Manual update selection of all slave delay line settings" "0,1"
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bitfld.long 0x14 0. "SC_PHY_MANUAL_UPDATE,Manual update of all slave delay line settings" "0,1"
line.long 0x18 "DDRSS_PHY_1286,"
bitfld.long 0x18 24. "SC_PHY_CSLVL_DEBUG_CONT,Allows the CS training state machine to advance (when in debug mode)" "0,1"
bitfld.long 0x18 16. "PHY_CSLVL_DEBUG_MODE,Enables CS training debug mode" "0,1"
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hexmask.long.word 0x18 0.--10. 1. "PHY_CSLVL_COARSE_DLY,Defines the CS training DDL coarse cycle delay value"
line.long 0x1C "DDRSS_PHY_1287,"
bitfld.long 0x1C 0. "SC_PHY_CSLVL_ERROR_CLR,Clears the CS training state machine error status" "0,1"
line.long 0x20 "DDRSS_PHY_1288,"
line.long 0x24 "DDRSS_PHY_1289,"
line.long 0x28 "DDRSS_PHY_1290,"
line.long 0x2C "DDRSS_PHY_1291,"
bitfld.long 0x2C 24. "PHY_LP4_BOOT_DISABLE,Controls the handling of the DFI frequency" "0,1"
hexmask.long.word 0x2C 8.--16. 1. "PHY_CSLVL_PERIODIC_START_OFFSET,Defines the relative offset from previous LE and TE to start periodic CSLVL with"
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bitfld.long 0x2C 0. "PHY_CSLVL_ENABLE,CS training enable" "0,1"
line.long 0x30 "DDRSS_PHY_1292,"
hexmask.long.word 0x30 8.--18. 1. "PHY_CSLVL_QTR,Defines the CS training DDL 1/4 cycle delay value"
bitfld.long 0x30 0.--3. "PHY_CSLVL_CS_MAP,CS training map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DDRSS_PHY_1293,"
hexmask.long.byte 0x34 24.--31. 1. "PHY_CALVL_CS_MAP,Defines the slice numbers associated with each CS during CA training"
bitfld.long 0x34 16.--19. "PHY_CSLVL_COARSE_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training coarse CA training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x34 0.--10. 1. "PHY_CSLVL_COARSE_CHK,Defines the CS training coarse CA training DDL 1/16th cycle delay value"
line.long 0x38 "DDRSS_PHY_1294,"
bitfld.long 0x38 24. "PHY_ADRCTL_LPDDR,Adds a cycle of delay for the address/control slices to match the address slice" "0,1"
bitfld.long 0x38 16.--17. "PHY_DFI_PHYUPD_TYPE,Defines the value of the dfi_phyupd_type output signal to MC" "0,1,2,3"
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bitfld.long 0x38 8. "PHY_ADRCTL_SNAP_OBS_REGS,Initiates a snapshot of the internal observation registers for the address/control block" "0,1"
bitfld.long 0x38 0.--2. "PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE,Reserved for the address/control master" "0,1,2,3,4,5,6,7"
line.long 0x3C "DDRSS_PHY_1295,"
hexmask.long.byte 0x3C 24.--31. 1. "PHY_CLK_DC_CAL_TIMEOUT,Duty cycle correction maximum iteration count"
hexmask.long.byte 0x3C 16.--23. 1. "PHY_CLK_DC_CAL_SAMPLE_WAIT,Number of cal clock cycles to wait for a sample to be taken"
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bitfld.long 0x3C 8. "PHY_LPDDR3_CS,Alters reset state polarity for LPDDR chip selects" "0,1"
bitfld.long 0x3C 0. "PHY_LP4_ACTIVE,Indicates an LPDDR4 device is connected to the PHY" "0,1"
line.long 0x40 "DDRSS_PHY_1296,"
hexmask.long.byte 0x40 24.--31. 1. "PHY_CLK_DC_ADJUST_SAMPLE_CNT,Duty cycle correction algorithm sample count per adjustment setting"
bitfld.long 0x40 16.--21. "PHY_CLK_DC_ADJUST_START,Duty cycle correction algorithm adjustment starting value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x40 8. "PHY_CLK_DC_FREQ_CHG_ADJ,Duty cycle correction during frequency change control" "0,1"
bitfld.long 0x40 0.--1. "PHY_CLK_DC_WEIGHT,Duty cycle correction weighting factor base value" "0,1,2,3"
line.long 0x44 "DDRSS_PHY_1297,"
bitfld.long 0x44 24. "PHY_CLK_DC_CAL_START,Duty cycle correction calibration manual start" "0,1"
bitfld.long 0x44 16. "PHY_CLK_DC_CAL_POLARITY,Duty cycle correction algorithm measurement polarity" "0,1"
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bitfld.long 0x44 8. "PHY_CLK_DC_ADJUST_DIRECT,Duty cycle correction algorithm adjustment direction" "0,1"
hexmask.long.byte 0x44 0.--7. 1. "PHY_CLK_DC_ADJUST_THRSHLD,Duty cycle correction algorithm threshold delta comparison"
line.long 0x48 "DDRSS_PHY_1298,"
bitfld.long 0x48 24.--27. "PHY_SW_TXIO_CTRL_1,This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x48 16.--19. "PHY_SW_TXIO_CTRL_0,This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 8. "PHY_CONTINUOUS_CLK_CAL_UPDATE,Continuous update of all latest PVTP PVTN and PVTR values to the CLK IO pads" "0,1"
bitfld.long 0x48 0. "SC_PHY_UPDATE_CLK_CAL_VALUES,Manual update of all latest PVTP PVTN and PVTR values to the CLK IO pads" "0,1"
line.long 0x4C "DDRSS_PHY_1299,"
bitfld.long 0x4C 24. "PHY_MEMCLK_SW_TXPWR_CTRL,This register is used to control if clk pads should be shutoff for TX mode in deep sleep mode" "0,1"
bitfld.long 0x4C 16.--19. "PHY_ADRCTL_SW_TXPWR_CTRL_1,This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x4C 8.--11. "PHY_ADRCTL_SW_TXPWR_CTRL_0,This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4C 0. "PHY_MEMCLK_SW_TXIO_CTRL,This register is used to control if clk pads should be shutoff for TX mode" "0,1"
line.long 0x50 "DDRSS_PHY_1300,"
hexmask.long.word 0x50 16.--31. 1. "PHY_STATIC_TOG_CONTROL,Clock divider to create toggle signal"
bitfld.long 0x50 8. "PHY_BYTE_DISABLE_STATIC_TOG_DISABLE,Control to disable the toggle signal for data slice during static activity when dfi_data_byte_disable is asserted" "0,1"
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bitfld.long 0x50 0. "PHY_TOP_STATIC_TOG_DISABLE,Disables the generation of the toggle for static clock based paths in the PHY to prevent assymetric aging" "0,1"
line.long 0x54 "DDRSS_PHY_1301,"
bitfld.long 0x54 16. "PHY_LP4_BOOT_PLL_BYPASS,PHY clock PLL bypass select" "0,1"
bitfld.long 0x54 8. "PHY_MEMCLK_STATIC_TOG_DISABLE,Control to disable toggle during static activity" "0,1"
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bitfld.long 0x54 0.--3. "PHY_ADRCTL_STATIC_TOG_DISABLE,Control to disable toggle during static activity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "DDRSS_PHY_1302,"
line.long 0x5C "DDRSS_PHY_1303,"
hexmask.long.word 0x5C 0.--15. 1. "PHY_PLL_WAIT,PHY clock PLL wait time after locking"
line.long 0x60 "DDRSS_PHY_1304,"
bitfld.long 0x60 0. "PHY_SW_PLL_BYPASS,PHY clock PLL bypass select" "0,1"
line.long 0x64 "DDRSS_PHY_1305,"
bitfld.long 0x64 24.--27. "PHY_CS_ACS_ALLOCATION_BIT1_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x64 16.--19. "PHY_CS_ACS_ALLOCATION_BIT0_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x64 8.--11. "PHY_SET_DFI_INPUT_1,Used to indicate the default value of the adrctl slice bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x64 0.--3. "PHY_SET_DFI_INPUT_0,Used to indicate the default value of the adrctl slice bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "DDRSS_PHY_1306,"
bitfld.long 0x68 24.--27. "PHY_CS_ACS_ALLOCATION_BIT1_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x68 16.--19. "PHY_CS_ACS_ALLOCATION_BIT0_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x68 8.--11. "PHY_CS_ACS_ALLOCATION_BIT3_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x68 0.--3. "PHY_CS_ACS_ALLOCATION_BIT2_0,The map for which chip select is associated with each bit in the adrctl slice 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DDRSS_PHY_1307,"
bitfld.long 0x6C 24. "PHY_CLK_DC_INIT_DISABLE,Disable duty cycle adjust at initialization" "0,1"
hexmask.long.byte 0x6C 16.--23. 1. "PHY_CLK_DC_ADJUST_0,Adjust value of Duty Cycle Adjuster for clock slice 0"
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bitfld.long 0x6C 8.--11. "PHY_CS_ACS_ALLOCATION_BIT3_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 0.--3. "PHY_CS_ACS_ALLOCATION_BIT2_1,The map for which chip select is associated with each bit in the adrctl slice 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "DDRSS_PHY_1308,"
hexmask.long.word 0x70 8.--20. 1. "PHY_LP4_BOOT_PLL_CTRL,PHY deskew PLL controls for LPDDR4 boot frequency"
hexmask.long.byte 0x70 0.--7. 1. "PHY_CLK_DC_DM_THRSHLD,Data measurement cell threshold offset"
line.long 0x74 "DDRSS_PHY_1309,"
bitfld.long 0x74 16. "PHY_USE_PLL_DSKEWCALLOCK,Use DSKEWCALLOCK or not" "0,1"
hexmask.long.word 0x74 0.--15. 1. "PHY_PLL_CTRL_OVERRIDE,Individual PHY clock PLL control overrides"
line.long 0x78 "DDRSS_PHY_1310,"
bitfld.long 0x78 24.--25. "SC_PHY_PLL_SPO_CAL_SNAP_OBS,Register command to take a snapshot of PLL output" "0,1,2,3"
hexmask.long.tbyte 0x78 0.--18. 1. "PHY_PLL_SPO_CAL_CTRL,PLL SPO Cal controls"
line.long 0x7C "DDRSS_PHY_1311,"
bitfld.long 0x7C 16.--17. "SC_PHY_PLL_CAL_CLK_MEAS,Register command to initiate cal_clklout clock frequency measurement" "0,1,2,3"
hexmask.long.word 0x7C 0.--9. 1. "PHY_PLL_CAL_CLK_MEAS_CYCLES,Measurement cycles of cal_clkout clock"
line.long 0x80 "DDRSS_PHY_1312,"
hexmask.long.word 0x80 0.--15. 1. "PHY_PLL_OBS_0,PHY TOP level clock PLL_0 observe values"
line.long 0x84 "DDRSS_PHY_1313,"
hexmask.long.tbyte 0x84 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_0,PHY TOP level PLL_0 SPO Cal observe values"
line.long 0x88 "DDRSS_PHY_1314,"
hexmask.long.tbyte 0x88 0.--17. 1. "PHY_PLL_CAL_CLK_MEAS_OBS_0,PHY TOP level PLL_0 cal_clkout measurement observe values"
line.long 0x8C "DDRSS_PHY_1315,"
hexmask.long.word 0x8C 0.--15. 1. "PHY_PLL_OBS_1,PHY TOP level clock PLL_1 observe values"
line.long 0x90 "DDRSS_PHY_1316,"
hexmask.long.tbyte 0x90 0.--16. 1. "PHY_PLL_SPO_CAL_OBS_1,PHY TOP level PLL_1 SPO Cal observe values"
line.long 0x94 "DDRSS_PHY_1317,"
bitfld.long 0x94 24. "PHY_LP4_BOOT_LOW_FREQ_SEL,Control the PLL domain enter/exit from the negative clock edge for LPDDR4 boot frequency" "0,1"
hexmask.long.tbyte 0x94 0.--17. 1. "PHY_PLL_CAL_CLK_MEAS_OBS_1,PHY TOP level PLL_1 cal_clkout measurement observe values"
line.long 0x98 "DDRSS_PHY_1318,"
bitfld.long 0x98 16. "PHY_LS_IDLE_EN,Indicates the Reduced Idle Power State is enabled in low power mode" "0,1"
hexmask.long.byte 0x98 8.--15. 1. "PHY_LP_WAKEUP,Specifies the number of cycles the PHY takes to wakeup in low power mode"
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bitfld.long 0x98 0.--3. "PHY_TCKSRE_WAIT,Specifies the number of cycles the PHY should wait before turning off the PLL for a deep sleep or DFS event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "DDRSS_PHY_1319,"
bitfld.long 0x9C 16. "PHY_TDFI_PHY_WRDELAY,DFI timing parameter TDFI_PHY_WRDELAY" "0,1"
hexmask.long.word 0x9C 0.--9. 1. "PHY_LP_CTRLUPD_CNTR_CFG,Specifies the number of cycles the PHY takes from light sleep req deassert to ack deassert in low power mode"
line.long 0xA0 "DDRSS_PHY_1320,"
hexmask.long.tbyte 0xA0 0.--17. 1. "PHY_PAD_FDBK_TERM,Controls term settings for gate feedback pads"
line.long 0xA4 "DDRSS_PHY_1321,"
hexmask.long.tbyte 0xA4 0.--16. 1. "PHY_PAD_DATA_TERM,Controls term settings for data pads"
line.long 0xA8 "DDRSS_PHY_1322,"
hexmask.long.tbyte 0xA8 0.--16. 1. "PHY_PAD_DQS_TERM,Controls term settings for dqs pads"
line.long 0xAC "DDRSS_PHY_1323,"
hexmask.long.tbyte 0xAC 0.--17. 1. "PHY_PAD_ADDR_TERM,Controls term settings for the address/control pads"
line.long 0xB0 "DDRSS_PHY_1324,"
hexmask.long.tbyte 0xB0 0.--17. 1. "PHY_PAD_CLK_TERM,Controls term settings for clock pads"
line.long 0xB4 "DDRSS_PHY_1325,"
hexmask.long.tbyte 0xB4 0.--17. 1. "PHY_PAD_CKE_TERM,Controls term settings for cke pads"
line.long 0xB8 "DDRSS_PHY_1326,"
hexmask.long.tbyte 0xB8 0.--17. 1. "PHY_PAD_RST_TERM,Controls term settings for reset_n pads"
line.long 0xBC "DDRSS_PHY_1327,"
hexmask.long.tbyte 0xBC 0.--17. 1. "PHY_PAD_CS_TERM,Controls term settings for cs pads"
line.long 0xC0 "DDRSS_PHY_1328,"
hexmask.long.tbyte 0xC0 0.--17. 1. "PHY_PAD_ODT_TERM,Controls term settings for odt pads"
line.long 0xC4 "DDRSS_PHY_1329,"
hexmask.long.word 0xC4 16.--28. 1. "PHY_ADRCTL_LP3_RX_CAL,PHY CKE/RESET_N RX calibration controls"
hexmask.long.word 0xC4 0.--9. 1. "PHY_ADRCTL_RX_CAL,PHY address/control RX calibration controls"
line.long 0xC8 "DDRSS_PHY_1330,"
bitfld.long 0xC8 24. "PHY_CAL_START_0,Manual start for the pad calibration state machine for block 0" "0,1"
bitfld.long 0xC8 16. "PHY_CAL_CLEAR_0,Clear the pad calibration state machine and results for block 0" "0,1"
newline
hexmask.long.word 0xC8 0.--12. 1. "PHY_CAL_MODE_0,Pad calibration mode bits for block 0"
line.long 0xCC "DDRSS_PHY_1331,"
line.long 0xD0 "DDRSS_PHY_1332,"
bitfld.long 0xD0 8.--10. "PHY_LP4_BOOT_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for LPDDR4 boot frequency for block 0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xD0 0.--7. 1. "PHY_CAL_SAMPLE_WAIT_0,Pad calibration state machine wait count in pad clock cycles for block 0"
line.long 0xD4 "DDRSS_PHY_1333,"
hexmask.long.tbyte 0xD4 0.--23. 1. "PHY_CAL_RESULT_OBS_0,Pad calibration results observation values for block 0"
line.long 0xD8 "DDRSS_PHY_1334,"
hexmask.long.tbyte 0xD8 0.--23. 1. "PHY_CAL_RESULT2_OBS_0,Pad calibration results (CKE/RESET_N) observation values for block 0"
line.long 0xDC "DDRSS_PHY_1335,"
hexmask.long.tbyte 0xDC 0.--23. 1. "PHY_CAL_RESULT4_OBS_0,Pad calibration pass1 shadow results observation values for block 0"
line.long 0xE0 "DDRSS_PHY_1336,"
hexmask.long.tbyte 0xE0 0.--23. 1. "PHY_CAL_RESULT5_OBS_0,Pad calibration pass2 shadow results observation values for block 0"
line.long 0xE4 "DDRSS_PHY_1337,"
hexmask.long.tbyte 0xE4 0.--23. 1. "PHY_CAL_RESULT6_OBS_0,Pad calibration internal results observation delta values for block 0"
line.long 0xE8 "DDRSS_PHY_1338,"
hexmask.long.byte 0xE8 24.--30. 1. "PHY_CAL_CPTR_CNT_0,defines sample capture number in pad calibration process"
hexmask.long.tbyte 0xE8 0.--23. 1. "PHY_CAL_RESULT7_OBS_0,Pad calibration internal results observation delta values for block 0"
line.long 0xEC "DDRSS_PHY_1339,"
bitfld.long 0xEC 24. "PHY_CAL_DBG_CFG_0,defines debug configuration in pad calibration process" "0,1"
hexmask.long.byte 0xEC 16.--23. 1. "PHY_CAL_RCV_FINE_ADJ_0,defines adjustment for RCV code in pad calibration process"
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hexmask.long.byte 0xEC 8.--15. 1. "PHY_CAL_PD_FINE_ADJ_0,defines adjustment for PD code in pad calibration process"
hexmask.long.byte 0xEC 0.--7. 1. "PHY_CAL_PU_FINE_ADJ_0,defines adjustment for PU code in pad calibration process"
line.long 0xF0 "DDRSS_PHY_1340,"
bitfld.long 0xF0 0. "SC_PHY_PAD_DBG_CONT_0,Allows the pad calibration state machine to advance (when in debug mode) for slice 0" "0,1"
line.long 0xF4 "DDRSS_PHY_1341,"
line.long 0xF8 "DDRSS_PHY_1342,"
hexmask.long.tbyte 0xF8 8.--27. 1. "PHY_CAL_SLOPE_ADJ_0,defines slope configure in pad calibration process"
hexmask.long.byte 0xF8 0.--6. 1. "PHY_ADRCTL_PVT_MAP_0,defines slope configure in pad calibration process"
line.long 0xFC "DDRSS_PHY_1343,"
hexmask.long.tbyte 0xFC 0.--19. 1. "PHY_CAL_SLOPE_ADJ_PASS2_0,defines slope configure for pass2 in pad calibration process"
line.long 0x100 "DDRSS_PHY_1344,"
hexmask.long 0x100 0.--24. 1. "PHY_CAL_TWO_PASS_CFG_0,defines cal_en configure in pad calibration process"
line.long 0x104 "DDRSS_PHY_1345,"
bitfld.long 0x104 24.--29. "PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0,Pad calibration pass1 pu results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.tbyte 0x104 0.--22. 1. "PHY_CAL_SW_CAL_CFG_0,defines firmware based pad calibration process"
line.long 0x108 "DDRSS_PHY_1346,"
bitfld.long 0x108 24.--29. "PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0,Pad calibration pass2 pd results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x108 16.--21. "PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0,Pad calibration pass2 pu results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x108 8.--12. "PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0,Pad calibration pass1 rx results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x108 0.--5. "PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0,Pad calibration pass1 pd results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10C "DDRSS_PHY_1347,"
bitfld.long 0x10C 24.--28. "PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0,Pad calibration pass1 rx results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10C 16.--21. "PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0,Pad calibration pass1 pd results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10C 8.--13. "PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0,Pad calibration pass1 pu results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10C 0.--4. "PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0,Pad calibration pass2 rx results won't update if out of max delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x110 "DDRSS_PHY_1348,"
bitfld.long 0x110 16.--20. "PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0,Pad calibration pass2 rx results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x110 8.--13. "PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0,Pad calibration pass2 pd results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x110 0.--5. "PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0,Pad calibration pass2 pu results won't update if out of min delta range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x114 "DDRSS_PHY_1349,"
hexmask.long.word 0x114 16.--26. 1. "PHY_PARITY_ERROR_REGIF_AC,Inject parity error to register interface signals for ac slice"
hexmask.long.word 0x114 0.--15. 1. "PHY_PAD_ATB_CTRL,Pad ATB control settings"
line.long 0x118 "DDRSS_PHY_1350,"
bitfld.long 0x118 24.--25. "PHY_AC_LPBK_ENABLE,Loopback enable for the address/control slices" "0,1,2,3"
bitfld.long 0x118 16. "PHY_AC_LPBK_OBS_SELECT,Select value to map an individual loopback address/control slice observation register to the global observation register" "0,1"
newline
bitfld.long 0x118 8. "PHY_AC_LPBK_ERR_CLEAR,Address/control loopback error clear" "0,1"
bitfld.long 0x118 0. "PHY_ADRCTL_MANUAL_UPDATE,Address/control manual update of slave delay lines" "0,1"
line.long 0x11C "DDRSS_PHY_1351,"
bitfld.long 0x11C 24.--27. "PHY_AC_PRBS_PATTERN_MASK,PRBS7 mask signal for address/control slice" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x11C 16.--22. 1. "PHY_AC_PRBS_PATTERN_START,PRBS7 start pattern for address/control slice"
newline
hexmask.long.word 0x11C 0.--8. 1. "PHY_AC_LPBK_CONTROL,Address/control slice loopback control setting"
line.long 0x120 "DDRSS_PHY_1352,"
line.long 0x124 "DDRSS_PHY_1353,"
bitfld.long 0x124 16.--21. "PHY_AC_CLK_LPBK_CONTROL,Mem clk block loopback control setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x124 8. "PHY_AC_CLK_LPBK_ENABLE,Loopback enable for mem clk blocks" "0,1"
newline
bitfld.long 0x124 0. "PHY_AC_CLK_LPBK_OBS_SELECT,Select value to map an individual loopback mem clk block observation register to the global observation register" "0,1"
line.long 0x128 "DDRSS_PHY_1354,"
bitfld.long 0x128 24. "PHY_TOP_PWR_RDC_DISABLE,top param power reduction disable" "0,1"
bitfld.long 0x128 16. "PHY_AC_PWR_RDC_DISABLE,ac slice power reduction disable" "0,1"
newline
hexmask.long.word 0x128 0.--15. 1. "PHY_AC_CLK_LPBK_RESULT_OBS,Observation register for loopback mem clk blocks"
line.long 0x12C "DDRSS_PHY_1355,"
bitfld.long 0x12C 0. "PHY_AC_SLV_DLY_CTRL_GATE_DISABLE,ac slice slv_dly_control block power reduction disable" "0,1"
line.long 0x130 "DDRSS_PHY_1356,"
line.long 0x134 "DDRSS_PHY_1357,"
bitfld.long 0x134 24.--25. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_0,Select adrctl_mstr_dly_enc for the address/control slice 0" "0,1,2,3"
bitfld.long 0x134 16.--20. "PHY_CALVL_DEVICE_MAP,Define which device's DQ feedback data bits should be used during CA training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x134 8. "PHY_LPDDR4_CONNECT,PHY is connected to LPDDR4 devices" "0,1"
hexmask.long.byte 0x134 0.--7. 1. "PHY_DATA_BYTE_ORDER_SEL_HIGH,Used to define the data slice's byte swap for CA bits"
line.long 0x138 "DDRSS_PHY_1358,"
bitfld.long 0x138 0.--1. "PHY_ADRCTL_MSTR_DLY_ENC_SEL_1,Select adrctl_mstr_dly_enc for the address/control slice 1" "0,1,2,3"
line.long 0x13C "DDRSS_PHY_1359,"
line.long 0x140 "DDRSS_PHY_1360,"
hexmask.long 0x140 0.--25. 1. "PHY_DDL_AC_MODE,PHY Address/Control DDL BIST mode"
line.long 0x144 "DDRSS_PHY_1361,"
bitfld.long 0x144 24.--26. "PHY_ERR_MASK_EN,PHY ERROR information report mask enable" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x144 16.--23. 1. "PHY_DDL_TRACK_UPD_THRESHOLD_AC,Specify threshold value for PHY init update tracking for AC slice"
newline
bitfld.long 0x144 8.--10. "PHY_INIT_UPDATE_CONFIG,PHY init update function configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x144 0.--5. "PHY_DDL_AC_MASK,PHY Address/Control DDL BIST mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x148 "DDRSS_PHY_1362,"
bitfld.long 0x148 0.--2. "PHY_ERR_STATUS,PHY ERROR information" "0,1,2,3,4,5,6,7"
line.long 0x14C "DDRSS_PHY_1363,"
line.long 0x150 "DDRSS_PHY_1364,"
line.long 0x154 "DDRSS_PHY_1365,"
line.long 0x158 "DDRSS_PHY_1366,"
line.long 0x15C "DDRSS_PHY_1367,"
rbitfld.long 0x15C 24.--27. "PHY_DS_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for data slice" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x15C 8.--17. 1. "PHY_AC_INIT_COMPLETE_OBS,Observation register for dfi_init_complete for adr and ac slice"
newline
bitfld.long 0x15C 0.--1. "PHY_DLL_RST_EN,PHY DDL reset software interface enable" "0,1,2,3"
line.long 0x160 "DDRSS_PHY_1368,"
bitfld.long 0x160 24.--26. "PHY_GRP_SHIFT_OBS_SELECT,Select value to map an individual address/control group slice automatic cycle/half_cycle shift settings to the observation register" "0,1,2,3,4,5,6,7"
bitfld.long 0x160 16.--19. "PHY_GRP_SLV_DLY_ENC_OBS_SELECT,Select value to map an individual address/control group slice slave delay to the encoded value observation register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x160 8. "PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE,Memory clock bit slice DCC block power reduction disable" "0,1"
bitfld.long 0x160 0. "PHY_UPDATE_MASK,Control to disable the generation of dfi_phyupd_req and use of dfi_ctrlupd_req" "0,1"
line.long 0x164 "DDRSS_PHY_1369,"
bitfld.long 0x164 16.--18. "PHY_GRP_SHIFT_OBS,Observation register for the address/control group automatic half cycle and cycle shift values" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x164 0.--10. 1. "PHY_GRP_SLV_DLY_ENC_OBS,Observation register for all address/control group slice slave delay encoded values"
line.long 0x168 "DDRSS_PHY_1370,"
bitfld.long 0x168 24.--26. "PHY_PLL_LOCK_DEASSERT_MASK,PLL Lock de-assert Mask" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x168 8.--18. 1. "PHY_PARITY_ERROR_REGIF_PS,Injects parity error to register interface signals in param_split"
newline
bitfld.long 0x168 0. "PHY_PARITY_ERROR_INJECTION_ENABLE,Enable parity error injection" "0,1"
line.long 0x16C "DDRSS_PHY_1371,"
hexmask.long.byte 0x16C 16.--22. 1. "SC_PHY_PARITY_ERROR_INFO_WOCLR,Parity Error Info"
hexmask.long.byte 0x16C 8.--14. 1. "PHY_PARITY_ERROR_INFO_MASK,Parity Error Info Mask"
newline
hexmask.long.byte 0x16C 0.--6. 1. "PHY_PARITY_ERROR_INFO,Parity Error Info"
line.long 0x170 "DDRSS_PHY_1372,"
hexmask.long.word 0x170 16.--29. 1. "PHY_TIMEOUT_ERROR_INFO_MASK,Timeout Error Info Mask"
hexmask.long.word 0x170 0.--13. 1. "PHY_TIMEOUT_ERROR_INFO,Timeout Error Info"
line.long 0x174 "DDRSS_PHY_1373,"
bitfld.long 0x174 24.--29. "PHY_PLL_FREQUENCY_ERROR_MASK,PLL Frequency Error Info Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x174 16.--19. "PHY_PLL_FREQUENCY_ERROR,PLL Frequency Error Info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x174 0.--13. 1. "SC_PHY_TIMEOUT_ERROR_INFO_WOCLR,Timeout Error Info"
line.long 0x178 "DDRSS_PHY_1374,"
hexmask.long.word 0x178 8.--19. 1. "PHY_PLL_DSKEWCALOUT_MIN,PLL DSKEWCALOUT threshold min value"
bitfld.long 0x178 0.--5. "SC_PHY_PLL_FREQUENCY_ERROR_WOCLR,PLL_Frequency Error Info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x17C "DDRSS_PHY_1375,"
bitfld.long 0x17C 24.--25. "PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK,PLL DSKEWCALOUT threshold Error Info Mask" "0,1,2,3"
rbitfld.long 0x17C 16.--17. "PHY_PLL_DSKEWCALOUT_ERROR_INFO,PLL DSKEWCALOUT threshold Error Info" "0,1,2,3"
newline
hexmask.long.word 0x17C 0.--11. 1. "PHY_PLL_DSKEWCALOUT_MAX,PLL DSKEWCALOUT threshold max value"
line.long 0x180 "DDRSS_PHY_1376,"
hexmask.long.word 0x180 8.--16. 1. "PHY_TOP_FSM_ERROR_INFO,Top level FSM Error Info"
bitfld.long 0x180 0.--1. "SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR,PLL DSKEWCALOUT threshold Error Info" "0,1,2,3"
line.long 0x184 "DDRSS_PHY_1377,"
hexmask.long.word 0x184 16.--24. 1. "SC_PHY_TOP_FSM_ERROR_INFO_WOCLR,Top level FSM Error Info"
hexmask.long.word 0x184 0.--8. 1. "PHY_TOP_FSM_ERROR_INFO_MASK,Top level FSM Error Info Mask"
line.long 0x188 "DDRSS_PHY_1378,"
hexmask.long.word 0x188 16.--25. 1. "PHY_FSM_TRANSIENT_ERROR_INFO_MASK,Accumulated Top level FSM Error Info Mask"
hexmask.long.word 0x188 0.--9. 1. "PHY_FSM_TRANSIENT_ERROR_INFO,Accumulated Top level FSM Error Info"
line.long 0x18C "DDRSS_PHY_1379,"
bitfld.long 0x18C 24.--25. "PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK,Training/Calibration Error Info Mask for TOP" "0,1,2,3"
rbitfld.long 0x18C 16.--17. "PHY_TOP_TRAIN_CALIB_ERROR_INFO,Training/Calibration Error Info for TOP" "0,1,2,3"
newline
hexmask.long.word 0x18C 0.--9. 1. "SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR,Accumulated Top level FSM Error Info"
line.long 0x190 "DDRSS_PHY_1380,"
hexmask.long.byte 0x190 24.--30. 1. "SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR,Training/Calibration Error Info"
hexmask.long.byte 0x190 16.--22. 1. "PHY_TRAIN_CALIB_ERROR_INFO_MASK,Training/Calibration Error Info Mask"
newline
hexmask.long.byte 0x190 8.--14. 1. "PHY_TRAIN_CALIB_ERROR_INFO,Training/Calibration Error Info"
bitfld.long 0x190 0.--1. "SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR,Training/Calibration Error Info for TOP" "0,1,2,3"
line.long 0x194 "DDRSS_PHY_1381,"
bitfld.long 0x194 8.--13. "PHY_GLOBAL_ERROR_INFO_MASK,Global Error Info Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x194 0.--5. "PHY_GLOBAL_ERROR_INFO,Global Error Info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x198 "DDRSS_PHY_1382,"
hexmask.long.tbyte 0x198 0.--19. 1. "PHY_TRAINING_TIMEOUT_VALUE,Training timeout value"
line.long 0x19C "DDRSS_PHY_1383,"
hexmask.long.tbyte 0x19C 0.--19. 1. "PHY_INIT_TIMEOUT_VALUE,Init or DFS timeout value"
line.long 0x1A0 "DDRSS_PHY_1384,"
hexmask.long.word 0x1A0 0.--15. 1. "PHY_LP_TIMEOUT_VALUE,DFI LP timeout value"
line.long 0x1A4 "DDRSS_PHY_1385,"
line.long 0x1A8 "DDRSS_PHY_1386,"
bitfld.long 0x1A8 24.--28. "PHY_PLL_LOCK_0_MIN_VALUE,PLL min timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.tbyte 0x1A8 0.--19. 1. "PHY_PHYMSTR_TIMEOUT_VALUE,DFI PHYMSTR timeout value"
line.long 0x1AC "DDRSS_PHY_1387,"
bitfld.long 0x1AC 24.--27. "PHY_PLL_FREQUENCY_DELTA,Acceptable PLL frequency delta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1AC 16.--23. 1. "PHY_RDDATA_VALID_TIMEOUT_VALUE,RDDATA VALID timeout value"
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hexmask.long.word 0x1AC 0.--15. 1. "PHY_PLL_LOCK_TIMEOUT_VALUE,PLL max timeout value"
line.long 0x1B0 "DDRSS_PHY_1388,"
hexmask.long.word 0x1B0 16.--29. 1. "PHY_ADRCTL_FSM_ERROR_INFO_0,ADRCTL slice level FSM Error Info"
hexmask.long.word 0x1B0 0.--15. 1. "PHY_PLL_FREQUENCY_COMPARE_INTERVAL,PLL Frequency compare interval"
line.long 0x1B4 "DDRSS_PHY_1389,"
hexmask.long.word 0x1B4 16.--29. 1. "SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0,ADRCTL Slice level FSM Error Info"
hexmask.long.word 0x1B4 0.--13. 1. "PHY_ADRCTL_FSM_ERROR_INFO_MASK_0,ADRCTL Slice level FSM Error Info Mask"
line.long 0x1B8 "DDRSS_PHY_1390,"
hexmask.long.word 0x1B8 16.--29. 1. "PHY_ADRCTL_FSM_ERROR_INFO_MASK_1,ADRCTL Slice level FSM Error Info Mask"
hexmask.long.word 0x1B8 0.--13. 1. "PHY_ADRCTL_FSM_ERROR_INFO_1,ADRCTL slice level FSM Error Info"
line.long 0x1BC "DDRSS_PHY_1391,"
hexmask.long.word 0x1BC 16.--29. 1. "PHY_MEMCLK_FSM_ERROR_INFO_0,MEMCLK slice level FSM Error Info"
hexmask.long.word 0x1BC 0.--13. 1. "SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1,ADRCTL Slice level FSM Error Info"
line.long 0x1C0 "DDRSS_PHY_1392,"
hexmask.long.word 0x1C0 16.--29. 1. "SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0,MEMCLK Slice level FSM Error Info"
hexmask.long.word 0x1C0 0.--13. 1. "PHY_MEMCLK_FSM_ERROR_INFO_MASK_0,MEMCLK Slice level FSM Error Info Mask"
line.long 0x1C4 "DDRSS_PHY_1393,"
hexmask.long.tbyte 0x1C4 0.--17. 1. "PHY_PAD_CAL_IO_CFG_0,Pad calibration Controls PCLK/PARK pin and vref switch"
line.long 0x1C8 "DDRSS_PHY_1394,"
hexmask.long.word 0x1C8 0.--13. 1. "PHY_PAD_ACS_IO_CFG,Controls PCLK/PARK pin for acs pad"
line.long 0x1CC "DDRSS_PHY_1395,"
bitfld.long 0x1CC 0. "PHY_PLL_BYPASS,PHY clock PLL bypass select" "0,1"
line.long 0x1D0 "DDRSS_PHY_1396,"
bitfld.long 0x1D0 16. "PHY_LOW_FREQ_SEL,Enables the PHY to enter/exit the PLL domain from the negative clock edge" "0,1"
hexmask.long.word 0x1D0 0.--12. 1. "PHY_PLL_CTRL,PHY clock PLL controls"
line.long 0x1D4 "DDRSS_PHY_1397,"
bitfld.long 0x1D4 24.--27. "PHY_CSLVL_DLY_STEP,Sets the delay step size plus 1 during CS training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1D4 16.--19. "PHY_CSLVL_CAPTURE_CNT,Defines the number of samples to take at each GRP slave delay setting during CS training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x1D4 0.--11. 1. "PHY_PAD_VREF_CTRL_AC,Pad VREF control settings for the address/control"
line.long 0x1D8 "DDRSS_PHY_1398,"
bitfld.long 0x1D8 24. "PHY_LVL_MEAS_DLY_STEP_ENABLE,Enables the phy_adr_meas_dly_step_value to be used instead of the phy_cslvl_dly_step parameter" "0,1"
bitfld.long 0x1D8 16. "PHY_SW_CSLVL_DVW_MIN_EN,Enables the software override data valid window size during CS training" "0,1"
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hexmask.long.word 0x1D8 0.--8. 1. "PHY_SW_CSLVL_DVW_MIN,Sets the software override data valid window size during CS training"
line.long 0x1DC "DDRSS_PHY_1399,"
hexmask.long.word 0x1DC 16.--26. 1. "PHY_GRP1_SLAVE_DELAY_0,Address slice slave delay setting for address slice 1"
hexmask.long.word 0x1DC 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_0,Address slice slave delay setting for address slice 0"
line.long 0x1E0 "DDRSS_PHY_1400,"
hexmask.long.word 0x1E0 16.--26. 1. "PHY_GRP3_SLAVE_DELAY_0,Address slice slave delay setting for address slice 3"
hexmask.long.word 0x1E0 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_0,Address slice slave delay setting for address slice 2"
line.long 0x1E4 "DDRSS_PHY_1401,"
hexmask.long.word 0x1E4 0.--10. 1. "PHY_GRP0_SLAVE_DELAY_1,Address slice slave delay setting for address slice 0"
line.long 0x1E8 "DDRSS_PHY_1402,"
hexmask.long.word 0x1E8 0.--10. 1. "PHY_GRP1_SLAVE_DELAY_1,Address slice slave delay setting for address slice 1"
line.long 0x1EC "DDRSS_PHY_1403,"
hexmask.long.word 0x1EC 0.--10. 1. "PHY_GRP2_SLAVE_DELAY_1,Address slice slave delay setting for address slice 2"
line.long 0x1F0 "DDRSS_PHY_1404,"
hexmask.long.word 0x1F0 0.--10. 1. "PHY_GRP3_SLAVE_DELAY_1,Address slice slave delay setting for address slice 3"
line.long 0x1F4 "DDRSS_PHY_1405,"
bitfld.long 0x1F4 0.--2. "PHY_CLK_DC_CAL_CLK_SEL,Determines DCC CAL clock" "0,1,2,3,4,5,6,7"
line.long 0x1F8 "DDRSS_PHY_1406,"
hexmask.long 0x1F8 0.--29. 1. "PHY_PAD_FDBK_DRIVE,Controls drive settings for gate feedback pads"
line.long 0x1FC "DDRSS_PHY_1407,"
hexmask.long.tbyte 0x1FC 0.--17. 1. "PHY_PAD_FDBK_DRIVE2,Controls drive settings (enslice/boost) for gate feedback pads"
line.long 0x200 "DDRSS_PHY_1408,"
hexmask.long 0x200 0.--30. 1. "PHY_PAD_DATA_DRIVE,Controls drive settings for data pads"
line.long 0x204 "DDRSS_PHY_1409,"
line.long 0x208 "DDRSS_PHY_1410,"
hexmask.long 0x208 0.--29. 1. "PHY_PAD_ADDR_DRIVE,Controls drive settings for the address/control pads"
line.long 0x20C "DDRSS_PHY_1411,"
hexmask.long 0x20C 0.--26. 1. "PHY_PAD_ADDR_DRIVE2,Controls drive settings for the address/control pads"
line.long 0x210 "DDRSS_PHY_1412,"
line.long 0x214 "DDRSS_PHY_1413,"
hexmask.long.tbyte 0x214 0.--17. 1. "PHY_PAD_CLK_DRIVE2,Controls drive settings for clock pads"
line.long 0x218 "DDRSS_PHY_1414,"
hexmask.long 0x218 0.--29. 1. "PHY_PAD_CKE_DRIVE,Controls drive settings for cke pads"
line.long 0x21C "DDRSS_PHY_1415,"
hexmask.long 0x21C 0.--26. 1. "PHY_PAD_CKE_DRIVE2,Controls drive settings for cke pads"
line.long 0x220 "DDRSS_PHY_1416,"
hexmask.long 0x220 0.--29. 1. "PHY_PAD_RST_DRIVE,Controls drive settings for reset_n pads"
line.long 0x224 "DDRSS_PHY_1417,"
hexmask.long 0x224 0.--26. 1. "PHY_PAD_RST_DRIVE2,Controls drive settings for reset_n pads"
line.long 0x228 "DDRSS_PHY_1418,"
hexmask.long 0x228 0.--29. 1. "PHY_PAD_CS_DRIVE,Controls drive settings for cs pads"
line.long 0x22C "DDRSS_PHY_1419,"
hexmask.long 0x22C 0.--26. 1. "PHY_PAD_CS_DRIVE2,Controls drive settings for cs pads"
line.long 0x230 "DDRSS_PHY_1420,"
hexmask.long 0x230 0.--29. 1. "PHY_PAD_ODT_DRIVE,Controls drive settings for odt pads"
line.long 0x234 "DDRSS_PHY_1421,"
hexmask.long 0x234 0.--26. 1. "PHY_PAD_ODT_DRIVE2,Controls drive settings for odt pads"
line.long 0x238 "DDRSS_PHY_1422,"
hexmask.long.byte 0x238 24.--30. 1. "PHY_CAL_SETTLING_PRD_0,Number of clock cycles to extend dfi_phyupd_req after the ack is received for settling of final values"
hexmask.long.word 0x238 8.--23. 1. "PHY_CAL_VREF_SWITCH_TIMER_0,The settling time for a switch in VREF during IO pad calibration"
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bitfld.long 0x238 0.--2. "PHY_CAL_CLK_SELECT_0,Pad calibration pad clock frequency select setting for block 0" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "DDR_Subsystem"
tree "COMPUTE_CLUSTER0_SS_CFG"
base ad:0x2980000
rgroup.long 0x00++0x07
line.long 0x00 "DDRSS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MIN_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DDRSS_SS_CTL_REG,The Subsystem Control Register contains fields for control functions required for submodules in the subsystem"
bitfld.long 0x04 0. "PHY_PLL_BYPASS,PHY De-Skew PLL bypass" "0,1"
group.long 0x20++0x1F
line.long 0x00 "DDRSS_V2A_CTL_REG,The MSMC2DDR Bridge Control register contains control functions required for the MSMC2DDR bridge submodule"
bitfld.long 0x00 17.--21. "WR_LO_BLK_THR,Write data threshold in 64 byte quantas" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 12.--16. "CRIT_THRESH,Critical threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "SDRAM_3QT,Setting this field to a 1 will modify SDRAM Index to be 3/4 its programmed value to support 3 6 12 and 24 GB sizes" "0,1"
bitfld.long 0x00 5.--9. "SDRAM_IDX,SDRAM Index = log2(connected SDRAM size) - 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "REGION_IDX,Region Index = log2(CBA region size) - 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRSS_V2A_R1_MAT_REG,The Range 1 Match Register allows a single master to a range of masters to change their priority mapping"
bitfld.long 0x04 31. "RANGE1_RANGEEN_A,The range1_rangeen_a enables the RouteID AND'd with range1_mask_a to match the range1_routeid_a" "0,1"
bitfld.long 0x04 28.--30. "RANGE1_MASK_A,The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--27. 1. "RANGE1_ROUTEID_A,The range1_routeid_a is the value that is compared to the RouteID arriving on the command interface"
bitfld.long 0x04 15. "RANGE1_RANGEEN_B,The range1_rangeen_b enables the RouteID AND'd with range1_mask_b to match the range1_routeid_b" "0,1"
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bitfld.long 0x04 12.--14. "RANGE1_MASK_B,The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--11. 1. "RANGE1_ROUTEID_B,The range1_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x08 "DDRSS_V2A_R2_MAT_REG,The Range 2 Match Register allows a single master to a range of masters to change their priority mapping"
bitfld.long 0x08 31. "RANGE2_RANGEEN_A,The range2_rangeen_a enables the RouteID AND'd with range2_mask_a to match the range2_routeid_a" "0,1"
bitfld.long 0x08 28.--30. "RANGE2_MASK_A,The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x08 16.--27. 1. "RANGE2_ROUTEID_A,The range2_routeid_a is the value that is compared to the RouteID arriving on the command interface"
bitfld.long 0x08 15. "RANGE2_RANGEEN_B,The range2_rangeen_b enables the RouteID AND'd with range2_mask_b to match the range2_routeid_b" "0,1"
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bitfld.long 0x08 12.--14. "RANGE2_MASK_B,The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x08 0.--11. 1. "RANGE2_ROUTEID_B,The range2_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x0C "DDRSS_V2A_R3_MAT_REG,The Range 3 Match Register allows a single master to a range of masters to change their priority mapping"
bitfld.long 0x0C 31. "RANGE3_RANGEEN_A,The range3_rangeen_a enables the RouteID AND'd with range3_mask_a to match the range3_routeid_a" "0,1"
bitfld.long 0x0C 28.--30. "RANGE3_MASK_A,The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0C 16.--27. 1. "RANGE3_ROUTEID_A,The range3_routeid_a is the value that is compared to the RouteID arriving on the command interface"
bitfld.long 0x0C 15. "RANGE3_RANGEEN_B,The range3_rangeen_b enables the RouteID AND'd with range3_mask_b to match the range3_routeid_b" "0,1"
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bitfld.long 0x0C 12.--14. "RANGE3_MASK_B,The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0C 0.--11. 1. "RANGE3_ROUTEID_B,The range3_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x10 "DDRSS_V2A_LPT_DEF_PRI_MAP_REG,The LPT Default Priority Mapping Register is the default map for the inbound VBUSM.C priority on the Low Priority Thread to AXI priority"
bitfld.long 0x10 28.--30. "LPT_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "LPT_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 20.--22. "LPT_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "LPT_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 12.--14. "LPT_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "LPT_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "LPT_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "LPT_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7" "0,1,2,3,4,5,6,7"
line.long 0x14 "DDRSS_V2A_LPT_R1_PRI_MAP_REG,The LPT Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 1 occurs"
bitfld.long 0x14 28.--30. "LPT_RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 24.--26. "LPT_RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 20.--22. "LPT_RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 16.--18. "LPT_RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 12.--14. "LPT_RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 8.--10. "LPT_RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 4.--6. "LPT_RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 0.--2. "LPT_RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 1" "0,1,2,3,4,5,6,7"
line.long 0x18 "DDRSS_V2A_LPT_R2_PRI_MAP_REG,The LPT Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 2 occurs"
bitfld.long 0x18 28.--30. "LPT_RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 24.--26. "LPT_RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 20.--22. "LPT_RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 16.--18. "LPT_RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 12.--14. "LPT_RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 8.--10. "LPT_RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 4.--6. "LPT_RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 0.--2. "LPT_RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 2" "0,1,2,3,4,5,6,7"
line.long 0x1C "DDRSS_V2A_LPT_R3_PRI_MAP_REG,The LPT Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 3 occurs"
bitfld.long 0x1C 28.--30. "LPT_RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 24.--26. "LPT_RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 20.--22. "LPT_RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 16.--18. "LPT_RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 12.--14. "LPT_RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 8.--10. "LPT_RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "LPT_RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 0.--2. "LPT_RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 3" "0,1,2,3,4,5,6,7"
group.long 0x4C++0x0F
line.long 0x00 "DDRSS_V2A_HPT_DEF_PRI_MAP_REG,The HPT Default Priority Mapping Register is the default map for the inbound VBUSM.C priority on the High Priority Thread to the AXI priority"
bitfld.long 0x00 28.--30. "HPT_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "HPT_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "HPT_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "HPT_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--14. "HPT_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "HPT_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "HPT_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "HPT_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7" "0,1,2,3,4,5,6,7"
line.long 0x04 "DDRSS_V2A_HPT_R1_PRI_MAP_REG,The HPT Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 1 occurs"
bitfld.long 0x04 28.--30. "HPT_RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 24.--26. "HPT_RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 20.--22. "HPT_RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--18. "HPT_RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 12.--14. "HPT_RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--10. "HPT_RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 4.--6. "HPT_RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. "HPT_RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 1" "0,1,2,3,4,5,6,7"
line.long 0x08 "DDRSS_V2A_HPT_R2_PRI_MAP_REG,The HPT Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 2 occurs"
bitfld.long 0x08 28.--30. "HPT_RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "HPT_RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20.--22. "HPT_RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "HPT_RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 12.--14. "HPT_RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--10. "HPT_RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 4.--6. "HPT_RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "HPT_RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 2" "0,1,2,3,4,5,6,7"
line.long 0x0C "DDRSS_V2A_HPT_R3_PRI_MAP_REG,The HPT Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 3 occurs"
bitfld.long 0x0C 28.--30. "HPT_RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 24.--26. "HPT_RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 20.--22. "HPT_RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 16.--18. "HPT_RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 12.--14. "HPT_RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8.--10. "HPT_RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4.--6. "HPT_RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--2. "HPT_RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 3" "0,1,2,3,4,5,6,7"
group.long 0x70++0x0B
line.long 0x00 "DDRSS_V2A_AERR_LOG1_REG,The Address Error Log 1 register displays the RouteID and lsb of the address for the first VBUSM.C command that was outside the programmed addressing range"
hexmask.long.word 0x00 16.--31. 1. "AERR_ADDR_LSB,Address"
hexmask.long.word 0x00 0.--11. 1. "AERR_ROUTE_ID,RouteID of the VBUSM.C write command"
line.long 0x04 "DDRSS_V2A_AERR_LOG2_REG,The Address Error Log 2 registers displays the msb of the address for the first VBUSM.C command that was outside the programmed addressing range"
line.long 0x08 "DDRSS_V2A_OERR_LOG_REG,The Opcode Error Log register displays the RouteID and opcode for the first VBUSM.C command that had an unsupported opcode"
bitfld.long 0x08 12.--17. "OERR_OP_CODE,Opcode of the VBUSM.C command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--11. 1. "OERR_ROUTE_ID,RouteID of the VBUSM.C command"
group.long 0x80++0x13
line.long 0x00 "DDRSS_V2A_1B_ERR_CNT_REG,MSMC2DDR Bridge 1-Bit EDC Error Count Register"
hexmask.long.word 0x00 0.--15. 1. "EDC_1B_ERR_CNT,"
line.long 0x04 "DDRSS_V2A_1B_ERR_LOG1_REG,The 1-Bit EDC Error Log 1 register displays the RouteID and error position of the first VBUSM.C write that incurred 1-bit EDC error"
hexmask.long.word 0x04 16.--24. 1. "ERR_POS_1B,Bit error position"
hexmask.long.word 0x04 0.--11. 1. "ROUTE_ID_1B,RouteID of the VBUSM.C write command"
line.long 0x08 "DDRSS_V2A_1B_ERR_LOG2_REG,The 1-Bit EDC Error Log 2 registers displays the address of the first VBUSM.C write that incurred 1-bit EDC error"
hexmask.long 0x08 0.--29. 1. "ADDR_MSB_1B,Address"
line.long 0x0C "DDRSS_V2A_2B_ERR_LOG1_REG,The 2-Bit EDC Error Log 1 register displays the RouteID of the first VBUSM.C write that incurred 2-bit EDC error"
hexmask.long.word 0x0C 0.--11. 1. "ROUTE_ID_2B,RouteID of the VBUSM.C write command"
line.long 0x10 "DDRSS_V2A_2B_ERR_LOG2_REG,The 2-Bit EDC Error Log 1 register displays the address of the first VBUSM.C write that incurred 2-bit EDC error"
hexmask.long 0x10 0.--29. 1. "ADR_MSB_2B,Address"
group.long 0x9C++0x17
line.long 0x00 "DDRSS_V2A_BUS_TO,MSMC2DDR Bridge Bus Timeout Register"
hexmask.long.tbyte 0x00 0.--23. 1. "BUS_TIMER,AXI bus timeout value"
line.long 0x04 "DDRSS_V2A_INT_RAW_REG,MSMC2DDR Bridge Interrupt Raw Status Register"
bitfld.long 0x04 5. "ECCM1BERR,Raw status of SDRAM ECC multi 1-bit errors in same SDRAM burst" "0,1"
bitfld.long 0x04 4. "ECC2BERR,Raw status of SDRAM ECC 2-bit error" "0,1"
bitfld.long 0x04 3. "ECC1BERR,Raw status of SDRAM ECC 1-bit error" "0,1"
bitfld.long 0x04 2. "TOERR,Raw status of MSMC2DDR bridge interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x04 1. "AERR,Raw status of MSMC2DDR bridge interrupt for VBUSM.C address outside the programmed range" "0,1"
bitfld.long 0x04 0. "OERR,Raw status of MSMC2DDR bridge interrupt for VBUSM.C unsupported opcode" "0,1"
line.long 0x08 "DDRSS_V2A_INT_STAT_REG,MSMC2DDR Bridge Interrupt Status Register"
bitfld.long 0x08 5. "ECCM1BERR,Enabled status of SDRAM ECC multi 1-bit errors in same SDRAM burst" "0,1"
bitfld.long 0x08 4. "ECC2BERR,Enabled status of SDRAM ECC 2-bit error" "0,1"
bitfld.long 0x08 3. "ECC1BERR,Enabled status of SDRAM ECC 1-bit error" "0,1"
bitfld.long 0x08 2. "TOERR,Enabled status of MSMC2DDR bridge interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x08 1. "AERR,Enabled status of MSMC2DDR bridge interrupt for VBUSM.C address outside the programmed range" "0,1"
bitfld.long 0x08 0. "OERR,Enabled status of MSMC2DDR bridge interrupt for VBUSM.C unsupported opcode" "0,1"
line.long 0x0C "DDRSS_V2A_INT_SET_REG,MSMC2DDR Bridge Interrupt Enable Set Register"
bitfld.long 0x0C 5. "ECCM1BERR_EN,Enable set for SDRAM ECC multi" "0,1"
bitfld.long 0x0C 4. "ECC2BERR_EN,Enable set for SDRAM ECC" "0,1"
bitfld.long 0x0C 3. "ECC1BERR_EN,Enable set for SDRAM ECC" "0,1"
bitfld.long 0x0C 2. "TOERR_EN,Enable set for MSMC2DDR bridge interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x0C 1. "AERR_EN,Enable set for MSMC2DDR bridge interrupt for VBUSM.C address outside the programmed range" "0,1"
bitfld.long 0x0C 0. "OERR_EN,Enable set for MSMC2DDR bridge interrupt for VBUSM.C unsupported opcode" "0,1"
line.long 0x10 "DDRSS_V2A_INT_CLR_REG,MSMC2DDR Bridge Interrupt Enable Clear Register"
bitfld.long 0x10 5. "ECCM1BERR_EN,Enable clear for SDRAM ECC multi" "0,1"
bitfld.long 0x10 4. "ECC2BERR_EN,Enable clear for SDRAM ECC" "0,1"
bitfld.long 0x10 3. "ECC1BERR_EN,Enable clear for SDRAM ECC" "0,1"
bitfld.long 0x10 2. "TOERR_EN,Enable clear for MSMC2DDR bridge interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x10 1. "AERR_EN,Enable clear for MSMC2DDR bridge interrupt for VBUSM.C address outside the programmed range" "0,1"
bitfld.long 0x10 0. "OERR_EN,Enable clear for MSMC2DDR bridge interrupt for VBUSM.C unsupported opcode" "0,1"
line.long 0x14 "DDRSS_V2A_EOI_REG,MSMC2DDR Bridge End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x14 0.--1. "EOI,Software End Of Interrupt (EOI) control" "0,1,2,3"
group.long 0x100++0x13
line.long 0x00 "DDRSS_PERF_CNT_SEL_REG,The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register"
bitfld.long 0x00 24.--29. "CNT4_SEL,Statistic select for Performance Counter 4 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "CNT3_SEL,Statistic select for Performance Counter 3 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "CNT2_SEL,Statistic select for Performance Counter 2 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "CNT1_SEL,Statistic select for Performance Counter 1 register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DDRSS_PERF_CNT1_REG,Performance Counter 1 Register"
line.long 0x08 "DDRSS_PERF_CNT2_REG,Performance Counter 2 Register"
line.long 0x0C "DDRSS_PERF_CNT3_REG,Performance Counter 3 Register"
line.long 0x10 "DDRSS_PERF_CNT4_REG,Performance Counter 4 Register"
group.long 0x120++0x0B
line.long 0x00 "DDRSS_ECC_CTRL_REG,ECC Control Register"
bitfld.long 0x00 8.--12. "COR_ECC_THRESH,Threshold for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. "WR_ALLOC,When set to 1 an unassigned ECC cache-line will be allocated for a write with routeID that do not match any of the mapped routeID's" "0,1"
bitfld.long 0x00 2. "ECC_CK,Set 1 to enable ECC verification for read accesses when ecc_en=1" "0,1"
bitfld.long 0x00 1. "RMW_EN,Read modify write enable" "0,1"
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bitfld.long 0x00 0. "ECC_EN,DRAM ECC enable" "0,1"
line.long 0x04 "DDRSS_ECC_RID_INDX_REG,ECC Cache RouteID Index Register"
hexmask.long.byte 0x04 0.--6. 1. "ECCRID_ADR,This index specifies the ECC cache entry number that the eccrid_val is mapped to"
line.long 0x08 "DDRSS_ECC_RID_VAL_REG,ECC Cache RouteID Write Value Register"
bitfld.long 0x08 15. "ECCRID_VAL_VLD,A 1 in this field indicates that value in eccrid_val is valid" "0,1"
hexmask.long.word 0x08 0.--11. 1. "ECCRID_VAL,RouteID value written or read"
group.long 0x130++0x17
line.long 0x00 "DDRSS_ECC_R0_STR_ADDR_REG,ECC Range 0 Start Address Register"
hexmask.long.tbyte 0x00 0.--18. 1. "ECC_STR_ADR_0,Start caddress"
line.long 0x04 "DDRSS_ECC_R0_END_ADDR_REG,ECC Range 0 End Address Register"
hexmask.long.tbyte 0x04 0.--18. 1. "ECC_END_ADR_0,End caddress"
line.long 0x08 "DDRSS_ECC_R1_STR_ADDR_REG,ECC Range 1 Start Address Register"
hexmask.long.tbyte 0x08 0.--18. 1. "ECC_STR_ADR_1,Start caddress"
line.long 0x0C "DDRSS_ECC_R1_END_ADDR_REG,ECC Range 1 End Address Register"
hexmask.long.tbyte 0x0C 0.--18. 1. "ECC_END_ADR_1,End caddress"
line.long 0x10 "DDRSS_ECC_R2_STR_ADDR_REG,ECC Range 2 Start Address Register"
hexmask.long.tbyte 0x10 0.--18. 1. "ECC_STR_ADR_2,Start caddress"
line.long 0x14 "DDRSS_ECC_R2_END_ADDR_REG,ECC Range 2 End Address Register"
hexmask.long.tbyte 0x14 0.--18. 1. "ECC_END_ADR_2,End caddress"
group.long 0x150++0x17
line.long 0x00 "DDRSS_ECC_1B_ERR_CNT_REG,ECC 1-Bit Error Count Register"
hexmask.long.word 0x00 0.--15. 1. "ECC_1B_ERR_CNT,"
line.long 0x04 "DDRSS_ECC_1B_ERR_THRSH_REG,ECC 1-Bit Error Threshold Register"
hexmask.long.word 0x04 0.--15. 1. "ECC_1B_ERR_THRSH,ECC"
line.long 0x08 "DDRSS_ECC_1B_ERR_ADR_LOG_REG,ECC 1-Bit Error Address Log Register"
hexmask.long 0x08 0.--28. 1. "ECC_1B_ERR_ADR,ECC"
line.long 0x0C "DDRSS_ECC_1B_ERR_MSK_LOG_REG,ECC 1-Bit Error Mask Log Register"
hexmask.long.word 0x0C 0.--15. 1. "ECC_1B_ERR_MSK,ECC"
line.long 0x10 "DDRSS_ECC_2B_ERR_ADR_LOG_REG,ECC 2-Bit Error Address Log Register"
hexmask.long 0x10 0.--28. 1. "ECC_2B_ERR_ADR,ECC"
line.long 0x14 "DDRSS_ECC_2B_ERR_MSK_LOG_REG,ECC 2-Bit Error Mask Log Register"
hexmask.long.word 0x14 0.--15. 1. "ECC_2B_ERR_MSK,ECC"
group.long 0x180++0x03
line.long 0x00 "DDRSS_PHY_BIST_CTRL_REG,PHY BIST Control Register"
hexmask.long.word 0x00 0.--15. 1. "BIST_TSEL_SELECT,This field controls the bist_tsel_select input of the PHY"
tree.end
tree.end
tree "DDRSS0_ECC_AGGR_CFG"
tree "COMPUTE_CLUSTER0_ECC_AGGR_CFG"
base ad:0x4D200B0800
rgroup.long 0x00++0x03
line.long 0x00 "DDRSS_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "DDRSS_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "DDRSS_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "DDRSS_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "DDRSS_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DDRSS_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1"
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bitfld.long 0x04 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x04 4. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1"
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bitfld.long 0x04 3. "DST_M2P_DST_BUSECC_PEND,Interrupt Pending Status for dst_m2p_dst_busecc_pend" "0,1"
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bitfld.long 0x04 2. "DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for dst_m2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1"
newline
bitfld.long 0x04 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "DDRSS_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x00 4. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DST_M2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1"
newline
bitfld.long 0x00 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DDRSS_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x00 4. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DST_M2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1"
newline
bitfld.long 0x00 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DDRSS_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DDRSS_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
newline
bitfld.long 0x04 4. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND,Interrupt Pending Status for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1"
newline
bitfld.long 0x04 3. "DST_M2P_DST_BUSECC_PEND,Interrupt Pending Status for dst_m2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x04 2. "DST_M2P_SRC_BUSECC_PEND,Interrupt Pending Status for dst_m2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "M2M_M2M_VBUSS_PEND,Interrupt Pending Status for m2m_m2m_vbuss_pend" "0,1"
newline
bitfld.long 0x04 0. "M2M_DST_VBUSS_PEND,Interrupt Pending Status for m2m_dst_vbuss_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DDRSS_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
newline
bitfld.long 0x00 4. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DST_M2P_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "DST_M2P_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dst_m2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "M2M_M2M_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_m2m_vbuss_pend" "0,1"
newline
bitfld.long 0x00 0. "M2M_DST_VBUSS_ENABLE_SET,Interrupt Enable Set Register for m2m_dst_vbuss_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DDRSS_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
newline
bitfld.long 0x00 4. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DST_M2P_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "DST_M2P_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dst_m2p_src_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "M2M_M2M_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_m2m_vbuss_pend" "0,1"
newline
bitfld.long 0x00 0. "M2M_DST_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for m2m_dst_vbuss_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "DDRSS_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "DDRSS_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "DDRSS_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "DDRSS_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "DDRSS0_ECC_AGGR_CTL"
tree "COMPUTE_CLUSTER0_ECC_AGGR_CTL"
base ad:0x4D200B0000
rgroup.long 0x00++0x03
line.long 0x00 "DDRSS_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "DDRSS_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "DDRSS_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "DDRSS_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "DDRSS_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DDRSS_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x04 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1"
newline
bitfld.long 0x04 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1"
newline
bitfld.long 0x04 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1"
newline
bitfld.long 0x04 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "DDRSS_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1"
newline
bitfld.long 0x00 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1"
newline
bitfld.long 0x00 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1"
newline
bitfld.long 0x00 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DDRSS_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1"
newline
bitfld.long 0x00 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1"
newline
bitfld.long 0x00 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1"
newline
bitfld.long 0x00 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DDRSS_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DDRSS_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "V2A_EDC_CTRL_PEND,Interrupt Pending Status for v2a_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x04 3. "ASAFE_3_SI_PEND,Interrupt Pending Status for asafe_3_si_pend" "0,1"
newline
bitfld.long 0x04 2. "ASAFE_2_SI_PEND,Interrupt Pending Status for asafe_2_si_pend" "0,1"
newline
bitfld.long 0x04 1. "ASAFE_1_SI_PEND,Interrupt Pending Status for asafe_1_si_pend" "0,1"
newline
bitfld.long 0x04 0. "ASAFE_0_SI_PEND,Interrupt Pending Status for asafe_0_si_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DDRSS_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "V2A_EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for v2a_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 3. "ASAFE_3_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_3_si_pend" "0,1"
newline
bitfld.long 0x00 2. "ASAFE_2_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_2_si_pend" "0,1"
newline
bitfld.long 0x00 1. "ASAFE_1_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_1_si_pend" "0,1"
newline
bitfld.long 0x00 0. "ASAFE_0_SI_ENABLE_SET,Interrupt Enable Set Register for asafe_0_si_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DDRSS_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 5. "DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for ddr32ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_dst_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "V2A_EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for v2a_edc_ctrl_pend" "0,1"
newline
bitfld.long 0x00 3. "ASAFE_3_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_3_si_pend" "0,1"
newline
bitfld.long 0x00 2. "ASAFE_2_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_2_si_pend" "0,1"
newline
bitfld.long 0x00 1. "ASAFE_1_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_1_si_pend" "0,1"
newline
bitfld.long 0x00 0. "ASAFE_0_SI_ENABLE_CLR,Interrupt Enable Clear Register for asafe_0_si_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "DDRSS_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "DDRSS_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "DDRSS_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "DDRSS_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "DDRSS0_ECC_AGGR_VBUS"
tree "COMPUTE_CLUSTER0_ECC_AGGR_VBUS"
base ad:0x4D200B0400
rgroup.long 0x00++0x03
line.long 0x00 "DDRSS_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "DDRSS_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "DDRSS_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "DDRSS_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "DDRSS_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DDRSS_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "DDRSS_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DDRSS_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DDRSS_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DDRSS_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "VSAFE_SI_PEND,Interrupt Pending Status for vsafe_si_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DDRSS_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "VSAFE_SI_ENABLE_SET,Interrupt Enable Set Register for vsafe_si_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DDRSS_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "VSAFE_SI_ENABLE_CLR,Interrupt Enable Clear Register for vsafe_si_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "DDRSS_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "DDRSS_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "DDRSS_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "DDRSS_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "DECODER"
tree "DECODER0_IMG_VIDEO_BUS4_MMU"
base ad:0x4301000
group.long 0x00++0x03
line.long 0x00 "DECODER0_MMU_CONTROL0,"
bitfld.long 0x00 16. "USE_TILE_STRIDE_PER_CONTEXT," "0,1"
bitfld.long 0x00 12. "STALL_ON_PROTOCOL_FAULT,Debug only:Setting this bit to '1' causes any requestor with a protocol fault to stall" "0,1"
bitfld.long 0x00 9. "FORCE_CACHE_POLICY_BYPASS,Setting this bit to '1' causes all requests to external memory to have a cache policy of 0 [bypass] setting this bit to '0' passes internal cache policy to external interface" "0,1"
newline
bitfld.long 0x00 8. "MMU_CACHE_POLICY," "0,1"
bitfld.long 0x00 0. "MMU_TILING_SCHEME,This bit controls the tiling scheme described in MMU Address Tiling section" "0,1"
group.long 0x08++0x03
line.long 0x00 "DECODER0_MMU_CONTROL1,"
bitfld.long 0x00 28. "MMU_SOFT_RESET,Writing '1' to this bit causes all currently active or new memory requests to be discarded so a reset of all active requestors is likely to also be required" "0,1"
bitfld.long 0x00 25. "MMU_PAUSE_CLEAR,Writing '1' to this bit clears the pause bit and allows new memory requests to resume" "0,1"
bitfld.long 0x00 24. "MMU_PAUSE_SET,Writing '1' to this bit causes all new memory requests to pause [requests further down the pipeline will be allowed to complete]" "0,1"
newline
bitfld.long 0x00 20. "PROTOCOL_FAULT_CLEAR,Writing '1' to this bit clears all bus protocol fault flags" "0,1"
bitfld.long 0x00 16. "MMU_FAULT_CLEAR,Writing '1' to this bit clears MMU fault [either page fault or read/write fault]" "0,1"
bitfld.long 0x00 11. "MMU_INVALDC,For each 'dir_base_addr' used writing '1' triggers invalidation[/flushing] of both the directory cache and page table cache for that 'dir_base_addr' [cached results for different 'dir_base_addr' can be invalidated/flushed independently]" "0,1"
newline
bitfld.long 0x00 3. "MMU_FLUSH,For each 'dir_base_addr' used writing '1' triggers a flush of the Page Table cache and registered results for that 'dir_base_addr' [cached results for different 'dir_base_addr' can be flushed independently]" "0,1"
group.long 0x10++0x0F
line.long 0x00 "DECODER0_MMU_BANK_INDEX,"
bitfld.long 0x00 30.--31. "MMU_BANK_INDEX,Specify which directory base address to use for 'group override' input n [If GROUP_OVERRIDE_SIZE is 0 this register is not used otherwise there are '2 to the power GROUP_OVERRIDE_SIZE' entries supported in this register" "0,1,2,3"
line.long 0x04 "DECODER0_EXT_REQUEST_PRIORITY_ENABLE,"
bitfld.long 0x04 31. "EXT_CMD_PRIORITY_ENABLE,This register is only used if there are more than 16 requestors in which case it defines the enable for requestors 16 to 47" "0,1"
line.long 0x08 "DECODER0_REQUEST_PRIORITY_ENABLE,"
bitfld.long 0x08 16. "CMD_MMU_PRIORITY_ENABLE,MMU requests [Directory Table and Page Table reads] should normally be considered a priority on the bus infrastructure" "0,1"
bitfld.long 0x08 15. "CMD_PRIORITY_ENABLE,Each requestor can generate a command priority signal to indicate the request should be treated as a priority in the external bus infrastructure [MMU requests are always considered to be a priority]" "0,1"
line.long 0x0C "DECODER0_REQUEST_LIMITED_THROUGHPUT,This register controls the memory bus stalling behaviour which occurs when the 'mem_limited_throughput' input is set"
hexmask.long.word 0x0C 16.--27. 1. "REQUEST_GAP,Number of cycles all command requests are stalled for due to 'mem_limited_throughput' being set"
hexmask.long.word 0x0C 0.--9. 1. "LIMITED_WORDS,Number of commands which can be issued before all requests are stalled for 'REQUEST_GAP' cycles due to 'mem_limited_throughput' being set"
group.long 0x70++0x03
line.long 0x00 "DECODER0_MMU_ADDRESS_CONTROL,"
hexmask.long.byte 0x00 16.--23. 1. "UPPER_ADDRESS_FIXED,If 'EXTENDED_ADDR_RANGE' is > 0 and MMU is used in bypass mode or MMU_ENABLE_EXT_ADDRESSING = '0' EXTENDED_ADDR_RANGE bits from this field will be used to define the state of the upper physical address bits [for all memory.."
bitfld.long 0x00 8.--10. "SOFT_PAGE_SIZE,This field selects MMU page size at run time [if this field is less than the minimum hardware configuration for PAGE_SIZE from" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MMU_ENABLE_EXT_ADDRESSING," "0,1"
newline
bitfld.long 0x00 0. "MMU_BYPASS," "0,1"
rgroup.long 0x80++0x17
line.long 0x00 "DECODER0_MMU_CONFIG0,"
hexmask.long.word 0x00 22.--31. 1. "TAGS_SUPPORTED,Number of outstanding bursts supported"
bitfld.long 0x00 21. "NO_READ_REORDER,If this field is set it indicates there is no read data re-ordering buffer [all requestors must accept read response out of order]" "0,1"
bitfld.long 0x00 16.--20. "TILE_ADDR_GRANULARITY,This field indicates the granularity of the tile address range [where virtual address range is matched from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 14.--15. "NUM_REQUESTORS_EXT,In MMU version 4.2 onwards NUM_REQUESTORS_EXT*16 + NUM_REQUESTORS indicates the number of requestors the core has been configured for [before version 4.2 this field was always 0]" "0,1,2,3"
bitfld.long 0x00 13. "MMU_SUPPORTED,This field indicates if MMU page table mapping is supported [N.B" "0,1"
bitfld.long 0x00 12. "ADDR_COHERENCY_SUPPORTED,This field indicates if address coherency checking is supported [if it is not supported requestors need to use another mechanism to gurantee reads and writes to the same address don't occur out of order]" "0,1"
newline
bitfld.long 0x00 8.--10. "GROUP_OVERRIDE_SIZE,If this field is 0 only 1 directory base address is supported [MMU_DIR_BASE_ADDR0]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--7. "EXTENDED_ADDR_RANGE,This field indicates the number of extended address bits [above 32] that the external memory interface uses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "NUM_REQUESTORS,Before MMU version 4.2 this field indicates the number of requestors the core has been configured for [between 1 and 15 or a value of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DECODER0_MMU_CONFIG1,"
bitfld.long 0x04 30. "SUPPORT_EXCLUSIVE,Logic included to support exclusive transactions [for doing read-modify-write without another master modifying the value]" "0,1"
bitfld.long 0x04 29. "SUPPORT_STRIDE_PER_CONTEXT,Logic included to support separate tile stride per context" "0,1"
bitfld.long 0x04 28. "SUPPORT_READ_INTERLEAVE,Logic included to support interleaved read responses [violates Bus4 protocol but may occur when Bus4 to AXI bridge is used]" "0,1"
newline
bitfld.long 0x04 26. "LATENCY_COUNT_SUPPORTED,Latency counts included" "0,1"
bitfld.long 0x04 25. "STALL_COUNT_SUPPORTED,Stall counts included" "0,1"
bitfld.long 0x04 24. "BANDWIDTH_COUNT_SUPPORTED,Bandwidth counts included" "0,1"
newline
bitfld.long 0x04 16.--20. "DIR_CACHE_ENTRIES,DIR_CACHE_ENTRIES * 128 defines the number of Directory Table entries which can be cached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x04 8.--15. 1. "PAGE_CACHE_ENTRIES,PAGE_CACHE_ENTRIES * 128 defines the number of Page Table entries which can be cached"
bitfld.long 0x04 0.--3. "PAGE_SIZE,Log2 MMU page size minus 12 [4kbyte page = 0 16kbyte page = 2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DECODER0_MMU_STATUS0,"
hexmask.long.tbyte 0x08 12.--31. 1. "MMU_FAULT_ADDR,Page-aligned virtual address causing page fault"
bitfld.long 0x08 0. "MMU_PF_N_RW,Indicates whether the current fault is a page fault [when high] or R/W protection fault [when low]" "0,1"
line.long 0x0C "DECODER0_MMU_STATUS1,"
bitfld.long 0x0C 28. "MMU_FAULT_RNW,Indicates if a read or write operation caused the current fault" "0,1"
bitfld.long 0x0C 24.--25. "MMU_FAULT_INDEX,Indicates the directory cache index of the current fault" "0,1,2,3"
bitfld.long 0x0C 16.--21. "MMU_FAULT_REQ_ID,Indicates the requestor ID of the request causing the current page fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x0C 0.--15. 1. "MMU_FAULT_REQ_STAT,"
line.long 0x10 "DECODER0_MMU_MEM_REQ,"
bitfld.long 0x10 31. "INT_PROTOCOL_FAULT,When set indicates the corresponding requestor had a bus protocol fault [excludes MMU requests]" "0,1"
bitfld.long 0x10 14. "EXT_READ_BURST_FAULT,When set indicates the external interface returned a read burst for a tag which didn't contain the expected number of words" "0,1"
bitfld.long 0x10 13. "EXT_RDRESP_FAULT,When set indicates the external interface returned a read response for a tag which wasn't outstanding [may occur after reset]" "0,1"
newline
bitfld.long 0x10 12. "EXT_WRRESP_FAULT,When set indicates the external interface returned a write response for a tag which wasn't outstanding [may occur after reset]" "0,1"
hexmask.long.word 0x10 0.--9. 1. "TAG_OUTSTANDING,Number of outstanding burst requests [TAGS which have been allocated but not yet freed includes reads which have been returned but are still in the read re-order buffer]"
line.long 0x14 "DECODER0_MMU_MEM_EXT_OUTSTANDING,"
hexmask.long.word 0x14 0.--15. 1. "READ_WORDS_OUTSTANDING,Number of outstanding read words [in which read commands have been sent to the external interface but the corresponding words haven't been received yet counted in 'external data bus width' words]"
group.long 0xA0++0x03
line.long 0x00 "DECODER0_MMU_FAULT_SELECT,"
bitfld.long 0x00 0.--3. "MMU_FAULT_SELECT,The core can be configured to include protocol checkers on the input requestors this field selects which interface is read from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xA8++0x03
line.long 0x00 "DECODER0_PROTOCOL_FAULT,"
bitfld.long 0x00 5. "FAULT_READ,For requestor interface indicates a read command on a requestor configured for write only" "0,1"
bitfld.long 0x00 4. "FAULT_WRITE,For requestor interface indicates a write command on a requestor configured for read only" "0,1"
bitfld.long 0x00 0. "FAULT_PAGE_BREAK,The command crossed a page in the middle of a burst" "0,1"
rgroup.long 0x100++0x0F
line.long 0x00 "DECODER0_TOTAL_READ_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x04 "DECODER0_TOTAL_WRITE_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x08 "DECODER0_READS_LESS_64_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x0C "DECODER0_WRITES_LESS_64_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
rgroup.long 0x120++0x13
line.long 0x00 "DECODER0_EXT_CMD_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x04 "DECODER0_WRITE_REQ_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x08 "DECODER0_MMU_MISS_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x0C "DECODER0_ADDRESS_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x10 "DECODER0_TAG_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
rgroup.long 0x140++0x07
line.long 0x00 "DECODER0_PEAK_READ_OUTSTANDING,If .LATENCY_COUNT_SUPPORTED is 0. this register will be fixed at 0"
hexmask.long.word 0x00 16.--31. 1. "PEAK_READ_LATENCY,Debug only: Peak read latency detected [number of cycles a read tag remains outstanding]"
hexmask.long.word 0x00 0.--9. 1. "PEAK_TAG_OUTSTANDING,Debug only: Largest value on TAG_OUTSTANDING since last initialisation"
line.long 0x04 "DECODER0_AVERAGE_READ_LATENCY,If .LATENCY_COUNT_SUPPORTED is 0. this register will be fixed at 0"
group.long 0x160++0x03
line.long 0x00 "DECODER0_STATISTICS_CONTROL,"
bitfld.long 0x00 2. "LATENCY_STATS_INIT,Writing '1' resets the latency statistics [this bit automatically clears to '0']" "0,1"
bitfld.long 0x00 1. "STALL_STATS_INIT,Writing '1' resets the stall count statistics [this bit automatically clears to '0']" "0,1"
bitfld.long 0x00 0. "BANDWIDTH_STATS_INIT,Writing '1' resets the bandwidth statistics [this bit automatically clears to '0']" "0,1"
rgroup.long 0x1D0++0x03
line.long 0x00 "DECODER0_MMU_VERSION,"
hexmask.long.byte 0x00 16.--23. 1. "MMU_MAJOR_REV,MMU Major Revision"
hexmask.long.byte 0x00 8.--15. 1. "MMU_MINOR_REV,MMU Minor Revision"
hexmask.long.byte 0x00 0.--7. 1. "MMU_MAINT_REV,MMU Maintenance Revision"
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x60)++0x03
line.long 0x00 "DECODER0_MMU_TILE_MAX_ADDR_$1,"
repeat.end
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "DECODER0_MMU_TILE_MIN_ADDR_$1,"
repeat.end
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x40)++0x03
line.long 0x00 "DECODER0_MMU_TILE_CFG_$1,If USE_TILE_STRIDE_PER_CONTEXT is low. only the bottom byte of the register is used. and each of the four registers applies to the four regions defined by the corresponding MIN and MAX tile address ranges.If.."
bitfld.long 0x00 28. "TILE_128INTERLEAVE_SPCR3," "0,1"
bitfld.long 0x00 27. "TILE_ENABLE_SPCR3," "0,1"
newline
bitfld.long 0x00 24.--26. "TILE_STRIDE_SPCR3,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20. "TILE_128INTERLEAVE_SPCR2," "0,1"
newline
bitfld.long 0x00 19. "TILE_ENABLE_SPCR2," "0,1"
bitfld.long 0x00 16.--18. "TILE_STRIDE_SPCR2,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "TILE_128INTERLEAVE_SPCR1," "0,1"
bitfld.long 0x00 11. "TILE_ENABLE_SPCR1," "0,1"
newline
bitfld.long 0x00 8.--10. "TILE_STRIDE_SPCR1,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "TILE_128INTERLEAVE," "0,1"
newline
bitfld.long 0x00 3. "TILE_ENABLE," "0,1"
bitfld.long 0x00 0.--2. "TILE_STRIDE,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
repeat.end
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x20)++0x03
line.long 0x00 "DECODER0_MMU_DIR_BASE_ADDR_$1,"
repeat.end
tree.end
tree "DECODER0_IMG_VIDEO_BUS4_MMU2"
base ad:0x4321000
group.long 0x00++0x03
line.long 0x00 "DECODER0_MMU_CONTROL0,"
bitfld.long 0x00 16. "USE_TILE_STRIDE_PER_CONTEXT," "0,1"
bitfld.long 0x00 12. "STALL_ON_PROTOCOL_FAULT,Debug only:Setting this bit to '1' causes any requestor with a protocol fault to stall" "0,1"
bitfld.long 0x00 9. "FORCE_CACHE_POLICY_BYPASS,Setting this bit to '1' causes all requests to external memory to have a cache policy of 0 [bypass] setting this bit to '0' passes internal cache policy to external interface" "0,1"
newline
bitfld.long 0x00 8. "MMU_CACHE_POLICY," "0,1"
bitfld.long 0x00 0. "MMU_TILING_SCHEME,This bit controls the tiling scheme described in MMU Address Tiling section" "0,1"
group.long 0x08++0x03
line.long 0x00 "DECODER0_MMU_CONTROL1,"
bitfld.long 0x00 28. "MMU_SOFT_RESET,Writing '1' to this bit causes all currently active or new memory requests to be discarded so a reset of all active requestors is likely to also be required" "0,1"
bitfld.long 0x00 25. "MMU_PAUSE_CLEAR,Writing '1' to this bit clears the pause bit and allows new memory requests to resume" "0,1"
bitfld.long 0x00 24. "MMU_PAUSE_SET,Writing '1' to this bit causes all new memory requests to pause [requests further down the pipeline will be allowed to complete]" "0,1"
newline
bitfld.long 0x00 20. "PROTOCOL_FAULT_CLEAR,Writing '1' to this bit clears all bus protocol fault flags" "0,1"
bitfld.long 0x00 16. "MMU_FAULT_CLEAR,Writing '1' to this bit clears MMU fault [either page fault or read/write fault]" "0,1"
bitfld.long 0x00 11. "MMU_INVALDC,For each 'dir_base_addr' used writing '1' triggers invalidation[/flushing] of both the directory cache and page table cache for that 'dir_base_addr' [cached results for different 'dir_base_addr' can be invalidated/flushed independently]" "0,1"
newline
bitfld.long 0x00 3. "MMU_FLUSH,For each 'dir_base_addr' used writing '1' triggers a flush of the Page Table cache and registered results for that 'dir_base_addr' [cached results for different 'dir_base_addr' can be flushed independently]" "0,1"
group.long 0x10++0x0F
line.long 0x00 "DECODER0_MMU_BANK_INDEX,"
bitfld.long 0x00 30.--31. "MMU_BANK_INDEX,Specify which directory base address to use for 'group override' input n [If GROUP_OVERRIDE_SIZE is 0 this register is not used otherwise there are '2 to the power GROUP_OVERRIDE_SIZE' entries supported in this register" "0,1,2,3"
line.long 0x04 "DECODER0_EXT_REQUEST_PRIORITY_ENABLE,"
bitfld.long 0x04 31. "EXT_CMD_PRIORITY_ENABLE,This register is only used if there are more than 16 requestors in which case it defines the enable for requestors 16 to 47" "0,1"
line.long 0x08 "DECODER0_REQUEST_PRIORITY_ENABLE,"
bitfld.long 0x08 16. "CMD_MMU_PRIORITY_ENABLE,MMU requests [Directory Table and Page Table reads] should normally be considered a priority on the bus infrastructure" "0,1"
bitfld.long 0x08 15. "CMD_PRIORITY_ENABLE,Each requestor can generate a command priority signal to indicate the request should be treated as a priority in the external bus infrastructure [MMU requests are always considered to be a priority]" "0,1"
line.long 0x0C "DECODER0_REQUEST_LIMITED_THROUGHPUT,This register controls the memory bus stalling behaviour which occurs when the 'mem_limited_throughput' input is set"
hexmask.long.word 0x0C 16.--27. 1. "REQUEST_GAP,Number of cycles all command requests are stalled for due to 'mem_limited_throughput' being set"
hexmask.long.word 0x0C 0.--9. 1. "LIMITED_WORDS,Number of commands which can be issued before all requests are stalled for 'REQUEST_GAP' cycles due to 'mem_limited_throughput' being set"
group.long 0x70++0x03
line.long 0x00 "DECODER0_MMU_ADDRESS_CONTROL,"
hexmask.long.byte 0x00 16.--23. 1. "UPPER_ADDRESS_FIXED,If 'EXTENDED_ADDR_RANGE' is > 0 and MMU is used in bypass mode or MMU_ENABLE_EXT_ADDRESSING = '0' EXTENDED_ADDR_RANGE bits from this field will be used to define the state of the upper physical address bits [for all memory.."
bitfld.long 0x00 8.--10. "SOFT_PAGE_SIZE,This field selects MMU page size at run time [if this field is less than the minimum hardware configuration for PAGE_SIZE from" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "MMU_ENABLE_EXT_ADDRESSING," "0,1"
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bitfld.long 0x00 0. "MMU_BYPASS," "0,1"
rgroup.long 0x80++0x17
line.long 0x00 "DECODER0_MMU_CONFIG0,"
hexmask.long.word 0x00 22.--31. 1. "TAGS_SUPPORTED,Number of outstanding bursts supported"
bitfld.long 0x00 21. "NO_READ_REORDER,If this field is set it indicates there is no read data re-ordering buffer [all requestors must accept read response out of order]" "0,1"
bitfld.long 0x00 16.--20. "TILE_ADDR_GRANULARITY,This field indicates the granularity of the tile address range [where virtual address range is matched from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--15. "NUM_REQUESTORS_EXT,In MMU version 4.2 onwards NUM_REQUESTORS_EXT*16 + NUM_REQUESTORS indicates the number of requestors the core has been configured for [before version 4.2 this field was always 0]" "0,1,2,3"
bitfld.long 0x00 13. "MMU_SUPPORTED,This field indicates if MMU page table mapping is supported [N.B" "0,1"
bitfld.long 0x00 12. "ADDR_COHERENCY_SUPPORTED,This field indicates if address coherency checking is supported [if it is not supported requestors need to use another mechanism to gurantee reads and writes to the same address don't occur out of order]" "0,1"
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bitfld.long 0x00 8.--10. "GROUP_OVERRIDE_SIZE,If this field is 0 only 1 directory base address is supported [MMU_DIR_BASE_ADDR0]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--7. "EXTENDED_ADDR_RANGE,This field indicates the number of extended address bits [above 32] that the external memory interface uses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "NUM_REQUESTORS,Before MMU version 4.2 this field indicates the number of requestors the core has been configured for [between 1 and 15 or a value of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DECODER0_MMU_CONFIG1,"
bitfld.long 0x04 30. "SUPPORT_EXCLUSIVE,Logic included to support exclusive transactions [for doing read-modify-write without another master modifying the value]" "0,1"
bitfld.long 0x04 29. "SUPPORT_STRIDE_PER_CONTEXT,Logic included to support separate tile stride per context" "0,1"
bitfld.long 0x04 28. "SUPPORT_READ_INTERLEAVE,Logic included to support interleaved read responses [violates Bus4 protocol but may occur when Bus4 to AXI bridge is used]" "0,1"
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bitfld.long 0x04 26. "LATENCY_COUNT_SUPPORTED,Latency counts included" "0,1"
bitfld.long 0x04 25. "STALL_COUNT_SUPPORTED,Stall counts included" "0,1"
bitfld.long 0x04 24. "BANDWIDTH_COUNT_SUPPORTED,Bandwidth counts included" "0,1"
newline
bitfld.long 0x04 16.--20. "DIR_CACHE_ENTRIES,DIR_CACHE_ENTRIES * 128 defines the number of Directory Table entries which can be cached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x04 8.--15. 1. "PAGE_CACHE_ENTRIES,PAGE_CACHE_ENTRIES * 128 defines the number of Page Table entries which can be cached"
bitfld.long 0x04 0.--3. "PAGE_SIZE,Log2 MMU page size minus 12 [4kbyte page = 0 16kbyte page = 2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DECODER0_MMU_STATUS0,"
hexmask.long.tbyte 0x08 12.--31. 1. "MMU_FAULT_ADDR,Page-aligned virtual address causing page fault"
bitfld.long 0x08 0. "MMU_PF_N_RW,Indicates whether the current fault is a page fault [when high] or R/W protection fault [when low]" "0,1"
line.long 0x0C "DECODER0_MMU_STATUS1,"
bitfld.long 0x0C 28. "MMU_FAULT_RNW,Indicates if a read or write operation caused the current fault" "0,1"
bitfld.long 0x0C 24.--25. "MMU_FAULT_INDEX,Indicates the directory cache index of the current fault" "0,1,2,3"
bitfld.long 0x0C 16.--21. "MMU_FAULT_REQ_ID,Indicates the requestor ID of the request causing the current page fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x0C 0.--15. 1. "MMU_FAULT_REQ_STAT,"
line.long 0x10 "DECODER0_MMU_MEM_REQ,"
bitfld.long 0x10 31. "INT_PROTOCOL_FAULT,When set indicates the corresponding requestor had a bus protocol fault [excludes MMU requests]" "0,1"
bitfld.long 0x10 14. "EXT_READ_BURST_FAULT,When set indicates the external interface returned a read burst for a tag which didn't contain the expected number of words" "0,1"
bitfld.long 0x10 13. "EXT_RDRESP_FAULT,When set indicates the external interface returned a read response for a tag which wasn't outstanding [may occur after reset]" "0,1"
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bitfld.long 0x10 12. "EXT_WRRESP_FAULT,When set indicates the external interface returned a write response for a tag which wasn't outstanding [may occur after reset]" "0,1"
hexmask.long.word 0x10 0.--9. 1. "TAG_OUTSTANDING,Number of outstanding burst requests [TAGS which have been allocated but not yet freed includes reads which have been returned but are still in the read re-order buffer]"
line.long 0x14 "DECODER0_MMU_MEM_EXT_OUTSTANDING,"
hexmask.long.word 0x14 0.--15. 1. "READ_WORDS_OUTSTANDING,Number of outstanding read words [in which read commands have been sent to the external interface but the corresponding words haven't been received yet counted in 'external data bus width' words]"
group.long 0xA0++0x03
line.long 0x00 "DECODER0_MMU_FAULT_SELECT,"
bitfld.long 0x00 0.--3. "MMU_FAULT_SELECT,The core can be configured to include protocol checkers on the input requestors this field selects which interface is read from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xA8++0x03
line.long 0x00 "DECODER0_PROTOCOL_FAULT,"
bitfld.long 0x00 5. "FAULT_READ,For requestor interface indicates a read command on a requestor configured for write only" "0,1"
bitfld.long 0x00 4. "FAULT_WRITE,For requestor interface indicates a write command on a requestor configured for read only" "0,1"
bitfld.long 0x00 0. "FAULT_PAGE_BREAK,The command crossed a page in the middle of a burst" "0,1"
rgroup.long 0x100++0x0F
line.long 0x00 "DECODER0_TOTAL_READ_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x04 "DECODER0_TOTAL_WRITE_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x08 "DECODER0_READS_LESS_64_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x0C "DECODER0_WRITES_LESS_64_REQ,If .BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0"
rgroup.long 0x120++0x13
line.long 0x00 "DECODER0_EXT_CMD_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x04 "DECODER0_WRITE_REQ_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x08 "DECODER0_MMU_MISS_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x0C "DECODER0_ADDRESS_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
line.long 0x10 "DECODER0_TAG_STALL,If .STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0"
rgroup.long 0x140++0x07
line.long 0x00 "DECODER0_PEAK_READ_OUTSTANDING,If .LATENCY_COUNT_SUPPORTED is 0. this register will be fixed at 0"
hexmask.long.word 0x00 16.--31. 1. "PEAK_READ_LATENCY,Debug only: Peak read latency detected [number of cycles a read tag remains outstanding]"
hexmask.long.word 0x00 0.--9. 1. "PEAK_TAG_OUTSTANDING,Debug only: Largest value on TAG_OUTSTANDING since last initialisation"
line.long 0x04 "DECODER0_AVERAGE_READ_LATENCY,If .LATENCY_COUNT_SUPPORTED is 0. this register will be fixed at 0"
group.long 0x160++0x03
line.long 0x00 "DECODER0_STATISTICS_CONTROL,"
bitfld.long 0x00 2. "LATENCY_STATS_INIT,Writing '1' resets the latency statistics [this bit automatically clears to '0']" "0,1"
bitfld.long 0x00 1. "STALL_STATS_INIT,Writing '1' resets the stall count statistics [this bit automatically clears to '0']" "0,1"
bitfld.long 0x00 0. "BANDWIDTH_STATS_INIT,Writing '1' resets the bandwidth statistics [this bit automatically clears to '0']" "0,1"
rgroup.long 0x1D0++0x03
line.long 0x00 "DECODER0_MMU_VERSION,"
hexmask.long.byte 0x00 16.--23. 1. "MMU_MAJOR_REV,MMU Major Revision"
hexmask.long.byte 0x00 8.--15. 1. "MMU_MINOR_REV,MMU Minor Revision"
hexmask.long.byte 0x00 0.--7. 1. "MMU_MAINT_REV,MMU Maintenance Revision"
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x60)++0x03
line.long 0x00 "DECODER0_MMU_TILE_MAX_ADDR_$1,"
repeat.end
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "DECODER0_MMU_TILE_MIN_ADDR_$1,"
repeat.end
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x40)++0x03
line.long 0x00 "DECODER0_MMU_TILE_CFG_$1,If USE_TILE_STRIDE_PER_CONTEXT is low. only the bottom byte of the register is used. and each of the four registers applies to the four regions defined by the corresponding MIN and MAX tile address ranges.If.."
bitfld.long 0x00 28. "TILE_128INTERLEAVE_SPCR3," "0,1"
bitfld.long 0x00 27. "TILE_ENABLE_SPCR3," "0,1"
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bitfld.long 0x00 24.--26. "TILE_STRIDE_SPCR3,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20. "TILE_128INTERLEAVE_SPCR2," "0,1"
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bitfld.long 0x00 19. "TILE_ENABLE_SPCR2," "0,1"
bitfld.long 0x00 16.--18. "TILE_STRIDE_SPCR2,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "TILE_128INTERLEAVE_SPCR1," "0,1"
bitfld.long 0x00 11. "TILE_ENABLE_SPCR1," "0,1"
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bitfld.long 0x00 8.--10. "TILE_STRIDE_SPCR1,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "TILE_128INTERLEAVE," "0,1"
newline
bitfld.long 0x00 3. "TILE_ENABLE," "0,1"
bitfld.long 0x00 0.--2. "TILE_STRIDE,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7"
repeat.end
repeat 4. (list 00. 01. 02. 03. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x20)++0x03
line.long 0x00 "DECODER0_MMU_DIR_BASE_ADDR_$1,"
repeat.end
tree.end
tree "DECODER0_MSVDX_AXI"
base ad:0x4301800
group.long 0x04++0x03
line.long 0x00 "DECODER0_AXI_EXACCESS,"
bitfld.long 0x00 0. "ENABLE,enable the exclusive access logic in the module img2_axi2img.vhd" "0,1"
tree.end
tree "DECODER0_MSVDX_AXI2"
base ad:0x4321800
group.long 0x04++0x03
line.long 0x00 "DECODER0_AXI_EXACCESS,"
bitfld.long 0x00 0. "ENABLE,enable the exclusive access logic in the module img2_axi2img.vhd" "0,1"
tree.end
tree.end
tree "DMPAC_CFG"
tree "DMPAC_TOP_MAIN_0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS"
base ad:0xF400000
rgroup.long 0x00++0x03
line.long 0x00 "DMPAC_INTD_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
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bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,MajorDMPAC_INTD_REVISION" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,CustomDMPAC_INTD_REVISION" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINREV,MinorDMPAC_INTD_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "DMPAC_INTD_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "DMPAC_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x6F
line.long 0x00 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_0,Enable Register 0"
bitfld.long 0x00 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR,Enable Set for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x00 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR,Enable Set for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT,Enable Set for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR,Enable Set for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR,Enable Set for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT,Enable Set for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_WRITE_ERROR,Enable Set for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_READ_ERROR,Enable Set for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_FRAME_DONE,Enable Set for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_BLK_DONE,Enable Set for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_WRITE_ERROR,Enable Set for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_READ_ERROR,Enable Set for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_FRAME_DONE,Enable Set for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_ROW_DONE,Enable Set for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_1,Enable Register 1"
bitfld.long 0x04 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_8,Enable Set for level_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_7,Enable Set for level_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x04 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_1,Enable Set for level_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x04 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_0,Enable Set for level_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_L,Enable Set for level_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_P,Enable Set for level_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_L,Enable Set for level_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_P,Enable Set for level_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_2,Enable Register 2"
bitfld.long 0x08 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_3,Enable Register 3"
bitfld.long 0x0C 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_31,Enable Set for level_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x0C 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_30,Enable Set for level_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x0C 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_29,Enable Set for level_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x0C 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_28,Enable Set for level_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x0C 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_27,Enable Set for level_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x0C 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_26,Enable Set for level_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x0C 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_25,Enable Set for level_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x0C 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_24,Enable Set for level_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x0C 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_23,Enable Set for level_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x0C 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_22,Enable Set for level_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x0C 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_21,Enable Set for level_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x0C 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_20,Enable Set for level_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_19,Enable Set for level_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x0C 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_18,Enable Set for level_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x0C 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_17,Enable Set for level_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x0C 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_16,Enable Set for level_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_15,Enable Set for level_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x0C 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_14,Enable Set for level_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x0C 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_13,Enable Set for level_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x0C 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_12,Enable Set for level_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_11,Enable Set for level_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x0C 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_10,Enable Set for level_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_9,Enable Set for level_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_8,Enable Set for level_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_7,Enable Set for level_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x0C 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_6,Enable Set for level_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x0C 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_5,Enable Set for level_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x0C 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_4,Enable Set for level_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_3,Enable Set for level_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_2,Enable Set for level_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_1,Enable Set for level_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_0,Enable Set for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_4,Enable Register 4"
bitfld.long 0x10 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_31,Enable Set for level_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x10 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_30,Enable Set for level_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x10 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_29,Enable Set for level_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_28,Enable Set for level_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_27,Enable Set for level_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x10 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_26,Enable Set for level_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_25,Enable Set for level_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_24,Enable Set for level_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_23,Enable Set for level_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_22,Enable Set for level_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x10 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_21,Enable Set for level_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_20,Enable Set for level_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_19,Enable Set for level_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_18,Enable Set for level_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_17,Enable Set for level_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_16,Enable Set for level_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_15,Enable Set for level_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_14,Enable Set for level_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_13,Enable Set for level_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_12,Enable Set for level_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_11,Enable Set for level_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_10,Enable Set for level_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_9,Enable Set for level_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x10 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_8,Enable Set for level_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_7,Enable Set for level_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_6,Enable Set for level_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_5,Enable Set for level_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_4,Enable Set for level_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_3,Enable Set for level_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_2,Enable Set for level_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_1,Enable Set for level_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_0,Enable Set for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_5,Enable Register 5"
bitfld.long 0x14 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_6,Enable Register 6"
bitfld.long 0x18 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_CTM_PULSE,Enable Set for level_dmpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x18 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_PROT_ERR,Enable Set for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_0,Enable Register 7"
bitfld.long 0x1C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR,Enable Set for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR,Enable Set for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT,Enable Set for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR,Enable Set for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR,Enable Set for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT,Enable Set for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_WRITE_ERROR,Enable Set for level_dmpac_out_1_en_sde_write_error" "0,1"
newline
bitfld.long 0x1C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_READ_ERROR,Enable Set for level_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x1C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_FRAME_DONE,Enable Set for level_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x1C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_BLK_DONE,Enable Set for level_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x1C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x1C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_WRITE_ERROR,Enable Set for level_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x1C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_READ_ERROR,Enable Set for level_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x1C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_FRAME_DONE,Enable Set for level_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x1C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_ROW_DONE,Enable Set for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_1,Enable Register 8"
bitfld.long 0x20 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_8,Enable Set for level_dmpac_out_1_en_tdone_8" "0,1"
newline
bitfld.long 0x20 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_7,Enable Set for level_dmpac_out_1_en_tdone_7" "0,1"
newline
bitfld.long 0x20 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_1,Enable Set for level_dmpac_out_1_en_tdone_1" "0,1"
newline
bitfld.long 0x20 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_0,Enable Set for level_dmpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x20 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_L,Enable Set for level_dmpac_out_1_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x20 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_P,Enable Set for level_dmpac_out_1_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x20 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_L,Enable Set for level_dmpac_out_1_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x20 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_P,Enable Set for level_dmpac_out_1_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x20 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for level_dmpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x20 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for level_dmpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x20 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for level_dmpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x20 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for level_dmpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x20 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for level_dmpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x20 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_2,Enable Register 9"
bitfld.long 0x24 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x24 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x24 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x24 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_3,Enable Register 10"
bitfld.long 0x28 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_31,Enable Set for level_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x28 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_30,Enable Set for level_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x28 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_29,Enable Set for level_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x28 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_28,Enable Set for level_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x28 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_27,Enable Set for level_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x28 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_26,Enable Set for level_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x28 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_25,Enable Set for level_dmpac_out_1_en_dru_error_25" "0,1"
newline
bitfld.long 0x28 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_24,Enable Set for level_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x28 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_23,Enable Set for level_dmpac_out_1_en_dru_error_23" "0,1"
newline
bitfld.long 0x28 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_22,Enable Set for level_dmpac_out_1_en_dru_error_22" "0,1"
newline
bitfld.long 0x28 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_21,Enable Set for level_dmpac_out_1_en_dru_error_21" "0,1"
newline
bitfld.long 0x28 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_20,Enable Set for level_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x28 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_19,Enable Set for level_dmpac_out_1_en_dru_error_19" "0,1"
newline
bitfld.long 0x28 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_18,Enable Set for level_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x28 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_17,Enable Set for level_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x28 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_16,Enable Set for level_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x28 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_15,Enable Set for level_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x28 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_14,Enable Set for level_dmpac_out_1_en_dru_error_14" "0,1"
newline
bitfld.long 0x28 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_13,Enable Set for level_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x28 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_12,Enable Set for level_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x28 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_11,Enable Set for level_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x28 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_10,Enable Set for level_dmpac_out_1_en_dru_error_10" "0,1"
newline
bitfld.long 0x28 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_9,Enable Set for level_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x28 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_8,Enable Set for level_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x28 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_7,Enable Set for level_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x28 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_6,Enable Set for level_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x28 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_5,Enable Set for level_dmpac_out_1_en_dru_error_5" "0,1"
newline
bitfld.long 0x28 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_4,Enable Set for level_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x28 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_3,Enable Set for level_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x28 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_2,Enable Set for level_dmpac_out_1_en_dru_error_2" "0,1"
newline
bitfld.long 0x28 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_1,Enable Set for level_dmpac_out_1_en_dru_error_1" "0,1"
newline
bitfld.long 0x28 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_0,Enable Set for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_4,Enable Register 11"
bitfld.long 0x2C 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_31,Enable Set for level_dmpac_out_1_en_dru_complete_31" "0,1"
newline
bitfld.long 0x2C 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_30,Enable Set for level_dmpac_out_1_en_dru_complete_30" "0,1"
newline
bitfld.long 0x2C 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_29,Enable Set for level_dmpac_out_1_en_dru_complete_29" "0,1"
newline
bitfld.long 0x2C 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_28,Enable Set for level_dmpac_out_1_en_dru_complete_28" "0,1"
newline
bitfld.long 0x2C 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_27,Enable Set for level_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x2C 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_26,Enable Set for level_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x2C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_25,Enable Set for level_dmpac_out_1_en_dru_complete_25" "0,1"
newline
bitfld.long 0x2C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_24,Enable Set for level_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x2C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_23,Enable Set for level_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x2C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_22,Enable Set for level_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x2C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_21,Enable Set for level_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x2C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_20,Enable Set for level_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x2C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_19,Enable Set for level_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x2C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_18,Enable Set for level_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x2C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_17,Enable Set for level_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x2C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_16,Enable Set for level_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x2C 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_15,Enable Set for level_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x2C 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_14,Enable Set for level_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x2C 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_13,Enable Set for level_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x2C 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_12,Enable Set for level_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x2C 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_11,Enable Set for level_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x2C 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_10,Enable Set for level_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x2C 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_9,Enable Set for level_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x2C 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_8,Enable Set for level_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x2C 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_7,Enable Set for level_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x2C 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_6,Enable Set for level_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x2C 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_5,Enable Set for level_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x2C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_4,Enable Set for level_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x2C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_3,Enable Set for level_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x2C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_2,Enable Set for level_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x2C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_1,Enable Set for level_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x2C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_0,Enable Set for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_5,Enable Register 12"
bitfld.long 0x30 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x30 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x30 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x30 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x30 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x30 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x30 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x30 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x30 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x30 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x30 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x30 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x30 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x30 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x30 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x30 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x30 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x30 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x30 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x30 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x30 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x30 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x30 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x30 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x30 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x30 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x30 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x30 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x30 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x30 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x30 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x30 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_6,Enable Register 13"
bitfld.long 0x34 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_CTM_PULSE,Enable Set for level_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x34 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_PROT_ERR,Enable Set for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_0,Enable Register 14"
bitfld.long 0x38 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR,Enable Set for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR,Enable Set for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT,Enable Set for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x38 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR,Enable Set for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR,Enable Set for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT,Enable Set for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x38 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_WRITE_ERROR,Enable Set for pulse_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x38 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_READ_ERROR,Enable Set for pulse_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x38 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_FRAME_DONE,Enable Set for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x38 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_BLK_DONE,Enable Set for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x38 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x38 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_WRITE_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x38 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_READ_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x38 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_FRAME_DONE,Enable Set for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x38 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_ROW_DONE,Enable Set for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_1,Enable Register 15"
bitfld.long 0x3C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_8,Enable Set for pulse_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x3C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_7,Enable Set for pulse_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x3C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_1,Enable Set for pulse_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x3C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_0,Enable Set for pulse_dmpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0x3C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_L,Enable Set for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x3C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_P,Enable Set for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x3C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_L,Enable Set for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x3C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_P,Enable Set for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x3C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x3C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x3C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x3C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x3C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x3C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_2,Enable Register 16"
bitfld.long 0x40 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x40 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x40 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x40 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_3,Enable Register 17"
bitfld.long 0x44 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_31,Enable Set for pulse_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x44 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_30,Enable Set for pulse_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x44 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_29,Enable Set for pulse_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x44 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_28,Enable Set for pulse_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x44 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_27,Enable Set for pulse_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x44 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_26,Enable Set for pulse_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x44 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_25,Enable Set for pulse_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x44 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_24,Enable Set for pulse_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x44 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_23,Enable Set for pulse_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x44 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_22,Enable Set for pulse_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x44 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_21,Enable Set for pulse_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x44 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_20,Enable Set for pulse_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x44 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_19,Enable Set for pulse_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x44 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_18,Enable Set for pulse_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x44 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_17,Enable Set for pulse_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x44 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_16,Enable Set for pulse_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x44 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_15,Enable Set for pulse_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x44 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_14,Enable Set for pulse_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x44 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_13,Enable Set for pulse_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x44 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_12,Enable Set for pulse_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x44 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_11,Enable Set for pulse_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x44 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_10,Enable Set for pulse_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x44 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_9,Enable Set for pulse_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x44 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_8,Enable Set for pulse_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x44 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_7,Enable Set for pulse_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x44 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_6,Enable Set for pulse_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x44 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_5,Enable Set for pulse_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x44 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_4,Enable Set for pulse_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x44 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_3,Enable Set for pulse_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x44 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_2,Enable Set for pulse_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x44 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_1,Enable Set for pulse_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x44 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_0,Enable Set for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_4,Enable Register 18"
bitfld.long 0x48 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_31,Enable Set for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x48 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_30,Enable Set for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x48 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_29,Enable Set for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x48 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_28,Enable Set for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x48 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_27,Enable Set for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x48 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_26,Enable Set for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x48 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_25,Enable Set for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x48 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_24,Enable Set for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x48 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_23,Enable Set for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x48 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_22,Enable Set for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x48 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_21,Enable Set for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x48 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_20,Enable Set for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x48 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_19,Enable Set for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x48 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_18,Enable Set for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x48 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_17,Enable Set for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x48 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_16,Enable Set for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x48 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_15,Enable Set for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x48 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_14,Enable Set for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x48 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_13,Enable Set for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x48 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_12,Enable Set for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x48 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_11,Enable Set for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x48 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_10,Enable Set for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x48 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_9,Enable Set for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x48 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_8,Enable Set for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x48 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_7,Enable Set for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x48 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_6,Enable Set for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x48 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_5,Enable Set for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x48 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_4,Enable Set for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x48 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_3,Enable Set for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x48 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_2,Enable Set for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x48 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_1,Enable Set for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x48 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_0,Enable Set for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_5,Enable Register 19"
bitfld.long 0x4C 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x4C 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x4C 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x4C 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x4C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x4C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x4C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x4C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x4C 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x4C 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x4C 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x4C 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x4C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x4C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x4C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x4C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x4C 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x4C 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x4C 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x4C 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x4C 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x4C 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x4C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x4C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x4C 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x4C 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x4C 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x4C 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x4C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x4C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x4C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x4C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_6,Enable Register 20"
bitfld.long 0x50 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_CTM_PULSE,Enable Set for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x50 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_PROT_ERR,Enable Set for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_0,Enable Register 21"
bitfld.long 0x54 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR,Enable Set for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x54 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR,Enable Set for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x54 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT,Enable Set for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x54 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR,Enable Set for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x54 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR,Enable Set for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x54 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT,Enable Set for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x54 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_WRITE_ERROR,Enable Set for pulse_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x54 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_READ_ERROR,Enable Set for pulse_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x54 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_FRAME_DONE,Enable Set for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x54 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_BLK_DONE,Enable Set for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x54 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x54 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_WRITE_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x54 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_READ_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x54 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_FRAME_DONE,Enable Set for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x54 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_ROW_DONE,Enable Set for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_1,Enable Register 22"
bitfld.long 0x58 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_8,Enable Set for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_7,Enable Set for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_1,Enable Set for pulse_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x58 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_0,Enable Set for pulse_dmpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x58 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_L,Enable Set for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1"
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bitfld.long 0x58 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_P,Enable Set for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1"
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bitfld.long 0x58 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_L,Enable Set for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1"
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bitfld.long 0x58 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_P,Enable Set for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1"
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bitfld.long 0x58 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x58 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x58 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x58 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_2,Enable Register 23"
bitfld.long 0x5C 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x5C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x5C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_3,Enable Register 24"
bitfld.long 0x60 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_31,Enable Set for pulse_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x60 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_30,Enable Set for pulse_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x60 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_29,Enable Set for pulse_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x60 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_28,Enable Set for pulse_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x60 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_27,Enable Set for pulse_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x60 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_26,Enable Set for pulse_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x60 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_25,Enable Set for pulse_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x60 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_24,Enable Set for pulse_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x60 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_23,Enable Set for pulse_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x60 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_22,Enable Set for pulse_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x60 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_21,Enable Set for pulse_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x60 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_20,Enable Set for pulse_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x60 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_19,Enable Set for pulse_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x60 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_18,Enable Set for pulse_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x60 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_17,Enable Set for pulse_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x60 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_16,Enable Set for pulse_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x60 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_15,Enable Set for pulse_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x60 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_14,Enable Set for pulse_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x60 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_13,Enable Set for pulse_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x60 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_12,Enable Set for pulse_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x60 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_11,Enable Set for pulse_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x60 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_10,Enable Set for pulse_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x60 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_9,Enable Set for pulse_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x60 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_8,Enable Set for pulse_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x60 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_7,Enable Set for pulse_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x60 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_6,Enable Set for pulse_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x60 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_5,Enable Set for pulse_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x60 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_4,Enable Set for pulse_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x60 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_3,Enable Set for pulse_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x60 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_2,Enable Set for pulse_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x60 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_1,Enable Set for pulse_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x60 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_0,Enable Set for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_4,Enable Register 25"
bitfld.long 0x64 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_31,Enable Set for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x64 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_30,Enable Set for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x64 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_29,Enable Set for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x64 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_28,Enable Set for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x64 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_27,Enable Set for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x64 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_26,Enable Set for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x64 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_25,Enable Set for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x64 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_24,Enable Set for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x64 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_23,Enable Set for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x64 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_22,Enable Set for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x64 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_21,Enable Set for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x64 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_20,Enable Set for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x64 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_19,Enable Set for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x64 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_18,Enable Set for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x64 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_17,Enable Set for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x64 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_16,Enable Set for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
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bitfld.long 0x64 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_15,Enable Set for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
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bitfld.long 0x64 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_14,Enable Set for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
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bitfld.long 0x64 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_13,Enable Set for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
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bitfld.long 0x64 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_12,Enable Set for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
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bitfld.long 0x64 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_11,Enable Set for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
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bitfld.long 0x64 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_10,Enable Set for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
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bitfld.long 0x64 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_9,Enable Set for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
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bitfld.long 0x64 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_8,Enable Set for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
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bitfld.long 0x64 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_7,Enable Set for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x64 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_6,Enable Set for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
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bitfld.long 0x64 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_5,Enable Set for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x64 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_4,Enable Set for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x64 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_3,Enable Set for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x64 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_2,Enable Set for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x64 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_1,Enable Set for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x64 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_0,Enable Set for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_5,Enable Register 26"
bitfld.long 0x68 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x68 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x68 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x68 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x68 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x68 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x68 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x68 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x68 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x68 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x68 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x68 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x68 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_6,Enable Register 27"
bitfld.long 0x6C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_CTM_PULSE,Enable Set for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x6C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_PROT_ERR,Enable Set for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
group.long 0x300++0x6F
line.long 0x00 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_0,Enable Clear Register 0"
bitfld.long 0x00 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_READ_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_BLK_DONE_CLR,Enable Clear for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_READ_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_ROW_DONE_CLR,Enable Clear for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_1,Enable Clear Register 1"
bitfld.long 0x04 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_8_CLR,Enable Clear for level_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_7_CLR,Enable Clear for level_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x04 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_1_CLR,Enable Clear for level_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x04 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for level_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_L_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_P_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_L_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_P_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_2,Enable Clear Register 2"
bitfld.long 0x08 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_3,Enable Clear Register 3"
bitfld.long 0x0C 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x0C 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x0C 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x0C 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x0C 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x0C 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x0C 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x0C 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x0C 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x0C 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x0C 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x0C 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x0C 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x0C 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x0C 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x0C 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x0C 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x0C 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x0C 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x0C 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x0C 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x0C 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_4,Enable Clear Register 4"
bitfld.long 0x10 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x10 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x10 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x10 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x10 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x10 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_5,Enable Clear Register 5"
bitfld.long 0x14 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_6,Enable Clear Register 6"
bitfld.long 0x18 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for level_dmpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x18 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_PROT_ERR_CLR,Enable Clear for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_0,Enable Clear Register 7"
bitfld.long 0x1C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_sde_write_error" "0,1"
newline
bitfld.long 0x1C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_READ_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x1C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x1C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_BLK_DONE_CLR,Enable Clear for level_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x1C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x1C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x1C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_READ_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x1C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x1C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_ROW_DONE_CLR,Enable Clear for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_1,Enable Clear Register 8"
bitfld.long 0x20 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_8_CLR,Enable Clear for level_dmpac_out_1_en_tdone_8" "0,1"
newline
bitfld.long 0x20 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_7_CLR,Enable Clear for level_dmpac_out_1_en_tdone_7" "0,1"
newline
bitfld.long 0x20 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_1_CLR,Enable Clear for level_dmpac_out_1_en_tdone_1" "0,1"
newline
bitfld.long 0x20 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for level_dmpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x20 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_L_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x20 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_P_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x20 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_L_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x20 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_P_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x20 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for level_dmpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x20 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for level_dmpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x20 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x20 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x20 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x20 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_2,Enable Clear Register 9"
bitfld.long 0x24 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x24 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x24 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x24 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_3,Enable Clear Register 10"
bitfld.long 0x28 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x28 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x28 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x28 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x28 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x28 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x28 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_25" "0,1"
newline
bitfld.long 0x28 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x28 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_23" "0,1"
newline
bitfld.long 0x28 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_22" "0,1"
newline
bitfld.long 0x28 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_21" "0,1"
newline
bitfld.long 0x28 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x28 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_19" "0,1"
newline
bitfld.long 0x28 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x28 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x28 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x28 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x28 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_14" "0,1"
newline
bitfld.long 0x28 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x28 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x28 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x28 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_10" "0,1"
newline
bitfld.long 0x28 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x28 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x28 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x28 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x28 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_5" "0,1"
newline
bitfld.long 0x28 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x28 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x28 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_2" "0,1"
newline
bitfld.long 0x28 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_1" "0,1"
newline
bitfld.long 0x28 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_4,Enable Clear Register 11"
bitfld.long 0x2C 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_31" "0,1"
newline
bitfld.long 0x2C 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_30" "0,1"
newline
bitfld.long 0x2C 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_29" "0,1"
newline
bitfld.long 0x2C 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_28" "0,1"
newline
bitfld.long 0x2C 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x2C 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x2C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_25" "0,1"
newline
bitfld.long 0x2C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x2C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x2C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x2C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x2C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x2C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x2C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x2C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x2C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x2C 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x2C 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x2C 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x2C 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x2C 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x2C 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x2C 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x2C 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x2C 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x2C 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x2C 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x2C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x2C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x2C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x2C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x2C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_5,Enable Clear Register 12"
bitfld.long 0x30 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x30 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x30 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x30 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x30 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x30 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x30 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x30 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x30 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x30 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x30 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x30 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x30 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x30 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x30 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x30 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x30 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x30 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x30 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x30 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x30 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x30 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x30 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x30 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x30 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x30 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x30 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x30 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x30 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x30 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x30 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x30 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_6,Enable Clear Register 13"
bitfld.long 0x34 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for level_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x34 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_PROT_ERR_CLR,Enable Clear for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_0,Enable Clear Register 14"
bitfld.long 0x38 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x38 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x38 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x38 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x38 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x38 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_BLK_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x38 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x38 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x38 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x38 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x38 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_ROW_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_1,Enable Clear Register 15"
bitfld.long 0x3C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_8_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x3C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_7_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x3C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x3C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x3C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_L_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x3C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_P_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x3C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_L_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x3C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_P_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x3C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x3C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x3C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x3C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x3C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x3C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_2,Enable Clear Register 16"
bitfld.long 0x40 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x40 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x40 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x40 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_3,Enable Clear Register 17"
bitfld.long 0x44 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x44 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x44 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x44 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x44 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x44 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x44 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x44 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x44 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x44 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x44 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x44 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x44 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x44 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x44 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x44 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x44 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x44 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x44 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x44 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x44 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x44 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x44 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x44 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x44 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x44 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x44 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x44 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x44 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x44 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x44 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x44 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_4,Enable Clear Register 18"
bitfld.long 0x48 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x48 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x48 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x48 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x48 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x48 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x48 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x48 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x48 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x48 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x48 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x48 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x48 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x48 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x48 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x48 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x48 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x48 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x48 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x48 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x48 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x48 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x48 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x48 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x48 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x48 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x48 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x48 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x48 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x48 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x48 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x48 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_5,Enable Clear Register 19"
bitfld.long 0x4C 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x4C 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x4C 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x4C 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x4C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x4C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x4C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x4C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x4C 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x4C 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x4C 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x4C 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x4C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x4C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x4C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x4C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x4C 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x4C 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x4C 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x4C 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x4C 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x4C 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x4C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x4C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x4C 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x4C 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x4C 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x4C 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x4C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x4C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x4C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x4C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_6,Enable Clear Register 20"
bitfld.long 0x50 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x50 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_PROT_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_0,Enable Clear Register 21"
bitfld.long 0x54 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x54 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x54 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x54 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x54 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x54 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x54 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_write_error" "0,1"
newline
bitfld.long 0x54 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x54 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x54 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_BLK_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x54 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x54 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x54 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x54 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x54 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_ROW_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_1,Enable Clear Register 22"
bitfld.long 0x58 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_8_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_7_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x58 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x58 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_L_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1"
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bitfld.long 0x58 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_P_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1"
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bitfld.long 0x58 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_L_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1"
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bitfld.long 0x58 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_P_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1"
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bitfld.long 0x58 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x58 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x58 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x58 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_2,Enable Clear Register 23"
bitfld.long 0x5C 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x5C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x5C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_3,Enable Clear Register 24"
bitfld.long 0x60 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x60 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x60 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x60 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x60 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x60 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x60 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x60 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x60 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x60 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x60 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x60 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x60 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x60 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x60 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x60 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x60 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x60 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x60 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x60 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x60 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x60 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x60 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x60 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x60 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x60 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x60 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x60 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x60 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x60 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x60 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x60 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_4,Enable Clear Register 25"
bitfld.long 0x64 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x64 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x64 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x64 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x64 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x64 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x64 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x64 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x64 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x64 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x64 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x64 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x64 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x64 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x64 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x64 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x64 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x64 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x64 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x64 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x64 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x64 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x64 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x64 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x64 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x64 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x64 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x64 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x64 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x64 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x64 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x64 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_5,Enable Clear Register 26"
bitfld.long 0x68 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x68 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x68 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x68 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x68 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x68 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x68 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x68 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x68 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x68 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x68 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x68 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x68 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_6,Enable Clear Register 27"
bitfld.long 0x6C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x6C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_PROT_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
group.long 0x500++0x6F
line.long 0x00 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_0,Status Register 0"
bitfld.long 0x00 25. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x00 24. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x00 23. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x00 22. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_DMPAC_OUT_0_SDE_WRITE_ERROR,Status write 1 to set for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "STATUS_LEVEL_DMPAC_OUT_0_SDE_READ_ERROR,Status write 1 to set for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_DMPAC_OUT_0_SDE_FRAME_DONE,Status write 1 to set for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "STATUS_LEVEL_DMPAC_OUT_0_SDE_BLK_DONE,Status write 1 to set for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "STATUS_LEVEL_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_DMPAC_OUT_0_DOF_WRITE_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_DMPAC_OUT_0_DOF_READ_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_DMPAC_OUT_0_DOF_FRAME_DONE,Status write 1 to set for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_DMPAC_OUT_0_DOF_ROW_DONE,Status write 1 to set for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_1,Status Register 1"
bitfld.long 0x04 27. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_8,Status write 1 to set for level_dmpac_out_0_en_tdone_8" "0,1"
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bitfld.long 0x04 26. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_7,Status write 1 to set for level_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x04 25. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_1,Status write 1 to set for level_dmpac_out_0_en_tdone_1" "0,1"
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bitfld.long 0x04 24. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_0,Status write 1 to set for level_dmpac_out_0_en_tdone_0" "0,1"
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rbitfld.long 0x04 19. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_1_L,Status for level_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
rbitfld.long 0x04 18. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_1_P,Status for level_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
rbitfld.long 0x04 17. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_0_L,Status for level_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
rbitfld.long 0x04 16. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_0_P,Status for level_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x04 9. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_2,Status Register 2"
bitfld.long 0x08 3. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x08 0. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_3,Status Register 3"
bitfld.long 0x0C 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_31,Status write 1 to set for level_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x0C 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_30,Status write 1 to set for level_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x0C 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_29,Status write 1 to set for level_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x0C 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_28,Status write 1 to set for level_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x0C 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_27,Status write 1 to set for level_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x0C 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_26,Status write 1 to set for level_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x0C 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_25,Status write 1 to set for level_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x0C 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_24,Status write 1 to set for level_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x0C 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_23,Status write 1 to set for level_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x0C 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_22,Status write 1 to set for level_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x0C 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_21,Status write 1 to set for level_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x0C 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_20,Status write 1 to set for level_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x0C 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_19,Status write 1 to set for level_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x0C 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_18,Status write 1 to set for level_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x0C 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_17,Status write 1 to set for level_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x0C 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_16,Status write 1 to set for level_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x0C 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_15,Status write 1 to set for level_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x0C 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_14,Status write 1 to set for level_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x0C 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_13,Status write 1 to set for level_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x0C 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_12,Status write 1 to set for level_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x0C 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_11,Status write 1 to set for level_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x0C 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_10,Status write 1 to set for level_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x0C 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_9,Status write 1 to set for level_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x0C 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_8,Status write 1 to set for level_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x0C 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_7,Status write 1 to set for level_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x0C 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_6,Status write 1 to set for level_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x0C 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_5,Status write 1 to set for level_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x0C 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_4,Status write 1 to set for level_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x0C 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_3,Status write 1 to set for level_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x0C 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_2,Status write 1 to set for level_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x0C 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_1,Status write 1 to set for level_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x0C 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_0,Status write 1 to set for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_4,Status Register 4"
bitfld.long 0x10 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_31,Status write 1 to set for level_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x10 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_30,Status write 1 to set for level_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x10 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_29,Status write 1 to set for level_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x10 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_28,Status write 1 to set for level_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x10 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_27,Status write 1 to set for level_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x10 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_26,Status write 1 to set for level_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x10 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_25,Status write 1 to set for level_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x10 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_24,Status write 1 to set for level_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x10 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_23,Status write 1 to set for level_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x10 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_22,Status write 1 to set for level_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x10 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_21,Status write 1 to set for level_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x10 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_20,Status write 1 to set for level_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x10 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_19,Status write 1 to set for level_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x10 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_18,Status write 1 to set for level_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x10 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_17,Status write 1 to set for level_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x10 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_16,Status write 1 to set for level_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x10 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_15,Status write 1 to set for level_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x10 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_14,Status write 1 to set for level_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x10 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_13,Status write 1 to set for level_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x10 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_12,Status write 1 to set for level_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x10 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_11,Status write 1 to set for level_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x10 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_10,Status write 1 to set for level_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x10 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_9,Status write 1 to set for level_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x10 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_8,Status write 1 to set for level_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x10 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_7,Status write 1 to set for level_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x10 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_6,Status write 1 to set for level_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_5,Status write 1 to set for level_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_4,Status write 1 to set for level_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x10 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_3,Status write 1 to set for level_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x10 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_2,Status write 1 to set for level_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x10 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_1,Status write 1 to set for level_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x10 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_0,Status write 1 to set for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_5,Status Register 5"
bitfld.long 0x14 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x14 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x14 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x14 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x14 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x14 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x14 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x14 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x14 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_6,Status Register 6"
bitfld.long 0x18 1. "STATUS_LEVEL_DMPAC_OUT_0_CTM_PULSE,Status write 1 to set for level_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x18 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_PROT_ERR,Status write 1 to set for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_0,Status Register 7"
bitfld.long 0x1C 25. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x1C 24. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x1C 23. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x1C 22. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x1C 21. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x1C 20. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x1C 19. "STATUS_LEVEL_DMPAC_OUT_1_SDE_WRITE_ERROR,Status write 1 to set for level_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x1C 18. "STATUS_LEVEL_DMPAC_OUT_1_SDE_READ_ERROR,Status write 1 to set for level_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x1C 17. "STATUS_LEVEL_DMPAC_OUT_1_SDE_FRAME_DONE,Status write 1 to set for level_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x1C 16. "STATUS_LEVEL_DMPAC_OUT_1_SDE_BLK_DONE,Status write 1 to set for level_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x1C 4. "STATUS_LEVEL_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x1C 3. "STATUS_LEVEL_DMPAC_OUT_1_DOF_WRITE_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x1C 2. "STATUS_LEVEL_DMPAC_OUT_1_DOF_READ_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x1C 1. "STATUS_LEVEL_DMPAC_OUT_1_DOF_FRAME_DONE,Status write 1 to set for level_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x1C 0. "STATUS_LEVEL_DMPAC_OUT_1_DOF_ROW_DONE,Status write 1 to set for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_1,Status Register 8"
bitfld.long 0x20 27. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_8,Status write 1 to set for level_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x20 26. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_7,Status write 1 to set for level_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x20 25. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_1,Status write 1 to set for level_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x20 24. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_0,Status write 1 to set for level_dmpac_out_1_en_tdone_0" "0,1"
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rbitfld.long 0x20 19. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_1_L,Status for level_dmpac_out_1_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x20 18. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_1_P,Status for level_dmpac_out_1_en_spare_pend_1_p" "0,1"
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rbitfld.long 0x20 17. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_0_L,Status for level_dmpac_out_1_en_spare_pend_0_l" "0,1"
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rbitfld.long 0x20 16. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_0_P,Status for level_dmpac_out_1_en_spare_pend_0_p" "0,1"
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bitfld.long 0x20 9. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for level_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x20 8. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for level_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x20 3. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for level_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x20 2. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for level_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x20 1. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for level_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x20 0. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_2,Status Register 9"
bitfld.long 0x24 3. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x24 2. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x24 1. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x24 0. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_3,Status Register 10"
bitfld.long 0x28 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_31,Status write 1 to set for level_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x28 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_30,Status write 1 to set for level_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x28 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_29,Status write 1 to set for level_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x28 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_28,Status write 1 to set for level_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x28 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_27,Status write 1 to set for level_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x28 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_26,Status write 1 to set for level_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x28 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_25,Status write 1 to set for level_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x28 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_24,Status write 1 to set for level_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x28 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_23,Status write 1 to set for level_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x28 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_22,Status write 1 to set for level_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x28 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_21,Status write 1 to set for level_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x28 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_20,Status write 1 to set for level_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x28 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_19,Status write 1 to set for level_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x28 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_18,Status write 1 to set for level_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x28 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_17,Status write 1 to set for level_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x28 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_16,Status write 1 to set for level_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x28 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_15,Status write 1 to set for level_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x28 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_14,Status write 1 to set for level_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x28 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_13,Status write 1 to set for level_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x28 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_12,Status write 1 to set for level_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x28 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_11,Status write 1 to set for level_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x28 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_10,Status write 1 to set for level_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x28 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_9,Status write 1 to set for level_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x28 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_8,Status write 1 to set for level_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x28 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_7,Status write 1 to set for level_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x28 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_6,Status write 1 to set for level_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x28 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_5,Status write 1 to set for level_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x28 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_4,Status write 1 to set for level_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x28 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_3,Status write 1 to set for level_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x28 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_2,Status write 1 to set for level_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x28 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_1,Status write 1 to set for level_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x28 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_0,Status write 1 to set for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_4,Status Register 11"
bitfld.long 0x2C 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_31,Status write 1 to set for level_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x2C 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_30,Status write 1 to set for level_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x2C 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_29,Status write 1 to set for level_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x2C 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_28,Status write 1 to set for level_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x2C 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_27,Status write 1 to set for level_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x2C 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_26,Status write 1 to set for level_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x2C 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_25,Status write 1 to set for level_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x2C 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_24,Status write 1 to set for level_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x2C 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_23,Status write 1 to set for level_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x2C 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_22,Status write 1 to set for level_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x2C 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_21,Status write 1 to set for level_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x2C 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_20,Status write 1 to set for level_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x2C 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_19,Status write 1 to set for level_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x2C 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_18,Status write 1 to set for level_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x2C 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_17,Status write 1 to set for level_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x2C 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_16,Status write 1 to set for level_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x2C 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_15,Status write 1 to set for level_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x2C 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_14,Status write 1 to set for level_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x2C 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_13,Status write 1 to set for level_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x2C 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_12,Status write 1 to set for level_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x2C 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_11,Status write 1 to set for level_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x2C 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_10,Status write 1 to set for level_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x2C 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_9,Status write 1 to set for level_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x2C 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_8,Status write 1 to set for level_dmpac_out_1_en_dru_complete_8" "0,1"
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bitfld.long 0x2C 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_7,Status write 1 to set for level_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x2C 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_6,Status write 1 to set for level_dmpac_out_1_en_dru_complete_6" "0,1"
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bitfld.long 0x2C 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_5,Status write 1 to set for level_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x2C 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_4,Status write 1 to set for level_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x2C 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_3,Status write 1 to set for level_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x2C 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_2,Status write 1 to set for level_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x2C 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_1,Status write 1 to set for level_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x2C 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_0,Status write 1 to set for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_5,Status Register 12"
bitfld.long 0x30 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x30 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x30 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x30 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x30 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x30 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x30 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x30 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x30 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x30 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x30 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x30 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x30 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x30 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x30 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x30 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x30 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x30 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x30 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x30 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x30 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x30 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x30 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x30 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x30 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x30 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x30 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x30 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x30 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x30 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x30 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x30 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_6,Status Register 13"
bitfld.long 0x34 1. "STATUS_LEVEL_DMPAC_OUT_1_CTM_PULSE,Status write 1 to set for level_dmpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x34 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_PROT_ERR,Status write 1 to set for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_0,Status Register 14"
bitfld.long 0x38 25. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x38 24. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x38 23. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x38 22. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x38 21. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x38 20. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x38 19. "STATUS_PULSE_DMPAC_OUT_0_SDE_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_sde_write_error" "0,1"
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bitfld.long 0x38 18. "STATUS_PULSE_DMPAC_OUT_0_SDE_READ_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_sde_read_error" "0,1"
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bitfld.long 0x38 17. "STATUS_PULSE_DMPAC_OUT_0_SDE_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
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bitfld.long 0x38 16. "STATUS_PULSE_DMPAC_OUT_0_SDE_BLK_DONE,Status write 1 to set for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
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bitfld.long 0x38 4. "STATUS_PULSE_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x38 3. "STATUS_PULSE_DMPAC_OUT_0_DOF_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_write_error" "0,1"
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bitfld.long 0x38 2. "STATUS_PULSE_DMPAC_OUT_0_DOF_READ_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_read_error" "0,1"
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bitfld.long 0x38 1. "STATUS_PULSE_DMPAC_OUT_0_DOF_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
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bitfld.long 0x38 0. "STATUS_PULSE_DMPAC_OUT_0_DOF_ROW_DONE,Status write 1 to set for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_1,Status Register 15"
bitfld.long 0x3C 27. "STATUS_PULSE_DMPAC_OUT_0_TDONE_8,Status write 1 to set for pulse_dmpac_out_0_en_tdone_8" "0,1"
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bitfld.long 0x3C 26. "STATUS_PULSE_DMPAC_OUT_0_TDONE_7,Status write 1 to set for pulse_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x3C 25. "STATUS_PULSE_DMPAC_OUT_0_TDONE_1,Status write 1 to set for pulse_dmpac_out_0_en_tdone_1" "0,1"
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bitfld.long 0x3C 24. "STATUS_PULSE_DMPAC_OUT_0_TDONE_0,Status write 1 to set for pulse_dmpac_out_0_en_tdone_0" "0,1"
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rbitfld.long 0x3C 19. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_1_L,Status for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x3C 18. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_1_P,Status for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1"
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rbitfld.long 0x3C 17. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_0_L,Status for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1"
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rbitfld.long 0x3C 16. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_0_P,Status for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1"
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bitfld.long 0x3C 9. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x3C 8. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0x3C 3. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x3C 2. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x3C 1. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x3C 0. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_2,Status Register 16"
bitfld.long 0x40 3. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x40 2. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x40 1. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x40 0. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_3,Status Register 17"
bitfld.long 0x44 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x44 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x44 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x44 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x44 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x44 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_26" "0,1"
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bitfld.long 0x44 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x44 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x44 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_23" "0,1"
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bitfld.long 0x44 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x44 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_21" "0,1"
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bitfld.long 0x44 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x44 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x44 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x44 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x44 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x44 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x44 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x44 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x44 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x44 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x44 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x44 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x44 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x44 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x44 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x44 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x44 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x44 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x44 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x44 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x44 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_4,Status Register 18"
bitfld.long 0x48 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x48 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x48 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x48 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
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bitfld.long 0x48 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
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bitfld.long 0x48 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
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bitfld.long 0x48 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
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bitfld.long 0x48 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
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bitfld.long 0x48 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
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bitfld.long 0x48 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
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bitfld.long 0x48 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
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bitfld.long 0x48 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
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bitfld.long 0x48 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
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bitfld.long 0x48 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
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bitfld.long 0x48 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
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bitfld.long 0x48 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
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bitfld.long 0x48 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
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bitfld.long 0x48 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
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bitfld.long 0x48 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
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bitfld.long 0x48 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
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bitfld.long 0x48 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
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bitfld.long 0x48 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
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bitfld.long 0x48 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
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bitfld.long 0x48 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
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bitfld.long 0x48 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
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bitfld.long 0x48 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
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bitfld.long 0x48 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
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bitfld.long 0x48 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
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bitfld.long 0x48 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
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bitfld.long 0x48 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
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bitfld.long 0x48 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
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bitfld.long 0x48 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_5,Status Register 19"
bitfld.long 0x4C 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x4C 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x4C 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x4C 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x4C 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x4C 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x4C 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x4C 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x4C 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x4C 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x4C 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x4C 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x4C 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x4C 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x4C 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x4C 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x4C 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x4C 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x4C 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x4C 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x4C 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x4C 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x4C 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x4C 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x4C 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x4C 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x4C 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x4C 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x4C 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x4C 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x4C 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x4C 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_6,Status Register 20"
bitfld.long 0x50 1. "STATUS_PULSE_DMPAC_OUT_0_CTM_PULSE,Status write 1 to set for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x50 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_PROT_ERR,Status write 1 to set for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_0,Status Register 21"
bitfld.long 0x54 25. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x54 24. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x54 23. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x54 22. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x54 21. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x54 20. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x54 19. "STATUS_PULSE_DMPAC_OUT_1_SDE_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x54 18. "STATUS_PULSE_DMPAC_OUT_1_SDE_READ_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x54 17. "STATUS_PULSE_DMPAC_OUT_1_SDE_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x54 16. "STATUS_PULSE_DMPAC_OUT_1_SDE_BLK_DONE,Status write 1 to set for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x54 4. "STATUS_PULSE_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x54 3. "STATUS_PULSE_DMPAC_OUT_1_DOF_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x54 2. "STATUS_PULSE_DMPAC_OUT_1_DOF_READ_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x54 1. "STATUS_PULSE_DMPAC_OUT_1_DOF_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x54 0. "STATUS_PULSE_DMPAC_OUT_1_DOF_ROW_DONE,Status write 1 to set for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_1,Status Register 22"
bitfld.long 0x58 27. "STATUS_PULSE_DMPAC_OUT_1_TDONE_8,Status write 1 to set for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "STATUS_PULSE_DMPAC_OUT_1_TDONE_7,Status write 1 to set for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "STATUS_PULSE_DMPAC_OUT_1_TDONE_1,Status write 1 to set for pulse_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x58 24. "STATUS_PULSE_DMPAC_OUT_1_TDONE_0,Status write 1 to set for pulse_dmpac_out_1_en_tdone_0" "0,1"
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rbitfld.long 0x58 19. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_1_L,Status for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x58 18. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_1_P,Status for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1"
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rbitfld.long 0x58 17. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_0_L,Status for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1"
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rbitfld.long 0x58 16. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_0_P,Status for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1"
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bitfld.long 0x58 9. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x58 8. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x58 3. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x58 0. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_2,Status Register 23"
bitfld.long 0x5C 3. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x5C 1. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x5C 0. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_3,Status Register 24"
bitfld.long 0x60 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x60 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x60 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x60 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x60 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x60 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x60 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x60 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x60 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x60 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x60 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x60 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x60 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x60 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x60 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x60 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x60 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x60 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_14" "0,1"
newline
bitfld.long 0x60 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x60 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x60 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x60 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_10" "0,1"
newline
bitfld.long 0x60 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x60 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x60 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x60 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x60 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_5" "0,1"
newline
bitfld.long 0x60 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x60 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x60 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_2" "0,1"
newline
bitfld.long 0x60 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_1" "0,1"
newline
bitfld.long 0x60 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_4,Status Register 25"
bitfld.long 0x64 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
newline
bitfld.long 0x64 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
newline
bitfld.long 0x64 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
newline
bitfld.long 0x64 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
newline
bitfld.long 0x64 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x64 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x64 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
newline
bitfld.long 0x64 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x64 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x64 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x64 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x64 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x64 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x64 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x64 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x64 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x64 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x64 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x64 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x64 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x64 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x64 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x64 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x64 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x64 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x64 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x64 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x64 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x64 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x64 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x64 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x64 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_5,Status Register 26"
bitfld.long 0x68 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x68 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x68 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x68 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x68 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x68 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x68 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x68 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x68 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x68 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x68 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x68 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x68 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_6,Status Register 27"
bitfld.long 0x6C 1. "STATUS_PULSE_DMPAC_OUT_1_CTM_PULSE,Status write 1 to set for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x6C 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_PROT_ERR,Status write 1 to set for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
group.long 0x700++0x6F
line.long 0x00 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_0,Status Clear Register 0"
bitfld.long 0x00 25. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 24. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x00 22. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_DMPAC_OUT_0_SDE_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "STATUS_LEVEL_DMPAC_OUT_0_SDE_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_DMPAC_OUT_0_SDE_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "STATUS_LEVEL_DMPAC_OUT_0_SDE_BLK_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "STATUS_LEVEL_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_DMPAC_OUT_0_DOF_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_DMPAC_OUT_0_DOF_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_DMPAC_OUT_0_DOF_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_DMPAC_OUT_0_DOF_ROW_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_1,Status Clear Register 1"
bitfld.long 0x04 27. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x04 26. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x04 25. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x04 24. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x04 9. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_2,Status Clear Register 2"
bitfld.long 0x08 3. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_3,Status Clear Register 3"
bitfld.long 0x0C 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x0C 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x0C 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x0C 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x0C 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x0C 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_26" "0,1"
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bitfld.long 0x0C 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x0C 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x0C 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_23" "0,1"
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bitfld.long 0x0C 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x0C 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_21" "0,1"
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bitfld.long 0x0C 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_20" "0,1"
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bitfld.long 0x0C 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_19" "0,1"
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bitfld.long 0x0C 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_18" "0,1"
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bitfld.long 0x0C 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_17" "0,1"
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bitfld.long 0x0C 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_16" "0,1"
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bitfld.long 0x0C 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_15" "0,1"
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bitfld.long 0x0C 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_14" "0,1"
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bitfld.long 0x0C 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_13" "0,1"
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bitfld.long 0x0C 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_12" "0,1"
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bitfld.long 0x0C 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_11" "0,1"
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bitfld.long 0x0C 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_10" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_9" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_8" "0,1"
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bitfld.long 0x0C 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_7" "0,1"
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bitfld.long 0x0C 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_6" "0,1"
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bitfld.long 0x0C 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_5" "0,1"
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bitfld.long 0x0C 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_4" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_3" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_2" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_4,Status Clear Register 4"
bitfld.long 0x10 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_31" "0,1"
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bitfld.long 0x10 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_30" "0,1"
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bitfld.long 0x10 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_29" "0,1"
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bitfld.long 0x10 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_28" "0,1"
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bitfld.long 0x10 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_27" "0,1"
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bitfld.long 0x10 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_26" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_25" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_24" "0,1"
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bitfld.long 0x10 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_23" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_22" "0,1"
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bitfld.long 0x10 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_21" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_20" "0,1"
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bitfld.long 0x10 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_19" "0,1"
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bitfld.long 0x10 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_18" "0,1"
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bitfld.long 0x10 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_17" "0,1"
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bitfld.long 0x10 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_16" "0,1"
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bitfld.long 0x10 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_15" "0,1"
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bitfld.long 0x10 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_14" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_13" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_12" "0,1"
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bitfld.long 0x10 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_11" "0,1"
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bitfld.long 0x10 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_10" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_9" "0,1"
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bitfld.long 0x10 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_8" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_7" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_6" "0,1"
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bitfld.long 0x10 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_5" "0,1"
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bitfld.long 0x10 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_5,Status Clear Register 5"
bitfld.long 0x14 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x14 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x14 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x14 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x14 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x14 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x14 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x14 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_6,Status Clear Register 6"
bitfld.long 0x18 1. "STATUS_LEVEL_DMPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for level_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x18 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_PROT_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_0,Status Clear Register 7"
bitfld.long 0x1C 25. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x1C 24. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x1C 23. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x1C 22. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x1C 21. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x1C 20. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x1C 19. "STATUS_LEVEL_DMPAC_OUT_1_SDE_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x1C 18. "STATUS_LEVEL_DMPAC_OUT_1_SDE_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x1C 17. "STATUS_LEVEL_DMPAC_OUT_1_SDE_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x1C 16. "STATUS_LEVEL_DMPAC_OUT_1_SDE_BLK_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x1C 4. "STATUS_LEVEL_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x1C 3. "STATUS_LEVEL_DMPAC_OUT_1_DOF_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x1C 2. "STATUS_LEVEL_DMPAC_OUT_1_DOF_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x1C 1. "STATUS_LEVEL_DMPAC_OUT_1_DOF_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x1C 0. "STATUS_LEVEL_DMPAC_OUT_1_DOF_ROW_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_1,Status Clear Register 8"
bitfld.long 0x20 27. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x20 26. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x20 25. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x20 24. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x20 9. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x20 8. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x20 3. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x20 2. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x20 1. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x20 0. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_2,Status Clear Register 9"
bitfld.long 0x24 3. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x24 2. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x24 1. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x24 0. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_3,Status Clear Register 10"
bitfld.long 0x28 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x28 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x28 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x28 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x28 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x28 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x28 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x28 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x28 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x28 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x28 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x28 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x28 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x28 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x28 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x28 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x28 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x28 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x28 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x28 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x28 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x28 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x28 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x28 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x28 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x28 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x28 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x28 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x28 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x28 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x28 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x28 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_4,Status Clear Register 11"
bitfld.long 0x2C 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x2C 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x2C 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x2C 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x2C 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x2C 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x2C 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x2C 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x2C 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x2C 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x2C 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x2C 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x2C 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x2C 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x2C 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x2C 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_16" "0,1"
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bitfld.long 0x2C 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_15" "0,1"
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bitfld.long 0x2C 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_14" "0,1"
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bitfld.long 0x2C 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_13" "0,1"
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bitfld.long 0x2C 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_12" "0,1"
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bitfld.long 0x2C 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_11" "0,1"
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bitfld.long 0x2C 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_10" "0,1"
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bitfld.long 0x2C 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_9" "0,1"
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bitfld.long 0x2C 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_8" "0,1"
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bitfld.long 0x2C 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x2C 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_6" "0,1"
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bitfld.long 0x2C 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x2C 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x2C 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x2C 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x2C 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x2C 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_5,Status Clear Register 12"
bitfld.long 0x30 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x30 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x30 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x30 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x30 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x30 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x30 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x30 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x30 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x30 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x30 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x30 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x30 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x30 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x30 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x30 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x30 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x30 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x30 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x30 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x30 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x30 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x30 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x30 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x30 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x30 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x30 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x30 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x30 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x30 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x30 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x30 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_6,Status Clear Register 13"
bitfld.long 0x34 1. "STATUS_LEVEL_DMPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for level_dmpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x34 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_PROT_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_0,Status Clear Register 14"
bitfld.long 0x38 25. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x38 24. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x38 23. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x38 22. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x38 21. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x38 20. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x38 19. "STATUS_PULSE_DMPAC_OUT_0_SDE_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_write_error" "0,1"
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bitfld.long 0x38 18. "STATUS_PULSE_DMPAC_OUT_0_SDE_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_read_error" "0,1"
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bitfld.long 0x38 17. "STATUS_PULSE_DMPAC_OUT_0_SDE_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
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bitfld.long 0x38 16. "STATUS_PULSE_DMPAC_OUT_0_SDE_BLK_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
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bitfld.long 0x38 4. "STATUS_PULSE_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x38 3. "STATUS_PULSE_DMPAC_OUT_0_DOF_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_write_error" "0,1"
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bitfld.long 0x38 2. "STATUS_PULSE_DMPAC_OUT_0_DOF_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_read_error" "0,1"
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bitfld.long 0x38 1. "STATUS_PULSE_DMPAC_OUT_0_DOF_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
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bitfld.long 0x38 0. "STATUS_PULSE_DMPAC_OUT_0_DOF_ROW_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_1,Status Clear Register 15"
bitfld.long 0x3C 27. "STATUS_PULSE_DMPAC_OUT_0_TDONE_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_8" "0,1"
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bitfld.long 0x3C 26. "STATUS_PULSE_DMPAC_OUT_0_TDONE_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x3C 25. "STATUS_PULSE_DMPAC_OUT_0_TDONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_1" "0,1"
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bitfld.long 0x3C 24. "STATUS_PULSE_DMPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0x3C 9. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x3C 8. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0x3C 3. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x3C 2. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x3C 1. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x3C 0. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_2,Status Clear Register 16"
bitfld.long 0x40 3. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x40 2. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x40 1. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x40 0. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_3,Status Clear Register 17"
bitfld.long 0x44 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x44 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x44 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x44 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x44 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x44 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_26" "0,1"
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bitfld.long 0x44 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x44 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x44 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_23" "0,1"
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bitfld.long 0x44 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x44 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_21" "0,1"
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bitfld.long 0x44 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_20" "0,1"
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bitfld.long 0x44 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_19" "0,1"
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bitfld.long 0x44 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_18" "0,1"
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bitfld.long 0x44 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_17" "0,1"
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bitfld.long 0x44 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_16" "0,1"
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bitfld.long 0x44 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_15" "0,1"
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bitfld.long 0x44 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_14" "0,1"
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bitfld.long 0x44 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_13" "0,1"
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bitfld.long 0x44 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_12" "0,1"
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bitfld.long 0x44 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_11" "0,1"
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bitfld.long 0x44 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_10" "0,1"
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bitfld.long 0x44 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_9" "0,1"
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bitfld.long 0x44 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_8" "0,1"
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bitfld.long 0x44 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_7" "0,1"
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bitfld.long 0x44 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_6" "0,1"
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bitfld.long 0x44 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_5" "0,1"
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bitfld.long 0x44 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_4" "0,1"
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bitfld.long 0x44 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_3" "0,1"
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bitfld.long 0x44 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_2" "0,1"
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bitfld.long 0x44 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_1" "0,1"
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bitfld.long 0x44 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_4,Status Clear Register 18"
bitfld.long 0x48 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
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bitfld.long 0x48 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
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bitfld.long 0x48 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
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bitfld.long 0x48 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
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bitfld.long 0x48 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
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bitfld.long 0x48 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
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bitfld.long 0x48 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
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bitfld.long 0x48 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
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bitfld.long 0x48 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
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bitfld.long 0x48 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
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bitfld.long 0x48 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
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bitfld.long 0x48 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
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bitfld.long 0x48 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
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bitfld.long 0x48 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
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bitfld.long 0x48 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
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bitfld.long 0x48 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
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bitfld.long 0x48 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
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bitfld.long 0x48 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
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bitfld.long 0x48 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
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bitfld.long 0x48 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
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bitfld.long 0x48 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
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bitfld.long 0x48 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
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bitfld.long 0x48 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
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bitfld.long 0x48 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
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bitfld.long 0x48 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
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bitfld.long 0x48 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
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bitfld.long 0x48 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
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bitfld.long 0x48 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
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bitfld.long 0x48 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
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bitfld.long 0x48 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
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bitfld.long 0x48 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
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bitfld.long 0x48 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_5,Status Clear Register 19"
bitfld.long 0x4C 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x4C 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x4C 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x4C 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x4C 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x4C 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x4C 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x4C 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x4C 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x4C 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x4C 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x4C 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x4C 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x4C 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x4C 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x4C 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x4C 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x4C 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x4C 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x4C 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x4C 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x4C 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x4C 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x4C 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x4C 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x4C 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x4C 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x4C 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x4C 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x4C 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x4C 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x4C 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_6,Status Clear Register 20"
bitfld.long 0x50 1. "STATUS_PULSE_DMPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x50 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_PROT_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_0,Status Clear Register 21"
bitfld.long 0x54 25. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x54 24. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x54 23. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x54 22. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x54 21. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x54 20. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x54 19. "STATUS_PULSE_DMPAC_OUT_1_SDE_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x54 18. "STATUS_PULSE_DMPAC_OUT_1_SDE_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x54 17. "STATUS_PULSE_DMPAC_OUT_1_SDE_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x54 16. "STATUS_PULSE_DMPAC_OUT_1_SDE_BLK_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x54 4. "STATUS_PULSE_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x54 3. "STATUS_PULSE_DMPAC_OUT_1_DOF_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x54 2. "STATUS_PULSE_DMPAC_OUT_1_DOF_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x54 1. "STATUS_PULSE_DMPAC_OUT_1_DOF_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x54 0. "STATUS_PULSE_DMPAC_OUT_1_DOF_ROW_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_1,Status Clear Register 22"
bitfld.long 0x58 27. "STATUS_PULSE_DMPAC_OUT_1_TDONE_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "STATUS_PULSE_DMPAC_OUT_1_TDONE_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "STATUS_PULSE_DMPAC_OUT_1_TDONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x58 24. "STATUS_PULSE_DMPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x58 9. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x58 8. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x58 3. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x58 0. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_2,Status Clear Register 23"
bitfld.long 0x5C 3. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x5C 1. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x5C 0. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_3,Status Clear Register 24"
bitfld.long 0x60 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x60 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x60 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x60 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x60 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x60 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x60 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x60 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x60 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x60 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x60 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x60 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x60 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x60 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x60 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x60 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x60 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x60 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x60 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x60 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x60 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x60 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x60 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x60 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x60 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x60 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x60 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x60 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x60 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x60 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x60 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x60 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_4,Status Clear Register 25"
bitfld.long 0x64 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x64 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x64 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x64 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x64 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x64 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x64 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x64 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x64 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x64 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x64 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x64 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x64 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x64 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x64 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x64 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x64 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x64 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x64 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x64 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x64 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x64 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x64 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x64 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x64 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x64 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x64 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x64 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x64 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x64 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x64 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x64 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_5,Status Clear Register 26"
bitfld.long 0x68 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x68 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x68 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x68 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x68 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x68 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x68 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x68 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x68 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x68 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x68 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x68 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x68 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_6,Status Clear Register 27"
bitfld.long 0x6C 1. "STATUS_PULSE_DMPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x6C 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_PROT_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0xA88)++0x03
line.long 0x00 "DMPAC_INTD_INTR_VECTOR_REG_PULSE_DMPAC_OUT_$1,Interrupt Vector for pulse_dmpac_out_0"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0xA80)++0x03
line.long 0x00 "DMPAC_INTD_INTR_VECTOR_REG_LEVEL_DMPAC_OUT_$1,Interrupt Vector for level_dmpac_out_0"
repeat.end
tree.end
tree.end
tree "DMPAC_CP_INTD"
tree "DMPAC_TOP_MAIN_0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS"
base ad:0xF401000
rgroup.long 0x00++0x03
line.long 0x00 "DMPAC_INTD_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,MajorDMPAC_INTD_REVISION" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,CustomDMPAC_INTD_REVISION" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,MinorDMPAC_INTD_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "DMPAC_INTD_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "DMPAC_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x6F
line.long 0x00 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_0,Enable Register 0"
bitfld.long 0x00 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR,Enable Set for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR,Enable Set for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT,Enable Set for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR,Enable Set for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR,Enable Set for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT,Enable Set for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_WRITE_ERROR,Enable Set for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_READ_ERROR,Enable Set for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_FRAME_DONE,Enable Set for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_BLK_DONE,Enable Set for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_WRITE_ERROR,Enable Set for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_READ_ERROR,Enable Set for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_FRAME_DONE,Enable Set for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_ROW_DONE,Enable Set for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_1,Enable Register 1"
bitfld.long 0x04 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_8,Enable Set for level_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_7,Enable Set for level_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x04 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_1,Enable Set for level_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x04 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_0,Enable Set for level_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_L,Enable Set for level_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_P,Enable Set for level_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_L,Enable Set for level_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_P,Enable Set for level_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_2,Enable Register 2"
bitfld.long 0x08 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_3,Enable Register 3"
bitfld.long 0x0C 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_31,Enable Set for level_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x0C 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_30,Enable Set for level_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x0C 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_29,Enable Set for level_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x0C 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_28,Enable Set for level_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x0C 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_27,Enable Set for level_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x0C 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_26,Enable Set for level_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x0C 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_25,Enable Set for level_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x0C 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_24,Enable Set for level_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x0C 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_23,Enable Set for level_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x0C 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_22,Enable Set for level_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x0C 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_21,Enable Set for level_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x0C 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_20,Enable Set for level_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_19,Enable Set for level_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x0C 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_18,Enable Set for level_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x0C 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_17,Enable Set for level_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x0C 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_16,Enable Set for level_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_15,Enable Set for level_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x0C 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_14,Enable Set for level_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x0C 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_13,Enable Set for level_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x0C 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_12,Enable Set for level_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_11,Enable Set for level_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x0C 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_10,Enable Set for level_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_9,Enable Set for level_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_8,Enable Set for level_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_7,Enable Set for level_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x0C 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_6,Enable Set for level_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x0C 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_5,Enable Set for level_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x0C 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_4,Enable Set for level_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_3,Enable Set for level_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_2,Enable Set for level_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_1,Enable Set for level_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_0,Enable Set for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_4,Enable Register 4"
bitfld.long 0x10 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_31,Enable Set for level_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x10 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_30,Enable Set for level_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x10 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_29,Enable Set for level_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_28,Enable Set for level_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_27,Enable Set for level_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x10 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_26,Enable Set for level_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_25,Enable Set for level_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_24,Enable Set for level_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_23,Enable Set for level_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_22,Enable Set for level_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x10 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_21,Enable Set for level_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_20,Enable Set for level_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_19,Enable Set for level_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_18,Enable Set for level_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_17,Enable Set for level_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_16,Enable Set for level_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_15,Enable Set for level_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_14,Enable Set for level_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_13,Enable Set for level_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_12,Enable Set for level_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_11,Enable Set for level_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_10,Enable Set for level_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_9,Enable Set for level_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x10 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_8,Enable Set for level_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_7,Enable Set for level_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_6,Enable Set for level_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_5,Enable Set for level_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_4,Enable Set for level_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_3,Enable Set for level_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_2,Enable Set for level_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_1,Enable Set for level_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_0,Enable Set for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_5,Enable Register 5"
bitfld.long 0x14 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_0_6,Enable Register 6"
bitfld.long 0x18 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_CTM_PULSE,Enable Set for level_dmpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x18 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_PROT_ERR,Enable Set for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_0,Enable Register 7"
bitfld.long 0x1C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR,Enable Set for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR,Enable Set for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT,Enable Set for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR,Enable Set for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR,Enable Set for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT,Enable Set for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_WRITE_ERROR,Enable Set for level_dmpac_out_1_en_sde_write_error" "0,1"
newline
bitfld.long 0x1C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_READ_ERROR,Enable Set for level_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x1C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_FRAME_DONE,Enable Set for level_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x1C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_BLK_DONE,Enable Set for level_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x1C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x1C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_WRITE_ERROR,Enable Set for level_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x1C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_READ_ERROR,Enable Set for level_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x1C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_FRAME_DONE,Enable Set for level_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x1C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_ROW_DONE,Enable Set for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_1,Enable Register 8"
bitfld.long 0x20 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_8,Enable Set for level_dmpac_out_1_en_tdone_8" "0,1"
newline
bitfld.long 0x20 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_7,Enable Set for level_dmpac_out_1_en_tdone_7" "0,1"
newline
bitfld.long 0x20 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_1,Enable Set for level_dmpac_out_1_en_tdone_1" "0,1"
newline
bitfld.long 0x20 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_0,Enable Set for level_dmpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x20 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_L,Enable Set for level_dmpac_out_1_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x20 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_P,Enable Set for level_dmpac_out_1_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x20 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_L,Enable Set for level_dmpac_out_1_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x20 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_P,Enable Set for level_dmpac_out_1_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x20 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for level_dmpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x20 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for level_dmpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x20 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for level_dmpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x20 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for level_dmpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x20 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for level_dmpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x20 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_2,Enable Register 9"
bitfld.long 0x24 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x24 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x24 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x24 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_3,Enable Register 10"
bitfld.long 0x28 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_31,Enable Set for level_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x28 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_30,Enable Set for level_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x28 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_29,Enable Set for level_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x28 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_28,Enable Set for level_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x28 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_27,Enable Set for level_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x28 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_26,Enable Set for level_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x28 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_25,Enable Set for level_dmpac_out_1_en_dru_error_25" "0,1"
newline
bitfld.long 0x28 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_24,Enable Set for level_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x28 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_23,Enable Set for level_dmpac_out_1_en_dru_error_23" "0,1"
newline
bitfld.long 0x28 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_22,Enable Set for level_dmpac_out_1_en_dru_error_22" "0,1"
newline
bitfld.long 0x28 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_21,Enable Set for level_dmpac_out_1_en_dru_error_21" "0,1"
newline
bitfld.long 0x28 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_20,Enable Set for level_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x28 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_19,Enable Set for level_dmpac_out_1_en_dru_error_19" "0,1"
newline
bitfld.long 0x28 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_18,Enable Set for level_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x28 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_17,Enable Set for level_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x28 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_16,Enable Set for level_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x28 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_15,Enable Set for level_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x28 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_14,Enable Set for level_dmpac_out_1_en_dru_error_14" "0,1"
newline
bitfld.long 0x28 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_13,Enable Set for level_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x28 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_12,Enable Set for level_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x28 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_11,Enable Set for level_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x28 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_10,Enable Set for level_dmpac_out_1_en_dru_error_10" "0,1"
newline
bitfld.long 0x28 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_9,Enable Set for level_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x28 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_8,Enable Set for level_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x28 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_7,Enable Set for level_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x28 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_6,Enable Set for level_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x28 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_5,Enable Set for level_dmpac_out_1_en_dru_error_5" "0,1"
newline
bitfld.long 0x28 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_4,Enable Set for level_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x28 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_3,Enable Set for level_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x28 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_2,Enable Set for level_dmpac_out_1_en_dru_error_2" "0,1"
newline
bitfld.long 0x28 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_1,Enable Set for level_dmpac_out_1_en_dru_error_1" "0,1"
newline
bitfld.long 0x28 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_0,Enable Set for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_4,Enable Register 11"
bitfld.long 0x2C 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_31,Enable Set for level_dmpac_out_1_en_dru_complete_31" "0,1"
newline
bitfld.long 0x2C 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_30,Enable Set for level_dmpac_out_1_en_dru_complete_30" "0,1"
newline
bitfld.long 0x2C 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_29,Enable Set for level_dmpac_out_1_en_dru_complete_29" "0,1"
newline
bitfld.long 0x2C 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_28,Enable Set for level_dmpac_out_1_en_dru_complete_28" "0,1"
newline
bitfld.long 0x2C 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_27,Enable Set for level_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x2C 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_26,Enable Set for level_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x2C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_25,Enable Set for level_dmpac_out_1_en_dru_complete_25" "0,1"
newline
bitfld.long 0x2C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_24,Enable Set for level_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x2C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_23,Enable Set for level_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x2C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_22,Enable Set for level_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x2C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_21,Enable Set for level_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x2C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_20,Enable Set for level_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x2C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_19,Enable Set for level_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x2C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_18,Enable Set for level_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x2C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_17,Enable Set for level_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x2C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_16,Enable Set for level_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x2C 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_15,Enable Set for level_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x2C 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_14,Enable Set for level_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x2C 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_13,Enable Set for level_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x2C 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_12,Enable Set for level_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x2C 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_11,Enable Set for level_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x2C 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_10,Enable Set for level_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x2C 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_9,Enable Set for level_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x2C 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_8,Enable Set for level_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x2C 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_7,Enable Set for level_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x2C 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_6,Enable Set for level_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x2C 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_5,Enable Set for level_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x2C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_4,Enable Set for level_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x2C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_3,Enable Set for level_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x2C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_2,Enable Set for level_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x2C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_1,Enable Set for level_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x2C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_0,Enable Set for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_5,Enable Register 12"
bitfld.long 0x30 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x30 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x30 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x30 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x30 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x30 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x30 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x30 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x30 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x30 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x30 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x30 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x30 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x30 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x30 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x30 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x30 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x30 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x30 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x30 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x30 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x30 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x30 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x30 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x30 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x30 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x30 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x30 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x30 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x30 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x30 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x30 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_ENABLE_REG_LEVEL_DMPAC_OUT_1_6,Enable Register 13"
bitfld.long 0x34 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_CTM_PULSE,Enable Set for level_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x34 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_PROT_ERR,Enable Set for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_0,Enable Register 14"
bitfld.long 0x38 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR,Enable Set for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR,Enable Set for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT,Enable Set for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x38 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR,Enable Set for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR,Enable Set for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT,Enable Set for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x38 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_WRITE_ERROR,Enable Set for pulse_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x38 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_READ_ERROR,Enable Set for pulse_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x38 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_FRAME_DONE,Enable Set for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x38 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_BLK_DONE,Enable Set for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x38 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x38 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_WRITE_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x38 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_READ_ERROR,Enable Set for pulse_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x38 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_FRAME_DONE,Enable Set for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x38 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_ROW_DONE,Enable Set for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_1,Enable Register 15"
bitfld.long 0x3C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_8,Enable Set for pulse_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x3C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_7,Enable Set for pulse_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x3C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_1,Enable Set for pulse_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x3C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_0,Enable Set for pulse_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x3C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_L,Enable Set for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x3C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_P,Enable Set for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x3C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_L,Enable Set for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x3C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_P,Enable Set for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x3C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x3C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x3C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x3C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x3C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x3C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_2,Enable Register 16"
bitfld.long 0x40 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x40 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x40 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x40 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_3,Enable Register 17"
bitfld.long 0x44 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_31,Enable Set for pulse_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x44 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_30,Enable Set for pulse_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x44 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_29,Enable Set for pulse_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x44 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_28,Enable Set for pulse_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x44 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_27,Enable Set for pulse_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x44 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_26,Enable Set for pulse_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x44 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_25,Enable Set for pulse_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x44 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_24,Enable Set for pulse_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x44 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_23,Enable Set for pulse_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x44 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_22,Enable Set for pulse_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x44 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_21,Enable Set for pulse_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x44 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_20,Enable Set for pulse_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x44 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_19,Enable Set for pulse_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x44 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_18,Enable Set for pulse_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x44 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_17,Enable Set for pulse_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x44 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_16,Enable Set for pulse_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x44 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_15,Enable Set for pulse_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x44 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_14,Enable Set for pulse_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x44 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_13,Enable Set for pulse_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x44 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_12,Enable Set for pulse_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x44 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_11,Enable Set for pulse_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x44 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_10,Enable Set for pulse_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x44 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_9,Enable Set for pulse_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x44 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_8,Enable Set for pulse_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x44 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_7,Enable Set for pulse_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x44 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_6,Enable Set for pulse_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x44 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_5,Enable Set for pulse_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x44 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_4,Enable Set for pulse_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x44 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_3,Enable Set for pulse_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x44 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_2,Enable Set for pulse_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x44 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_1,Enable Set for pulse_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x44 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_0,Enable Set for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_4,Enable Register 18"
bitfld.long 0x48 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_31,Enable Set for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x48 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_30,Enable Set for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x48 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_29,Enable Set for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x48 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_28,Enable Set for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x48 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_27,Enable Set for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x48 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_26,Enable Set for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x48 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_25,Enable Set for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x48 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_24,Enable Set for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x48 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_23,Enable Set for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x48 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_22,Enable Set for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x48 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_21,Enable Set for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x48 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_20,Enable Set for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x48 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_19,Enable Set for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x48 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_18,Enable Set for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x48 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_17,Enable Set for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x48 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_16,Enable Set for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x48 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_15,Enable Set for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x48 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_14,Enable Set for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x48 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_13,Enable Set for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x48 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_12,Enable Set for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x48 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_11,Enable Set for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x48 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_10,Enable Set for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x48 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_9,Enable Set for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x48 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_8,Enable Set for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x48 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_7,Enable Set for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x48 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_6,Enable Set for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x48 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_5,Enable Set for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x48 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_4,Enable Set for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x48 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_3,Enable Set for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x48 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_2,Enable Set for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x48 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_1,Enable Set for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x48 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_0,Enable Set for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_5,Enable Register 19"
bitfld.long 0x4C 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x4C 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x4C 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x4C 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x4C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x4C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x4C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x4C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x4C 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x4C 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x4C 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x4C 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x4C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x4C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x4C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x4C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x4C 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x4C 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x4C 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x4C 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x4C 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x4C 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x4C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x4C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x4C 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x4C 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x4C 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x4C 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x4C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x4C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x4C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x4C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_0_6,Enable Register 20"
bitfld.long 0x50 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_CTM_PULSE,Enable Set for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x50 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_PROT_ERR,Enable Set for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_0,Enable Register 21"
bitfld.long 0x54 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR,Enable Set for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x54 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR,Enable Set for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x54 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT,Enable Set for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x54 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR,Enable Set for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x54 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR,Enable Set for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x54 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT,Enable Set for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x54 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_WRITE_ERROR,Enable Set for pulse_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x54 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_READ_ERROR,Enable Set for pulse_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x54 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_FRAME_DONE,Enable Set for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x54 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_BLK_DONE,Enable Set for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x54 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x54 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_WRITE_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x54 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_READ_ERROR,Enable Set for pulse_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x54 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_FRAME_DONE,Enable Set for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x54 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_ROW_DONE,Enable Set for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_1,Enable Register 22"
bitfld.long 0x58 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_8,Enable Set for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_7,Enable Set for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_1,Enable Set for pulse_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x58 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_0,Enable Set for pulse_dmpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x58 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_L,Enable Set for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1"
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bitfld.long 0x58 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_P,Enable Set for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1"
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bitfld.long 0x58 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_L,Enable Set for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1"
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bitfld.long 0x58 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_P,Enable Set for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1"
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bitfld.long 0x58 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x58 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x58 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x58 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_2,Enable Register 23"
bitfld.long 0x5C 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x5C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x5C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_3,Enable Register 24"
bitfld.long 0x60 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_31,Enable Set for pulse_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x60 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_30,Enable Set for pulse_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x60 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_29,Enable Set for pulse_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x60 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_28,Enable Set for pulse_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x60 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_27,Enable Set for pulse_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x60 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_26,Enable Set for pulse_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x60 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_25,Enable Set for pulse_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x60 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_24,Enable Set for pulse_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x60 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_23,Enable Set for pulse_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x60 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_22,Enable Set for pulse_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x60 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_21,Enable Set for pulse_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x60 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_20,Enable Set for pulse_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x60 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_19,Enable Set for pulse_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x60 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_18,Enable Set for pulse_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x60 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_17,Enable Set for pulse_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x60 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_16,Enable Set for pulse_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x60 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_15,Enable Set for pulse_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x60 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_14,Enable Set for pulse_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x60 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_13,Enable Set for pulse_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x60 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_12,Enable Set for pulse_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x60 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_11,Enable Set for pulse_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x60 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_10,Enable Set for pulse_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x60 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_9,Enable Set for pulse_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x60 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_8,Enable Set for pulse_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x60 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_7,Enable Set for pulse_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x60 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_6,Enable Set for pulse_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x60 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_5,Enable Set for pulse_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x60 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_4,Enable Set for pulse_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x60 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_3,Enable Set for pulse_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x60 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_2,Enable Set for pulse_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x60 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_1,Enable Set for pulse_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x60 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_0,Enable Set for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_4,Enable Register 25"
bitfld.long 0x64 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_31,Enable Set for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x64 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_30,Enable Set for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x64 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_29,Enable Set for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x64 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_28,Enable Set for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x64 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_27,Enable Set for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x64 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_26,Enable Set for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x64 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_25,Enable Set for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x64 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_24,Enable Set for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x64 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_23,Enable Set for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x64 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_22,Enable Set for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x64 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_21,Enable Set for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x64 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_20,Enable Set for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x64 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_19,Enable Set for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x64 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_18,Enable Set for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x64 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_17,Enable Set for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x64 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_16,Enable Set for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
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bitfld.long 0x64 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_15,Enable Set for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
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bitfld.long 0x64 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_14,Enable Set for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
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bitfld.long 0x64 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_13,Enable Set for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
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bitfld.long 0x64 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_12,Enable Set for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
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bitfld.long 0x64 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_11,Enable Set for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
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bitfld.long 0x64 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_10,Enable Set for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
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bitfld.long 0x64 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_9,Enable Set for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
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bitfld.long 0x64 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_8,Enable Set for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
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bitfld.long 0x64 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_7,Enable Set for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x64 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_6,Enable Set for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
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bitfld.long 0x64 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_5,Enable Set for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x64 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_4,Enable Set for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x64 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_3,Enable Set for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x64 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_2,Enable Set for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x64 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_1,Enable Set for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x64 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_0,Enable Set for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_5,Enable Register 26"
bitfld.long 0x68 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x68 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x68 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x68 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x68 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x68 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x68 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x68 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x68 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x68 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x68 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x68 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x68 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0,Enable Set for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_ENABLE_REG_PULSE_DMPAC_OUT_1_6,Enable Register 27"
bitfld.long 0x6C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_CTM_PULSE,Enable Set for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x6C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_PROT_ERR,Enable Set for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
group.long 0x300++0x6F
line.long 0x00 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_0,Enable Clear Register 0"
bitfld.long 0x00 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_READ_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SDE_BLK_DONE_CLR,Enable Clear for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_READ_ERROR_CLR,Enable Clear for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DOF_ROW_DONE_CLR,Enable Clear for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_1,Enable Clear Register 1"
bitfld.long 0x04 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_8_CLR,Enable Clear for level_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_7_CLR,Enable Clear for level_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x04 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_1_CLR,Enable Clear for level_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x04 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for level_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_L_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_1_P_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_L_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_PEND_0_P_CLR,Enable Clear for level_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_2,Enable Clear Register 2"
bitfld.long 0x08 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_3,Enable Clear Register 3"
bitfld.long 0x0C 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x0C 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x0C 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x0C 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x0C 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x0C 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x0C 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x0C 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x0C 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x0C 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x0C 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x0C 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x0C 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x0C 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x0C 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x0C 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x0C 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x0C 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x0C 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x0C 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x0C 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x0C 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_ERROR_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_4,Enable Clear Register 4"
bitfld.long 0x10 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x10 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x10 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x10 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x10 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x10 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_COMPLETE_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_5,Enable Clear Register 5"
bitfld.long 0x14 31. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_0_6,Enable Clear Register 6"
bitfld.long 0x18 1. "ENABLE_LEVEL_DMPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for level_dmpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x18 0. "ENABLE_LEVEL_DMPAC_OUT_0_EN_DRU_PROT_ERR_CLR,Enable Clear for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_0,Enable Clear Register 7"
bitfld.long 0x1C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x1C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x1C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x1C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_sde_write_error" "0,1"
newline
bitfld.long 0x1C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_READ_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x1C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x1C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SDE_BLK_DONE_CLR,Enable Clear for level_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x1C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x1C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_WRITE_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x1C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_READ_ERROR_CLR,Enable Clear for level_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x1C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_FRAME_DONE_CLR,Enable Clear for level_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x1C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DOF_ROW_DONE_CLR,Enable Clear for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_1,Enable Clear Register 8"
bitfld.long 0x20 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_8_CLR,Enable Clear for level_dmpac_out_1_en_tdone_8" "0,1"
newline
bitfld.long 0x20 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_7_CLR,Enable Clear for level_dmpac_out_1_en_tdone_7" "0,1"
newline
bitfld.long 0x20 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_1_CLR,Enable Clear for level_dmpac_out_1_en_tdone_1" "0,1"
newline
bitfld.long 0x20 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for level_dmpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x20 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_L_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x20 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_1_P_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x20 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_L_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x20 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_PEND_0_P_CLR,Enable Clear for level_dmpac_out_1_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x20 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for level_dmpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x20 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for level_dmpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x20 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x20 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x20 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x20 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_2,Enable Clear Register 9"
bitfld.long 0x24 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x24 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x24 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x24 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_3,Enable Clear Register 10"
bitfld.long 0x28 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x28 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x28 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x28 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x28 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x28 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x28 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_25" "0,1"
newline
bitfld.long 0x28 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x28 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_23" "0,1"
newline
bitfld.long 0x28 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_22" "0,1"
newline
bitfld.long 0x28 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_21" "0,1"
newline
bitfld.long 0x28 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x28 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_19" "0,1"
newline
bitfld.long 0x28 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x28 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x28 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x28 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x28 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_14" "0,1"
newline
bitfld.long 0x28 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x28 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x28 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x28 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_10" "0,1"
newline
bitfld.long 0x28 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x28 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x28 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x28 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x28 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_5" "0,1"
newline
bitfld.long 0x28 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x28 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x28 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_2" "0,1"
newline
bitfld.long 0x28 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_1" "0,1"
newline
bitfld.long 0x28 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_ERROR_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_4,Enable Clear Register 11"
bitfld.long 0x2C 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x2C 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x2C 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x2C 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x2C 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x2C 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x2C 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x2C 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x2C 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x2C 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x2C 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x2C 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x2C 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x2C 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x2C 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x2C 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x2C 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x2C 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x2C 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x2C 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x2C 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x2C 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x2C 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x2C 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x2C 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x2C 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x2C 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x2C 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x2C 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x2C 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x2C 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x2C 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_COMPLETE_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_5,Enable Clear Register 12"
bitfld.long 0x30 31. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x30 30. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x30 29. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x30 28. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x30 27. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x30 26. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x30 25. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x30 24. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x30 23. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x30 22. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x30 21. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x30 20. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x30 19. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x30 18. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x30 17. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x30 16. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x30 15. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x30 14. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x30 13. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x30 12. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x30 11. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x30 10. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x30 9. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x30 8. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x30 7. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x30 6. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x30 5. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x30 4. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x30 3. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x30 2. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x30 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x30 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_ENABLE_CLR_REG_LEVEL_DMPAC_OUT_1_6,Enable Clear Register 13"
bitfld.long 0x34 1. "ENABLE_LEVEL_DMPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for level_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x34 0. "ENABLE_LEVEL_DMPAC_OUT_1_EN_DRU_PROT_ERR_CLR,Enable Clear for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_0,Enable Clear Register 14"
bitfld.long 0x38 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x38 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x38 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x38 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x38 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x38 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x38 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x38 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SDE_BLK_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x38 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x38 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x38 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x38 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x38 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DOF_ROW_DONE_CLR,Enable Clear for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_1,Enable Clear Register 15"
bitfld.long 0x3C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_8_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x3C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_7_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x3C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x3C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x3C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_L_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x3C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_1_P_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x3C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_L_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x3C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_PEND_0_P_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x3C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x3C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x3C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x3C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x3C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x3C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_2,Enable Clear Register 16"
bitfld.long 0x40 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x40 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x40 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x40 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_3,Enable Clear Register 17"
bitfld.long 0x44 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_31" "0,1"
newline
bitfld.long 0x44 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_30" "0,1"
newline
bitfld.long 0x44 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_29" "0,1"
newline
bitfld.long 0x44 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_28" "0,1"
newline
bitfld.long 0x44 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_27" "0,1"
newline
bitfld.long 0x44 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x44 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_25" "0,1"
newline
bitfld.long 0x44 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_24" "0,1"
newline
bitfld.long 0x44 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x44 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_22" "0,1"
newline
bitfld.long 0x44 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x44 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x44 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_19" "0,1"
newline
bitfld.long 0x44 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x44 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x44 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x44 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x44 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x44 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x44 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x44 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x44 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x44 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x44 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x44 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x44 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x44 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x44 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x44 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x44 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x44 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x44 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_ERROR_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_4,Enable Clear Register 18"
bitfld.long 0x48 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x48 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x48 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x48 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x48 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x48 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x48 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x48 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x48 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x48 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x48 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x48 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x48 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x48 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x48 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x48 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x48 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x48 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x48 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x48 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x48 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x48 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x48 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x48 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x48 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x48 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x48 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x48 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x48 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x48 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x48 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x48 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_COMPLETE_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_5,Enable Clear Register 19"
bitfld.long 0x4C 31. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x4C 30. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x4C 29. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x4C 28. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x4C 27. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x4C 26. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x4C 25. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x4C 24. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x4C 23. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x4C 22. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x4C 21. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x4C 20. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x4C 19. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x4C 18. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x4C 17. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x4C 16. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x4C 15. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x4C 14. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x4C 13. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x4C 12. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x4C 11. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x4C 10. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x4C 9. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x4C 8. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x4C 7. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x4C 6. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x4C 5. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x4C 4. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x4C 3. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x4C 2. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x4C 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x4C 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_0_6,Enable Clear Register 20"
bitfld.long 0x50 1. "ENABLE_PULSE_DMPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x50 0. "ENABLE_PULSE_DMPAC_OUT_0_EN_DRU_PROT_ERR_CLR,Enable Clear for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_0,Enable Clear Register 21"
bitfld.long 0x54 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x54 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x54 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_1_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x54 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_WR_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x54 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_SL2_RD_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x54 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_FOCO_0_FR_DONE_EVT_CLR,Enable Clear for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x54 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_write_error" "0,1"
newline
bitfld.long 0x54 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x54 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x54 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SDE_BLK_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x54 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_MP0_RD_STATUS_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x54 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_WRITE_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x54 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_READ_ERROR_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x54 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_FRAME_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x54 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DOF_ROW_DONE_CLR,Enable Clear for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_1,Enable Clear Register 22"
bitfld.long 0x58 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_8_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_8" "0,1"
newline
bitfld.long 0x58 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_7_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_7" "0,1"
newline
bitfld.long 0x58 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_1" "0,1"
newline
bitfld.long 0x58 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x58 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_L_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1"
newline
bitfld.long 0x58 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_1_P_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1"
newline
bitfld.long 0x58 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_L_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1"
newline
bitfld.long 0x58 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_PEND_0_P_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x58 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x58 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x58 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x58 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x58 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x58 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_2,Enable Clear Register 23"
bitfld.long 0x5C 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_8_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_7_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x5C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_1_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x5C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_3,Enable Clear Register 24"
bitfld.long 0x60 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x60 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x60 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x60 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x60 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x60 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x60 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_25" "0,1"
newline
bitfld.long 0x60 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x60 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_23" "0,1"
newline
bitfld.long 0x60 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_22" "0,1"
newline
bitfld.long 0x60 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_21" "0,1"
newline
bitfld.long 0x60 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x60 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_19" "0,1"
newline
bitfld.long 0x60 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x60 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x60 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x60 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x60 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_14" "0,1"
newline
bitfld.long 0x60 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x60 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x60 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x60 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_10" "0,1"
newline
bitfld.long 0x60 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x60 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x60 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x60 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x60 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_5" "0,1"
newline
bitfld.long 0x60 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x60 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x60 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_2" "0,1"
newline
bitfld.long 0x60 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_1" "0,1"
newline
bitfld.long 0x60 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_ERROR_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_4,Enable Clear Register 25"
bitfld.long 0x64 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
newline
bitfld.long 0x64 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
newline
bitfld.long 0x64 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
newline
bitfld.long 0x64 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
newline
bitfld.long 0x64 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x64 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x64 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
newline
bitfld.long 0x64 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x64 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x64 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x64 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x64 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x64 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x64 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x64 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x64 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x64 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x64 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x64 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x64 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x64 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x64 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x64 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x64 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x64 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x64 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x64 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x64 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x64 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x64 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x64 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x64 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_COMPLETE_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_5,Enable Clear Register 26"
bitfld.long 0x68 31. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_31_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x68 30. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_30_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x68 29. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_29_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x68 28. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_28_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x68 27. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_27_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x68 26. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_26_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x68 25. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_25_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x68 24. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_24_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x68 23. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_23_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x68 22. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_22_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_21_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_20_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_19_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_18_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_17_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_16_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_15_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_14_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_13_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_12_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_11_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_10_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_9_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_8_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_7_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_6_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_5_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_4_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_3_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x68 2. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_2_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x68 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_1_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x68 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_LOCAL_OUT_EVENT_0_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_ENABLE_CLR_REG_PULSE_DMPAC_OUT_1_6,Enable Clear Register 27"
bitfld.long 0x6C 1. "ENABLE_PULSE_DMPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x6C 0. "ENABLE_PULSE_DMPAC_OUT_1_EN_DRU_PROT_ERR_CLR,Enable Clear for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
group.long 0x500++0x6F
line.long 0x00 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_0,Status Register 0"
bitfld.long 0x00 25. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x00 24. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x00 23. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x00 22. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x00 21. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x00 20. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x00 19. "STATUS_LEVEL_DMPAC_OUT_0_SDE_WRITE_ERROR,Status write 1 to set for level_dmpac_out_0_en_sde_write_error" "0,1"
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bitfld.long 0x00 18. "STATUS_LEVEL_DMPAC_OUT_0_SDE_READ_ERROR,Status write 1 to set for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_DMPAC_OUT_0_SDE_FRAME_DONE,Status write 1 to set for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "STATUS_LEVEL_DMPAC_OUT_0_SDE_BLK_DONE,Status write 1 to set for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "STATUS_LEVEL_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_DMPAC_OUT_0_DOF_WRITE_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_DMPAC_OUT_0_DOF_READ_ERROR,Status write 1 to set for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_DMPAC_OUT_0_DOF_FRAME_DONE,Status write 1 to set for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_DMPAC_OUT_0_DOF_ROW_DONE,Status write 1 to set for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_1,Status Register 1"
bitfld.long 0x04 27. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_8,Status write 1 to set for level_dmpac_out_0_en_tdone_8" "0,1"
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bitfld.long 0x04 26. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_7,Status write 1 to set for level_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x04 25. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_1,Status write 1 to set for level_dmpac_out_0_en_tdone_1" "0,1"
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bitfld.long 0x04 24. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_0,Status write 1 to set for level_dmpac_out_0_en_tdone_0" "0,1"
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rbitfld.long 0x04 19. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_1_L,Status for level_dmpac_out_0_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x04 18. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_1_P,Status for level_dmpac_out_0_en_spare_pend_1_p" "0,1"
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rbitfld.long 0x04 17. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_0_L,Status for level_dmpac_out_0_en_spare_pend_0_l" "0,1"
newline
rbitfld.long 0x04 16. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_PEND_0_P,Status for level_dmpac_out_0_en_spare_pend_0_p" "0,1"
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bitfld.long 0x04 9. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for level_dmpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x04 8. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for level_dmpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for level_dmpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for level_dmpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_2,Status Register 2"
bitfld.long 0x08 3. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_3,Status Register 3"
bitfld.long 0x0C 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_31,Status write 1 to set for level_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x0C 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_30,Status write 1 to set for level_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x0C 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_29,Status write 1 to set for level_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x0C 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_28,Status write 1 to set for level_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x0C 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_27,Status write 1 to set for level_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x0C 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_26,Status write 1 to set for level_dmpac_out_0_en_dru_error_26" "0,1"
newline
bitfld.long 0x0C 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_25,Status write 1 to set for level_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x0C 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_24,Status write 1 to set for level_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x0C 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_23,Status write 1 to set for level_dmpac_out_0_en_dru_error_23" "0,1"
newline
bitfld.long 0x0C 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_22,Status write 1 to set for level_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x0C 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_21,Status write 1 to set for level_dmpac_out_0_en_dru_error_21" "0,1"
newline
bitfld.long 0x0C 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_20,Status write 1 to set for level_dmpac_out_0_en_dru_error_20" "0,1"
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bitfld.long 0x0C 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_19,Status write 1 to set for level_dmpac_out_0_en_dru_error_19" "0,1"
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bitfld.long 0x0C 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_18,Status write 1 to set for level_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x0C 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_17,Status write 1 to set for level_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x0C 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_16,Status write 1 to set for level_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x0C 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_15,Status write 1 to set for level_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x0C 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_14,Status write 1 to set for level_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x0C 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_13,Status write 1 to set for level_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x0C 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_12,Status write 1 to set for level_dmpac_out_0_en_dru_error_12" "0,1"
newline
bitfld.long 0x0C 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_11,Status write 1 to set for level_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x0C 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_10,Status write 1 to set for level_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x0C 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_9,Status write 1 to set for level_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x0C 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_8,Status write 1 to set for level_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x0C 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_7,Status write 1 to set for level_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x0C 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_6,Status write 1 to set for level_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x0C 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_5,Status write 1 to set for level_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x0C 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_4,Status write 1 to set for level_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x0C 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_3,Status write 1 to set for level_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x0C 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_2,Status write 1 to set for level_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x0C 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_1,Status write 1 to set for level_dmpac_out_0_en_dru_error_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_0,Status write 1 to set for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_4,Status Register 4"
bitfld.long 0x10 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_31,Status write 1 to set for level_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x10 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_30,Status write 1 to set for level_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x10 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_29,Status write 1 to set for level_dmpac_out_0_en_dru_complete_29" "0,1"
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bitfld.long 0x10 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_28,Status write 1 to set for level_dmpac_out_0_en_dru_complete_28" "0,1"
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bitfld.long 0x10 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_27,Status write 1 to set for level_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x10 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_26,Status write 1 to set for level_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x10 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_25,Status write 1 to set for level_dmpac_out_0_en_dru_complete_25" "0,1"
newline
bitfld.long 0x10 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_24,Status write 1 to set for level_dmpac_out_0_en_dru_complete_24" "0,1"
newline
bitfld.long 0x10 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_23,Status write 1 to set for level_dmpac_out_0_en_dru_complete_23" "0,1"
newline
bitfld.long 0x10 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_22,Status write 1 to set for level_dmpac_out_0_en_dru_complete_22" "0,1"
newline
bitfld.long 0x10 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_21,Status write 1 to set for level_dmpac_out_0_en_dru_complete_21" "0,1"
newline
bitfld.long 0x10 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_20,Status write 1 to set for level_dmpac_out_0_en_dru_complete_20" "0,1"
newline
bitfld.long 0x10 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_19,Status write 1 to set for level_dmpac_out_0_en_dru_complete_19" "0,1"
newline
bitfld.long 0x10 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_18,Status write 1 to set for level_dmpac_out_0_en_dru_complete_18" "0,1"
newline
bitfld.long 0x10 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_17,Status write 1 to set for level_dmpac_out_0_en_dru_complete_17" "0,1"
newline
bitfld.long 0x10 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_16,Status write 1 to set for level_dmpac_out_0_en_dru_complete_16" "0,1"
newline
bitfld.long 0x10 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_15,Status write 1 to set for level_dmpac_out_0_en_dru_complete_15" "0,1"
newline
bitfld.long 0x10 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_14,Status write 1 to set for level_dmpac_out_0_en_dru_complete_14" "0,1"
newline
bitfld.long 0x10 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_13,Status write 1 to set for level_dmpac_out_0_en_dru_complete_13" "0,1"
newline
bitfld.long 0x10 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_12,Status write 1 to set for level_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x10 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_11,Status write 1 to set for level_dmpac_out_0_en_dru_complete_11" "0,1"
newline
bitfld.long 0x10 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_10,Status write 1 to set for level_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x10 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_9,Status write 1 to set for level_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x10 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_8,Status write 1 to set for level_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x10 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_7,Status write 1 to set for level_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x10 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_6,Status write 1 to set for level_dmpac_out_0_en_dru_complete_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_5,Status write 1 to set for level_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_4,Status write 1 to set for level_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x10 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_3,Status write 1 to set for level_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x10 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_2,Status write 1 to set for level_dmpac_out_0_en_dru_complete_2" "0,1"
newline
bitfld.long 0x10 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_1,Status write 1 to set for level_dmpac_out_0_en_dru_complete_1" "0,1"
newline
bitfld.long 0x10 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_0,Status write 1 to set for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_5,Status Register 5"
bitfld.long 0x14 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x14 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x14 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
newline
bitfld.long 0x14 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x14 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x14 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x14 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x14 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x14 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x14 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x14 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_0_6,Status Register 6"
bitfld.long 0x18 1. "STATUS_LEVEL_DMPAC_OUT_0_CTM_PULSE,Status write 1 to set for level_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x18 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_PROT_ERR,Status write 1 to set for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_0,Status Register 7"
bitfld.long 0x1C 25. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x1C 24. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x1C 23. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x1C 22. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x1C 21. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR,Status write 1 to set for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x1C 20. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT,Status write 1 to set for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x1C 19. "STATUS_LEVEL_DMPAC_OUT_1_SDE_WRITE_ERROR,Status write 1 to set for level_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x1C 18. "STATUS_LEVEL_DMPAC_OUT_1_SDE_READ_ERROR,Status write 1 to set for level_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x1C 17. "STATUS_LEVEL_DMPAC_OUT_1_SDE_FRAME_DONE,Status write 1 to set for level_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x1C 16. "STATUS_LEVEL_DMPAC_OUT_1_SDE_BLK_DONE,Status write 1 to set for level_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x1C 4. "STATUS_LEVEL_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x1C 3. "STATUS_LEVEL_DMPAC_OUT_1_DOF_WRITE_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x1C 2. "STATUS_LEVEL_DMPAC_OUT_1_DOF_READ_ERROR,Status write 1 to set for level_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x1C 1. "STATUS_LEVEL_DMPAC_OUT_1_DOF_FRAME_DONE,Status write 1 to set for level_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x1C 0. "STATUS_LEVEL_DMPAC_OUT_1_DOF_ROW_DONE,Status write 1 to set for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_1,Status Register 8"
bitfld.long 0x20 27. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_8,Status write 1 to set for level_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x20 26. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_7,Status write 1 to set for level_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x20 25. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_1,Status write 1 to set for level_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x20 24. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_0,Status write 1 to set for level_dmpac_out_1_en_tdone_0" "0,1"
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rbitfld.long 0x20 19. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_1_L,Status for level_dmpac_out_1_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x20 18. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_1_P,Status for level_dmpac_out_1_en_spare_pend_1_p" "0,1"
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rbitfld.long 0x20 17. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_0_L,Status for level_dmpac_out_1_en_spare_pend_0_l" "0,1"
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rbitfld.long 0x20 16. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_PEND_0_P,Status for level_dmpac_out_1_en_spare_pend_0_p" "0,1"
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bitfld.long 0x20 9. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for level_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x20 8. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for level_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x20 3. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for level_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x20 2. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for level_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x20 1. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for level_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x20 0. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_2,Status Register 9"
bitfld.long 0x24 3. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x24 2. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x24 1. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x24 0. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_3,Status Register 10"
bitfld.long 0x28 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_31,Status write 1 to set for level_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x28 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_30,Status write 1 to set for level_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x28 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_29,Status write 1 to set for level_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x28 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_28,Status write 1 to set for level_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x28 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_27,Status write 1 to set for level_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x28 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_26,Status write 1 to set for level_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x28 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_25,Status write 1 to set for level_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x28 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_24,Status write 1 to set for level_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x28 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_23,Status write 1 to set for level_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x28 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_22,Status write 1 to set for level_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x28 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_21,Status write 1 to set for level_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x28 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_20,Status write 1 to set for level_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x28 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_19,Status write 1 to set for level_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x28 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_18,Status write 1 to set for level_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x28 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_17,Status write 1 to set for level_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x28 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_16,Status write 1 to set for level_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x28 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_15,Status write 1 to set for level_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x28 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_14,Status write 1 to set for level_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x28 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_13,Status write 1 to set for level_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x28 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_12,Status write 1 to set for level_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x28 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_11,Status write 1 to set for level_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x28 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_10,Status write 1 to set for level_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x28 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_9,Status write 1 to set for level_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x28 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_8,Status write 1 to set for level_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x28 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_7,Status write 1 to set for level_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x28 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_6,Status write 1 to set for level_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x28 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_5,Status write 1 to set for level_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x28 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_4,Status write 1 to set for level_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x28 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_3,Status write 1 to set for level_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x28 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_2,Status write 1 to set for level_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x28 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_1,Status write 1 to set for level_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x28 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_0,Status write 1 to set for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_4,Status Register 11"
bitfld.long 0x2C 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_31,Status write 1 to set for level_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x2C 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_30,Status write 1 to set for level_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x2C 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_29,Status write 1 to set for level_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x2C 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_28,Status write 1 to set for level_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x2C 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_27,Status write 1 to set for level_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x2C 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_26,Status write 1 to set for level_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x2C 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_25,Status write 1 to set for level_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x2C 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_24,Status write 1 to set for level_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x2C 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_23,Status write 1 to set for level_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x2C 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_22,Status write 1 to set for level_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x2C 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_21,Status write 1 to set for level_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x2C 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_20,Status write 1 to set for level_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x2C 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_19,Status write 1 to set for level_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x2C 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_18,Status write 1 to set for level_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x2C 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_17,Status write 1 to set for level_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x2C 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_16,Status write 1 to set for level_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x2C 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_15,Status write 1 to set for level_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x2C 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_14,Status write 1 to set for level_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x2C 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_13,Status write 1 to set for level_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x2C 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_12,Status write 1 to set for level_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x2C 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_11,Status write 1 to set for level_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x2C 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_10,Status write 1 to set for level_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x2C 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_9,Status write 1 to set for level_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x2C 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_8,Status write 1 to set for level_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x2C 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_7,Status write 1 to set for level_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x2C 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_6,Status write 1 to set for level_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x2C 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_5,Status write 1 to set for level_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x2C 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_4,Status write 1 to set for level_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x2C 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_3,Status write 1 to set for level_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x2C 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_2,Status write 1 to set for level_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x2C 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_1,Status write 1 to set for level_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x2C 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_0,Status write 1 to set for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_5,Status Register 12"
bitfld.long 0x30 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x30 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x30 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x30 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x30 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x30 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x30 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x30 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x30 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x30 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x30 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x30 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x30 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x30 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x30 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x30 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x30 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x30 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x30 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x30 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x30 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x30 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x30 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x30 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x30 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x30 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x30 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x30 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x30 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x30 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x30 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x30 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_STATUS_REG_LEVEL_DMPAC_OUT_1_6,Status Register 13"
bitfld.long 0x34 1. "STATUS_LEVEL_DMPAC_OUT_1_CTM_PULSE,Status write 1 to set for level_dmpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x34 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_PROT_ERR,Status write 1 to set for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_0,Status Register 14"
bitfld.long 0x38 25. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x38 24. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x38 23. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x38 22. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x38 21. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x38 20. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x38 19. "STATUS_PULSE_DMPAC_OUT_0_SDE_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_sde_write_error" "0,1"
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bitfld.long 0x38 18. "STATUS_PULSE_DMPAC_OUT_0_SDE_READ_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_sde_read_error" "0,1"
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bitfld.long 0x38 17. "STATUS_PULSE_DMPAC_OUT_0_SDE_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
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bitfld.long 0x38 16. "STATUS_PULSE_DMPAC_OUT_0_SDE_BLK_DONE,Status write 1 to set for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
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bitfld.long 0x38 4. "STATUS_PULSE_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x38 3. "STATUS_PULSE_DMPAC_OUT_0_DOF_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_write_error" "0,1"
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bitfld.long 0x38 2. "STATUS_PULSE_DMPAC_OUT_0_DOF_READ_ERROR,Status write 1 to set for pulse_dmpac_out_0_en_dof_read_error" "0,1"
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bitfld.long 0x38 1. "STATUS_PULSE_DMPAC_OUT_0_DOF_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
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bitfld.long 0x38 0. "STATUS_PULSE_DMPAC_OUT_0_DOF_ROW_DONE,Status write 1 to set for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_1,Status Register 15"
bitfld.long 0x3C 27. "STATUS_PULSE_DMPAC_OUT_0_TDONE_8,Status write 1 to set for pulse_dmpac_out_0_en_tdone_8" "0,1"
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bitfld.long 0x3C 26. "STATUS_PULSE_DMPAC_OUT_0_TDONE_7,Status write 1 to set for pulse_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x3C 25. "STATUS_PULSE_DMPAC_OUT_0_TDONE_1,Status write 1 to set for pulse_dmpac_out_0_en_tdone_1" "0,1"
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bitfld.long 0x3C 24. "STATUS_PULSE_DMPAC_OUT_0_TDONE_0,Status write 1 to set for pulse_dmpac_out_0_en_tdone_0" "0,1"
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rbitfld.long 0x3C 19. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_1_L,Status for pulse_dmpac_out_0_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x3C 18. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_1_P,Status for pulse_dmpac_out_0_en_spare_pend_1_p" "0,1"
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rbitfld.long 0x3C 17. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_0_L,Status for pulse_dmpac_out_0_en_spare_pend_0_l" "0,1"
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rbitfld.long 0x3C 16. "STATUS_PULSE_DMPAC_OUT_0_SPARE_PEND_0_P,Status for pulse_dmpac_out_0_en_spare_pend_0_p" "0,1"
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bitfld.long 0x3C 9. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x3C 8. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0x3C 3. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x3C 2. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x3C 1. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x3C 0. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_2,Status Register 16"
bitfld.long 0x40 3. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x40 2. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x40 1. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x40 0. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_3,Status Register 17"
bitfld.long 0x44 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x44 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x44 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x44 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x44 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x44 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_26" "0,1"
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bitfld.long 0x44 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x44 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x44 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_23" "0,1"
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bitfld.long 0x44 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x44 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_21" "0,1"
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bitfld.long 0x44 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_20" "0,1"
newline
bitfld.long 0x44 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_19" "0,1"
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bitfld.long 0x44 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_18" "0,1"
newline
bitfld.long 0x44 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_17" "0,1"
newline
bitfld.long 0x44 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_16" "0,1"
newline
bitfld.long 0x44 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_15" "0,1"
newline
bitfld.long 0x44 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_14" "0,1"
newline
bitfld.long 0x44 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_13" "0,1"
newline
bitfld.long 0x44 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_12" "0,1"
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bitfld.long 0x44 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_11" "0,1"
newline
bitfld.long 0x44 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_10" "0,1"
newline
bitfld.long 0x44 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_9" "0,1"
newline
bitfld.long 0x44 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_8" "0,1"
newline
bitfld.long 0x44 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_7" "0,1"
newline
bitfld.long 0x44 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_6" "0,1"
newline
bitfld.long 0x44 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_5" "0,1"
newline
bitfld.long 0x44 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_4" "0,1"
newline
bitfld.long 0x44 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_3" "0,1"
newline
bitfld.long 0x44 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_2" "0,1"
newline
bitfld.long 0x44 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_1" "0,1"
newline
bitfld.long 0x44 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_4,Status Register 18"
bitfld.long 0x48 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
newline
bitfld.long 0x48 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
newline
bitfld.long 0x48 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
newline
bitfld.long 0x48 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
newline
bitfld.long 0x48 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
newline
bitfld.long 0x48 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
newline
bitfld.long 0x48 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
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bitfld.long 0x48 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
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bitfld.long 0x48 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
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bitfld.long 0x48 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
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bitfld.long 0x48 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
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bitfld.long 0x48 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
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bitfld.long 0x48 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
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bitfld.long 0x48 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
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bitfld.long 0x48 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
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bitfld.long 0x48 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
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bitfld.long 0x48 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
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bitfld.long 0x48 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
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bitfld.long 0x48 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
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bitfld.long 0x48 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
newline
bitfld.long 0x48 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
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bitfld.long 0x48 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
newline
bitfld.long 0x48 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
newline
bitfld.long 0x48 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
newline
bitfld.long 0x48 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
newline
bitfld.long 0x48 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
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bitfld.long 0x48 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
newline
bitfld.long 0x48 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
newline
bitfld.long 0x48 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
newline
bitfld.long 0x48 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
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bitfld.long 0x48 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
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bitfld.long 0x48 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_5,Status Register 19"
bitfld.long 0x4C 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x4C 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x4C 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x4C 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x4C 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x4C 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x4C 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x4C 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x4C 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x4C 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x4C 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x4C 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x4C 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x4C 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x4C 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x4C 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x4C 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x4C 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x4C 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x4C 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x4C 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x4C 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x4C 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x4C 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x4C 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x4C 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x4C 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x4C 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x4C 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x4C 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x4C 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x4C 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_0_6,Status Register 20"
bitfld.long 0x50 1. "STATUS_PULSE_DMPAC_OUT_0_CTM_PULSE,Status write 1 to set for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x50 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_PROT_ERR,Status write 1 to set for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_0,Status Register 21"
bitfld.long 0x54 25. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x54 24. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x54 23. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x54 22. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x54 21. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x54 20. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT,Status write 1 to set for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x54 19. "STATUS_PULSE_DMPAC_OUT_1_SDE_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x54 18. "STATUS_PULSE_DMPAC_OUT_1_SDE_READ_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_sde_read_error" "0,1"
newline
bitfld.long 0x54 17. "STATUS_PULSE_DMPAC_OUT_1_SDE_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
newline
bitfld.long 0x54 16. "STATUS_PULSE_DMPAC_OUT_1_SDE_BLK_DONE,Status write 1 to set for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
newline
bitfld.long 0x54 4. "STATUS_PULSE_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x54 3. "STATUS_PULSE_DMPAC_OUT_1_DOF_WRITE_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_write_error" "0,1"
newline
bitfld.long 0x54 2. "STATUS_PULSE_DMPAC_OUT_1_DOF_READ_ERROR,Status write 1 to set for pulse_dmpac_out_1_en_dof_read_error" "0,1"
newline
bitfld.long 0x54 1. "STATUS_PULSE_DMPAC_OUT_1_DOF_FRAME_DONE,Status write 1 to set for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
newline
bitfld.long 0x54 0. "STATUS_PULSE_DMPAC_OUT_1_DOF_ROW_DONE,Status write 1 to set for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_1,Status Register 22"
bitfld.long 0x58 27. "STATUS_PULSE_DMPAC_OUT_1_TDONE_8,Status write 1 to set for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "STATUS_PULSE_DMPAC_OUT_1_TDONE_7,Status write 1 to set for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "STATUS_PULSE_DMPAC_OUT_1_TDONE_1,Status write 1 to set for pulse_dmpac_out_1_en_tdone_1" "0,1"
newline
bitfld.long 0x58 24. "STATUS_PULSE_DMPAC_OUT_1_TDONE_0,Status write 1 to set for pulse_dmpac_out_1_en_tdone_0" "0,1"
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rbitfld.long 0x58 19. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_1_L,Status for pulse_dmpac_out_1_en_spare_pend_1_l" "0,1"
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rbitfld.long 0x58 18. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_1_P,Status for pulse_dmpac_out_1_en_spare_pend_1_p" "0,1"
newline
rbitfld.long 0x58 17. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_0_L,Status for pulse_dmpac_out_1_en_spare_pend_0_l" "0,1"
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rbitfld.long 0x58 16. "STATUS_PULSE_DMPAC_OUT_1_SPARE_PEND_0_P,Status for pulse_dmpac_out_1_en_spare_pend_0_p" "0,1"
newline
bitfld.long 0x58 9. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x58 8. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x58 3. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x58 0. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_2,Status Register 23"
bitfld.long 0x5C 3. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x5C 1. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x5C 0. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_3,Status Register 24"
bitfld.long 0x60 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_31" "0,1"
newline
bitfld.long 0x60 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_30" "0,1"
newline
bitfld.long 0x60 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_29" "0,1"
newline
bitfld.long 0x60 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_28" "0,1"
newline
bitfld.long 0x60 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_27" "0,1"
newline
bitfld.long 0x60 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_26" "0,1"
newline
bitfld.long 0x60 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_25" "0,1"
newline
bitfld.long 0x60 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_24" "0,1"
newline
bitfld.long 0x60 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_23" "0,1"
newline
bitfld.long 0x60 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_22" "0,1"
newline
bitfld.long 0x60 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_21" "0,1"
newline
bitfld.long 0x60 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_20" "0,1"
newline
bitfld.long 0x60 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_19" "0,1"
newline
bitfld.long 0x60 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_18" "0,1"
newline
bitfld.long 0x60 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_17" "0,1"
newline
bitfld.long 0x60 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_16" "0,1"
newline
bitfld.long 0x60 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_15" "0,1"
newline
bitfld.long 0x60 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x60 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_13" "0,1"
newline
bitfld.long 0x60 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_12" "0,1"
newline
bitfld.long 0x60 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_11" "0,1"
newline
bitfld.long 0x60 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x60 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_9" "0,1"
newline
bitfld.long 0x60 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_8" "0,1"
newline
bitfld.long 0x60 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_7" "0,1"
newline
bitfld.long 0x60 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_6" "0,1"
newline
bitfld.long 0x60 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x60 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_4" "0,1"
newline
bitfld.long 0x60 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_3" "0,1"
newline
bitfld.long 0x60 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x60 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x60 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_4,Status Register 25"
bitfld.long 0x64 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
newline
bitfld.long 0x64 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
newline
bitfld.long 0x64 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
newline
bitfld.long 0x64 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x64 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
newline
bitfld.long 0x64 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
newline
bitfld.long 0x64 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
newline
bitfld.long 0x64 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
newline
bitfld.long 0x64 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
newline
bitfld.long 0x64 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
newline
bitfld.long 0x64 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
newline
bitfld.long 0x64 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
newline
bitfld.long 0x64 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
newline
bitfld.long 0x64 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
newline
bitfld.long 0x64 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
newline
bitfld.long 0x64 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
newline
bitfld.long 0x64 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
newline
bitfld.long 0x64 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
newline
bitfld.long 0x64 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
newline
bitfld.long 0x64 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
newline
bitfld.long 0x64 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
newline
bitfld.long 0x64 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
newline
bitfld.long 0x64 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
newline
bitfld.long 0x64 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
newline
bitfld.long 0x64 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
newline
bitfld.long 0x64 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
newline
bitfld.long 0x64 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
newline
bitfld.long 0x64 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
newline
bitfld.long 0x64 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
newline
bitfld.long 0x64 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
newline
bitfld.long 0x64 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
newline
bitfld.long 0x64 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_5,Status Register 26"
bitfld.long 0x68 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
newline
bitfld.long 0x68 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
newline
bitfld.long 0x68 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x68 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x68 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
newline
bitfld.long 0x68 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
newline
bitfld.long 0x68 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
newline
bitfld.long 0x68 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
newline
bitfld.long 0x68 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
newline
bitfld.long 0x68 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
newline
bitfld.long 0x68 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
newline
bitfld.long 0x68 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
newline
bitfld.long 0x68 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
newline
bitfld.long 0x68 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
newline
bitfld.long 0x68 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
newline
bitfld.long 0x68 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
newline
bitfld.long 0x68 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
newline
bitfld.long 0x68 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
newline
bitfld.long 0x68 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
newline
bitfld.long 0x68 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
newline
bitfld.long 0x68 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
newline
bitfld.long 0x68 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
newline
bitfld.long 0x68 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
newline
bitfld.long 0x68 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
newline
bitfld.long 0x68 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
newline
bitfld.long 0x68 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
newline
bitfld.long 0x68 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
newline
bitfld.long 0x68 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
newline
bitfld.long 0x68 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
newline
bitfld.long 0x68 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
newline
bitfld.long 0x68 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
newline
bitfld.long 0x68 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0,Status write 1 to set for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_STATUS_REG_PULSE_DMPAC_OUT_1_6,Status Register 27"
bitfld.long 0x6C 1. "STATUS_PULSE_DMPAC_OUT_1_CTM_PULSE,Status write 1 to set for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x6C 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_PROT_ERR,Status write 1 to set for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
group.long 0x700++0x6F
line.long 0x00 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_0,Status Clear Register 0"
bitfld.long 0x00 25. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 24. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
newline
bitfld.long 0x00 22. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "STATUS_LEVEL_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_DMPAC_OUT_0_SDE_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_write_error" "0,1"
newline
bitfld.long 0x00 18. "STATUS_LEVEL_DMPAC_OUT_0_SDE_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_read_error" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_DMPAC_OUT_0_SDE_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_frame_done" "0,1"
newline
bitfld.long 0x00 16. "STATUS_LEVEL_DMPAC_OUT_0_SDE_BLK_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_sde_blk_done" "0,1"
newline
bitfld.long 0x00 4. "STATUS_LEVEL_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_DMPAC_OUT_0_DOF_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_write_error" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_DMPAC_OUT_0_DOF_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_read_error" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_DMPAC_OUT_0_DOF_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_frame_done" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_DMPAC_OUT_0_DOF_ROW_DONE_CLR,Status write 1 to clear for level_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x04 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_1,Status Clear Register 1"
bitfld.long 0x04 27. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_8" "0,1"
newline
bitfld.long 0x04 26. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_7" "0,1"
newline
bitfld.long 0x04 25. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_1" "0,1"
newline
bitfld.long 0x04 24. "STATUS_LEVEL_DMPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x04 9. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x04 8. "STATUS_LEVEL_DMPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x04 3. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x04 2. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x04 1. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_LEVEL_DMPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x08 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_2,Status Clear Register 2"
bitfld.long 0x08 3. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
newline
bitfld.long 0x08 2. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
newline
bitfld.long 0x08 1. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
newline
bitfld.long 0x08 0. "STATUS_LEVEL_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x0C "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_3,Status Clear Register 3"
bitfld.long 0x0C 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x0C 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x0C 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x0C 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x0C 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x0C 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_26" "0,1"
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bitfld.long 0x0C 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x0C 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x0C 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_23" "0,1"
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bitfld.long 0x0C 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x0C 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_21" "0,1"
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bitfld.long 0x0C 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_20" "0,1"
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bitfld.long 0x0C 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_19" "0,1"
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bitfld.long 0x0C 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_18" "0,1"
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bitfld.long 0x0C 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_17" "0,1"
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bitfld.long 0x0C 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_16" "0,1"
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bitfld.long 0x0C 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_15" "0,1"
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bitfld.long 0x0C 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_14" "0,1"
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bitfld.long 0x0C 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_13" "0,1"
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bitfld.long 0x0C 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_12" "0,1"
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bitfld.long 0x0C 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_11" "0,1"
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bitfld.long 0x0C 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_10" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_9" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_8" "0,1"
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bitfld.long 0x0C 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_7" "0,1"
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bitfld.long 0x0C 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_6" "0,1"
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bitfld.long 0x0C 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_5" "0,1"
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bitfld.long 0x0C 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_4" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_3" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_2" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_ERROR_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x10 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_4,Status Clear Register 4"
bitfld.long 0x10 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_31" "0,1"
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bitfld.long 0x10 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_30" "0,1"
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bitfld.long 0x10 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_29" "0,1"
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bitfld.long 0x10 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_28" "0,1"
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bitfld.long 0x10 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_27" "0,1"
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bitfld.long 0x10 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_26" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_25" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_24" "0,1"
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bitfld.long 0x10 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_23" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_22" "0,1"
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bitfld.long 0x10 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_21" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_20" "0,1"
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bitfld.long 0x10 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_19" "0,1"
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bitfld.long 0x10 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_18" "0,1"
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bitfld.long 0x10 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_17" "0,1"
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bitfld.long 0x10 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_16" "0,1"
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bitfld.long 0x10 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_15" "0,1"
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bitfld.long 0x10 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_14" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_13" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_12" "0,1"
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bitfld.long 0x10 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_11" "0,1"
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bitfld.long 0x10 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_10" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_9" "0,1"
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bitfld.long 0x10 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_8" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_7" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_6" "0,1"
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bitfld.long 0x10 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_5" "0,1"
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bitfld.long 0x10 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_COMPLETE_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x14 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_5,Status Clear Register 5"
bitfld.long 0x14 31. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x14 30. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x14 29. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x14 28. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x14 27. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x14 26. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x14 25. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x14 24. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x18 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_0_6,Status Clear Register 6"
bitfld.long 0x18 1. "STATUS_LEVEL_DMPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for level_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x18 0. "STATUS_LEVEL_DMPAC_OUT_0_DRU_PROT_ERR_CLR,Status write 1 to clear for level_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x1C "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_0,Status Clear Register 7"
bitfld.long 0x1C 25. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x1C 24. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x1C 23. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x1C 22. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x1C 21. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x1C 20. "STATUS_LEVEL_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for level_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x1C 19. "STATUS_LEVEL_DMPAC_OUT_1_SDE_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x1C 18. "STATUS_LEVEL_DMPAC_OUT_1_SDE_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x1C 17. "STATUS_LEVEL_DMPAC_OUT_1_SDE_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x1C 16. "STATUS_LEVEL_DMPAC_OUT_1_SDE_BLK_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x1C 4. "STATUS_LEVEL_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x1C 3. "STATUS_LEVEL_DMPAC_OUT_1_DOF_WRITE_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x1C 2. "STATUS_LEVEL_DMPAC_OUT_1_DOF_READ_ERROR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x1C 1. "STATUS_LEVEL_DMPAC_OUT_1_DOF_FRAME_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x1C 0. "STATUS_LEVEL_DMPAC_OUT_1_DOF_ROW_DONE_CLR,Status write 1 to clear for level_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x20 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_1,Status Clear Register 8"
bitfld.long 0x20 27. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x20 26. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x20 25. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x20 24. "STATUS_LEVEL_DMPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x20 9. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x20 8. "STATUS_LEVEL_DMPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x20 3. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x20 2. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x20 1. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x20 0. "STATUS_LEVEL_DMPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x24 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_2,Status Clear Register 9"
bitfld.long 0x24 3. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x24 2. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x24 1. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x24 0. "STATUS_LEVEL_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x28 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_3,Status Clear Register 10"
bitfld.long 0x28 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x28 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x28 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x28 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x28 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x28 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x28 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x28 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x28 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x28 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x28 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x28 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x28 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x28 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x28 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x28 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x28 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x28 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x28 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x28 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x28 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x28 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x28 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x28 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x28 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x28 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x28 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x28 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x28 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x28 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x28 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x28 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_ERROR_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x2C "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_4,Status Clear Register 11"
bitfld.long 0x2C 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x2C 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x2C 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x2C 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x2C 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x2C 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x2C 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x2C 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x2C 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x2C 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x2C 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x2C 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x2C 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x2C 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x2C 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x2C 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_16" "0,1"
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bitfld.long 0x2C 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_15" "0,1"
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bitfld.long 0x2C 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_14" "0,1"
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bitfld.long 0x2C 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_13" "0,1"
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bitfld.long 0x2C 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_12" "0,1"
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bitfld.long 0x2C 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_11" "0,1"
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bitfld.long 0x2C 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_10" "0,1"
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bitfld.long 0x2C 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_9" "0,1"
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bitfld.long 0x2C 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_8" "0,1"
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bitfld.long 0x2C 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x2C 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_6" "0,1"
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bitfld.long 0x2C 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x2C 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x2C 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x2C 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x2C 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x2C 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_COMPLETE_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x30 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_5,Status Clear Register 12"
bitfld.long 0x30 31. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x30 30. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x30 29. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x30 28. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x30 27. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x30 26. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x30 25. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x30 24. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x30 23. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x30 22. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x30 21. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x30 20. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x30 19. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x30 18. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x30 17. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x30 16. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x30 15. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x30 14. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x30 13. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x30 12. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x30 11. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x30 10. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x30 9. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x30 8. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x30 7. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x30 6. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x30 5. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x30 4. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x30 3. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x30 2. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x30 1. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x30 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x34 "DMPAC_INTD_STATUS_CLR_REG_LEVEL_DMPAC_OUT_1_6,Status Clear Register 13"
bitfld.long 0x34 1. "STATUS_LEVEL_DMPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for level_dmpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x34 0. "STATUS_LEVEL_DMPAC_OUT_1_DRU_PROT_ERR_CLR,Status write 1 to clear for level_dmpac_out_1_en_dru_prot_err" "0,1"
line.long 0x38 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_0,Status Clear Register 14"
bitfld.long 0x38 25. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x38 24. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x38 23. "STATUS_PULSE_DMPAC_OUT_0_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x38 22. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x38 21. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x38 20. "STATUS_PULSE_DMPAC_OUT_0_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x38 19. "STATUS_PULSE_DMPAC_OUT_0_SDE_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_write_error" "0,1"
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bitfld.long 0x38 18. "STATUS_PULSE_DMPAC_OUT_0_SDE_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_read_error" "0,1"
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bitfld.long 0x38 17. "STATUS_PULSE_DMPAC_OUT_0_SDE_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_frame_done" "0,1"
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bitfld.long 0x38 16. "STATUS_PULSE_DMPAC_OUT_0_SDE_BLK_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_sde_blk_done" "0,1"
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bitfld.long 0x38 4. "STATUS_PULSE_DMPAC_OUT_0_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x38 3. "STATUS_PULSE_DMPAC_OUT_0_DOF_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_write_error" "0,1"
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bitfld.long 0x38 2. "STATUS_PULSE_DMPAC_OUT_0_DOF_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_read_error" "0,1"
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bitfld.long 0x38 1. "STATUS_PULSE_DMPAC_OUT_0_DOF_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_frame_done" "0,1"
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bitfld.long 0x38 0. "STATUS_PULSE_DMPAC_OUT_0_DOF_ROW_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dof_row_done" "0,1"
line.long 0x3C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_1,Status Clear Register 15"
bitfld.long 0x3C 27. "STATUS_PULSE_DMPAC_OUT_0_TDONE_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_8" "0,1"
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bitfld.long 0x3C 26. "STATUS_PULSE_DMPAC_OUT_0_TDONE_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_7" "0,1"
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bitfld.long 0x3C 25. "STATUS_PULSE_DMPAC_OUT_0_TDONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_1" "0,1"
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bitfld.long 0x3C 24. "STATUS_PULSE_DMPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0x3C 9. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x3C 8. "STATUS_PULSE_DMPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0x3C 3. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x3C 2. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x3C 1. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x3C 0. "STATUS_PULSE_DMPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_pipe_done_0" "0,1"
line.long 0x40 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_2,Status Clear Register 16"
bitfld.long 0x40 3. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x40 2. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x40 1. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x40 0. "STATUS_PULSE_DMPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_watchdogtimer_err_0" "0,1"
line.long 0x44 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_3,Status Clear Register 17"
bitfld.long 0x44 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_31" "0,1"
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bitfld.long 0x44 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_30" "0,1"
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bitfld.long 0x44 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_29" "0,1"
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bitfld.long 0x44 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_28" "0,1"
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bitfld.long 0x44 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_27" "0,1"
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bitfld.long 0x44 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_26" "0,1"
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bitfld.long 0x44 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_25" "0,1"
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bitfld.long 0x44 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_24" "0,1"
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bitfld.long 0x44 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_23" "0,1"
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bitfld.long 0x44 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_22" "0,1"
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bitfld.long 0x44 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_21" "0,1"
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bitfld.long 0x44 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_20" "0,1"
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bitfld.long 0x44 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_19" "0,1"
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bitfld.long 0x44 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_18" "0,1"
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bitfld.long 0x44 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_17" "0,1"
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bitfld.long 0x44 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_16" "0,1"
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bitfld.long 0x44 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_15" "0,1"
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bitfld.long 0x44 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_14" "0,1"
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bitfld.long 0x44 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_13" "0,1"
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bitfld.long 0x44 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_12" "0,1"
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bitfld.long 0x44 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_11" "0,1"
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bitfld.long 0x44 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_10" "0,1"
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bitfld.long 0x44 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_9" "0,1"
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bitfld.long 0x44 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_8" "0,1"
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bitfld.long 0x44 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_7" "0,1"
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bitfld.long 0x44 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_6" "0,1"
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bitfld.long 0x44 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_5" "0,1"
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bitfld.long 0x44 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_4" "0,1"
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bitfld.long 0x44 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_3" "0,1"
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bitfld.long 0x44 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_2" "0,1"
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bitfld.long 0x44 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_1" "0,1"
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bitfld.long 0x44 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_ERROR_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_error_0" "0,1"
line.long 0x48 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_4,Status Clear Register 18"
bitfld.long 0x48 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_31" "0,1"
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bitfld.long 0x48 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_30" "0,1"
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bitfld.long 0x48 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_29" "0,1"
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bitfld.long 0x48 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_28" "0,1"
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bitfld.long 0x48 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_27" "0,1"
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bitfld.long 0x48 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_26" "0,1"
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bitfld.long 0x48 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_25" "0,1"
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bitfld.long 0x48 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_24" "0,1"
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bitfld.long 0x48 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_23" "0,1"
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bitfld.long 0x48 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_22" "0,1"
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bitfld.long 0x48 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_21" "0,1"
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bitfld.long 0x48 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_20" "0,1"
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bitfld.long 0x48 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_19" "0,1"
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bitfld.long 0x48 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_18" "0,1"
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bitfld.long 0x48 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_17" "0,1"
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bitfld.long 0x48 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_16" "0,1"
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bitfld.long 0x48 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_15" "0,1"
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bitfld.long 0x48 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_14" "0,1"
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bitfld.long 0x48 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_13" "0,1"
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bitfld.long 0x48 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_12" "0,1"
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bitfld.long 0x48 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_11" "0,1"
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bitfld.long 0x48 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_10" "0,1"
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bitfld.long 0x48 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_9" "0,1"
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bitfld.long 0x48 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_8" "0,1"
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bitfld.long 0x48 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_7" "0,1"
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bitfld.long 0x48 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_6" "0,1"
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bitfld.long 0x48 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_5" "0,1"
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bitfld.long 0x48 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_4" "0,1"
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bitfld.long 0x48 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_3" "0,1"
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bitfld.long 0x48 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_2" "0,1"
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bitfld.long 0x48 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_1" "0,1"
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bitfld.long 0x48 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_COMPLETE_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_complete_0" "0,1"
line.long 0x4C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_5,Status Clear Register 19"
bitfld.long 0x4C 31. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x4C 30. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x4C 29. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x4C 28. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_28" "0,1"
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bitfld.long 0x4C 27. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x4C 26. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x4C 25. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x4C 24. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x4C 23. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x4C 22. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x4C 21. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x4C 20. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x4C 19. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x4C 18. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x4C 17. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x4C 16. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x4C 15. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x4C 14. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x4C 13. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x4C 12. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x4C 11. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x4C 10. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x4C 9. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x4C 8. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x4C 7. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x4C 6. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x4C 5. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x4C 4. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x4C 3. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x4C 2. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x4C 1. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x4C 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_local_out_event_0" "0,1"
line.long 0x50 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_0_6,Status Clear Register 20"
bitfld.long 0x50 1. "STATUS_PULSE_DMPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x50 0. "STATUS_PULSE_DMPAC_OUT_0_DRU_PROT_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_0_en_dru_prot_err" "0,1"
line.long 0x54 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_0,Status Clear Register 21"
bitfld.long 0x54 25. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_sl2_wr_err" "0,1"
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bitfld.long 0x54 24. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_sl2_rd_err" "0,1"
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bitfld.long 0x54 23. "STATUS_PULSE_DMPAC_OUT_1_FOCO_1_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_1_fr_done_evt" "0,1"
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bitfld.long 0x54 22. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_sl2_wr_err" "0,1"
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bitfld.long 0x54 21. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_sl2_rd_err" "0,1"
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bitfld.long 0x54 20. "STATUS_PULSE_DMPAC_OUT_1_FOCO_0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_foco_0_fr_done_evt" "0,1"
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bitfld.long 0x54 19. "STATUS_PULSE_DMPAC_OUT_1_SDE_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_write_error" "0,1"
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bitfld.long 0x54 18. "STATUS_PULSE_DMPAC_OUT_1_SDE_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_read_error" "0,1"
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bitfld.long 0x54 17. "STATUS_PULSE_DMPAC_OUT_1_SDE_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_frame_done" "0,1"
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bitfld.long 0x54 16. "STATUS_PULSE_DMPAC_OUT_1_SDE_BLK_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_sde_blk_done" "0,1"
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bitfld.long 0x54 4. "STATUS_PULSE_DMPAC_OUT_1_DOF_MP0_RD_STATUS_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_mp0_rd_status_error" "0,1"
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bitfld.long 0x54 3. "STATUS_PULSE_DMPAC_OUT_1_DOF_WRITE_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_write_error" "0,1"
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bitfld.long 0x54 2. "STATUS_PULSE_DMPAC_OUT_1_DOF_READ_ERROR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_read_error" "0,1"
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bitfld.long 0x54 1. "STATUS_PULSE_DMPAC_OUT_1_DOF_FRAME_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_frame_done" "0,1"
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bitfld.long 0x54 0. "STATUS_PULSE_DMPAC_OUT_1_DOF_ROW_DONE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dof_row_done" "0,1"
line.long 0x58 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_1,Status Clear Register 22"
bitfld.long 0x58 27. "STATUS_PULSE_DMPAC_OUT_1_TDONE_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_8" "0,1"
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bitfld.long 0x58 26. "STATUS_PULSE_DMPAC_OUT_1_TDONE_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_7" "0,1"
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bitfld.long 0x58 25. "STATUS_PULSE_DMPAC_OUT_1_TDONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_1" "0,1"
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bitfld.long 0x58 24. "STATUS_PULSE_DMPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x58 9. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x58 8. "STATUS_PULSE_DMPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x58 3. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x58 2. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x58 1. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x58 0. "STATUS_PULSE_DMPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_pipe_done_0" "0,1"
line.long 0x5C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_2,Status Clear Register 23"
bitfld.long 0x5C 3. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_8" "0,1"
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bitfld.long 0x5C 2. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_7" "0,1"
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bitfld.long 0x5C 1. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_1" "0,1"
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bitfld.long 0x5C 0. "STATUS_PULSE_DMPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_watchdogtimer_err_0" "0,1"
line.long 0x60 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_3,Status Clear Register 24"
bitfld.long 0x60 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_31" "0,1"
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bitfld.long 0x60 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_30" "0,1"
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bitfld.long 0x60 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_29" "0,1"
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bitfld.long 0x60 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_28" "0,1"
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bitfld.long 0x60 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_27" "0,1"
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bitfld.long 0x60 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_26" "0,1"
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bitfld.long 0x60 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_25" "0,1"
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bitfld.long 0x60 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_24" "0,1"
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bitfld.long 0x60 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_23" "0,1"
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bitfld.long 0x60 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_22" "0,1"
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bitfld.long 0x60 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_21" "0,1"
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bitfld.long 0x60 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_20" "0,1"
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bitfld.long 0x60 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_19" "0,1"
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bitfld.long 0x60 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_18" "0,1"
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bitfld.long 0x60 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_17" "0,1"
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bitfld.long 0x60 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_16" "0,1"
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bitfld.long 0x60 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_15" "0,1"
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bitfld.long 0x60 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_14" "0,1"
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bitfld.long 0x60 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_13" "0,1"
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bitfld.long 0x60 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_12" "0,1"
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bitfld.long 0x60 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_11" "0,1"
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bitfld.long 0x60 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_10" "0,1"
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bitfld.long 0x60 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_9" "0,1"
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bitfld.long 0x60 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_8" "0,1"
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bitfld.long 0x60 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_7" "0,1"
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bitfld.long 0x60 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_6" "0,1"
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bitfld.long 0x60 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_5" "0,1"
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bitfld.long 0x60 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_4" "0,1"
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bitfld.long 0x60 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_3" "0,1"
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bitfld.long 0x60 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_2" "0,1"
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bitfld.long 0x60 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_1" "0,1"
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bitfld.long 0x60 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_ERROR_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_error_0" "0,1"
line.long 0x64 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_4,Status Clear Register 25"
bitfld.long 0x64 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_31" "0,1"
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bitfld.long 0x64 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_30" "0,1"
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bitfld.long 0x64 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_29" "0,1"
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bitfld.long 0x64 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_28" "0,1"
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bitfld.long 0x64 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_27" "0,1"
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bitfld.long 0x64 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_26" "0,1"
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bitfld.long 0x64 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_25" "0,1"
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bitfld.long 0x64 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_24" "0,1"
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bitfld.long 0x64 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_23" "0,1"
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bitfld.long 0x64 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_22" "0,1"
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bitfld.long 0x64 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_21" "0,1"
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bitfld.long 0x64 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_20" "0,1"
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bitfld.long 0x64 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_19" "0,1"
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bitfld.long 0x64 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_18" "0,1"
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bitfld.long 0x64 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_17" "0,1"
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bitfld.long 0x64 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_16" "0,1"
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bitfld.long 0x64 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_15" "0,1"
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bitfld.long 0x64 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_14" "0,1"
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bitfld.long 0x64 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_13" "0,1"
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bitfld.long 0x64 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_12" "0,1"
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bitfld.long 0x64 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_11" "0,1"
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bitfld.long 0x64 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_10" "0,1"
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bitfld.long 0x64 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_9" "0,1"
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bitfld.long 0x64 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_8" "0,1"
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bitfld.long 0x64 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_7" "0,1"
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bitfld.long 0x64 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_6" "0,1"
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bitfld.long 0x64 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_5" "0,1"
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bitfld.long 0x64 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_4" "0,1"
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bitfld.long 0x64 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_3" "0,1"
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bitfld.long 0x64 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_2" "0,1"
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bitfld.long 0x64 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_1" "0,1"
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bitfld.long 0x64 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_COMPLETE_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_complete_0" "0,1"
line.long 0x68 "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_5,Status Clear Register 26"
bitfld.long 0x68 31. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_31_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_31" "0,1"
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bitfld.long 0x68 30. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_30_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_30" "0,1"
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bitfld.long 0x68 29. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_29_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_29" "0,1"
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bitfld.long 0x68 28. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_28_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_28" "0,1"
newline
bitfld.long 0x68 27. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_27_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_27" "0,1"
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bitfld.long 0x68 26. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_26_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_26" "0,1"
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bitfld.long 0x68 25. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_25_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_25" "0,1"
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bitfld.long 0x68 24. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_24_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_24" "0,1"
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bitfld.long 0x68 23. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_23_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_23" "0,1"
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bitfld.long 0x68 22. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_22_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_22" "0,1"
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bitfld.long 0x68 21. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_21_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_21" "0,1"
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bitfld.long 0x68 20. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_20_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_20" "0,1"
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bitfld.long 0x68 19. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_19_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_19" "0,1"
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bitfld.long 0x68 18. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_18_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_18" "0,1"
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bitfld.long 0x68 17. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_17_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_17" "0,1"
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bitfld.long 0x68 16. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_16_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_16" "0,1"
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bitfld.long 0x68 15. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_15_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_15" "0,1"
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bitfld.long 0x68 14. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_14_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_14" "0,1"
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bitfld.long 0x68 13. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_13_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_13" "0,1"
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bitfld.long 0x68 12. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_12_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_12" "0,1"
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bitfld.long 0x68 11. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_11_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_11" "0,1"
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bitfld.long 0x68 10. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_10_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_10" "0,1"
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bitfld.long 0x68 9. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_9_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_9" "0,1"
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bitfld.long 0x68 8. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_8_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_8" "0,1"
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bitfld.long 0x68 7. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_7_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_7" "0,1"
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bitfld.long 0x68 6. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_6_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_6" "0,1"
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bitfld.long 0x68 5. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_5_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_5" "0,1"
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bitfld.long 0x68 4. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_4_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_4" "0,1"
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bitfld.long 0x68 3. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_3_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_3" "0,1"
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bitfld.long 0x68 2. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_2_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_2" "0,1"
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bitfld.long 0x68 1. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_1_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_1" "0,1"
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bitfld.long 0x68 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_LOCAL_OUT_EVENT_0_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_local_out_event_0" "0,1"
line.long 0x6C "DMPAC_INTD_STATUS_CLR_REG_PULSE_DMPAC_OUT_1_6,Status Clear Register 27"
bitfld.long 0x6C 1. "STATUS_PULSE_DMPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x6C 0. "STATUS_PULSE_DMPAC_OUT_1_DRU_PROT_ERR_CLR,Status write 1 to clear for pulse_dmpac_out_1_en_dru_prot_err" "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0xA88)++0x03
line.long 0x00 "DMPAC_INTD_INTR_VECTOR_REG_PULSE_DMPAC_OUT_$1,Interrupt Vector for pulse_dmpac_out_0"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0xA80)++0x03
line.long 0x00 "DMPAC_INTD_INTR_VECTOR_REG_LEVEL_DMPAC_OUT_$1,Interrupt Vector for level_dmpac_out_0"
repeat.end
tree.end
tree.end
tree "DMPAC_CTSET"
tree "DMPAC0_CTSET2_WRAP_CFG_CTSET2_CFG"
base ad:0xF400000
rgroup.long 0x20000++0x03
line.long 0x00 "DMPAC_CTSET_CTSETID,CTSET identification register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,The value 10b designates this as Processor Business Unit IP" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Function : Indicates a Debug IP (0x2nn) and 0x80 is the identifier for CT-SET"
bitfld.long 0x00 11.--15. "RTL_VERSION,This field changes on bug fix and resets to '0' when either Minor Revision or Major Revision field changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,Major Revision.This field changes when there is a major feature change" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device.0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,Minor Revision.This field changes when features are scaled up or down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20010++0x0F
line.long 0x00 "DMPAC_CTSET_CTSETSYSCFG,CTSET system configuration register"
bitfld.long 0x00 2.--3. "IDLEMODE,Sets the Idle Mode for CTSET (0=Force Idle 1=No Idle 2=Smart Idle 3= Smart Idle wakeup)" "?,No Idle,Smart Idle,Smart Idle wakeup)"
bitfld.long 0x00 0. "SOFTRESET,This will reset entire CTSET except the registers and the CFG interface.This bit is automatically cleared by hardware" "0,1"
line.long 0x04 "DMPAC_CTSET_SETSTR,CTSET status register"
bitfld.long 0x04 8. "HWFIFOEMPTY,System Event Trace FIFO status 1 is empty 0 means captured data not yet exported" "0,1"
bitfld.long 0x04 0. "RESETDONE,Reset status 0 means reset ongoing 1 indicates completed" "0,1"
line.long 0x08 "DMPAC_CTSET_DBGTIMELOW,The 32 low order bits of the debug time value supplied on the time input interface"
line.long 0x0C "DMPAC_CTSET_DBGTIMEHI,The 32 high order bits of the debug time value supplied on the time input interface"
group.long 0x20024++0x07
line.long 0x00 "DMPAC_CTSET_CTSETCFG,The 32 low order bits of the debug time value supplied on the time input interface The 32 high order bits of the debug time value supplied on the time input interface"
bitfld.long 0x00 28.--31. "CLAIM,Claim control and status.To program any bits other than" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "SYSEVENTCAPTEN,When 1 the System event capture is enabled" "0,1"
bitfld.long 0x00 4. "EVENTLEVEL,0 enables low level event detection 1 enables high level event detection" "0,1"
bitfld.long 0x00 3. "MSGMODE,Message generated based on event detection 0 is sampling window 1 is event detection" "0,1"
bitfld.long 0x00 2. "STOPCAPT,Stop capturing system events from external trigger detection" "0,1"
newline
bitfld.long 0x00 1. "STARTCAPT,Start capturing system events from external trigger detection" "0,1"
line.long 0x04 "DMPAC_CTSET_SETSPLREG,System Event Sampling Window register"
hexmask.long.byte 0x04 0.--7. 1. "WINDOWSIZE,System events sampling window size expressed as CTSET cycles"
group.long 0x20030++0x23
line.long 0x00 "DMPAC_CTSET_SETEVTENBL1,System event detection enable register 1"
bitfld.long 0x00 31. "EVENT32DETEN,Event(32) Detection Enable" "0,1"
bitfld.long 0x00 30. "EVENT31DETEN,Event(31) Detection Enable" "0,1"
bitfld.long 0x00 29. "EVENT30DETEN,Event(30) Detection Enable" "0,1"
bitfld.long 0x00 28. "EVENT29DETEN,Event(29) Detection Enable" "0,1"
bitfld.long 0x00 27. "EVENT28DETEN,Event(28) Detection Enable" "0,1"
newline
bitfld.long 0x00 26. "EVENT27DETEN,Event(27) Detection Enable" "0,1"
bitfld.long 0x00 25. "EVENT26DETEN,Event(26) Detection Enable" "0,1"
bitfld.long 0x00 24. "EVENT25DETEN,Event(25) Detection Enable" "0,1"
bitfld.long 0x00 23. "EVENT24DETEN,Event(24) Detection Enable" "0,1"
bitfld.long 0x00 22. "EVENT23DETEN,Event(23) Detection Enable" "0,1"
newline
bitfld.long 0x00 21. "EVENT22DETEN,Event(22) Detection Enable" "0,1"
bitfld.long 0x00 20. "EVENT21DETEN,Event(21) Detection Enable" "0,1"
bitfld.long 0x00 19. "EVENT20DETEN,Event(20) Detection Enable" "0,1"
bitfld.long 0x00 18. "EVENT19DETEN,Event(19) Detection Enable" "0,1"
bitfld.long 0x00 17. "EVENT18DETEN,Event(18) Detection Enable" "0,1"
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bitfld.long 0x00 16. "EVENT17DETEN,Event(17) Detection Enable" "0,1"
bitfld.long 0x00 15. "EVENT16DETEN,Event(16) Detection Enable" "0,1"
bitfld.long 0x00 14. "EVENT15DETEN,Event(15) Detection Enable" "0,1"
bitfld.long 0x00 13. "EVENT14DETEN,Event(14) Detection Enable" "0,1"
bitfld.long 0x00 12. "EVENT13DETEN,Event(13) Detection Enable" "0,1"
newline
bitfld.long 0x00 11. "EVENT12DETEN,Event(12) Detection Enable" "0,1"
bitfld.long 0x00 10. "EVENT11DETEN,Event(11) Detection Enable" "0,1"
bitfld.long 0x00 9. "EVENT10DETEN,Event(10) Detection Enable" "0,1"
bitfld.long 0x00 8. "EVENT9DETEN,Event(9) Detection Enable" "0,1"
bitfld.long 0x00 7. "EVENT8DETEN,Event(8) Detection Enable" "0,1"
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bitfld.long 0x00 6. "EVENT7DETEN,Event(7) Detection Enable" "0,1"
bitfld.long 0x00 5. "EVENT6DETEN,Event(6) Detection Enable" "0,1"
bitfld.long 0x00 4. "EVENT5DETEN,Event(5) Detection Enable" "0,1"
bitfld.long 0x00 3. "EVENT4DETEN,Event(4) Detection Enable" "0,1"
bitfld.long 0x00 2. "EVENT3DETEN,Event(3) Detection Enable" "0,1"
newline
bitfld.long 0x00 1. "EVENT2DETEN,Event(2) Detection Enable" "0,1"
bitfld.long 0x00 0. "EVENT1DETEN,Event(1) Detection Enable" "0,1"
line.long 0x04 "DMPAC_CTSET_SETEVTENBL2,System event detection enable register 2 (if number of events > 32)"
bitfld.long 0x04 31. "EVENT64DETEN,Event(64) Detection Enable" "0,1"
bitfld.long 0x04 30. "EVENT63DETEN,Event(63) Detection Enable" "0,1"
bitfld.long 0x04 29. "EVENT62DETEN,Event(62) Detection Enable" "0,1"
bitfld.long 0x04 28. "EVENT61DETEN,Event(61) Detection Enable" "0,1"
bitfld.long 0x04 27. "EVENT60DETEN,Event(60) Detection Enable" "0,1"
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bitfld.long 0x04 26. "EVENT59DETEN,Event(59) Detection Enable" "0,1"
bitfld.long 0x04 25. "EVENT58DETEN,Event(58) Detection Enable" "0,1"
bitfld.long 0x04 24. "EVENT57DETEN,Event(57) Detection Enable" "0,1"
bitfld.long 0x04 23. "EVENT56DETEN,Event(56) Detection Enable" "0,1"
bitfld.long 0x04 22. "EVENT55DETEN,Event(55) Detection Enable" "0,1"
newline
bitfld.long 0x04 21. "EVENT54DETEN,Event(54) Detection Enable" "0,1"
bitfld.long 0x04 20. "EVENT53DETEN,Event(53) Detection Enable" "0,1"
bitfld.long 0x04 19. "EVENT52DETEN,Event(52) Detection Enable" "0,1"
bitfld.long 0x04 18. "EVENT51DETEN,Event(51) Detection Enable" "0,1"
bitfld.long 0x04 17. "EVENT50DETEN,Event(50) Detection Enable" "0,1"
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bitfld.long 0x04 16. "EVENT49DETEN,Event(49) Detection Enable" "0,1"
bitfld.long 0x04 15. "EVENT48DETEN,Event(48) Detection Enable" "0,1"
bitfld.long 0x04 14. "EVENT47DETEN,Event(47) Detection Enable" "0,1"
bitfld.long 0x04 13. "EVENT46DETEN,Event(46) Detection Enable" "0,1"
bitfld.long 0x04 12. "EVENT45DETEN,Event(45) Detection Enable" "0,1"
newline
bitfld.long 0x04 11. "EVENT44DETEN,Event(44) Detection Enable" "0,1"
bitfld.long 0x04 10. "EVENT43DETEN,Event(43) Detection Enable" "0,1"
bitfld.long 0x04 9. "EVENT42DETEN,Event(42) Detection Enable" "0,1"
bitfld.long 0x04 8. "EVENT41DETEN,Event(41) Detection Enable" "0,1"
bitfld.long 0x04 7. "EVENT40DETEN,Event(40) Detection Enable" "0,1"
newline
bitfld.long 0x04 6. "EVENT39DETEN,Event(39) Detection Enable" "0,1"
bitfld.long 0x04 5. "EVENT38DETEN,Event(38) Detection Enable" "0,1"
bitfld.long 0x04 4. "EVENT37DETEN,Event(37) Detection Enable" "0,1"
bitfld.long 0x04 3. "EVENT36DETEN,Event(36) Detection Enable" "0,1"
bitfld.long 0x04 2. "EVENT35DETEN,Event(35) Detection Enable" "0,1"
newline
bitfld.long 0x04 1. "EVENT34DETEN,Event(34) Detection Enable" "0,1"
bitfld.long 0x04 0. "EVENT33DETEN,Event(33) Detection Enable" "0,1"
line.long 0x08 "DMPAC_CTSET_SETEVTENBL3,System event detection enable register 3 (if number of events > 64)"
bitfld.long 0x08 31. "EVENT96DETEN,Event(96) Detection Enable" "0,1"
bitfld.long 0x08 30. "EVENT95DETEN,Event(95) Detection Enable" "0,1"
bitfld.long 0x08 29. "EVENT94DETEN,Event(94) Detection Enable" "0,1"
bitfld.long 0x08 28. "EVENT93DETEN,Event(93) Detection Enable" "0,1"
bitfld.long 0x08 27. "EVENT92DETEN,Event(92) Detection Enable" "0,1"
newline
bitfld.long 0x08 26. "EVENT91DETEN,Event(91) Detection Enable" "0,1"
bitfld.long 0x08 25. "EVENT90DETEN,Event(90) Detection Enable" "0,1"
bitfld.long 0x08 24. "EVENT89DETEN,Event(89) Detection Enable" "0,1"
bitfld.long 0x08 23. "EVENT88DETEN,Event(88) Detection Enable" "0,1"
bitfld.long 0x08 22. "EVENT87DETEN,Event(87) Detection Enable" "0,1"
newline
bitfld.long 0x08 21. "EVENT86DETEN,Event(86) Detection Enable" "0,1"
bitfld.long 0x08 20. "EVENT85DETEN,Event(85) Detection Enable" "0,1"
bitfld.long 0x08 19. "EVENT84DETEN,Event(84) Detection Enable" "0,1"
bitfld.long 0x08 18. "EVENT83DETEN,Event(83) Detection Enable" "0,1"
bitfld.long 0x08 17. "EVENT82DETEN,Event(82) Detection Enable" "0,1"
newline
bitfld.long 0x08 16. "EVENT81DETEN,Event(81) Detection Enable" "0,1"
bitfld.long 0x08 15. "EVENT80DETEN,Event(80) Detection Enable" "0,1"
bitfld.long 0x08 14. "EVENT79DETEN,Event(79) Detection Enable" "0,1"
bitfld.long 0x08 13. "EVENT78DETEN,Event(78) Detection Enable" "0,1"
bitfld.long 0x08 12. "EVENT77DETEN,Event(77) Detection Enable" "0,1"
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bitfld.long 0x08 11. "EVENT76DETEN,Event(76) Detection Enable" "0,1"
bitfld.long 0x08 10. "EVENT75DETEN,Event(75) Detection Enable" "0,1"
bitfld.long 0x08 9. "EVENT74DETEN,Event(74) Detection Enable" "0,1"
bitfld.long 0x08 8. "EVENT73DETEN,Event(73) Detection Enable" "0,1"
bitfld.long 0x08 7. "EVENT72DETEN,Event(72) Detection Enable" "0,1"
newline
bitfld.long 0x08 6. "EVENT71DETEN,Event(71) Detection Enable" "0,1"
bitfld.long 0x08 5. "EVENT70DETEN,Event(70) Detection Enable" "0,1"
bitfld.long 0x08 4. "EVENT69DETEN,Event(69) Detection Enable" "0,1"
bitfld.long 0x08 3. "EVENT68DETEN,Event(68) Detection Enable" "0,1"
bitfld.long 0x08 2. "EVENT67DETEN,Event(67) Detection Enable" "0,1"
newline
bitfld.long 0x08 1. "EVENT66DETEN,Event(66) Detection Enable" "0,1"
bitfld.long 0x08 0. "EVENT65DETEN,Event(65) Detection Enable" "0,1"
line.long 0x0C "DMPAC_CTSET_SETEVTENBL4,System event detection enable register 4 (if number of events > 96)"
bitfld.long 0x0C 31. "EVENT128DETEN,Event(128) Detection Enable" "0,1"
bitfld.long 0x0C 30. "EVENT127DETEN,Event(127) Detection Enable" "0,1"
bitfld.long 0x0C 29. "EVENT126DETEN,Event(126) Detection Enable" "0,1"
bitfld.long 0x0C 28. "EVENT125DETEN,Event(125) Detection Enable" "0,1"
bitfld.long 0x0C 27. "EVENT124DETEN,Event(124) Detection Enable" "0,1"
newline
bitfld.long 0x0C 26. "EVENT123DETEN,Event(123) Detection Enable" "0,1"
bitfld.long 0x0C 25. "EVENT122DETEN,Event(122) Detection Enable" "0,1"
bitfld.long 0x0C 24. "EVENT121DETEN,Event(121) Detection Enable" "0,1"
bitfld.long 0x0C 23. "EVENT120DETEN,Event(120) Detection Enable" "0,1"
bitfld.long 0x0C 22. "EVENT119DETEN,Event(119) Detection Enable" "0,1"
newline
bitfld.long 0x0C 21. "EVENT118DETEN,Event(118) Detection Enable" "0,1"
bitfld.long 0x0C 20. "EVENT117DETEN,Event(117) Detection Enable" "0,1"
bitfld.long 0x0C 19. "EVENT116DETEN,Event(116) Detection Enable" "0,1"
bitfld.long 0x0C 18. "EVENT115DETEN,Event(115) Detection Enable" "0,1"
bitfld.long 0x0C 17. "EVENT114DETEN,Event(114) Detection Enable" "0,1"
newline
bitfld.long 0x0C 16. "EVENT113DETEN,Event(113) Detection Enable" "0,1"
bitfld.long 0x0C 15. "EVENT112DETEN,Event(112) Detection Enable" "0,1"
bitfld.long 0x0C 14. "EVENT111DETEN,Event(111) Detection Enable" "0,1"
bitfld.long 0x0C 13. "EVENT110DETEN,Event(110) Detection Enable" "0,1"
bitfld.long 0x0C 12. "EVENT109DETEN,Event(109) Detection Enable" "0,1"
newline
bitfld.long 0x0C 11. "EVENT108DETEN,Event(108) Detection Enable" "0,1"
bitfld.long 0x0C 10. "EVENT107DETEN,Event(107) Detection Enable" "0,1"
bitfld.long 0x0C 9. "EVENT106DETEN,Event(106) Detection Enable" "0,1"
bitfld.long 0x0C 8. "EVENT105DETEN,Event(105) Detection Enable" "0,1"
bitfld.long 0x0C 7. "EVENT104DETEN,Event(104) Detection Enable" "0,1"
newline
bitfld.long 0x0C 6. "EVENT103DETEN,Event(103) Detection Enable" "0,1"
bitfld.long 0x0C 5. "EVENT102DETEN,Event(102) Detection Enable" "0,1"
bitfld.long 0x0C 4. "EVENT101DETEN,Event(101) Detection Enable" "0,1"
bitfld.long 0x0C 3. "EVENT100DETEN,Event(100) Detection Enable" "0,1"
bitfld.long 0x0C 2. "EVENT99DETEN,Event(99) Detection Enable" "0,1"
newline
bitfld.long 0x0C 1. "EVENT98DETEN,Event(98) Detection Enable" "0,1"
bitfld.long 0x0C 0. "EVENT97DETEN,Event(97) Detection Enable" "0,1"
line.long 0x10 "DMPAC_CTSET_SETEVTENBL5,System event detection enable register 5 (if number of events > 128)"
bitfld.long 0x10 31. "EVENT160DETEN,Event(160) Detection Enable" "0,1"
bitfld.long 0x10 30. "EVENT159DETEN,Event(159) Detection Enable" "0,1"
bitfld.long 0x10 29. "EVENT158DETEN,Event(158) Detection Enable" "0,1"
bitfld.long 0x10 28. "EVENT157DETEN,Event(157) Detection Enable" "0,1"
bitfld.long 0x10 27. "EVENT156DETEN,Event(156) Detection Enable" "0,1"
newline
bitfld.long 0x10 26. "EVENT155DETEN,Event(155) Detection Enable" "0,1"
bitfld.long 0x10 25. "EVENT154DETEN,Event(154) Detection Enable" "0,1"
bitfld.long 0x10 24. "EVENT153DETEN,Event(153) Detection Enable" "0,1"
bitfld.long 0x10 23. "EVENT152DETEN,Event(152) Detection Enable" "0,1"
bitfld.long 0x10 22. "EVENT151DETEN,Event(151) Detection Enable" "0,1"
newline
bitfld.long 0x10 21. "EVENT150DETEN,Event(150) Detection Enable" "0,1"
bitfld.long 0x10 20. "EVENT149DETEN,Event(149) Detection Enable" "0,1"
bitfld.long 0x10 19. "EVENT148DETEN,Event(148) Detection Enable" "0,1"
bitfld.long 0x10 18. "EVENT147DETEN,Event(147) Detection Enable" "0,1"
bitfld.long 0x10 17. "EVENT1468DETEN,Event(146) Detection Enable" "0,1"
newline
bitfld.long 0x10 16. "EVENT145DETEN,Event(145) Detection Enable" "0,1"
bitfld.long 0x10 15. "EVENT144DETEN,Event(144) Detection Enable" "0,1"
bitfld.long 0x10 14. "EVENT143DETEN,Event(143) Detection Enable" "0,1"
bitfld.long 0x10 13. "EVENT142DETEN,Event(142) Detection Enable" "0,1"
bitfld.long 0x10 12. "EVENT141DETEN,Event(141) Detection Enable" "0,1"
newline
bitfld.long 0x10 11. "EVENT140DETEN,Event(140) Detection Enable" "0,1"
bitfld.long 0x10 10. "EVENT139DETEN,Event(139) Detection Enable" "0,1"
bitfld.long 0x10 9. "EVENT138DETEN,Event(138) Detection Enable" "0,1"
bitfld.long 0x10 8. "EVENT137DETEN,Event(137) Detection Enable" "0,1"
bitfld.long 0x10 7. "EVENT136DETEN,Event(136) Detection Enable" "0,1"
newline
bitfld.long 0x10 6. "EVENT135DETEN,Event(135) Detection Enable" "0,1"
bitfld.long 0x10 5. "EVENT134DETEN,Event(134) Detection Enable" "0,1"
bitfld.long 0x10 4. "EVENT133DETEN,Event(133) Detection Enable" "0,1"
bitfld.long 0x10 3. "EVENT132DETEN,Event(132) Detection Enable" "0,1"
bitfld.long 0x10 2. "EVENT131DETEN,Event(131) Detection Enable" "0,1"
newline
bitfld.long 0x10 1. "EVENT130DETEN,Event(130) Detection Enable" "0,1"
bitfld.long 0x10 0. "EVENT129DETEN,Event(129) Detection Enable" "0,1"
line.long 0x14 "DMPAC_CTSET_SETEVTENBL6,System event detection enable register 6 (if number of events > 160)"
bitfld.long 0x14 31. "EVENT192DETEN,Event(192) Detection Enable" "0,1"
bitfld.long 0x14 30. "EVENT191DETEN,Event(191) Detection Enable" "0,1"
bitfld.long 0x14 29. "EVENT190DETEN,Event(190) Detection Enable" "0,1"
bitfld.long 0x14 28. "EVENT189DETEN,Event(189) Detection Enable" "0,1"
bitfld.long 0x14 27. "EVENT188DETEN,Event(188) Detection Enable" "0,1"
newline
bitfld.long 0x14 26. "EVENT187DETEN,Event(187) Detection Enable" "0,1"
bitfld.long 0x14 25. "EVENT186DETEN,Event(186) Detection Enable" "0,1"
bitfld.long 0x14 24. "EVENT185DETEN,Event(185) Detection Enable" "0,1"
bitfld.long 0x14 23. "EVENT184DETEN,Event(184) Detection Enable" "0,1"
bitfld.long 0x14 22. "EVENT183DETEN,Event(183) Detection Enable" "0,1"
newline
bitfld.long 0x14 21. "EVENT182DETEN,Event(182) Detection Enable" "0,1"
bitfld.long 0x14 20. "EVENT181DETEN,Event(181) Detection Enable" "0,1"
bitfld.long 0x14 19. "EVENT180DETEN,Event(180) Detection Enable" "0,1"
bitfld.long 0x14 18. "EVENT179DETEN,Event(179) Detection Enable" "0,1"
bitfld.long 0x14 17. "EVENT178DETEN,Event(178) Detection Enable" "0,1"
newline
bitfld.long 0x14 16. "EVENT177DETEN,Event(177) Detection Enable" "0,1"
bitfld.long 0x14 15. "EVENT176DETEN,Event(176) Detection Enable" "0,1"
bitfld.long 0x14 14. "EVENT175DETEN,Event(175) Detection Enable" "0,1"
bitfld.long 0x14 13. "EVENT174DETEN,Event(174) Detection Enable" "0,1"
bitfld.long 0x14 12. "EVENT173DETEN,Event(173) Detection Enable" "0,1"
newline
bitfld.long 0x14 11. "EVENT172DETEN,Event(172) Detection Enable" "0,1"
bitfld.long 0x14 10. "EVENT171DETEN,Event(171) Detection Enable" "0,1"
bitfld.long 0x14 9. "EVENT170DETEN,Event(170) Detection Enable" "0,1"
bitfld.long 0x14 8. "EVENT169DETEN,Event(169) Detection Enable" "0,1"
bitfld.long 0x14 7. "EVENT168DETEN,Event(168) Detection Enable" "0,1"
newline
bitfld.long 0x14 6. "EVENT167DETEN,Event(167) Detection Enable" "0,1"
bitfld.long 0x14 5. "EVENT166DETEN,Event(166) Detection Enable" "0,1"
bitfld.long 0x14 4. "EVENT165DETEN,Event(165) Detection Enable" "0,1"
bitfld.long 0x14 3. "EVENT164DETEN,Event(164) Detection Enable" "0,1"
bitfld.long 0x14 2. "EVENT163DETEN,Event(163) Detection Enable" "0,1"
newline
bitfld.long 0x14 1. "EVENT162DETEN,Event(162) Detection Enable" "0,1"
bitfld.long 0x14 0. "EVENT161DETEN,Event(161) Detection Enable" "0,1"
line.long 0x18 "DMPAC_CTSET_SETEVTENBL7,System event detection enable register 7 (if number of events > 192)"
bitfld.long 0x18 31. "EVENT224DETEN,Event(224) Detection Enable" "0,1"
bitfld.long 0x18 30. "EVENT223DETEN,Event(223) Detection Enable" "0,1"
bitfld.long 0x18 29. "EVENT222DETEN,Event(222) Detection Enable" "0,1"
bitfld.long 0x18 28. "EVENT221DETEN,Event(221) Detection Enable" "0,1"
bitfld.long 0x18 27. "EVENT220DETEN,Event(220) Detection Enable" "0,1"
newline
bitfld.long 0x18 26. "EVENT219DETEN,Event(219) Detection Enable" "0,1"
bitfld.long 0x18 25. "EVENT218DETEN,Event(218) Detection Enable" "0,1"
bitfld.long 0x18 24. "EVENT217DETEN,Event(217) Detection Enable" "0,1"
bitfld.long 0x18 23. "EVENT216DETEN,Event(216) Detection Enable" "0,1"
bitfld.long 0x18 22. "EVENT215DETEN,Event(215) Detection Enable" "0,1"
newline
bitfld.long 0x18 21. "EVENT214DETEN,Event(214) Detection Enable" "0,1"
bitfld.long 0x18 20. "EVENT213DETEN,Event(213) Detection Enable" "0,1"
bitfld.long 0x18 19. "EVENT212DETEN,Event(212) Detection Enable" "0,1"
bitfld.long 0x18 18. "EVENT211DETEN,Event(211) Detection Enable" "0,1"
bitfld.long 0x18 17. "EVENT210DETEN,Event(210) Detection Enable" "0,1"
newline
bitfld.long 0x18 16. "EVENT209DETEN,Event(209) Detection Enable" "0,1"
bitfld.long 0x18 15. "EVENT208DETEN,Event(208) Detection Enable" "0,1"
bitfld.long 0x18 14. "EVENT207DETEN,Event(207) Detection Enable" "0,1"
bitfld.long 0x18 13. "EVENT206DETEN,Event(206) Detection Enable" "0,1"
bitfld.long 0x18 12. "EVENT205DETEN,Event(205) Detection Enable" "0,1"
newline
bitfld.long 0x18 11. "EVENT204DETEN,Event(204) Detection Enable" "0,1"
bitfld.long 0x18 10. "EVENT203DETEN,Event(203) Detection Enable" "0,1"
bitfld.long 0x18 9. "EVENT202DETEN,Event(202) Detection Enable" "0,1"
bitfld.long 0x18 8. "EVENT201DETEN,Event(201) Detection Enable" "0,1"
bitfld.long 0x18 7. "EVENT200DETEN,Event(200) Detection Enable" "0,1"
newline
bitfld.long 0x18 6. "EVENT199DETEN,Event(199) Detection Enable" "0,1"
bitfld.long 0x18 5. "EVENT198DETEN,Event(198) Detection Enable" "0,1"
bitfld.long 0x18 4. "EVENT197DETEN,Event(197) Detection Enable" "0,1"
bitfld.long 0x18 3. "EVENT196DETEN,Event(196) Detection Enable" "0,1"
bitfld.long 0x18 2. "EVENT195DETEN,Event(195) Detection Enable" "0,1"
newline
bitfld.long 0x18 1. "EVENT194DETEN,Event(194) Detection Enable" "0,1"
bitfld.long 0x18 0. "EVENT193DETEN,Event(193) Detection Enable" "0,1"
line.long 0x1C "DMPAC_CTSET_SETEVTENBL8,System event detection enable register 8 (if number of events > 224)"
bitfld.long 0x1C 31. "EVENT256DETEN,Event(256) Detection Enable" "0,1"
bitfld.long 0x1C 30. "EVENT255DETEN,Event(255) Detection Enable" "0,1"
bitfld.long 0x1C 29. "EVENT254DETEN,Event(254) Detection Enable" "0,1"
bitfld.long 0x1C 28. "EVENT253DETEN,Event(253) Detection Enable" "0,1"
bitfld.long 0x1C 27. "EVENT252DETEN,Event(252) Detection Enable" "0,1"
newline
bitfld.long 0x1C 26. "EVENT251DETEN,Event(251) Detection Enable" "0,1"
bitfld.long 0x1C 25. "EVENT250DETEN,Event(250) Detection Enable" "0,1"
bitfld.long 0x1C 24. "EVENT249DETEN,Event(249) Detection Enable" "0,1"
bitfld.long 0x1C 23. "EVENT248DETEN,Event(248) Detection Enable" "0,1"
bitfld.long 0x1C 22. "EVENT247DETEN,Event(247) Detection Enable" "0,1"
newline
bitfld.long 0x1C 21. "EVENT246DETEN,Event(246) Detection Enable" "0,1"
bitfld.long 0x1C 20. "EVENT245DETEN,Event(245) Detection Enable" "0,1"
bitfld.long 0x1C 19. "EVENT244DETEN,Event(244) Detection Enable" "0,1"
bitfld.long 0x1C 18. "EVENT243DETEN,Event(243) Detection Enable" "0,1"
bitfld.long 0x1C 17. "EVENT242DETEN,Event(242) Detection Enable" "0,1"
newline
bitfld.long 0x1C 16. "EVENT241DETEN,Event(241) Detection Enable" "0,1"
bitfld.long 0x1C 15. "EVENT240DETEN,Event(240) Detection Enable" "0,1"
bitfld.long 0x1C 14. "EVENT239DETEN,Event(239) Detection Enable" "0,1"
bitfld.long 0x1C 13. "EVENT238DETEN,Event(238) Detection Enable" "0,1"
bitfld.long 0x1C 12. "EVENT237DETEN,Event(237) Detection Enable" "0,1"
newline
bitfld.long 0x1C 11. "EVENT236DETEN,Event(236) Detection Enable" "0,1"
bitfld.long 0x1C 10. "EVENT235DETEN,Event(235) Detection Enable" "0,1"
bitfld.long 0x1C 9. "EVENT234DETEN,Event(234) Detection Enable" "0,1"
bitfld.long 0x1C 8. "EVENT233DETEN,Event(233) Detection Enable" "0,1"
bitfld.long 0x1C 7. "EVENT232DETEN,Event(232) Detection Enable" "0,1"
newline
bitfld.long 0x1C 6. "EVENT231DETEN,Event(231) Detection Enable" "0,1"
bitfld.long 0x1C 5. "EVENT230DETEN,Event(230) Detection Enable" "0,1"
bitfld.long 0x1C 4. "EVENT229DETEN,Event(229) Detection Enable" "0,1"
bitfld.long 0x1C 3. "EVENT228DETEN,Event(228) Detection Enable" "0,1"
bitfld.long 0x1C 2. "EVENT227DETEN,Event(227) Detection Enable" "0,1"
newline
bitfld.long 0x1C 1. "EVENT226DETEN,Event(226) Detection Enable" "0,1"
bitfld.long 0x1C 0. "EVENT225DETEN,Event(225) Detection Enable" "0,1"
line.long 0x20 "DMPAC_CTSET_SETMSTID,System Event Master ID"
hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for System Event module.Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs"
rgroup.long 0x20800++0x0B
line.long 0x00 "DMPAC_CTSET_CTCNTL,Counter Timer Control"
bitfld.long 0x00 26.--31. "NUMSTM,Number of counters that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals"
bitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 3.--6. "REVID,Revision ID of CTSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "NUMCOREMD,Indicated the number of mode bus interfaces 0 is 2 CPU buses 1 is 4 buses" "0,1"
line.long 0x04 "DMPAC_CTSET_CTNUMDBG,Counter Timer Number Debug Event Register"
bitfld.long 0x04 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7"
line.long 0x08 "DMPAC_CTSET_CTUSERACCCTL,Counter Timer User Access Control. can only be written in priviledged mode"
bitfld.long 0x08 2. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x08 1. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x08 0. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
group.long 0x20820++0x13
line.long 0x00 "DMPAC_CTSET_CTSTMCNTL,Counter Timer STM Control register"
rbitfld.long 0x00 6.--11. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 5. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1"
bitfld.long 0x00 4. "CCMPORT,SW control of CCM message export" "0,1"
bitfld.long 0x00 3. "CCMAVAIL,CTSET supports CCM export" "0,1"
bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1"
newline
bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1"
bitfld.long 0x00 0. "ENBL,CTSET STM global enable for counter/timer messages" "0,1"
line.long 0x04 "DMPAC_CTSET_CTSTMMSTID,Counter Timer STM Master ID register"
hexmask.long.byte 0x04 0.--7. 1. "MASTID,HW Master ID for System Event module"
line.long 0x08 "DMPAC_CTSET_CTSTMINTVL,Counter Timer STM Interval Register"
hexmask.long.word 0x08 0.--14. 1. "INTERVAL,Counter Timer Periodic export interval"
line.long 0x0C "DMPAC_CTSET_CTSTMSEL0,Counter Timer STM Counter Select Register 0"
line.long 0x10 "DMPAC_CTSET_CTSTMSEL1,Counter Timer STM Counter Select Register 1"
group.long 0x208A0++0x03
line.long 0x00 "DMPAC_CTSET_CTDBGSGL0,Timer Interval Register 0"
hexmask.long.byte 0x00 0.--7. 1. "INPSEL,Counter Timer input selection"
group.long 0x209F0++0x0F
line.long 0x00 "DMPAC_CTSET_CTGNBL0,Counter Timer Global Enable Register 0"
hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter.Bits 30 and 31 will be high if global time stamp output interface is enabled"
line.long 0x04 "DMPAC_CTSET_CTGNBL1,Counter Timer Global Enable Register 1"
hexmask.long.byte 0x04 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter"
line.long 0x08 "DMPAC_CTSET_CTGRST0,Counter Timer Global Reset Register 0"
hexmask.long.byte 0x08 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter.These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared"
line.long 0x0C "DMPAC_CTSET_CTGRST1,Counter Timer Global Reset Register 0"
hexmask.long.byte 0x0C 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter.These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared"
group.long 0x20B00++0x7F
line.long 0x00 "DMPAC_CTSET_CTFILT0,Counter Timer 0 Filter Register"
bitfld.long 0x00 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x00 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x00 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x00 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x00 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x00 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x00 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x00 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x04 "DMPAC_CTSET_CTFILT1,Counter Timer 1 Filter Register"
bitfld.long 0x04 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x04 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x04 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x04 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x04 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x04 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x04 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x04 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x08 "DMPAC_CTSET_CTFILT2,Counter Timer 2 Filter Register"
bitfld.long 0x08 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x08 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x08 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x08 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x08 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x08 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x08 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x08 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x0C "DMPAC_CTSET_CTFILT3,Counter Timer 3 Filter Register"
bitfld.long 0x0C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x0C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x0C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x0C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x0C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x0C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x0C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x0C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x10 "DMPAC_CTSET_CTFILT4,Counter Timer 4 Filter Register"
bitfld.long 0x10 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x10 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x10 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x10 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x10 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x10 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x10 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x10 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x14 "DMPAC_CTSET_CTFILT5,Counter Timer 5 Filter Register"
bitfld.long 0x14 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x14 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x14 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x14 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x14 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x14 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x14 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x14 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x18 "DMPAC_CTSET_CTFILT6,Counter Timer 6 Filter Register"
bitfld.long 0x18 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x18 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x18 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x18 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x18 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x18 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x18 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x18 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x1C "DMPAC_CTSET_CTFILT7,Counter Timer 7 Filter Register"
bitfld.long 0x1C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x1C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x1C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x1C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x1C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x1C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x1C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x1C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x20 "DMPAC_CTSET_CTFILT8,Counter Timer 8 Filter Register"
bitfld.long 0x20 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x20 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x20 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x20 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x20 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x20 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x20 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x20 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x24 "DMPAC_CTSET_CTFILT9,Counter Timer 9 Filter Register"
bitfld.long 0x24 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x24 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x24 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x24 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x24 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x24 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x24 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x24 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x28 "DMPAC_CTSET_CTFILT10,Counter Timer 10 Filter Register"
bitfld.long 0x28 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x28 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x28 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x28 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x28 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x28 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x28 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x28 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x2C "DMPAC_CTSET_CTFILT11,Counter Timer 11 Filter Register"
bitfld.long 0x2C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x2C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x2C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x2C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x2C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x2C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x2C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x2C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x30 "DMPAC_CTSET_CTFILT12,Counter Timer 12 Filter Register"
bitfld.long 0x30 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x30 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x30 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x30 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x30 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x30 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x30 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x30 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x34 "DMPAC_CTSET_CTFILT13,Counter Timer 13 Filter Register"
bitfld.long 0x34 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x34 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x34 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x34 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x34 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x34 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x34 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x34 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x38 "DMPAC_CTSET_CTFILT14,Counter Timer 14 Filter Register"
bitfld.long 0x38 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x38 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x38 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x38 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x38 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x38 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x38 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x38 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x3C "DMPAC_CTSET_CTFILT15,Counter Timer 15 Filter Register"
bitfld.long 0x3C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x3C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x3C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x3C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x3C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x3C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x3C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x3C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x40 "DMPAC_CTSET_CTFILT16,Counter Timer 16 Filter Register"
bitfld.long 0x40 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x40 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x40 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x40 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x40 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x40 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x40 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x40 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x44 "DMPAC_CTSET_CTFILT17,Counter Timer 17 Filter Register"
bitfld.long 0x44 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x44 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x44 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x44 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x44 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x44 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x44 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x44 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x48 "DMPAC_CTSET_CTFILT18,Counter Timer 18 Filter Register"
bitfld.long 0x48 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x48 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x48 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x48 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x48 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x48 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x48 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x48 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x4C "DMPAC_CTSET_CTFILT19,Counter Timer 19 Filter Register"
bitfld.long 0x4C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x4C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x4C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x4C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x4C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x4C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x4C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x4C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x50 "DMPAC_CTSET_CTFILT20,Counter Timer 20 Filter Register"
bitfld.long 0x50 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x50 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x50 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x50 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x50 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x50 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x50 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x50 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x54 "DMPAC_CTSET_CTFILT21,Counter Timer 21 Filter Register"
bitfld.long 0x54 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x54 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x54 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x54 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x54 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x54 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x54 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x54 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x58 "DMPAC_CTSET_CTFILT22,Counter Timer 22 Filter Register"
bitfld.long 0x58 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x58 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x58 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x58 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x58 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x58 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x58 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x58 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x5C "DMPAC_CTSET_CTFILT23,Counter Timer 23 Filter Register"
bitfld.long 0x5C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x5C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x5C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x5C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x5C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x5C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x5C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x5C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x60 "DMPAC_CTSET_CTFILT24,Counter Timer 24 Filter Register"
bitfld.long 0x60 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x60 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x60 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x60 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x60 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x60 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x60 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x60 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x64 "DMPAC_CTSET_CTFILT25,Counter Timer 25 Filter Register"
bitfld.long 0x64 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x64 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x64 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x64 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x64 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x64 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x64 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x64 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x68 "DMPAC_CTSET_CTFILT26,Counter Timer 26 Filter Register"
bitfld.long 0x68 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x68 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x68 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x68 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x68 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x68 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x68 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x68 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x6C "DMPAC_CTSET_CTFILT27,Counter Timer 27 Filter Register"
bitfld.long 0x6C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x6C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x6C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x6C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x6C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x6C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x6C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x6C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x70 "DMPAC_CTSET_CTFILT28,Counter Timer 28 Filter Register"
bitfld.long 0x70 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x70 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x70 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x70 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x70 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x70 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x70 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x70 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x74 "DMPAC_CTSET_CTFILT29,Counter Timer 29 Filter Register"
bitfld.long 0x74 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x74 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x74 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x74 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x74 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x74 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x74 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x74 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x78 "DMPAC_CTSET_CTFILT30,Counter Timer 30 Filter Register"
bitfld.long 0x78 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x78 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x78 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x78 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x78 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x78 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x78 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x78 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x7C "DMPAC_CTSET_CTFILT31,Counter Timer 31 Filter Register"
bitfld.long 0x7C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x7C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x7C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x7C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x7C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
newline
bitfld.long 0x7C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
bitfld.long 0x7C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x7C 0. "FREE,Counter functions while system/core is halted" "0,1"
group.long 0x20C00++0x13
line.long 0x00 "DMPAC_CTSET_CT_EOI,Counter Timer EOI Register"
bitfld.long 0x00 0. "EOI,EOI value" "0,1"
line.long 0x04 "DMPAC_CTSET_CTIRQSTAT_RAW,Counter Timer IRQSTATUS RAW Register"
line.long 0x08 "DMPAC_CTSET_CTIRQSTAT,Counter Timer IRQSTATUS Register"
line.long 0x0C "DMPAC_CTSET_CTIRQENABLE_SET,Counter Timer IRQENABLE_SET Register"
line.long 0x10 "DMPAC_CTSET_CTIRQENABLE_CLR,Counter Timer IRQENABLE_CLR Register"
group.long 0x21800++0x07
line.long 0x00 "DMPAC_CTSET_STPTCR,STP Trace Control Register"
rbitfld.long 0x00 24. "MOD_FIFOFULL,STPMI2ATB internal MID packet fifo is full" "0,1"
rbitfld.long 0x00 23. "DATA_FIFOFULL,STPMI2ATB internal Data packet fifo is full" "0,1"
bitfld.long 0x00 5. "COMPEN,Compression of Data enable" "0,1"
rbitfld.long 0x00 2. "SYNCEN,The value 1 indicatesDMPAC_CTSET_STPASYNC is supported" "0,1"
bitfld.long 0x00 1. "TSEN,Timestamp Enable.This bit is static and should not be changed dynamically" "0,1"
line.long 0x04 "DMPAC_CTSET_STPTID,STP Trace ID Register"
hexmask.long.byte 0x04 0.--6. 1. "TRACEID,Trace ID value.Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs"
group.long 0x21810++0x0B
line.long 0x00 "DMPAC_CTSET_STPASYNC,STP Synchronization Control Register"
bitfld.long 0x00 12. "EXPMODE,Exponent mode A value of 1 sets count to 2 to the Nth where Nth is ((bits11 : 8)+12)" "0,1"
hexmask.long.word 0x00 0.--11. 1. "COUNT,The number of bytes between Synchronization packets"
line.long 0x04 "DMPAC_CTSET_STPFFCR,STP Flush Control Register"
bitfld.long 0x04 5. "FORCEFLUSH,Write a 1 to force a flush automatically clears after the operation is complete" "0,1"
bitfld.long 0x04 1. "ASYNCPE,Async Priority Enable.0 indicates ASYNC packet priority is lower than trace" "0,1"
bitfld.long 0x04 0. "AUTOFLUSH,Auto flush enable.When set on every complete data (ATDATA : WIDTH) in the fifo written data is exported out when ATREADY is asserted" "0,1"
line.long 0x08 "DMPAC_CTSET_STPFEAT1,STP Features 1 Register"
bitfld.long 0x08 27.--31. "STP_RTLVER,RTL Version.Reset each time major or minor version is updated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 24.--26. "STP_MAJVER,Functional Major Version.This is the first version of STPMI2ATB" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 22.--23. "STP_CUSTVER,Custom Version (not used)" "0,1,2,3"
bitfld.long 0x08 17.--21. "STP_MINVER,Functional Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--6. "VERSION,STP2.0 Time Stamp Value of 011 indicates Natural binary timestamp a value of 100 indicates gray binary timestamps" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--3. "PROT,Protocol Revision.Value of 0001 indicates STP 2.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x20BC0)++0x03
line.long 0x00 "DMPAC_CTSET_CTCNTR$1,Counter Timer Counter Register 16"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x20B80)++0x03
line.long 0x00 "DMPAC_CTSET_CTCNTR$1,Counter Timer Counter Register 0"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x20AC0)++0x03
line.long 0x00 "DMPAC_CTSET_CTOWN$1,Counter/Timer Ownership register 16"
bitfld.long 0x00 30.--31. "OWNERSHIP,Counter/Timer Ownership Status.The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved)" "?,claim,enable,nop)"
bitfld.long 0x00 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1"
newline
rbitfld.long 0x00 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned " "0,1"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x20A80)++0x03
line.long 0x00 "DMPAC_CTSET_CTOWN$1,Counter/Timer Ownership register 0"
bitfld.long 0x00 30.--31. "OWNERSHIP,Counter/Timer Ownership Status.The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved)" "?,claim,enable,nop)"
bitfld.long 0x00 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1"
newline
rbitfld.long 0x00 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned " "0,1"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x20A40)++0x03
line.long 0x00 "DMPAC_CTSET_CTCR$1,Counter Timer Control Register 16"
hexmask.long.byte 0x00 24.--31. 1. "WDRESET,WD reset event input selector.Only available for modules capable of timer and counter functions"
hexmask.long.byte 0x00 16.--23. 1. "INPSEL,Counter Timer input selection.For WD mode it is the start event selector"
newline
bitfld.long 0x00 14.--15. "MODESEL,Counter is in duration or occurrence mode.Only writable by debug accesses" "0,1,2,3"
bitfld.long 0x00 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1"
newline
bitfld.long 0x00 12. "DBG_TRIG_STAT,Debug event triggered.Write 1 will clear this bit" "0,1"
bitfld.long 0x00 11. "WDMODE,WD Timer mode selection.Only available for modules capable of timer and counter functions" "0,1"
newline
bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match.Only available for modules capable of timer and counter functions" "0,1"
bitfld.long 0x00 9. "DBG,Signal debug logic on interval match.Only available for modules capable of timer and counter functions" "0,1"
newline
bitfld.long 0x00 8. "INT,Generate interrupt on interval match.Only available for modules capable of timer and counter functions" "0,1"
bitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads.Only valid on counters with an even number index" "0,1"
newline
bitfld.long 0x00 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1"
bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1"
bitfld.long 0x00 1. "RESET,Counter reset control" "0,1"
newline
bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x20A00)++0x03
line.long 0x00 "DMPAC_CTSET_CTCR$1,Counter Timer Control Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDRESET,WD reset event input selector.Only available for modules capable of timer and counter functions"
hexmask.long.byte 0x00 16.--23. 1. "INPSEL,Counter Timer input selection.For WD mode it is the start event selector"
newline
bitfld.long 0x00 14.--15. "MODESEL,Counter is in duration or occurrence mode.Only writable by debug accesses" "0,1,2,3"
bitfld.long 0x00 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1"
newline
bitfld.long 0x00 12. "DBG_TRIG_STAT,Debug event triggered.Write 1 will clear this bit" "0,1"
bitfld.long 0x00 11. "WDMODE,WD Timer mode selection.Only available for modules capable of timer and counter functions" "0,1"
newline
bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match.Only available for modules capable of timer and counter functions" "0,1"
bitfld.long 0x00 9. "DBG,Signal debug logic on interval match.Only available for modules capable of timer and counter functions" "0,1"
newline
bitfld.long 0x00 8. "INT,Generate interrupt on interval match.Only available for modules capable of timer and counter functions" "0,1"
bitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads.Only valid on counters with an even number index" "0,1"
newline
bitfld.long 0x00 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1"
bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1"
bitfld.long 0x00 1. "RESET,Counter reset control" "0,1"
newline
bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1"
repeat.end
repeat 7. (list 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x208A4)++0x03
line.long 0x00 "DMPAC_CTSET_CTDBGSGL$1,Counter Timer Debug Event Register 1"
hexmask.long.byte 0x00 0.--7. 1. "INPSEL,Counter Timer input selection"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x20840)++0x03
line.long 0x00 "DMPAC_CTSET_CTINTVLR$1,These registers contain the interval match value for the corresponding timers in the CTSET"
repeat.end
tree.end
tree.end
tree "DMPAC_DOF_CORE"
tree "DMPAC0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM"
base ad:0xF4C0000
rgroup.long 0x00++0x03
line.long 0x00 "DMPAC_DOF_PSE_MEM_RAM_Y,pse_mem_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000C0000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x2000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM0_RAM_Y,srb_mem0_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000C2000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x4000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM1_RAM_Y,srb_mem1_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000C4000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x6000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM2_RAM_Y,srb_mem2_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000C6000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x8000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM3_RAM_Y,srb_mem3_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000C8000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0xA000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM4_RAM_Y,srb_mem4_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000CA000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0xC000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM5_RAM_Y,srb_mem5_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000CC000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0xE000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM6_RAM_Y,srb_mem6_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000CE000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x10000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM7_RAM_Y,srb_mem7_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000D0000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x12000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM8_RAM_Y,srb_mem8_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000D2000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x14000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM9_RAM_Y,srb_mem9_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000D4000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x16000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM10_RAM_Y,srb_mem10_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000D6000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x18000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM11_RAM_Y,srb_mem11_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000D8000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x1A000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM12_RAM_Y,srb_mem12_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000DA000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x1C000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM13_RAM_Y,srb_mem13_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000DC000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x1E000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM14_RAM_Y,srb_mem14_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000DE000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x20000++0x03
line.long 0x00 "DMPAC_DOF_SRB_MEM15_RAM_Y,srb_mem15_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000E0000h + (y * 4h); where y = 0h to 7FFh"
rgroup.long 0x22000++0x03
line.long 0x00 "DMPAC_DOF_CSRAMGRD_RAM_y,csRamGrd_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000E2000h + (y * 4h); where y = 0h to 7FFh"
hexmask.long.word 0x00 20.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--19. 1. "DATA,Data read from RAM"
rgroup.long 0x24000++0x03
line.long 0x00 "DMPAC_DOF_CSRAMIIR_RAM_y,csRamIir_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000E4000h + (y * 4h); where y = 0h to FFFh"
rgroup.long 0x28000++0x03
line.long 0x00 "DMPAC_DOF_MFRAM0_RAM_y,mfRam0_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000E8000h + (y * 4h); where y = 0h to FFFh"
rgroup.long 0x2C000++0x03
line.long 0x00 "DMPAC_DOF_MFRAM1_RAM_y,mfRam1_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 000EC000h + (y * 4h); where y = 0h to FFFh"
tree.end
tree "DMPAC0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE"
base ad:0xF480000
rgroup.long 0x00++0x0B
line.long 0x00 "DMPAC_DOF_PID,DOF"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme.Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family.If there is no level of software compatibility a new FUNC number and hence DMPAC_DOF_PID should be assigned"
bitfld.long 0x00 11.--15. "RTL,RTL Version.R as described in PDR with additional clarifications and definitions below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision.X as described in PDR with additional clarifications/definitions below" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device.Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision.Y as described in PDR with additional clarifications/definitions below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMPAC_DOF_CR,Controls DOF operations"
rbitfld.long 0x04 26.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "REF_CT_TYPE_CFG,Census transform type for reference image.0: 24 bits generated for census transform by using a 5x5 neighborhood around the pixel" "0,1"
newline
bitfld.long 0x04 24. "CUR_CT_TYPE_CFG,Census transform type for current image.0: 24 bits generated for census transform by using a 5x5 neighborhood around the pixel" "0,1"
rbitfld.long 0x04 19.--23. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 18. "SOFSPARSEEN_CFG,sparse optical flow enable bit.Set to 0x1 to enable sparse optical flow processing" "0,1"
bitfld.long 0x04 17. "MF_EN_CFG,Median filter enable bit.Set to 0x1 to enable median filter processing" "0,1"
newline
bitfld.long 0x04 16. "LK_CS_EN_CFG,LK refinement and confidence score generation enable bit.Set to 0x1 to enable LK and CS processing" "0,1"
hexmask.long.word 0x04 5.--15. 1. "RSVD,Reserved"
newline
bitfld.long 0x04 4. "DL_EN_CFG,Delayed Left Predictor Enable bit.Set to 0x1 to enable use of delayed left predictor during the DOF processing" "0,1"
bitfld.long 0x04 3. "TP_EN_CFG,Temporal Predictor Enable bit.Set to 0x1 to enable use of temporal predictor during the DOF processing" "0,1"
newline
bitfld.long 0x04 2. "PYL_EN_CFG,Pyramidal Top Left Predictor Enable bit.Set to 0x1 to enable use of pyramidal top left predictor during DOF processing" "0,1"
bitfld.long 0x04 1. "PYC_EN_CFG,Pyramidal Top Co-located Predictor Enable bit.Set to 0x1 to enable use of pyramidal top colocated predictor during DOF processing" "0,1"
newline
bitfld.long 0x04 0. "DOF_EN_CFG,DOF Enable.Set to 0x1 to enable DOF engine" "0,1"
line.long 0x08 "DMPAC_DOF_STAT,Provides status info"
hexmask.long.word 0x08 20.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x08 10.--19. 1. "CURPAXADDRX_STS,Current Paxel Address X co-ordinate.Provides address of 2x2 paxel currently being processed"
newline
hexmask.long.word 0x08 1.--9. 1. "CURPAXADDRY_STS,Current Paxel Address Y co-ordinate.Provides address of 2x2 paxel currently being processed"
bitfld.long 0x08 0. "DOFACT_STS,DOF Active Status.When read as 0x1 indicates DOF engine is in active state processing flow vector for the frame" "0,1"
group.long 0x10++0x0B
line.long 0x00 "DMPAC_DOF_RES,Set up frame width. height"
rbitfld.long 0x00 27.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 16.--26. 1. "HEIGHT_CFG,Height of frame (in pixel) to be processed by Optical Flow engine.1024 pixel max and 16 pixels min"
newline
rbitfld.long 0x00 12.--15. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "WIDTH_CFG,Width of frame (in pixel) to be processed by Optical Flow engine.2048 pixel max and 32 pixels min"
line.long 0x04 "DMPAC_DOF_SR,Setup horizontal and vertical search range"
rbitfld.long 0x04 30.--31. "RSVD2,Reserved" "0,1,2,3"
bitfld.long 0x04 24.--29. "VSR_N_CFG,Negative or Upward direction Vertical Search Range in pixels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x04 22.--23. "RSVD1,Reserved" "0,1,2,3"
bitfld.long 0x04 16.--21. "VSR_P_CFG,Positive or Downward direction Vertical Search Range in pixels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x04 8.--15. 1. "RSVD,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "HSR_CFG,Horizontal Search Range in pixels in both the directions"
line.long 0x08 "DMPAC_DOF_SOF,Controls sparse optical flow output processing"
hexmask.long.tbyte 0x08 12.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x08 0.--11. 1. "MAX_OUTPUT_COUNT_PER_LINE_CFG,Maximum number of MV output per line in case of sparse optical flow processing"
group.long 0x20++0x0B
line.long 0x00 "DMPAC_DOF_CFGWBASE,Current Frame GW Base address in SL2"
hexmask.long.word 0x00 20.--31. 1. "RSVD,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "ADDR_CFG,SL2 base byte address.Should be aligned to 64 bytes"
line.long 0x04 "DMPAC_DOF_CFGWWIDTH,CFGW width. Max 2048 pix"
hexmask.long.tbyte 0x04 13.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x04 0.--12. 1. "WIDTH_CFG,Width of Frame Growing Window in bytes.Should be multiple of 64 bytes"
line.long 0x08 "DMPAC_DOF_CFGWHEIGHT,CFGW Height. Max 32 rows"
hexmask.long 0x08 5.--31. 1. "RSVD,Reserved"
bitfld.long 0x08 0.--4. "HEIGHT_CFG,Height of Frame Growing Window.Max 31 rows" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x30++0x0B
line.long 0x00 "DMPAC_DOF_RFGWBASE,Reference Frame GW Base address in SL2"
hexmask.long.word 0x00 20.--31. 1. "RSVD,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "ADDR_CFG,SL2 base byte address.Should be aligned to 64 bytes"
line.long 0x04 "DMPAC_DOF_RFGWWIDTH,RFGW width. Max 2048 pix"
hexmask.long.tbyte 0x04 13.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x04 0.--12. 1. "WIDTH_CFG,Width of Frame Growing Window in bytes.Should be multiple of 64 bytes"
line.long 0x08 "DMPAC_DOF_RFGWHEIGHT,RFGW height. Max 256 rows"
hexmask.long.tbyte 0x08 8.--31. 1. "RSVD,Reserved"
hexmask.long.byte 0x08 0.--7. 1. "HEIGHT_CFG,Height of Frame Growing Window.Max 255 rows"
group.long 0x40++0x0F
line.long 0x00 "DMPAC_DOF_SPBUFBASE,Base address in SL2"
rbitfld.long 0x00 27.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 20.--23. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--19. 1. "ADDR_CFG,SL2 base byte address.Should be aligned to 64 bytes"
line.long 0x04 "DMPAC_DOF_TPBUFBASE,Base address in SL2"
rbitfld.long 0x04 27.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 20.--23. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x04 0.--19. 1. "ADDR_CFG,SL2 base byte address.Should be aligned to 64 bytes"
line.long 0x08 "DMPAC_DOF_BMBUFBASE,Base address in SL2"
rbitfld.long 0x08 27.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x08 20.--23. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x08 0.--19. 1. "ADDR_CFG,SL2 base byte address.Should be aligned to 64 bytes"
line.long 0x0C "DMPAC_DOF_FVBUFBASE,Base address in SL2"
rbitfld.long 0x0C 27.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 24.--26. "DEPTH_CFG,Depth of SL2 buffer" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0C 20.--23. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x0C 0.--19. 1. "ADDR_CFG,SL2 base byte address.Should be aligned to 64 bytes"
group.long 0x60++0x07
line.long 0x00 "DMPAC_DOF_MSFR,5b unsigned integer for Step Search cost function"
hexmask.long 0x00 5.--31. 1. "RSVD,Reserved"
bitfld.long 0x00 0.--4. "MSF_CFG,Motion smoothness factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DMPAC_DOF_CSCFGR,Feature filter parameters. confidence score scaling factor setup"
rbitfld.long 0x04 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x04 16.--25. 1. "CS_GAIN_CFG,Multiplier factor (Gain) for the combined confidence score.The sum of individual scores from different decision trees are multiplied by CS Gain before scaling to final 4bit (16 levels) confidence score value"
newline
hexmask.long.byte 0x04 8.--15. 1. "RSVD,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "IIR_ALPHA_CFG,Coefficient for IIR filter used for smoothing horizontal flow vector gradient.The usage can be illustrated as: SmoothU(i j)= [ U(i j)*alpha + SmoothU(i-1 j)*beta + round ]>>8 where beta = 256-alpha round = 128"
group.long 0x70++0x07
line.long 0x00 "DMPAC_DOF_PSA_CTRL,Control register for calculating 32b CRC signature on flow vector output"
hexmask.long 0x00 1.--31. 1. "RSVD,Reserved"
bitfld.long 0x00 0. "PSA_EN_CFG,Enable calculating 32b CRC signature on 32b flow vector and confidence score output" "0,1"
line.long 0x04 "DMPAC_DOF_PSA_SIGNATURE,32b CRC signature calculated on flow vector output"
group.long 0x80++0x1F
line.long 0x00 "DMPAC_DOF_TH0_j,Confidence Score Decision Tree[a] Threshold 0"
hexmask.long.word 0x00 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x00 0.--15. 1. "THRESHOLD_CFG,Threshold 0 value.If Feature(Index0).ge.Thresh0 then 2ndBranch11 else 2ndBranch10"
line.long 0x04 "DMPAC_DOF_TH10_j,Confidence Score Decision Tree[a] Threshold 10"
hexmask.long.word 0x04 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x04 0.--15. 1. "THRESHOLD_CFG,Threshold 10 value.If Feature(Index10).ge.Thresh10 then Weight01 else Weight00"
line.long 0x08 "DMPAC_DOF_TH11_j,Confidence Score Decision Tree[a] Threshold 11"
hexmask.long.word 0x08 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x08 0.--15. 1. "THRESHOLD_CFG,Threshold 11 value.If Feature(Index11).ge.Thresh11 then Weight11 else Weight10"
line.long 0x0C "DMPAC_DOF_WT00_j,Confidence Score Decision Tree[a] Weight 00"
hexmask.long.word 0x0C 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WEIGHT_CFG,Weight 00 value for Confidence Score Decision Tree"
line.long 0x10 "DMPAC_DOF_WT01_j,Confidence Score Decision Tree[a] Weight 01"
hexmask.long.word 0x10 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x10 0.--15. 1. "WEIGHT_CFG,Weight 01 value for Confidence Score Decision Tree"
line.long 0x14 "DMPAC_DOF_WT10_j,Confidence Score Decision Tree Tree[a] Weight 10"
hexmask.long.word 0x14 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x14 0.--15. 1. "WEIGHT_CFG,Weight 10 value for Confidence Score Decision Tree"
line.long 0x18 "DMPAC_DOF_WT11_j,Confidence Score Decision Tree[a] Weight 11"
hexmask.long.word 0x18 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x18 0.--15. 1. "WEIGHT_CFG,Weight 11 value for Confidence Score Decision Tree"
line.long 0x1C "DMPAC_DOF_FIDS_j,Decision Tree n=0-to-15 Feature Indices"
hexmask.long.tbyte 0x1C 9.--31. 1. "RSVD,Reserved"
bitfld.long 0x1C 6.--8. "INDEX2_CFG,Specifies the index of a feature (in the confidence score feature vector) to be used as the 3rd feature in the decision tree traversal0: Winner Cost" "?,Texture,Flow Grad U,Flow Grad V,Aggregated Winner Cost,Aggregated Texture,Aggregated Flow Grad U,Aggregated Flow Grad V"
newline
bitfld.long 0x1C 3.--5. "INDEX1_CFG,Specifies the index of a feature (in the confidence score feature vector) to be used as the 2nd feature in the decision tree traversal0: Winner Cost" "?,Texture,Flow Grad U,Flow Grad V,Aggregated Winner Cost,Aggregated Texture,Aggregated Flow Grad U,Aggregated Flow Grad V"
bitfld.long 0x1C 0.--2. "INDEX0_CFG,Specifies the index of a feature (in the confidence score feature vector) to be used as the 1st feature in the decision tree traversal0: Winner Cost" "?,Texture,Flow Grad U,Flow Grad V,Aggregated Winner Cost,Aggregated Texture,Aggregated Flow Grad U,Aggregated Flow Grad V"
rgroup.long 0x300++0x03
line.long 0x00 "DMPAC_DOF_DOFCSHIST_y,Confidence Score Histogram Number of pixels having confidence score value of Bin Index Offset = 00080300h + (y * 4h); where y = 0h to Fh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "BIN_STS,Number of pixels having confidence score value of Bin Index"
tree.end
tree.end
tree "DMPAC_ECC_AGGR"
tree "DMPAC0_KSDW_ECC_AGGR_CFG"
base ad:0x2A6A000
rgroup.long 0x00++0x03
line.long 0x00 "DMPAC_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "DMPAC_ECC_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "DMPAC_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "DMPAC_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "DMPAC_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DMPAC_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "DRU_PSI_EDC_PEND,Interrupt Pending Status for dru_psi_edc_pend" "0,1"
bitfld.long 0x04 5. "DRU_ENG_EDC_PEND,Interrupt Pending Status for dru_eng_edc_pend" "0,1"
bitfld.long 0x04 4. "DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x04 3. "DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x04 2. "DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 1. "DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for tpram_dru_response_buffer0_ecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "DMPAC_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_psi_edc_pend" "0,1"
bitfld.long 0x00 5. "DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_eng_edc_pend" "0,1"
bitfld.long 0x00 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 2. "DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for tpram_dru_response_buffer0_ecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DMPAC_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_psi_edc_pend" "0,1"
bitfld.long 0x00 5. "DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_eng_edc_pend" "0,1"
bitfld.long 0x00 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 2. "DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for tpram_dru_response_buffer0_ecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DMPAC_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DMPAC_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "DRU_PSI_EDC_PEND,Interrupt Pending Status for dru_psi_edc_pend" "0,1"
bitfld.long 0x04 5. "DRU_ENG_EDC_PEND,Interrupt Pending Status for dru_eng_edc_pend" "0,1"
bitfld.long 0x04 4. "DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x04 3. "DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x04 2. "DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 1. "DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for tpram_dru_response_buffer0_ecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DMPAC_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_psi_edc_pend" "0,1"
bitfld.long 0x00 5. "DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for dru_eng_edc_pend" "0,1"
bitfld.long 0x00 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 2. "DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for tpram_dru_response_buffer0_ecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DMPAC_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_psi_edc_pend" "0,1"
bitfld.long 0x00 5. "DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for dru_eng_edc_pend" "0,1"
bitfld.long 0x00 4. "DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 2. "DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 1. "DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 0. "TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for tpram_dru_response_buffer0_ecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "DMPAC_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "DMPAC_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "DMPAC_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "DMPAC_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "DMPAC_FOCO_0"
tree "DMPAC0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS"
base ad:0xF424000
group.long 0x00++0x07
line.long 0x00 "DMPAC_FOCO_0_CH_CTRL_j,Defines parameters that control the format conversion for input-output channel pair"
hexmask.long.word 0x00 16.--31. 1. "MASK,16b mask value that will be and-ed with the result"
bitfld.long 0x00 12.--15. "ROUND,Unsigned Rounding value that will be added" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 9.--11. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "DIR,Shift direction - left or right.\n0 -> Right\n 1 -> Left" "0,1"
bitfld.long 0x00 5.--7. "SHIFT_M1,Amount of bit shift minus 1.Valid values 0 to 7 meaning shift of 1 to 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "SHIFT_EN,Enable for shifting.\n0 --> No shift\n 1 --> Shift determined by SHIFT_M1" "0,1"
rbitfld.long 0x00 1.--3. "RSVD,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "CH_EN,Enable format conversion channel" "0,1"
line.long 0x04 "DMPAC_FOCO_0_CH_COUNT_j,Defines count values for pre/post load and functional operation for the format conversion for input-output channel pair"
hexmask.long.word 0x04 16.--31. 1. "TRIG,Defines the number of FOCO module operations (HTS starts/dones) for which the actual format conversion happens after PRELOAD number of FOCO module operations.This number cannot be 0 for an active channel"
hexmask.long.byte 0x04 8.--15. 1. "POSTLOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after PRELOAD + TRIG number of FOCO module operations"
hexmask.long.byte 0x04 0.--7. 1. "PRELOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after HTS init"
tree.end
tree "DMPAC0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP"
base ad:0xF424200
rgroup.long 0x00++0x13
line.long 0x00 "DMPAC_FOCO_0_STATUS_PARAM,The register returns the LSE compile configuration parameters"
bitfld.long 0x00 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3"
bitfld.long 0x00 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1"
bitfld.long 0x00 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1"
newline
bitfld.long 0x00 23.--27. "CORE_OUT_DW,Core Output Channel Data Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1"
bitfld.long 0x00 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1"
newline
bitfld.long 0x00 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1"
bitfld.long 0x00 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--16. "CORE_DW,Core Input Data Bus Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3"
bitfld.long 0x00 6.--9. "SL2_OUT_CH,Number of SL2 Output Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2. "VPORT_THR,Number of VPORT input enabled" "0,1"
bitfld.long 0x00 0.--1. "NTHR,Number of threads supported" "0,1,2,3"
line.long 0x04 "DMPAC_FOCO_0_STATUS_ERROR,The register returns the LSE error status"
hexmask.long.byte 0x04 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status[14:11] Write Channel Number [10:8] VBUSM write error status"
bitfld.long 0x04 0.--4. "VM_RD_ERR,VBUSM I/F Last Read Error Status[4:3] Read Channel Number [2:0] VBUSM read error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DMPAC_FOCO_0_STATUS_IDLE_MODE,The register returns IDLE status of LSE VBUSM port and in/output"
bitfld.long 0x08 12.--15. "LSE_OUT_CHAN,Output Channel[3:0] Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 4.--7. "LSE_IN_CHAN,Input Channel[3:0] Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1"
newline
bitfld.long 0x08 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1"
line.long 0x0C "DMPAC_FOCO_0_CFG_LSE,The register configures the LSE general hardware modes"
bitfld.long 0x0C 8. "PSA_EN,Test mode Output Channel Signature Generation Enable0: Disable (default)" "0,1"
bitfld.long 0x0C 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select0: Round-Robin Arbitration (default)" "0,1"
line.long 0x10 "DMPAC_FOCO_0_CFG,The SRC_CFG register configures the input channels for the processing thread"
bitfld.long 0x10 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable0: Disable" "0,1"
bitfld.long 0x10 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment0: LSB-aligned" "0,1"
bitfld.long 0x10 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel0: 8-bit" "?,12-bit,16-bit,reserved Input.."
newline
bitfld.long 0x10 0.--1. "PIX_FMT_PW,Input Pixel Width Sel0: 8-bit" "?,12-bit,14-bit,16-bit The width.."
group.long 0x18++0x0B
line.long 0x00 "DMPAC_FOCO_0_FRAME_SIZE,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)"
line.long 0x04 "DMPAC_FOCO_0_BUF_ATTR,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size[15:6] (64 byte multiple) stride size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size[5:0] - 6 LSB bits of buffer stride size should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMPAC_FOCO_0_BUF_BA_y,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread"
bitfld.long 0x08 31. "ENABLE,Input Buffer Enable0: Disable" "0,1"
hexmask.long.tbyte 0x08 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address"
rbitfld.long 0x08 0.--5. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x07
line.long 0x00 "DMPAC_FOCO_0_BUF_CFG_j,The DST_BUF_CFG register configures the output buffer channel"
rbitfld.long 0x00 31. "CH_DISABLED,Channel Disable Status (read-only)0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory" "0,1"
bitfld.long 0x00 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection0: UYVY" "0,1"
bitfld.long 0x00 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable0: Disable" "0,1"
newline
bitfld.long 0x00 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment0: LSB-aligned" "0,1"
bitfld.long 0x00 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel0: 8-bit" "?,12-bit,16-bit,reserved Output.."
bitfld.long 0x00 0.--1. "PIX_FMT_PW,Output Pixel Width Sel0: 8-bit" "?,12-bit,reserved,16-bit The width.."
line.long 0x04 "DMPAC_FOCO_0_BUF_ATTR0_j,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size[15:6] (64 byte multiple) stride size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size[5:0] - 6 LSB bits of buffer stride size should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5C++0x03
line.long 0x00 "DMPAC_FOCO_0_BUF_BA_j,The DST_BUF_BA register configures the base address of the output SL2 circular buffer"
bitfld.long 0x00 31. "ENABLE,Output Channel Enable0: Disable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x140++0x03
line.long 0x00 "DMPAC_FOCO_0_PSA_SIGNATURE_y,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]"
rgroup.long 0x1E0++0x03
line.long 0x00 "DMPAC_FOCO_0_DBG_y,The DBG register returns the current status of internal FSM - TI internal use only"
tree.end
tree.end
tree "DMPAC_FOCO_1"
tree "DMPAC0_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS"
base ad:0xF428000
group.long 0x00++0x07
line.long 0x00 "DMPAC_FOCO_1_CH_CTRL_j,Defines parameters that control the format conversion for input-output channel pair"
hexmask.long.word 0x00 16.--31. 1. "MASK,16b mask value that will be and-ed with the result"
bitfld.long 0x00 12.--15. "ROUND,Unsigned Rounding value that will be added" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 9.--11. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "DIR,Shift direction - left or right.\n0 -> Right\n 1 -> Left" "0,1"
bitfld.long 0x00 5.--7. "SHIFT_M1,Amount of bit shift minus 1.Valid values 0 to 7 meaning shift of 1 to 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "SHIFT_EN,Enable for shifting.\n0 --> No shift\n 1 --> Shift determined by SHIFT_M1" "0,1"
rbitfld.long 0x00 1.--3. "RSVD,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "CH_EN,Enable format conversion channel" "0,1"
line.long 0x04 "DMPAC_FOCO_1_CH_COUNT_j,Defines count values for pre/post load and functional operation for the format conversion for input-output channel pair"
hexmask.long.word 0x04 16.--31. 1. "TRIG,Defines the number of FOCO module operations (HTS starts/dones) for which the actual format conversion happens after PRELOAD number of FOCO module operations.This number cannot be 0 for an active channel"
hexmask.long.byte 0x04 8.--15. 1. "POSTLOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after PRELOAD + TRIG number of FOCO module operations"
hexmask.long.byte 0x04 0.--7. 1. "PRELOAD,Defines the number of FOCO module operations (HTS starts/dones) that would be skipped after HTS init"
tree.end
tree "DMPAC0_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP"
base ad:0xF428200
rgroup.long 0x00++0x13
line.long 0x00 "DMPAC_FOCO_1_STATUS_PARAM,The register returns the LSE compile configuration parameters"
bitfld.long 0x00 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3"
bitfld.long 0x00 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1"
bitfld.long 0x00 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1"
newline
bitfld.long 0x00 23.--27. "CORE_OUT_DW,Core Output Channel Data Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1"
bitfld.long 0x00 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1"
newline
bitfld.long 0x00 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1"
bitfld.long 0x00 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--16. "CORE_DW,Core Input Data Bus Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3"
bitfld.long 0x00 6.--9. "SL2_OUT_CH,Number of SL2 Output Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2. "VPORT_THR,Number of VPORT input enabled" "0,1"
bitfld.long 0x00 0.--1. "NTHR,Number of threads supported" "0,1,2,3"
line.long 0x04 "DMPAC_FOCO_1_STATUS_ERROR,The register returns the LSE error status"
hexmask.long.byte 0x04 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status[14:11] Write Channel Number [10:8] VBUSM write error status"
bitfld.long 0x04 0.--4. "VM_RD_ERR,VBUSM I/F Last Read Error Status[4:3] Read Channel Number [2:0] VBUSM read error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DMPAC_FOCO_1_STATUS_IDLE_MODE,The register returns IDLE status of LSE VBUSM port and in/output"
bitfld.long 0x08 12.--15. "LSE_OUT_CHAN,Output Channel[3:0] Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 4.--7. "LSE_IN_CHAN,Input Channel[3:0] Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1"
newline
bitfld.long 0x08 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1"
line.long 0x0C "DMPAC_FOCO_1_CFG_LSE,The register configures the LSE general hardware modes"
bitfld.long 0x0C 8. "PSA_EN,Test mode Output Channel Signature Generation Enable0: Disable (default)" "0,1"
bitfld.long 0x0C 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select0: Round-Robin Arbitration (default)" "0,1"
line.long 0x10 "DMPAC_FOCO_1_CFG,The SRC_CFG register configures the input channels for the processing thread"
bitfld.long 0x10 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable0: Disable" "0,1"
bitfld.long 0x10 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment0: LSB-aligned" "0,1"
bitfld.long 0x10 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel0: 8-bit" "?,12-bit,16-bit,reserved Input.."
newline
bitfld.long 0x10 0.--1. "PIX_FMT_PW,Input Pixel Width Sel0: 8-bit" "?,12-bit,14-bit,16-bit The width.."
group.long 0x18++0x0B
line.long 0x00 "DMPAC_FOCO_1_FRAME_SIZE,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)"
line.long 0x04 "DMPAC_FOCO_1_BUF_ATTR,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size[15:6] (64 byte multiple) stride size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size[5:0] - 6 LSB bits of buffer stride size should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMPAC_FOCO_1_BUF_BA_y,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread"
bitfld.long 0x08 31. "ENABLE,Input Buffer Enable0: Disable" "0,1"
hexmask.long.tbyte 0x08 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address"
rbitfld.long 0x08 0.--5. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x07
line.long 0x00 "DMPAC_FOCO_1_BUF_CFG_j,The DST_BUF_CFG register configures the output buffer channel"
rbitfld.long 0x00 31. "CH_DISABLED,Channel Disable Status (read-only)0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory" "0,1"
bitfld.long 0x00 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection0: UYVY" "0,1"
bitfld.long 0x00 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable0: Disable" "0,1"
newline
bitfld.long 0x00 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment0: LSB-aligned" "0,1"
bitfld.long 0x00 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel0: 8-bit" "?,12-bit,16-bit,reserved Output.."
bitfld.long 0x00 0.--1. "PIX_FMT_PW,Output Pixel Width Sel0: 8-bit" "?,12-bit,reserved,16-bit The width.."
line.long 0x04 "DMPAC_FOCO_1_BUF_ATTR0_j,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size[15:6] (64 byte multiple) stride size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size[5:0] - 6 LSB bits of buffer stride size should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5C++0x03
line.long 0x00 "DMPAC_FOCO_1_BUF_BA_j,The DST_BUF_BA register configures the base address of the output SL2 circular buffer"
bitfld.long 0x00 31. "ENABLE,Output Channel Enable0: Disable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x140++0x03
line.long 0x00 "DMPAC_FOCO_1_PSA_SIGNATURE_y,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]"
rgroup.long 0x1E0++0x03
line.long 0x00 "DMPAC_FOCO_1_DBG_y,The DBG register returns the current status of internal FSM - TI internal use only"
tree.end
tree.end
tree "DMPAC_HTS"
tree "DMPAC0_HTS_S_VBUSP"
base ad:0xF408000
group.long 0x00++0x1B
line.long 0x00 "DMPAC_HTS_PIPELINE_CONTROL_0,Enable pipeline to activate all connected scheduler"
bitfld.long 0x00 0. "PIPE_EN,Pipeline 0 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x04 "DMPAC_HTS_PIPELINE_CONTROL_1,Enable pipeline to activate all connected scheduler"
bitfld.long 0x04 0. "PIPE_EN,Pipeline 1 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x08 "DMPAC_HTS_PIPELINE_CONTROL_2,Enable pipeline to activate all connected scheduler"
bitfld.long 0x08 0. "PIPE_EN,Pipeline 2 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x0C "DMPAC_HTS_PIPELINE_CONTROL_3,Enable pipeline to activate all connected scheduler"
bitfld.long 0x0C 0. "PIPE_EN,Pipeline 3 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x10 "DMPAC_HTS_PIPELINE_CONTROL_4,Enable pipeline to activate all connected scheduler"
bitfld.long 0x10 0. "PIPE_EN,Pipeline 4 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x14 "DMPAC_HTS_PIPELINE_CONTROL_5,Enable pipeline to activate all connected scheduler"
bitfld.long 0x14 0. "PIPE_EN,Pipeline 5 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x18 "DMPAC_HTS_PIPELINE_CONTROL_6,Enable pipeline to activate all connected scheduler"
bitfld.long 0x18 0. "PIPE_EN,Pipeline 6 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
group.long 0x50++0x5B
line.long 0x00 "DMPAC_HTS_HWA0_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA0 Scheduler resources must not be read during halted state.'1'-> HWA0 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA0 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA0 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA0_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA0_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA0 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA0 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA0_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA0 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA0_CONS0_CONTROL,Controlling consumer socket 0 for HWA0"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA0_CONS1_CONTROL,Controlling consumer socket 1 for HWA0"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA0_CONS2_CONTROL,Controlling consumer socket 2 for HWA0"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA0_CONS3_CONTROL,Controlling consumer socket 3 for HWA0"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA0_CONS4_CONTROL,Controlling consumer socket 4 for HWA0"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "DMPAC_HTS_HWA0_CONS5_CONTROL,Controlling consumer socket 5 for HWA0"
hexmask.long.word 0x24 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 5"
bitfld.long 0x24 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1"
line.long 0x28 "DMPAC_HTS_HWA0_PROD0_CONTROL,Controlling producer socket0 for HWA0"
hexmask.long.byte 0x28 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x28 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA0_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA0"
bitfld.long 0x2C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x2C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x2C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x30 "DMPAC_HTS_HWA0_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod0"
hexmask.long.word 0x30 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x30 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x30 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x34 "DMPAC_HTS_HWA0_PA0_CONTROL,control register to manage pattern adapter on HWA0 prod socket0"
hexmask.long.word 0x34 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x34 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x34 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x34 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x34 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x38 "DMPAC_HTS_HWA0_PA0_PRODCOUNT,count values for HWA0 prod socket0"
hexmask.long.word 0x38 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x38 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "DMPAC_HTS_HWA0_PROD1_CONTROL,Controlling producer socket1 for HWA0"
hexmask.long.byte 0x3C 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x3C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA0_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA0"
bitfld.long 0x40 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x40 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x40 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x44 "DMPAC_HTS_HWA0_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod1"
hexmask.long.word 0x44 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x44 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x44 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x48 "DMPAC_HTS_HWA0_PA1_CONTROL,control register to manage pattern adapter on HWA0 prod socket1"
hexmask.long.word 0x48 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x48 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x48 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x48 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x48 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x4C "DMPAC_HTS_HWA0_PA1_PRODCOUNT,count values for HWA0 prod socket1"
hexmask.long.word 0x4C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x4C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x50 "DMPAC_HTS_HWA0_PROD2_CONTROL,Controlling producer socket2 for HWA0"
hexmask.long.byte 0x50 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x50 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x54 "DMPAC_HTS_HWA0_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA0"
bitfld.long 0x54 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x54 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x54 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x58 "DMPAC_HTS_HWA0_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod2"
hexmask.long.word 0x58 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x58 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x58 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xB4++0x0B
line.long 0x00 "DMPAC_HTS_HWA0_PROD3_CONTROL,Controlling producer socket3 for HWA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA0_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA0_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xC8++0x0B
line.long 0x00 "DMPAC_HTS_HWA0_PROD4_CONTROL,Controlling producer socket4 for HWA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 4.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA0_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA0_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xDC++0x0B
line.long 0x00 "DMPAC_HTS_HWA0_PROD5_CONTROL,Controlling producer socket5 for HWA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 5.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA0_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA0_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xF0++0x0B
line.long 0x00 "DMPAC_HTS_HWA0_PROD6_CONTROL,Controlling producer socket6 for HWA0"
bitfld.long 0x00 24.--26. "MASK_SELECT,define which tdone_mask apply to prod socket 6.tdone_mask[mask_select] applies to prod_socket6" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 6.Used in decrementing count of producer buffer"
newline
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA0_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA0_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x104++0x5B
line.long 0x00 "DMPAC_HTS_HWA1_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA1 Scheduler resources must not be read during halted state.'1'-> HWA1 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA1 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA1 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA1_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA1_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA1 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA1 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA1_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA1 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA1_CONS0_CONTROL,Controlling consumer socket 0 for HWA1"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA1_CONS1_CONTROL,Controlling consumer socket 1 for HWA1"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA1_CONS2_CONTROL,Controlling consumer socket 2 for HWA1"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA1_CONS3_CONTROL,Controlling consumer socket 3 for HWA1"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA1_CONS4_CONTROL,Controlling consumer socket 4 for HWA1"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "DMPAC_HTS_HWA1_CONS5_CONTROL,Controlling consumer socket 5 for HWA1"
hexmask.long.word 0x24 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 5"
bitfld.long 0x24 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1"
line.long 0x28 "DMPAC_HTS_HWA1_PROD0_CONTROL,Controlling producer socket0 for HWA1"
hexmask.long.byte 0x28 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x28 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA1_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA1"
bitfld.long 0x2C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x2C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x2C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x30 "DMPAC_HTS_HWA1_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod0"
hexmask.long.word 0x30 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x30 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x30 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x34 "DMPAC_HTS_HWA1_PA0_CONTROL,control register to manage pattern adapter on HWA1 prod socket0"
hexmask.long.word 0x34 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x34 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x34 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x34 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x34 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x38 "DMPAC_HTS_HWA1_PA0_PRODCOUNT,count values for HWA1 prod socket0"
hexmask.long.word 0x38 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x38 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "DMPAC_HTS_HWA1_PROD1_CONTROL,Controlling producer socket1 for HWA1"
hexmask.long.byte 0x3C 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x3C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA1_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA1"
bitfld.long 0x40 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x40 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x40 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x44 "DMPAC_HTS_HWA1_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod1"
hexmask.long.word 0x44 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x44 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x44 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x48 "DMPAC_HTS_HWA1_PA1_CONTROL,control register to manage pattern adapter on HWA1 prod socket1"
hexmask.long.word 0x48 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x48 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x48 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x48 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x48 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x4C "DMPAC_HTS_HWA1_PA1_PRODCOUNT,count values for HWA1 prod socket1"
hexmask.long.word 0x4C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x4C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x50 "DMPAC_HTS_HWA1_PROD2_CONTROL,Controlling producer socket2 for HWA1"
hexmask.long.byte 0x50 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x50 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x54 "DMPAC_HTS_HWA1_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA1"
bitfld.long 0x54 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x54 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x54 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x58 "DMPAC_HTS_HWA1_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod2"
hexmask.long.word 0x58 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x58 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x58 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x168++0x0B
line.long 0x00 "DMPAC_HTS_HWA1_PROD3_CONTROL,Controlling producer socket3 for HWA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA1_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA1_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x17C++0x0B
line.long 0x00 "DMPAC_HTS_HWA1_PROD4_CONTROL,Controlling producer socket4 for HWA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 4.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA1_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA1_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x190++0x0B
line.long 0x00 "DMPAC_HTS_HWA1_PROD5_CONTROL,Controlling producer socket5 for HWA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 5.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA1_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA1_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x1A4++0x0B
line.long 0x00 "DMPAC_HTS_HWA1_PROD6_CONTROL,Controlling producer socket6 for HWA1"
bitfld.long 0x00 24.--26. "MASK_SELECT,define which tdone_mask apply to prod socket 6.tdone_mask[mask_select] applies to prod_socket6" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 6.Used in decrementing count of producer buffer"
newline
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA1_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA1_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x1B8++0xB3
line.long 0x00 "DMPAC_HTS_HWA2_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA2 Scheduler resources must not be read during halted state.'1'-> HWA2 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA2 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA2 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA2_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA2_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA2 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA2 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA2_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA2 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA2_CONS0_CONTROL,Controlling consumer socket 0 for HWA2"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA2_CONS1_CONTROL,Controlling consumer socket 1 for HWA2"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA2_CONS2_CONTROL,Controlling consumer socket 2 for HWA2"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA2_PROD0_CONTROL,Controlling producer socket0 for HWA2"
bitfld.long 0x1C 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 0 is used to trigger DMA channel to..,Prod Socket 0 is used to trigger DMA channel to..,?..."
bitfld.long 0x1C 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA2_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA2"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA2_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod0"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA2_PA0_CONTROL,control register to manage pattern adapter on HWA2 prod socket0"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA2_PA0_PRODCOUNT,count values for HWA2 prod socket0"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA2_PROD1_CONTROL,Controlling producer socket1 for HWA2"
bitfld.long 0x30 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 1 is used to trigger DMA channel to..,Prod Socket 1 is used to trigger DMA channel to..,?..."
bitfld.long 0x30 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA2_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA2"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA2_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod1"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA2_PA1_CONTROL,control register to manage pattern adapter on HWA2 prod socket1"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA2_PA1_PRODCOUNT,count values for HWA2 prod socket1"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA2_PROD2_CONTROL,Controlling producer socket2 for HWA2"
bitfld.long 0x44 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 2 is used to trigger DMA channel to..,Prod Socket 2 is used to trigger DMA channel to..,?..."
bitfld.long 0x44 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA2_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA2"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA2_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod2"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x50 "DMPAC_HTS_HWA2_PA2_CONTROL,control register to manage pattern adapter on HWA2 prod socket2"
hexmask.long.word 0x50 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x50 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x50 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x50 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x50 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x54 "DMPAC_HTS_HWA2_PA2_PRODCOUNT,count values for HWA2 prod socket2"
hexmask.long.word 0x54 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x54 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x58 "DMPAC_HTS_HWA2_PROD3_CONTROL,Controlling producer socket3 for HWA2"
bitfld.long 0x58 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 3 is used to trigger DMA channel to..,Prod Socket 3 is used to trigger DMA channel to..,?..."
bitfld.long 0x58 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x58 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x58 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x5C "DMPAC_HTS_HWA2_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA2"
bitfld.long 0x5C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x5C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x5C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x60 "DMPAC_HTS_HWA2_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod3"
hexmask.long.word 0x60 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x60 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x60 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x64 "DMPAC_HTS_HWA2_PA3_CONTROL,control register to manage pattern adapter on HWA2 prod socket3"
hexmask.long.word 0x64 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x64 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x64 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x64 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x64 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x68 "DMPAC_HTS_HWA2_PA3_PRODCOUNT,count values for HWA2 prod socket3"
hexmask.long.word 0x68 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x68 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x6C "DMPAC_HTS_HWA2_PROD4_CONTROL,Controlling producer socket4 for HWA2"
bitfld.long 0x6C 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4.tdone_mask[mask_select] applies to prod_socket4" "0,1,2,3"
hexmask.long.byte 0x6C 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 4.Used in decrementing count of producer buffer"
newline
bitfld.long 0x6C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x70 "DMPAC_HTS_HWA2_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA2"
bitfld.long 0x70 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x70 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x70 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x74 "DMPAC_HTS_HWA2_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod4"
hexmask.long.word 0x74 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x74 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x74 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x78 "DMPAC_HTS_HWA2_PA4_CONTROL,control register to manage pattern adapter on HWA2 prod socket4"
hexmask.long.word 0x78 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x78 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x78 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x78 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x78 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x7C "DMPAC_HTS_HWA2_PA4_PRODCOUNT,count values for HWA2 prod socket4"
hexmask.long.word 0x7C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x7C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DMPAC_HTS_HWA2_PROD5_CONTROL,Controlling producer socket5 for HWA2"
bitfld.long 0x80 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 5.tdone_mask[mask_select] applies to prod_socket5" "0,1,2,3"
hexmask.long.byte 0x80 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 5.Used in decrementing count of producer buffer"
newline
bitfld.long 0x80 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x84 "DMPAC_HTS_HWA2_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA2"
bitfld.long 0x84 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x84 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x84 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x88 "DMPAC_HTS_HWA2_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod5"
hexmask.long.word 0x88 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x88 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x88 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x8C "DMPAC_HTS_HWA2_PA5_CONTROL,control register to manage pattern adapter on HWA2 prod socket5"
hexmask.long.word 0x8C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x8C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x8C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x8C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x8C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x90 "DMPAC_HTS_HWA2_PA5_PRODCOUNT,count values for HWA2 prod socket5"
hexmask.long.word 0x90 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x90 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x94 "DMPAC_HTS_HWA2_PROD6_CONTROL,Controlling producer socket6 for HWA2"
bitfld.long 0x94 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 6.tdone_mask[mask_select] applies to prod_socket6" "0,1,2,3"
hexmask.long.byte 0x94 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 6.Used in decrementing count of producer buffer"
newline
bitfld.long 0x94 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x98 "DMPAC_HTS_HWA2_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA2"
bitfld.long 0x98 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x98 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x98 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x9C "DMPAC_HTS_HWA2_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod6"
hexmask.long.word 0x9C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x9C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x9C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0xA0 "DMPAC_HTS_HWA2_PA6_CONTROL,control register to manage pattern adapter on HWA2 prod socket6"
hexmask.long.word 0xA0 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0xA0 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0xA0 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0xA0 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0xA0 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0xA4 "DMPAC_HTS_HWA2_PA6_PRODCOUNT,count values for HWA2 prod socket6"
hexmask.long.word 0xA4 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0xA4 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "DMPAC_HTS_HWA2_PROD7_CONTROL,Controlling producer socket7 for HWA2"
bitfld.long 0xA8 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 7.tdone_mask[mask_select] applies to prod_socket7" "0,1,2,3"
hexmask.long.byte 0xA8 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 7.Used in decrementing count of producer buffer"
newline
bitfld.long 0xA8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0xAC "DMPAC_HTS_HWA2_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA2"
bitfld.long 0xAC 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0xAC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0xAC 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0xB0 "DMPAC_HTS_HWA2_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod7"
hexmask.long.word 0xB0 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0xB0 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0xB0 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x274++0xB3
line.long 0x00 "DMPAC_HTS_HWA3_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA3 Scheduler resources must not be read during halted state.'1'-> HWA3 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA3 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA3 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA3_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA3_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA3 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA3 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA3_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA3 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA3_CONS0_CONTROL,Controlling consumer socket 0 for HWA3"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA3_CONS1_CONTROL,Controlling consumer socket 1 for HWA3"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA3_CONS2_CONTROL,Controlling consumer socket 2 for HWA3"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA3_PROD0_CONTROL,Controlling producer socket0 for HWA3"
bitfld.long 0x1C 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 0 is used to trigger DMA channel to..,Prod Socket 0 is used to trigger DMA channel to..,?..."
bitfld.long 0x1C 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA3_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA3"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA3_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod0"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA3_PA0_CONTROL,control register to manage pattern adapter on HWA3 prod socket0"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA3_PA0_PRODCOUNT,count values for HWA3 prod socket0"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA3_PROD1_CONTROL,Controlling producer socket1 for HWA3"
bitfld.long 0x30 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 1 is used to trigger DMA channel to..,Prod Socket 1 is used to trigger DMA channel to..,?..."
bitfld.long 0x30 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA3_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA3"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA3_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod1"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA3_PA1_CONTROL,control register to manage pattern adapter on HWA3 prod socket1"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA3_PA1_PRODCOUNT,count values for HWA3 prod socket1"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA3_PROD2_CONTROL,Controlling producer socket2 for HWA3"
bitfld.long 0x44 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 2 is used to trigger DMA channel to..,Prod Socket 2 is used to trigger DMA channel to..,?..."
bitfld.long 0x44 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA3_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA3"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA3_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod2"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x50 "DMPAC_HTS_HWA3_PA2_CONTROL,control register to manage pattern adapter on HWA3 prod socket2"
hexmask.long.word 0x50 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x50 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x50 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x50 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x50 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x54 "DMPAC_HTS_HWA3_PA2_PRODCOUNT,count values for HWA3 prod socket2"
hexmask.long.word 0x54 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x54 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x58 "DMPAC_HTS_HWA3_PROD3_CONTROL,Controlling producer socket3 for HWA3"
bitfld.long 0x58 22.--23. "PARTIAL_BPR_TRIGMODE," "?,Prod Socket 3 is used to trigger DMA channel to..,Prod Socket 3 is used to trigger DMA channel to..,?..."
bitfld.long 0x58 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x58 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x58 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x5C "DMPAC_HTS_HWA3_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA3"
bitfld.long 0x5C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x5C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x5C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x60 "DMPAC_HTS_HWA3_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod3"
hexmask.long.word 0x60 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x60 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x60 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x64 "DMPAC_HTS_HWA3_PA3_CONTROL,control register to manage pattern adapter on HWA3 prod socket3"
hexmask.long.word 0x64 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x64 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x64 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x64 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x64 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x68 "DMPAC_HTS_HWA3_PA3_PRODCOUNT,count values for HWA3 prod socket3"
hexmask.long.word 0x68 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x68 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x6C "DMPAC_HTS_HWA3_PROD4_CONTROL,Controlling producer socket4 for HWA3"
bitfld.long 0x6C 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4.tdone_mask[mask_select] applies to prod_socket4" "0,1,2,3"
hexmask.long.byte 0x6C 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 4.Used in decrementing count of producer buffer"
newline
bitfld.long 0x6C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x70 "DMPAC_HTS_HWA3_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA3"
bitfld.long 0x70 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x70 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x70 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x74 "DMPAC_HTS_HWA3_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod4"
hexmask.long.word 0x74 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x74 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x74 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x78 "DMPAC_HTS_HWA3_PA4_CONTROL,control register to manage pattern adapter on HWA3 prod socket4"
hexmask.long.word 0x78 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x78 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x78 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x78 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x78 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x7C "DMPAC_HTS_HWA3_PA4_PRODCOUNT,count values for HWA3 prod socket4"
hexmask.long.word 0x7C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x7C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "DMPAC_HTS_HWA3_PROD5_CONTROL,Controlling producer socket5 for HWA3"
bitfld.long 0x80 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 5.tdone_mask[mask_select] applies to prod_socket5" "0,1,2,3"
hexmask.long.byte 0x80 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 5.Used in decrementing count of producer buffer"
newline
bitfld.long 0x80 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x84 "DMPAC_HTS_HWA3_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA3"
bitfld.long 0x84 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x84 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x84 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x88 "DMPAC_HTS_HWA3_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod5"
hexmask.long.word 0x88 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x88 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x88 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x8C "DMPAC_HTS_HWA3_PA5_CONTROL,control register to manage pattern adapter on HWA3 prod socket5"
hexmask.long.word 0x8C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x8C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x8C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x8C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x8C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x90 "DMPAC_HTS_HWA3_PA5_PRODCOUNT,count values for HWA3 prod socket5"
hexmask.long.word 0x90 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x90 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x94 "DMPAC_HTS_HWA3_PROD6_CONTROL,Controlling producer socket6 for HWA3"
bitfld.long 0x94 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 6.tdone_mask[mask_select] applies to prod_socket6" "0,1,2,3"
hexmask.long.byte 0x94 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 6.Used in decrementing count of producer buffer"
newline
bitfld.long 0x94 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x98 "DMPAC_HTS_HWA3_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA3"
bitfld.long 0x98 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x98 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x98 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x9C "DMPAC_HTS_HWA3_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod6"
hexmask.long.word 0x9C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x9C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x9C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0xA0 "DMPAC_HTS_HWA3_PA6_CONTROL,control register to manage pattern adapter on HWA3 prod socket6"
hexmask.long.word 0xA0 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0xA0 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0xA0 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0xA0 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0xA0 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0xA4 "DMPAC_HTS_HWA3_PA6_PRODCOUNT,count values for HWA3 prod socket6"
hexmask.long.word 0xA4 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0xA4 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "DMPAC_HTS_HWA3_PROD7_CONTROL,Controlling producer socket7 for HWA3"
bitfld.long 0xA8 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 7.tdone_mask[mask_select] applies to prod_socket7" "0,1,2,3"
hexmask.long.byte 0xA8 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 7.Used in decrementing count of producer buffer"
newline
bitfld.long 0xA8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0xAC "DMPAC_HTS_HWA3_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA3"
bitfld.long 0xAC 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0xAC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0xAC 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0xB0 "DMPAC_HTS_HWA3_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod7"
hexmask.long.word 0xB0 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0xB0 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0xB0 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x330++0x23
line.long 0x00 "DMPAC_HTS_HWA4_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA4 Scheduler resources must not be read during halted state.'1'-> HWA4 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA4 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA4 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA4_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA4 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA4 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA4_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA4 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA4_CONS0_CONTROL,Controlling consumer socket 0 for HWA4"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA4_CONS1_CONTROL,Controlling consumer socket 1 for HWA4"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA4_PROD0_CONTROL,Controlling producer socket0 for HWA4"
hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA4_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA4"
bitfld.long 0x1C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x20 "DMPAC_HTS_HWA4_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod0"
hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x35C++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD1_CONTROL,Controlling producer socket1 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod1"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x370++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD2_CONTROL,Controlling producer socket2 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod2"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x384++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD3_CONTROL,Controlling producer socket3 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x398++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD4_CONTROL,Controlling producer socket4 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 4.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3AC++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD5_CONTROL,Controlling producer socket5 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 5.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3C0++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD6_CONTROL,Controlling producer socket6 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 6.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3D4++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD7_CONTROL,Controlling producer socket7 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 7.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod7"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3E8++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD8_CONTROL,Controlling producer socket8 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 8.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD8_BUF_CONTROL,Controlling producer socket8 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD8_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod8"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3FC++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD9_CONTROL,Controlling producer socket9 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 9.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD9_BUF_CONTROL,Controlling producer socket9 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD9_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod9"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x410++0x0B
line.long 0x00 "DMPAC_HTS_HWA4_PROD10_CONTROL,Controlling producer socket10 for HWA4"
bitfld.long 0x00 24.--27. "MASK_SELECT,define which tdone_mask apply to prod socket 10.tdone_mask[mask_select] applies to prod_socket10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 10.Used in decrementing count of producer buffer"
newline
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA4_PROD10_BUF_CONTROL,Controlling producer socket10 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA4_PROD10_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod10"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x424++0x23
line.long 0x00 "DMPAC_HTS_HWA5_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA5 Scheduler resources must not be read during halted state.'1'-> HWA5 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA5 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA5 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA5_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA5 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA5 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA5_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA5 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA5_CONS0_CONTROL,Controlling consumer socket 0 for HWA5"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA5_CONS1_CONTROL,Controlling consumer socket 1 for HWA5"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA5_PROD0_CONTROL,Controlling producer socket0 for HWA5"
hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA5_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA5"
bitfld.long 0x1C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x20 "DMPAC_HTS_HWA5_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod0"
hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x450++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD1_CONTROL,Controlling producer socket1 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod1"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x464++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD2_CONTROL,Controlling producer socket2 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod2"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x478++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD3_CONTROL,Controlling producer socket3 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x48C++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD4_CONTROL,Controlling producer socket4 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 4.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4A0++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD5_CONTROL,Controlling producer socket5 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 5.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4B4++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD6_CONTROL,Controlling producer socket6 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 6.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4C8++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD7_CONTROL,Controlling producer socket7 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 7.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod7"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4DC++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD8_CONTROL,Controlling producer socket8 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 8.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD8_BUF_CONTROL,Controlling producer socket8 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD8_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod8"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4F0++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD9_CONTROL,Controlling producer socket9 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 9.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD9_BUF_CONTROL,Controlling producer socket9 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD9_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod9"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x504++0x0B
line.long 0x00 "DMPAC_HTS_HWA5_PROD10_CONTROL,Controlling producer socket10 for HWA5"
bitfld.long 0x00 24.--27. "MASK_SELECT,define which tdone_mask apply to prod socket 10.tdone_mask[mask_select] applies to prod_socket10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 10.Used in decrementing count of producer buffer"
newline
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA5_PROD10_BUF_CONTROL,Controlling producer socket10 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA5_PROD10_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod10"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x518++0x23
line.long 0x00 "DMPAC_HTS_HWA6_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA6 Scheduler resources must not be read during halted state.'1'-> HWA6 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA6 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA6 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA6_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA6_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA6 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA6 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA6_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA6 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA6_CONS0_CONTROL,Controlling consumer socket 0 for HWA6"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA6_CONS1_CONTROL,Controlling consumer socket 1 for HWA6"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA6_PROD0_CONTROL,Controlling producer socket0 for HWA6"
hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA6_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA6"
bitfld.long 0x1C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x20 "DMPAC_HTS_HWA6_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA6 prod0"
hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x544++0x0B
line.long 0x00 "DMPAC_HTS_HWA6_PROD1_CONTROL,Controlling producer socket1 for HWA6"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA6_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA6"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_HWA6_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA6 prod1"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x558++0x7F
line.long 0x00 "DMPAC_HTS_HWA7_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA7 Scheduler resources must not be read during halted state.'1'-> HWA7 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA7 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA7 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA7_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA7_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA7 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA7 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA7_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA7 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA7_CONS0_CONTROL,Controlling consumer socket 0 for HWA7"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA7_CONS1_CONTROL,Controlling consumer socket 1 for HWA7"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA7_CONS2_CONTROL,Controlling consumer socket 2 for HWA7"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA7_CONS3_CONTROL,Controlling consumer socket 3 for HWA7"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA7_CONS4_CONTROL,Controlling consumer socket 4 for HWA7"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "DMPAC_HTS_HWA7_PROD0_CONTROL,Controlling producer socket0 for HWA7"
hexmask.long.byte 0x24 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x24 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x28 "DMPAC_HTS_HWA7_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA7"
bitfld.long 0x28 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x28 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x28 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x2C "DMPAC_HTS_HWA7_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod0"
hexmask.long.word 0x2C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x2C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x2C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x30 "DMPAC_HTS_HWA7_PA0_CONTROL,control register to manage pattern adapter on HWA7 prod socket0"
hexmask.long.word 0x30 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x30 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x30 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x30 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x30 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA7_PA0_PRODCOUNT,count values for HWA7 prod socket0"
hexmask.long.word 0x34 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x34 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "DMPAC_HTS_HWA7_PROD1_CONTROL,Controlling producer socket1 for HWA7"
hexmask.long.byte 0x38 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x38 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x3C "DMPAC_HTS_HWA7_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA7"
bitfld.long 0x3C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x3C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x3C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x40 "DMPAC_HTS_HWA7_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod1"
hexmask.long.word 0x40 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x40 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x40 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x44 "DMPAC_HTS_HWA7_PA1_CONTROL,control register to manage pattern adapter on HWA7 prod socket1"
hexmask.long.word 0x44 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x44 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x44 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x44 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x44 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA7_PA1_PRODCOUNT,count values for HWA7 prod socket1"
hexmask.long.word 0x48 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x48 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4C "DMPAC_HTS_HWA7_PROD2_CONTROL,Controlling producer socket2 for HWA7"
hexmask.long.byte 0x4C 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x4C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x50 "DMPAC_HTS_HWA7_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA7"
bitfld.long 0x50 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x50 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x50 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x54 "DMPAC_HTS_HWA7_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod2"
hexmask.long.word 0x54 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x54 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x54 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x58 "DMPAC_HTS_HWA7_PA2_CONTROL,control register to manage pattern adapter on HWA7 prod socket2"
hexmask.long.word 0x58 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x58 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x58 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x58 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x58 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x5C "DMPAC_HTS_HWA7_PA2_PRODCOUNT,count values for HWA7 prod socket2"
hexmask.long.word 0x5C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x5C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "DMPAC_HTS_HWA7_PROD3_CONTROL,Controlling producer socket3 for HWA7"
hexmask.long.byte 0x60 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x60 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x64 "DMPAC_HTS_HWA7_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA7"
bitfld.long 0x64 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x64 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x64 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x68 "DMPAC_HTS_HWA7_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod3"
hexmask.long.word 0x68 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x68 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x68 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x6C "DMPAC_HTS_HWA7_PA3_CONTROL,control register to manage pattern adapter on HWA7 prod socket3"
hexmask.long.word 0x6C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x6C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x6C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x6C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x6C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x70 "DMPAC_HTS_HWA7_PA3_PRODCOUNT,count values for HWA7 prod socket3"
hexmask.long.word 0x70 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x70 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x74 "DMPAC_HTS_HWA7_PROD4_CONTROL,Controlling producer socket4 for HWA7"
bitfld.long 0x74 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4.tdone_mask[mask_select] applies to prod_socket4" "0,1,2,3"
hexmask.long.byte 0x74 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 4.Used in decrementing count of producer buffer"
newline
bitfld.long 0x74 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x78 "DMPAC_HTS_HWA7_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA7"
bitfld.long 0x78 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x78 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x78 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x7C "DMPAC_HTS_HWA7_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod4"
hexmask.long.word 0x7C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x7C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x7C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x5E0++0x7F
line.long 0x00 "DMPAC_HTS_HWA8_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA8 Scheduler resources must not be read during halted state.'1'-> HWA8 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA8 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA8 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA8_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "DMPAC_HTS_HWA8_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA8 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
newline
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA8 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "DMPAC_HTS_HWA8_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA8 sch '0' --> Disable" "0,1"
line.long 0x10 "DMPAC_HTS_HWA8_CONS0_CONTROL,Controlling consumer socket 0 for HWA8"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "DMPAC_HTS_HWA8_CONS1_CONTROL,Controlling consumer socket 1 for HWA8"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA8_CONS2_CONTROL,Controlling consumer socket 2 for HWA8"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "DMPAC_HTS_HWA8_CONS3_CONTROL,Controlling consumer socket 3 for HWA8"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA8_CONS4_CONTROL,Controlling consumer socket 4 for HWA8"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "DMPAC_HTS_HWA8_PROD0_CONTROL,Controlling producer socket0 for HWA8"
hexmask.long.byte 0x24 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x24 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x28 "DMPAC_HTS_HWA8_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA8"
bitfld.long 0x28 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x28 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x28 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x2C "DMPAC_HTS_HWA8_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod0"
hexmask.long.word 0x2C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x2C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x2C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x30 "DMPAC_HTS_HWA8_PA0_CONTROL,control register to manage pattern adapter on HWA8 prod socket0"
hexmask.long.word 0x30 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x30 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x30 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x30 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x30 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA8_PA0_PRODCOUNT,count values for HWA8 prod socket0"
hexmask.long.word 0x34 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x34 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "DMPAC_HTS_HWA8_PROD1_CONTROL,Controlling producer socket1 for HWA8"
hexmask.long.byte 0x38 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x38 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x3C "DMPAC_HTS_HWA8_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA8"
bitfld.long 0x3C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x3C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x3C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x40 "DMPAC_HTS_HWA8_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod1"
hexmask.long.word 0x40 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x40 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x40 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x44 "DMPAC_HTS_HWA8_PA1_CONTROL,control register to manage pattern adapter on HWA8 prod socket1"
hexmask.long.word 0x44 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x44 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x44 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x44 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x44 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA8_PA1_PRODCOUNT,count values for HWA8 prod socket1"
hexmask.long.word 0x48 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x48 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4C "DMPAC_HTS_HWA8_PROD2_CONTROL,Controlling producer socket2 for HWA8"
hexmask.long.byte 0x4C 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x4C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x50 "DMPAC_HTS_HWA8_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA8"
bitfld.long 0x50 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x50 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x50 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x54 "DMPAC_HTS_HWA8_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod2"
hexmask.long.word 0x54 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x54 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x54 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x58 "DMPAC_HTS_HWA8_PA2_CONTROL,control register to manage pattern adapter on HWA8 prod socket2"
hexmask.long.word 0x58 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x58 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x58 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x58 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x58 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x5C "DMPAC_HTS_HWA8_PA2_PRODCOUNT,count values for HWA8 prod socket2"
hexmask.long.word 0x5C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x5C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "DMPAC_HTS_HWA8_PROD3_CONTROL,Controlling producer socket3 for HWA8"
hexmask.long.byte 0x60 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x60 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x64 "DMPAC_HTS_HWA8_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA8"
bitfld.long 0x64 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x64 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x64 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x68 "DMPAC_HTS_HWA8_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod3"
hexmask.long.word 0x68 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x68 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x68 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x6C "DMPAC_HTS_HWA8_PA3_CONTROL,control register to manage pattern adapter on HWA8 prod socket3"
hexmask.long.word 0x6C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x6C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x6C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x6C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x6C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x70 "DMPAC_HTS_HWA8_PA3_PRODCOUNT,count values for HWA8 prod socket3"
hexmask.long.word 0x70 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x70 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x74 "DMPAC_HTS_HWA8_PROD4_CONTROL,Controlling producer socket4 for HWA8"
bitfld.long 0x74 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4.tdone_mask[mask_select] applies to prod_socket4" "0,1,2,3"
hexmask.long.byte 0x74 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 4.Used in decrementing count of producer buffer"
newline
bitfld.long 0x74 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x78 "DMPAC_HTS_HWA8_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA8"
bitfld.long 0x78 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x78 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x78 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x7C "DMPAC_HTS_HWA8_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod4"
hexmask.long.word 0x7C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x7C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x7C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x668++0x07
line.long 0x00 "DMPAC_HTS_HWA12_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA12"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA12 Scheduler resources must not be read during halted state.'1'-> HWA12 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA12 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA12 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA12_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x678++0x4F
line.long 0x00 "DMPAC_HTS_HWA12_CONS0_CONTROL,Controlling consumer socket 0 for HWA12"
bitfld.long 0x00 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1"
bitfld.long 0x00 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1"
newline
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA12_CONS1_CONTROL,Controlling consumer socket 1 for HWA12"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA12_PROD0_CONTROL,Controlling producer socket0 for HWA12"
bitfld.long 0x08 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1"
bitfld.long 0x08 30. "PROD_DEC,writing '1' decrement prod count value" "0,1"
newline
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA12_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA12"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA12_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA12_PA0_CONTROL,control register to manage pattern adapter on HWA12 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA12_PA0_PRODCOUNT,count values for HWA12 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA12_PROD1_CONTROL,Controlling producer socket1 for HWA12"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA12_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA12"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA12_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA12_PA1_CONTROL,control register to manage pattern adapter on HWA12 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA12_PA1_PRODCOUNT,count values for HWA12 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA12_PROD2_CONTROL,Controlling producer socket2 for HWA12"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA12_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA12"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA12_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA12_PA2_CONTROL,control register to manage pattern adapter on HWA12 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA12_PA2_PRODCOUNT,count values for HWA12 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA12_PROD3_CONTROL,Controlling producer socket3 for HWA12"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA12_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA12"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA12_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x6D0++0x07
line.long 0x00 "DMPAC_HTS_HWA13_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA13"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA13 Scheduler resources must not be read during halted state.'1'-> HWA13 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA13 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA13 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA13_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x6E0++0x4F
line.long 0x00 "DMPAC_HTS_HWA13_CONS0_CONTROL,Controlling consumer socket 0 for HWA13"
bitfld.long 0x00 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1"
bitfld.long 0x00 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1"
newline
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA13_CONS1_CONTROL,Controlling consumer socket 1 for HWA13"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA13_PROD0_CONTROL,Controlling producer socket0 for HWA13"
bitfld.long 0x08 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1"
bitfld.long 0x08 30. "PROD_DEC,writing '1' decrement prod count value" "0,1"
newline
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA13_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA13"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA13_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA13_PA0_CONTROL,control register to manage pattern adapter on HWA13 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA13_PA0_PRODCOUNT,count values for HWA13 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA13_PROD1_CONTROL,Controlling producer socket1 for HWA13"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA13_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA13"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA13_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA13_PA1_CONTROL,control register to manage pattern adapter on HWA13 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA13_PA1_PRODCOUNT,count values for HWA13 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA13_PROD2_CONTROL,Controlling producer socket2 for HWA13"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA13_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA13"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA13_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA13_PA2_CONTROL,control register to manage pattern adapter on HWA13 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA13_PA2_PRODCOUNT,count values for HWA13 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA13_PROD3_CONTROL,Controlling producer socket3 for HWA13"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA13_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA13"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA13_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x738++0x07
line.long 0x00 "DMPAC_HTS_HWA14_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA14"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA14 Scheduler resources must not be read during halted state.'1'-> HWA14 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA14 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA14 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA14_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x748++0x4F
line.long 0x00 "DMPAC_HTS_HWA14_CONS0_CONTROL,Controlling consumer socket 0 for HWA14"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA14_CONS1_CONTROL,Controlling consumer socket 1 for HWA14"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA14_PROD0_CONTROL,Controlling producer socket0 for HWA14"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA14_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA14"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA14_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA14_PA0_CONTROL,control register to manage pattern adapter on HWA14 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA14_PA0_PRODCOUNT,count values for HWA14 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA14_PROD1_CONTROL,Controlling producer socket1 for HWA14"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA14_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA14"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA14_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA14_PA1_CONTROL,control register to manage pattern adapter on HWA14 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA14_PA1_PRODCOUNT,count values for HWA14 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA14_PROD2_CONTROL,Controlling producer socket2 for HWA14"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA14_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA14"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA14_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA14_PA2_CONTROL,control register to manage pattern adapter on HWA14 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA14_PA2_PRODCOUNT,count values for HWA14 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA14_PROD3_CONTROL,Controlling producer socket3 for HWA14"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA14_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA14"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA14_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x7A0++0x07
line.long 0x00 "DMPAC_HTS_HWA15_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA15"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA15 Scheduler resources must not be read during halted state.'1'-> HWA15 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA15 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA15 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA15_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x7B0++0x4F
line.long 0x00 "DMPAC_HTS_HWA15_CONS0_CONTROL,Controlling consumer socket 0 for HWA15"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA15_CONS1_CONTROL,Controlling consumer socket 1 for HWA15"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA15_PROD0_CONTROL,Controlling producer socket0 for HWA15"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA15_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA15"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA15_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA15_PA0_CONTROL,control register to manage pattern adapter on HWA15 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA15_PA0_PRODCOUNT,count values for HWA15 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA15_PROD1_CONTROL,Controlling producer socket1 for HWA15"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA15_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA15"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA15_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA15_PA1_CONTROL,control register to manage pattern adapter on HWA15 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA15_PA1_PRODCOUNT,count values for HWA15 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA15_PROD2_CONTROL,Controlling producer socket2 for HWA15"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA15_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA15"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA15_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA15_PA2_CONTROL,control register to manage pattern adapter on HWA15 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA15_PA2_PRODCOUNT,count values for HWA15 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA15_PROD3_CONTROL,Controlling producer socket3 for HWA15"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA15_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA15"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA15_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x808++0x07
line.long 0x00 "DMPAC_HTS_HWA16_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA16"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA16 Scheduler resources must not be read during halted state.'1'-> HWA16 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA16 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA16 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA16_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x818++0x4F
line.long 0x00 "DMPAC_HTS_HWA16_CONS0_CONTROL,Controlling consumer socket 0 for HWA16"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA16_CONS1_CONTROL,Controlling consumer socket 1 for HWA16"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA16_PROD0_CONTROL,Controlling producer socket0 for HWA16"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA16_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA16"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA16_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA16_PA0_CONTROL,control register to manage pattern adapter on HWA16 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA16_PA0_PRODCOUNT,count values for HWA16 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA16_PROD1_CONTROL,Controlling producer socket1 for HWA16"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA16_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA16"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA16_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA16_PA1_CONTROL,control register to manage pattern adapter on HWA16 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA16_PA1_PRODCOUNT,count values for HWA16 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA16_PROD2_CONTROL,Controlling producer socket2 for HWA16"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA16_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA16"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA16_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA16_PA2_CONTROL,control register to manage pattern adapter on HWA16 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA16_PA2_PRODCOUNT,count values for HWA16 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA16_PROD3_CONTROL,Controlling producer socket3 for HWA16"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA16_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA16"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA16_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x870++0x07
line.long 0x00 "DMPAC_HTS_HWA17_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA17"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA17 Scheduler resources must not be read during halted state.'1'-> HWA17 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA17 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA17 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA17_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x880++0x4F
line.long 0x00 "DMPAC_HTS_HWA17_CONS0_CONTROL,Controlling consumer socket 0 for HWA17"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA17_CONS1_CONTROL,Controlling consumer socket 1 for HWA17"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA17_PROD0_CONTROL,Controlling producer socket0 for HWA17"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA17_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA17"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA17_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA17_PA0_CONTROL,control register to manage pattern adapter on HWA17 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA17_PA0_PRODCOUNT,count values for HWA17 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA17_PROD1_CONTROL,Controlling producer socket1 for HWA17"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA17_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA17"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA17_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA17_PA1_CONTROL,control register to manage pattern adapter on HWA17 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA17_PA1_PRODCOUNT,count values for HWA17 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA17_PROD2_CONTROL,Controlling producer socket2 for HWA17"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA17_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA17"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA17_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA17_PA2_CONTROL,control register to manage pattern adapter on HWA17 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA17_PA2_PRODCOUNT,count values for HWA17 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA17_PROD3_CONTROL,Controlling producer socket3 for HWA17"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA17_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA17"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA17_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x8D8++0x07
line.long 0x00 "DMPAC_HTS_HWA18_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA18"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA18 Scheduler resources must not be read during halted state.'1'-> HWA18 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA18 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA18 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA18_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x8E8++0x4F
line.long 0x00 "DMPAC_HTS_HWA18_CONS0_CONTROL,Controlling consumer socket 0 for HWA18"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA18_CONS1_CONTROL,Controlling consumer socket 1 for HWA18"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA18_PROD0_CONTROL,Controlling producer socket0 for HWA18"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA18_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA18"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA18_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA18_PA0_CONTROL,control register to manage pattern adapter on HWA18 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA18_PA0_PRODCOUNT,count values for HWA18 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA18_PROD1_CONTROL,Controlling producer socket1 for HWA18"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA18_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA18"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA18_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA18_PA1_CONTROL,control register to manage pattern adapter on HWA18 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA18_PA1_PRODCOUNT,count values for HWA18 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA18_PROD2_CONTROL,Controlling producer socket2 for HWA18"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA18_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA18"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA18_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA18_PA2_CONTROL,control register to manage pattern adapter on HWA18 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA18_PA2_PRODCOUNT,count values for HWA18 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA18_PROD3_CONTROL,Controlling producer socket3 for HWA18"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA18_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA18"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA18_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x940++0x07
line.long 0x00 "DMPAC_HTS_HWA19_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA19"
newline
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA19 Scheduler resources must not be read during halted state.'1'-> HWA19 Scheduler resources are readable during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA19 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA19 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_HWA19_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x950++0x4F
line.long 0x00 "DMPAC_HTS_HWA19_CONS0_CONTROL,Controlling consumer socket 0 for HWA19"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_HWA19_CONS1_CONTROL,Controlling consumer socket 1 for HWA19"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "DMPAC_HTS_HWA19_PROD0_CONTROL,Controlling producer socket0 for HWA19"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "DMPAC_HTS_HWA19_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA19"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "DMPAC_HTS_HWA19_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "DMPAC_HTS_HWA19_PA0_CONTROL,control register to manage pattern adapter on HWA19 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "DMPAC_HTS_HWA19_PA0_PRODCOUNT,count values for HWA19 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMPAC_HTS_HWA19_PROD1_CONTROL,Controlling producer socket1 for HWA19"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 1.Used in decrementing count of producer buffer"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "DMPAC_HTS_HWA19_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA19"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "DMPAC_HTS_HWA19_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "DMPAC_HTS_HWA19_PA1_CONTROL,control register to manage pattern adapter on HWA19 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "DMPAC_HTS_HWA19_PA1_PRODCOUNT,count values for HWA19 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "DMPAC_HTS_HWA19_PROD2_CONTROL,Controlling producer socket2 for HWA19"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 2.Used in decrementing count of producer buffer"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "DMPAC_HTS_HWA19_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA19"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "DMPAC_HTS_HWA19_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "DMPAC_HTS_HWA19_PA2_CONTROL,control register to manage pattern adapter on HWA19 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "DMPAC_HTS_HWA19_PA2_PRODCOUNT,count values for HWA19 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DMPAC_HTS_HWA19_PROD3_CONTROL,Controlling producer socket3 for HWA19"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 3.Used in decrementing count of producer buffer"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "DMPAC_HTS_HWA19_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA19"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "DMPAC_HTS_HWA19_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x9A8++0x07
line.long 0x00 "DMPAC_HTS_DMA0_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA0"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA0 Scheduler resources must not be read during halted state.'1'-> DMA0 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA0 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA0 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA0_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x9B8++0x13
line.long 0x00 "DMPAC_HTS_DMA0_PROD0_CONTROL,Controlling producer socket0 for DMA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA0 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA0_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA0_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA0 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA1_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA1"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA1 Scheduler resources must not be read during halted state.'1'-> DMA1 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA1 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA1 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA1_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x9D4++0x13
line.long 0x00 "DMPAC_HTS_DMA1_PROD0_CONTROL,Controlling producer socket0 for DMA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA1 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA1_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA1_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA1 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA2_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA2"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA2 Scheduler resources must not be read during halted state.'1'-> DMA2 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA2 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA2 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA2_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x9F0++0x13
line.long 0x00 "DMPAC_HTS_DMA2_PROD0_CONTROL,Controlling producer socket0 for DMA2"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA2 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA2_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA2"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA2_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA2 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA3_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA3"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA3 Scheduler resources must not be read during halted state.'1'-> DMA3 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA3 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA3 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA3_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xA0C++0x13
line.long 0x00 "DMPAC_HTS_DMA3_PROD0_CONTROL,Controlling producer socket0 for DMA3"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA3 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA3_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA3"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA3_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA3 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA4_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA4"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA4 Scheduler resources must not be read during halted state.'1'-> DMA4 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA4 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA4 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA4_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xA28++0x0B
line.long 0x00 "DMPAC_HTS_DMA4_PROD0_CONTROL,Controlling producer socket0 for DMA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA4 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA4_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA4_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA4 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xA88++0x07
line.long 0x00 "DMPAC_HTS_DMA8_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA8"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA8 Scheduler resources must not be read during halted state.'1'-> DMA8 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA8 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA8 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA8_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xA98++0x1B
line.long 0x00 "DMPAC_HTS_DMA8_PROD0_CONTROL,Controlling producer socket0 for DMA8"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA8 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA8_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA8"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA8_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA8 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA8_PA0_CONTROL,control register to manage pattern adapter on DMA8 prod socket0"
hexmask.long.word 0x0C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x0C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x0C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x0C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x0C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x10 "DMPAC_HTS_DMA8_PA0_PRODCOUNT,count values for HWA8 prod socket0"
hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x10 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMPAC_HTS_DMA9_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x14 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA9"
bitfld.long 0x14 12. "DEBUG_RDY,'0' -> DMA9 Scheduler resources must not be read during halted state.'1'-> DMA9 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x14 7.--10. "STATE,Current state of DMA9 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x14 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x14 1.--3. "PIPELINE_NUM,Pipeline Number of DMA9 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x18 "DMPAC_HTS_DMA9_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x18 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x18 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xABC++0x1B
line.long 0x00 "DMPAC_HTS_DMA9_PROD0_CONTROL,Controlling producer socket0 for DMA9"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA9 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA9_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA9"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA9_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA9 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA9_PA0_CONTROL,control register to manage pattern adapter on DMA9 prod socket0"
hexmask.long.word 0x0C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x0C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x0C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x0C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x0C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x10 "DMPAC_HTS_DMA9_PA0_PRODCOUNT,count values for HWA9 prod socket0"
hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x10 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMPAC_HTS_DMA10_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x14 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA10"
bitfld.long 0x14 12. "DEBUG_RDY,'0' -> DMA10 Scheduler resources must not be read during halted state.'1'-> DMA10 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x14 7.--10. "STATE,Current state of DMA10 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x14 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x14 1.--3. "PIPELINE_NUM,Pipeline Number of DMA10 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x18 "DMPAC_HTS_DMA10_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x18 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x18 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xAE0++0x13
line.long 0x00 "DMPAC_HTS_DMA10_PROD0_CONTROL,Controlling producer socket0 for DMA10"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA10 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA10_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA10"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA10_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA10 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA10_PA0_CONTROL,control register to manage pattern adapter on DMA10 prod socket0"
hexmask.long.word 0x0C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x0C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
newline
bitfld.long 0x0C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern.." "0,1"
bitfld.long 0x0C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x0C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x10 "DMPAC_HTS_DMA10_PA0_PRODCOUNT,count values for HWA10 prod socket0"
hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x10 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD40++0x07
line.long 0x00 "DMPAC_HTS_DMA32_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA32"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA32 Scheduler resources must not be read during halted state.'1'-> DMA32 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA32 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA32 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA32_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xD50++0x0B
line.long 0x00 "DMPAC_HTS_DMA32_PROD0_CONTROL,Controlling producer socket0 for DMA32"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA32 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA32_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA32"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA32_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA32 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xE20++0x07
line.long 0x00 "DMPAC_HTS_DMA40_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA40"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA40 Scheduler resources must not be read during halted state.'1'-> DMA40 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA40 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA40 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA40_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xE30++0x0B
line.long 0x00 "DMPAC_HTS_DMA40_PROD0_CONTROL,Controlling producer socket0 for DMA40"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA40 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA40_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA40"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA40_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA40 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xF00++0x07
line.long 0x00 "DMPAC_HTS_DMA48_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA48"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA48 Scheduler resources must not be read during halted state.'1'-> DMA48 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA48 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA48 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA48_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xF10++0x0B
line.long 0x00 "DMPAC_HTS_DMA48_PROD0_CONTROL,Controlling producer socket0 for DMA48"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA48 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA48_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA48"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA48_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA48 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xFE0++0x07
line.long 0x00 "DMPAC_HTS_DMA56_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA56"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA56 Scheduler resources must not be read during halted state.'1'-> DMA56 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA56 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA56 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA56_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xFF0++0x13
line.long 0x00 "DMPAC_HTS_DMA56_PROD0_CONTROL,Controlling producer socket0 for DMA56"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA56 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA56_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA56"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA56_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA56 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA57_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA57"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA57 Scheduler resources must not be read during halted state.'1'-> DMA57 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA57 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA57 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA57_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x100C++0x13
line.long 0x00 "DMPAC_HTS_DMA57_PROD0_CONTROL,Controlling producer socket0 for DMA57"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA57 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA57_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA57"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA57_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA57 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA58_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA58"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA58 Scheduler resources must not be read during halted state.'1'-> DMA58 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA58 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA58 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA58_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1028++0x13
line.long 0x00 "DMPAC_HTS_DMA58_PROD0_CONTROL,Controlling producer socket0 for DMA58"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA58 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA58_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA58"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA58_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA58 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA59_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA59"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA59 Scheduler resources must not be read during halted state.'1'-> DMA59 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA59 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA59 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA59_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1044++0x0B
line.long 0x00 "DMPAC_HTS_DMA59_PROD0_CONTROL,Controlling producer socket0 for DMA59"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA59 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA59_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA59"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA59_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA59 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x10C0++0x07
line.long 0x00 "DMPAC_HTS_DMA64_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA64"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA64 Scheduler resources must not be read during halted state.'1'-> DMA64 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA64 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA64 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x04 "DMPAC_HTS_DMA64_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x10D0++0x13
line.long 0x00 "DMPAC_HTS_DMA64_PROD0_CONTROL,Controlling producer socket0 for DMA64"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA64 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA64_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA64"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA64_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA64 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA65_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA65"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA65 Scheduler resources must not be read during halted state.'1'-> DMA65 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA65 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA65 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA65_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x10EC++0x13
line.long 0x00 "DMPAC_HTS_DMA65_PROD0_CONTROL,Controlling producer socket0 for DMA65"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA65 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA65_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA65"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA65_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA65 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA66_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA66"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA66 Scheduler resources must not be read during halted state.'1'-> DMA66 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA66 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA66 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA66_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1108++0x13
line.long 0x00 "DMPAC_HTS_DMA66_PROD0_CONTROL,Controlling producer socket0 for DMA66"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA66 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA66_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA66"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA66_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA66 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "DMPAC_HTS_DMA67_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA67"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA67 Scheduler resources must not be read during halted state.'1'-> DMA67 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA67 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA67 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
line.long 0x10 "DMPAC_HTS_DMA67_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1124++0x0B
line.long 0x00 "DMPAC_HTS_DMA67_PROD0_CONTROL,Controlling producer socket0 for DMA67"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA67 prod socket 0.Used in decrementing count of producer buffer"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA67_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA67"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
newline
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "DMPAC_HTS_DMA67_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA67 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
newline
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x21B4++0x03
line.long 0x00 "DMPAC_HTS_DMA240_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA240"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA240 Scheduler resources must not be read during halted state.'1'-> DMA240 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA240 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA240 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x21C4++0x07
line.long 0x00 "DMPAC_HTS_DMA240_CONS0_CONTROL,Controlling consumer socket 0 for DMA240"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA240 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA241_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA241"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA241 Scheduler resources must not be read during halted state.'1'-> DMA241 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA241 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA241 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x21D8++0x07
line.long 0x00 "DMPAC_HTS_DMA241_CONS0_CONTROL,Controlling consumer socket 0 for DMA241"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA241 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA242_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA242"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA242 Scheduler resources must not be read during halted state.'1'-> DMA242 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA242 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA242 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x21EC++0x07
line.long 0x00 "DMPAC_HTS_DMA242_CONS0_CONTROL,Controlling consumer socket 0 for DMA242"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA242 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA243_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA243"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA243 Scheduler resources must not be read during halted state.'1'-> DMA243 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA243 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA243 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2200++0x07
line.long 0x00 "DMPAC_HTS_DMA243_CONS0_CONTROL,Controlling consumer socket 0 for DMA243"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA243 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA244_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA244"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA244 Scheduler resources must not be read during halted state.'1'-> DMA244 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA244 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA244 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2214++0x07
line.long 0x00 "DMPAC_HTS_DMA244_CONS0_CONTROL,Controlling consumer socket 0 for DMA244"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA244 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA245_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA245"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA245 Scheduler resources must not be read during halted state.'1'-> DMA245 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA245 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA245 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2228++0x07
line.long 0x00 "DMPAC_HTS_DMA245_CONS0_CONTROL,Controlling consumer socket 0 for DMA245"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA245 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA256_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA256"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA256 Scheduler resources must not be read during halted state.'1'-> DMA256 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA256 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA256 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x223C++0x07
line.long 0x00 "DMPAC_HTS_DMA256_CONS0_CONTROL,Controlling consumer socket 0 for DMA256"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA256 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA257_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA257"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA257 Scheduler resources must not be read during halted state.'1'-> DMA257 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA257 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA257 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2250++0x07
line.long 0x00 "DMPAC_HTS_DMA257_CONS0_CONTROL,Controlling consumer socket 0 for DMA257"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA257 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA258_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA258"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA258 Scheduler resources must not be read during halted state.'1'-> DMA258 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA258 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA258 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2264++0x07
line.long 0x00 "DMPAC_HTS_DMA258_CONS0_CONTROL,Controlling consumer socket 0 for DMA258"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA258 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA259_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA259"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA259 Scheduler resources must not be read during halted state.'1'-> DMA259 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA259 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA259 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2278++0x07
line.long 0x00 "DMPAC_HTS_DMA259_CONS0_CONTROL,Controlling consumer socket 0 for DMA259"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA259 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA260_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA260"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA260 Scheduler resources must not be read during halted state.'1'-> DMA260 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA260 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA260 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x228C++0x07
line.long 0x00 "DMPAC_HTS_DMA260_CONS0_CONTROL,Controlling consumer socket 0 for DMA260"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA260 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA261_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA261"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA261 Scheduler resources must not be read during halted state.'1'-> DMA261 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA261 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA261 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x22A0++0x07
line.long 0x00 "DMPAC_HTS_DMA261_CONS0_CONTROL,Controlling consumer socket 0 for DMA261"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA261 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA272_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA272"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA272 Scheduler resources must not be read during halted state.'1'-> DMA272 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA272 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA272 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x22B4++0x07
line.long 0x00 "DMPAC_HTS_DMA272_CONS0_CONTROL,Controlling consumer socket 0 for DMA272"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA272 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA273_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA273"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA273 Scheduler resources must not be read during halted state.'1'-> DMA273 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA273 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA273 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x22C8++0x07
line.long 0x00 "DMPAC_HTS_DMA273_CONS0_CONTROL,Controlling consumer socket 0 for DMA273"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA273 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA274_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA274"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA274 Scheduler resources must not be read during halted state.'1'-> DMA274 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA274 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA274 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x22DC++0x07
line.long 0x00 "DMPAC_HTS_DMA274_CONS0_CONTROL,Controlling consumer socket 0 for DMA274"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA274 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA275_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA275"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA275 Scheduler resources must not be read during halted state.'1'-> DMA275 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA275 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA275 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x22F0++0x07
line.long 0x00 "DMPAC_HTS_DMA275_CONS0_CONTROL,Controlling consumer socket 0 for DMA275"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA275 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA288_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA288"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA288 Scheduler resources must not be read during halted state.'1'-> DMA288 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA288 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA288 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2304++0x07
line.long 0x00 "DMPAC_HTS_DMA288_CONS0_CONTROL,Controlling consumer socket 0 for DMA288"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA288 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA289_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA289"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA289 Scheduler resources must not be read during halted state.'1'-> DMA289 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA289 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA289 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2318++0x07
line.long 0x00 "DMPAC_HTS_DMA289_CONS0_CONTROL,Controlling consumer socket 0 for DMA289"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA289 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA290_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA290"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA290 Scheduler resources must not be read during halted state.'1'-> DMA290 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA290 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA290 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x232C++0x07
line.long 0x00 "DMPAC_HTS_DMA290_CONS0_CONTROL,Controlling consumer socket 0 for DMA290"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA290 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA291_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA291"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA291 Scheduler resources must not be read during halted state.'1'-> DMA291 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA291 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA291 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2340++0x07
line.long 0x00 "DMPAC_HTS_DMA291_CONS0_CONTROL,Controlling consumer socket 0 for DMA291"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA291 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA304_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA304"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA304 Scheduler resources must not be read during halted state.'1'-> DMA304 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA304 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA304 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2354++0x07
line.long 0x00 "DMPAC_HTS_DMA304_CONS0_CONTROL,Controlling consumer socket 0 for DMA304"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA304 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA305_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA305"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA305 Scheduler resources must not be read during halted state.'1'-> DMA305 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA305 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA305 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2368++0x07
line.long 0x00 "DMPAC_HTS_DMA305_CONS0_CONTROL,Controlling consumer socket 0 for DMA305"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA305 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA306_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA306"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA306 Scheduler resources must not be read during halted state.'1'-> DMA306 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA306 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA306 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x237C++0x07
line.long 0x00 "DMPAC_HTS_DMA306_CONS0_CONTROL,Controlling consumer socket 0 for DMA306"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA306 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA307_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA307"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA307 Scheduler resources must not be read during halted state.'1'-> DMA307 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA307 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA307 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2390++0x07
line.long 0x00 "DMPAC_HTS_DMA307_CONS0_CONTROL,Controlling consumer socket 0 for DMA307"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA307 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA308_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA308"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA308 Scheduler resources must not be read during halted state.'1'-> DMA308 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA308 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA308 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x23A4++0x07
line.long 0x00 "DMPAC_HTS_DMA308_CONS0_CONTROL,Controlling consumer socket 0 for DMA308"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA308 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA309_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA309"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA309 Scheduler resources must not be read during halted state.'1'-> DMA309 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA309 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA309 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x23B8++0x07
line.long 0x00 "DMPAC_HTS_DMA309_CONS0_CONTROL,Controlling consumer socket 0 for DMA309"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA309 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA310_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA310"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA310 Scheduler resources must not be read during halted state.'1'-> DMA310 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA310 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA310 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x23CC++0x07
line.long 0x00 "DMPAC_HTS_DMA310_CONS0_CONTROL,Controlling consumer socket 0 for DMA310"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA310 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA311_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA311"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA311 Scheduler resources must not be read during halted state.'1'-> DMA311 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA311 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA311 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x23E0++0x07
line.long 0x00 "DMPAC_HTS_DMA311_CONS0_CONTROL,Controlling consumer socket 0 for DMA311"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA311 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA312_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA312"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA312 Scheduler resources must not be read during halted state.'1'-> DMA312 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA312 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA312 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x23F4++0x07
line.long 0x00 "DMPAC_HTS_DMA312_CONS0_CONTROL,Controlling consumer socket 0 for DMA312"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA312 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA313_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA313"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA313 Scheduler resources must not be read during halted state.'1'-> DMA313 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA313 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA313 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2408++0x07
line.long 0x00 "DMPAC_HTS_DMA313_CONS0_CONTROL,Controlling consumer socket 0 for DMA313"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA313 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA336_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA336"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA336 Scheduler resources must not be read during halted state.'1'-> DMA336 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA336 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA336 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x241C++0x07
line.long 0x00 "DMPAC_HTS_DMA336_CONS0_CONTROL,Controlling consumer socket 0 for DMA336"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA336 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA352_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA352"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA352 Scheduler resources must not be read during halted state.'1'-> DMA352 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA352 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA352 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2430++0x07
line.long 0x00 "DMPAC_HTS_DMA352_CONS0_CONTROL,Controlling consumer socket 0 for DMA352"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA352 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA353_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA353"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA353 Scheduler resources must not be read during halted state.'1'-> DMA353 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA353 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA353 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2444++0x07
line.long 0x00 "DMPAC_HTS_DMA353_CONS0_CONTROL,Controlling consumer socket 0 for DMA353"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA353 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA354_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA354"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA354 Scheduler resources must not be read during halted state.'1'-> DMA354 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA354 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA354 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2458++0x07
line.long 0x00 "DMPAC_HTS_DMA354_CONS0_CONTROL,Controlling consumer socket 0 for DMA354"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA354 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA355_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA355"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA355 Scheduler resources must not be read during halted state.'1'-> DMA355 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA355 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA355 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x246C++0x07
line.long 0x00 "DMPAC_HTS_DMA355_CONS0_CONTROL,Controlling consumer socket 0 for DMA355"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA355 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA368_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA368"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA368 Scheduler resources must not be read during halted state.'1'-> DMA368 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA368 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA368 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2480++0x07
line.long 0x00 "DMPAC_HTS_DMA368_CONS0_CONTROL,Controlling consumer socket 0 for DMA368"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA368 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA369_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA369"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA369 Scheduler resources must not be read during halted state.'1'-> DMA369 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA369 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA369 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x2494++0x07
line.long 0x00 "DMPAC_HTS_DMA369_CONS0_CONTROL,Controlling consumer socket 0 for DMA369"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA369 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA370_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA370"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA370 Scheduler resources must not be read during halted state.'1'-> DMA370 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA370 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA370 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x24A8++0x07
line.long 0x00 "DMPAC_HTS_DMA370_CONS0_CONTROL,Controlling consumer socket 0 for DMA370"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA370 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "DMPAC_HTS_DMA371_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA371"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA371 Scheduler resources must not be read during halted state.'1'-> DMA371 Scheduler resources are readable during halted state" "0,1"
newline
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA371 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA371 Scheduler" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "SCH_EN,scheduler enable write '1' to enable scheduler" "0,1"
group.long 0x24BC++0x03
line.long 0x00 "DMPAC_HTS_DMA371_CONS0_CONTROL,Controlling consumer socket 0 for DMA371"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA371 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
group.long 0x2650++0x0B
line.long 0x00 "DMPAC_HTS_PIPE_DBG_CNTL,Pipeline Debug Control register is used by debug software to control pipeline debug behavior"
rbitfld.long 0x00 17.--19. "DEBUG_STATE,Current state of Debug activity" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "ABORT_DEBUG,'1' -> Abort Debug activity on debug enabled pipelines '0' no impact" "0,1"
newline
bitfld.long 0x00 6. "PIPE_DBG_DIS_6,'1' -> Pipeline6 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1"
bitfld.long 0x00 5. "PIPE_DBG_DIS_5,'1' -> Pipeline5 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1"
newline
bitfld.long 0x00 4. "PIPE_DBG_DIS_4,'1' -> Pipeline4 doesn't respond to debug events '0' Pipeline4 respond to debug events" "0,1"
bitfld.long 0x00 3. "PIPE_DBG_DIS_3,'1' -> Pipeline3 doesn't respond to debug events '0' Pipeline3 respond to debug events" "0,1"
newline
bitfld.long 0x00 2. "PIPE_DBG_DIS_2,'1' -> Pipeline2 doesn't respond to debug events '0' Pipeline2 respond to debug events" "0,1"
bitfld.long 0x00 1. "PIPE_DBG_DIS_1,'1' -> Pipeline1 doesn't respond to debug events '0' Pipeline1 respond to debug events" "0,1"
newline
bitfld.long 0x00 0. "PIPE_DBG_DIS_0,'1' -> Pipeline0 doesn't respond to debug events '0' Pipeline0 respond to debug events" "0,1"
line.long 0x04 "DMPAC_HTS_DBG_CAP,Debug Capability register is used by debug software to determine which optional debug modules are present and how many instances of each module exist"
bitfld.long 0x04 30. "DBG_INT_STEP_SUP,Indicates that debug execution control can determine if single step blocks or allows interrupts.b0 No step/interrupt control b1 Step interrupt control via DBG_INT_STEP_IN" "0,1"
bitfld.long 0x04 29. "DBG_WP_DATA_SUP,Indicates if the WP resources has corresponding data qualification.b0 - Not supported" "0,1"
newline
bitfld.long 0x04 28. "DBG_OWN_SUP,Indicates if the HWA supports an module ownership.v2.0 and above" "Not Supported,Ownership supported"
bitfld.long 0x04 27. "DBG_INDIRECT_SUP,Indicates if the HWA supports an indirect memory access port.v2.0 and above" "Not Supported,Indirect port supported"
newline
bitfld.long 0x04 26. "DBG_SWBP_SUP,Whether HWA Core supports SWBP or not.b0 - Not Supported" "0,1"
bitfld.long 0x04 25. "DBQ_RESET_SUP,Whether HWA Core reset is supported or not which does not affect debug logic.b0 - Not Supported" "0,1"
newline
bitfld.long 0x04 24. "SYS_EXE_REQ,Whether HWA Core Execution status and control is supported.b0 - Not Supported" "0,1"
bitfld.long 0x04 23. "TRIG_OUTPUT," "0,1"
newline
bitfld.long 0x04 22. "TRIG_INPUT," "0,1"
bitfld.long 0x04 20.--21. "TRIG_CHNS,Number of Trigger Channels Supported.b00 ------ No channels supported" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "NUM_CNTRS,The number of counter modules that exist.The registers supporting the counter modules must be implemented consecutively in the memory map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "NUM_WPS,The number of watchpoint modules that exist.The registers supporting the watchpoint modules must be implemented consecutively in the memory map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8.--11. "NUM_BPS,The number of breakpoint modules that exist.The registers supporting the breakpoint modules must be implemented consecutively in the memory map" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "REV_MAJ,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "REV_MIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DMPAC_HTS_DBG_CNTL,Debug Control register is used by debug software to control all of the basic debug functions"
bitfld.long 0x08 26. "DBG_RESET_OCC,Sticky status bit to reflect reset has been generated" "0,1"
bitfld.long 0x08 16.--19. "DBG_EMU0_CNTL,EMU0 output control.The cross trigger output control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 12. "DBG_HALT_EMU0,Execution halted due to trigger in on EMU0 input Set to '1' when halt due to EMU0 input completes Set to '0' when execution resumes" "0,1"
rbitfld.long 0x08 11. "DBG_HALT_USER,Execution halted due to register update of DBG_HALT Set to '1' when halt due to DBG_HALT update completes Set to '0' when execution resumes" "0,1"
newline
rbitfld.long 0x08 10. "DBG_HALT_STEP,Execution halted due to single step completion Set to '1' when the single step completes Set to '0' when execution resumes" "0,1"
rbitfld.long 0x08 7. "DBG_EXE_STAT,The execution status of the module Set to '1' when halted due to debug event Set to '0' when execution resumes" "0,1"
newline
bitfld.long 0x08 5. "DBG_EMU0_EN,EMU0 input trigger enable Writing '1' enables halting on the falling edge of the EMU0 input Writing '0' disables halts via EMU0 input" "0,1"
bitfld.long 0x08 2. "DBG_SINGLE_STEP_EN,Single Step Execution enable.When this bit is set the accelerator core shall be halted upon execution of a single instruction" "0,1"
newline
bitfld.long 0x08 1. "DBG_RESTART,Debug Restart Status bit.This bit is normally set when the DBG_HALT bit transitions from '1' to '0' when the natural execution state is entered.It is a sticky bit.It may also be set when a synchronous run causes the accelerator to leave.." "0,1"
bitfld.long 0x08 0. "DBG_HALT,Global debug run control.The bit will be read as being set upon entry to HALTED state due to halted state being entered because of SWBP HWBP HWWP EMU0 / 1 trigger or manual halt requested through this control" "0,1"
tree.end
tree.end
tree "DMPAC_SDE"
tree "DMPAC0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM"
base ad:0xF540000
rgroup.long 0x00++0x03
line.long 0x00 "DMPAC_SDE_CS_HIST_RAM_y,cs_hist_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00140000h + (y * 4h); where y = 0h to 7Fh"
hexmask.long.word 0x00 21.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--20. 1. "DATA,Data read from RAM"
rgroup.long 0x400++0x03
line.long 0x00 "DMPAC_SDE_SRB_S0_RAM_y,srb_s0_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00140400h + (y * 4h); where y = 0h to FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x800++0x03
line.long 0x00 "DMPAC_SDE_SRB_S1_RAM_y,srb_s1_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00140800h + (y * 4h); where y = 0h to FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x1000++0x03
line.long 0x00 "DMPAC_SDE_SRB_L0_RAM_Y,srb_l0_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00141000h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x1800++0x03
line.long 0x00 "DMPAC_SDE_SRB_L1_RAM_Y,srb_l1_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00141800h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x2000++0x03
line.long 0x00 "DMPAC_SDE_SRB_L2_RAM_Y,srb_l2_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00142000h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x2800++0x03
line.long 0x00 "DMPAC_SDE_SRB_L3_RAM_Y,srb_l3_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00142800h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x3000++0x03
line.long 0x00 "DMPAC_SDE_SRB_L4_RAM_Y,srb_l4_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00143000h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x3800++0x03
line.long 0x00 "DMPAC_SDE_SRB_L5_RAM_Y,srb_l5_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00143800h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x4000++0x03
line.long 0x00 "DMPAC_SDE_SRB_L6_RAM_Y,srb_l6_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00144000h + (y * 4h); where y = 0h to 1FFh"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,Data read from RAM"
rgroup.long 0x6000++0x03
line.long 0x00 "DMPAC_SDE_DRCG_FAST_LR_RAM_Y,drcg_fast_lr_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00146000h + (y * 4h); where y = 0h to 5FFh"
rgroup.long 0x8000++0x03
line.long 0x00 "DMPAC_SDE_LCC_OP0_RAM_y,lcc_op0_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00148000h + (y * 4h); where y = 0h to 9FFh"
rgroup.long 0xC000++0x03
line.long 0x00 "DMPAC_SDE_LCC_OP1_RAM_y,lcc_op1_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 0014C000h + (y * 4h); where y = 0h to 9FFh"
rgroup.long 0x10000++0x03
line.long 0x00 "DMPAC_SDE_LCC_OP2_RAM_y,lcc_op2_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00150000h + (y * 4h); where y = 0h to 9FFh"
rgroup.long 0x14000++0x03
line.long 0x00 "DMPAC_SDE_LCC_OP3_RAM_y,lcc_op3_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00154000h + (y * 4h); where y = 0h to 9FFh"
rgroup.long 0x18000++0x03
line.long 0x00 "DMPAC_SDE_LCC_OP4_RAM_y,lcc_op4_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00158000h + (y * 4h); where y = 0h to 9FFh"
rgroup.long 0x1C000++0x03
line.long 0x00 "DMPAC_SDE_DRCG_DISP_RAM_y,drcg_disp_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 0015C000h + (y * 4h); where y = 0h to BFFh"
hexmask.long.word 0x00 20.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--19. 1. "DATA,Data read from RAM"
rgroup.long 0x20000++0x03
line.long 0x00 "DMPAC_SDE_MF_LINE_RAM_Y,mf_line_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00160000h + (y * 4h); where y = 0h to FFFh"
bitfld.long 0x00 30.--31. "RSVD,Always read as 0.Writes have no effect" "0,1,2,3"
hexmask.long 0x00 0.--29. 1. "DATA,Data read from RAM"
rgroup.long 0x28000++0x03
line.long 0x00 "DMPAC_SDE_SCA_BRC_RAM_y,sca_brc_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00168000h + (y * 4h); where y = 0h to 1FFFh"
rgroup.long 0x30000++0x03
line.long 0x00 "DMPAC_SDE_SCA_BPCC_RAM_y,sca_bpcc_ram diagnostic read only port. vbusp will stall until RAM is available for read Offset = 00170000h + (y * 4h); where y = 0h to 27FFh"
tree.end
tree "DMPAC0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR"
base ad:0xF500000
rgroup.long 0x00++0x47
line.long 0x00 "DMPAC_SDE_PID,SDE"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme.Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family.If there is no level of software compatibility a new FUNC number and hence DMPAC_SDE_PID should be assigned"
bitfld.long 0x00 11.--15. "RTL,RTL Version.R as described in PDR with additional clarifications and definitions below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision.X as described in PDR with additional clarifications/definitions below" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device.Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision.Y as described in PDR with additional clarifications/definitions below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMPAC_SDE_CTRL,SDE control register contains fields that can be used to control DMPAC operation"
hexmask.long 0x04 4.--31. 1. "RSVD,always read as 0.Write has no effect"
bitfld.long 0x04 3. "RRSRCHEN,Enable reduced range search on pixels near right margin where the search range is less than the configured maximum disparity.Write a '1' to enable reduced range search" "0,1"
bitfld.long 0x04 2. "MEDFEN,Median filter enable.Write a '1' to enable median filter for post processing" "0,1"
bitfld.long 0x04 1. "SDEEN,SDE enable.Write a '1' to enable DMPAC stereo" "0,1"
rbitfld.long 0x04 0. "RSVD1,always read as 0.Write has no effect" "0,1"
line.long 0x08 "DMPAC_SDE_STATUS,SDE register contains fields that return the DMPAC stereo internal"
hexmask.long.tbyte 0x08 11.--31. 1. "RSVD,always read as 0.Write has no effect"
bitfld.long 0x08 10. "SDEIDLE,sdeidle=1 indicate SDE is idle" "0,1"
bitfld.long 0x08 8.--9. "LCCSTAT,LCC sub-moduleDMPAC_SDE_STATUS" "IDLE,ACTIVE,PAUSE,RSVD"
bitfld.long 0x08 6.--7. "SCASTAT,SCA sub-moduleDMPAC_SDE_STATUS" "IDLE,ACTIVE,PAUSE,RSVD"
bitfld.long 0x08 4.--5. "DRCGSTAT,DRCG sub-moduleDMPAC_SDE_STATUS" "IDLE,ACTIVE,PAUSE,RSVD"
newline
bitfld.long 0x08 2.--3. "MEDFCGSTAT,Median filter sub-moduleDMPAC_SDE_STATUS" "IDLE,ACTIVE,PAUSE,RSVD"
bitfld.long 0x08 0.--1. "DPACKSTAT,Disparity packing sub-moduleDMPAC_SDE_STATUS" "IDLE,ACTIVE,PAUSE,RSVD"
line.long 0x0C "DMPAC_SDE_IMGRES,SDE image resolution register contains fields that can be used to configure input image resolution"
hexmask.long.word 0x0C 23.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.byte 0x0C 16.--22. 1. "IWINC,Image width increment factor.Image width iw=128 + 16*iwinc pixels iwinc=0 1 ... 120"
hexmask.long.word 0x0C 6.--15. 1. "RSVD1,always read as 0.Write has no effect"
bitfld.long 0x0C 0.--5. "IHINC,Image height increment factor.Image height ih=64 + 16*ihinc pixels ihinc=0 1 ... 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMPAC_SDE_SRCHRNG,SDE search range register contains fields that can be used to configure disparity search range"
hexmask.long 0x10 3.--31. 1. "RSVD,always read as 0.Write has no effect"
bitfld.long 0x10 1.--2. "CFGDRANGE,Configure disparity search range in" "0,1,2,3"
bitfld.long 0x10 0. "CFGDMIN,Configure minimum disparity (minDisp) to be searched in pixels.0: minDisp=0 " "0,1"
line.long 0x14 "DMPAC_SDE_LRCHCK,SDE left-right consistence check register contains fields that can be used to configure left-right consistence check"
hexmask.long.tbyte 0x14 8.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.byte 0x14 0.--7. 1. "DIFFTHLD,Left-right consistence check threshold in pixels.Program diffThld >= maxDisp-minDisp will disable Left-right consistence check"
line.long 0x18 "DMPAC_SDE_TXTFLT,SDE texture based filtering control register contains fields that can be used to configure texture based filtering function"
hexmask.long.tbyte 0x18 9.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.byte 0x18 1.--8. 1. "TXTTHLD,Scaled texture threshold.Any pixel whose texture metric is lower than txtthld is considered to be low texture"
bitfld.long 0x18 0. "TXTFLTEN,Enable texture based filtering" "0,1"
line.long 0x1C "DMPAC_SDE_PNLTY,SDE cost penalty configuration register contains fields that can be used to configure cost penalty function"
hexmask.long.word 0x1C 23.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.byte 0x1C 16.--22. 1. "P1,SDE aggregation penalty P1.Optimization penalty constant for small disparity change"
hexmask.long.byte 0x1C 8.--14. 1. "RSVD1,always read as 0.Write has no effect"
hexmask.long.byte 0x1C 0.--7. 1. "P2,SDE aggregation penalty P2.Optimization penalty constant for large disparity change"
line.long 0x20 "DMPAC_SDE_CONFMAPG0,SDE confidence score mapping configuration register 0 specifies level 0 and 1 mapping threshold"
hexmask.long.word 0x20 23.--31. 1. "RSVD0,always read as 0.Write has no effect"
hexmask.long.byte 0x20 16.--22. 1. "CONFMAP_0,SDE confidence score mapping 0.Internal confidence score will map to level 0 (of 8 level output) if it is less than confmap_0"
hexmask.long.word 0x20 7.--15. 1. "RSVD1,always read as 0.Write has no effect"
hexmask.long.byte 0x20 0.--6. 1. "CONFMAP_1,SDE confidence score mapping 1.Internal confidence score will map to level 1 if it is less than confmap_1 but greater than or equal to confmap_0"
line.long 0x24 "DMPAC_SDE_CONFMAPG1,SDE confidence score mapping configuration register 1 specifies level 2 and 3 mapping threshold"
hexmask.long.word 0x24 23.--31. 1. "RSVD0,always read as 0.Write has no effect"
hexmask.long.byte 0x24 16.--22. 1. "CONFMAP_2,SDE confidence score mapping 2.Internal confidence score will map to level 2 if it is less than confmap_2 but greater than or equal to confmap_1"
hexmask.long.word 0x24 7.--15. 1. "RSVD1,always read as 0.Write has no effect"
hexmask.long.byte 0x24 0.--6. 1. "CONFMAP_3,SDE confidence score mapping 3.Internal confidence score will map to level 3 if it is less than confmap_3 but greater than or equal to confmap_2"
line.long 0x28 "DMPAC_SDE_CONFMAPG2,SDE confidence score mapping configuration register 2 specifies level 4 and 5 mapping threshold"
hexmask.long.word 0x28 23.--31. 1. "RSVD0,always read as 0.Write has no effect"
hexmask.long.byte 0x28 16.--22. 1. "CONFMAP_4,SDE confidence score mapping 4.Internal confidence score will map to level 4 if it is less than confmap_4 but greater than or equal to confmap_3"
hexmask.long.word 0x28 7.--15. 1. "RSVD1,always read as 0.Write has no effect"
hexmask.long.byte 0x28 0.--6. 1. "CONFMAP_5,SDE confidence score mapping 5.Internal confidence score will map to level 5 if it is less than confmap_5 but greater than or equal to confmap_4"
line.long 0x2C "DMPAC_SDE_CONFMAPG3,SDE confidence score mapping configuration register 3 specifies level 6 and 7 mapping threshold"
hexmask.long.word 0x2C 23.--31. 1. "RSVD0,always read as 0.Write has no effect"
hexmask.long.byte 0x2C 16.--22. 1. "CONFMAP_6,SDE confidence score mapping 6.Internal confidence score will map to level 6 if it is less than confmap_6 but greater than or equal to confmap_5"
hexmask.long.word 0x2C 0.--15. 1. "RSVD1,always read as 0.Write has no effect"
line.long 0x30 "DMPAC_SDE_BASEIMGADDR,SDE base image buffer start address register specifies the base image buffer start address in SL2"
hexmask.long.word 0x30 20.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.tbyte 0x30 0.--19. 1. "BASEAD,SL2 base image buffer start address (byte address aligned to 64 byte boundary basead[5:0] should be programmed as 0)"
line.long 0x34 "DMPAC_SDE_BASEIMGWD,SDE base image buffer width register specifies the SL2 base image buffer width (The height is fixed at 24 for growing window)"
hexmask.long.tbyte 0x34 12.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.word 0x34 0.--11. 1. "BWIDTH,SL2 base image buffer width in bytes.bwidth has to satisfy bwidth >= 1.5iw (image width) and is aligned to 64 byte boundaries (LSB 6 bits are always programmed as 0)"
line.long 0x38 "DMPAC_SDE_REFIMGADDR,SDE reference image buffer start address register specifies the reference image buffer start address in SL2"
hexmask.long.word 0x38 20.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.tbyte 0x38 0.--19. 1. "REFAD,SL2 reference image buffer start address (byte address aligned to 64 byte boundary refad[5:0] should be programmed as 0)"
line.long 0x3C "DMPAC_SDE_REFIMGWD,SDE reference image buffer width register specifies the SL2 reference image buffer width (The height is fixed at 24 for growing window)"
hexmask.long.tbyte 0x3C 12.--31. 1. "RSVD,always read as 0.Write has no effect"
hexmask.long.word 0x3C 0.--11. 1. "RWIDTH,SL2 reference image buffer width in bytes.rwidth has to satisfy rwidth >= 1.5*iw (image width) and is aligned to 64 byte boundaries (LSB 6 bits are always programmed as 0)"
line.long 0x40 "DMPAC_SDE_DISPBUFCFG,SDE disparity block buffer configuration register specifies the disparity output block buffer start address and number of buffers in SL2"
rbitfld.long 0x40 29.--31. "RSVD0,always read as 0.Write has no effect" "0,1,2,3,4,5,6,7"
bitfld.long 0x40 24.--28. "NUMDISPBUF_M1,number of SL2 disparity block buffers minus 1.For instance programming numdispbuf_m1 to 1 makes a ping-pong buffer (number of disparity buffers is 2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x40 20.--23. "RSVD1,always read as 0.Write has no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x40 0.--19. 1. "DISPBUFAD,SL2 disparity output block buffer start address (byte address aligned to 64 byte boundary dispbufad[5:0] should be programmed as 0)"
line.long 0x44 "DMPAC_SDE_IRCBUF,SDE image row cost buffer configuration register specifies the image row cost buffer start address in SL2"
hexmask.long.word 0x44 20.--31. 1. "RSVD1,always read as 0.Write has no effect"
hexmask.long.tbyte 0x44 0.--19. 1. "IRCBUFAD,SL2 image row cost buffer start address (byte address aligned to 64 byte boundary ircbufad[5:0] should be programmed as 0)"
group.long 0x50++0x07
line.long 0x00 "DMPAC_SDE_PSA_CTRL,Control register for calculating 32b CRC signature on stereo disparity output"
hexmask.long 0x00 1.--31. 1. "RSVD,Reserved"
bitfld.long 0x00 0. "PSA_EN_CFG,Enable calculating 32b CRC signature on 16b stereo disparity and confidence score output" "0,1"
line.long 0x04 "DMPAC_SDE_PSA_SIGNATURE,32b CRC signature calculated on stereo disparity output"
rgroup.long 0x60++0x03
line.long 0x00 "DMPAC_SDE_HIST_y,SDE Histogram registers stores the counter value of how many confidence scores (scaled to 7-bits) have fallen into each bin Offset = 00100060h + (y * 4h); where y = 0h to 7Fh"
hexmask.long.word 0x00 21.--31. 1. "RSVD,Always read as 0.Writes have no effect"
hexmask.long.tbyte 0x00 0.--20. 1. "BIN_STS,BIN accumulated counter value.Clear to 0 within a 128 cycle window after hts_sde_init is asserted"
tree.end
tree.end
tree "DMPAC_UTC_DRU"
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU"
base ad:0xF600000
rgroup.quad 0x00++0x0F
line.quad 0x00 "DMPAC_UTC_DRU_PID,Peripheral ID Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad 0x00 0.--31. 1. "REVISION,PID Revision"
line.quad 0x08 "DMPAC_UTC_DRU_CAPABILITIES,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions"
hexmask.quad.tbyte 0x08 47.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 43.--46. "SECTR,Maximum second TR function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 39.--42. "DFMT,Maximum data reformatting function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 35.--38. "ELTYPE,Maximum element type value that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 32.--34. "AMODE,The maximum AMODE that is supported.If AMODE is supported then DIR field must be supported for that AMODE" "0,1,2,3,4,5,6,7"
hexmask.quad.word 0x08 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features.This implementation has no configuration specific features"
newline
bitfld.quad 0x08 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1"
bitfld.quad 0x08 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1"
bitfld.quad 0x08 17. "EOL,EOL Field is supported" "0,1"
bitfld.quad 0x08 16. "TRSTATIC,STATIC Field is supported" "0,1"
bitfld.quad 0x08 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.quad 0x08 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.quad 0x08 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.quad 0x08 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.quad 0x08 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.quad 0x08 10. "TYPE10,Type 10 TR is supported" "0,1"
bitfld.quad 0x08 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.quad 0x08 8. "TYPE8,Type 8 TR is supported" "0,1"
newline
bitfld.quad 0x08 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.quad 0x08 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.quad 0x08 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.quad 0x08 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.quad 0x08 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.quad 0x08 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.quad 0x08 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.quad 0x08 0. "TYPE0,Type 0 TR is supported" "0,1"
tree.end
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE"
base ad:0xF6E0000
rgroup.quad 0x00++0x07
line.quad 0x00 "DMPAC_UTC_DRU_CAUSE_y,Error Register cause for channels 0 to 15 Offset = 002E0000h + (y * 8h); where y = 0h to 1h"
bitfld.quad 0x00 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1"
bitfld.quad 0x00 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1"
bitfld.quad 0x00 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1"
newline
bitfld.quad 0x00 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1"
bitfld.quad 0x00 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1"
bitfld.quad 0x00 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1"
newline
bitfld.quad 0x00 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1"
bitfld.quad 0x00 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1"
bitfld.quad 0x00 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1"
newline
bitfld.quad 0x00 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1"
bitfld.quad 0x00 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1"
bitfld.quad 0x00 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1"
newline
bitfld.quad 0x00 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1"
bitfld.quad 0x00 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1"
bitfld.quad 0x00 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1"
newline
bitfld.quad 0x00 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1"
bitfld.quad 0x00 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1"
bitfld.quad 0x00 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1"
newline
bitfld.quad 0x00 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1"
bitfld.quad 0x00 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 3. "R_ERR0,Masked error bit for Tx channel n" "0,1"
bitfld.quad 0x00 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1"
bitfld.quad 0x00 1. "T_ERR0,Masked error bit for Tx channel n" "0,1"
newline
bitfld.quad 0x00 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1"
tree.end
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG"
base ad:0xF680000
rgroup.quad 0x00++0x7F
line.quad 0x00 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD0_1_j,The first TR submission word"
hexmask.quad.word 0x00 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x00 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x00 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x08 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD2_3_j,The second TR submission word"
hexmask.quad.word 0x08 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x08 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x10 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD4_5_j,The third TR submission word"
hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x10 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x18 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD6_7_j,The fourth TR submission word"
hexmask.quad 0x18 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x18 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x20 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD8_9_j,The fifth TR submission word"
hexmask.quad 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x28 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD10_11_j,The sixth TR submission word"
hexmask.quad.word 0x28 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x30 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD12_13_j,The seventh TR submission word"
hexmask.quad 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x38 "DMPAC_UTC_DRU_ATOMIC_SUBMIT_CURR_TR_WORD14_15_j,The eight TR submission word"
hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
line.quad 0x40 "DMPAC_UTC_DRU_NEXT_TR_WORD0_1_j_k,The first TR submission word"
hexmask.quad.word 0x40 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x40 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x40 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x48 "DMPAC_UTC_DRU_NEXT_TR_WORD2_3_j_k,The second TR submission word"
hexmask.quad.word 0x48 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x48 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x50 "DMPAC_UTC_DRU_NEXT_TR_WORD4_5_j_k,The third TR submission word"
hexmask.quad.word 0x50 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x50 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x50 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x58 "DMPAC_UTC_DRU_NEXT_TR_WORD6_7_j_k,The fourth TR submission word"
hexmask.quad 0x58 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x58 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x60 "DMPAC_UTC_DRU_NEXT_TR_WORD8_9_j_k,The fifth TR submission word"
hexmask.quad 0x60 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x60 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x68 "DMPAC_UTC_DRU_NEXT_TR_WORD10_11_j_k,The sixth TR submission word"
hexmask.quad.word 0x68 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x68 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x70 "DMPAC_UTC_DRU_NEXT_TR_WORD12_13_j_k,The seventh TR submission word"
hexmask.quad 0x70 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x70 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x78 "DMPAC_UTC_DRU_NEXT_TR_WORD14_15_j_k,The eight TR submission word"
hexmask.quad.word 0x78 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x78 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x78 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x78 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
tree.end
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT"
base ad:0xF640000
group.quad 0x00++0x07
line.quad 0x00 "DMPAC_UTC_DRU_CFG_j,Channel Configuration Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,RESERVED"
bitfld.quad 0x00 31. "PAUSE_ON_ERR,Pause on Error.This field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.quad 0x00 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC.If it is 0 then the SUBMISSION registers must be written to submit it" "0,1"
rbitfld.quad 0x00 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC.The value of this is all zeroes" "0,1,2,3,4,5,6,7"
group.quad 0x20++0x07
line.quad 0x00 "DMPAC_UTC_DRU_CHOES0_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.quad 0x00 16.--63. 1. "RSVD,RESERVED"
hexmask.quad.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.quad 0x60++0x07
line.quad 0x00 "DMPAC_UTC_DRU_CHST_SCHED_j,Channel Static Scheduler Config Register"
bitfld.quad 0x00 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7"
tree.end
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT"
base ad:0xF660000
group.quad 0x00++0x1F
line.quad 0x00 "DMPAC_UTC_DRU_CHRT_CTL_j,The channel realtime control register contains real-time cotrol and status information for the DMA Channel"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 31. "ENABLE,This field enables or disables the channel.Disabling a channel halts operation on the channel after the current block transfer is completed" "channel is disabled,channel is enabled This field will be cleared.."
bitfld.quad 0x00 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down.This field will remain set after a channel teardown is complete" "0,1"
newline
bitfld.quad 0x00 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary.This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow" "0,1"
line.quad 0x08 "DMPAC_UTC_DRU_CHRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
hexmask.quad 0x08 3.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel.This will trigger LOCAL Event" "0,1"
bitfld.quad 0x08 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel.This will trigger Global Event 1" "0,1"
newline
bitfld.quad 0x08 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel.This will trigger Global Event 0" "0,1"
line.quad 0x10 "DMPAC_UTC_DRU_CHRT_STATUS_DET_j,The channel status details"
hexmask.quad 0x10 16.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x10 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue"
bitfld.quad 0x10 4.--7. "INFO,The info of the error that was received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x10 0.--3. "STATUS_TYPE,The type of error that was received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x18 "DMPAC_UTC_DRU_CHRT_STATUS_CNT_j,The channel count details"
hexmask.quad.word 0x18 48.--63. 1. "ICNT3,The last icnt3 given to the write queue"
hexmask.quad.word 0x18 32.--47. 1. "ICNT2,The last icnt2 given to the write queue"
hexmask.quad.word 0x18 16.--31. 1. "ICNT1,The last icnt1 given to the write queue"
newline
hexmask.quad.word 0x18 0.--15. 1. "ICNT0,The last icnt0 given to the write queue"
tree.end
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE"
base ad:0xF608000
group.quad 0x00++0x07
line.quad 0x00 "DMPAC_UTC_DRU_CFG_y,Configuration Register for Queue 0 Offset = 00208000h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x00 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands.This is only started when a queue exhausted its consecutive trans count"
hexmask.quad.byte 0x00 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands.This is the maximum number of commands that it can send"
bitfld.quad 0x00 8.--10. "QOS,This configures the QOS for QUEUE0.This should only be set for fixed priority queues and the lower queue should have the lower QoS" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 4.--7. "ORDERID,This configures the orderid for QUEUE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0.--2. "PRI,This configures the priority for QUEUE0.This will be the priority that will be presented on the External bus for all commands from this queue" "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x07
line.quad 0x00 "DMPAC_UTC_DRU_STATUS_y,Status Register for Queue 0 Offset = 00208040h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 36.--63. 1. "RSVD,Reserved"
hexmask.quad.word 0x00 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on"
tree.end
tree "DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET"
base ad:0xF604000
group.quad 0x00++0x07
line.quad 0x00 "DMPAC_UTC_DRU_SHARED_EVT_SET,DRU Shared Event Set Register"
hexmask.quad 0x00 1.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 0. "PROT_ERR,Set the Prot Error event" "0,1"
group.quad 0x40++0x07
line.quad 0x00 "DMPAC_UTC_DRU_COMP_EVT_SET0,DRU Completion Event Set Register"
bitfld.quad 0x00 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1"
bitfld.quad 0x00 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1"
bitfld.quad 0x00 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1"
bitfld.quad 0x00 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1"
bitfld.quad 0x00 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1"
bitfld.quad 0x00 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1"
bitfld.quad 0x00 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1"
bitfld.quad 0x00 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1"
group.quad 0x80++0x07
line.quad 0x00 "DMPAC_UTC_DRU_ERR_EVT_SET0,DRU Error Event Set Register"
bitfld.quad 0x00 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1"
bitfld.quad 0x00 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1"
bitfld.quad 0x00 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1"
bitfld.quad 0x00 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1"
bitfld.quad 0x00 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1"
bitfld.quad 0x00 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1"
bitfld.quad 0x00 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1"
bitfld.quad 0x00 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1"
bitfld.quad 0x00 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1"
bitfld.quad 0x00 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1"
bitfld.quad 0x00 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1"
bitfld.quad 0x00 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1"
bitfld.quad 0x00 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1"
bitfld.quad 0x00 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1"
bitfld.quad 0x00 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1"
bitfld.quad 0x00 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1"
bitfld.quad 0x00 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1"
bitfld.quad 0x00 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1"
bitfld.quad 0x00 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1"
bitfld.quad 0x00 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1"
bitfld.quad 0x00 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1"
bitfld.quad 0x00 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1"
bitfld.quad 0x00 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1"
bitfld.quad 0x00 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1"
bitfld.quad 0x00 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1"
bitfld.quad 0x00 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1"
bitfld.quad 0x00 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1"
bitfld.quad 0x00 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1"
bitfld.quad 0x00 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1"
group.quad 0xC0++0x07
line.quad 0x00 "DMPAC_UTC_DRU_LOCAL_EVT_SET0,DRU Local Event Set Register"
bitfld.quad 0x00 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1"
bitfld.quad 0x00 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1"
bitfld.quad 0x00 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1"
bitfld.quad 0x00 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1"
bitfld.quad 0x00 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1"
bitfld.quad 0x00 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1"
bitfld.quad 0x00 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1"
bitfld.quad 0x00 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1"
tree.end
tree.end
tree "DPHY_RX"
tree "DPHY_RX0_MMR_SLV_K3_DPHY_WRAP"
base ad:0x4581000
group.long 0x1000++0x03
line.long 0x00 "DPHY_RX_MMR_SLV_LANE,control and status"
rbitfld.long 0x00 31. "RXCLKACTIVEHSCLK,Receiver high speed clock active: Driven active when the receiver high speed clock is active" "0,1"
rbitfld.long 0x00 30. "CMN_READY,Common ready indication: Indicates the completion of the startup process of the common module" "0,1"
bitfld.long 0x00 26. "PSO_DISABLE,Disable power shut off: Disables the ability to switch off the analog switched power islands in" "0,1"
bitfld.long 0x00 24. "PSO_CMN,Disable power shut off: Power Shutoff signal for CMN" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "PSM_CLOCK_FREQ,PMA state machine clock frequency divider control: This signal specifies a divider value used to create an internal divided clock that is a function of the psm_clock clock"
newline
bitfld.long 0x00 9.--11. "IPCONFIG_CMN,This signal decides which clock" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "CLK_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 7. "CLK_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 6. "DATA_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 5. "DATA_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
newline
bitfld.long 0x00 4. "CLK_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 3. "CLK_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 2. "DATA_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 1. "DATA_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 0. "CLK_SWAPDPDN_CL_L,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
tree.end
tree "DPHY_RX1_MMR_SLV_K3_DPHY_WRAP"
base ad:0x4591000
group.long 0x1000++0x03
line.long 0x00 "DPHY_RX_MMR_SLV_LANE,control and status"
rbitfld.long 0x00 31. "RXCLKACTIVEHSCLK,Receiver high speed clock active: Driven active when the receiver high speed clock is active" "0,1"
rbitfld.long 0x00 30. "CMN_READY,Common ready indication: Indicates the completion of the startup process of the common module" "0,1"
bitfld.long 0x00 26. "PSO_DISABLE,Disable power shut off: Disables the ability to switch off the analog switched power islands in" "0,1"
bitfld.long 0x00 24. "PSO_CMN,Disable power shut off: Power Shutoff signal for CMN" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "PSM_CLOCK_FREQ,PMA state machine clock frequency divider control: This signal specifies a divider value used to create an internal divided clock that is a function of the psm_clock clock"
newline
bitfld.long 0x00 9.--11. "IPCONFIG_CMN,This signal decides which clock" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "CLK_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 7. "CLK_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 6. "DATA_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 5. "DATA_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
newline
bitfld.long 0x00 4. "CLK_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 3. "CLK_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 2. "DATA_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 1. "DATA_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
bitfld.long 0x00 0. "CLK_SWAPDPDN_CL_L,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "0,1"
tree.end
tree "DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX"
base ad:0x4580000
rgroup.long 0x0C++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_ANA_TBIT3,CMN_ANA_TBIT3"
group.long 0x14++0x3F
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_ANA_TBIT5,CMN_ANA_TBIT5"
hexmask.long.tbyte 0x00 8.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x00 0.--7. 1. "ANA_TBIT5,Analog Test register 5"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT0,CMN_DIG_TBIT0"
rbitfld.long 0x04 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 28. "O_RES_CAL_START_TM,res_cal_start in test mode" "0,1"
newline
bitfld.long 0x04 27. "O_RES_CAL_START_TM_SEL,res_cal_start select from test_mode" "0,1"
newline
bitfld.long 0x04 26. "O_RES_COMP_OUT_POL_INV_TM,Invert polarity for resistor calib comparator output" "0,1"
newline
bitfld.long 0x04 22.--25. "O_RES_TX_OFFSET_TEST_LOW_TM,o_res_tx_offset_test_low_TM - Res calib manipulation code for res calib code low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 21. "O_RES_TX_OFFSET_LOW_DEC_TM,o_res_tx_offset_low_dec_TM asserted - Perform increment manipulation on res calib code if o_res_tx_offset_low_TM_sel is asserted" "0,1"
newline
bitfld.long 0x04 20. "O_RES_TX_OFFSET_LOW_TM_SEL,o_res_tx_offset_low_TM_sel asserted - Enable offset manipulation for res calib code low" "0,1"
newline
bitfld.long 0x04 16.--19. "O_RES_TX_OFFSET_TEST_HIGH_TM,o_res_tx_offset_test_high_TM - Res calib manipulation code for res calib code high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 15. "O_RES_TX_OFFSET_HIGH_DEC_TM,o_res_tx_offset_high_dec_TM asserted - Perform increment manipulation on res calib code if o_res_tx_offset_high_TM_sel is asserted" "0,1"
newline
bitfld.long 0x04 14. "O_RES_TX_OFFSET_HIGH_TM_SEL,o_res_tx_offset_high_TM_sel asserted - Enable offset manipulation for res calib code high" "0,1"
newline
bitfld.long 0x04 10.--13. "O_RES_CALIB_DECISION_WAIT_TM,res_calib decision wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 6.--9. "O_RES_CALIB_INIT_WAIT_TM,res_calib initial wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 5. "O_RES_CALIB_RSTB_TM,w_res_calib_rstb value in testmode" "0,1"
newline
bitfld.long 0x04 4. "O_RES_CALIB_RSTB_TM_SEL,w_res_calib_rstb select from test_mode" "0,1"
newline
rbitfld.long 0x04 0.--3. "UNUSED2,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT1,CMN_DIG_TBIT1"
bitfld.long 0x08 31. "O_ATB_EN,ATB probing enabled" "0,1"
newline
bitfld.long 0x08 30. "O_ATB_SRC,Select IO for atb probing" "0,1"
newline
hexmask.long.word 0x08 17.--29. 1. "BF_29_17,"
newline
bitfld.long 0x08 16. "O_ANA_PLL_ATB_CP_CUR_SEL,o_ana_pll_atb_cp_cur_sel" "0,1"
newline
bitfld.long 0x08 15. "O_ANA_PLL_ATBH_GM_CUR_SEL,o_ana_pll_atbh_gm_cur_sel" "0,1"
newline
rbitfld.long 0x08 10.--14. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 9. "O_ANA_BG_PD_TM,o_ana_bg_pd value in testmode" "0,1"
newline
bitfld.long 0x08 8. "O_ANA_BG_PD_TM_SEL,o_ana_bg_pd select from test_mode" "0,1"
newline
bitfld.long 0x08 7. "O_ANA_RES_CALIB_PD_TM,o_ana_res_calib_pd value in testmode" "0,1"
newline
bitfld.long 0x08 6. "O_ANA_RES_CALIB_PD_TM_SEL,o_ana_res_calib_pd select from test_mode" "0,1"
newline
bitfld.long 0x08 1.--5. "O_ANA_RES_CALIB_CODE_TM,o_ana_res_calib_code value in test_mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 0. "O_ANA_RES_CALIB_CODE_TM_SEL,o_ana_res_calib_code select from test_mode" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2"
hexmask.long.tbyte 0x0C 11.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x0C 10. "O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1"
newline
bitfld.long 0x0C 9. "O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1"
newline
hexmask.long.byte 0x0C 1.--8. 1. "O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled [in us]"
newline
bitfld.long 0x0C 0. "O_CMN_SSM_EN,Enable CMN startup state machine" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT3,CMN_DIG_TBIT3"
hexmask.long.byte 0x10 24.--31. 1. "O_PLL_WAIT_PLL_ACCINV,Wait time in pll_accinv [in us]"
newline
hexmask.long.byte 0x10 16.--23. 1. "O_PLL_WAIT_PLL_BIAS,Wait time in pll_bias [in us]"
newline
hexmask.long.byte 0x10 8.--15. 1. "O_PLL_WAIT_PLL_EN_DEL,Wait time in pll_en_del [in us]"
newline
hexmask.long.byte 0x10 0.--7. 1. "O_PLL_WAIT_PLL_EN,Wait time in PLL en [in us]"
line.long 0x14 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT4,CMN_DIG_TBIT4"
rbitfld.long 0x14 28.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 16.--27. 1. "O_PLL_WAIT_PLL_LOCK_DET_WAIT,Wait time in pll_lock_det_wait [in us]"
newline
hexmask.long.byte 0x14 8.--15. 1. "O_PLL_WAIT_PLL_RST_DEASSERT_2,Wait time in pll_rst_deassert_2ndset [in us]"
newline
hexmask.long.byte 0x14 0.--7. 1. "O_PLL_WAIT_PLL_RST_DEASSERT,Wait time in pll_rst_deassert [in us]"
line.long 0x18 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT5,"
bitfld.long 0x18 30.--31. "O_CMN_TX_READY_TM_SEL,ATB probing enabled" "0,1,2,3"
newline
bitfld.long 0x18 29. "O_PLL_PROCEED_WITH_LOCK_FAIL_TM,o_ana_pll_atb_cp_cur_sel" "0,1"
newline
bitfld.long 0x18 28. "O_PLL_LOCKED_TM,Forced value of pll_locked going to fsm = 1" "0,1"
newline
bitfld.long 0x18 27. "O_PLL_LOCKED_TM_SEL,pll_locked going to fsm forced from test registers" "0,1"
newline
bitfld.long 0x18 26. "O_PLL_LOCK_DET_EN_TM,Forced value of pll_lock_det_en = 1" "0,1"
newline
bitfld.long 0x18 25. "O_PLL_LOCK_DET_EN_TM_SEL,pll_lock_det_en forced from test registers" "0,1"
newline
hexmask.long.byte 0x18 18.--24. 1. "UNUSED,RESERVED"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "O_PLL_WAIT_PLL_LOCK_TIMEOUT,Wait time for pll_lock_timeout [in us]"
line.long 0x1C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT6,CMN_DIG_TBIT6"
hexmask.long.word 0x1C 16.--31. 1. "O_LOCKDET_REFCNT_IDLE_VALUE,refcnt idle value for PLL lock detect module"
newline
hexmask.long.word 0x1C 0.--15. 1. "O_LOCKDET_REFCNT_START_VALUE,refcnt start value for PLL lock detect module"
line.long 0x20 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT7,CMN_DIG_TBIT7"
hexmask.long.word 0x20 16.--31. 1. "O_LOCKDET_PLLCNT_LOCK_THR_VALUE,pllcnt lock threshold value for PLL lock detect module"
newline
hexmask.long.word 0x20 0.--15. 1. "O_LOCKDET_PLLCNT_START_VALUE,pllcnt start value for PLL lock detect module"
line.long 0x24 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT8,CMN_DIG_TBIT8"
hexmask.long.byte 0x24 24.--31. 1. "O_ANA_PLL_VRESET_VCTRL_TUNE,unconnected intended for vreset_vctrl[CP output] progrmmability"
newline
hexmask.long.byte 0x24 16.--23. 1. "O_ANA_PLL_VRESET_VCO_BIAS_TUNE,Programmability for vco bias[gmbyc] initial voltage"
newline
hexmask.long.byte 0x24 8.--15. 1. "O_ANA_PLL_GM_TUNE,gm tune value for PLL"
newline
hexmask.long.byte 0x24 0.--7. 1. "O_ANA_PLL_CP_TUNE,Charge Pump Tune value for PLL"
line.long 0x28 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT9,CMN_DIG_TBIT9"
hexmask.long.byte 0x28 24.--31. 1. "O_ANA_PLL_VREF_VCO_BIAS_TUNE,Tuning Control for reference vco bias in PLL"
newline
hexmask.long.byte 0x28 16.--23. 1. "O_ANA_PLL_VCO_BIAS_TUNE,Tuning Control for PLL vco bias"
newline
hexmask.long.byte 0x28 8.--15. 1. "O_ANA_PLL_GMBYC_CAP_TUNE,gmbyc tune value for PLL"
newline
hexmask.long.byte 0x28 0.--7. 1. "O_ANA_PLL_LOOP_FILTER_TUNE,Tuning Control for loop filter"
line.long 0x2C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10"
rbitfld.long 0x2C 28.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x2C 20.--27. 1. "O_ANA_PLL_BYTECLK_DIV,Byteclk divider value"
newline
hexmask.long.word 0x2C 10.--19. 1. "O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider"
newline
hexmask.long.word 0x2C 0.--9. 1. "O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider"
line.long 0x30 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT11,CMN_DIG_TBIT11"
hexmask.long.word 0x30 16.--31. 1. "O_ANA_PLL_CYA,Drives pllda_cya going to ANA"
newline
rbitfld.long 0x30 13.--15. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 12. "O_ANA_PLL_PFD_EN_1U_DEL_TM_SEL,Testmode signal for selecting 1us delayed for pll_pfd_reset_n" "0,1"
newline
bitfld.long 0x30 11. "O_ANA_PLL_VRESET_VCO_BIAS_SEL,vreset_vctrl_gmbyc is set inside the pll_vreset_gen" "0,1"
newline
bitfld.long 0x30 10. "O_ANA_PLL_VRESET_VCTRL_SEL,vreset_vctrl is set to ground inside the pll_vreset_gen" "0,1"
newline
bitfld.long 0x30 9. "O_ANA_PLL_SEL_FBCLK_GM_PWM,Enable mode to use feedback clock as the PWM control input for the gm stage" "0,1"
newline
bitfld.long 0x30 8. "O_ANA_PLL_OP_BY2_BYPASS,Mode to bypass the divide by 2 in the PLL output which generates clk_bit and clk_bitb" "0,1"
newline
bitfld.long 0x30 7. "O_ANA_PLL_BYPASS,Bypass PLL and pass refclk as output" "0,1"
newline
bitfld.long 0x30 6. "O_ANA_PLL_FBDIV_CLKINBY2_EN,Enable division by 2 on the feedback divider input clock" "0,1"
newline
bitfld.long 0x30 5. "O_ANA_PLL_DSM_CLK_EN,Enable for dsm clock output to digital" "0,1"
newline
bitfld.long 0x30 4. "O_ANA_PLL_GM_PWM_EN,Enable PWM control of the gm else it will operate in the continuous mode" "0,1"
newline
bitfld.long 0x30 3. "O_ANA_PLL_OP_DIV_CLK_EN,Enable for op divider clock output to digital" "0,1"
newline
bitfld.long 0x30 2. "O_ANA_PLL_IP_DIV_CLK_EN,Enable for ip divider output to digital" "0,1"
newline
bitfld.long 0x30 1. "O_ANA_PLL_REF_CLK_EN,enables refclk to PLL" "0,1"
newline
bitfld.long 0x30 0. "O_ANA_PLL_FB_DIV_CLK_EN,Enable for feedback clock output to digital" "0,1"
line.long 0x34 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT12,CMN_DIG_TBIT12"
bitfld.long 0x34 31. "O_ANA_PLL_VRESET_GEN_EN_TM,Forced value of pll_vreset_gen_en = 1" "0,1"
newline
bitfld.long 0x34 30. "O_ANA_PLL_VRESET_GEN_EN_TM_SEL,pll_vreset_gen_en forced from test registers" "0,1"
newline
bitfld.long 0x34 29. "O_ANA_PLL_PFD_EN_TM,Forced value of pllda_pfd_en = 1" "0,1"
newline
bitfld.long 0x34 28. "O_ANA_PLL_PFD_EN_TM_SEL,pllda_pfd_en forced from test registers" "0,1"
newline
bitfld.long 0x34 27. "O_ANA_PLL_LOOP_FILTER_RESET_N_TM,Forced value of pll_loop_filter_reset_n = 1" "0,1"
newline
bitfld.long 0x34 26. "O_ANA_PLL_LOOP_FILTER_RESET_N_TM_SEL,pll_loop_filter_reset_n is drivne from test registers" "0,1"
newline
bitfld.long 0x34 25. "O_ANA_PLL_GM_RESET_N_TM,Forced value of pll_gm_reset_n = 1" "0,1"
newline
bitfld.long 0x34 24. "O_ANA_PLL_GM_RESET_N_TM_SEL,pll_gm_reset_n is drivne from test registers" "0,1"
newline
bitfld.long 0x34 23. "O_ANA_PLL_GMBYC_CAP_RESET_N_TM,Forced value of pll_gmbyc_cap_reset_n = 1" "0,1"
newline
bitfld.long 0x34 22. "O_ANA_PLL_GMBYC_CAP_RESET_N_TM_SEL,pll_gmbyc_cap_reset_n is drivne from test registers" "0,1"
newline
bitfld.long 0x34 21. "O_ANA_PLL_CP_RESET_N_TM,Forced value of pll_cp_reset_n = 1" "0,1"
newline
bitfld.long 0x34 20. "O_ANA_PLL_CP_RESET_N_TM_SEL,pll_cp_reset_n is drivne from test registers" "0,1"
newline
bitfld.long 0x34 19. "O_ANA_PLL_ACCINV_EN_TM,Forced value of pllda_accinv = 1" "0,1"
newline
bitfld.long 0x34 18. "O_ANA_PLL_ACCINV_EN_TM_SEL,pllda_accinv forced from test registers" "0,1"
newline
bitfld.long 0x34 17. "O_ANA_PLL_BIAS_EN_TM,Forced value of pllda_bias_en = 1" "0,1"
newline
bitfld.long 0x34 16. "O_ANA_PLL_BIAS_EN_TM_SEL,pllda_bias_en forced from test registers" "0,1"
newline
bitfld.long 0x34 15. "O_ANA_PLLDA_EN_DEL_TM,Forced value of pllda_en_del = 1" "0,1"
newline
bitfld.long 0x34 14. "O_ANA_PLLDA_EN_DEL_TM_SEL,pllda_en_del forced from test registers" "0,1"
newline
bitfld.long 0x34 13. "O_ANA_PLLDA_EN_TM,Forced value of pllda_en_del = 1" "0,1"
newline
bitfld.long 0x34 12. "O_ANA_PLLDA_EN_TM_SEL,pllda_en_del forced from test registers" "0,1"
newline
bitfld.long 0x34 11. "O_ANA_OP_BY2_DIV_RESET_N_TM,Forced valu of pllda_op_by2_div_reset_n = 1" "0,1"
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bitfld.long 0x34 10. "O_ANA_OP_BY2_DIV_RESET_N_TM_SEL,pllda_op_by2_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 9. "O_ANA_OP_DIV_RESET_N_TM,Forced value of pllda_op_div_reset_n = 1" "0,1"
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bitfld.long 0x34 8. "O_ANA_OP_DIV_RESET_N_TM_SEL,pllda_op_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 7. "O_ANA_IP_DIV_RESET_N_TM,Forced value of pllda_ip_div_reset_n = 1" "0,1"
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bitfld.long 0x34 6. "O_ANA_IP_DIV_RESET_N_TM_SEL,pllda_ip_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 5. "O_ANA_FB_DIV_RESET_N_TM,Forced value of pllda_fb_div_reset_n = 1" "0,1"
newline
bitfld.long 0x34 4. "O_ANA_FB_DIV_RESET_N_TM_SEL,pllda_fb_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 3. "O_ANA_GM_PWM_DIV_RESET_N_TM,Forced value of pllda_gm_pwm_div_reset_n = 1" "0,1"
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bitfld.long 0x34 2. "O_ANA_GM_PWM_DIV_RESET_N_TM_SEL,pllda_gm_pwm_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 1. "O_ANA_BYTECLK_DIV_RESET_N_TM,Forced value of pllda_byteclk_div_reset_n = 1" "0,1"
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bitfld.long 0x34 0. "O_ANA_BYTECLK_DIV_RESET_N_TM_SEL,pllda_byteclk_div_reset_n forced from test registers" "0,1"
line.long 0x38 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13"
hexmask.long.word 0x38 22.--31. 1. "O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low"
newline
bitfld.long 0x38 21. "O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1"
newline
hexmask.long.word 0x38 11.--20. 1. "O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high"
newline
bitfld.long 0x38 10. "O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1"
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hexmask.long.word 0x38 0.--9. 1. "UNUSED,RESERVED"
line.long 0x3C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14"
hexmask.long.tbyte 0x3C 13.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x3C 7.--12. "O_ANA_PLL_OP_DIV_TM,forced value for op_div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x3C 6. "O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1"
newline
bitfld.long 0x3C 1.--5. "O_ANA_PLL_IP_DIV_TM,forced value for ip_div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x3C 0. "O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1"
group.long 0x68++0x23
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT20,CMN_DIG_TBIT20"
hexmask.long.word 0x00 20.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x00 4.--19. 1. "O_CMSMT_REF_CLK_TMR_VALUE,Number of refclk cycles required for clock measurement"
newline
bitfld.long 0x00 1.--3. "BF_3_1," "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "O_CMSMT_MEASUREMENT_RUN,Enables clock measurement" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT21,CMN_DIG_TBIT21"
hexmask.long 0x04 7.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 6. "O_CMNDA_HSRX_BIST_CLK_SERSYNTH_SWAPDPDN,Enables swapping DP-DN lines for clock bist" "0,1"
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bitfld.long 0x04 5. "O_CMNDA_HSRX_BIST_DATA_SERSYNTH_SWAPDPDN,Enables swapping DP-DN lines for data bist" "0,1"
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bitfld.long 0x04 4. "O_CMNDA_RX_BIST_EN_DEL_TM,forced value of cmnda_rx_bist_en_del = 1" "0,1"
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bitfld.long 0x04 3. "O_CMNDA_RX_BIST_EN_DEL_TM_SEL,cmnda_rx_bist_en_del driven from test registers" "0,1"
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bitfld.long 0x04 2. "O_CMNDA_RX_BIST_EN_TM,forced value of cmnda_rx_bist_en = 1" "0,1"
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bitfld.long 0x04 1. "O_CMNDA_RX_BIST_EN_TM_SEL,cmnda_rx_bist_en driven from test registers" "0,1"
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bitfld.long 0x04 0. "O_RX_DIG_BIST_EN,BIST enable for digital" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT22,BIST_CONFIG_REG1"
bitfld.long 0x08 31. "TM_SKEW_CAL_SYNC_PKT_SEL,To send 'FF as Skew calibration sync packet" "0,1"
newline
hexmask.long.byte 0x08 23.--30. 1. "TM_SKEW_CAL_SYNC_PKT,desired skew calibration test sync packet"
newline
bitfld.long 0x08 22. "TM_HS_SYNC_PKT_SEL,To send 'B8 as HS sync packet" "0,1"
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hexmask.long.byte 0x08 14.--21. 1. "TM_HS_SYNC_PKT,desired HS test sync packet"
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hexmask.long.byte 0x08 7.--13. 1. "BIST_LENGTH_OF_DESKEW,Length of deskew sequence In terms of us By default 13us of deskew sequence will be transmitted"
newline
bitfld.long 0x08 5.--6. "BIST_SEND_CONFIG,Option of configuring what to send in BIST mose To send both deskew and HS data" "0,1,2,3"
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bitfld.long 0x08 1.--4. "BIST_MODE_ENTRY_WAIT_TIME,Once after giving bist_en signal to pattern generator after these many number of BYTE clcok cycles pattern generation will start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0. "BIST_CONTROLLER_EN,Enable BIST controller" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT23,BIST_CONFIG_REG2"
hexmask.long.byte 0x0C 24.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 23. "TM_TX_DATA_HS_SEL,sends single test byte to sersynth which is in <" "0,1"
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hexmask.long.byte 0x0C 15.--22. 1. "TM_TX_DATA_HS,Desired clock patetrn that can be sent using clk_sersynth"
newline
bitfld.long 0x0C 14. "BIST_TM_BAND_CTRL_SEL,To take the default band control settigns by the design" "0,1"
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bitfld.long 0x0C 9.--13. "BIST_TM_BAND_CTRL,Test mode band control setting to be done for BIST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 8. "TM_SKEW_CAL_PATTERN_SEL,To send 'AA as skew calibration pattern" "0,1"
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hexmask.long.byte 0x0C 0.--7. 1. "TM_SKEW_CAL_PATTERN,desired skew calibration test sequence"
line.long 0x10 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT24,BIST_CONFIG_REG3"
hexmask.long.byte 0x10 24.--31. 1. "BIST_FRM_IDLE_TIME,BIST_FRM_IDLE time is time between the frames"
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hexmask.long.byte 0x10 16.--23. 1. "BIST_PKT_NUM,BIST_PAK_NUM is number of packets that are to be transmitted per frame"
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bitfld.long 0x10 15. "BIST_INF_MODE,run infinite BIST mode" "0,1"
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hexmask.long.byte 0x10 7.--14. 1. "BIST_FRM_NUM,BIST_FRM_NUM is number of frames to be transmitted"
newline
bitfld.long 0x10 6. "BIST_CLEAR,clear the bist" "0,1"
newline
bitfld.long 0x10 4.--5. "BIST_PRBS,BIST PRBS MODE 9" "0,1,2,3"
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bitfld.long 0x10 1.--3. "BIST_TEST_MODE,PRBS mode" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 0. "UNUSED_0,RESERVED" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT25,BIST_CONFIG_REG4"
hexmask.long.tbyte 0x14 12.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x14 0.--11. 1. "BIST_RUN_LENGTH,BIST_RUN_LENGTH"
line.long 0x18 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT26,BIST_CONFIG_REG5"
hexmask.long.tbyte 0x18 8.--31. 1. "UNUSED_31_8,RESERVED"
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hexmask.long.byte 0x18 0.--7. 1. "BIST_IDLE_TIME,BIST_IDLE_TIME"
line.long 0x1C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT27,BIST_CONFIG_REG6"
hexmask.long.byte 0x1C 24.--31. 1. "BIST_PKT4,BIST_TEST_PAT4"
newline
hexmask.long.byte 0x1C 16.--23. 1. "BIST_PKT3,BIST_TEST_PAT3"
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hexmask.long.byte 0x1C 8.--15. 1. "BIST_PKT2,BIST_TEST_PAT2"
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hexmask.long.byte 0x1C 0.--7. 1. "BIST_PKT1,BIST_TEST_PAT1"
line.long 0x20 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT28,BIST_CONFIG_REG7"
hexmask.long.byte 0x20 24.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x20 23. "BIST_TM_CLOCK_LP_DP_SEL,Test mode selection bit to force clcok LP DP buffer to value from design" "0,1"
newline
bitfld.long 0x20 22. "BIST_TM_CLOCK_LP_DP_VAL,Test mode clock LP DP buffer value is 0" "0,1"
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bitfld.long 0x20 21. "BIST_TM_CLOCK_LP_DN_SEL,Test mode selection bit to force clcok LP DN buffer to value from design" "0,1"
newline
bitfld.long 0x20 20. "BIST_TM_CLOCK_LP_DN_VAL,Test mode clock LP DN buffer value is 0" "0,1"
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bitfld.long 0x20 19. "BIST_TM_DATA_LP_DP_SEL,Test mode selection bit to force data LP DP buffer to value from design" "0,1"
newline
bitfld.long 0x20 18. "BIST_TM_DATA_LP_DP_VAL,Test mode data LP DP buffer value is 0" "0,1"
newline
bitfld.long 0x20 17. "BIST_TM_DATA_LP_DN_SEL,Test mode selection bit to force data LP DN buffer to value from design" "0,1"
newline
bitfld.long 0x20 16. "BIST_TM_DATA_LP_DN_VAL,Test mode data LP DN buffer value is 0" "0,1"
newline
rbitfld.long 0x20 14.--15. "UNUSED_INT,RESERVED" "0,1,2,3"
newline
bitfld.long 0x20 13. "BIST_LFSR_FREEZE,Reset LFSR contents after every packet or frame" "0,1"
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hexmask.long.word 0x20 1.--12. 1. "BIST_ERR_INJ_POINT,BIST_ERR_INJECT_POINT is where to inject the error in the packet"
newline
bitfld.long 0x20 0. "BIST_ERR_INJ_EN,Inject error in the BIST during the packet" "0,1"
group.long 0x94++0x23
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT31,CMN_DIG_TBIT31"
hexmask.long.byte 0x00 24.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x00 16.--23. 1. "O_RX_SSM_LDO_EN_REF_TMR,Wait time before enabling oscialltor calibration"
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hexmask.long.byte 0x00 8.--15. 1. "O_RX_SSM_LDO_EN_DEL_TMR,wait time before enabling ldo_en_ref"
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hexmask.long.byte 0x00 0.--7. 1. "O_RX_SSM_LDO_EN_TMR,Wait time between ldo_en and ldo_en_del"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT32,CMN_DIG_TBIT32"
hexmask.long.word 0x04 16.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x04 8.--15. 1. "O_RX_SSM_ANA_BIST_ISO_DIS_TMR,Wait time between Bist_en_del and disabling isolation"
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hexmask.long.byte 0x04 0.--7. 1. "O_RX_SSM_ANA_BIST_EN_DEL_TMR,Wait time between Bist_en and bist_en_Del"
line.long 0x08 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT33,CMN_DIG_TBIT33"
bitfld.long 0x08 29.--31. "O_RX_OSC_CAL_TIMER_SCALE_SEL,Timer scale value for vco_count_window" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x08 26.--28. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 14.--25. 1. "O_RX_REFCLK_TIMER_ITER_VALUE_TM,Wait time required before enabling vco count window during iteration in test mode"
newline
bitfld.long 0x08 13. "O_RX_REFCLK_TIMER_ITER_VALUE_TM_SEL,refclk_timer_iter value driven from test register" "0,1"
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hexmask.long.word 0x08 1.--12. 1. "O_RX_REFCLK_TIMER_INIT_VALUE_TM,Wait time required before enabling vco count window in initial phase in test mode"
newline
bitfld.long 0x08 0. "O_RX_REFCLK_TIMER_INIT_VALUE_TM_SEL,refclk_timer_init value driven from test register" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT34,CMN_DIG_TBIT34"
rbitfld.long 0x0C 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x0C 14.--25. 1. "O_RX_OSC_EN_DEL_TMR_VALUE_TM,Wait time between osc_en and osc_en_del in Test mode"
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bitfld.long 0x0C 13. "O_RX_OSC_EN_DEL_TMR_VALUE_TM_SEL,osc_en_del_tmr driven from test register" "0,1"
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hexmask.long.word 0x0C 1.--12. 1. "O_RX_REFCLK_TIMER_START_VALUE_TM,No of refclk cycles required for single vco count window in test mode"
newline
bitfld.long 0x0C 0. "O_RX_REFCLK_TIMER_START_VALUE_TM_SEL,refclk_timer_start_value driven from test mode" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT35,CMN_DIG_TBIT35"
hexmask.long.byte 0x10 24.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.word 0x10 12.--23. 1. "O_RX_PLLCNT_COUNT_START_VALUE_2,No of PLL clock cycles expected in 25G mode"
newline
hexmask.long.word 0x10 0.--11. 1. "O_RX_PLLCNT_COUNT_START_VALUE_1,No of PLL clock cycles expected in 15G mode"
line.long 0x14 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT36,CMN_DIG_TBIT36"
hexmask.long.word 0x14 20.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x14 13.--19. 1. "O_RX_TM_VCOCAL_OVRD_VALUE,Vco calcode Test mode value"
newline
bitfld.long 0x14 12. "O_RX_TM_VCO_CAL_OVERRIDE_EN,Enables test mode overwrite for vco cal code" "0,1"
newline
hexmask.long.byte 0x14 5.--11. 1. "O_RX_OSC_CAL_CODE_START,Starting code for vco calibration"
newline
bitfld.long 0x14 2.--4. "O_RX_OSC_CAL_CODE_INIT_STEP,Step size for incrmenting vco cal code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 1. "O_RX_TM_SEL_1P5G_MODE,Select 1p5g mode oscillator clock" "0,1"
newline
bitfld.long 0x14 0. "O_RX_TM_OSC_CAL_EN,Test mode overwrite for crude osc calibration enable" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT37,"
hexmask.long.tbyte 0x18 15.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x18 14. "O_CMNDA_HSRX_OSC_CALIB_SEL_TM,forced value of hsrx_osc_calib_sel = 1" "0,1"
newline
bitfld.long 0x18 13. "O_CMNDA_HSRX_OSC_CALIB_SEL_TM_SEL,hsrx_osc_calib_sel driven from test registers" "0,1"
newline
bitfld.long 0x18 12. "O_CMNDA_RX_OSC_DIV_RESET_N_TM,forced value of rx_osc_div_reset_n = 1" "0,1"
newline
bitfld.long 0x18 11. "O_CMNDA_RX_OSC_DIV_RESET_N_TM_SEL,rx_osc_div_reset_n driven from test registers" "0,1"
newline
bitfld.long 0x18 10. "O_CMNDA_RX_OSC_EN_DEL_TM,forced value of rx_osc_en_del = 1" "0,1"
newline
bitfld.long 0x18 9. "O_CMNDA_RX_OSC_EN_DEL_TM_SEL,rx_osc_en_del driven from test registers" "0,1"
newline
bitfld.long 0x18 8. "O_CMNDA_RX_OSC_EN_TM,forced value of rx_osc_en = 1" "0,1"
newline
bitfld.long 0x18 7. "O_CMNDA_RX_OSC_EN_TM_SEL,rx_osc_en driven from test registers" "0,1"
newline
bitfld.long 0x18 6. "O_CMNDA_RX_LDO_BYPASS_TM,Bypass LDO in test mode" "0,1"
newline
bitfld.long 0x18 5. "O_CMNDA_RX_LDO_REF_EN_TM,forced value of rx_ldo_ref_en = 1" "0,1"
newline
bitfld.long 0x18 4. "O_CMNDA_RX_LDO_REF_EN_TM_SEL,rx_ldo_ref_en driven from test registers" "0,1"
newline
bitfld.long 0x18 3. "O_CMNDA_RX_LDO_EN_DEL_TM,forced value of rx_ldo_en_del = 1" "0,1"
newline
bitfld.long 0x18 2. "O_CMNDA_RX_LDO_EN_DEL_TM_SEL,rx_ldo_en_del driven from test registers" "0,1"
newline
bitfld.long 0x18 1. "O_CMNDA_RX_LDO_EN_TM,forced value of rx_ldo_en = 1" "0,1"
newline
bitfld.long 0x18 0. "O_CMNDA_RX_LDO_EN_TM_SEL,rx_ldo_en driven from test registers" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT38,CMN_DIG_TBIT38"
line.long 0x20 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT39,CMN_DIG_TBIT39"
rgroup.long 0xD8++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT50,BIST_STATUS_REG1"
hexmask.long 0x00 2.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x00 1. "BIST_COMPLETE,BIST is completed" "0,1"
newline
bitfld.long 0x00 0. "BIST_EN_ACK,BIST Controller is enabled" "0,1"
rgroup.long 0xE4++0x07
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT53,CMN_DIG_TBIT53"
hexmask.long.word 0x00 17.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.word 0x00 1.--16. 1. "I_CMSMT_TEST_CLK_CNT_VALUE,Gives clocks cycles count for test clock during measurement"
newline
bitfld.long 0x00 0. "I_CMSMT_MEASUREMENT_DONE,Indicates clock measurement is done" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT54,CMN_DIG_TBIT54"
hexmask.long.word 0x04 20.--31. 1. "I_CMN_PLL_SSM_STATE,Gives CMN PLL ssm state"
newline
hexmask.long.word 0x04 5.--19. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x04 4. "I_DIG_PG_ACK,PSM power good acknowledgement" "0,1"
newline
bitfld.long 0x04 3. "I_PLL_NOT_LOCKED,Indicates PLL is not locked before timeout" "0,1"
newline
bitfld.long 0x04 2. "I_PLL_LOCKED,Indicates PLL is locked" "0,1"
newline
bitfld.long 0x04 1. "I_ANA_RES_COMP_OUT,read value of comaprator output" "0,1"
newline
bitfld.long 0x04 0. "I_CMN_TX_READY,Indiacates cmn is ready for TX IP" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT56,CMN_DIG_TBIT56"
bitfld.long 0x00 28.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 21.--27. 1. "I_CMNDA_RX_OSC_CALCODE,Reads out calib code applied to osicllator"
newline
hexmask.long.word 0x00 11.--20. 1. "I_CMN_RX_SSM_STATE,Gives CMN Rx ssm state"
newline
hexmask.long.word 0x00 2.--10. 1. "I_RX_OSC_CAL_FSM_STATE,Gives Rx osc calib FSM state"
newline
bitfld.long 0x00 1. "I_ANA_RES_COMP_OUT,read value of comaprator output" "0,1"
newline
bitfld.long 0x00 0. "I_CMN_RX_READY,Indicates cmn is ready for RX IP" "0,1"
rgroup.long 0xF8++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT58,CMN_DIG_TBIT58"
hexmask.long 0x00 6.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x00 1.--5. "I_RES_CALIB_CODE,Gives out calibrated resistor calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "I_RES_CALIB_DONE,Indicates resistor calibration is done" "0,1"
rgroup.long 0x108++0x2B
line.long 0x00 "DPHY_RX_VBUS2APB_CLK0_RX_ANA_TBIT2,Analog Test Bit Reg2"
line.long 0x04 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT0,Digital Test Bit Reg0"
hexmask.long 0x04 5.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 4. "TD_RSTN,TD is reset - Active low reset control to 'transition_detector_logic'" "0,1"
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bitfld.long 0x04 3. "TD_EN,TD is ENABLED - Active high control to enable 'transition_detector_logic'" "0,1"
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bitfld.long 0x04 2. "TM_ULPS_ACTIVE_NOT_SEL,Power suspend request in ULPS mode through a test register bypassed with a test value via bit-1 here" "0,1"
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bitfld.long 0x04 1. "TM_ULPS_ACTIVE_NOT,When want to control the ULPS mode power suspend request by test register what should be the value" "0,1"
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bitfld.long 0x04 0. "FORCE_RX_HS_MODE,Set this bit to force the CRX into HS mode" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT1,Digital Extra Test Bit Reg0"
line.long 0x0C "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT2,Test Mux Register"
hexmask.long.byte 0x0C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 24. "RXDA_LPRX_BIST_EN,LP BIST ENABLED" "0,1"
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bitfld.long 0x0C 23. "RXDA_ASYNC_CLK_EN_SEL,rxda_async_clk_en_sel - Controls the selection on clock 'Gate-en' for allowing HS-DDR clock onto Aanlog Interface with options being the funtional mode or from Register-bit" "0,1"
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bitfld.long 0x0C 22. "RXDA_ASYNC_CLK_EN,rxda_async_clk_en - 'Gate_en' value to be considered when choosen to take the value through software way when [23] here is set" "0,1"
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bitfld.long 0x0C 21. "RXDA_HSRX_BIST_EN_SEL,rxda_hsrx_bist_en_sel - Select signal to choose between functional 'bist_en' from top-level [or] from software register" "0,1"
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bitfld.long 0x0C 20. "RXDA_HSRX_BIST_EN,rxda_hsrx_bist_en - value to be considered when choosen to take the value through software way" "0,1"
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bitfld.long 0x0C 19. "RXDA_FREQ_BAND_SEL1_SEL,rxda_freq_band_sel1_sel - Select signal to choose between functional 'freq_band' from top-level [or] from software register" "0,1"
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bitfld.long 0x0C 15.--18. "RXDA_FREQ_BAND_SEL1,rxda_freq_band_sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 14. "RXDA_FREQ_BAND_SEL2_SEL,rxda_freq_band_sel2_sel - Select signal to choose between functional 'freq_band' from top-level [or] from software register" "0,1"
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bitfld.long 0x0C 10.--13. "RXDA_FREQ_BAND_SEL2,rxda_freq_band_sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 9. "RXDA_HS_START_PULSE_SEL,rxda_hs_start_pulse_sel - Select signal to choose between functional 'start_pulse' [or] from software register" "0,1"
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bitfld.long 0x0C 8. "RXDA_HS_START_PULSE,rxda_hs_start_pulse - 'start_pulse' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "RXDA_HS_STBY_EN_SEL,rxda_hs_stby_en_sel - Select signal to choose between functional 'stby_en' [or] from software register" "0,1"
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bitfld.long 0x0C 6. "RXDA_HS_STBY_EN,rxda_hs_stby_en - 'stby_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 5. "RXDA_LPRXCD_EN_SEL,rxda_lprxcd_en_sel - Select signal to choose between functional 'lprxcd_en' [or] from software register" "0,1"
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bitfld.long 0x0C 4. "RXDA_LPRXCD_EN,rxda_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 3. "RXDA_RX_TERM_EN_SEL,rxda_rx_term_en_sel - Select signal to choose between functional 'term_en' [or] from software register" "0,1"
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bitfld.long 0x0C 2. "RXDA_RX_TERM_EN,rxda_rx_term_en - 'term_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 1. "RXDA_ULPS_EN_SEL,rxda_ulps_en_sel - Select signal to choose between functional 'ulps_en' [or] from software register" "0,1"
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bitfld.long 0x0C 0. "RXDA_ULPS_EN,rxda_ulps_en - 'ulps_en' value considered when selected to have it via software way" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT3,Digital Extra Test Bit Reg1"
line.long 0x14 "DPHY_RX_VBUS2APB_CLK0_RX_ANA_TBIT3,Analog Read Test Bit Reg3"
line.long 0x18 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT4,Digital Read Test Reg0"
hexmask.long.tbyte 0x18 14.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 8.--13. "LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x18 0.--7. 1. "TD_STATUS,Posedge and Negedge transition detect status of LPRX_DP LPRX_DN LPCD_DP LPCD_DN"
line.long 0x1C "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT5,Digital Read Test Bit Reg0"
line.long 0x20 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT6,BIST Status Reg0"
line.long 0x24 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT7,Bist Extra Status Read Reg0"
line.long 0x28 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT8,Digital Extra Read Reg0"
group.long 0x200++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
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bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
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bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
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bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
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bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
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bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
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bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
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hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
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bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
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bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
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hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
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bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
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bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
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bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
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bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
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bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x274++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x28C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
newline
bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
newline
bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x2C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0x300++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
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bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
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bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
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bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
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bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
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bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
newline
bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
newline
bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
newline
bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
newline
bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
newline
bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
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bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
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hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
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bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
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bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
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hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
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bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
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bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
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bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
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bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
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bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x374++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x38C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
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bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
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bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x3C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0x400++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
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bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
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bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
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bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
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bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
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bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
newline
bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
newline
bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
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hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
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bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
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bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
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hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
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bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
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bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
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bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
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bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
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bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x474++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x48C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
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bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
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bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x4C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0x500++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
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bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
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bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
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bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
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bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
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bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
newline
bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
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hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
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bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
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bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
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hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
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bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
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bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
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bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
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bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
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bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x574++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x58C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
newline
hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
newline
hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
newline
hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
newline
bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
newline
hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
newline
bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
newline
hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
newline
bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
newline
bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
newline
bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
newline
bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x5C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
newline
hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
newline
bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
newline
bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0xB00++0x2B
line.long 0x00 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL"
hexmask.long.tbyte 0x00 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x00 5.--9. "BAND_CTL_REG_R,Data Rate [80_100] MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "BAND_CTL_REG_L,Data Rate [80_100] MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG"
hexmask.long.tbyte 0x04 9.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x04 1.--8. 1. "PSM_CLOCK_FREQ,psm_clock freq value"
newline
bitfld.long 0x04 0. "PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT2,PHY_PI_PH2_DL_CONFIG"
bitfld.long 0x08 28.--31. "POWER_SW_2_TIME_DL_R_3,power_sw_2_time_dl_r_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 24.--27. "POWER_SW_2_TIME_DL_R_2,power_sw_2_time_dl_r_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 20.--23. "POWER_SW_2_TIME_DL_R_1,power_sw_2_time_dl_r_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "POWER_SW_2_TIME_DL_R_0,power_sw_2_time_dl_r_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 12.--15. "POWER_SW_2_TIME_DL_L_3,power_sw_2_time_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 8.--11. "POWER_SW_2_TIME_DL_L_2,power_sw_2_time_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 4.--7. "POWER_SW_2_TIME_DL_L_1,power_sw_2_time_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "POWER_SW_2_TIME_DL_L_0,power_sw_2_time_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT3,PHY_PI_PH2_CL_CMN_CONFIG"
hexmask.long.tbyte 0x0C 12.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x0C 8.--11. "POWER_SW_2_TIME_CMN,power_sw_2_time_cmn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 4.--7. "POWER_SW_2_TIME_CL_R,power_sw_2_time_cl_r" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "POWER_SW_2_TIME_CL_L,power_sw_2_time_cl_l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT4,PHY_PI_PH1_DL_CONFIG"
bitfld.long 0x10 28.--31. "POWER_SW_1_TIME_DL_R_3,power_sw_1_time_dl_r_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 24.--27. "POWER_SW_1_TIME_DL_R_2,power_sw_1_time_dl_r_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 20.--23. "POWER_SW_1_TIME_DL_R_1,power_sw_1_time_dl_r_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 16.--19. "POWER_SW_1_TIME_DL_R_0,power_sw_1_time_dl_r_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 12.--15. "POWER_SW_1_TIME_DL_L_3,power_sw_1_time_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 8.--11. "POWER_SW_1_TIME_DL_L_2,power_sw_1_time_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4.--7. "POWER_SW_1_TIME_DL_L_1,power_sw_1_time_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "POWER_SW_1_TIME_DL_L_0,power_sw_1_time_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT5,PHY_PI_PH1_CL_CMN_CONFIG"
hexmask.long.tbyte 0x14 12.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x14 8.--11. "POWER_SW_1_TIME_CMN,power_sw_1_time_cmn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 4.--7. "POWER_SW_1_TIME_CL_R,power_sw_1_time_cl_r" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0.--3. "POWER_SW_1_TIME_CL_L,power_sw_1_time_cl_l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT6,PHY_DL_SPARE_LEFT"
hexmask.long.byte 0x18 24.--31. 1. "DTX_L_3_SPARE,dtx_l_3 spare port"
newline
hexmask.long.byte 0x18 16.--23. 1. "DTX_L_2_SPARE,dtx_l_2 spare port"
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hexmask.long.byte 0x18 8.--15. 1. "DTX_L_1_SPARE,dtx_l_1 spare port"
newline
hexmask.long.byte 0x18 0.--7. 1. "DTX_L_0_SPARE,dtx_l_0 spare port"
line.long 0x1C "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT7,PHY_DL_SPARE_RIGHT"
hexmask.long.byte 0x1C 24.--31. 1. "DTX_R_3_SPARE,dtx_r_3 spare port"
newline
hexmask.long.byte 0x1C 16.--23. 1. "DTX_R_2_SPARE,dtx_r_2 spare port"
newline
hexmask.long.byte 0x1C 8.--15. 1. "DTX_R_1_SPARE,dtx_r_1 spare port"
newline
hexmask.long.byte 0x1C 0.--7. 1. "DTX_R_0_SPARE,dtx_r_0 spare port"
line.long 0x20 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT8,PHY_CL_CMN_SPARE"
hexmask.long.byte 0x20 24.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x20 16.--23. 1. "CMN_SPARE,cmn spare port"
newline
hexmask.long.byte 0x20 8.--15. 1. "CL_R_SPARE,cl_r spare port"
newline
hexmask.long.byte 0x20 0.--7. 1. "CL_L_SPARE,cl_l spare port"
line.long 0x24 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT9,PHY_PI_CONFIG"
hexmask.long 0x24 2.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x24 1. "PSO_DISABLE_VALUE,pso_disbale value" "0,1"
newline
bitfld.long 0x24 0. "PSO_DISABLE_EN,take pso_diable from tbit" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT10,DIG_TBIT10"
group.long 0xC00++0x47
line.long 0x00 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_CNTRL,PHY_ISO_CNTRL"
hexmask.long.tbyte 0x00 12.--31. 1. "BF_31_12,"
newline
bitfld.long 0x00 11. "PHY_ISOLATION,when set enables phy_isolation" "0,1"
newline
bitfld.long 0x00 10. "PHY_ISO_CMN,This bit enables the Isolation on Common Lane" "0,1"
newline
bitfld.long 0x00 8.--9. "PHY_ISO_CL,Bit" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "PHY_ISO_DL,Bit"
line.long 0x04 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_RESET,PHY_ISO_RESET"
hexmask.long.tbyte 0x04 11.--31. 1. "BF_31_11,"
newline
bitfld.long 0x04 10. "LANE_RSTB_CMN,Drives the Lane Reset for Common lane_rstb_cmn" "0,1"
newline
bitfld.long 0x04 9. "LANE_RSTB_CL_R,Drives the Right Clock Lane Reset lane_rstb_cl_l" "0,1"
newline
bitfld.long 0x04 8. "LANE_RSTB_CL_L,Drives the Left Clock Lane Reset lane_rstb_cl_l" "0,1"
newline
bitfld.long 0x04 7. "LANE_RSTB_DL_R_3,Drives the Data Lane 3 Right Link Reset lane_rstb_dl_7" "0,1"
newline
bitfld.long 0x04 6. "LANE_RSTB_DL_R_2,Drives the Data Lane 2 Right Link Reset lane_rstb_dl_6" "0,1"
newline
bitfld.long 0x04 5. "LANE_RSTB_DL_R_1,Drives the Data Lane 1 Right Link Reset lane_rstb_dl_5" "0,1"
newline
bitfld.long 0x04 4. "LANE_RSTB_DL_R_0,Drives the Data Lane 0 Right Link Reset lane_rstb_dl_4" "0,1"
newline
bitfld.long 0x04 3. "LANE_RSTB_DL_L_3,Drives the Data Lane 3 Left Link Reset lane_rstb_dl_3" "0,1"
newline
bitfld.long 0x04 2. "LANE_RSTB_DL_L_2,Drives the Data Lane 2 Left Link Reset lane_rstb_dl_2" "0,1"
newline
bitfld.long 0x04 1. "LANE_RSTB_DL_L_1,Drives the Data Lane 1 Left Link Reset lane_rstb_dl_1" "0,1"
newline
bitfld.long 0x04 0. "LANE_RSTB_DL_L_0,Drives the Data Lane 0 Left Link Reset lane_rstb_dl_0" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_ENABLE,PHY_ISO_ENABLE"
hexmask.long.tbyte 0x08 10.--31. 1. "BF_31_10,"
newline
bitfld.long 0x08 9. "RXENABLECLK_CLK_R,Drives to enable the right clock DPHY_RX_VBUS2APB_LANE TxEnableClk_clk_r" "0,1"
newline
bitfld.long 0x08 8. "RXENABLECLK_CLK_L,Drives to enable the left clock DPHY_RX_VBUS2APB_LANE TxEnableClk_clk_l" "0,1"
newline
bitfld.long 0x08 7. "S_ENABLE_DL_R_3,Enables the Data Lane 3 Right Link M_Enable_dl_7" "0,1"
newline
bitfld.long 0x08 6. "S_ENABLE_DL_R_2,Enables the Data Lane 2 Right Link M_Enable_dl_6" "0,1"
newline
bitfld.long 0x08 5. "S_ENABLE_DL_R_1,Enables the Data Lane 1 Right Link M_Enable_dl_5" "0,1"
newline
bitfld.long 0x08 4. "S_ENABLE_DL_R_0,Enables the Data Lane 0 Right Link M_Enable_dl_4" "0,1"
newline
bitfld.long 0x08 3. "S_ENABLE_DL_L_3,Enables the Data Lane 3 Left Link M_Enable_dl_3" "0,1"
newline
bitfld.long 0x08 2. "S_ENABLE_DL_L_2,Enables the Data Lane 2 Left Link M_Enable_dl_2" "0,1"
newline
bitfld.long 0x08 1. "S_ENABLE_DL_L_1,Enables the Data Lane 1 Left Link M_Enable_dl_1" "0,1"
newline
bitfld.long 0x08 0. "S_ENABLE_DL_L_0,Enables the Data Lane 0 Left Link M_Enable_dl_0" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_ISO_PHY_ISO_CMN_CTRL,PHY_ISO_CMN_CTRL"
hexmask.long.tbyte 0x0C 9.--31. 1. "BF_31_9,"
newline
rbitfld.long 0x0C 8. "LANE_READY_CMN,Drives lane_ready_cmn" "0,1"
newline
rbitfld.long 0x0C 7. "O_SUPPLY_IO_PG,I/O supply power is good o_supply_io_pg" "0,1"
newline
rbitfld.long 0x0C 6. "O_SUPPLY_CORE_PG,Core Supply Power is good o_supply_core_pg" "0,1"
newline
rbitfld.long 0x0C 5. "O_CMN_READY,Common ready Indicator o_cmn_ready" "0,1"
newline
bitfld.long 0x0C 2.--4. "IP_CONFIG_CMN,Drives the IP configuration to decide which clock DPHY_RX_VBUS2APB_LANE acts as the master DPHY_RX_VBUS2APB_LANE to all clock lanes ip_config_cmn" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 1. "PSO_CMN,Drives the power shut off for the Common pso_cmn" "0,1"
newline
bitfld.long 0x0C 0. "PSO_DISABLE,Disable power shut off pso_disable" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_CL_CNTRL_L,PHY_ISO_CL_CNTRL_L"
hexmask.long 0x10 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x10 6. "S_CLK_SWAPDPDN_CL_L,Drives the value to enable the Swap of DP and DN signals inside the clock DPHY_RX_VBUS2APB_LANE S_Clk_SwapDpDn_cl_l" "0,1"
newline
rbitfld.long 0x10 5. "RXULPSCLKNOT_CL_L,Receives ULPS power state status RxULPSClkNot_cl_l" "0,1"
newline
rbitfld.long 0x10 4. "RXSTOPSTATECLK_CL_L,Receives DPHY_RX_VBUS2APB_LANE state status RxStopStateClk_cl_l" "0,1"
newline
rbitfld.long 0x10 3. "RXULPSACTIVENOTCLK_CL_L,Receives DPHY_RX_VBUS2APB_LANE ULPS active state status RxULPSActiveNotClk_cl_l" "0,1"
newline
rbitfld.long 0x10 2. "RXCLKACTIVEHSCLK_CL_L,Stores Receiver high speed active RxClkActiveHSClk_cl_l" "0,1"
newline
bitfld.long 0x10 1. "RXENABLECLK_CL_L,Enable the Clock Lane RxEnableClk_cl_l" "0,1"
newline
rbitfld.long 0x10 0. "LANE_READY_CL_L,High speed clock transmission ready lane_ready_cl_l" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_CTRL_L0,PHY_ISO_DL_CTRL_L0"
hexmask.long 0x14 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x14 6. "S_CLK_SWAPDPDN_DL_L_0,Drives S_Clk_SwapDpDn_dl_l_0" "0,1"
newline
bitfld.long 0x14 5. "FORCERXMODE_DL_L_0,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_0" "0,1"
newline
bitfld.long 0x14 4. "S_DATA_SWAPDPDN_DL_L_0,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_0" "0,1"
newline
rbitfld.long 0x14 3. "S_STOPSTATE_DL_L_0,Receives Lane Stop state status S_StopState_dl_l_0" "0,1"
newline
rbitfld.long 0x14 2. "S_ULPSACTIVENOT_DL_L_0,Receives the Turnaround request S_ULPSActiveNot_dl_l_0" "0,1"
newline
bitfld.long 0x14 1. "S_ENABLE_DL_L_0,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_0" "0,1"
newline
rbitfld.long 0x14 0. "LANE_READY_DL_L_0,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_0" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_HS_L0,PHY_ISO_DL_HS_L0"
hexmask.long.tbyte 0x18 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x18 13. "ERRSOTSYNCHS_DL_L_0,Start of transmission error ErrSoTSyncHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 12. "ERRSOTHS_DL_L_0,Start of transmission error ErrSoTHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 11. "RXSYNCHS_DL_L_0,Stores the high speed receive synchronization RxSyncHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 10. "RXVALIDHS_DL_L_0,High speed data receive data valid RxValidHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 9. "RXSKEWCALHS_DL_L_0,High speed data receive dksew calibration RxSkewCalHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 8. "RXACTIVEHS_DL_L_0,Stores the high speed data reception active RxActiveHS_dl_l_0" "0,1"
newline
hexmask.long.byte 0x18 0.--7. 1. "RXDATAHS_DL_L_0,High speed receive data RxDataHS_dl_l_0"
line.long 0x1C "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_RX_ESC_L0,PHY_ISO_DL_RX_ESC_L0"
hexmask.long.word 0x1C 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x1C 17. "S_ERRSYNC_DL_L_0,Control error S_ErrControl_dl_l_0" "0,1"
newline
bitfld.long 0x1C 16. "S_ERRCONTROL_DL_L_0,Control error S_ErrControl_dl_l_0" "0,1"
newline
bitfld.long 0x1C 15. "S_ERRESC_DL_L_0,Escape entry error S_ErrEsc_dl_l_0" "0,1"
newline
bitfld.long 0x1C 11.--14. "S_RXTRIGGERESC_DL_L_0,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 10. "S_RXULPSESC_DL_L_0,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_0" "0,1"
newline
bitfld.long 0x1C 9. "S_RXVALIDESC_DL_L_0,Receive escape mode data present S_RxValidEsc_dl_l_0" "0,1"
newline
bitfld.long 0x1C 8. "S_RXLPDTESC_DL_L_0,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_0" "0,1"
newline
hexmask.long.byte 0x1C 0.--7. 1. "S_RXDATAESC_DL_L_0,Receive escape mode low power receive data S_RxDataEsc_dl_l_0"
line.long 0x20 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_CTRL_L1,PHY_ISO_DL_CTRL_L1"
hexmask.long 0x20 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x20 6. "S_CLK_SWAPDPDN_DL_L_1,Drives S_Clk_SwapDpDn_dl_l_1" "0,1"
newline
bitfld.long 0x20 5. "FORCERXMODE_DL_L_1,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_1" "0,1"
newline
bitfld.long 0x20 4. "S_DATA_SWAPDPDN_DL_L_1,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_1" "0,1"
newline
rbitfld.long 0x20 3. "S_STOPSTATE_DL_L_1,Receives Lane Stop state status S_StopState_dl_l_1" "0,1"
newline
rbitfld.long 0x20 2. "S_ULPSACTIVENOT_DL_L_1,Receives the Turnaround request S_ULPSActiveNot_dl_l_1" "0,1"
newline
bitfld.long 0x20 1. "S_ENABLE_DL_L_1,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_1" "0,1"
newline
rbitfld.long 0x20 0. "LANE_READY_DL_L_1,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_1" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_HS_L1,PHY_ISO_DL_HS_L1"
hexmask.long.tbyte 0x24 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x24 13. "ERRSOTSYNCHS_DL_L_1,Start of transmission error ErrSoTSyncHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 12. "ERRSOTHS_DL_L_1,Start of transmission error ErrSoTHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 11. "RXSYNCHS_DL_L_1,Stores the high speed receive synchronization RxSyncHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 10. "RXVALIDHS_DL_L_1,High speed data receive data valid RxValidHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 9. "RXSKEWCALHS_DL_L_1,High speed data receive dksew calibration RxSkewCalHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 8. "RXACTIVEHS_DL_L_1,Stores the high speed data reception active RxActiveHS_dl_l_1" "0,1"
newline
hexmask.long.byte 0x24 0.--7. 1. "RXDATAHS_DL_L_1,High speed receive data RxDataHS_dl_l_1"
line.long 0x28 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_RX_ESC_L1,PHY_ISO_DL_RX_ESC_L1"
hexmask.long.word 0x28 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x28 17. "S_ERRSYNC_DL_L_1,Control error S_ErrControl_dl_l_1" "0,1"
newline
bitfld.long 0x28 16. "S_ERRCONTROL_DL_L_1,Control error S_ErrControl_dl_l_1" "0,1"
newline
bitfld.long 0x28 15. "S_ERRESC_DL_L_1,Escape entry error S_ErrEsc_dl_l_1" "0,1"
newline
bitfld.long 0x28 11.--14. "S_RXTRIGGERESC_DL_L_1,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 10. "S_RXULPSESC_DL_L_1,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_1" "0,1"
newline
bitfld.long 0x28 9. "S_RXVALIDESC_DL_L_1,Receive escape mode data present S_RxValidEsc_dl_l_1" "0,1"
newline
bitfld.long 0x28 8. "S_RXLPDTESC_DL_L_1,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_1" "0,1"
newline
hexmask.long.byte 0x28 0.--7. 1. "S_RXDATAESC_DL_L_1,Receive escape mode low power receive data S_RxDataEsc_dl_l_1"
line.long 0x2C "DPHY_RX_VBUS2APB_ISO_PHY_ISO_SPARE_1,PHY_ISO_SPARE_1"
line.long 0x30 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_CTRL_L2,PHY_ISO_DL_CTRL_L2"
hexmask.long 0x30 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x30 6. "S_CLK_SWAPDPDN_DL_L_2,Drives S_Clk_SwapDpDn_dl_l_2" "0,1"
newline
bitfld.long 0x30 5. "FORCERXMODE_DL_L_2,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_2" "0,1"
newline
bitfld.long 0x30 4. "S_DATA_SWAPDPDN_DL_L_2,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_2" "0,1"
newline
rbitfld.long 0x30 3. "S_STOPSTATE_DL_L_2,Receives Lane Stop state status S_StopState_dl_l_2" "0,1"
newline
rbitfld.long 0x30 2. "S_ULPSACTIVENOT_DL_L_2,Receives the Turnaround request S_ULPSActiveNot_dl_l_2" "0,1"
newline
bitfld.long 0x30 1. "S_ENABLE_DL_L_2,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_2" "0,1"
newline
rbitfld.long 0x30 0. "LANE_READY_DL_L_2,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_2" "0,1"
line.long 0x34 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_HS_L2,PHY_ISO_DL_HS_L2"
hexmask.long.tbyte 0x34 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x34 13. "ERRSOTSYNCHS_DL_L_2,Start of transmission error ErrSoTSyncHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 12. "ERRSOTHS_DL_L_2,Start of transmission error ErrSoTHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 11. "RXSYNCHS_DL_L_2,Stores the high speed receive synchronization RxSyncHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 10. "RXVALIDHS_DL_L_2,High speed data receive data valid RxValidHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 9. "RXSKEWCALHS_DL_L_2,High speed data receive dksew calibration RxSkewCalHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 8. "RXACTIVEHS_DL_L_2,Stores the high speed data reception active RxActiveHS_dl_l_2" "0,1"
newline
hexmask.long.byte 0x34 0.--7. 1. "RXDATAHS_DL_L_2,High speed receive data RxDataHS_dl_l_2"
line.long 0x38 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_RX_ESC_L2,PHY_ISO_DL_RX_ESC_L2"
hexmask.long.word 0x38 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x38 17. "S_ERRSYNC_DL_L_2,Control error S_ErrControl_dl_r_2" "0,1"
newline
bitfld.long 0x38 16. "S_ERRCONTROL_DL_L_2,Control error S_ErrControl_dl_l_2" "0,1"
newline
bitfld.long 0x38 15. "S_ERRESC_DL_L_2,Escape entry error S_ErrEsc_dl_l_2" "0,1"
newline
bitfld.long 0x38 11.--14. "S_RXTRIGGERESC_DL_L_2,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 10. "S_RXULPSESC_DL_L_2,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_2" "0,1"
newline
bitfld.long 0x38 9. "S_RXVALIDESC_DL_L_2,Receive escape mode data present S_RxValidEsc_dl_l_2" "0,1"
newline
bitfld.long 0x38 8. "S_RXLPDTESC_DL_L_2,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_2" "0,1"
newline
hexmask.long.byte 0x38 0.--7. 1. "S_RXDATAESC_DL_L_2,Receive escape mode low power receive data S_RxDataEsc_dl_l_2"
line.long 0x3C "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_CTRL_L3,PHY_ISO_DL_CTRL_L3"
hexmask.long 0x3C 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x3C 6. "S_CLK_SWAPDPDN_DL_L_3,Drives S_Clk_SwapDpDn_dl_l_0" "0,1"
newline
bitfld.long 0x3C 5. "FORCERXMODE_DL_L_3,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_3" "0,1"
newline
bitfld.long 0x3C 4. "S_DATA_SWAPDPDN_DL_L_3,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_3" "0,1"
newline
rbitfld.long 0x3C 3. "S_STOPSTATE_DL_L_3,Receives Lane Stop state status S_StopState_dl_l_3" "0,1"
newline
rbitfld.long 0x3C 2. "S_ULPSACTIVENOT_DL_L_3,Receives the Turnaround request S_ULPSActiveNot_dl_l_3" "0,1"
newline
bitfld.long 0x3C 1. "S_ENABLE_DL_L_3,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_3" "0,1"
newline
rbitfld.long 0x3C 0. "LANE_READY_DL_L_3,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_3" "0,1"
line.long 0x40 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_HS_L3,PHY_ISO_DL_HS_L3"
hexmask.long.tbyte 0x40 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x40 13. "ERRSOTSYNCHS_DL_L_3,Start of transmission error ErrSoTSyncHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 12. "ERRSOTHS_DL_L_3,Start of transmission error ErrSoTHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 11. "RXSYNCHS_DL_L_3,Stores the high speed receive synchronization RxSyncHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 10. "RXVALIDHS_DL_L_3,High speed data receive data valid RxValidHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 9. "RXSKEWCALHS_DL_L_3,High speed data receive dksew calibration RxSkewCalHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 8. "RXACTIVEHS_DL_L_3,Stores the high speed data reception active RxActiveHS_dl_l_3" "0,1"
newline
hexmask.long.byte 0x40 0.--7. 1. "RXDATAHS_DL_L_3,High speed receive data RxDataHS_dl_l_3"
line.long 0x44 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_RX_ESC_L3,PHY_ISO_DL_RX_ESC_L3"
hexmask.long.word 0x44 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x44 17. "S_ERRSYNC_DL_L_3,Control error S_ErrSync_dl_l_3" "0,1"
newline
bitfld.long 0x44 16. "S_ERRCONTROL_DL_L_3,Control error S_ErrControl_dl_l_3" "0,1"
newline
bitfld.long 0x44 15. "S_ERRESC_DL_L_3,Escape entry error S_ErrEsc_dl_l_3" "0,1"
newline
bitfld.long 0x44 11.--14. "S_RXTRIGGERESC_DL_L_3,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x44 10. "S_RXULPSESC_DL_L_3,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_3" "0,1"
newline
bitfld.long 0x44 9. "S_RXVALIDESC_DL_L_3,Receive escape mode data present S_RxValidEsc_dl_l_3" "0,1"
newline
bitfld.long 0x44 8. "S_RXLPDTESC_DL_L_3,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_3" "0,1"
newline
hexmask.long.byte 0x44 0.--7. 1. "S_RXDATAESC_DL_L_3,Receive escape mode low power receive data S_RxDataEsc_dl_l_3"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
rgroup.long ($2+0xC48)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_RX_SPARE_$1,PHY_ISO_RX_SPARE_1"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x5D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x5C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x584)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x56C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x4D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x4C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x484)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x46C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x3D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x3C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x384)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x36C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x2D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x2C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x284)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x26C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x100)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CLK0_RX_ANA_TBIT$1,Analog Test Bit Reg0"
repeat.end
repeat 4. (list 0. 1. 2. 4. )(list 0x00 0x04 0x08 0x10 )
group.long ($2+0x00)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_ANA_TBIT$1,CMN_ANA_TBIT0"
repeat.end
tree.end
tree "DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX"
base ad:0x4590000
rgroup.long 0x0C++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_ANA_TBIT3,CMN_ANA_TBIT3"
group.long 0x14++0x3F
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_ANA_TBIT5,CMN_ANA_TBIT5"
hexmask.long.tbyte 0x00 8.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x00 0.--7. 1. "ANA_TBIT5,Analog Test register 5"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT0,CMN_DIG_TBIT0"
rbitfld.long 0x04 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 28. "O_RES_CAL_START_TM,res_cal_start in test mode" "0,1"
newline
bitfld.long 0x04 27. "O_RES_CAL_START_TM_SEL,res_cal_start select from test_mode" "0,1"
newline
bitfld.long 0x04 26. "O_RES_COMP_OUT_POL_INV_TM,Invert polarity for resistor calib comparator output" "0,1"
newline
bitfld.long 0x04 22.--25. "O_RES_TX_OFFSET_TEST_LOW_TM,o_res_tx_offset_test_low_TM - Res calib manipulation code for res calib code low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 21. "O_RES_TX_OFFSET_LOW_DEC_TM,o_res_tx_offset_low_dec_TM asserted - Perform increment manipulation on res calib code if o_res_tx_offset_low_TM_sel is asserted" "0,1"
newline
bitfld.long 0x04 20. "O_RES_TX_OFFSET_LOW_TM_SEL,o_res_tx_offset_low_TM_sel asserted - Enable offset manipulation for res calib code low" "0,1"
newline
bitfld.long 0x04 16.--19. "O_RES_TX_OFFSET_TEST_HIGH_TM,o_res_tx_offset_test_high_TM - Res calib manipulation code for res calib code high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 15. "O_RES_TX_OFFSET_HIGH_DEC_TM,o_res_tx_offset_high_dec_TM asserted - Perform increment manipulation on res calib code if o_res_tx_offset_high_TM_sel is asserted" "0,1"
newline
bitfld.long 0x04 14. "O_RES_TX_OFFSET_HIGH_TM_SEL,o_res_tx_offset_high_TM_sel asserted - Enable offset manipulation for res calib code high" "0,1"
newline
bitfld.long 0x04 10.--13. "O_RES_CALIB_DECISION_WAIT_TM,res_calib decision wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 6.--9. "O_RES_CALIB_INIT_WAIT_TM,res_calib initial wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 5. "O_RES_CALIB_RSTB_TM,w_res_calib_rstb value in testmode" "0,1"
newline
bitfld.long 0x04 4. "O_RES_CALIB_RSTB_TM_SEL,w_res_calib_rstb select from test_mode" "0,1"
newline
rbitfld.long 0x04 0.--3. "UNUSED2,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT1,CMN_DIG_TBIT1"
bitfld.long 0x08 31. "O_ATB_EN,ATB probing enabled" "0,1"
newline
bitfld.long 0x08 30. "O_ATB_SRC,Select IO for atb probing" "0,1"
newline
hexmask.long.word 0x08 17.--29. 1. "BF_29_17,"
newline
bitfld.long 0x08 16. "O_ANA_PLL_ATB_CP_CUR_SEL,o_ana_pll_atb_cp_cur_sel" "0,1"
newline
bitfld.long 0x08 15. "O_ANA_PLL_ATBH_GM_CUR_SEL,o_ana_pll_atbh_gm_cur_sel" "0,1"
newline
rbitfld.long 0x08 10.--14. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 9. "O_ANA_BG_PD_TM,o_ana_bg_pd value in testmode" "0,1"
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bitfld.long 0x08 8. "O_ANA_BG_PD_TM_SEL,o_ana_bg_pd select from test_mode" "0,1"
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bitfld.long 0x08 7. "O_ANA_RES_CALIB_PD_TM,o_ana_res_calib_pd value in testmode" "0,1"
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bitfld.long 0x08 6. "O_ANA_RES_CALIB_PD_TM_SEL,o_ana_res_calib_pd select from test_mode" "0,1"
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bitfld.long 0x08 1.--5. "O_ANA_RES_CALIB_CODE_TM,o_ana_res_calib_code value in test_mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0. "O_ANA_RES_CALIB_CODE_TM_SEL,o_ana_res_calib_code select from test_mode" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2"
hexmask.long.tbyte 0x0C 11.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 10. "O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1"
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bitfld.long 0x0C 9. "O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1"
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hexmask.long.byte 0x0C 1.--8. 1. "O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled [in us]"
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bitfld.long 0x0C 0. "O_CMN_SSM_EN,Enable CMN startup state machine" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT3,CMN_DIG_TBIT3"
hexmask.long.byte 0x10 24.--31. 1. "O_PLL_WAIT_PLL_ACCINV,Wait time in pll_accinv [in us]"
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hexmask.long.byte 0x10 16.--23. 1. "O_PLL_WAIT_PLL_BIAS,Wait time in pll_bias [in us]"
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hexmask.long.byte 0x10 8.--15. 1. "O_PLL_WAIT_PLL_EN_DEL,Wait time in pll_en_del [in us]"
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hexmask.long.byte 0x10 0.--7. 1. "O_PLL_WAIT_PLL_EN,Wait time in PLL en [in us]"
line.long 0x14 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT4,CMN_DIG_TBIT4"
rbitfld.long 0x14 28.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x14 16.--27. 1. "O_PLL_WAIT_PLL_LOCK_DET_WAIT,Wait time in pll_lock_det_wait [in us]"
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hexmask.long.byte 0x14 8.--15. 1. "O_PLL_WAIT_PLL_RST_DEASSERT_2,Wait time in pll_rst_deassert_2ndset [in us]"
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hexmask.long.byte 0x14 0.--7. 1. "O_PLL_WAIT_PLL_RST_DEASSERT,Wait time in pll_rst_deassert [in us]"
line.long 0x18 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT5,"
bitfld.long 0x18 30.--31. "O_CMN_TX_READY_TM_SEL,ATB probing enabled" "0,1,2,3"
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bitfld.long 0x18 29. "O_PLL_PROCEED_WITH_LOCK_FAIL_TM,o_ana_pll_atb_cp_cur_sel" "0,1"
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bitfld.long 0x18 28. "O_PLL_LOCKED_TM,Forced value of pll_locked going to fsm = 1" "0,1"
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bitfld.long 0x18 27. "O_PLL_LOCKED_TM_SEL,pll_locked going to fsm forced from test registers" "0,1"
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bitfld.long 0x18 26. "O_PLL_LOCK_DET_EN_TM,Forced value of pll_lock_det_en = 1" "0,1"
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bitfld.long 0x18 25. "O_PLL_LOCK_DET_EN_TM_SEL,pll_lock_det_en forced from test registers" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x18 0.--17. 1. "O_PLL_WAIT_PLL_LOCK_TIMEOUT,Wait time for pll_lock_timeout [in us]"
line.long 0x1C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT6,CMN_DIG_TBIT6"
hexmask.long.word 0x1C 16.--31. 1. "O_LOCKDET_REFCNT_IDLE_VALUE,refcnt idle value for PLL lock detect module"
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hexmask.long.word 0x1C 0.--15. 1. "O_LOCKDET_REFCNT_START_VALUE,refcnt start value for PLL lock detect module"
line.long 0x20 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT7,CMN_DIG_TBIT7"
hexmask.long.word 0x20 16.--31. 1. "O_LOCKDET_PLLCNT_LOCK_THR_VALUE,pllcnt lock threshold value for PLL lock detect module"
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hexmask.long.word 0x20 0.--15. 1. "O_LOCKDET_PLLCNT_START_VALUE,pllcnt start value for PLL lock detect module"
line.long 0x24 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT8,CMN_DIG_TBIT8"
hexmask.long.byte 0x24 24.--31. 1. "O_ANA_PLL_VRESET_VCTRL_TUNE,unconnected intended for vreset_vctrl[CP output] progrmmability"
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hexmask.long.byte 0x24 16.--23. 1. "O_ANA_PLL_VRESET_VCO_BIAS_TUNE,Programmability for vco bias[gmbyc] initial voltage"
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hexmask.long.byte 0x24 8.--15. 1. "O_ANA_PLL_GM_TUNE,gm tune value for PLL"
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hexmask.long.byte 0x24 0.--7. 1. "O_ANA_PLL_CP_TUNE,Charge Pump Tune value for PLL"
line.long 0x28 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT9,CMN_DIG_TBIT9"
hexmask.long.byte 0x28 24.--31. 1. "O_ANA_PLL_VREF_VCO_BIAS_TUNE,Tuning Control for reference vco bias in PLL"
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hexmask.long.byte 0x28 16.--23. 1. "O_ANA_PLL_VCO_BIAS_TUNE,Tuning Control for PLL vco bias"
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hexmask.long.byte 0x28 8.--15. 1. "O_ANA_PLL_GMBYC_CAP_TUNE,gmbyc tune value for PLL"
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hexmask.long.byte 0x28 0.--7. 1. "O_ANA_PLL_LOOP_FILTER_TUNE,Tuning Control for loop filter"
line.long 0x2C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10"
rbitfld.long 0x2C 28.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 20.--27. 1. "O_ANA_PLL_BYTECLK_DIV,Byteclk divider value"
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hexmask.long.word 0x2C 10.--19. 1. "O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider"
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hexmask.long.word 0x2C 0.--9. 1. "O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider"
line.long 0x30 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT11,CMN_DIG_TBIT11"
hexmask.long.word 0x30 16.--31. 1. "O_ANA_PLL_CYA,Drives pllda_cya going to ANA"
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rbitfld.long 0x30 13.--15. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 12. "O_ANA_PLL_PFD_EN_1U_DEL_TM_SEL,Testmode signal for selecting 1us delayed for pll_pfd_reset_n" "0,1"
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bitfld.long 0x30 11. "O_ANA_PLL_VRESET_VCO_BIAS_SEL,vreset_vctrl_gmbyc is set inside the pll_vreset_gen" "0,1"
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bitfld.long 0x30 10. "O_ANA_PLL_VRESET_VCTRL_SEL,vreset_vctrl is set to ground inside the pll_vreset_gen" "0,1"
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bitfld.long 0x30 9. "O_ANA_PLL_SEL_FBCLK_GM_PWM,Enable mode to use feedback clock as the PWM control input for the gm stage" "0,1"
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bitfld.long 0x30 8. "O_ANA_PLL_OP_BY2_BYPASS,Mode to bypass the divide by 2 in the PLL output which generates clk_bit and clk_bitb" "0,1"
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bitfld.long 0x30 7. "O_ANA_PLL_BYPASS,Bypass PLL and pass refclk as output" "0,1"
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bitfld.long 0x30 6. "O_ANA_PLL_FBDIV_CLKINBY2_EN,Enable division by 2 on the feedback divider input clock" "0,1"
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bitfld.long 0x30 5. "O_ANA_PLL_DSM_CLK_EN,Enable for dsm clock output to digital" "0,1"
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bitfld.long 0x30 4. "O_ANA_PLL_GM_PWM_EN,Enable PWM control of the gm else it will operate in the continuous mode" "0,1"
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bitfld.long 0x30 3. "O_ANA_PLL_OP_DIV_CLK_EN,Enable for op divider clock output to digital" "0,1"
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bitfld.long 0x30 2. "O_ANA_PLL_IP_DIV_CLK_EN,Enable for ip divider output to digital" "0,1"
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bitfld.long 0x30 1. "O_ANA_PLL_REF_CLK_EN,enables refclk to PLL" "0,1"
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bitfld.long 0x30 0. "O_ANA_PLL_FB_DIV_CLK_EN,Enable for feedback clock output to digital" "0,1"
line.long 0x34 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT12,CMN_DIG_TBIT12"
bitfld.long 0x34 31. "O_ANA_PLL_VRESET_GEN_EN_TM,Forced value of pll_vreset_gen_en = 1" "0,1"
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bitfld.long 0x34 30. "O_ANA_PLL_VRESET_GEN_EN_TM_SEL,pll_vreset_gen_en forced from test registers" "0,1"
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bitfld.long 0x34 29. "O_ANA_PLL_PFD_EN_TM,Forced value of pllda_pfd_en = 1" "0,1"
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bitfld.long 0x34 28. "O_ANA_PLL_PFD_EN_TM_SEL,pllda_pfd_en forced from test registers" "0,1"
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bitfld.long 0x34 27. "O_ANA_PLL_LOOP_FILTER_RESET_N_TM,Forced value of pll_loop_filter_reset_n = 1" "0,1"
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bitfld.long 0x34 26. "O_ANA_PLL_LOOP_FILTER_RESET_N_TM_SEL,pll_loop_filter_reset_n is drivne from test registers" "0,1"
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bitfld.long 0x34 25. "O_ANA_PLL_GM_RESET_N_TM,Forced value of pll_gm_reset_n = 1" "0,1"
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bitfld.long 0x34 24. "O_ANA_PLL_GM_RESET_N_TM_SEL,pll_gm_reset_n is drivne from test registers" "0,1"
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bitfld.long 0x34 23. "O_ANA_PLL_GMBYC_CAP_RESET_N_TM,Forced value of pll_gmbyc_cap_reset_n = 1" "0,1"
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bitfld.long 0x34 22. "O_ANA_PLL_GMBYC_CAP_RESET_N_TM_SEL,pll_gmbyc_cap_reset_n is drivne from test registers" "0,1"
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bitfld.long 0x34 21. "O_ANA_PLL_CP_RESET_N_TM,Forced value of pll_cp_reset_n = 1" "0,1"
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bitfld.long 0x34 20. "O_ANA_PLL_CP_RESET_N_TM_SEL,pll_cp_reset_n is drivne from test registers" "0,1"
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bitfld.long 0x34 19. "O_ANA_PLL_ACCINV_EN_TM,Forced value of pllda_accinv = 1" "0,1"
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bitfld.long 0x34 18. "O_ANA_PLL_ACCINV_EN_TM_SEL,pllda_accinv forced from test registers" "0,1"
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bitfld.long 0x34 17. "O_ANA_PLL_BIAS_EN_TM,Forced value of pllda_bias_en = 1" "0,1"
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bitfld.long 0x34 16. "O_ANA_PLL_BIAS_EN_TM_SEL,pllda_bias_en forced from test registers" "0,1"
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bitfld.long 0x34 15. "O_ANA_PLLDA_EN_DEL_TM,Forced value of pllda_en_del = 1" "0,1"
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bitfld.long 0x34 14. "O_ANA_PLLDA_EN_DEL_TM_SEL,pllda_en_del forced from test registers" "0,1"
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bitfld.long 0x34 13. "O_ANA_PLLDA_EN_TM,Forced value of pllda_en_del = 1" "0,1"
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bitfld.long 0x34 12. "O_ANA_PLLDA_EN_TM_SEL,pllda_en_del forced from test registers" "0,1"
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bitfld.long 0x34 11. "O_ANA_OP_BY2_DIV_RESET_N_TM,Forced valu of pllda_op_by2_div_reset_n = 1" "0,1"
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bitfld.long 0x34 10. "O_ANA_OP_BY2_DIV_RESET_N_TM_SEL,pllda_op_by2_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 9. "O_ANA_OP_DIV_RESET_N_TM,Forced value of pllda_op_div_reset_n = 1" "0,1"
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bitfld.long 0x34 8. "O_ANA_OP_DIV_RESET_N_TM_SEL,pllda_op_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 7. "O_ANA_IP_DIV_RESET_N_TM,Forced value of pllda_ip_div_reset_n = 1" "0,1"
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bitfld.long 0x34 6. "O_ANA_IP_DIV_RESET_N_TM_SEL,pllda_ip_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 5. "O_ANA_FB_DIV_RESET_N_TM,Forced value of pllda_fb_div_reset_n = 1" "0,1"
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bitfld.long 0x34 4. "O_ANA_FB_DIV_RESET_N_TM_SEL,pllda_fb_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 3. "O_ANA_GM_PWM_DIV_RESET_N_TM,Forced value of pllda_gm_pwm_div_reset_n = 1" "0,1"
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bitfld.long 0x34 2. "O_ANA_GM_PWM_DIV_RESET_N_TM_SEL,pllda_gm_pwm_div_reset_n forced from test registers" "0,1"
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bitfld.long 0x34 1. "O_ANA_BYTECLK_DIV_RESET_N_TM,Forced value of pllda_byteclk_div_reset_n = 1" "0,1"
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bitfld.long 0x34 0. "O_ANA_BYTECLK_DIV_RESET_N_TM_SEL,pllda_byteclk_div_reset_n forced from test registers" "0,1"
line.long 0x38 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13"
hexmask.long.word 0x38 22.--31. 1. "O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low"
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bitfld.long 0x38 21. "O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1"
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hexmask.long.word 0x38 11.--20. 1. "O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high"
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bitfld.long 0x38 10. "O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1"
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hexmask.long.word 0x38 0.--9. 1. "UNUSED,RESERVED"
line.long 0x3C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14"
hexmask.long.tbyte 0x3C 13.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x3C 7.--12. "O_ANA_PLL_OP_DIV_TM,forced value for op_div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x3C 6. "O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1"
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bitfld.long 0x3C 1.--5. "O_ANA_PLL_IP_DIV_TM,forced value for ip_div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 0. "O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1"
group.long 0x68++0x23
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT20,CMN_DIG_TBIT20"
hexmask.long.word 0x00 20.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x00 4.--19. 1. "O_CMSMT_REF_CLK_TMR_VALUE,Number of refclk cycles required for clock measurement"
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bitfld.long 0x00 1.--3. "BF_3_1," "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "O_CMSMT_MEASUREMENT_RUN,Enables clock measurement" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT21,CMN_DIG_TBIT21"
hexmask.long 0x04 7.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 6. "O_CMNDA_HSRX_BIST_CLK_SERSYNTH_SWAPDPDN,Enables swapping DP-DN lines for clock bist" "0,1"
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bitfld.long 0x04 5. "O_CMNDA_HSRX_BIST_DATA_SERSYNTH_SWAPDPDN,Enables swapping DP-DN lines for data bist" "0,1"
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bitfld.long 0x04 4. "O_CMNDA_RX_BIST_EN_DEL_TM,forced value of cmnda_rx_bist_en_del = 1" "0,1"
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bitfld.long 0x04 3. "O_CMNDA_RX_BIST_EN_DEL_TM_SEL,cmnda_rx_bist_en_del driven from test registers" "0,1"
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bitfld.long 0x04 2. "O_CMNDA_RX_BIST_EN_TM,forced value of cmnda_rx_bist_en = 1" "0,1"
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bitfld.long 0x04 1. "O_CMNDA_RX_BIST_EN_TM_SEL,cmnda_rx_bist_en driven from test registers" "0,1"
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bitfld.long 0x04 0. "O_RX_DIG_BIST_EN,BIST enable for digital" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT22,BIST_CONFIG_REG1"
bitfld.long 0x08 31. "TM_SKEW_CAL_SYNC_PKT_SEL,To send 'FF as Skew calibration sync packet" "0,1"
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hexmask.long.byte 0x08 23.--30. 1. "TM_SKEW_CAL_SYNC_PKT,desired skew calibration test sync packet"
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bitfld.long 0x08 22. "TM_HS_SYNC_PKT_SEL,To send 'B8 as HS sync packet" "0,1"
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hexmask.long.byte 0x08 14.--21. 1. "TM_HS_SYNC_PKT,desired HS test sync packet"
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hexmask.long.byte 0x08 7.--13. 1. "BIST_LENGTH_OF_DESKEW,Length of deskew sequence In terms of us By default 13us of deskew sequence will be transmitted"
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bitfld.long 0x08 5.--6. "BIST_SEND_CONFIG,Option of configuring what to send in BIST mose To send both deskew and HS data" "0,1,2,3"
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bitfld.long 0x08 1.--4. "BIST_MODE_ENTRY_WAIT_TIME,Once after giving bist_en signal to pattern generator after these many number of BYTE clcok cycles pattern generation will start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0. "BIST_CONTROLLER_EN,Enable BIST controller" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT23,BIST_CONFIG_REG2"
hexmask.long.byte 0x0C 24.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 23. "TM_TX_DATA_HS_SEL,sends single test byte to sersynth which is in <" "0,1"
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hexmask.long.byte 0x0C 15.--22. 1. "TM_TX_DATA_HS,Desired clock patetrn that can be sent using clk_sersynth"
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bitfld.long 0x0C 14. "BIST_TM_BAND_CTRL_SEL,To take the default band control settigns by the design" "0,1"
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bitfld.long 0x0C 9.--13. "BIST_TM_BAND_CTRL,Test mode band control setting to be done for BIST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 8. "TM_SKEW_CAL_PATTERN_SEL,To send 'AA as skew calibration pattern" "0,1"
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hexmask.long.byte 0x0C 0.--7. 1. "TM_SKEW_CAL_PATTERN,desired skew calibration test sequence"
line.long 0x10 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT24,BIST_CONFIG_REG3"
hexmask.long.byte 0x10 24.--31. 1. "BIST_FRM_IDLE_TIME,BIST_FRM_IDLE time is time between the frames"
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hexmask.long.byte 0x10 16.--23. 1. "BIST_PKT_NUM,BIST_PAK_NUM is number of packets that are to be transmitted per frame"
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bitfld.long 0x10 15. "BIST_INF_MODE,run infinite BIST mode" "0,1"
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hexmask.long.byte 0x10 7.--14. 1. "BIST_FRM_NUM,BIST_FRM_NUM is number of frames to be transmitted"
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bitfld.long 0x10 6. "BIST_CLEAR,clear the bist" "0,1"
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bitfld.long 0x10 4.--5. "BIST_PRBS,BIST PRBS MODE 9" "0,1,2,3"
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bitfld.long 0x10 1.--3. "BIST_TEST_MODE,PRBS mode" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x10 0. "UNUSED_0,RESERVED" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT25,BIST_CONFIG_REG4"
hexmask.long.tbyte 0x14 12.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.word 0x14 0.--11. 1. "BIST_RUN_LENGTH,BIST_RUN_LENGTH"
line.long 0x18 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT26,BIST_CONFIG_REG5"
hexmask.long.tbyte 0x18 8.--31. 1. "UNUSED_31_8,RESERVED"
newline
hexmask.long.byte 0x18 0.--7. 1. "BIST_IDLE_TIME,BIST_IDLE_TIME"
line.long 0x1C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT27,BIST_CONFIG_REG6"
hexmask.long.byte 0x1C 24.--31. 1. "BIST_PKT4,BIST_TEST_PAT4"
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hexmask.long.byte 0x1C 16.--23. 1. "BIST_PKT3,BIST_TEST_PAT3"
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hexmask.long.byte 0x1C 8.--15. 1. "BIST_PKT2,BIST_TEST_PAT2"
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hexmask.long.byte 0x1C 0.--7. 1. "BIST_PKT1,BIST_TEST_PAT1"
line.long 0x20 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT28,BIST_CONFIG_REG7"
hexmask.long.byte 0x20 24.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 23. "BIST_TM_CLOCK_LP_DP_SEL,Test mode selection bit to force clcok LP DP buffer to value from design" "0,1"
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bitfld.long 0x20 22. "BIST_TM_CLOCK_LP_DP_VAL,Test mode clock LP DP buffer value is 0" "0,1"
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bitfld.long 0x20 21. "BIST_TM_CLOCK_LP_DN_SEL,Test mode selection bit to force clcok LP DN buffer to value from design" "0,1"
newline
bitfld.long 0x20 20. "BIST_TM_CLOCK_LP_DN_VAL,Test mode clock LP DN buffer value is 0" "0,1"
newline
bitfld.long 0x20 19. "BIST_TM_DATA_LP_DP_SEL,Test mode selection bit to force data LP DP buffer to value from design" "0,1"
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bitfld.long 0x20 18. "BIST_TM_DATA_LP_DP_VAL,Test mode data LP DP buffer value is 0" "0,1"
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bitfld.long 0x20 17. "BIST_TM_DATA_LP_DN_SEL,Test mode selection bit to force data LP DN buffer to value from design" "0,1"
newline
bitfld.long 0x20 16. "BIST_TM_DATA_LP_DN_VAL,Test mode data LP DN buffer value is 0" "0,1"
newline
rbitfld.long 0x20 14.--15. "UNUSED_INT,RESERVED" "0,1,2,3"
newline
bitfld.long 0x20 13. "BIST_LFSR_FREEZE,Reset LFSR contents after every packet or frame" "0,1"
newline
hexmask.long.word 0x20 1.--12. 1. "BIST_ERR_INJ_POINT,BIST_ERR_INJECT_POINT is where to inject the error in the packet"
newline
bitfld.long 0x20 0. "BIST_ERR_INJ_EN,Inject error in the BIST during the packet" "0,1"
group.long 0x94++0x23
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT31,CMN_DIG_TBIT31"
hexmask.long.byte 0x00 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x00 16.--23. 1. "O_RX_SSM_LDO_EN_REF_TMR,Wait time before enabling oscialltor calibration"
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hexmask.long.byte 0x00 8.--15. 1. "O_RX_SSM_LDO_EN_DEL_TMR,wait time before enabling ldo_en_ref"
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hexmask.long.byte 0x00 0.--7. 1. "O_RX_SSM_LDO_EN_TMR,Wait time between ldo_en and ldo_en_del"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT32,CMN_DIG_TBIT32"
hexmask.long.word 0x04 16.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x04 8.--15. 1. "O_RX_SSM_ANA_BIST_ISO_DIS_TMR,Wait time between Bist_en_del and disabling isolation"
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hexmask.long.byte 0x04 0.--7. 1. "O_RX_SSM_ANA_BIST_EN_DEL_TMR,Wait time between Bist_en and bist_en_Del"
line.long 0x08 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT33,CMN_DIG_TBIT33"
bitfld.long 0x08 29.--31. "O_RX_OSC_CAL_TIMER_SCALE_SEL,Timer scale value for vco_count_window" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x08 26.--28. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 14.--25. 1. "O_RX_REFCLK_TIMER_ITER_VALUE_TM,Wait time required before enabling vco count window during iteration in test mode"
newline
bitfld.long 0x08 13. "O_RX_REFCLK_TIMER_ITER_VALUE_TM_SEL,refclk_timer_iter value driven from test register" "0,1"
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hexmask.long.word 0x08 1.--12. 1. "O_RX_REFCLK_TIMER_INIT_VALUE_TM,Wait time required before enabling vco count window in initial phase in test mode"
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bitfld.long 0x08 0. "O_RX_REFCLK_TIMER_INIT_VALUE_TM_SEL,refclk_timer_init value driven from test register" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT34,CMN_DIG_TBIT34"
rbitfld.long 0x0C 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x0C 14.--25. 1. "O_RX_OSC_EN_DEL_TMR_VALUE_TM,Wait time between osc_en and osc_en_del in Test mode"
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bitfld.long 0x0C 13. "O_RX_OSC_EN_DEL_TMR_VALUE_TM_SEL,osc_en_del_tmr driven from test register" "0,1"
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hexmask.long.word 0x0C 1.--12. 1. "O_RX_REFCLK_TIMER_START_VALUE_TM,No of refclk cycles required for single vco count window in test mode"
newline
bitfld.long 0x0C 0. "O_RX_REFCLK_TIMER_START_VALUE_TM_SEL,refclk_timer_start_value driven from test mode" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT35,CMN_DIG_TBIT35"
hexmask.long.byte 0x10 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x10 12.--23. 1. "O_RX_PLLCNT_COUNT_START_VALUE_2,No of PLL clock cycles expected in 25G mode"
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hexmask.long.word 0x10 0.--11. 1. "O_RX_PLLCNT_COUNT_START_VALUE_1,No of PLL clock cycles expected in 15G mode"
line.long 0x14 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT36,CMN_DIG_TBIT36"
hexmask.long.word 0x14 20.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x14 13.--19. 1. "O_RX_TM_VCOCAL_OVRD_VALUE,Vco calcode Test mode value"
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bitfld.long 0x14 12. "O_RX_TM_VCO_CAL_OVERRIDE_EN,Enables test mode overwrite for vco cal code" "0,1"
newline
hexmask.long.byte 0x14 5.--11. 1. "O_RX_OSC_CAL_CODE_START,Starting code for vco calibration"
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bitfld.long 0x14 2.--4. "O_RX_OSC_CAL_CODE_INIT_STEP,Step size for incrmenting vco cal code" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 1. "O_RX_TM_SEL_1P5G_MODE,Select 1p5g mode oscillator clock" "0,1"
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bitfld.long 0x14 0. "O_RX_TM_OSC_CAL_EN,Test mode overwrite for crude osc calibration enable" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT37,"
hexmask.long.tbyte 0x18 15.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x18 14. "O_CMNDA_HSRX_OSC_CALIB_SEL_TM,forced value of hsrx_osc_calib_sel = 1" "0,1"
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bitfld.long 0x18 13. "O_CMNDA_HSRX_OSC_CALIB_SEL_TM_SEL,hsrx_osc_calib_sel driven from test registers" "0,1"
newline
bitfld.long 0x18 12. "O_CMNDA_RX_OSC_DIV_RESET_N_TM,forced value of rx_osc_div_reset_n = 1" "0,1"
newline
bitfld.long 0x18 11. "O_CMNDA_RX_OSC_DIV_RESET_N_TM_SEL,rx_osc_div_reset_n driven from test registers" "0,1"
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bitfld.long 0x18 10. "O_CMNDA_RX_OSC_EN_DEL_TM,forced value of rx_osc_en_del = 1" "0,1"
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bitfld.long 0x18 9. "O_CMNDA_RX_OSC_EN_DEL_TM_SEL,rx_osc_en_del driven from test registers" "0,1"
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bitfld.long 0x18 8. "O_CMNDA_RX_OSC_EN_TM,forced value of rx_osc_en = 1" "0,1"
newline
bitfld.long 0x18 7. "O_CMNDA_RX_OSC_EN_TM_SEL,rx_osc_en driven from test registers" "0,1"
newline
bitfld.long 0x18 6. "O_CMNDA_RX_LDO_BYPASS_TM,Bypass LDO in test mode" "0,1"
newline
bitfld.long 0x18 5. "O_CMNDA_RX_LDO_REF_EN_TM,forced value of rx_ldo_ref_en = 1" "0,1"
newline
bitfld.long 0x18 4. "O_CMNDA_RX_LDO_REF_EN_TM_SEL,rx_ldo_ref_en driven from test registers" "0,1"
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bitfld.long 0x18 3. "O_CMNDA_RX_LDO_EN_DEL_TM,forced value of rx_ldo_en_del = 1" "0,1"
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bitfld.long 0x18 2. "O_CMNDA_RX_LDO_EN_DEL_TM_SEL,rx_ldo_en_del driven from test registers" "0,1"
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bitfld.long 0x18 1. "O_CMNDA_RX_LDO_EN_TM,forced value of rx_ldo_en = 1" "0,1"
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bitfld.long 0x18 0. "O_CMNDA_RX_LDO_EN_TM_SEL,rx_ldo_en driven from test registers" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT38,CMN_DIG_TBIT38"
line.long 0x20 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT39,CMN_DIG_TBIT39"
rgroup.long 0xD8++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT50,BIST_STATUS_REG1"
hexmask.long 0x00 2.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x00 1. "BIST_COMPLETE,BIST is completed" "0,1"
newline
bitfld.long 0x00 0. "BIST_EN_ACK,BIST Controller is enabled" "0,1"
rgroup.long 0xE4++0x07
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT53,CMN_DIG_TBIT53"
hexmask.long.word 0x00 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x00 1.--16. 1. "I_CMSMT_TEST_CLK_CNT_VALUE,Gives clocks cycles count for test clock during measurement"
newline
bitfld.long 0x00 0. "I_CMSMT_MEASUREMENT_DONE,Indicates clock measurement is done" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT54,CMN_DIG_TBIT54"
hexmask.long.word 0x04 20.--31. 1. "I_CMN_PLL_SSM_STATE,Gives CMN PLL ssm state"
newline
hexmask.long.word 0x04 5.--19. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x04 4. "I_DIG_PG_ACK,PSM power good acknowledgement" "0,1"
newline
bitfld.long 0x04 3. "I_PLL_NOT_LOCKED,Indicates PLL is not locked before timeout" "0,1"
newline
bitfld.long 0x04 2. "I_PLL_LOCKED,Indicates PLL is locked" "0,1"
newline
bitfld.long 0x04 1. "I_ANA_RES_COMP_OUT,read value of comaprator output" "0,1"
newline
bitfld.long 0x04 0. "I_CMN_TX_READY,Indiacates cmn is ready for TX IP" "0,1"
rgroup.long 0xF0++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT56,CMN_DIG_TBIT56"
bitfld.long 0x00 28.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 21.--27. 1. "I_CMNDA_RX_OSC_CALCODE,Reads out calib code applied to osicllator"
newline
hexmask.long.word 0x00 11.--20. 1. "I_CMN_RX_SSM_STATE,Gives CMN Rx ssm state"
newline
hexmask.long.word 0x00 2.--10. 1. "I_RX_OSC_CAL_FSM_STATE,Gives Rx osc calib FSM state"
newline
bitfld.long 0x00 1. "I_ANA_RES_COMP_OUT,read value of comaprator output" "0,1"
newline
bitfld.long 0x00 0. "I_CMN_RX_READY,Indicates cmn is ready for RX IP" "0,1"
rgroup.long 0xF8++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT58,CMN_DIG_TBIT58"
hexmask.long 0x00 6.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x00 1.--5. "I_RES_CALIB_CODE,Gives out calibrated resistor calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "I_RES_CALIB_DONE,Indicates resistor calibration is done" "0,1"
rgroup.long 0x108++0x2B
line.long 0x00 "DPHY_RX_VBUS2APB_CLK0_RX_ANA_TBIT2,Analog Test Bit Reg2"
line.long 0x04 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT0,Digital Test Bit Reg0"
hexmask.long 0x04 5.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x04 4. "TD_RSTN,TD is reset - Active low reset control to 'transition_detector_logic'" "0,1"
newline
bitfld.long 0x04 3. "TD_EN,TD is ENABLED - Active high control to enable 'transition_detector_logic'" "0,1"
newline
bitfld.long 0x04 2. "TM_ULPS_ACTIVE_NOT_SEL,Power suspend request in ULPS mode through a test register bypassed with a test value via bit-1 here" "0,1"
newline
bitfld.long 0x04 1. "TM_ULPS_ACTIVE_NOT,When want to control the ULPS mode power suspend request by test register what should be the value" "0,1"
newline
bitfld.long 0x04 0. "FORCE_RX_HS_MODE,Set this bit to force the CRX into HS mode" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT1,Digital Extra Test Bit Reg0"
line.long 0x0C "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT2,Test Mux Register"
hexmask.long.byte 0x0C 25.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x0C 24. "RXDA_LPRX_BIST_EN,LP BIST ENABLED" "0,1"
newline
bitfld.long 0x0C 23. "RXDA_ASYNC_CLK_EN_SEL,rxda_async_clk_en_sel - Controls the selection on clock 'Gate-en' for allowing HS-DDR clock onto Aanlog Interface with options being the funtional mode or from Register-bit" "0,1"
newline
bitfld.long 0x0C 22. "RXDA_ASYNC_CLK_EN,rxda_async_clk_en - 'Gate_en' value to be considered when choosen to take the value through software way when [23] here is set" "0,1"
newline
bitfld.long 0x0C 21. "RXDA_HSRX_BIST_EN_SEL,rxda_hsrx_bist_en_sel - Select signal to choose between functional 'bist_en' from top-level [or] from software register" "0,1"
newline
bitfld.long 0x0C 20. "RXDA_HSRX_BIST_EN,rxda_hsrx_bist_en - value to be considered when choosen to take the value through software way" "0,1"
newline
bitfld.long 0x0C 19. "RXDA_FREQ_BAND_SEL1_SEL,rxda_freq_band_sel1_sel - Select signal to choose between functional 'freq_band' from top-level [or] from software register" "0,1"
newline
bitfld.long 0x0C 15.--18. "RXDA_FREQ_BAND_SEL1,rxda_freq_band_sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 14. "RXDA_FREQ_BAND_SEL2_SEL,rxda_freq_band_sel2_sel - Select signal to choose between functional 'freq_band' from top-level [or] from software register" "0,1"
newline
bitfld.long 0x0C 10.--13. "RXDA_FREQ_BAND_SEL2,rxda_freq_band_sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 9. "RXDA_HS_START_PULSE_SEL,rxda_hs_start_pulse_sel - Select signal to choose between functional 'start_pulse' [or] from software register" "0,1"
newline
bitfld.long 0x0C 8. "RXDA_HS_START_PULSE,rxda_hs_start_pulse - 'start_pulse' value considered when selected to have it via software way" "0,1"
newline
bitfld.long 0x0C 7. "RXDA_HS_STBY_EN_SEL,rxda_hs_stby_en_sel - Select signal to choose between functional 'stby_en' [or] from software register" "0,1"
newline
bitfld.long 0x0C 6. "RXDA_HS_STBY_EN,rxda_hs_stby_en - 'stby_en' value considered when selected to have it via software way" "0,1"
newline
bitfld.long 0x0C 5. "RXDA_LPRXCD_EN_SEL,rxda_lprxcd_en_sel - Select signal to choose between functional 'lprxcd_en' [or] from software register" "0,1"
newline
bitfld.long 0x0C 4. "RXDA_LPRXCD_EN,rxda_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
newline
bitfld.long 0x0C 3. "RXDA_RX_TERM_EN_SEL,rxda_rx_term_en_sel - Select signal to choose between functional 'term_en' [or] from software register" "0,1"
newline
bitfld.long 0x0C 2. "RXDA_RX_TERM_EN,rxda_rx_term_en - 'term_en' value considered when selected to have it via software way" "0,1"
newline
bitfld.long 0x0C 1. "RXDA_ULPS_EN_SEL,rxda_ulps_en_sel - Select signal to choose between functional 'ulps_en' [or] from software register" "0,1"
newline
bitfld.long 0x0C 0. "RXDA_ULPS_EN,rxda_ulps_en - 'ulps_en' value considered when selected to have it via software way" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT3,Digital Extra Test Bit Reg1"
line.long 0x14 "DPHY_RX_VBUS2APB_CLK0_RX_ANA_TBIT3,Analog Read Test Bit Reg3"
line.long 0x18 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT4,Digital Read Test Reg0"
hexmask.long.tbyte 0x18 14.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x18 8.--13. "LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x18 0.--7. 1. "TD_STATUS,Posedge and Negedge transition detect status of LPRX_DP LPRX_DN LPCD_DP LPCD_DN"
line.long 0x1C "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT5,Digital Read Test Bit Reg0"
line.long 0x20 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT6,BIST Status Reg0"
line.long 0x24 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT7,Bist Extra Status Read Reg0"
line.long 0x28 "DPHY_RX_VBUS2APB_CLK0_RX_DIG_TBIT8,Digital Extra Read Reg0"
group.long 0x200++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
newline
bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
newline
bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
newline
bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
newline
bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
newline
bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
newline
bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
newline
hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
newline
bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
newline
rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
newline
bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
newline
bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
newline
bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
newline
rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
newline
hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
newline
bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
newline
hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
newline
bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
newline
bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
newline
bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
newline
bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
newline
bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
newline
bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
newline
bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
newline
bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
newline
hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
newline
bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
newline
bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
newline
hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
newline
bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
newline
bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
newline
bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
newline
bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
newline
bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
newline
bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x274++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x28C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
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bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
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bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x2C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0x300++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
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bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
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bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
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bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
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bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
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bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
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bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
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hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
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bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
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bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
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hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
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bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
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bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
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bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
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bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
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bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x374++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x38C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
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bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
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bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x3C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0x400++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
newline
bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
newline
bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
newline
bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
newline
bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
newline
bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
newline
bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
newline
bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
newline
hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
newline
bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
newline
bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
newline
hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
newline
bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
newline
bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
newline
hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
newline
bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
newline
bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
newline
bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
newline
bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x474++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
newline
hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x48C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
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bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
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bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x4C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0x500++0x6B
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_ANA_TBIT0,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_ANA_TBIT1,ANA_EXTRA_TBIT0"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT0,DIG_TBIT0"
hexmask.long.word 0x08 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 22. "TM_1P5TO2P5G_MODE_SEL,w_tm_1p5to2p5g_mode_sel - Select signal to choose 'mode_en' based on top-level 'bandctrl' input provided [or] from software register" "0,1"
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bitfld.long 0x08 21. "TM_1P5TO2P5G_MODE_EN,w_tm_1p5to2p5g_mode_en - 'mode_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x08 20. "TM_STD_BY,w_tm_std_by - 'tm_std_by' value to be considered when selected to have it via software way Part of control logic to initiate movement of 'calib_ctrl' FSM" "0,1"
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bitfld.long 0x08 19. "TM_STD_BY_SEL,w_tm_std_by_sel - Select signal to choose between functional 'tm_std_by' [or] from software register" "0,1"
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bitfld.long 0x08 18. "TM_TERM_EN,w_tm_term_en - 'tm_term_en' value to be considered when selected to have it via software way Value provided here converges onto 'rxda_rx_term_en' pin on alalog interface" "0,1"
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bitfld.long 0x08 17. "TM_TERM_EN_SEL,w_tm_term_en_sel - Select signal to choose between functional 'term_en_sel' [or] from software register" "0,1"
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bitfld.long 0x08 16. "TM_SETTLE_COUNT_SEL,Test mode settle count selection =" "0,1"
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hexmask.long.byte 0x08 9.--15. 1. "TM_SETTLE_COUNT,Test mode settle count if bit <16> is set - 'settle_count' value to be considered when selected to have it via software way"
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bitfld.long 0x08 5.--8. "SETTLE_COUNT_OFFSET_CORR,Settle count offset correction value that adds up to the internal predifined settle count based on 'BandCtl' which helps in deciding the final 'settle_count' to be observed for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4. "TM_DISABLE_BCLK_PHASE_ALIGN,test mode to disable byte clock phase alignment" "0,1"
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rbitfld.long 0x08 0.--3. "UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT1,DIG_TBIT1"
hexmask.long.tbyte 0x0C 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 9. "TM_ULP_RCV_SEL,w_tm_ulp_rcv_sel - Select signal to choose between functional 'ulp_rcv_en' or a value from software register The effective value converges onto port 'i_ana_ulps_rcv_en' of 'lane_always_on' block at DPHY_RX_VBUS2APB_LANE-level" "0,1"
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bitfld.long 0x0C 8. "TM_ULP_RCV,w_tm_ulp_rcv_en - 'ulp_rcv_en' value considered when selected to have it via software way" "0,1"
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bitfld.long 0x0C 7. "TM_LPRXCD_SEL,w_tm_lprxcd_sel - Select signal to choose the lprxcd's block enable value to analog between the one from 'lane_always_on' or from the software way onto the port 'rxda_lprxcd_en' on Analog interface" "0,1"
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bitfld.long 0x0C 6. "TM_LPRXCD,w_tm_lprxcd_en - 'lprxcd_en' value considered when selected to have it via software way" "0,1"
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rbitfld.long 0x0C 1.--5. "TM_UNUSED_5_1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0. "TM_FORCE_TX_STOP_STATE," "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT2,DIGITAL_EXTRA_TEST_REG0"
line.long 0x14 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT3,preamp_cal_ctrl_reg1"
bitfld.long 0x14 31. "TM_DIAG_CAL_CLOCK_GATE_EN,While running diagnostic calibrations this acts as calibration's clock gate enable Enable = 1" "0,1"
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hexmask.long.word 0x14 18.--30. 1. "TM_UNUSED_30_18,RESERVED"
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bitfld.long 0x14 17. "TM_PREAMP_CAL_ITER_WAIT_TIME_EN,test mode wait time between two codes selection" "0,1"
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hexmask.long.byte 0x14 9.--16. 1. "TM_PREAMP_CAL_ITER_WAIT_TIME,test mode wait time between two codes"
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bitfld.long 0x14 8. "TM_PREAMP_CAL_INIT_WAIT_TIME_EN,test mode initial wait time selection - Select signal to choose between the one from software way or the functional one Functional value gets decided internally based on the 'psm_clock_freq' input to Data-Lane" "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "TM_PREAMP_CAL_INIT_WAIT_TIME,test mode initial wait time - 'init_value' considered when selected to choose it via software way"
line.long 0x18 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT4,preamp_cal_ctrl_reg2"
rbitfld.long 0x18 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "TM_PREAMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x18 25. "TM_PREAMP_ANA_CAL_EN,test mode analog calibration enable" "0,1"
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hexmask.long.byte 0x18 18.--24. 1. "TM_UNUSED_24_18,RESERVED"
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bitfld.long 0x18 15.--17. "TM_PREAMP_CAL_CODE_TUNE,final preamp cal code tune value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 7.--14. 1. "TM_PREAMP_CAL_OVERRIDE_CODE,preamp calibration override code"
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bitfld.long 0x18 6. "TM_PREAMP_CAL_OVERRIDE_EN,preamp calibration code override enable" "0,1"
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bitfld.long 0x18 5. "TM_PREAMP_CAL_RUN_SEL,test mode calibration run selection" "0,1"
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bitfld.long 0x18 4. "TM_PREAMP_CAL_RUN,test mode calibration run" "0,1"
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rbitfld.long 0x18 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT5,dcc_comp_cal_ctrl_reg1"
hexmask.long.word 0x1C 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x1C 17. "TM_DCC_COMP_CAL_ITER_WAIT_TIME_EN,test mode dcc comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x1C 9.--16. 1. "TM_DCC_COMP_CAL_ITER_WAIT_TIME,test mode dcc comp calibration iteration time"
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bitfld.long 0x1C 8. "TM_DCC_COMP_CAL_INIT_WAIT_TIME_EN,test mode dcc comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x1C 0.--7. 1. "TM_DCC_COMP_CAL_INIT_WAIT_TIME,test mode dcc comp calibration initial wait time"
line.long 0x20 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT6,dcc_comp_cal_ctrl_reg2"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_DCC_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x20 19. "TM_DCC_COMP_ANA_CAL_EN,test mode dcc comp cal analog enable" "0,1"
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rbitfld.long 0x20 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 13.--15. "TM_DCC_COMP_CAL_CODE_TUNE,test mode dcc comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 7.--12. "TM_DCC_COMP_CAL_OVERRIDE_CODE,test mode dcc comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 6. "TM_DCC_COMP_CAL_OVERRIDE_EN,test mode dcc comp calibration override code enable" "0,1"
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bitfld.long 0x20 5. "TM_DCC_COMP_CAL_RUN_SEL,dcc comp calibration run selection" "0,1"
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bitfld.long 0x20 4. "TM_DCC_COMP_CAL_RUN,dcc comp calibration test mode run" "0,1"
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rbitfld.long 0x20 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT7,mix_comp_cal_ctrl_reg1"
hexmask.long.word 0x24 18.--31. 1. "TM_UNUSED_31_18,RESERVED"
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bitfld.long 0x24 17. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME_EN,test mode mixer comp calibration itertaion time enable" "0,1"
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hexmask.long.byte 0x24 9.--16. 1. "TM_MIXER_COMP_CAL_ITER_WAIT_TIME,test mode mixer comp calibration iteration time"
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bitfld.long 0x24 8. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME_EN,test mode mixer comp calibration initial wait time enable" "0,1"
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hexmask.long.byte 0x24 0.--7. 1. "TM_MIXER_COMP_CAL_INIT_WAIT_TIME,test mode mixer comp calibration initial wait time"
line.long 0x28 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT8,mix_comp_cal_ctrl_reg2"
hexmask.long.word 0x28 21.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x28 20. "TM_MIXER_COMP_ANA_CAL_EN_SEL,take analog calib en from logic or test reg" "0,1"
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bitfld.long 0x28 19. "TM_MIXER_COMP_ANA_CAL_EN,test mode mixer comp cal analog enable" "0,1"
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rbitfld.long 0x28 16.--18. "TM_UNUSED_18_16,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 13.--15. "TM_MIXER_COMP_CAL_CODE_TUNE,test mode mixer comp calibration code tune value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 7.--12. "TM_MIXER_COMP_CAL_OVERRIDE_CODE,test mode mixer comp calibration code overirde" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 6. "TM_MIXER_COMP_CAL_OVERRIDE_EN,test mode mixer comp calibration override code enable" "0,1"
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bitfld.long 0x28 5. "TM_MIXER_COMP_CAL_RUN_SEL,mixer comp calibration run selection" "0,1"
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bitfld.long 0x28 4. "TM_MIXER_COMP_CAL_RUN,mixer comp calibration test mode run" "0,1"
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rbitfld.long 0x28 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT9,pos_samp_cal_ctrl_reg1"
hexmask.long.word 0x2C 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x2C 8.--15. 1. "TM_POS_SAMP_CAL_ITER_WAIT_TIME,posedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x2C 0.--7. 1. "TM_POS_SAMP_CAL_INIT_WAIT_TIME,posedge sampler calibration initial wait time"
line.long 0x30 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT10,pos_samp_cal_ctrl_reg2"
bitfld.long 0x30 31. "TM_POS_SAMP_CAL_ITER_WAIT_TIME_EN,posedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x30 30. "TM_POS_SAMP_CAL_INIT_WAIT_TIME_EN,posedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x30 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x30 16.--23. 1. "TM_POS_SAMP_MCAL_OVERRIDE_CODE,posedge sampler calibration override mcal_code"
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bitfld.long 0x30 15. "TM_POS_SAMP_MCAL_OVERRIDE_EN,posedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x30 7.--14. 1. "TM_POS_SAMP_PCAL_OVERRIDE_CODE,posedge sampler calibration override pcal_code"
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bitfld.long 0x30 6. "TM_POS_SAMP_PCAL_OVERRIDE_EN,posedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x30 5. "TM_POS_SAMP_CAL_RUN,posedge sampler calibration test mode run" "0,1"
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bitfld.long 0x30 4. "TM_POS_SAMP_CAL_RUN_SEL,posedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x30 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT11,pos_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x34 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x34 9. "TM_POS_SAMP_ANA_CAL_EN_SEL,posedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x34 8. "TM_POS_SAMP_ANA_CAL_EN,posedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x34 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--2. "TM_POS_SAMP_CAL_CODE_TUNE,posedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x38 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT12,neg_samp_cal_ctrl_reg1"
hexmask.long.word 0x38 16.--31. 1. "TM_UNUSED_31_16,RESERVED"
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hexmask.long.byte 0x38 8.--15. 1. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME,negedge sampler calibration ieration time between codes"
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hexmask.long.byte 0x38 0.--7. 1. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME,negedge sampler calibration initial wait time"
line.long 0x3C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT13,neg_samp_cal_ctrl_reg2"
bitfld.long 0x3C 31. "TM_NEG_SAMP_CAL_ITER_WAIT_TIME_EN,negedge sampler calibration test mode iteration wait time enable" "0,1"
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bitfld.long 0x3C 30. "TM_NEG_SAMP_CAL_INIT_WAIT_TIME_EN,negedge sampler calibration test mode initial wait time enable" "0,1"
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rbitfld.long 0x3C 24.--29. "TM_UNUSED_29_24,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x3C 16.--23. 1. "TM_NEG_SAMP_MCAL_OVERRIDE_CODE,negedge sampler calibration override mcal_code"
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bitfld.long 0x3C 15. "TM_NEG_SAMP_MCAL_OVERRIDE_EN,negedge sampler calibration mcal_code override en" "0,1"
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hexmask.long.byte 0x3C 7.--14. 1. "TM_NEG_SAMP_PCAL_OVERRIDE_CODE,negedge sampler calibration override pcal_code"
newline
bitfld.long 0x3C 6. "TM_NEG_SAMP_PCAL_OVERRIDE_EN,negedge sampler calibration pcal_code override en" "0,1"
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bitfld.long 0x3C 5. "TM_NEG_SAMP_CAL_RUN,negedge sampler calibration test mode run" "0,1"
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bitfld.long 0x3C 4. "TM_NEG_SAMP_CAL_RUN_SEL,negedge sampler calibration test mode selection" "0,1"
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rbitfld.long 0x3C 0.--3. "TM_UNUSED_3_0,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT14,neg_samp_cal_ctrl_reg3"
hexmask.long.tbyte 0x40 10.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x40 9. "TM_NEG_SAMP_ANA_CAL_EN_SEL,negedge sampler calibration analog calib enable selection" "0,1"
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bitfld.long 0x40 8. "TM_NEG_SAMP_ANA_CAL_EN,negedge sampler calibration analog calibration enable" "0,1"
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rbitfld.long 0x40 3.--7. "TM_UNUSED_7_3,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--2. "TM_NEG_SAMP_CAL_CODE_TUNE,negedge sampler calibration tune code" "0,1,2,3,4,5,6,7"
line.long 0x44 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT15,skew_cal_fsm_reg1"
rbitfld.long 0x44 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 28. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT,skew calibration analog max satiration test mode enable" "0,1"
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bitfld.long 0x44 27. "TM_SKEW_CAL_ANA_DESKEW_MAX_SAT_SEL,skew calibration analog max satiration selection" "0,1"
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hexmask.long.word 0x44 18.--26. 1. "TM_SKEW_CAL_FPHASE_LONG_WAIT_TIME,skew calibration fast phase long wait time"
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hexmask.long.word 0x44 9.--17. 1. "TM_SKEW_CAL_FPHASE_WAIT_TIME,skew calibration fast phase wait time"
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hexmask.long.word 0x44 0.--8. 1. "TM_SKEW_CAL_TIMER_INIT_COUNT,skew calibration initial wait time"
line.long 0x48 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT16,skew_cal_fsm_reg2"
rbitfld.long 0x48 27.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x48 19.--26. 1. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE,skew calibration delay code test mode max value"
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bitfld.long 0x48 18. "TM_SKEW_CAL_ACC_CODE_MAX_VALUE_SEL,skew calibration max code test reg selection" "0,1"
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hexmask.long.byte 0x48 10.--17. 1. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE,skew calibration delay code test mode min value"
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bitfld.long 0x48 9. "TM_SKEW_CAL_ACC_CODE_MIN_VALUE_SEL,skew calibration min code test reg selection" "0,1"
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hexmask.long.word 0x48 0.--8. 1. "TM_SKEW_CAL_SPHASE_WAIT_TIME,skew calibration slow phase wait time"
line.long 0x4C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT17,skew_cal_fsm_reg3"
hexmask.long.tbyte 0x4C 8.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TM_SKEW_CAL_DESKEW_START_CODE,skew calibration initial start code"
line.long 0x50 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT18,ducy_corr_ctrl_reg1"
hexmask.long.word 0x50 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.word 0x50 9.--17. 1. "TM_DUCY_CORR_TIMER_ITER_COUNT,duty cycle correction iteration wait time specified in this register will be considered when a non-zero value is speci fied here"
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hexmask.long.word 0x50 0.--8. 1. "TM_DUCY_CORR_TIMER_INIT_COUNT,duty cycle correction initial wait time specified in this register will be considered when a non-zero value is speci fied here"
line.long 0x54 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT19,ducy_corr_ctrl_reg2"
hexmask.long.word 0x54 18.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x54 13.--17. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE,duty cycle correction test mode max value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 12. "TM_DUCY_CORR_ACC_CODE_MAX_VALUE_SEL,duty cycle correction test mode max value selection" "0,1"
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bitfld.long 0x54 7.--11. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE,duty cycle correction test mode min value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 6. "TM_DUCY_CORR_ACC_CODE_MIN_VALUE_SEL,duty cycle correction test mode min value selection" "0,1"
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bitfld.long 0x54 1.--5. "TM_DUCY_CORR_ACC_START_CODE,duty cycle correction test mode start code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 0. "TM_DUCY_CORR_ACC_START_CODE_SEL,duty cycle correction test mode start code selection" "0,1"
line.long 0x58 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT20,skew_cal_avg_reg1"
bitfld.long 0x58 31. "TM_ANA_DESKEW_DCC_EN,test mode analog deskew enable" "0,1"
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bitfld.long 0x58 30. "TM_ANA_DESKEW_DCC_EN_SEL,test mode deskew analog enable selection" "0,1"
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bitfld.long 0x58 27.--29. "TM_DCC_CODE_TUNE,duty cycle correction code tune" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 26. "TM_DCC_CODE_OVERRIDE_EN,duty cycle correction code override enable" "0,1"
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bitfld.long 0x58 22.--25. "TM_DCC_CODE_OVERRIDE,duty cycle correction override code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 17.--21. "TM_DESKEW_CODE_TUNE,skew calibration delay line code tune" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16. "TM_DESKEW_CODE_OVERRIDE_EN,skew calibration delay code override enable" "0,1"
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hexmask.long.byte 0x58 9.--15. 1. "TM_DESKEW_CODE_OVERRIDE,skew calibration delay line override code"
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hexmask.long.byte 0x58 1.--8. 1. "TM_PROC_TIMER_LOAD_VAL,skew calibration process time test mode value"
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bitfld.long 0x58 0. "TM_PROC_TIMER_LOAD_VAL_SEL,skew calibration process time test mode value selection" "0,1"
line.long 0x5C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT21,skew_cal_avg_reg2"
hexmask.long.word 0x5C 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x5C 10.--17. 1. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL,delay line code averaging to dcc code averaging wait time"
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bitfld.long 0x5C 9. "TM_AVG2AVG_LENG_TIMER_LOAD_VAL_SEL,delay line code averaging to dcc code averaging wait time selection" "0,1"
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hexmask.long.byte 0x5C 1.--8. 1. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL,total number of dcc codes to be taken for averaging in test mode"
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bitfld.long 0x5C 0. "TM_DCC_ACC_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for test mode number of dcc codes under averaging" "0,1"
line.long 0x60 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT22,skew_cal_avg_reg3"
hexmask.long.word 0x60 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x60 10.--17. 1. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL,after skew calibration is done length of wait timer"
newline
bitfld.long 0x60 9. "TM_DESKEW_DONE_LENG_TIMER_LOAD_VAL_SEL,test mode selection value for length of wait time after deskew" "0,1"
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hexmask.long.byte 0x60 1.--8. 1. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL,number of deskew dealy codes to be taken for averaging"
newline
bitfld.long 0x60 0. "TM_DESKEW_ACC_LENG_TIMER_LOAD_VAL_SEL,tets mode selction for test mode number of delay line codes for averaging" "0,1"
line.long 0x64 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT23,skew_cal_avg_reg4"
hexmask.long.word 0x64 18.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x64 10.--17. 1. "TM_AVG2AVG_RES_TIMER_LOAD_VAL,resolution time of dcc averaging to deskew averaging wait time in test mode"
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bitfld.long 0x64 9. "TM_AVG2AVG_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging to deskew averaging wait time" "0,1"
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hexmask.long.byte 0x64 1.--8. 1. "TM_DCC_ACC_RES_TIMER_LOAD_VAL,resolution time of dcc averaging wait time in test mode"
newline
bitfld.long 0x64 0. "TM_DCC_ACC_RES_TIMER_LOAD_VAL_SEL,test mode selection of resolution time of dcc averaging wait time" "0,1"
line.long 0x68 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT24,skew_cal_avg_reg5"
hexmask.long.word 0x68 18.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x68 10.--17. 1. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL,resolution time of deskew done wait time in test mode"
newline
bitfld.long 0x68 9. "TM_DESKEW_DONE_RES_TIMER_LOAD_VAL_SEL,test mode selcetion of resolution time of deskew done wait time in test mode" "0,1"
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hexmask.long.byte 0x68 1.--8. 1. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL,resolution time of deskew averaging wait time in test mode"
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bitfld.long 0x68 0. "TM_DESKEW_ACC_RES_TIMER_LOAD_VAL_SEL,tets mode selection of resolution time of deskew averaging wait time in test mode" "0,1"
group.long 0x574++0x0F
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT27,bist_config_reg1"
hexmask.long.byte 0x00 24.--31. 1. "TM_IDLE_TIME_LENGTH,BIST_IDLE_TIME"
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hexmask.long.word 0x00 8.--23. 1. "TM_UNUSED_23_8,RESERVED"
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bitfld.long 0x00 5.--7. "TM_TEST_MODE,PRBS mode - when set to '1' PRBS mode is selected" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--4. "TM_PRBS_MODE,BIST PRBS MODE 9 when 0x0" "0,1,2,3"
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rbitfld.long 0x00 2. "TM_UNUSED_2,RESERVED" "0,1"
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bitfld.long 0x00 1. "TM_FREEZE,Freeze the LFSR contents after every packet or frame" "0,1"
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bitfld.long 0x00 0. "TM_BIST_EN,Enable signal for pattern checker" "0,1"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT28,bist_config_reg2"
hexmask.long.byte 0x04 24.--31. 1. "TM_TEST_PAT4,User registers to specify the BIST data4 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 16.--23. 1. "TM_TEST_PAT3,User registers to specify the BIST data3 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 8.--15. 1. "TM_TEST_PAT2,User registers to specify the BIST data2 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
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hexmask.long.byte 0x04 0.--7. 1. "TM_TEST_PAT1,User registers to specify the BIST data1 Based on the deault_mode setting design will consider either of the hard-value from RTL [or] the soft-value provided here"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT29,bist_config_reg3"
rbitfld.long 0x08 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 28. "TM_CLEAR_BIST,Setting this will clear all the BIST related flags and counters" "0,1"
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hexmask.long.word 0x08 12.--27. 1. "TM_UNUSED_27_12,RESERVED"
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hexmask.long.word 0x08 0.--11. 1. "TM_PKT_LENGTH,Based on the default_mode design will consider the run-length from design or the programmed value specified here"
line.long 0x0C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT30,bist_config_reg4"
hexmask.long 0x0C 2.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 1. "TM_LPRX_BIST_EN,LPRX BIST is enbaled - rxda_lprx_bist_en - When '1' LP BIST is enabled" "0,1"
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bitfld.long 0x0C 0. "TM_HSRX_BIST_EN,HSRX BIST is enbaled - rxda_hsrx_bist_en - when '1' HS BIST is enabled" "0,1"
rgroup.long 0x58C++0x33
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_ANA_TBIT2,ANA_TBIT0"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT33,deserialiser_fsm_status"
bitfld.long 0x04 26.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x04 18.--25. 1. "TM_PPI_CUR_STATE,Current State of the SYNC detection FSM during the HS data receive mode or skew calibration mode"
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hexmask.long.word 0x04 8.--17. 1. "TM_CTRL_CUR_STATE,current state status of HS receive FSM"
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hexmask.long.byte 0x04 0.--7. 1. "TM_SYNC_PKT,Status of received SYNC packet"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT34,lp_status"
hexmask.long.word 0x08 19.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x08 14.--18. "TM_LP_RX_CUR_STATE,Current state of LP receiver FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--13. "TM_LP_STATUS,Status of DP DN pins of LPRX LPCD ULPRX respectively" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x08 0.--7. 1. "UNUSED_7_0,RESERVED"
line.long 0x0C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT35,DIGITAL_EXTRA_READ_REG0"
line.long 0x10 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT36,dcc_mixer_comparator_calibration_stat"
hexmask.long.word 0x10 23.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x10 22. "TM_MIX_COMP_ANA_RESP,Mixer comparator analog response" "0,1"
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bitfld.long 0x10 17.--21. "TM_MIX_COMP_CALCODE,Mixer comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "TM_MIX_COMP_CAL_NO_RESP,Mixer comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 15. "TM_MIX_COMP_CAL_DONE,Mixer comparator calibration is done properly" "0,1"
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bitfld.long 0x10 14. "TM_DCC_COMP_ANA_RESP,Duty Cycle Comparator analog response" "0,1"
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bitfld.long 0x10 9.--13. "TM_DCC_COMP_CALCODE,Duty cycle corrector comparator calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8. "TM_DCC_COMP_CAL_NO_RESP,Duty cycle corrector comparator calibration has no response from analog" "0,1"
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bitfld.long 0x10 7. "TM_DCC_COMP_CAL_DONE,Duty cycle corrector comparator calibration is done properly" "0,1"
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bitfld.long 0x10 1.--6. "TM_CALIB_CTRL_CUR_STATE,If struck indicates calibration FSM current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0. "TM_CUR_DRX_CAL_DONE,Current DRX DPHY_RX_VBUS2APB_LANE calibrations are done" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT37,preamp_cal_status_reg1"
bitfld.long 0x14 31. "TM_ANA_RESP_STAT,current analog or test mode response for which calibration is happening" "0,1"
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bitfld.long 0x14 25.--30. "TM_PREAMP_STAT_ANA_CAL_CODE,code going to analog" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 17.--24. 1. "TM_PREAMP_STAT_ANA_FINAL_CAL_CODE,code decided to send to analog before tune"
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bitfld.long 0x14 11.--16. "TM_PREAMP_STAT_NCAL_PREAMP_CODE,calib code in posedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 5.--10. "TM_PREAMP_STAT_PCAL_PREAMP_CODE,calib code in negedge_data run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. "TM_PREAMP_STAT_NCAL_NO_RESP,negedge_data run ha sno response" "0,1"
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bitfld.long 0x14 3. "TM_PREAMP_STAT_PCAL_NO_RESP,posedge_data run ha sno response" "0,1"
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bitfld.long 0x14 2. "TM_PREAMP_STAT_NCAL_DONE,negedge_data cal run is done" "0,1"
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bitfld.long 0x14 1. "TM_PREAMP_STAT_PCAL_DONE,posedge_data cal run is done" "0,1"
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bitfld.long 0x14 0. "TM_PREAMP_STAT_CAL_DONE,preamp calibration is done" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT38,pos_samp_cal_status_reg1"
hexmask.long.word 0x18 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x18 20. "TM_POS_SAMP_STAT_SAMPLTM_POS_SAMP_STAT_CAL_DONE,posedge sampler calibration is done" "0,1"
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hexmask.long.word 0x18 11.--19. 1. "TM_POS_SAMP_STAT_FINAL_CAL_CODE,posedge sampler calbration final code"
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bitfld.long 0x18 10. "TM_POS_SAMP_STAT_CODE_TYPE,code type that is changing for posedge sampler" "0,1"
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hexmask.long.byte 0x18 2.--9. 1. "TM_POS_SAMP_STAT_UP_CAL_CODE,up check calib run code for posedge sampler"
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bitfld.long 0x18 1. "TM_POS_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x18 0. "TM_POS_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x1C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT39,pos_samp_cal_status_reg2"
hexmask.long.byte 0x1C 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x1C 24. "TM_POS_SAMP_ANA_CAL_RESP,test mode status of posedge sampler" "0,1"
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hexmask.long.byte 0x1C 17.--23. 1. "TM_POS_SAMP_STAT_ANA_CAL_MCODE,final m code going to posedge sampler"
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hexmask.long.byte 0x1C 10.--16. 1. "TM_POS_SAMP_STAT_ANA_CAL_PCODE,final p code going to posedge sampler"
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hexmask.long.byte 0x1C 2.--9. 1. "TM_POS_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for posedge sampler"
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bitfld.long 0x1C 1. "TM_POS_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x1C 0. "TM_POS_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x20 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT40,neg_samp_cal_status_reg1"
hexmask.long.word 0x20 21.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x20 20. "TM_NEG_SAMP_STAT_SAMPLTM_NEG_SAMP_STAT_CAL_DONE,negedge sampler calibration is done" "0,1"
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hexmask.long.word 0x20 11.--19. 1. "TM_NEG_SAMP_STAT_FINAL_CAL_CODE,negedge sampler calbration final code"
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bitfld.long 0x20 10. "TM_NEG_SAMP_STAT_CODE_TYPE,code type that is changing for negedge sampler" "0,1"
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hexmask.long.byte 0x20 2.--9. 1. "TM_NEG_SAMP_STAT_UP_CAL_CODE,up check calib run code for negedge sampler"
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bitfld.long 0x20 1. "TM_NEG_SAMP_STAT_NO_UP_CAL_RESP,up check calib run code has no analog response" "0,1"
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bitfld.long 0x20 0. "TM_NEG_SAMP_STAT_UP_CAL_DONE,up check calibration is done" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT41,neg_samp_cal_status_reg2"
hexmask.long.byte 0x24 25.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x24 24. "TM_NEG_SAMP_ANA_CAL_RESP,test mode status of negedge sampler" "0,1"
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hexmask.long.byte 0x24 17.--23. 1. "TM_NEG_SAMP_STAT_ANA_CAL_MCODE,final m code going to negedge sampler"
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hexmask.long.byte 0x24 10.--16. 1. "TM_NEG_SAMP_STAT_ANA_CAL_PCODE,final p code going to negedge sampler"
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hexmask.long.byte 0x24 2.--9. 1. "TM_NEG_SAMP_STAT_DOWN_CAL_CODE,down check calib run code for negedge sampler"
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bitfld.long 0x24 1. "TM_NEG_SAMP_STAT_NO_DOWN_CAL_RESP,down check calib run code has no analog response" "0,1"
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bitfld.long 0x24 0. "TM_NEG_SAMP_STAT_DOWN_CAL_DONE,down check calibration is done" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT42,skew_cal_fsm_status_reg1"
bitfld.long 0x28 29.--31. "UNUSED,RESERVED" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 22.--28. 1. "TM_DESKEW_DCC_CUR_STATE,Duty cycle correction logic current state"
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bitfld.long 0x28 21. "TM_DESKEW_DCC_INIT_MIXER_VALUE,Duty cycle correction initial comparator value" "0,1"
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hexmask.long.byte 0x28 14.--20. 1. "TM_SP_FIRST_TRIP_CODE,slow phase first trip code"
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bitfld.long 0x28 10.--13. "TM_DESKEW_DCC_CUTM_DESKEW_DCC_STATE,current state of the deskew FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 9. "TM_DESKEW_DCC_MAX_SAT_SECOND_TIME,if asserted deskew FSM has gone into max saturation second time" "0,1"
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bitfld.long 0x28 8. "TM_DESKEW_DCC_MAX_SAT_FIRST_TIME,if asserted deskew FSM has got saturated once" "0,1"
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hexmask.long.byte 0x28 1.--7. 1. "TM_DESKEW_DCC_FAST_PHASE_TRIP_CODE,deskew FSM fast phase trip code"
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bitfld.long 0x28 0. "TM_DESKEW_DCC_MIX_COMP_INIT_VALUE,deskew algorithm mixer initial value" "0,1"
line.long 0x2C "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT43,skew_cal_avg_status_reg1"
hexmask.long.byte 0x2C 24.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x2C 17.--23. 1. "TM_DESKEW_DCC_AVG_ANA_SKEW_CAL_CODE,final code going to delay line"
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bitfld.long 0x2C 13.--16. "TM_DESKEW_DCC_AVG_ANA_DCC_CODE,final code going to duty cycle corrector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x2C 6.--12. 1. "TM_DESKEW_DCC_AVG_DESKEW_FINAL_CODE,delay line code before tuning"
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bitfld.long 0x2C 2.--5. "TM_DESKEW_DCC_AVG_DCC_FINAL_CODE,ducy code before tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 1. "TM_DESKEW_DCC_AVG_DONE_DESKEW,skew calibration is done" "0,1"
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bitfld.long 0x2C 0. "TM_DESKEW_DCC_AVG_DONE_DCC,duty cycle correction is done" "0,1"
line.long 0x30 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT44,skew_cal_avg_status_reg2"
hexmask.long.word 0x30 17.--31. 1. "UNUSED,RESERVED"
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hexmask.long.tbyte 0x30 0.--16. 1. "TM_DESKEW_DCC_AVG_CUTM_DESKEW_DCC_AVG_STATE,current state of deskew_dcc_averaging FSM"
rgroup.long 0x5C8++0x0B
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT47,bist_status_reg1"
hexmask.long.word 0x00 16.--31. 1. "W_PAT_CHE_ERROR_COUNT,BIST Pattern checker error count's live status can be obtained by poling this field"
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hexmask.long.word 0x00 0.--15. 1. "W_PAT_CHE_PKT_COUNT,BIST packet count's live status can be obtained by poling this field"
line.long 0x04 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT48,bist_status_reg2"
hexmask.long 0x04 3.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x04 2. "W_BIST_ERROR,Status of HS data path comparision outcome '0' means pass" "0,1"
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bitfld.long 0x04 1. "R_PAT_CHE_SYNC,Informs BIST Pattern checker is not in sync with pattern generator - Check polarity" "0,1"
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bitfld.long 0x04 0. "W_DRX_BIST_PASS,Entire DRX has passed BIST when this bit's status is set" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT49,DIG_BIST_EXTRA_READ_REG0"
group.long 0xB00++0x2B
line.long 0x00 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL"
hexmask.long.tbyte 0x00 10.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x00 5.--9. "BAND_CTL_REG_R,Data Rate [80_100] MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "BAND_CTL_REG_L,Data Rate [80_100] MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG"
hexmask.long.tbyte 0x04 9.--31. 1. "UNUSED,RESERVED"
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hexmask.long.byte 0x04 1.--8. 1. "PSM_CLOCK_FREQ,psm_clock freq value"
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bitfld.long 0x04 0. "PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT2,PHY_PI_PH2_DL_CONFIG"
bitfld.long 0x08 28.--31. "POWER_SW_2_TIME_DL_R_3,power_sw_2_time_dl_r_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 24.--27. "POWER_SW_2_TIME_DL_R_2,power_sw_2_time_dl_r_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "POWER_SW_2_TIME_DL_R_1,power_sw_2_time_dl_r_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "POWER_SW_2_TIME_DL_R_0,power_sw_2_time_dl_r_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 12.--15. "POWER_SW_2_TIME_DL_L_3,power_sw_2_time_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. "POWER_SW_2_TIME_DL_L_2,power_sw_2_time_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. "POWER_SW_2_TIME_DL_L_1,power_sw_2_time_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. "POWER_SW_2_TIME_DL_L_0,power_sw_2_time_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT3,PHY_PI_PH2_CL_CMN_CONFIG"
hexmask.long.tbyte 0x0C 12.--31. 1. "UNUSED,RESERVED"
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bitfld.long 0x0C 8.--11. "POWER_SW_2_TIME_CMN,power_sw_2_time_cmn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 4.--7. "POWER_SW_2_TIME_CL_R,power_sw_2_time_cl_r" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "POWER_SW_2_TIME_CL_L,power_sw_2_time_cl_l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT4,PHY_PI_PH1_DL_CONFIG"
bitfld.long 0x10 28.--31. "POWER_SW_1_TIME_DL_R_3,power_sw_1_time_dl_r_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 24.--27. "POWER_SW_1_TIME_DL_R_2,power_sw_1_time_dl_r_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "POWER_SW_1_TIME_DL_R_1,power_sw_1_time_dl_r_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "POWER_SW_1_TIME_DL_R_0,power_sw_1_time_dl_r_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 12.--15. "POWER_SW_1_TIME_DL_L_3,power_sw_1_time_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "POWER_SW_1_TIME_DL_L_2,power_sw_1_time_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4.--7. "POWER_SW_1_TIME_DL_L_1,power_sw_1_time_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0.--3. "POWER_SW_1_TIME_DL_L_0,power_sw_1_time_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT5,PHY_PI_PH1_CL_CMN_CONFIG"
hexmask.long.tbyte 0x14 12.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x14 8.--11. "POWER_SW_1_TIME_CMN,power_sw_1_time_cmn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 4.--7. "POWER_SW_1_TIME_CL_R,power_sw_1_time_cl_r" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0.--3. "POWER_SW_1_TIME_CL_L,power_sw_1_time_cl_l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT6,PHY_DL_SPARE_LEFT"
hexmask.long.byte 0x18 24.--31. 1. "DTX_L_3_SPARE,dtx_l_3 spare port"
newline
hexmask.long.byte 0x18 16.--23. 1. "DTX_L_2_SPARE,dtx_l_2 spare port"
newline
hexmask.long.byte 0x18 8.--15. 1. "DTX_L_1_SPARE,dtx_l_1 spare port"
newline
hexmask.long.byte 0x18 0.--7. 1. "DTX_L_0_SPARE,dtx_l_0 spare port"
line.long 0x1C "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT7,PHY_DL_SPARE_RIGHT"
hexmask.long.byte 0x1C 24.--31. 1. "DTX_R_3_SPARE,dtx_r_3 spare port"
newline
hexmask.long.byte 0x1C 16.--23. 1. "DTX_R_2_SPARE,dtx_r_2 spare port"
newline
hexmask.long.byte 0x1C 8.--15. 1. "DTX_R_1_SPARE,dtx_r_1 spare port"
newline
hexmask.long.byte 0x1C 0.--7. 1. "DTX_R_0_SPARE,dtx_r_0 spare port"
line.long 0x20 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT8,PHY_CL_CMN_SPARE"
hexmask.long.byte 0x20 24.--31. 1. "UNUSED,RESERVED"
newline
hexmask.long.byte 0x20 16.--23. 1. "CMN_SPARE,cmn spare port"
newline
hexmask.long.byte 0x20 8.--15. 1. "CL_R_SPARE,cl_r spare port"
newline
hexmask.long.byte 0x20 0.--7. 1. "CL_L_SPARE,cl_l spare port"
line.long 0x24 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT9,PHY_PI_CONFIG"
hexmask.long 0x24 2.--31. 1. "UNUSED,RESERVED"
newline
bitfld.long 0x24 1. "PSO_DISABLE_VALUE,pso_disbale value" "0,1"
newline
bitfld.long 0x24 0. "PSO_DISABLE_EN,take pso_diable from tbit" "0,1"
line.long 0x28 "DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT10,DIG_TBIT10"
group.long 0xC00++0x47
line.long 0x00 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_CNTRL,PHY_ISO_CNTRL"
hexmask.long.tbyte 0x00 12.--31. 1. "BF_31_12,"
newline
bitfld.long 0x00 11. "PHY_ISOLATION,when set enables phy_isolation" "0,1"
newline
bitfld.long 0x00 10. "PHY_ISO_CMN,This bit enables the Isolation on Common Lane" "0,1"
newline
bitfld.long 0x00 8.--9. "PHY_ISO_CL,Bit" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "PHY_ISO_DL,Bit"
line.long 0x04 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_RESET,PHY_ISO_RESET"
hexmask.long.tbyte 0x04 11.--31. 1. "BF_31_11,"
newline
bitfld.long 0x04 10. "LANE_RSTB_CMN,Drives the Lane Reset for Common lane_rstb_cmn" "0,1"
newline
bitfld.long 0x04 9. "LANE_RSTB_CL_R,Drives the Right Clock Lane Reset lane_rstb_cl_l" "0,1"
newline
bitfld.long 0x04 8. "LANE_RSTB_CL_L,Drives the Left Clock Lane Reset lane_rstb_cl_l" "0,1"
newline
bitfld.long 0x04 7. "LANE_RSTB_DL_R_3,Drives the Data Lane 3 Right Link Reset lane_rstb_dl_7" "0,1"
newline
bitfld.long 0x04 6. "LANE_RSTB_DL_R_2,Drives the Data Lane 2 Right Link Reset lane_rstb_dl_6" "0,1"
newline
bitfld.long 0x04 5. "LANE_RSTB_DL_R_1,Drives the Data Lane 1 Right Link Reset lane_rstb_dl_5" "0,1"
newline
bitfld.long 0x04 4. "LANE_RSTB_DL_R_0,Drives the Data Lane 0 Right Link Reset lane_rstb_dl_4" "0,1"
newline
bitfld.long 0x04 3. "LANE_RSTB_DL_L_3,Drives the Data Lane 3 Left Link Reset lane_rstb_dl_3" "0,1"
newline
bitfld.long 0x04 2. "LANE_RSTB_DL_L_2,Drives the Data Lane 2 Left Link Reset lane_rstb_dl_2" "0,1"
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bitfld.long 0x04 1. "LANE_RSTB_DL_L_1,Drives the Data Lane 1 Left Link Reset lane_rstb_dl_1" "0,1"
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bitfld.long 0x04 0. "LANE_RSTB_DL_L_0,Drives the Data Lane 0 Left Link Reset lane_rstb_dl_0" "0,1"
line.long 0x08 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_ENABLE,PHY_ISO_ENABLE"
hexmask.long.tbyte 0x08 10.--31. 1. "BF_31_10,"
newline
bitfld.long 0x08 9. "RXENABLECLK_CLK_R,Drives to enable the right clock DPHY_RX_VBUS2APB_LANE TxEnableClk_clk_r" "0,1"
newline
bitfld.long 0x08 8. "RXENABLECLK_CLK_L,Drives to enable the left clock DPHY_RX_VBUS2APB_LANE TxEnableClk_clk_l" "0,1"
newline
bitfld.long 0x08 7. "S_ENABLE_DL_R_3,Enables the Data Lane 3 Right Link M_Enable_dl_7" "0,1"
newline
bitfld.long 0x08 6. "S_ENABLE_DL_R_2,Enables the Data Lane 2 Right Link M_Enable_dl_6" "0,1"
newline
bitfld.long 0x08 5. "S_ENABLE_DL_R_1,Enables the Data Lane 1 Right Link M_Enable_dl_5" "0,1"
newline
bitfld.long 0x08 4. "S_ENABLE_DL_R_0,Enables the Data Lane 0 Right Link M_Enable_dl_4" "0,1"
newline
bitfld.long 0x08 3. "S_ENABLE_DL_L_3,Enables the Data Lane 3 Left Link M_Enable_dl_3" "0,1"
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bitfld.long 0x08 2. "S_ENABLE_DL_L_2,Enables the Data Lane 2 Left Link M_Enable_dl_2" "0,1"
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bitfld.long 0x08 1. "S_ENABLE_DL_L_1,Enables the Data Lane 1 Left Link M_Enable_dl_1" "0,1"
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bitfld.long 0x08 0. "S_ENABLE_DL_L_0,Enables the Data Lane 0 Left Link M_Enable_dl_0" "0,1"
line.long 0x0C "DPHY_RX_VBUS2APB_ISO_PHY_ISO_CMN_CTRL,PHY_ISO_CMN_CTRL"
hexmask.long.tbyte 0x0C 9.--31. 1. "BF_31_9,"
newline
rbitfld.long 0x0C 8. "LANE_READY_CMN,Drives lane_ready_cmn" "0,1"
newline
rbitfld.long 0x0C 7. "O_SUPPLY_IO_PG,I/O supply power is good o_supply_io_pg" "0,1"
newline
rbitfld.long 0x0C 6. "O_SUPPLY_CORE_PG,Core Supply Power is good o_supply_core_pg" "0,1"
newline
rbitfld.long 0x0C 5. "O_CMN_READY,Common ready Indicator o_cmn_ready" "0,1"
newline
bitfld.long 0x0C 2.--4. "IP_CONFIG_CMN,Drives the IP configuration to decide which clock DPHY_RX_VBUS2APB_LANE acts as the master DPHY_RX_VBUS2APB_LANE to all clock lanes ip_config_cmn" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 1. "PSO_CMN,Drives the power shut off for the Common pso_cmn" "0,1"
newline
bitfld.long 0x0C 0. "PSO_DISABLE,Disable power shut off pso_disable" "0,1"
line.long 0x10 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_CL_CNTRL_L,PHY_ISO_CL_CNTRL_L"
hexmask.long 0x10 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x10 6. "S_CLK_SWAPDPDN_CL_L,Drives the value to enable the Swap of DP and DN signals inside the clock DPHY_RX_VBUS2APB_LANE S_Clk_SwapDpDn_cl_l" "0,1"
newline
rbitfld.long 0x10 5. "RXULPSCLKNOT_CL_L,Receives ULPS power state status RxULPSClkNot_cl_l" "0,1"
newline
rbitfld.long 0x10 4. "RXSTOPSTATECLK_CL_L,Receives DPHY_RX_VBUS2APB_LANE state status RxStopStateClk_cl_l" "0,1"
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rbitfld.long 0x10 3. "RXULPSACTIVENOTCLK_CL_L,Receives DPHY_RX_VBUS2APB_LANE ULPS active state status RxULPSActiveNotClk_cl_l" "0,1"
newline
rbitfld.long 0x10 2. "RXCLKACTIVEHSCLK_CL_L,Stores Receiver high speed active RxClkActiveHSClk_cl_l" "0,1"
newline
bitfld.long 0x10 1. "RXENABLECLK_CL_L,Enable the Clock Lane RxEnableClk_cl_l" "0,1"
newline
rbitfld.long 0x10 0. "LANE_READY_CL_L,High speed clock transmission ready lane_ready_cl_l" "0,1"
line.long 0x14 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_CTRL_L0,PHY_ISO_DL_CTRL_L0"
hexmask.long 0x14 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x14 6. "S_CLK_SWAPDPDN_DL_L_0,Drives S_Clk_SwapDpDn_dl_l_0" "0,1"
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bitfld.long 0x14 5. "FORCERXMODE_DL_L_0,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_0" "0,1"
newline
bitfld.long 0x14 4. "S_DATA_SWAPDPDN_DL_L_0,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_0" "0,1"
newline
rbitfld.long 0x14 3. "S_STOPSTATE_DL_L_0,Receives Lane Stop state status S_StopState_dl_l_0" "0,1"
newline
rbitfld.long 0x14 2. "S_ULPSACTIVENOT_DL_L_0,Receives the Turnaround request S_ULPSActiveNot_dl_l_0" "0,1"
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bitfld.long 0x14 1. "S_ENABLE_DL_L_0,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_0" "0,1"
newline
rbitfld.long 0x14 0. "LANE_READY_DL_L_0,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_0" "0,1"
line.long 0x18 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_HS_L0,PHY_ISO_DL_HS_L0"
hexmask.long.tbyte 0x18 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x18 13. "ERRSOTSYNCHS_DL_L_0,Start of transmission error ErrSoTSyncHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 12. "ERRSOTHS_DL_L_0,Start of transmission error ErrSoTHS_dl_l_0" "0,1"
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bitfld.long 0x18 11. "RXSYNCHS_DL_L_0,Stores the high speed receive synchronization RxSyncHS_dl_l_0" "0,1"
newline
bitfld.long 0x18 10. "RXVALIDHS_DL_L_0,High speed data receive data valid RxValidHS_dl_l_0" "0,1"
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bitfld.long 0x18 9. "RXSKEWCALHS_DL_L_0,High speed data receive dksew calibration RxSkewCalHS_dl_l_0" "0,1"
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bitfld.long 0x18 8. "RXACTIVEHS_DL_L_0,Stores the high speed data reception active RxActiveHS_dl_l_0" "0,1"
newline
hexmask.long.byte 0x18 0.--7. 1. "RXDATAHS_DL_L_0,High speed receive data RxDataHS_dl_l_0"
line.long 0x1C "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_RX_ESC_L0,PHY_ISO_DL_RX_ESC_L0"
hexmask.long.word 0x1C 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x1C 17. "S_ERRSYNC_DL_L_0,Control error S_ErrControl_dl_l_0" "0,1"
newline
bitfld.long 0x1C 16. "S_ERRCONTROL_DL_L_0,Control error S_ErrControl_dl_l_0" "0,1"
newline
bitfld.long 0x1C 15. "S_ERRESC_DL_L_0,Escape entry error S_ErrEsc_dl_l_0" "0,1"
newline
bitfld.long 0x1C 11.--14. "S_RXTRIGGERESC_DL_L_0,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 10. "S_RXULPSESC_DL_L_0,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_0" "0,1"
newline
bitfld.long 0x1C 9. "S_RXVALIDESC_DL_L_0,Receive escape mode data present S_RxValidEsc_dl_l_0" "0,1"
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bitfld.long 0x1C 8. "S_RXLPDTESC_DL_L_0,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_0" "0,1"
newline
hexmask.long.byte 0x1C 0.--7. 1. "S_RXDATAESC_DL_L_0,Receive escape mode low power receive data S_RxDataEsc_dl_l_0"
line.long 0x20 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_CTRL_L1,PHY_ISO_DL_CTRL_L1"
hexmask.long 0x20 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x20 6. "S_CLK_SWAPDPDN_DL_L_1,Drives S_Clk_SwapDpDn_dl_l_1" "0,1"
newline
bitfld.long 0x20 5. "FORCERXMODE_DL_L_1,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_1" "0,1"
newline
bitfld.long 0x20 4. "S_DATA_SWAPDPDN_DL_L_1,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_1" "0,1"
newline
rbitfld.long 0x20 3. "S_STOPSTATE_DL_L_1,Receives Lane Stop state status S_StopState_dl_l_1" "0,1"
newline
rbitfld.long 0x20 2. "S_ULPSACTIVENOT_DL_L_1,Receives the Turnaround request S_ULPSActiveNot_dl_l_1" "0,1"
newline
bitfld.long 0x20 1. "S_ENABLE_DL_L_1,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_1" "0,1"
newline
rbitfld.long 0x20 0. "LANE_READY_DL_L_1,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_1" "0,1"
line.long 0x24 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_HS_L1,PHY_ISO_DL_HS_L1"
hexmask.long.tbyte 0x24 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x24 13. "ERRSOTSYNCHS_DL_L_1,Start of transmission error ErrSoTSyncHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 12. "ERRSOTHS_DL_L_1,Start of transmission error ErrSoTHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 11. "RXSYNCHS_DL_L_1,Stores the high speed receive synchronization RxSyncHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 10. "RXVALIDHS_DL_L_1,High speed data receive data valid RxValidHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 9. "RXSKEWCALHS_DL_L_1,High speed data receive dksew calibration RxSkewCalHS_dl_l_1" "0,1"
newline
bitfld.long 0x24 8. "RXACTIVEHS_DL_L_1,Stores the high speed data reception active RxActiveHS_dl_l_1" "0,1"
newline
hexmask.long.byte 0x24 0.--7. 1. "RXDATAHS_DL_L_1,High speed receive data RxDataHS_dl_l_1"
line.long 0x28 "DPHY_RX_VBUS2APB_ISO_PHY_ISO_DL_RX_ESC_L1,PHY_ISO_DL_RX_ESC_L1"
hexmask.long.word 0x28 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x28 17. "S_ERRSYNC_DL_L_1,Control error S_ErrControl_dl_l_1" "0,1"
newline
bitfld.long 0x28 16. "S_ERRCONTROL_DL_L_1,Control error S_ErrControl_dl_l_1" "0,1"
newline
bitfld.long 0x28 15. "S_ERRESC_DL_L_1,Escape entry error S_ErrEsc_dl_l_1" "0,1"
newline
bitfld.long 0x28 11.--14. "S_RXTRIGGERESC_DL_L_1,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 10. "S_RXULPSESC_DL_L_1,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_1" "0,1"
newline
bitfld.long 0x28 9. "S_RXVALIDESC_DL_L_1,Receive escape mode data present S_RxValidEsc_dl_l_1" "0,1"
newline
bitfld.long 0x28 8. "S_RXLPDTESC_DL_L_1,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_1" "0,1"
newline
hexmask.long.byte 0x28 0.--7. 1. "S_RXDATAESC_DL_L_1,Receive escape mode low power receive data S_RxDataEsc_dl_l_1"
line.long 0x2C "DPHY_RX_VBUS2APB_ISO_PHY_ISO_SPARE_1,PHY_ISO_SPARE_1"
line.long 0x30 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_CTRL_L2,PHY_ISO_DL_CTRL_L2"
hexmask.long 0x30 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x30 6. "S_CLK_SWAPDPDN_DL_L_2,Drives S_Clk_SwapDpDn_dl_l_2" "0,1"
newline
bitfld.long 0x30 5. "FORCERXMODE_DL_L_2,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_2" "0,1"
newline
bitfld.long 0x30 4. "S_DATA_SWAPDPDN_DL_L_2,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_2" "0,1"
newline
rbitfld.long 0x30 3. "S_STOPSTATE_DL_L_2,Receives Lane Stop state status S_StopState_dl_l_2" "0,1"
newline
rbitfld.long 0x30 2. "S_ULPSACTIVENOT_DL_L_2,Receives the Turnaround request S_ULPSActiveNot_dl_l_2" "0,1"
newline
bitfld.long 0x30 1. "S_ENABLE_DL_L_2,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_2" "0,1"
newline
rbitfld.long 0x30 0. "LANE_READY_DL_L_2,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_2" "0,1"
line.long 0x34 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_HS_L2,PHY_ISO_DL_HS_L2"
hexmask.long.tbyte 0x34 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x34 13. "ERRSOTSYNCHS_DL_L_2,Start of transmission error ErrSoTSyncHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 12. "ERRSOTHS_DL_L_2,Start of transmission error ErrSoTHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 11. "RXSYNCHS_DL_L_2,Stores the high speed receive synchronization RxSyncHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 10. "RXVALIDHS_DL_L_2,High speed data receive data valid RxValidHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 9. "RXSKEWCALHS_DL_L_2,High speed data receive dksew calibration RxSkewCalHS_dl_l_2" "0,1"
newline
bitfld.long 0x34 8. "RXACTIVEHS_DL_L_2,Stores the high speed data reception active RxActiveHS_dl_l_2" "0,1"
newline
hexmask.long.byte 0x34 0.--7. 1. "RXDATAHS_DL_L_2,High speed receive data RxDataHS_dl_l_2"
line.long 0x38 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_RX_ESC_L2,PHY_ISO_DL_RX_ESC_L2"
hexmask.long.word 0x38 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x38 17. "S_ERRSYNC_DL_L_2,Control error S_ErrControl_dl_r_2" "0,1"
newline
bitfld.long 0x38 16. "S_ERRCONTROL_DL_L_2,Control error S_ErrControl_dl_l_2" "0,1"
newline
bitfld.long 0x38 15. "S_ERRESC_DL_L_2,Escape entry error S_ErrEsc_dl_l_2" "0,1"
newline
bitfld.long 0x38 11.--14. "S_RXTRIGGERESC_DL_L_2,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 10. "S_RXULPSESC_DL_L_2,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_2" "0,1"
newline
bitfld.long 0x38 9. "S_RXVALIDESC_DL_L_2,Receive escape mode data present S_RxValidEsc_dl_l_2" "0,1"
newline
bitfld.long 0x38 8. "S_RXLPDTESC_DL_L_2,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_2" "0,1"
newline
hexmask.long.byte 0x38 0.--7. 1. "S_RXDATAESC_DL_L_2,Receive escape mode low power receive data S_RxDataEsc_dl_l_2"
line.long 0x3C "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_CTRL_L3,PHY_ISO_DL_CTRL_L3"
hexmask.long 0x3C 7.--31. 1. "BF_31_7,"
newline
bitfld.long 0x3C 6. "S_CLK_SWAPDPDN_DL_L_3,Drives S_Clk_SwapDpDn_dl_l_0" "0,1"
newline
bitfld.long 0x3C 5. "FORCERXMODE_DL_L_3,Forces the DPHY_RX_VBUS2APB_LANE in Receiver mode ForceRxMode_dl_l_3" "0,1"
newline
bitfld.long 0x3C 4. "S_DATA_SWAPDPDN_DL_L_3,Swaps the tx_p and tx_m differential pins S_Data_SwapDpDn_dl_l_3" "0,1"
newline
rbitfld.long 0x3C 3. "S_STOPSTATE_DL_L_3,Receives Lane Stop state status S_StopState_dl_l_3" "0,1"
newline
rbitfld.long 0x3C 2. "S_ULPSACTIVENOT_DL_L_3,Receives the Turnaround request S_ULPSActiveNot_dl_l_3" "0,1"
newline
bitfld.long 0x3C 1. "S_ENABLE_DL_L_3,Enables the data DPHY_RX_VBUS2APB_LANE S_Enable_dl_l_3" "0,1"
newline
rbitfld.long 0x3C 0. "LANE_READY_DL_L_3,High Speed data DPHY_RX_VBUS2APB_LANE ready lane_ready_dl_l_3" "0,1"
line.long 0x40 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_HS_L3,PHY_ISO_DL_HS_L3"
hexmask.long.tbyte 0x40 14.--31. 1. "BF_31_14,"
newline
bitfld.long 0x40 13. "ERRSOTSYNCHS_DL_L_3,Start of transmission error ErrSoTSyncHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 12. "ERRSOTHS_DL_L_3,Start of transmission error ErrSoTHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 11. "RXSYNCHS_DL_L_3,Stores the high speed receive synchronization RxSyncHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 10. "RXVALIDHS_DL_L_3,High speed data receive data valid RxValidHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 9. "RXSKEWCALHS_DL_L_3,High speed data receive dksew calibration RxSkewCalHS_dl_l_3" "0,1"
newline
bitfld.long 0x40 8. "RXACTIVEHS_DL_L_3,Stores the high speed data reception active RxActiveHS_dl_l_3" "0,1"
newline
hexmask.long.byte 0x40 0.--7. 1. "RXDATAHS_DL_L_3,High speed receive data RxDataHS_dl_l_3"
line.long 0x44 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_DL_RX_ESC_L3,PHY_ISO_DL_RX_ESC_L3"
hexmask.long.word 0x44 18.--31. 1. "BF_31_18,"
newline
bitfld.long 0x44 17. "S_ERRSYNC_DL_L_3,Control error S_ErrSync_dl_l_3" "0,1"
newline
bitfld.long 0x44 16. "S_ERRCONTROL_DL_L_3,Control error S_ErrControl_dl_l_3" "0,1"
newline
bitfld.long 0x44 15. "S_ERRESC_DL_L_3,Escape entry error S_ErrEsc_dl_l_3" "0,1"
newline
bitfld.long 0x44 11.--14. "S_RXTRIGGERESC_DL_L_3,Receive escape mode lower power trigger state S_RxTriggerEsc_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x44 10. "S_RXULPSESC_DL_L_3,Receive escape mode ultra low power state S_RxULPSEsc_dl_l_3" "0,1"
newline
bitfld.long 0x44 9. "S_RXVALIDESC_DL_L_3,Receive escape mode data present S_RxValidEsc_dl_l_3" "0,1"
newline
bitfld.long 0x44 8. "S_RXLPDTESC_DL_L_3,Receive escape mode low power data indicator S_RxLPDTEsc_dl_l_3" "0,1"
newline
hexmask.long.byte 0x44 0.--7. 1. "S_RXDATAESC_DL_L_3,Receive escape mode low power receive data S_RxDataEsc_dl_l_3"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
rgroup.long ($2+0xC48)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_ISO_LDD_PHY_ISO_RX_SPARE_$1,PHY_ISO_RX_SPARE_1"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x5D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x5C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x584)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x56C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL3_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x4D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x4C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x484)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x46C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL2_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x3D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x3C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x384)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x36C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL1_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 50. 51. )(list 0x00 0x04 )
rgroup.long ($2+0x2D4)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIG_EXTRA_READ_REG1"
repeat.end
repeat 2. (list 45. 46. )(list 0x00 0x04 )
rgroup.long ($2+0x2C0)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIGITAL_CALIB_EXTRA_READ_REG0"
repeat.end
repeat 2. (list 31. 32. )(list 0x00 0x04 )
rgroup.long ($2+0x284)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIGITAL_EXTRA_TEST_REG1"
repeat.end
repeat 2. (list 25. 26. )(list 0x00 0x04 )
rgroup.long ($2+0x26C)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_DL0_RX_DIG_TBIT$1,DIGITAL_EXTRA_CALIB_REG0"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x100)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CLK0_RX_ANA_TBIT$1,Analog Test Bit Reg0"
repeat.end
repeat 4. (list 0. 1. 2. 4. )(list 0x00 0x04 0x08 0x10 )
group.long ($2+0x00)++0x03
line.long 0x00 "DPHY_RX_VBUS2APB_CMN0_CMN_ANA_TBIT$1,CMN_ANA_TBIT0"
repeat.end
tree.end
tree.end
tree "DPHY_TX"
tree "DPHY_TX0"
base ad:0x4480000
rgroup.long 0xF00++0x17
line.long 0x00 "DPHY_TX_MOD_VER,The Module and Version Register identifies the module identifier and revision of the WIZ16B8M4CDT module"
bitfld.long 0x00 30.--31. "SCHEME,Module Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Module Business Unit" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,WIZ16B8M4CDT module ID"
bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DPHY_TX_PLL_CTRL,Sets the PLL info"
bitfld.long 0x04 31. "PLL_LOCK,Signal to indicate that PLL has got locked" "PLL not yet locked,PLL locked to required frequency"
bitfld.long 0x04 30. "PSO_DISABLE,Disables the ability to switch off the analog switched power islands in the lane when in the ultra-low power state" "0,1"
newline
bitfld.long 0x04 29. "PLL_PSO,Power Shut Off signal for PLL" "PLL power ON,PLL shutoff"
bitfld.long 0x04 28. "PLL_PD,Power down signal for PLL (Does not switch off the PLL supply)" "PLL is active,PLL is powered down"
newline
hexmask.long.word 0x04 16.--25. 1. "PLL_FBDIV,DPHY TX PLL VCO Feedback Divider ratio"
bitfld.long 0x04 8.--13. "PLL_OPDIV,DPHY TX PLL OUTCLK Divider ratio.<BR> 6'h" "?,Div by 1 2.5 Gbps - 1.25 Gbps<BR>..,Div by 2 1.24 Gbps - 630 Mbps<BR>..,?,Div by 4 620 Mbps - 320 Mbps<BR> 6'h,?,?,?,Div by 8 310 Mbps - 160 Mbps<BR> 6'h,?,Div by 16 150 Mbps - 80 Mbps,?..."
newline
bitfld.long 0x04 0.--4. "PLL_IPDIV,DPHY TX PLL REFCLK Input Divider ratio.<BR> 5'h" "?,Div by 1 9.6 MHz - <19.2..,Div by 2 19.2 MHz - <38.4..,?,Div by 4 38.4 MHz - < 76.8..,?,?,?,Div by 8 76.8 MHz - < 150 MHz,?..."
line.long 0x08 "DPHY_TX_STATUS,The register reports of the DPHYTS sub module"
bitfld.long 0x08 31. "O_CMN_READY,System Should check this during Power up Initialisation" "0,1"
bitfld.long 0x08 2. "O_SUPPLY_CORE_PG,The indicates the core supply is good" "0,1"
newline
bitfld.long 0x08 1. "O_SUPPLY_IO_PG,The indicates the IO supply is good" "0,1"
line.long 0x0C "DPHY_TX_RST_CTRL,Sets the RST info"
bitfld.long 0x0C 31. "LANE_RSTB_CMN,DPHY System Reset for Common Module - required to be released after APB register programming See DPHY PMA specification for details of DPHY power up sequence" "0,1"
line.long 0x10 "DPHY_TX_PSM_FREQ,The PSM Frequency register configures the so that it knows hoe fast the PSM clock is"
hexmask.long.byte 0x10 0.--7. 1. "PSM_CLOCK_FREQ,Static value based on System PSM clock frequency"
line.long 0x14 "DPHY_TX_IPCONFIG,IP Config"
bitfld.long 0x14 31. "PSO_CMN,Power Shutoff signal for CMN" "CMN is power ON,CMN is power OFF"
bitfld.long 0x14 0.--2. "IPCONFIG_CMN,This signal decides which clock lane acts as master clock lane to all data lanes" "Left RX clk lane provides clock to all left and..,Left RX clk lane provides clock to all right..,Right RX clk lane provides clock to all right..,Right RX clk lane provides clock to all left and..,?..."
group.long 0xFF8++0x07
line.long 0x00 "DPHY_TX_PLLRES,The PLL Reserved register is not being used currently"
hexmask.long.byte 0x00 0.--7. 1. "PLLREFSEL_CMN,PLL frequency range"
line.long 0x04 "DPHY_TX_DIAG_TEST,The Diagnostic Test Register allows the system to validate the read and write of all data bits"
tree.end
tree.end
tree "DRU"
tree "COMPUTE_CLUSTER0_MMR_DRU_MMR_CFG_DRU"
base ad:0x6D000000
rgroup.quad 0x00++0x0F
line.quad 0x00 "DRU_PID,Peripheral ID Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad 0x00 0.--31. 1. "REVISION,PID Revision"
line.quad 0x08 "DRU_CAPABILITIES,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions"
hexmask.quad.tbyte 0x08 47.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 43.--46. "SECTR,Maximum second TR function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 39.--42. "DFMT,Maximum data reformatting function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 35.--38. "ELTYPE,Maximum element type value that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x08 32.--34. "AMODE,The maximum AMODE that is supported" "0,1,2,3,4,5,6,7"
hexmask.quad.word 0x08 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features"
bitfld.quad 0x08 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1"
bitfld.quad 0x08 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1"
newline
bitfld.quad 0x08 17. "EOL,EOL Field is supported" "0,1"
bitfld.quad 0x08 16. "TRSTATIC,STATIC Field is supported" "0,1"
bitfld.quad 0x08 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.quad 0x08 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.quad 0x08 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.quad 0x08 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.quad 0x08 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.quad 0x08 10. "TYPE10,Type 10 TR is supported" "0,1"
newline
bitfld.quad 0x08 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.quad 0x08 8. "TYPE8,Type 8 TR is supported" "0,1"
bitfld.quad 0x08 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.quad 0x08 6. "TYPE6,Type 6 TR is supported" "0,1"
newline
bitfld.quad 0x08 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.quad 0x08 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.quad 0x08 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.quad 0x08 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.quad 0x08 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.quad 0x08 0. "TYPE0,Type 0 TR is supported" "0,1"
group.quad 0x4000++0x07
line.quad 0x00 "DRU_SHARED_EVT_SET,DRU Shared Event Set Register"
hexmask.quad 0x00 1.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 0. "PROT_ERR,Set the protocol error event" "0,1"
group.quad 0x4040++0x07
line.quad 0x00 "DRU_COMP_EVT_SET0,DRU Completion Event Set Register"
bitfld.quad 0x00 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1"
newline
bitfld.quad 0x00 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1"
bitfld.quad 0x00 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1"
newline
bitfld.quad 0x00 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1"
bitfld.quad 0x00 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1"
newline
bitfld.quad 0x00 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1"
bitfld.quad 0x00 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1"
newline
bitfld.quad 0x00 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1"
group.quad 0x4080++0x07
line.quad 0x00 "DRU_ERR_EVT_SET0,DRU Error Event Set Register"
bitfld.quad 0x00 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1"
bitfld.quad 0x00 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1"
bitfld.quad 0x00 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1"
bitfld.quad 0x00 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1"
newline
bitfld.quad 0x00 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1"
bitfld.quad 0x00 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1"
bitfld.quad 0x00 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1"
bitfld.quad 0x00 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1"
bitfld.quad 0x00 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1"
bitfld.quad 0x00 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1"
bitfld.quad 0x00 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1"
newline
bitfld.quad 0x00 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1"
bitfld.quad 0x00 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1"
bitfld.quad 0x00 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1"
bitfld.quad 0x00 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1"
bitfld.quad 0x00 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1"
bitfld.quad 0x00 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1"
bitfld.quad 0x00 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1"
newline
bitfld.quad 0x00 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1"
bitfld.quad 0x00 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1"
bitfld.quad 0x00 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1"
bitfld.quad 0x00 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1"
bitfld.quad 0x00 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1"
bitfld.quad 0x00 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1"
bitfld.quad 0x00 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1"
newline
bitfld.quad 0x00 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1"
bitfld.quad 0x00 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1"
bitfld.quad 0x00 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1"
bitfld.quad 0x00 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1"
group.quad 0x40C0++0x07
line.quad 0x00 "DRU_LOCAL_EVT_SET0,DRU Local Event Set Register"
bitfld.quad 0x00 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1"
newline
bitfld.quad 0x00 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1"
bitfld.quad 0x00 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1"
newline
bitfld.quad 0x00 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1"
bitfld.quad 0x00 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1"
newline
bitfld.quad 0x00 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1"
bitfld.quad 0x00 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1"
newline
bitfld.quad 0x00 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1"
group.quad 0x8000++0x07
line.quad 0x00 "DRU_CFG_y,Configuration Register for Queue 'y' Offset = 8000h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x00 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands"
hexmask.quad.byte 0x00 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands"
bitfld.quad 0x00 8.--10. "QOS,This configures the QoS for Queue 'y'" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 4.--7. "ORDERID,This configures the Order ID for Queue 'y'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0.--2. "PRI,This configures the priority for Queue 'y'" "0,1,2,3,4,5,6,7"
rgroup.quad 0x8040++0x07
line.quad 0x00 "DRU_STATUS_y,Status Register for Queue 'y' Offset = 8040h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 36.--63. 1. "RSVD,Reserved"
hexmask.quad.word 0x00 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 9.--17. 1. "WR_TOTAL,This is the channel that the write half is currently working on"
newline
hexmask.quad.word 0x00 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on"
group.quad 0x40000++0x07
line.quad 0x00 "DRU_CFG_j,Channel Configuration Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 31. "PAUSE_ON_ERR,Pause on Error" "0,1"
bitfld.quad 0x00 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC.0 = The1 = The TR will be received through PSI-L" "0,1"
rbitfld.quad 0x00 16.--18. "CHAN_TYPE,This field states the TR type that is being used along with CHAN_TYPE_OWNER field make up the 4-bit CHAN_TYPE for an UTC" "0,1,2,3,4,5,6,7"
group.quad 0x40020++0x07
line.quad 0x00 "DRU_CHOES0_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.quad 0x00 16.--63. 1. "RSVD,Reserved"
hexmask.quad.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.quad 0x40060++0x07
line.quad 0x00 "DRU_CHST_SCHED_j,Channel Static Scheduler Config Register Offset = 40060h + (j * 100h); where j = 0h to 1Fh"
bitfld.quad 0x00 0.--2. "QUEUE,Thus is the queue number that is written" "0,1,2,3,4,5,6,7"
group.quad 0x60000++0x1F
line.quad 0x00 "DRU_CHRT_CTL_j,The channel realtime control register contains real-time cotrol and status information for the DMA Channel"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 31. "ENABLE,This field enables or disables the channel" "0,1"
bitfld.quad 0x00 30. "TEARDOWN,Channel teardown.Setting this bit will request the channel to be torn down" "0,1"
bitfld.quad 0x00 29. "PAUSE,Channel pause.Setting this bit will request the channel to pause processing at the next packet boundary" "0,1"
line.quad 0x08 "DRU_CHRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
hexmask.quad 0x08 3.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
bitfld.quad 0x08 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
bitfld.quad 0x08 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
line.quad 0x10 "DRU_CHRT_STATUS_DET_j,The channel status details Offset = 60010h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.byte 0x10 8.--15. 1. "CMD_ID,The command id of the TR that had an error"
bitfld.quad 0x10 4.--7. "INFO,The information of the type of status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x10 0.--3. "STATUS_TYPE,The type of error that occured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x18 "DRU_CHRT_STATUS_CNT_j,The channel count details Offset = 60018h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x18 48.--63. 1. "ICNT3,Value of outermost count when error occurred"
hexmask.quad.word 0x18 32.--47. 1. "ICNT2,Value of second outermost count when error occurred"
hexmask.quad.word 0x18 16.--31. 1. "ICNT1,The value of the second innermost count when error occurred"
hexmask.quad.word 0x18 0.--15. 1. "ICNT0,The value of the innermost count when error occurred"
group.quad 0x80000++0x7F
line.quad 0x00 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD0_1_j,The first TR submission word Offset = 80000h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x00 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x00 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x00 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x08 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD2_3_j,The second TR submission word Offset = 80008h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x08 48.--63. 1. "RSVD,"
hexmask.quad 0x08 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x10 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD4_5_j,The third TR submission word Offset = 80010h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x10 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x18 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD6_7_j,The fourth TR submission word Offset = 80018h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x18 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x18 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x20 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD8_9_j,The fifth TR submission word Offset = 80020h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x28 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD10_11_j,The sixth TR submission word Offset = 80028h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x28 48.--63. 1. "RSVD,"
hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x30 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD12_13_j,The seventh TR submission word Offset = 80030h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x38 "DRU_ATOMIC_SUBMIT_CURR_TR_WORD14_15_j,The eight TR submission word Offset = 80038h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
line.quad 0x40 "DRU_NEXT_TR_WORD0_1_j_k,The first TR submission word Offset = 80040h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x40 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x40 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x40 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x48 "DRU_NEXT_TR_WORD2_3_j_k,The second TR submission word Offset = 80048h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x48 48.--63. 1. "RSVD,"
hexmask.quad 0x48 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x50 "DRU_NEXT_TR_WORD4_5_j_k,The third TR submission word Offset = 80050h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x50 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x50 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x50 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x58 "DRU_NEXT_TR_WORD6_7_j_k,The fourth TR submission word Offset = 80058h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x58 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x58 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x60 "DRU_NEXT_TR_WORD8_9_j_k,The fifth TR submission word Offset = 80060h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x60 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x60 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x68 "DRU_NEXT_TR_WORD10_11_j_k,The sixth TR submission word Offset = 80068h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x68 48.--63. 1. "RSVD,"
hexmask.quad 0x68 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x70 "DRU_NEXT_TR_WORD12_13_j_k,The seventh TR submission word Offset = 80070h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x70 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x70 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x78 "DRU_NEXT_TR_WORD14_15_j_k,The eight TR submission word Offset = 80078h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x78 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x78 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x78 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x78 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
group.quad 0xA0000++0x3F
line.quad 0x00 "DRU_SUBMIT_WORD0_1_j_k,The first TR submission word Offset = A0000h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x00 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x00 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x00 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x08 "DRU_SUBMIT_WORD2_3_j_k,The second TR submission word Offset = A0008h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x08 48.--63. 1. "RSVD,"
hexmask.quad 0x08 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x10 "DRU_SUBMIT_WORD4_5_j_k,The third TR submission word Offset = A0010h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x10 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x18 "DRU_SUBMIT_WORD6_7_j_k,The fourth TR submission word Offset = A0018h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x18 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x18 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x20 "DRU_SUBMIT_WORD8_9_j_k,The fifth TR submission word Offset = A0020h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x28 "DRU_SUBMIT_WORD10_11_j_k,The sixth TR submission word Offset = A0028h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x28 48.--63. 1. "RSVD,"
hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x30 "DRU_SUBMIT_WORD12_13_j_k,The seventh TR submission word Offset = A0030h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x38 "DRU_SUBMIT_WORD14_15_j_k,The eight TR submission word Offset = A0038h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
rgroup.quad 0xE0000++0x07
line.quad 0x00 "DRU_CAUSE_y,Offset = E0000h + (y * 8h); where y = 0h to 1h"
bitfld.quad 0x00 63. "R_ERR15,Masked error bit for Tx channel 16*y+15" "0,1"
bitfld.quad 0x00 62. "R_PEND15,Masked completion ring pending bit for Rx channel 16*y+15" "0,1"
bitfld.quad 0x00 61. "T_ERR15,Masked error bit for Tx channel 16*y+15" "0,1"
bitfld.quad 0x00 60. "T_PEND15,Masked completion ring pending bit for Tx channel 16*y+15" "0,1"
newline
bitfld.quad 0x00 59. "R_ERR14,Masked error bit for Tx channel 16*y+14" "0,1"
bitfld.quad 0x00 58. "R_PEND14,Masked completion ring pending bit for Rx channel 16*y+14" "0,1"
bitfld.quad 0x00 57. "T_ERR14,Masked error bit for Tx channel 16*y+14" "0,1"
bitfld.quad 0x00 56. "T_PEND14,Masked completion ring pending bit for Tx channel 16*y+14" "0,1"
newline
bitfld.quad 0x00 55. "R_ERR13,Masked error bit for Tx channel 16*y+13" "0,1"
bitfld.quad 0x00 54. "R_PEND13,Masked completion ring pending bit for Rx channel 16*y+13" "0,1"
bitfld.quad 0x00 53. "T_ERR13,Masked error bit for Tx channel 16*y+13" "0,1"
bitfld.quad 0x00 52. "T_PEND13,Masked completion ring pending bit for Tx channel 16*y+13" "0,1"
newline
bitfld.quad 0x00 51. "R_ERR12,Masked error bit for Tx channel 16*y+12" "0,1"
bitfld.quad 0x00 50. "R_PEND12,Masked completion ring pending bit for Rx channel 16*y+12" "0,1"
bitfld.quad 0x00 49. "T_ERR12,Masked error bit for Tx channel 16*y+12" "0,1"
bitfld.quad 0x00 48. "T_PEND12,Masked completion ring pending bit for Tx channel 16*y+12" "0,1"
newline
bitfld.quad 0x00 47. "R_ERR11,Masked error bit for Tx channel 16*y+11" "0,1"
bitfld.quad 0x00 46. "R_PEND11,Masked completion ring pending bit for Rx channel 16*y+11" "0,1"
bitfld.quad 0x00 45. "T_ERR11,Masked error bit for Tx channel 16*y+11" "0,1"
bitfld.quad 0x00 44. "T_PEND11,Masked completion ring pending bit for Tx channel 16*y+11" "0,1"
newline
bitfld.quad 0x00 43. "R_ERR10,Masked error bit for Tx channel 16*y+10" "0,1"
bitfld.quad 0x00 42. "R_PEND10,Masked completion ring pending bit for Rx channel 16*y+10" "0,1"
bitfld.quad 0x00 41. "T_ERR10,Masked error bit for Tx channel 16*y+10" "0,1"
bitfld.quad 0x00 40. "T_PEND10,Masked completion ring pending bit for Tx channel 16*y+10" "0,1"
newline
bitfld.quad 0x00 39. "R_ERR9,Masked error bit for Tx channel 16*y+9" "0,1"
bitfld.quad 0x00 38. "R_PEND9,Masked completion ring pending bit for Rx channel 16*y+9" "0,1"
bitfld.quad 0x00 37. "T_ERR9,Masked error bit for Tx channel 16*y+9" "0,1"
bitfld.quad 0x00 36. "T_PEND9,Masked completion ring pending bit for Tx channel 16*y+9" "0,1"
newline
bitfld.quad 0x00 35. "R_ERR8,Masked error bit for Tx channel 16*y+8" "0,1"
bitfld.quad 0x00 34. "R_PEND8,Masked completion ring pending bit for Rx channel 16*y+8" "0,1"
bitfld.quad 0x00 33. "T_ERR8,Masked error bit for Tx channel 16*y+8" "0,1"
bitfld.quad 0x00 32. "T_PEND8,Masked completion ring pending bit for Tx channel 16*y+8" "0,1"
newline
bitfld.quad 0x00 31. "R_ERR7,Masked error bit for Tx channel 16*y+7" "0,1"
bitfld.quad 0x00 30. "R_PEND7,Masked completion ring pending bit for Rx channel 16*y+7" "0,1"
bitfld.quad 0x00 29. "T_ERR7,Masked error bit for Tx channel 16*y+7" "0,1"
bitfld.quad 0x00 28. "T_PEND7,Masked completion ring pending bit for Tx channel 16*y+7" "0,1"
newline
bitfld.quad 0x00 27. "R_ERR6,Masked error bit for Tx channel 16*y+6" "0,1"
bitfld.quad 0x00 26. "R_PEND6,Masked completion ring pending bit for Rx channel 16*y+6" "0,1"
bitfld.quad 0x00 25. "T_ERR6,Masked error bit for Tx channel 16*y+6" "0,1"
bitfld.quad 0x00 24. "T_PEND6,Masked completion ring pending bit for Tx channel 16*y+6" "0,1"
newline
bitfld.quad 0x00 23. "R_ERR5,Masked error bit for Tx channel 16*y+5" "0,1"
bitfld.quad 0x00 22. "R_PEND5,Masked completion ring pending bit for Rx channel 16*y+5" "0,1"
bitfld.quad 0x00 21. "T_ERR5,Masked error bit for Tx channel 16*y+5" "0,1"
bitfld.quad 0x00 20. "T_PEND5,Masked completion ring pending bit for Tx channel 16*y+5" "0,1"
newline
bitfld.quad 0x00 19. "R_ERR4,Masked error bit for Tx channel 16*y+4" "0,1"
bitfld.quad 0x00 18. "R_PEND4,Masked completion ring pending bit for Rx channel 16*y+4" "0,1"
bitfld.quad 0x00 17. "T_ERR4,Masked error bit for Tx channel 16*y+4" "0,1"
bitfld.quad 0x00 16. "T_PEND4,Masked completion ring pending bit for Tx channel 16*y+4" "0,1"
newline
bitfld.quad 0x00 15. "R_ERR3,Masked error bit for Tx channel 16*y+3" "0,1"
bitfld.quad 0x00 14. "R_PEND3,Masked completion ring pending bit for Rx channel 16*y+3" "0,1"
bitfld.quad 0x00 13. "T_ERR3,Masked error bit for Tx channel 16*y+3" "0,1"
bitfld.quad 0x00 12. "T_PEND3,Masked completion ring pending bit for Tx channel 16*y+3" "0,1"
newline
bitfld.quad 0x00 11. "R_ERR2,Masked error bit for Tx channel 16*y+2" "0,1"
bitfld.quad 0x00 10. "R_PEND2,Masked completion ring pending bit for Rx channel 16*y+2" "0,1"
bitfld.quad 0x00 9. "T_ERR2,Masked error bit for Tx channel 16*y+2" "0,1"
bitfld.quad 0x00 8. "T_PEND2,Masked completion ring pending bit for Tx channel 16*y+2" "0,1"
newline
bitfld.quad 0x00 7. "R_ERR1,Masked error bit for Tx channel 16*y+1" "0,1"
bitfld.quad 0x00 6. "R_PEND1,Masked completion ring pending bit for Rx channel 16*y+1" "0,1"
bitfld.quad 0x00 5. "T_ERR1,Masked error bit for Tx channel 16*y+1" "0,1"
bitfld.quad 0x00 4. "T_PEND1,Masked completion ring pending bit for Tx channel 16*y+1" "0,1"
newline
bitfld.quad 0x00 3. "R_ERR0,Masked error bit for Tx channel 16*y" "0,1"
bitfld.quad 0x00 2. "R_PEND0,Masked completion ring pending bit for Rx channel 16*y" "0,1"
bitfld.quad 0x00 1. "T_ERR0,Masked error bit for Tx channel 16*y" "0,1"
bitfld.quad 0x00 0. "T_PEND0,Masked completion ring pending bit for Tx channel 16*y" "0,1"
tree.end
tree.end
tree "DRU_FW"
tree "COMPUTE_CLUSTER0_DRU_FW"
base ad:0x45047000
group.long 0x00++0x1FF
line.long 0x00 "FW0_FW_REGION_0_CONTROL,The FW Region 0 Control Register defines the control fields for the slave fw0 region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW0_FW_REGION_0_PERMISSION_0,The FW Region 0 Permission 0 Register defines the permissions for the slave fw0 region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW0_FW_REGION_0_PERMISSION_1,The FW Region 0 Permission 1 Register defines the permissions for the slave fw0 region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW0_FW_REGION_0_PERMISSION_2,The FW Region 0 Permission 2 Register defines the permissions for the slave fw0 region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW0_FW_REGION_0_START_ADDRESS_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW0_FW_REGION_0_START_ADDRESS_H,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW0_FW_REGION_0_END_ADDRESS_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW0_FW_REGION_0_END_ADDRESS_H,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW0_FW_REGION_1_CONTROL,The FW Region 1 Control Register defines the control fields for the slave fw0 region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW0_FW_REGION_1_PERMISSION_0,The FW Region 1 Permission 0 Register defines the permissions for the slave fw0 region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW0_FW_REGION_1_PERMISSION_1,The FW Region 1 Permission 1 Register defines the permissions for the slave fw0 region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW0_FW_REGION_1_PERMISSION_2,The FW Region 1 Permission 2 Register defines the permissions for the slave fw0 region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW0_FW_REGION_1_START_ADDRESS_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW0_FW_REGION_1_START_ADDRESS_H,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW0_FW_REGION_1_END_ADDRESS_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW0_FW_REGION_1_END_ADDRESS_H,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW0_FW_REGION_2_CONTROL,The FW Region 2 Control Register defines the control fields for the slave fw0 region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW0_FW_REGION_2_PERMISSION_0,The FW Region 2 Permission 0 Register defines the permissions for the slave fw0 region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW0_FW_REGION_2_PERMISSION_1,The FW Region 2 Permission 1 Register defines the permissions for the slave fw0 region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW0_FW_REGION_2_PERMISSION_2,The FW Region 2 Permission 2 Register defines the permissions for the slave fw0 region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW0_FW_REGION_2_START_ADDRESS_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW0_FW_REGION_2_START_ADDRESS_H,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW0_FW_REGION_2_END_ADDRESS_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW0_FW_REGION_2_END_ADDRESS_H,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW0_FW_REGION_3_CONTROL,The FW Region 3 Control Register defines the control fields for the slave fw0 region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW0_FW_REGION_3_PERMISSION_0,The FW Region 3 Permission 0 Register defines the permissions for the slave fw0 region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW0_FW_REGION_3_PERMISSION_1,The FW Region 3 Permission 1 Register defines the permissions for the slave fw0 region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW0_FW_REGION_3_PERMISSION_2,The FW Region 3 Permission 2 Register defines the permissions for the slave fw0 region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW0_FW_REGION_3_START_ADDRESS_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW0_FW_REGION_3_START_ADDRESS_H,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW0_FW_REGION_3_END_ADDRESS_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW0_FW_REGION_3_END_ADDRESS_H,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW0_FW_REGION_4_CONTROL,The FW Region 4 Control Register defines the control fields for the slave fw0 region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW0_FW_REGION_4_PERMISSION_0,The FW Region 4 Permission 0 Register defines the permissions for the slave fw0 region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW0_FW_REGION_4_PERMISSION_1,The FW Region 4 Permission 1 Register defines the permissions for the slave fw0 region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW0_FW_REGION_4_PERMISSION_2,The FW Region 4 Permission 2 Register defines the permissions for the slave fw0 region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW0_FW_REGION_4_START_ADDRESS_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW0_FW_REGION_4_START_ADDRESS_H,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW0_FW_REGION_4_END_ADDRESS_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW0_FW_REGION_4_END_ADDRESS_H,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW0_FW_REGION_5_CONTROL,The FW Region 5 Control Register defines the control fields for the slave fw0 region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW0_FW_REGION_5_PERMISSION_0,The FW Region 5 Permission 0 Register defines the permissions for the slave fw0 region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW0_FW_REGION_5_PERMISSION_1,The FW Region 5 Permission 1 Register defines the permissions for the slave fw0 region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW0_FW_REGION_5_PERMISSION_2,The FW Region 5 Permission 2 Register defines the permissions for the slave fw0 region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW0_FW_REGION_5_START_ADDRESS_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW0_FW_REGION_5_START_ADDRESS_H,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW0_FW_REGION_5_END_ADDRESS_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW0_FW_REGION_5_END_ADDRESS_H,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW0_FW_REGION_6_CONTROL,The FW Region 6 Control Register defines the control fields for the slave fw0 region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW0_FW_REGION_6_PERMISSION_0,The FW Region 6 Permission 0 Register defines the permissions for the slave fw0 region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW0_FW_REGION_6_PERMISSION_1,The FW Region 6 Permission 1 Register defines the permissions for the slave fw0 region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW0_FW_REGION_6_PERMISSION_2,The FW Region 6 Permission 2 Register defines the permissions for the slave fw0 region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW0_FW_REGION_6_START_ADDRESS_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW0_FW_REGION_6_START_ADDRESS_H,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW0_FW_REGION_6_END_ADDRESS_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW0_FW_REGION_6_END_ADDRESS_H,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW0_FW_REGION_7_CONTROL,The FW Region 7 Control Register defines the control fields for the slave fw0 region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW0_FW_REGION_7_PERMISSION_0,The FW Region 7 Permission 0 Register defines the permissions for the slave fw0 region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW0_FW_REGION_7_PERMISSION_1,The FW Region 7 Permission 1 Register defines the permissions for the slave fw0 region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW0_FW_REGION_7_PERMISSION_2,The FW Region 7 Permission 2 Register defines the permissions for the slave fw0 region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW0_FW_REGION_7_START_ADDRESS_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW0_FW_REGION_7_START_ADDRESS_H,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW0_FW_REGION_7_END_ADDRESS_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW0_FW_REGION_7_END_ADDRESS_H,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x100 "FW0_FW_REGION_8_CONTROL,The FW Region 8 Control Register defines the control fields for the slave fw0 region 8 firewall"
bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x100 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x100 4. "LOCK,Lock region" "0,1"
bitfld.long 0x100 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "FW0_FW_REGION_8_PERMISSION_0,The FW Region 8 Permission 0 Register defines the permissions for the slave fw0 region 8 firewall"
hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x108 "FW0_FW_REGION_8_PERMISSION_1,The FW Region 8 Permission 1 Register defines the permissions for the slave fw0 region 8 firewall"
hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10C "FW0_FW_REGION_8_PERMISSION_2,The FW Region 8 Permission 2 Register defines the permissions for the slave fw0 region 8 firewall"
hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x110 "FW0_FW_REGION_8_START_ADDRESS_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 8 firewall"
hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x114 "FW0_FW_REGION_8_START_ADDRESS_H,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 8 firewall"
hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x118 "FW0_FW_REGION_8_END_ADDRESS_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 8 firewall"
hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x11C "FW0_FW_REGION_8_END_ADDRESS_H,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 8 firewall"
hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x120 "FW0_FW_REGION_9_CONTROL,The FW Region 9 Control Register defines the control fields for the slave fw0 region 9 firewall"
bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x120 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x120 4. "LOCK,Lock region" "0,1"
bitfld.long 0x120 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "FW0_FW_REGION_9_PERMISSION_0,The FW Region 9 Permission 0 Register defines the permissions for the slave fw0 region 9 firewall"
hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x128 "FW0_FW_REGION_9_PERMISSION_1,The FW Region 9 Permission 1 Register defines the permissions for the slave fw0 region 9 firewall"
hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x12C "FW0_FW_REGION_9_PERMISSION_2,The FW Region 9 Permission 2 Register defines the permissions for the slave fw0 region 9 firewall"
hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x130 "FW0_FW_REGION_9_START_ADDRESS_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 9 firewall"
hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x134 "FW0_FW_REGION_9_START_ADDRESS_H,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 9 firewall"
hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x138 "FW0_FW_REGION_9_END_ADDRESS_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 9 firewall"
hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x13C "FW0_FW_REGION_9_END_ADDRESS_H,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 9 firewall"
hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x140 "FW0_FW_REGION_10_CONTROL,The FW Region 10 Control Register defines the control fields for the slave fw0 region 10 firewall"
bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x140 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x140 4. "LOCK,Lock region" "0,1"
bitfld.long 0x140 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "FW0_FW_REGION_10_PERMISSION_0,The FW Region 10 Permission 0 Register defines the permissions for the slave fw0 region 10 firewall"
hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x148 "FW0_FW_REGION_10_PERMISSION_1,The FW Region 10 Permission 1 Register defines the permissions for the slave fw0 region 10 firewall"
hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x14C "FW0_FW_REGION_10_PERMISSION_2,The FW Region 10 Permission 2 Register defines the permissions for the slave fw0 region 10 firewall"
hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x150 "FW0_FW_REGION_10_START_ADDRESS_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 10 firewall"
hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x154 "FW0_FW_REGION_10_START_ADDRESS_H,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 10 firewall"
hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x158 "FW0_FW_REGION_10_END_ADDRESS_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 10 firewall"
hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x15C "FW0_FW_REGION_10_END_ADDRESS_H,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 10 firewall"
hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x160 "FW0_FW_REGION_11_CONTROL,The FW Region 11 Control Register defines the control fields for the slave fw0 region 11 firewall"
bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x160 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x160 4. "LOCK,Lock region" "0,1"
bitfld.long 0x160 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "FW0_FW_REGION_11_PERMISSION_0,The FW Region 11 Permission 0 Register defines the permissions for the slave fw0 region 11 firewall"
hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x168 "FW0_FW_REGION_11_PERMISSION_1,The FW Region 11 Permission 1 Register defines the permissions for the slave fw0 region 11 firewall"
hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x16C "FW0_FW_REGION_11_PERMISSION_2,The FW Region 11 Permission 2 Register defines the permissions for the slave fw0 region 11 firewall"
hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x170 "FW0_FW_REGION_11_START_ADDRESS_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 11 firewall"
hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x174 "FW0_FW_REGION_11_START_ADDRESS_H,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 11 firewall"
hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x178 "FW0_FW_REGION_11_END_ADDRESS_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 11 firewall"
hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x17C "FW0_FW_REGION_11_END_ADDRESS_H,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 11 firewall"
hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x180 "FW0_FW_REGION_12_CONTROL,The FW Region 12 Control Register defines the control fields for the slave fw0 region 12 firewall"
bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x180 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x180 4. "LOCK,Lock region" "0,1"
bitfld.long 0x180 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "FW0_FW_REGION_12_PERMISSION_0,The FW Region 12 Permission 0 Register defines the permissions for the slave fw0 region 12 firewall"
hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x188 "FW0_FW_REGION_12_PERMISSION_1,The FW Region 12 Permission 1 Register defines the permissions for the slave fw0 region 12 firewall"
hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x18C "FW0_FW_REGION_12_PERMISSION_2,The FW Region 12 Permission 2 Register defines the permissions for the slave fw0 region 12 firewall"
hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x190 "FW0_FW_REGION_12_START_ADDRESS_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 12 firewall"
hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x194 "FW0_FW_REGION_12_START_ADDRESS_H,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 12 firewall"
hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x198 "FW0_FW_REGION_12_END_ADDRESS_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 12 firewall"
hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x19C "FW0_FW_REGION_12_END_ADDRESS_H,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 12 firewall"
hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1A0 "FW0_FW_REGION_13_CONTROL,The FW Region 13 Control Register defines the control fields for the slave fw0 region 13 firewall"
bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x1A0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1A0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "FW0_FW_REGION_13_PERMISSION_0,The FW Region 13 Permission 0 Register defines the permissions for the slave fw0 region 13 firewall"
hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1A8 "FW0_FW_REGION_13_PERMISSION_1,The FW Region 13 Permission 1 Register defines the permissions for the slave fw0 region 13 firewall"
hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1AC "FW0_FW_REGION_13_PERMISSION_2,The FW Region 13 Permission 2 Register defines the permissions for the slave fw0 region 13 firewall"
hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1B0 "FW0_FW_REGION_13_START_ADDRESS_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 13 firewall"
hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1B4 "FW0_FW_REGION_13_START_ADDRESS_H,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 13 firewall"
hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1B8 "FW0_FW_REGION_13_END_ADDRESS_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 13 firewall"
hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1BC "FW0_FW_REGION_13_END_ADDRESS_H,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 13 firewall"
hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1C0 "FW0_FW_REGION_14_CONTROL,The FW Region 14 Control Register defines the control fields for the slave fw0 region 14 firewall"
bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x1C0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1C0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "FW0_FW_REGION_14_PERMISSION_0,The FW Region 14 Permission 0 Register defines the permissions for the slave fw0 region 14 firewall"
hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1C8 "FW0_FW_REGION_14_PERMISSION_1,The FW Region 14 Permission 1 Register defines the permissions for the slave fw0 region 14 firewall"
hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1CC "FW0_FW_REGION_14_PERMISSION_2,The FW Region 14 Permission 2 Register defines the permissions for the slave fw0 region 14 firewall"
hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1D0 "FW0_FW_REGION_14_START_ADDRESS_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 14 firewall"
hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1D4 "FW0_FW_REGION_14_START_ADDRESS_H,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 14 firewall"
hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1D8 "FW0_FW_REGION_14_END_ADDRESS_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 14 firewall"
hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1DC "FW0_FW_REGION_14_END_ADDRESS_H,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 14 firewall"
hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1E0 "FW0_FW_REGION_15_CONTROL,The FW Region 15 Control Register defines the control fields for the slave fw0 region 15 firewall"
bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x1E0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1E0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "FW0_FW_REGION_15_PERMISSION_0,The FW Region 15 Permission 0 Register defines the permissions for the slave fw0 region 15 firewall"
hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1E8 "FW0_FW_REGION_15_PERMISSION_1,The FW Region 15 Permission 1 Register defines the permissions for the slave fw0 region 15 firewall"
hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1EC "FW0_FW_REGION_15_PERMISSION_2,The FW Region 15 Permission 2 Register defines the permissions for the slave fw0 region 15 firewall"
hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1F0 "FW0_FW_REGION_15_START_ADDRESS_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave fw0 region 15 firewall"
hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1F4 "FW0_FW_REGION_15_START_ADDRESS_H,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave fw0 region 15 firewall"
hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1F8 "FW0_FW_REGION_15_END_ADDRESS_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave fw0 region 15 firewall"
hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1FC "FW0_FW_REGION_15_END_ADDRESS_H,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave fw0 region 15 firewall"
hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
tree.end
tree.end
tree "DRU_FW_GLB"
tree "COMPUTE_CLUSTER0_DRU_FW_GLB"
base ad:0x45B17000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree.end
tree "DRU_MMR_FW"
tree "COMPUTE_CLUSTER0_DRU_MMR_FW"
base ad:0x45048000
group.long 0x00++0x07
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_CONTROL,The FW Region 0 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FW_REGION_0_PERMISSION_0,The FW Region 0 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x10++0x17
line.long 0x00 "DRU_MMR_CFG_FW_REGION_0_START_ADDRESS_L,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave mmr.dru_mmr_cfg region 0 firewall"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x04 "DRU_MMR_CFG_FW_REGION_0_START_ADDRESS_H,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave mmr.dru_mmr_cfg region 0 firewall"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "DRU_MMR_CFG_FW_REGION_0_END_ADDRESS_L,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave mmr.dru_mmr_cfg region 0 firewall"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x0C "DRU_MMR_CFG_FW_REGION_0_END_ADDRESS_H,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave mmr.dru_mmr_cfg region 0 firewall"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x10 "DRU_MMR_CFG_FW_REGION_1_CONTROL,The FW Region 1 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 1 firewall"
bitfld.long 0x10 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x10 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "DRU_MMR_CFG_FW_REGION_1_PERMISSION_0,The FW Region 1 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 1 firewall"
hexmask.long.byte 0x14 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x14 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x14 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x14 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x14 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x14 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x14 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x14 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x14 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x14 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x14 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x14 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x14 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x30++0x0F
line.long 0x00 "DRU_MMR_CFG_FW_REGION_1_START_ADDRESS_L,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave mmr.dru_mmr_cfg region 1 firewall"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x04 "DRU_MMR_CFG_FW_REGION_1_START_ADDRESS_H,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave mmr.dru_mmr_cfg region 1 firewall"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "DRU_MMR_CFG_FW_REGION_1_END_ADDRESS_L,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave mmr.dru_mmr_cfg region 1 firewall"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x0C "DRU_MMR_CFG_FW_REGION_1_END_ADDRESS_H,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave mmr.dru_mmr_cfg region 1 firewall"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x4000++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_0_CONTROL,The FW Region 0 Channel 0 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_0_PERMISSION_0,The FW Region 0 Channel 0 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4020++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_1_CONTROL,The FW Region 0 Channel 1 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 1 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_1_PERMISSION_0,The FW Region 0 Channel 1 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 1 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4040++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_2_CONTROL,The FW Region 0 Channel 2 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 2 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_2_PERMISSION_0,The FW Region 0 Channel 2 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 2 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4060++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_3_CONTROL,The FW Region 0 Channel 3 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 3 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_3_PERMISSION_0,The FW Region 0 Channel 3 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 3 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4080++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_4_CONTROL,The FW Region 0 Channel 4 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 4 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_4_PERMISSION_0,The FW Region 0 Channel 4 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 4 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x40A0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_5_CONTROL,The FW Region 0 Channel 5 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 5 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_5_PERMISSION_0,The FW Region 0 Channel 5 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 5 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x40C0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_6_CONTROL,The FW Region 0 Channel 6 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 6 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_6_PERMISSION_0,The FW Region 0 Channel 6 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 6 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x40E0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_7_CONTROL,The FW Region 0 Channel 7 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 7 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_7_PERMISSION_0,The FW Region 0 Channel 7 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 7 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4100++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_8_CONTROL,The FW Region 0 Channel 8 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 8 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_8_PERMISSION_0,The FW Region 0 Channel 8 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 8 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4120++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_9_CONTROL,The FW Region 0 Channel 9 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 9 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_9_PERMISSION_0,The FW Region 0 Channel 9 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 9 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4140++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_10_CONTROL,The FW Region 0 Channel 10 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 10 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_10_PERMISSION_0,The FW Region 0 Channel 10 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 10 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4160++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_11_CONTROL,The FW Region 0 Channel 11 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 11 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_11_PERMISSION_0,The FW Region 0 Channel 11 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 11 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4180++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_12_CONTROL,The FW Region 0 Channel 12 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 12 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_12_PERMISSION_0,The FW Region 0 Channel 12 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 12 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x41A0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_13_CONTROL,The FW Region 0 Channel 13 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 13 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_13_PERMISSION_0,The FW Region 0 Channel 13 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 13 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x41C0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_14_CONTROL,The FW Region 0 Channel 14 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 14 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_14_PERMISSION_0,The FW Region 0 Channel 14 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 14 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x41E0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_15_CONTROL,The FW Region 0 Channel 15 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 15 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_15_PERMISSION_0,The FW Region 0 Channel 15 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 15 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4200++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_16_CONTROL,The FW Region 0 Channel 16 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 16 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_16_PERMISSION_0,The FW Region 0 Channel 16 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 16 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4220++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_17_CONTROL,The FW Region 0 Channel 17 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 17 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_17_PERMISSION_0,The FW Region 0 Channel 17 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 17 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4240++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_18_CONTROL,The FW Region 0 Channel 18 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 18 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_18_PERMISSION_0,The FW Region 0 Channel 18 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 18 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4260++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_19_CONTROL,The FW Region 0 Channel 19 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 19 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_19_PERMISSION_0,The FW Region 0 Channel 19 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 19 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4280++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_20_CONTROL,The FW Region 0 Channel 20 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 20 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_20_PERMISSION_0,The FW Region 0 Channel 20 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 20 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x42A0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_21_CONTROL,The FW Region 0 Channel 21 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 21 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_21_PERMISSION_0,The FW Region 0 Channel 21 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 21 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x42C0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_22_CONTROL,The FW Region 0 Channel 22 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 22 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_22_PERMISSION_0,The FW Region 0 Channel 22 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 22 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x42E0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_23_CONTROL,The FW Region 0 Channel 23 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 23 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_23_PERMISSION_0,The FW Region 0 Channel 23 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 23 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4300++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_24_CONTROL,The FW Region 0 Channel 24 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 24 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_24_PERMISSION_0,The FW Region 0 Channel 24 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 24 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4320++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_25_CONTROL,The FW Region 0 Channel 25 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 25 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_25_PERMISSION_0,The FW Region 0 Channel 25 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 25 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4340++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_26_CONTROL,The FW Region 0 Channel 26 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 26 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_26_PERMISSION_0,The FW Region 0 Channel 26 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 26 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4360++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_27_CONTROL,The FW Region 0 Channel 27 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 27 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_27_PERMISSION_0,The FW Region 0 Channel 27 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 27 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x4380++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_28_CONTROL,The FW Region 0 Channel 28 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 28 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_28_PERMISSION_0,The FW Region 0 Channel 28 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 28 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x43A0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_29_CONTROL,The FW Region 0 Channel 29 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 29 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_29_PERMISSION_0,The FW Region 0 Channel 29 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 29 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x43C0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_30_CONTROL,The FW Region 0 Channel 30 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 30 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_30_PERMISSION_0,The FW Region 0 Channel 30 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 30 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x43E0++0x07
line.long 0x00 "DRU_MMR_CFG_FWCH_REGION_0_CH_31_CONTROL,The FW Region 0 Channel 31 Control Register defines the control fields for the slave mmr.dru_mmr_cfg region 0 channel 31 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DRU_MMR_CFG_FWCH_REGION_0_CH_31_PERMISSION_0,The FW Region 0 Channel 31 Permission 0 Register defines the permissions for the slave mmr.dru_mmr_cfg region 0 channel 31 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
tree.end
tree.end
tree "DRU_MMR_FW_GLB"
tree "COMPUTE_CLUSTER0_DRU_MMR_FW_GLB"
base ad:0x45B18000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree.end
tree "DSI_ECC_AGGR"
tree "DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG"
base ad:0x4700000
rgroup.long 0x00++0x03
line.long 0x00 "DSI_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "DSI_ECC_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "DSI_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "DSI_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "DSI_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DSI_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "EDC_CTRL_SYS_PEND,Interrupt Pending Status for edc_ctrl_sys_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "DSI_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "EDC_CTRL_SYS_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_sys_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "DSI_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "EDC_CTRL_SYS_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_sys_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DSI_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "DSI_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "EDC_CTRL_SYS_PEND,Interrupt Pending Status for edc_ctrl_sys_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DSI_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "EDC_CTRL_SYS_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_sys_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DSI_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "EDC_CTRL_SYS_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_sys_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "DSI_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "DSI_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "DSI_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "DSI_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "DSI_TOP"
tree "DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI"
base ad:0x4800000
rgroup.long 0x00++0x43
line.long 0x00 "DSI_IP_CONF,IP Configuration for Controller"
bitfld.long 0x00 31. "ASF_CONFIG,Active Safety Features [ASF] Configuration" "0,1"
bitfld.long 0x00 26.--30. "SP_HS_FIFO_DEPTH,SP_HS_FIFO_DEPTH : HS FIFO depth in sending path" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 21.--25. "SP_LP_FIFO_DEPTH,SP_LP_FIFO_DEPTH : LP FIFO depth in sending path" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "VRS_FIFO_DEPTH,VRS_FIFO_DEPTH : FIFO depth in the VRS block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 13.--15. "DIRCMD_FIFO_DEPTH,Direct Command FIFO Depth" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12. "INTERFACE_DATASIZE,SDI interface data width" "0,1"
newline
bitfld.long 0x00 10.--11. "DATAPATH_SIZE,Internal Datapath.width" "0,1,2,3"
bitfld.long 0x00 8.--9. "NUM_INTERFACE,Max Number of SDI interfaces" "0,1,2,3"
bitfld.long 0x00 6.--7. "MAX_LANE_NB,Max Number of Lanes" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "RX_FIFO_DEPTH,RX FIFO Depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DSI_MCTL_MAIN_DATA_CTL,Main Control - main control setting for datapath"
bitfld.long 0x04 25. "TE_MIPI_POLLING_EN,TE_MIPI_POLLING_EN: enables TE Polling feature following MIPI recommendations [polling by software]" "0,1"
bitfld.long 0x04 24. "TE_HW_POLLING_EN,TE_HW_POLLING_EN: enables TE Polling feature following internal solution" "0,1"
bitfld.long 0x04 18. "DISP_EOT_GEN,DISP_EOT_GEN: display adds an EOT packet to its LPDT transfers" "0,1"
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bitfld.long 0x04 17. "HOST_EOT_GEN,HOST_EOT_GEN: generates or not the EOT packet after a transfer in HS" "0,1"
bitfld.long 0x04 16. "DISP_GEN_CHECKSUM,DISP_GEN_CHECKSUM: display generates checksum on its response packets" "0,1"
bitfld.long 0x04 15. "DISP_GEN_ECC,DISP_GEN_ECC: display generates ECC on its response packets" "0,1"
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bitfld.long 0x04 14. "BTA_EN,BTA_EN: enables BTA" "0,1"
bitfld.long 0x04 13. "READ_EN,READ_EN: enables read operation" "0,1"
bitfld.long 0x04 12. "REG_TE_EN,REG_TE_EN: enables Tearing Effect from register" "0,1"
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bitfld.long 0x04 10. "SPLIT_PANEL_MODE,SPLIT_PANEL_MODE: when enabled DSC stage controls data for split panel signle DPHY link" "0,1"
bitfld.long 0x04 9. "IF3_TE_EN,IF3_TE_EN: enables Tearing Effect on interface 3" "0,1"
bitfld.long 0x04 8. "IF1_TE_EN,IF1_TE_EN: enables Tearing Effect on interface 1" "0,1"
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bitfld.long 0x04 6. "TVG_SEL,TVG_SEL: Test Video Generator is enabled [it is not the start signal!] - should not be set if if1_en = 1 and if1_mode = 1 [see" "0,1"
bitfld.long 0x04 5. "VID_EN,VID_EN: enables the video stream generator" "0,1"
bitfld.long 0x04 2.--3. "VID_IF_SELECT,VID_IF_SELECT: Determines which video interface is active" "0,1,2,3"
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bitfld.long 0x04 1. "SDI_IF_VID_MODE,SDI_IF_VID_MODE" "0,1"
bitfld.long 0x04 0. "LINK_EN,LINK_EN: enables [or not] the link]" "0,1"
line.long 0x08 "DSI_MCTL_MAIN_PHY_CTL,Main control setting for the physical lanes and drive the static signals for D-PHY clock lane"
bitfld.long 0x08 30. "HS_SKEWCAL_TIMEOUT_EN,HS_SKEWCAL_TIMEOUT_EN: Activate the HS SkewCal Control to occur after a timeout" "0,1"
bitfld.long 0x08 29. "HS_SKEWCAL_FORCE_EN,HS_SKEWCAL_FORCE_EN: Force the HS SkewCal Control to occur immediately" "0,1"
bitfld.long 0x08 28. "HS_SKEWCAL_EN,HS_SKEWCAL_EN: activate the HS SkewCal Control at start of HS Transmission" "0,1"
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bitfld.long 0x08 25. "HS_INVERT_DAT4,HS_INVERT_DAT" "0,1"
bitfld.long 0x08 24. "SWAP_PINS_DAT4,SWAP_PINS_DAT" "0,1"
bitfld.long 0x08 23. "HS_INVERT_DAT3,HS_INVERT_DAT" "0,1"
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bitfld.long 0x08 22. "SWAP_PINS_DAT3,SWAP_PINS_DAT" "0,1"
bitfld.long 0x08 21. "HS_INVERT_DAT2,HS_INVERT_DAT" "0,1"
bitfld.long 0x08 20. "SWAP_PINS_DAT2,SWAP_PINS_DAT" "0,1"
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bitfld.long 0x08 19. "HS_INVERT_DAT1,HS_INVERT_DAT" "0,1"
bitfld.long 0x08 18. "SWAP_PINS_DAT1,SWAP_PINS_DAT" "0,1"
bitfld.long 0x08 17. "HS_INVERT_CLK,HS_INVERT_CLK: invert HS signal on clock lane" "0,1"
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bitfld.long 0x08 16. "SWAP_PINS_CLK,SWAP_PINS_CLK: swap pins on clock lane" "0,1"
bitfld.long 0x08 10.--13. "WAIT_BURST_TIME,WAIT_BURST_TIME: delay to respect between two HS bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 9. "DAT4_ULPM_EN,DAT4_ULPM_EN: data lane 4 can be switched in ULP mode" "0,1"
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bitfld.long 0x08 8. "DAT3_ULPM_EN,DAT3_ULPM_EN: data lane 3 can be switched in ULP mode" "0,1"
bitfld.long 0x08 7. "DAT2_ULPM_EN,DAT2_ULPM_EN: data lane 2 can be switched in ULP mode" "0,1"
bitfld.long 0x08 6. "DAT1_ULPM_EN,DAT1_ULPM_EN: data lane 1 can be switched in ULP mode" "0,1"
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bitfld.long 0x08 5. "CLK_ULPM_EN,CLK_ULPM_EN: specifies that clock lane can be switched in ULP mode [on demand]" "0,1"
bitfld.long 0x08 4. "CLK_CONTINUOUS,CLK_CONTINUOUS: clock lane should remain in HS sending mode [no return in STOP state]" "0,1"
bitfld.long 0x08 2. "LANE4_EN,LANE4_EN: enables the fourth lane [ controls DCB FSM]" "0,1"
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bitfld.long 0x08 1. "LANE3_EN,LANE3_EN: enables the third lane [ controls DCB FSM]" "0,1"
bitfld.long 0x08 0. "LANE2_EN,LANE2_EN: enables the second lane [ controls DCB FSM]" "0,1"
line.long 0x0C "DSI_MCTL_MAIN_EN,Control start/stop of the DSI link"
bitfld.long 0x0C 17. "FORCE_STOP_MODE,FORCE_STOP_MODE: when enabled data lanes are forced back in STOP mode - this value should remain asserted for 10 us minimum" "0,1"
bitfld.long 0x0C 16. "CLK_FORCE_STOP,CLK_FORCE_STOP : force clock lanes back in STOP mode - this value should remain asserted for 10 us minimum" "0,1"
bitfld.long 0x0C 15. "IF3_EN,IF3_EN: enables DSC interface [i.e" "0,1"
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bitfld.long 0x0C 14. "IF2_EN,IF2_EN: enables DPI interface [i.e" "0,1"
bitfld.long 0x0C 13. "IF1_EN,IF1_EN: enables SDI interface [i.e" "0,1"
bitfld.long 0x0C 12. "DAT4_ULPM_REQ,DAT4_ULPM_REQ: switches data lane 4 in ULP mode" "0,1"
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bitfld.long 0x0C 11. "DAT3_ULPM_REQ,DAT3_ULPM_REQ: switches data lane 3 in ULP mode" "0,1"
bitfld.long 0x0C 10. "DAT2_ULPM_REQ,DAT2_ULPM_REQ: switches data lane 2 in ULP mode" "0,1"
bitfld.long 0x0C 9. "DAT1_ULPM_REQ,DAT1_ULPM_REQ: switches data lane 1 in ULP mode" "0,1"
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bitfld.long 0x0C 8. "CLKLANE_ULPM_REQ,CLKLANE_ULPM_REQ: switches clock lane in ULP mode" "0,1"
bitfld.long 0x0C 7. "DAT4_EN,DAT4_EN" "0,1"
bitfld.long 0x0C 6. "DAT3_EN,DAT3_EN" "0,1"
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bitfld.long 0x0C 5. "DAT2_EN,DAT2_EN" "0,1"
bitfld.long 0x0C 4. "DAT1_EN,DAT1_EN" "0,1"
bitfld.long 0x0C 3. "CKLANE_EN,CKLANE_EN" "0,1"
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bitfld.long 0x0C 0. "PLL_START,PLL_START: enables the PLL [when set the PLL is started]" "0,1"
line.long 0x10 "DSI_MCTL_DPHY_CFG0,DPHY Power and Reset Control"
bitfld.long 0x10 20. "DPHY_C_RSTB,Drives dphy_c_rstb output" "0,1"
bitfld.long 0x10 16.--19. "DPHY_D_RSTB,Drives dphy_d_rstb output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 10. "DPHY_PLL_PDN,Drives dphy_pll_pdn output" "0,1"
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bitfld.long 0x10 9. "DPHY_CMN_PDN,Drives dphy_cmn_pdn output" "0,1"
bitfld.long 0x10 8. "DPHY_C_PDN,Drives dphy_c_pdn output" "0,1"
bitfld.long 0x10 4.--7. "DPHY_D_PDN,Drives dphy_d_pdn output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 1. "DPHY_PLL_PSO,Drives dphy_pll_pso output" "0,1"
bitfld.long 0x10 0. "DPHY_CMN_PSO,Drives dphy_cmn_pso output" "0,1"
line.long 0x14 "DSI_MCTL_DPHY_TIMEOUT1,Main DPHY time-out settings"
hexmask.long.tbyte 0x14 4.--21. 1. "HSTX_TO_VAL,HSTX_TO_VAL: HS TX time-out detection value"
bitfld.long 0x14 0.--3. "CLK_DIV,CLK_DIV: clock division ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DSI_MCTL_DPHY_TIMEOUT2,To better understand the way this register is used. please refer to Section : DSI checks (DC) - the counters are on tx_byte_hs_clk and not on sys_clk"
hexmask.long.tbyte 0x18 0.--17. 1. "LPRX_TO_VAL,LPRX_TO_VAL: LP RX time-out detection value"
line.long 0x1C "DSI_MCTL_ULPOUT_TIME,Specify time to leave ULP mode"
hexmask.long.word 0x1C 9.--17. 1. "DATA_ULPOUT_TIME,DATA_ULPOUT_TIME: specify what the duration is to leave ULP mode is [for data lane[s] in system clock cycles"
hexmask.long.word 0x1C 0.--8. 1. "CKLANE_ULPOUT_TIME,CKLANE_ULPOUT_TIME: specify what the duration is to leave ULP mode is [for clock lane] in system clock cycles"
line.long 0x20 "DSI_MCTL_3DVIDEO_CTL,3D Video mode stream control"
bitfld.long 0x20 7. "VID_VSYNC_3D_EN,VID_VSYNC_3D_EN: Enable 3D Control this selects the 3D operation for VSYNC and video data control" "0,1"
bitfld.long 0x20 5. "VID_VSYNC_3D_LR,VID_VSYNC_3D_LR: When 3D mode is enabled this allows to choose which field to start the video stream" "0,1"
bitfld.long 0x20 4. "VID_VSYNC_3D_SECOND_EN,VID_VSYNC_3D_SECOND_EN: When 3D mode is enabled this allows to choose if a second VSYNC is enabled between L and R images" "0,1"
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bitfld.long 0x20 2.--3. "VID_VSYNC_3DFORMAT,VID_VSYNC_3DFORMAT: video 3D Format for VSYNC Control Parameter1" "0,1,2,3"
bitfld.long 0x20 0.--1. "VID_VSYNC_3DMODE,VID_VSYNC_3DMODE: video 3D mode for VSYNC Control Parameter1" "0,1,2,3"
line.long 0x24 "DSI_MCTL_MAIN_STS,Status of the DSI link"
bitfld.long 0x24 11. "HS_SKEWCAL_DONE,HS_SKEWCAL_DONE: HS SkewCal Control Done at start of HS Transmission" "0,1"
bitfld.long 0x24 10. "IF3_UNTERM_PCK,IF3_UNTERM_PCK: Indicates an unterminated packet on DSC interface" "0,1"
bitfld.long 0x24 9. "IF2_UNTERM_PCK,IF2_UNTERM_PCK: Indicates an unterminated packet on DPI interface" "0,1"
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bitfld.long 0x24 8. "IF1_UNTERM_PCK,IF1_UNTERM_PCK: Indicates an unterminated packet on SDI Interface" "0,1"
bitfld.long 0x24 7. "LPRX_TO_ERR,LPRX_TO_ERR: Indicates an LP_RX time-out error" "0,1"
bitfld.long 0x24 6. "HSTX_TO_ERR,HSTX_TO_ERR: Indicates an HS_TX time-out error" "0,1"
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bitfld.long 0x24 5. "DAT4_READY,DAT4_READY: Indicates data lane 4 is ready" "0,1"
bitfld.long 0x24 4. "DAT3_READY,DAT3_READY: Indicates data lane 3 is ready" "0,1"
bitfld.long 0x24 3. "DAT2_READY,DAT2_READY: Indicates data lane 2 is ready" "0,1"
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bitfld.long 0x24 2. "DAT1_READY,DAT1_READY: Indicates data lane 1 is ready" "0,1"
bitfld.long 0x24 1. "CLKLANE_READY,CLKLANE_READY: Indicates the clock lane is ready [normal DSI operation can start]" "0,1"
bitfld.long 0x24 0. "PLL_LCK,PLL_LCK: Indicates PLL is locked - data coming from DCB [if DSI link is PLL master] or copy of pll_en [if DSI link is slave]" "0,1"
line.long 0x28 "DSI_MCTL_DPHY_ERR,Errors reported from DPHY lanes - See description in DPHY inputs and outputs"
bitfld.long 0x28 25. "ERR_CONT_LP1_4,ERR_CONT_LP1_4" "0,1"
bitfld.long 0x28 24. "ERR_CONT_LP1_3,ERR_CONT_LP1_3" "0,1"
bitfld.long 0x28 23. "ERR_CONT_LP1_2,ERR_CONT_LP1_2" "0,1"
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bitfld.long 0x28 22. "ERR_CONT_LP1_1,ERR_CONT_LP1_1" "0,1"
bitfld.long 0x28 21. "ERR_CONT_LP0_4,ERR_CONT_LP0_4" "0,1"
bitfld.long 0x28 20. "ERR_CONT_LP0_3,ERR_CONT_LP0_3" "0,1"
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bitfld.long 0x28 19. "ERR_CONT_LP0_2,ERR_CONT_LP0_2" "0,1"
bitfld.long 0x28 18. "ERR_CONT_LP0_1,ERR_CONT_LP0_1" "0,1"
bitfld.long 0x28 17. "ERR_CONTROL_4,ERR_CONTROL_4" "0,1"
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bitfld.long 0x28 16. "ERR_CONTROL_3,ERR_CONTROL_3" "0,1"
bitfld.long 0x28 15. "ERR_CONTROL_2,ERR_CONTROL_2" "0,1"
bitfld.long 0x28 14. "ERR_CONTROL_1,ERR_CONTROL_1" "0,1"
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bitfld.long 0x28 13. "ERR_SYNCESC_4,ERR_SYNCESC_4" "0,1"
bitfld.long 0x28 12. "ERR_SYNCESC_3,ERR_SYNCESC_3" "0,1"
bitfld.long 0x28 11. "ERR_SYNCESC_2,ERR_SYNCESC_2" "0,1"
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bitfld.long 0x28 10. "ERR_SYNCESC_1,ERR_SYNCESC_1" "0,1"
bitfld.long 0x28 9. "ERR_ESC_4,ERR_ESC_4" "0,1"
bitfld.long 0x28 8. "ERR_ESC_3,ERR_ESC_3" "0,1"
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bitfld.long 0x28 7. "ERR_ESC_2,ERR_ESC_2" "0,1"
bitfld.long 0x28 6. "ERR_ESC_1,ERR_ESC_1" "0,1"
line.long 0x2C "DSI_MCTL_LANE_STS,DPHY Lane and PLL status information"
bitfld.long 0x2C 18. "PPI_C_TX_READY_HS,Value of ppi_c_tx_ready_hs input" "0,1"
bitfld.long 0x2C 17. "DPHY_PLL_LOCK,Value of dphy_pll_lock input" "0,1"
bitfld.long 0x2C 12.--15. "PPI_D_RX_ULPS_ESC,Value of ppi_d_rx_ulps_esc input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 9.--10. "DATLANE4_STATE,DATLANE4_STATE: state of the data lane 4" "0,1,2,3"
bitfld.long 0x2C 7.--8. "DATLANE3_STATE,DATLANE3_STATE: state of the data lane 3" "0,1,2,3"
bitfld.long 0x2C 5.--6. "DATLANE2_STATE,DATLANE2_STATE: state of the data lane 2" "0,1,2,3"
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bitfld.long 0x2C 2.--4. "DATLANE1_STATE,DATLANE1_STATE: state of the data lane 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 0.--1. "CLKLANE_STATE,CLKLANE_STATE: state of the clock lane" "0,1,2,3"
line.long 0x30 "DSI_DSC_MODE_CTL,DSC Mode Control register"
bitfld.long 0x30 0. "DSC_MODE_EN,Enable DSC Mode Controls" "0,1"
line.long 0x34 "DSI_DSC_CMD_SEND,DSC Command Control register"
bitfld.long 0x34 1. "DSC_SEND_PPS,Send PPS Command and Payload to the display" "0,1"
bitfld.long 0x34 0. "DSC_EXECUTE_QUEUE,Send Execute Queue Command to Synchonise the display drivers" "0,1"
line.long 0x38 "DSI_DSC_PPS_WRDAT,DSC PPS Write data to outgoing FIFO Buffer. byte 0 to 3; applicable to either Write or Read commands"
hexmask.long.byte 0x38 24.--31. 1. "PPS_WRDAT3,WRDAT"
hexmask.long.byte 0x38 16.--23. 1. "PPS_WRDAT2,WRDAT"
hexmask.long.byte 0x38 8.--15. 1. "PPS_WRDAT1,WRDAT"
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hexmask.long.byte 0x38 0.--7. 1. "PPS_WRDAT0,WRDAT"
line.long 0x3C "DSI_DSC_MODE_STS,DSC Event Status Register"
bitfld.long 0x3C 1. "DSC_PPS_DONE,DSC PPS Command Sent" "0,1"
bitfld.long 0x3C 0. "DSC_EXEC_DONE,DSC Execute Command Sent" "0,1"
line.long 0x40 "DSI_MCTL_DPHY_SKEWCAL_TIMEOUT,Used in conjunction with HS_SKEWCAL_TIMEOUT_EN from to control periodic skew calibration"
group.long 0x70++0x0B
line.long 0x00 "DSI_CMD_MODE_CTL,Command mode control"
bitfld.long 0x00 10. "IF3_LP_EN,IF3_LP_EN: enable to send command from DSC interface in LP if possible" "0,1"
bitfld.long 0x00 9. "IF1_LP_EN,IF1_LP_EN: enable to send command from SDI interface in LP if possible" "0,1"
bitfld.long 0x00 2.--3. "IF3_ID,IF3_ID: Virtual Channel ID of request from DSC interface command" "0,1,2,3"
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bitfld.long 0x00 0.--1. "IF1_ID,IF1_ID: Virtual Channel ID of request from SDI interface command" "0,1,2,3"
line.long 0x04 "DSI_CMD_MODE_CTL2,Command mode control"
hexmask.long.word 0x04 11.--22. 1. "TE_TIMEOUT,TE_TIMEOUT : on TE request - length of TE response window before timeout"
hexmask.long.byte 0x04 3.--10. 1. "FIL_VALUE,FIL_VALUE: value to use to fill packet during data underrun or to complete unterminated packet [referred as padding value]"
bitfld.long 0x04 1.--2. "ARB_PRI,ARB_PRI: in fixed mode specify interface with higher priority SDI 01 DSC 10" "0,1,2,3"
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bitfld.long 0x04 0. "ARB_MODE,ARB_MODE: arbitration mode" "0,1"
line.long 0x08 "DSI_CMD_MODE_STS,Command Mode status"
bitfld.long 0x08 4. "ERR_IF1_UNDERRUN,ERR_IF1_UNDERRUN: Indicates a data shortage occurs on IF1" "0,1"
bitfld.long 0x08 3. "ERR_UNWANTED_RD,ERR_UNWANTED_RD: Indicates a read request was received while read capability was not enabled" "0,1"
bitfld.long 0x08 2. "ERR_TE_MISS,ERR_TE_MISS: error: TE window time-out" "0,1"
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bitfld.long 0x08 1. "ERR_NO_TE,ERR_NO_TE: error: no TE generated by display" "0,1"
bitfld.long 0x08 0. "CSM_RUNNING,CSM_RUNNING: Indicates CSM is running - command[s] are being proceeded" "0,1"
group.long 0x80++0x17
line.long 0x00 "DSI_DIRECT_CMD_SEND,is not a real register"
line.long 0x04 "DSI_DIRECT_CMD_MAIN_SETTINGS,Main control of the Direct Command function"
bitfld.long 0x04 25.--28. "TRIGGER_VAL,TRIGGER_VAL: trigger value if trigger request [see Note about trigger mapping]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 24. "CMD_LP_EN,CMD_LP_EN: enables LP sending for the command request" "0,1"
hexmask.long.byte 0x04 16.--23. 1. "CMD_SIZE,CMD_SIZE: size in bytes of the command payload"
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bitfld.long 0x04 14.--15. "CMD_ID,CMD_ID: For a read/write command Virtual Channel of the command" "0,1,2,3"
bitfld.long 0x04 8.--13. "CMD_HEAD,CMD_HEAD: For a read/write command datatype of the command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 3. "CMD_LONGNOTSHORT,CMD_LONGNOTSHORT: Tie this to '1' if a long packet has to be generated" "0,1"
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bitfld.long 0x04 0.--2. "CMD_NAT,CMD_NAT: Type of the direct command" "0,1,2,3,4,5,6,7"
line.long 0x08 "DSI_DIRECT_CMD_STS,Direct Command Status: To ensure that the observed status bits are coherent and applicable to the last command message sent. it is recommended to clear this register between accesses by writing to direct_cmd_clr. otherwise the status.."
hexmask.long.word 0x08 16.--31. 1. "ACK_VAL,ACK_VAL: if an acknowledge with error has been received this field reports its value"
bitfld.long 0x08 11.--14. "TRIGGER_VAL,TRIGGER_VAL: if a trigger has been received this field reports its value - refer to Note regarding trigger mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10. "READ_COMPLETED_WITH_ERR,READ_COMPLETED_WITH_ERR: read command terminated with error" "0,1"
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bitfld.long 0x08 9. "BTA_FINISHED,BTA_FINISHED: DSI link recovered link master role after a BTA request" "0,1"
bitfld.long 0x08 8. "BTA_COMPLETED,BTA_COMPLETED: indicates that BTA request completed" "0,1"
bitfld.long 0x08 7. "TE_RECEIVED,TE_RECEIVED: TE received" "0,1"
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bitfld.long 0x08 6. "TRIGGER_RECEIVED,TRIGGER_RECEIVED: If command with BTA this bit is set if an trigger was received" "0,1"
bitfld.long 0x08 5. "ACK_WITH_ERR_RECEIVED,ACKNOWLEDGE_WITH_ERR_RECEIVED: If command with BTA this bit is set if an acknowledge with error was received" "0,1"
bitfld.long 0x08 4. "ACK_RECEIVED,ACKNOWLEDGE_RECEIVED: If command with BTA this bit is set if an acknowledge with no error was received" "0,1"
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bitfld.long 0x08 3. "READ_COMPLETED,READ_COMPLETED: read command request completed" "0,1"
bitfld.long 0x08 2. "TRIGGER_COMPLETED,TRIGGER_COMPLETED: trigger command request completed" "0,1"
bitfld.long 0x08 1. "WRITE_COMPLETED,WRITE_COMPLETED: write command request completed" "0,1"
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bitfld.long 0x08 0. "CMD_TRANSMISSION,CMD_TRANSMISSION: a command is being sent" "0,1"
line.long 0x0C "DSI_DIRECT_CMD_RD_INIT,This register is not a real register - when written it stops the read command process by emptying the FIFO and by stopping the reception of the data (RP does not consider the data that it receives and the system waits for the.."
line.long 0x10 "DSI_DIRECT_CMD_WRDAT,Write data to outgoing Direct Command FIFO. byte 0 to 3; applicable to either Write or Read commands"
hexmask.long.byte 0x10 24.--31. 1. "WRDAT3,WRDAT"
hexmask.long.byte 0x10 16.--23. 1. "WRDAT2,WRDAT"
hexmask.long.byte 0x10 8.--15. 1. "WRDAT1,WRDAT"
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hexmask.long.byte 0x10 0.--7. 1. "WRDAT0,WRDAT"
line.long 0x14 "DSI_DIRECT_CMD_FIFO_RST,Reset the write FIFO"
rgroup.long 0xA0++0x0B
line.long 0x00 "DSI_DIRECT_CMD_RDDAT,Data from incoming Direct Command receive path. byte 0 to 3"
hexmask.long.byte 0x00 24.--31. 1. "RDDAT3,RDDAT"
hexmask.long.byte 0x00 16.--23. 1. "RDDAT2,RDDAT"
hexmask.long.byte 0x00 8.--15. 1. "RDDAT1,RDDAT"
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hexmask.long.byte 0x00 0.--7. 1. "RDDAT0,RDDAT"
line.long 0x04 "DSI_DIRECT_CMD_RD_PROPERTY,read command characteristics"
bitfld.long 0x04 18. "RD_DCSNOTGENERIC,RD_DCSNOTGENERIC: Type of read command [DCS or generic]" "0,1"
bitfld.long 0x04 16.--17. "RD_ID,RD_ID: Virtual channel of the read received" "0,1,2,3"
hexmask.long.word 0x04 0.--15. 1. "RD_SIZE,RD_SIZE: Size of the read data received"
line.long 0x08 "DSI_DIRECT_CMD_RD_STS,Status of the read command received"
bitfld.long 0x08 8. "ERR_EOT_WITH_ERR,ERR_EOT_WITH_ERR: EOT received with error" "0,1"
bitfld.long 0x08 7. "ERR_MISSING_EOT,ERR_MISSING_EOT: EOT requested but not received" "0,1"
bitfld.long 0x08 6. "ERR_WRONG_LENGTH,ERR_WRONG_LENGTH : length error has been detected" "0,1"
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bitfld.long 0x08 5. "ERR_OVERSIZE,ERR_OVERSIZE : packet size exceeds maximum" "0,1"
bitfld.long 0x08 4. "ERR_RECEIVE,ERR_RECEIVE : received packet not complete" "0,1"
bitfld.long 0x08 3. "ERR_UNDECODABLE,ERR_UNDECODABLE : command opcode not understood" "0,1"
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bitfld.long 0x08 2. "ERR_CHECKSUM,ERR_CHECKSUM: error[s] detected by checksum" "0,1"
bitfld.long 0x08 1. "ERR_UNCORRECTABLE,ERR_UNCORRECTABLE : more than 1 error detected by ECC" "0,1"
bitfld.long 0x08 0. "ERR_FIXED,ERR_FIXED : one error detected and fixed by ECC" "0,1"
group.long 0xB0++0x0B
line.long 0x00 "DSI_VID_MAIN_CTL,Video mode main control"
bitfld.long 0x00 31. "VID_IGNORE_MISS_VSYNC,VID_IGNORE_MISSING_SYNC: When mode is enabled this allows the video stream to go to IDLE during VFP and wait for new VSYNC without link failing to recovery" "0,1"
bitfld.long 0x00 25.--26. "RECOVERY_MODE,RECOVERY_MODE: specify recovery mode" "0,1,2,3"
bitfld.long 0x00 23.--24. "REG_BLKEOL_MODE,REG_BLKEOL_MODE: behavior during end of line in burst mode - same coding as reg_blkline_mode" "0,1,2,3"
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bitfld.long 0x00 21.--22. "REG_BLKLINE_MODE,REG_BLKLINE_MODE : behavior during blanking time [1x: LP " "0,1,2,3"
bitfld.long 0x00 20. "SYNC_PULSE_HORIZONTAL,SYNC_PULSE_HORIZONTAL: syncs are pulse [1] or event [0] all the time [DSI protocol v1.00..._r6 and later] - to be set only when sync_pulse_active = 1" "0,1"
bitfld.long 0x00 19. "SYNC_PULSE_ACTIVE,SYNC_PULSE_ACTIVE: syncs are pulse [1] or event [0] during active area [DSI protocol v1.00..._r3 and before]" "0,1"
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bitfld.long 0x00 18. "BURST_MODE,BURST_MODE: signals if system works in burst mode or not" "0,1"
bitfld.long 0x00 14.--17. "VID_PIXEL_MODE,VID_PIXEL_MODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--13. "HEADER,HEADER : specify the datatype of RGB packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--5. "VID_ID,VID_ID : specify the Virtual Channel Identifier of the video packets" "0,1,2,3"
bitfld.long 0x00 2.--3. "STOP_MODE,STOP_MODE : video stop point [see description in Video Stream Generator [VSG] section] .[The configurations where the frame stops at the end of any line" "0,1,2,3"
bitfld.long 0x00 0.--1. "START_MODE,START_MODE: video entry point [see description in Video Stream Generator [VSG] section][The configuration where the frame starts with a VFP" "0,1,2,3"
line.long 0x04 "DSI_VID_VSIZE1,Image vertical Sync and Blanking settings"
hexmask.long.byte 0x04 12.--19. 1. "VFP_LENGTH,VFP_LENGTH: length of the VFP [in lines]"
bitfld.long 0x04 6.--11. "VBP_LENGTH,VBP_LENGTH: length of the VBP [in lines]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--5. "VSA_LENGTH,VSA_LENGTH: duration of the VSYNC pulse [in lines]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DSI_VID_VSIZE2,Image vertical active line setting"
hexmask.long.word 0x08 0.--12. 1. "VACT_LENGTH,VACT_LENGTH: vertical length of active area [in line]"
group.long 0xC0++0x07
line.long 0x00 "DSI_VID_HSIZE1,Image horizontal sync and Blanking setting Active line Pulse Mode: |____hsync_____|____hbp_____|________________hact_______________|_______hfp________|.."
hexmask.long.word 0x00 16.--31. 1. "HBP_LENGTH,HBP_LENGTH: length of HBP [in bytes] - if 0 HBP packet is sent with 0 payload"
hexmask.long.word 0x00 0.--9. 1. "HSA_LENGTH,HSA_LENGTH: duration of HSYNC pulse [in bytes]"
line.long 0x04 "DSI_VID_HSIZE2,Image horizontal byte size setting"
hexmask.long.word 0x04 16.--26. 1. "HFP_LENGTH,HFP_LENGTH: length of HFP [in bytes] - if 0 no HFP packet is sent"
hexmask.long.word 0x04 0.--14. 1. "RGB_SIZE,RGB_SIZE: size [in byte] of the RGB packet"
group.long 0xCC++0x07
line.long 0x00 "DSI_VID_BLKSIZE1,blanking packet size"
hexmask.long.word 0x00 15.--29. 1. "BLKEOL_PCK,BLKEOL_PCK: packet length [in byte] on end of line if burst mode [reg_blkeol_mode = 0b0x]"
hexmask.long.word 0x00 0.--14. 1. "BLKLINE_EVENT_PCK,BLKLINE_EVENT_PCK: packet length [in byte] in blanking line if line has to be filled with a packet [reg_blkline_mode = 0b0x] and sync is an event"
line.long 0x04 "DSI_VID_BLKSIZE2,Pulse Mode blanking packet size"
hexmask.long.word 0x04 0.--14. 1. "BLKLINE_PULSE_PCK,BLKLINE_PULSE_PCK: packet length in blanking line if line has to be filled with a packet [reg_blkline_mode = 0b0x] and sync is a pulse"
group.long 0xD8++0x3F
line.long 0x00 "DSI_VID_PCK_TIME,Packet duration"
hexmask.long.word 0x00 0.--14. 1. "BLKEOL_DURATION,BLKEOL_DURATION: specify the duration in clock cycles of the BLLP period [used for burst mode]"
line.long 0x04 "DSI_VID_DPHY_TIME,Time of D-PHY behavior for wakeup time and Line duration for LP during horozontal blanking lines"
hexmask.long.word 0x04 17.--27. 1. "REG_WAKEUP_TIME,REG_WAKEUP_TIME: estimated time [in clock cycles] to perform LP->HS on D-PHY"
hexmask.long.tbyte 0x04 0.--16. 1. "REG_LINE_DURATION,REG_LINE_DURATION: duration -in clock cycles - of the blanking area for VSA/VBP and VFP lines - considered when reg_blkline_mode = 1b1x"
line.long 0x08 "DSI_VID_ERR_COLOR1,error color (green and red)"
hexmask.long.word 0x08 12.--23. 1. "COL_GREEN,COL_GREEN: green component of the fill color"
hexmask.long.word 0x08 0.--11. 1. "COL_RED,COL_RED: red component of the fill color"
line.long 0x0C "DSI_VID_ERR_COLOR2,error color (blue and padding)"
hexmask.long.word 0x0C 12.--23. 1. "PAD_VALUE,PAD_VALUE: byte used to pad data [when system does not know exactly where it is]"
hexmask.long.word 0x0C 0.--11. 1. "COL_BLUE,COL_BLUE: blue component of the fill color"
line.long 0x10 "DSI_VID_VPOS,vertical position"
hexmask.long.word 0x10 2.--14. 1. "LINE_VAL,LINE_VAL: line number of the current area"
bitfld.long 0x10 0.--1. "LINE_POS,LINE_POS: position in the frame [see description in Video Stream Generator]" "0,1,2,3"
line.long 0x14 "DSI_VID_HPOS,Horizontal Position"
hexmask.long.word 0x14 3.--17. 1. "HORIZONTAL_VAL,HORIZONTAL_VAL: position in the current horizontal area [in clock cycles]"
bitfld.long 0x14 0.--2. "HORIZONTAL_POS,HORIZONTAL_POS: position in the line [see description in Video Stream Generator]" "0,1,2,3,4,5,6,7"
line.long 0x18 "DSI_VID_MODE_STS,Video mode status and error reporting"
bitfld.long 0x18 10. "VSG_RECOVERY,VSG_RECOVERY: specifies whether the VSG is in recovery mode or not" "0,1"
bitfld.long 0x18 9. "ERR_VRS_WRONG_LENGTH,ERR_VRS_WRONG_LENGTH: signals that packets in SDI interface differ from the expected size [as specified by rgb_size]" "0,1"
bitfld.long 0x18 8. "ERR_LONGREAD,ERR_LONGREAD: signals the read was too long" "0,1"
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bitfld.long 0x18 7. "ERR_LINEWRITE,ERR_LINEWRITE: signals the long packet is too long to pass during a long slot" "0,1"
bitfld.long 0x18 6. "ERR_BURSTWRITE,ERR_BURSTWRITE: signals a long packet has been sent during active area" "0,1"
bitfld.long 0x18 5. "REG_ERR_SMALL_HEIGHT,REG_ERR_SMALL_HEIGHT: fewer lines than expected between 2 VSYNC" "0,1"
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bitfld.long 0x18 4. "REG_ERR_SMALL_LENGTH,REG_ERR_SMALL_LENGTH: fewer bytes received than expected between 2 HSYNC" "0,1"
bitfld.long 0x18 3. "ERR_MISSING_VSYNC,ERR_MISSING_VSYNC: missing VSYNC" "0,1"
bitfld.long 0x18 2. "ERR_MISSING_HSYNC,ERR_MISSING_HSYNC: missing HSYNC" "0,1"
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bitfld.long 0x18 1. "ERR_MISSING_DATA,ERR_MISSING_DATA: data starvation at input of the VSG" "0,1"
bitfld.long 0x18 0. "VSG_RUNNING,VSG_RUNNING: VSG is running [1] or stopped [0]" "0,1"
line.long 0x1C "DSI_VID_VCA_SETTING1,VCA control register 1"
bitfld.long 0x1C 16. "BURST_LP,BURST_LP: after an active line the system can switch in LP [1] or should complete the line with NULL packet [0]" "0,1"
hexmask.long.word 0x1C 0.--15. 1. "MAX_BURST_LIMIT,MAX_BURST_LIMIT: size of the 'biggest' burst packet [packet that fits after RGB in burst mode]"
line.long 0x20 "DSI_VID_VCA_SETTING2,VCA control register 2"
hexmask.long.word 0x20 16.--31. 1. "MAX_LINE_LIMIT,MAX_LINE_LIMIT: maximum size of the line packet [packet that fits in blanking line]"
hexmask.long.word 0x20 0.--15. 1. "EXACT_BURST_LIMIT,EXACT_BURST_LIMIT: exact maximum size of the burst packet [packet that fits after RGB in burst mode]"
line.long 0x24 "DSI_TVG_CTL,Main control of the TVG"
bitfld.long 0x24 5.--7. "TVG_STRIPE_SIZE,TVG_STRIPE_SIZE: size of the stripe [in pixels] - defined by 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 3.--4. "TVG_MODE,TVG_MODE: TVG display mode" "0,1,2,3"
bitfld.long 0x24 1.--2. "TVG_STOPMODE,TVG_STOPMODE: stop mode" "0,1,2,3"
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bitfld.long 0x24 0. "TVG_RUN,TVG_RUN: start/stop of the TVG" "0,1"
line.long 0x28 "DSI_TVG_IMG_SIZE,TVG Generated image size"
hexmask.long.word 0x28 16.--28. 1. "TVG_NBLINE,TVG_NBLINE: Number of lines per frame"
hexmask.long.word 0x28 0.--14. 1. "TVG_LINE_SIZE,TVG_LINE_SIZE: Number of bytes per line"
line.long 0x2C "DSI_TVG_COLOR1,Color 1 of the dummy frame G. R"
hexmask.long.word 0x2C 12.--23. 1. "COL1_GREEN,COL1_GREEN: green component of the color 1"
hexmask.long.word 0x2C 0.--11. 1. "COL1_RED,COL1_RED: red component of the color 1"
line.long 0x30 "DSI_TVG_COLOR1_BIS,Color 1 of the dummy frame . B"
hexmask.long.word 0x30 0.--11. 1. "COL1_BLUE,COL1_BLUE: blue component of the color 1"
line.long 0x34 "DSI_TVG_COLOR2,Color 2 of the dummy frame. G. R"
hexmask.long.word 0x34 12.--23. 1. "COL2_GREEN,COL2_GREEN: green component of the color 2"
hexmask.long.word 0x34 0.--11. 1. "COL2_RED,COL2_RED: red component of the color 2"
line.long 0x38 "DSI_TVG_COLOR2_BIS,Color 2 of the dummy frame. B"
hexmask.long.word 0x38 0.--11. 1. "COL2_BLUE,COL2_BLUE: blue component of the color 2"
line.long 0x3C "DSI_TVG_STS,TVG status register"
bitfld.long 0x3C 0. "TVG_RUNNING,TVG_RUNNING: status of the TVG" "0,1"
group.long 0x130++0x3B
line.long 0x00 "DSI_MCTL_MAIN_STS_CTL,Controls the enabling and edge detection of main ctrl status bits EDGE = 0 captures the rising edge of the event. EDGE= 1 captures falling edge"
bitfld.long 0x00 25. "IF3_UNTERM_PCK_ERR_EDGE,IF3_UNTERM_PCK_ERR_EDGE: edge detection of if3_unterm_pck_err" "0,1"
bitfld.long 0x00 24. "IF1_UNTERM_PCK_ERR_EDGE,IF1_UNTERM_PCK_ERR_EDGE: edge detection of if1_unterm_pck_err" "0,1"
bitfld.long 0x00 23. "LPRX_TO_ERR_EDGE,LPRX_TO_ERR_EDGE: edge detection of LP_RX time-out error" "0,1"
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bitfld.long 0x00 22. "HSTX_TO_ERR_EDGE,HSTX_TO_ERR_EDGE: edge detection of HS_TX time-out error" "0,1"
bitfld.long 0x00 21. "DAT4_READY_EDGE,DAT4_READY_EDGE: edge detection of dat4_ready" "0,1"
bitfld.long 0x00 20. "DAT3_READY_EDGE,DAT3_READY_EDGE: edge detection of dat3_ready" "0,1"
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bitfld.long 0x00 19. "DAT2_READY_EDGE,DAT2_READY_EDGE: edge detection of dat2_ready" "0,1"
bitfld.long 0x00 18. "DAT1_READY_EDGE,DAT1_READY_EDGE: edge detection of dat1_ready" "0,1"
bitfld.long 0x00 17. "CLKLANE_READY_EDGE,CLKLANE_READY_EDGE: edge detection of clklane_ready" "0,1"
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bitfld.long 0x00 16. "PLL_LOCK_EDGE,PLL_LOCK_EDGE: edge detection of PLL lock" "0,1"
bitfld.long 0x00 9. "IF3_UNTERM_PCK_ERR_EN,IF3_UNTERM_PCK_ERR_EN: enables if3_unterm_pck_err" "0,1"
bitfld.long 0x00 8. "IF1_UNTERM_PCK_ERR_EN,IF1_UNTERM_PCK_ERR_EN: enables if1_unterm_pck_err" "0,1"
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bitfld.long 0x00 7. "LPRX_TO_ERR_EN,LPRX_TO_ERR_EN: enables lprx_to_err" "0,1"
bitfld.long 0x00 6. "HSTX_TO_ERR_EN,HSTX_TO_ERR_EN: enables hstx_to_err" "0,1"
bitfld.long 0x00 5. "DAT4_READY_EN,DAT4_READY_EN: enables dat4_ready" "0,1"
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bitfld.long 0x00 4. "DAT3_READY_EN,DAT3_READY_EN: enables dat3_ready" "0,1"
bitfld.long 0x00 3. "DAT2_READY_EN,DAT2_READY_EN: enables dat2_ready" "0,1"
bitfld.long 0x00 2. "DAT1_READY_EN,DAT1_READY_EN: enables dat1_ready" "0,1"
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bitfld.long 0x00 1. "CLKLANE_READY_EN,CLKLANE_READY_EN: enables clklane_ready" "0,1"
bitfld.long 0x00 0. "PLL_LOCK_EN,PLL_LOCK_EN: enables PLL lock" "0,1"
line.long 0x04 "DSI_CMD_MODE_STS_CTL,Controls the enabling and edge detection of command status bits EDGE = 0 captures the rising edge of the event. EDGE= 1 captures falling edge"
bitfld.long 0x04 21. "ERR_IF3_UNDERRUN_EDGE,ERR_IF3_UNDERRUN_EDGE: edge detection of err_IF3_underrun" "0,1"
bitfld.long 0x04 20. "ERR_IF1_UNDERRUN_EDGE,ERR_IF1_UNDERRUN_EDGE: edge detection of err_IF1_underrun" "0,1"
bitfld.long 0x04 19. "ERR_UNWANTED_RD_EDGE,ERR_UNWANTED_RD_EDGE: edge detection of err_unwanted_rd" "0,1"
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bitfld.long 0x04 18. "ERR_TE_MISS_EDGE,ERR_TE_MISS_EDGE: edge detection of err_te_miss" "0,1"
bitfld.long 0x04 17. "ERR_NO_TE_EDGE,ERR_NO_TE_EDGE: edge detection of err_no_te" "0,1"
bitfld.long 0x04 16. "CSM_RUNNING_EDGE,CSM_RUNNING_EDGE: edge detection of CSM running" "0,1"
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bitfld.long 0x04 5. "ERR_IF3_UNDERRUN_EN,ERR_IF3_UNDERRUN_EN: enables err_IF3_underrun" "0,1"
bitfld.long 0x04 4. "ERR_IF1_UNDERRUN_EN,ERR_IF1_UNDERRUN_EN: enables err_IF1_underrun" "0,1"
bitfld.long 0x04 3. "ERR_UNWANTED_RD_EN,ERR_UNWANTED_RD_EN: enables err_unwanted_rd" "0,1"
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bitfld.long 0x04 2. "ERR_TE_MISS_EN,ERR_TE_MISS_EN: enables err_te_miss" "0,1"
bitfld.long 0x04 1. "ERR_NO_TE_EN,ERR_NO_TE_EN: enables err_no_te" "0,1"
bitfld.long 0x04 0. "CSM_RUNNING_EN,CSM_RUNNING_EN: enables signaling of CSM running" "0,1"
line.long 0x08 "DSI_DIRECT_CMD_STS_CTL,Controls the enabling and edge detection of Direct Command status bits"
bitfld.long 0x08 26. "READ_COMPLETED_WITH_ERR_EDGE,READ_COMPLETED_WITH_ERR_EDGE: edge detection of read detection completed with errors" "0,1"
bitfld.long 0x08 25. "BTA_FINISHED_EDGE,BTA_FINISHED_EDGE: edge detection of BTA completion detection" "0,1"
bitfld.long 0x08 24. "BTA_COMPLETED_EDGE,BTA_COMPLETED_EDGE: edge detection of BTA request completed" "0,1"
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bitfld.long 0x08 23. "TE_RECEIVED_EDGE,TE_RECEIVED_EDGE: edge detection of TE received" "0,1"
bitfld.long 0x08 22. "TRIGGER_RECEIVED_EDGE,TRIGGER_RECEIVED_EDGE: edge detection of trigger" "0,1"
bitfld.long 0x08 21. "ACKNOWLEDGE_WITH_ERR_EDGE,ACKNOWLEDGE_WITH_ERR_EDGE: edge detection of acknowledge with error" "0,1"
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bitfld.long 0x08 20. "ACKNOWLEDGE_RECEIVED_EDGE,ACKNOWLEDGE_RECEIVED_EDGE: edge detection of acknowledge" "0,1"
bitfld.long 0x08 19. "READ_COMPLETED_EDGE,READ_COMPLETED_EDGE: edge detection of read request completed" "0,1"
bitfld.long 0x08 18. "TRIGGER_COMPLETED_EDGE,TRIGGER_COMPLETED_EDGE: edge detection of trigger request completed" "0,1"
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bitfld.long 0x08 17. "WRITE_COMPLETED_EDGE,WRITE_COMPLETED_EDGE: edge detection of detection of write request completed" "0,1"
bitfld.long 0x08 16. "CMD_TRANSMISSION_EDGE,CMD_TRANSMISSION_EDGE: edge detection of cmd_transmission" "0,1"
bitfld.long 0x08 10. "READ_COMPLETED_WITH_ERR_EN,READ_COMPLETED_WITH_ERR_EN: enables detection of read completed with errors" "0,1"
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bitfld.long 0x08 9. "BTA_FINISHED_EN,BTA_FINISHED_EN: enables BTA completion detection" "0,1"
bitfld.long 0x08 8. "BTA_COMPLETED_EN,BTA_COMPLETED_EN: enables BTA request completed" "0,1"
bitfld.long 0x08 7. "TE_RECEIVED_EN,TE_RECEIVED_EN: enables TE received" "0,1"
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bitfld.long 0x08 6. "TRIGGER_RECEIVED_EN,TRIGGER_RECEIVED_EN: enables trigger" "0,1"
bitfld.long 0x08 5. "ACKNOWLEDGE_WITH_ERR_EN,ACKNOWLEDGE_WITH_ERR_EN: enables acknowledge with error" "0,1"
bitfld.long 0x08 4. "ACKNOWLEDGE_RECEIVED_EN,ACKNOWLEDGE_RECEIVED_EN: enables acknowledge" "0,1"
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bitfld.long 0x08 3. "READ_COMPLETED_EN,READ_COMPLETED_EN: enables read request completed" "0,1"
bitfld.long 0x08 2. "TRIGGER_COMPLETED_EN,TRIGGER_COMPLETED_EN: enables trigger_completed" "0,1"
bitfld.long 0x08 1. "WRITE_COMPLETED_EN,WRITE_COMPLETED_EN: enables write_completed" "0,1"
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bitfld.long 0x08 0. "CMD_TRANSMISSION_EN,CMD_TRANSMISSION_EN: enables detection of cmd_transmission" "0,1"
line.long 0x0C "DSI_DIRECT_CMD_RD_STS_CTL,Controls the enabling and edge detection of read commands error"
bitfld.long 0x0C 24. "ERR_EOT_WITH_ERR_EDGE,ERR_EOT_WITH_ERR_EDGE: edge detection of err_eot_with_err" "0,1"
bitfld.long 0x0C 23. "ERR_MISSING_EOT_EDGE,ERR_MISSING_EOT_EDGE: edge detection of err_missing_eot" "0,1"
bitfld.long 0x0C 22. "ERR_WRONG_LENGTH_EDGE,ERR_WRONG_LENGTH_EDGE: edge detection of err_wrong_length" "0,1"
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bitfld.long 0x0C 21. "ERR_OVERSIZE_EDGE,ERR_OVERSIZE_EDGE: edge detection of err_oversize" "0,1"
bitfld.long 0x0C 20. "ERR_RECEIVE_EDGE,ERR_RECEIVE_EDGE: edge detection of err_receive" "0,1"
bitfld.long 0x0C 19. "ERR_UNDECODABLE_EDGE,ERR_UNDECODABLE_EDGE: edge detection of err_undecodable" "0,1"
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bitfld.long 0x0C 18. "ERR_CHECKSUM_EDGE,ERR_CHECKSUM_EDGE: edge detection of err_checksum" "0,1"
bitfld.long 0x0C 17. "ERR_UNCORRECTABLE_EDGE,ERR_UNCORRECTABLE_EDGE: edge detection of err_uncorrectable" "0,1"
bitfld.long 0x0C 16. "ERR_FIXED_EDGE,ERR_FIXED_EDGE: edge detection of err_fixed" "0,1"
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bitfld.long 0x0C 8. "ERR_EOT_WITH_ERR_EN,ERR_EOT_WITH_ERR_EN: enables err_eot_with_err" "0,1"
bitfld.long 0x0C 7. "ERR_MISSING_EOT_EN,ERR_MISSING_EOT_EN: enables err_missing_eot" "0,1"
bitfld.long 0x0C 6. "ERR_WRONG_LENGTH_EN,ERR_WRONG_LENGTH_EN: enables err_wrong_length" "0,1"
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bitfld.long 0x0C 5. "ERR_OVERSIZE_EN,ERR_OVERSIZE_EN: enables err_oversize" "0,1"
bitfld.long 0x0C 4. "ERR_RECEIVE_EN,ERR_RECEIVE_EN: enables err_receive" "0,1"
bitfld.long 0x0C 3. "ERR_UNDECODABLE_EN,ERR_UNDECODABLE_EN: enables err_undecodable" "0,1"
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bitfld.long 0x0C 2. "ERR_CHECKSUM_EN,ERR_CHECKSUM_EN: enables err_checksum" "0,1"
bitfld.long 0x0C 1. "ERR_UNCORRECTABLE_EN,ERR_UNCORRECTABLE_EN: enables err_uncorrectable" "0,1"
bitfld.long 0x0C 0. "ERR_FIXED_EN,ERR_FIXED_EN: enables err_fixed" "0,1"
line.long 0x10 "DSI_VID_MODE_STS_CTL,Control the enabling and edge detection of VSG status bits"
bitfld.long 0x10 26. "VSG_RECOVERY_EDGE,VSG_RECOVERY_EDGE: edge detection of vsg_recovery" "0,1"
bitfld.long 0x10 25. "ERR_VRS_WRONG_LENGTH_EDGE,ERR_VRS_WRONG_LENGTH_EDGE: edge detection of err_vrs_wrong_length" "0,1"
bitfld.long 0x10 24. "ERR_LONGREAD_EDGE,ERR_LONGREAD_EDGE: edge detection of err_longread" "0,1"
newline
bitfld.long 0x10 23. "ERR_LINEWRITE_EDGE,ERR_LINEWRITE_EDGE: edge detection of err_line_" "0,1"
bitfld.long 0x10 22. "ERR_BURSTWRITE_EDGE,ERR_BURSTWRITE_EDGE: edge detection of err_burst_" "0,1"
bitfld.long 0x10 21. "ERR_SMALL_HEIGHT_EDGE,ERR_SMALL_HEIGHT_EDGE: edge detection of unaligned line number" "0,1"
newline
bitfld.long 0x10 20. "ERR_SMALL_LENGTH_EDGE,ERR_SMALL_LENGTH_EDGE: edge detection of unaligned size" "0,1"
bitfld.long 0x10 19. "ERR_MISSING_VSYNC_EDGE,ERR_MISSING_VSYNC_EDGE: edge detection of detection of missing VSYNC" "0,1"
bitfld.long 0x10 18. "ERR_MISSING_HSYNC_EDGE,ERR_MISSING_HSYNC_EDGE: edge detection of detection of missing HSYNC" "0,1"
newline
bitfld.long 0x10 17. "ERR_MISSING_DATA_EDGE,ERR_MISSING_DATA_EDGE: edge detection of data miss detection" "0,1"
bitfld.long 0x10 16. "VSG_RUNNING_EDGE,VSG_RUNNING_EDGE: edge detection of VSG status observation" "0,1"
bitfld.long 0x10 10. "VSG_RECOVERY_EN,VSG_RECOVERY_EN: enables vsg_recovery" "0,1"
newline
bitfld.long 0x10 9. "ERR_VRS_WRONG_LENGTH_EN,ERR_VRS_WRONG_LENGTH_EN: enables err_vrs_wrong_length" "0,1"
bitfld.long 0x10 8. "ERR_LONGREAD_EN,ERR_LONGREAD_EN: enables err_longread" "0,1"
bitfld.long 0x10 7. "ERR_LINEWRITE_EN,ERR_LINEWRITE_EN: enables err_line_" "0,1"
newline
bitfld.long 0x10 6. "ERR_BURSTWRITE_EN,ERR_BURSTWRITE_EN: enables err_burst_" "0,1"
bitfld.long 0x10 5. "ERR_SMALL_HEIGHT_EN,ERR_SMALL_HEIGHT_EN: enables detection of unaligned line number" "0,1"
bitfld.long 0x10 4. "ERR_SMALL_LENGTH_EN,ERR_SMALL_LENGTH_EN: enables detection of unaligned size" "0,1"
newline
bitfld.long 0x10 3. "ERR_MISSING_VSYNC_EN,ERR_MISSING_VSYNC_EN: enables detection of missing VSYNC" "0,1"
bitfld.long 0x10 2. "ERR_MISSING_HSYNC_EN,ERR_MISSING_HSYNC_EN: enables detection of missing HSYNC" "0,1"
bitfld.long 0x10 1. "ERR_MISSING_DATA_EN,ERR_MISSING_DATA_EN: enables data miss detection" "0,1"
newline
bitfld.long 0x10 0. "VSG_RUNNING_EN,VSG_RUNNING_EN: enables VSG status observation" "0,1"
line.long 0x14 "DSI_TVG_STS_CTL,Control the enabling and edge detection of TVG status bits"
bitfld.long 0x14 16. "TVG_STS_EDGE,TVG_STS_EDGE: edge detection of TVG status observation" "0,1"
bitfld.long 0x14 0. "TVG_STS_EN,TVG_STS_EN: enables TVG status observation" "0,1"
line.long 0x18 "DSI_MCTL_DPHY_ERR_CTL1,Controls the enabling and edge detection of the DPHY errors"
bitfld.long 0x18 25. "ERR_CONT_LP1_4_EN,ERR_CONT_LP1_4_EN" "0,1"
bitfld.long 0x18 24. "ERR_CONT_LP1_3_EN,ERR_CONT_LP1_3_EN" "0,1"
bitfld.long 0x18 23. "ERR_CONT_LP1_2_EN,ERR_CONT_LP1_2_EN" "0,1"
newline
bitfld.long 0x18 22. "ERR_CONT_LP1_1_EN,ERR_CONT_LP1_1_EN" "0,1"
bitfld.long 0x18 21. "ERR_CONT_LP0_4_EN,ERR_CONT_LP0_4_EN" "0,1"
bitfld.long 0x18 20. "ERR_CONT_LP0_3_EN,ERR_CONT_LP0_3_EN" "0,1"
newline
bitfld.long 0x18 19. "ERR_CONT_LP0_2_EN,ERR_CONT_LP0_2_EN" "0,1"
bitfld.long 0x18 18. "ERR_CONT_LP0_1_EN,ERR_CONT_LP0_1_EN" "0,1"
bitfld.long 0x18 17. "ERR_CONTROL_4_EN,ERR_CONTROL_4_EN" "0,1"
newline
bitfld.long 0x18 16. "ERR_CONTROL_3_EN,ERR_CONTROL_3_EN" "0,1"
bitfld.long 0x18 15. "ERR_CONTROL_2_EN,ERR_CONTROL_2_EN" "0,1"
bitfld.long 0x18 14. "ERR_CONTROL_1_EN,ERR_CONTROL_1_EN" "0,1"
newline
bitfld.long 0x18 13. "ERR_SYNCESC_4_EN,ERR_SYNCESC_4_EN" "0,1"
bitfld.long 0x18 12. "ERR_SYNCESC_3_EN,ERR_SYNCESC_3_EN" "0,1"
bitfld.long 0x18 11. "ERR_SYNCESC_2_EN,ERR_SYNCESC_2_EN" "0,1"
newline
bitfld.long 0x18 10. "ERR_SYNCESC_1_EN,ERR_SYNCESC_1_EN" "0,1"
bitfld.long 0x18 9. "ERR_ESC_4_EN,ERR_ESC_4_EN" "0,1"
bitfld.long 0x18 8. "ERR_ESC_3_EN,ERR_ESC_3_EN" "0,1"
newline
bitfld.long 0x18 7. "ERR_ESC_2_EN,ERR_ESC_2_EN" "0,1"
bitfld.long 0x18 6. "ERR_ESC_1_EN,ERR_ESC_1_EN" "0,1"
line.long 0x1C "DSI_MCTL_DPHY_ERR_CTL2,Controls he enabling and edge detection of the DPHY errors"
bitfld.long 0x1C 19. "ERR_CONT_LP1_4_EDGE,ERR_CONT_LP1_4_EDGE" "0,1"
bitfld.long 0x1C 18. "ERR_CONT_LP1_3_EDGE,ERR_CONT_LP1_3_EDGE" "0,1"
bitfld.long 0x1C 17. "ERR_CONT_LP1_2_EDGE,ERR_CONT_LP1_2_EDGE" "0,1"
newline
bitfld.long 0x1C 16. "ERR_CONT_LP1_1_EDGE,ERR_CONT_LP1_1_EDGE" "0,1"
bitfld.long 0x1C 15. "ERR_CONT_LP0_4_EDGE,ERR_CONT_LP0_4_EDGE" "0,1"
bitfld.long 0x1C 14. "ERR_CONT_LP0_3_EDGE,ERR_CONT_LP0_3_EDGE" "0,1"
newline
bitfld.long 0x1C 13. "ERR_CONT_LP0_2_EDGE,ERR_CONT_LP0_2_EDGE" "0,1"
bitfld.long 0x1C 12. "ERR_CONT_LP0_1_EDGE,ERR_CONT_LP0_1_EDGE" "0,1"
bitfld.long 0x1C 11. "ERR_CONTROL_4_EDGE,ERR_CONTROL_4_EDGE" "0,1"
newline
bitfld.long 0x1C 10. "ERR_CONTROL_3_EDGE,ERR_CONTROL_3_EDGE" "0,1"
bitfld.long 0x1C 9. "ERR_CONTROL_2_EDGE,ERR_CONTROL_2_EDGE" "0,1"
bitfld.long 0x1C 8. "ERR_CONTROL_1_EDGE,ERR_CONTROL_1_EDGE" "0,1"
newline
bitfld.long 0x1C 7. "ERR_SYNCESC_4_EDGE,ERR_SYNCESC_4_EDGE" "0,1"
bitfld.long 0x1C 6. "ERR_SYNCESC_3_EDGE,ERR_SYNCESC_3_EDGE" "0,1"
bitfld.long 0x1C 5. "ERR_SYNCESC_2_EDGE,ERR_SYNCESC_2_EDGE" "0,1"
newline
bitfld.long 0x1C 4. "ERR_SYNCESC_1_EDGE,ERR_SYNCESC_1_EDGE" "0,1"
bitfld.long 0x1C 3. "ERR_ESC_4_EDGE,ERR_ESC_4_EDGE" "0,1"
bitfld.long 0x1C 2. "ERR_ESC_3_EDGE,ERR_ESC_3_EDGE" "0,1"
newline
bitfld.long 0x1C 1. "ERR_ESC_2_EDGE,ERR_ESC_2_EDGE" "0,1"
bitfld.long 0x1C 0. "ERR_ESC_1_EDGE,ERR_ESC_1_EDGE" "0,1"
line.long 0x20 "DSI_MCTL_MAIN_STS_CLR,Main control status register clear function"
bitfld.long 0x20 9. "IF3_UNTERM_PCK_ERR_CLR,IF3_UNTERM_PCK_ERR_CLR: clears if3_unterm_pck_err" "0,1"
bitfld.long 0x20 8. "IF1_UNTERM_PCK_ERR_CLR,IF1_UNTERM_PCK_ERR_CLR: clears if1_unterm_pck_err" "0,1"
bitfld.long 0x20 7. "LPRX_TO_ERR_CLR,LPRX_TO_ERR_CLR: clears lprx_to_err" "0,1"
newline
bitfld.long 0x20 6. "HSTX_TO_ERR_CLR,HSTX_TO_ERR_CLR: clears hstx_to_err" "0,1"
bitfld.long 0x20 5. "DAT4_READY_CLR,DAT4_READY_CLR: clears dat4_ready" "0,1"
bitfld.long 0x20 4. "DAT3_READY_CLR,DAT3_READY_CLR: clears dat3_ready" "0,1"
newline
bitfld.long 0x20 3. "DAT2_READY_CLR,DAT2_READY_CLR: clears dat2_ready" "0,1"
bitfld.long 0x20 2. "DAT1_READY_CLR,DAT1_READY_CLR: clears dat1_ready" "0,1"
bitfld.long 0x20 1. "CLKLANE_READY_CLR,CLKLANE_READY_CLR: clears clklane_ready" "0,1"
newline
bitfld.long 0x20 0. "PLL_LOCK_CLR,PLL_LOCK_CLR: clears PLL lock" "0,1"
line.long 0x24 "DSI_CMD_MODE_STS_CLR,Command status register clear function"
rbitfld.long 0x24 5. "ERR_IF3_UNDERRUN_CLR,ERR_IF3_UNDERRUN_CLR: clears err_IF3_underrun" "0,1"
bitfld.long 0x24 4. "ERR_IF1_UNDERRUN_CLR,ERR_IF1_UNDERRUN_CLR: clears err_IF1_underrun" "0,1"
bitfld.long 0x24 3. "ERR_UNWANTED_RD_CLR,ERR_UNWANTED_RD_CLR: clears err_unwanted_rd" "0,1"
newline
bitfld.long 0x24 2. "ERR_TE_MISS_CLR,ERR_TE_MISS_CLR: clears err_te_miss" "0,1"
bitfld.long 0x24 1. "ERR_NO_TE_CLR,ERR_NO_TE_CLR: clears err_no_te" "0,1"
bitfld.long 0x24 0. "CSM_RUNNING_CLR,CSM_RUNNING_CLR: clears CSM running bit" "0,1"
line.long 0x28 "DSI_DIRECT_CMD_STS_CLR,Direct command status register clear function"
bitfld.long 0x28 10. "READ_COMPLETED_WITH_ERR_CLR,READ_COMPLETED_WITH_ERR_CLR: clears detection of read completed with errors" "0,1"
bitfld.long 0x28 9. "BTA_FINISHED_CLR,BTA_FINISHED_CLR: clears BTA completion detection" "0,1"
bitfld.long 0x28 8. "BTA_COMPLETED_CLR,BTA_COMPLETED_CLR: clears BTA request completed" "0,1"
newline
bitfld.long 0x28 7. "TE_RECEIVED_CLR,TE_RECEIVED_CLR: clears TE received" "0,1"
bitfld.long 0x28 6. "TRIGGER_RECEIVED_CLR,TRIGGER_RECEIVED_CLR: clears trigger" "0,1"
bitfld.long 0x28 5. "ACK_WITH_ERR_CLR,ACKNOWLEDGE_WITH_ERR_CLR: clears acknowledge with errors" "0,1"
newline
bitfld.long 0x28 4. "ACK_RECEIVED_CLR,ACKNOWLEDGE_RECEIVED_CLR: clears acknowledge" "0,1"
bitfld.long 0x28 3. "READ_COMPLETED_CLR,READ_COMPLETED_CLR: clears read request completed" "0,1"
bitfld.long 0x28 2. "TRIGGER_COMPLETED_CLR,TRIGGER_COMPLETED_CLR: clears trigger request completed" "0,1"
newline
bitfld.long 0x28 1. "WRITE_COMPLETED_CLR,WRITE_COMPLETED_CLR: clears detection of write request completed" "0,1"
bitfld.long 0x28 0. "CMD_TRANSMISSION_CLR,CMD_TRANSMISSION_CLR: clears cmd_transmission" "0,1"
line.long 0x2C "DSI_DIRECT_CMD_RD_STS_CLR,Direct command read status register clear function"
bitfld.long 0x2C 8. "ERR_EOT_WITH_ERR_CLR,ERR_EOT_WITH_ERR_CLR: clears err_eot_with_err" "0,1"
bitfld.long 0x2C 7. "ERR_MISSING_EOT_CLR,ERR_MISSING_EOT_CLR: clears err_missing_eot" "0,1"
bitfld.long 0x2C 6. "ERR_WRONG_LENGTH_CLR,ERR_WRONG_LENGTH_CLR: clears err_wrong_length" "0,1"
newline
bitfld.long 0x2C 5. "ERR_OVERSIZE_CLR,ERR_OVERSIZE_CLR: clears err_oversize" "0,1"
bitfld.long 0x2C 4. "ERR_RECEIVE_CLR,ERR_RECEIVE_CLR: clears err_receive" "0,1"
bitfld.long 0x2C 3. "ERR_UNDECODABLE_CLR,ERR_UNDECODABLE_CLR: clears err_undecodable" "0,1"
newline
bitfld.long 0x2C 2. "ERR_CHECKSUM_CLR,ERR_CHECKSUM_CLR: clears err_checksum" "0,1"
bitfld.long 0x2C 1. "ERR_UNCORRECTABLE_CLR,ERR_UNCORRECTABLE_CLR: clears err_uncorrectable" "0,1"
bitfld.long 0x2C 0. "ERR_FIXED_CLR,ERR_FIXED_CLR: clears err_fixed" "0,1"
line.long 0x30 "DSI_VID_MODE_STS_CLR,VSG status register clear function"
bitfld.long 0x30 10. "VSG_RECOVERY_CLR,VSG_RECOVERY_CLR: clears the bit vsg_recovery" "0,1"
bitfld.long 0x30 9. "ERR_VRS_WRONG_LENGTH_CLR,ERR_VRS_WRONG_LENGTH_CLR: clears the bit err_vid_wrong_length" "0,1"
bitfld.long 0x30 8. "ERR_LONGREAD_CLR,ERR_LONGREAD_CLR: clears err_longread" "0,1"
newline
bitfld.long 0x30 7. "ERR_LINEWRITE_CLR,ERR_LINEWRITE_CLR: clears err_line" "0,1"
bitfld.long 0x30 6. "ERR_BURSTWRITE_CLR,ERR_BURSTWRITE_CLR: clears err_burst" "0,1"
bitfld.long 0x30 5. "ERR_SMALL_HEIGHT_CLR,ERR_SMALL_HEIGHT_CLR: clears unaligned line number" "0,1"
newline
bitfld.long 0x30 4. "ERR_SMALL_LENGTH_CLR,ERR_SMALL_LENGTH_CLR: clears analigned size" "0,1"
bitfld.long 0x30 3. "ERR_MISSING_VSYNC_CLR,ERR_MISSING_VSYNC_CLR: clears missing VSYNC" "0,1"
bitfld.long 0x30 2. "ERR_MISSING_HSYNC_CLR,ERR_MISSING_HSYNC_CLR: clears missing HSYNC" "0,1"
newline
bitfld.long 0x30 1. "ERR_MISSING_DATA_CLR,ERR_MISSING_DATA_CLR: clears data miss" "0,1"
bitfld.long 0x30 0. "VSG_STS_CLR,VSG_STS_CLR: clears VSG status" "0,1"
line.long 0x34 "DSI_TG_STS_CLR,TVG status register clear function"
bitfld.long 0x34 0. "TVG_STS_CLR,TVG_STS_CLR: clears TVG status observation" "0,1"
line.long 0x38 "DSI_MCTL_DPHY_ERR_CLR,D_PHY lanes output register clear function"
bitfld.long 0x38 25. "ERR_CONT_LP1_4_CLR,ERR_CONT_LP1_4_CLR" "0,1"
bitfld.long 0x38 24. "ERR_CONT_LP1_3_CLR,ERR_CONT_LP1_3_CLR" "0,1"
bitfld.long 0x38 23. "ERR_CONT_LP1_2_CLR,ERR_CONT_LP1_2_CLR" "0,1"
newline
bitfld.long 0x38 22. "ERR_CONT_LP1_1_CLR,ERR_CONT_LP1_1_CLR" "0,1"
bitfld.long 0x38 21. "ERR_CONT_LP0_4_CLR,ERR_CONT_LP0_4_CLR" "0,1"
bitfld.long 0x38 20. "ERR_CONT_LP0_3_CLR,ERR_CONT_LP0_3_CLR" "0,1"
newline
bitfld.long 0x38 19. "ERR_CONT_LP0_2_CLR,ERR_CONT_LP0_2_CLR" "0,1"
bitfld.long 0x38 18. "ERR_CONT_LP0_1_CLR,ERR_CONT_LP0_1_CLR" "0,1"
bitfld.long 0x38 17. "ERR_CONTROL_4_CLR,ERR_CONTROL_4_CLR" "0,1"
newline
bitfld.long 0x38 16. "ERR_CONTROL_3_CLR,ERR_CONTROL_3_CLR" "0,1"
bitfld.long 0x38 15. "ERR_CONTROL_2_CLR,ERR_CONTROL_2_CLR" "0,1"
bitfld.long 0x38 14. "ERR_CONTROL_1_CLR,ERR_CONTROL_1_CLR" "0,1"
newline
bitfld.long 0x38 13. "ERR_SYNCESC_4_CLR,ERR_SYNCESC_4_CLR" "0,1"
bitfld.long 0x38 12. "ERR_SYNCESC_3_CLR,ERR_SYNCESC_3_CLR" "0,1"
bitfld.long 0x38 11. "ERR_SYNCESC_2_CLR,ERR_SYNCESC_2_CLR" "0,1"
newline
bitfld.long 0x38 10. "ERR_SYNCESC_1_CLR,ERR_SYNCESC_1_CLR" "0,1"
bitfld.long 0x38 9. "ERR_ESC_4_CLR,ERR_ESC_4_CLR" "0,1"
bitfld.long 0x38 8. "ERR_ESC_3_CLR,ERR_ESC_3_CLR" "0,1"
newline
bitfld.long 0x38 7. "ERR_ESC_2_CLR,ERR_ESC_2_CLR" "0,1"
bitfld.long 0x38 6. "ERR_ESC_1_CLR,ERR_ESC_1_CLR" "0,1"
rgroup.long 0x170++0x1B
line.long 0x00 "DSI_MCTL_MAIN_STS_FLAG,Main control status Flag registers"
bitfld.long 0x00 9. "IF3_UNTERM_PCK_ERR_FLAG,IF3_UNTERM_PCK_ERR_FLAG: flags if3_unterm_pck_err" "0,1"
bitfld.long 0x00 8. "IF1_UNTERM_PCK_ERR_FLAG,IF1_UNTERM_PCK_ERR_FLAG: flags if1_unterm_pck_err" "0,1"
bitfld.long 0x00 7. "LPRX_TO_ERR_FLAG,LPRX_TO_ERR_FLAG: flags lprx_to_err" "0,1"
newline
bitfld.long 0x00 6. "HSTX_TO_ERR_FLAG,HSTX_TO_ERR_FLAG: flags hstx_to_err" "0,1"
bitfld.long 0x00 5. "DAT4_READY_FLAG,DAT4_READY_FLAG: flags dat4_ready" "0,1"
bitfld.long 0x00 4. "DAT3_READY_FLAG,DAT3_READY_FLAG: flags dat3_ready" "0,1"
newline
bitfld.long 0x00 3. "DAT2_READY_FLAG,DAT2_READY_FLAG: flags dat2_ready" "0,1"
bitfld.long 0x00 2. "DAT1_READY_FLAG,DAT1_READY_FLAG: flags dat1_ready" "0,1"
bitfld.long 0x00 1. "CLKLANE_READY_FLAG,CLKLANE_READY_FLAG: flags clklane_ready" "0,1"
newline
bitfld.long 0x00 0. "PLL_LOCK_FLAG,PLL_LOCK_FLAG: flags PLL lock" "0,1"
line.long 0x04 "DSI_CMD_MODE_STS_FLAG,Command Mode status"
bitfld.long 0x04 5. "ERR_IF3_UNDERRUN_FLAG,ERR_IF3_UNDERRUN_FLAG: flags err_IF3_underrun" "0,1"
bitfld.long 0x04 4. "ERR_IF1_UNDERRUN_FLAG,ERR_IF1_UNDERRUN_FLAG: flags err_IF1_underrun" "0,1"
bitfld.long 0x04 3. "ERR_UNWANTED_RD_FLAG,ERR_UNWANTED_RD_FLAG: flags fixed_err" "0,1"
newline
bitfld.long 0x04 2. "ERR_TE_MISS_FLAG,ERR_TE_MISS_FLAG: flags err_te_miss" "0,1"
bitfld.long 0x04 1. "ERR_NO_TE_FLAG,ERR_NO_TE_FLAG: flags err_no_te" "0,1"
bitfld.long 0x04 0. "CSM_RUNNING_FLAG,CSM_RUNNING_FLAG: flags remaining_err" "0,1"
line.long 0x08 "DSI_DIRECT_CMD_STS_FLAG,Direct command mode status"
bitfld.long 0x08 10. "READ_COMPLETED_WITH_ERR_FLAG,READ_COMPLETED_WITH_ERR_FLAG: flags detection of read completed with errors" "0,1"
bitfld.long 0x08 9. "BTA_FINISHED_FLAG,BTA_FINISHED_FLAG: flags BTA completion detection" "0,1"
bitfld.long 0x08 8. "BTA_COMPLETED_FLAG,BTA_COMPLETED_FLAG: flags BTA request completed" "0,1"
newline
bitfld.long 0x08 7. "TE_RECEIVED_FLAG,TE_RECEIVED_FLAG: flags TE received" "0,1"
bitfld.long 0x08 6. "TRIGGER_RECEIVED_FLAG,TRIGGER_RECEIVED_FLAG: flags trigger" "0,1"
bitfld.long 0x08 5. "ACK_WITH_ERR_RECEIVED_FLAG,ACK_WITH_ERR_RECEIVED_FLAG: flag acknowledge with error detection" "0,1"
newline
bitfld.long 0x08 4. "ACKNOWLEDGE_RECEIVED_FLAG,ACKNOWLEDGE_RECEIVED_FLAG: flags acknowledge" "0,1"
bitfld.long 0x08 3. "READ_COMPLETED_FLAG,READ_COMPLETED_FLAG: flags read request completed" "0,1"
bitfld.long 0x08 2. "TRIGGER_COMPLETED_FLAG,TRIGGER_COMPLETED_FLAG: flags trigger request completed" "0,1"
newline
bitfld.long 0x08 1. "WRITE_COMPLETED_FLAG,WRITE_COMPLETED_FLAG: flags detection of write request completed" "0,1"
bitfld.long 0x08 0. "CMD_TRANSMISSION_FLAG,CMD_TRANSMISSION_FLAG: flags cmd_transmission" "0,1"
line.long 0x0C "DSI_DIRECT_CMD_RD_STS_FLAG,Direct command read status bits"
bitfld.long 0x0C 8. "ERR_EOT_WITH_ERR_FLAG,ERR_EOT_WITH_ERR_FLAG: flags err_eot_with_err" "0,1"
bitfld.long 0x0C 7. "ERR_MISSING_EOT_FLAG,ERR_MISSING_EOT_FLAG: flags err_missing_eot" "0,1"
bitfld.long 0x0C 6. "ERR_WRONG_LENGTH_FLAG,ERR_WRONG_LENGTH_FLAG: flags err_wrong_length" "0,1"
newline
bitfld.long 0x0C 5. "ERR_OVERSIZE_FLAG,ERR_OVERSIZE_FLAG: flags err_oversize" "0,1"
bitfld.long 0x0C 4. "ERR_RECEIVE_FLAG,ERR_RECEIVE_FLAG: flags err_receive" "0,1"
bitfld.long 0x0C 3. "ERR_UNDECODABLE_FLAG,ERR_UNDECODABLE_FLAG: flags err_undecodable" "0,1"
newline
bitfld.long 0x0C 2. "ERR_CHECKSUM_FLAG,ERR_CHECKSUM_FLAG: flags err_checksum" "0,1"
bitfld.long 0x0C 1. "ERR_UNCORRECTABLE_FLAG,ERR_UNCORRECTABLE_FLAG: flags err_uncorrectable" "0,1"
bitfld.long 0x0C 0. "ERR_FIXED_FLAG,ERR_FIXED_FLAG: flags err_fixed" "0,1"
line.long 0x10 "DSI_VID_MODE_STS_FLAG,Video Mode status flag"
bitfld.long 0x10 10. "FLAG_VSG_RECOVERY,FLAG_VSG_RECOVERY: lags vsg_recovery" "0,1"
bitfld.long 0x10 9. "ERR_VRS_WRONG_LENGTH_FLAG,ERR_VRS_WRONG_LENGTH_FLAG: flags err_vrs_wrong_length" "0,1"
bitfld.long 0x10 8. "ERR_LONGREAD_FLAG,ERR_LONGREAD_FLAG: flags err_longread" "0,1"
newline
bitfld.long 0x10 7. "ERR_LONGWRITE_FLAG,ERR_LONGWRITE_FLAG: flags err_long" "0,1"
bitfld.long 0x10 6. "ERR_SHORTWRITE_FLAG,ERR_SHORTWRITE_FLAG: flags err_short" "0,1"
bitfld.long 0x10 5. "ERR_SMALL_HEIGHT_FLAG,ERR_SMALL_HEIGHT_FLAG: flags the detection of unaligned line number" "0,1"
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bitfld.long 0x10 4. "ERR_SMALL_LENGTH_FLAG,ERR_SMALL_LENGTH_FLAG: flags the detection of unaligned size" "0,1"
bitfld.long 0x10 3. "ERR_MISS_VSYNC_FLAG,ERR_MISS_VSYNC_FLAG: flags missing VSYNC" "0,1"
bitfld.long 0x10 2. "ERR_MISSING_HSYNC_FLAG,ERR_MISSING_HSYNC_FLAG: flags missing HSYNC" "0,1"
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bitfld.long 0x10 1. "ERR_MISSING_DATA_FLAG,ERR_MISSING_DATA_FLAG: flags data miss" "0,1"
bitfld.long 0x10 0. "VSG_STS_FLAG,VSG_STS_FLAG: flags VSG status" "0,1"
line.long 0x14 "DSI_TG_STS_FLAG,TVG status Flags"
bitfld.long 0x14 0. "TVG_STS_FLAG,TVG_STS_FLAG: Indicates TVG status observation" "0,1"
line.long 0x18 "DSI_MCTL_DPHY_ERR_FLAG,Errors output from D_PHY lanes - flags error bit"
bitfld.long 0x18 25. "ERR_CONT_LP1_4_FLAG,ERR_CONT_LP1_4_FLAG" "0,1"
bitfld.long 0x18 24. "ERR_CONT_LP1_3_FLAG,ERR_CONT_LP1_3_FLAG" "0,1"
bitfld.long 0x18 23. "ERR_CONT_LP1_2_FLAG,ERR_CONT_LP1_2_FLAG" "0,1"
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bitfld.long 0x18 22. "ERR_CONT_LP1_1_FLAG,ERR_CONT_LP1_1_FLAG" "0,1"
bitfld.long 0x18 21. "ERR_CONT_LP0_4_FLAG,ERR_CONT_LP0_4_FLAG" "0,1"
bitfld.long 0x18 20. "ERR_CONT_LP0_3_FLAG,ERR_CONT_LP0_3_FLAG" "0,1"
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bitfld.long 0x18 19. "ERR_CONT_LP0_2_FLAG,ERR_CONT_LP0_2_FLAG" "0,1"
bitfld.long 0x18 18. "ERR_CONT_LP0_1_FLAG,ERR_CONT_LP0_1_FLAG" "0,1"
bitfld.long 0x18 17. "ERR_CONTROL_4_FLAG,ERR_CONTROL_4_FLAG" "0,1"
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bitfld.long 0x18 16. "ERR_CONTROL_3_FLAG,ERR_CONTROL_3_FLAG" "0,1"
bitfld.long 0x18 15. "ERR_CONTROL_2_FLAG,ERR_CONTROL_2_FLAG" "0,1"
bitfld.long 0x18 14. "ERR_CONTROL_1_FLAG,ERR_CONTROL_1_FLAG" "0,1"
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bitfld.long 0x18 13. "ERR_SYNCESC_4_FLAG,ERR_SYNCESC_4_FLAG" "0,1"
bitfld.long 0x18 12. "ERR_SYNCESC_3_FLAG,ERR_SYNCESC_3_FLAG" "0,1"
bitfld.long 0x18 11. "ERR_SYNCESC_2_FLAG,ERR_SYNCESC_2_FLAG" "0,1"
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bitfld.long 0x18 10. "ERR_SYNCESC_1_FLAG,ERR_SYNCESC_1_FLAG" "0,1"
bitfld.long 0x18 9. "ERR_ESC_4_FLAG,ERR_ESC_4_FLAG" "0,1"
bitfld.long 0x18 8. "ERR_ESC_3_FLAG,ERR_ESC_3_FLAG" "0,1"
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bitfld.long 0x18 7. "ERR_ESC_2_FLAG,ERR_ESC_2_FLAG" "0,1"
bitfld.long 0x18 6. "ERR_ESC_1_FLAG,ERR_ESC_1_FLAG" "0,1"
group.long 0x1A0++0x0F
line.long 0x00 "DSI_DPI_IRQ_EN,DPI interrupt enable"
bitfld.long 0x00 0. "PIXEL_BUF_OVERFLOW_IRQ_EN,Enable DPI FIFO Overflow interrupt" "0,1"
line.long 0x04 "DSI_DPI_IRQ_CLR,DPI interrupt clear register"
bitfld.long 0x04 0. "PIXEL_BUF_OVERFLOW_IRQ_CLR,Clear DPI FIFO Overflow interrupt" "0,1"
line.long 0x08 "DSI_DPI_IRQ_STS,DPI interrupt status"
bitfld.long 0x08 0. "PIXEL_BUF_OVERFLOW_STS,Status of DPI FIFO Overflow interrupt" "0,1"
line.long 0x0C "DSI_DPI_CFG,DPI interface configuration information"
hexmask.long.word 0x0C 16.--31. 1. "DPI_CFG_FIFODEPTH,DPI FIFO"
hexmask.long.word 0x0C 0.--15. 1. "DPI_CFG_FIFO_LEVEL,DPI FIFO fill level - can be read mid-line for debug purposes to allow adjustment of settings"
group.long 0x1F0++0x03
line.long 0x00 "DSI_TEST_GENERIC,Generic test control and status register"
hexmask.long.word 0x00 16.--31. 1. "STATUS,Test status - Value of test_generic_status input"
hexmask.long.word 0x00 0.--15. 1. "CTRL,Test control - Drives test_generic_ctrl output"
rgroup.long 0x1FC++0x17
line.long 0x00 "DSI_ID_REG,ID register for Controller"
hexmask.long.word 0x00 20.--31. 1. "REV_VENDOR_ID,VENDOR_ID: IP vendor ID affected to IP [reset = 0xCAD]"
hexmask.long.byte 0x00 12.--19. 1. "REV_PRODUCT_ID,PRODUCT_ID: unique IP identifier within IP portfolio [reset = 0xD5]"
bitfld.long 0x00 8.--11. "REV_HARDWARE,H: Hardware revision number [reset = 0x1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "REV_X,X: Major revision value [reset = 0x3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "REV_Y,Y: Minor revision value [reset = 0x1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DSI_ASF_INT_STATUS,ASF Interrupt Status Register"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
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bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "DSI_ASF_INT_RAW_STATUS,ASF Interrupt Raw Status Register"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
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bitfld.long 0x08 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
bitfld.long 0x08 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x0C "DSI_ASF_INT_MASK,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
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bitfld.long 0x0C 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt" "0,1"
bitfld.long 0x0C 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "DSI_ASF_INT_TEST,The ASF interrupt test register emulate hardware even"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
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bitfld.long 0x10 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt" "0,1"
bitfld.long 0x10 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x14 "DSI_ASF_FATAL_NONFATAL_SELECT,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered"
bitfld.long 0x14 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x14 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
bitfld.long 0x14 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
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bitfld.long 0x14 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal" "0,1"
bitfld.long 0x14 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
bitfld.long 0x14 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
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bitfld.long 0x14 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x220++0x0B
line.long 0x00 "DSI_ASF_SRAM_CORR_FAULT_STATUS,Status register for SRAM correctable fault"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "DSI_ASF_SRAM_UNCORR_FAULT_STATUS,Status register for SRAM uncorrectable fault"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "DSI_ASF_SRAM_FAULT_STATS,Statistics register for SRAM faults"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x230++0x0B
line.long 0x00 "DSI_ASF_TRANS_TO_CTRL,Control register to configure the ASF transaction timeout monitors"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "DSI_ASF_TRANS_TO_FAULT_MASK,Control register to mask out ASF transaction timeout faults from triggering interrupts"
bitfld.long 0x04 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
bitfld.long 0x04 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
bitfld.long 0x04 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
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bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
line.long 0x08 "DSI_ASF_TRANS_TO_FAULT_STATUS,Status register for transaction timeouts fault"
bitfld.long 0x08 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for transaction timeouts faults" "0,1"
bitfld.long 0x08 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for transaction timeouts faults" "0,1"
bitfld.long 0x08 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for transaction timeouts faults" "0,1"
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bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults" "0,1"
group.long 0x240++0x07
line.long 0x00 "DSI_ASF_PROTOCOL_FAULT_MASK,Control register to mask out ASF Protocol faults from triggering interrupts"
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source" "0,1"
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source" "0,1"
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bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source" "0,1"
line.long 0x04 "DSI_ASF_PROTOCOL_FAULT_STATUS,Status register for protocol faults"
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults" "0,1"
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults" "0,1"
tree.end
tree.end
tree "DSI_WRAP"
tree "DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP"
base ad:0x4710000
rgroup.long 0x00++0x07
line.long 0x00 "DSI_WRAP_REVISION,The REVISION register contains the DSI revision number and PID"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID Field"
bitfld.long 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DSI_WRAP_DPI_CONTROL,Controls the DPI Video Input ports of the DSI Wrapper"
bitfld.long 0x04 4. "DSI2_MUX_SEL,Select between DPI-1 and DPI-2 to drive the DPI input of DSITX2" "0,1"
bitfld.long 0x04 0. "DPI_0_EN,Enable for DPI-0 input" "0,1"
group.long 0x0C++0x07
line.long 0x00 "DSI_WRAP_DPI_SECURE,Controls the DPI Video Input ports SECURE settings"
bitfld.long 0x00 1. "DPI_0_SECURE_VIOLATION,SECURE VIOLATION status for DPI-0 input" "0,1"
bitfld.long 0x00 0. "DPI_0_SECURE,SECURE bit for DPI-0 input" "0,1"
line.long 0x04 "DSI_WRAP_DSI_0_ASF_STATUS,ASF Status"
bitfld.long 0x04 6. "INTEGRITY_ERR,INTEGRITY_ERR" "0,1"
bitfld.long 0x04 5. "PROTOCOL_ERR,PROTOCOL_ERR" "0,1"
bitfld.long 0x04 4. "TRANS_TO_ERR,TRANS_TO_ERR" "0,1"
bitfld.long 0x04 3. "CSR_ERR,CSR_ERR" "0,1"
newline
bitfld.long 0x04 2. "DAP_ERR,DAP_ERR" "0,1"
bitfld.long 0x04 1. "SRAM_UNCORR_ERR,SRAM_UNCORR_ERR" "0,1"
bitfld.long 0x04 0. "SRAM_CORR_ERR,SRAM_CORR_ERR" "0,1"
tree.end
tree.end
tree "DSS_COMMON"
tree "DSS0_DISPC_0_COMMON_M"
base ad:0x4A00000
rgroup.long 0x04++0x07
line.long 0x00 "DSS0_COMMON_DSS_REVISION,This register contains the K3_DSS revision number"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID Field"
bitfld.long 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DSS0_COMMON_DSS_SYSCONFIG,This register controls various parameters related to software reset and IP idle"
bitfld.long 0x04 5. "WARMRESET,Warm reset" "0,1"
bitfld.long 0x04 3.--4. "IDLEMODE,Deprecated" "0,1,2,3"
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
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bitfld.long 0x04 0. "AUTOCLKGATING,Internal clock gating strategy" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "DSS0_COMMON_DSS_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information"
bitfld.long 0x00 9. "DISPC_IDLE_STATUS,Idle status of DISPC" "0,1"
bitfld.long 0x00 1.--4. "DISPC_VP_RESETDONE,Reset status of VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain" "0,1"
group.long 0x28++0x0F
line.long 0x00 "DSS0_COMMON_DISPC_IRQSTATUS_RAW,RAW Interrupt status"
bitfld.long 0x00 16. "DUMMY_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1"
bitfld.long 0x00 15. "DUMMY1_IRQ,Dummy IRQ STATUS- Reserved for future use" "0,1"
bitfld.long 0x00 14. "WB_IRQ,WB IRQ STATUS" "0,1"
newline
bitfld.long 0x00 4.--7. "VID_IRQ,VID IRQ STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "VP_IRQ,VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DSS0_COMMON_DISPC_IRQSTATUS,Interrupt status"
bitfld.long 0x04 16. "DUMMY_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1"
bitfld.long 0x04 15. "DUMMY1_IRQ,Dummy IRQ STATUS-Reserved for future use" "0,1"
bitfld.long 0x04 14. "WB_IRQ,WB IRQ STATUS" "0,1"
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bitfld.long 0x04 4.--7. "VID_IRQ,VID IRQ STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "VP_IRQ,VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DSS0_COMMON_DISPC_IRQENABLE_SET,SET Interrupt enable"
bitfld.long 0x08 16. "SET_DUMMY_IRQ,Dummy IRQ" "0,1"
bitfld.long 0x08 15. "SET_DUMMY1_IRQ,Dummy IRQ" "0,1"
bitfld.long 0x08 14. "SET_WB_IRQ,WB IRQ if WB pipeline is present" "0,1"
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bitfld.long 0x08 4.--7. "SET_VID_IRQ,VID IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "SET_VP_IRQ,VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DSS0_COMMON_DISPC_IRQENABLE_CLR,CLR Interrupt enable"
bitfld.long 0x0C 16. "CLR_DUMMY_IRQ,Dummy IRQ" "0,1"
bitfld.long 0x0C 15. "CLR_DUMMY1_IRQ,Dummy IRQ" "0,1"
bitfld.long 0x0C 14. "CLR_WB_IRQ,WB IRQ if WB pipeline is present" "0,1"
newline
bitfld.long 0x0C 4.--7. "CLR_VID_IRQ,VID IRQ.[0] -> VID1 [1] -> VIDL1 [2] -> VID2 [3] -> VIDL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CLR_VP_IRQ,VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x33
line.long 0x00 "DSS0_COMMON_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x00 13.--16. "SAFETYREGION1_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x00 11. "VPSYNC_EN,Go bit clear event" "0,1"
newline
bitfld.long 0x00 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
bitfld.long 0x00 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
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bitfld.long 0x00 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x00 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
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bitfld.long 0x00 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
bitfld.long 0x00 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
line.long 0x04 "DSS0_COMMON_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x04 13.--16. "SAFETYREGION1_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x04 11. "VPSYNC_EN,Go bit clear event" "0,1"
newline
bitfld.long 0x04 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
bitfld.long 0x04 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x04 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x04 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
newline
bitfld.long 0x04 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
bitfld.long 0x04 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
line.long 0x08 "DSS0_COMMON_VP_IRQENABLE_2,This register allows to mask/unmask the VP_2 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x08 13.--16. "SAFETYREGION1_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x08 11. "VPSYNC_EN,Go bit clear event" "0,1"
newline
bitfld.long 0x08 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
bitfld.long 0x08 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x08 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
bitfld.long 0x08 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x08 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
newline
bitfld.long 0x08 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
bitfld.long 0x08 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
line.long 0x0C "DSS0_COMMON_VP_IRQENABLE_3,This register allows to mask/unmask the VP_3 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x0C 13.--16. "SAFETYREGION1_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x0C 11. "VPSYNC_EN,Go bit clear event" "0,1"
newline
bitfld.long 0x0C 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
bitfld.long 0x0C 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x0C 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
bitfld.long 0x0C 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x0C 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
newline
bitfld.long 0x0C 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
bitfld.long 0x0C 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
line.long 0x10 "DSS0_COMMON_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt"
bitfld.long 0x10 13.--16. "SAFETYREGION1_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x10 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
newline
bitfld.long 0x10 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x10 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x10 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
bitfld.long 0x10 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x10 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
newline
bitfld.long 0x10 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
bitfld.long 0x10 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
line.long 0x14 "DSS0_COMMON_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt"
bitfld.long 0x14 13.--16. "SAFETYREGION1_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x14 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
newline
bitfld.long 0x14 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x14 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x14 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
bitfld.long 0x14 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x14 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
newline
bitfld.long 0x14 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
bitfld.long 0x14 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
line.long 0x18 "DSS0_COMMON_VP_IRQSTATUS_2,This register groups all the status of the VP_2 internal events that generate an interrupt"
bitfld.long 0x18 13.--16. "SAFETYREGION1_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x18 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
newline
bitfld.long 0x18 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x18 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x18 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
bitfld.long 0x18 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x18 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
newline
bitfld.long 0x18 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
bitfld.long 0x18 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
line.long 0x1C "DSS0_COMMON_VP_IRQSTATUS_3,This register groups all the status of the VP_3 internal events that generate an interrupt"
bitfld.long 0x1C 13.--16. "SAFETYREGION1_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x1C 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
newline
bitfld.long 0x1C 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x1C 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
newline
bitfld.long 0x1C 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
bitfld.long 0x1C 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x1C 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
newline
bitfld.long 0x1C 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
bitfld.long 0x1C 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
line.long 0x20 "DSS0_COMMON_WB_IRQENABLE,This register allows to mask/unmask the WB internal sources of interrupt. if WB pipeline is present. on an event-by-event basis"
bitfld.long 0x20 4. "WBSYNC_EN,Write-back sync IRQ" "0,1"
bitfld.long 0x20 3. "SECURITYVIOLATION_EN,Security Violation IRQ" "0,1"
bitfld.long 0x20 2. "WBFRAMEDONE_EN,Write-back Frame Done" "0,1"
newline
bitfld.long 0x20 1. "WBUNCOMPLETEERROR_EN,The write back buffer has been flushed before been fully drained" "0,1"
bitfld.long 0x20 0. "WBBUFFEROVERFLOW_EN,Write-back DMA Buffer Overflow" "0,1"
line.long 0x24 "DSS0_COMMON_WB_IRQSTATUS,This register groups all the status of the WB internal events that generate an interrupt. if WB pipeline is present"
bitfld.long 0x24 4. "WBSYNC_IRQ,Write-back sync IRQ" "0,1"
bitfld.long 0x24 3. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x24 2. "WBFRAMEDONE_IRQ,Write-back Frame Done" "0,1"
newline
bitfld.long 0x24 1. "WBUNCOMPLETEERROR_IRQ,Write back DMA buffer is flushed before been completely drained" "0,1"
bitfld.long 0x24 0. "WBBUFFEROVERFLOW_IRQ,Write-back DMA Buffer Overflow The DMA buffer is full" "0,1"
line.long 0x28 "DSS0_COMMON_DISPC_IRQ_EOI_FUNC,End-Of-Interrupt register for FUNC interrupts. to be used if pulse interrupts are used The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x28 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1"
line.long 0x2C "DSS0_COMMON_DISPC_IRQ_EOI_SAFETY,End-Of-Interrupt register for SAFETY interrupts. to be used if pulse interrupts are used The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x2C 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1"
line.long 0x30 "DSS0_COMMON_DISPC_IRQ_EOI_SECURITY,End-Of-Interrupt register for SECURITY interrupts. to be used if pulse interrupts are used The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x30 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1"
group.long 0x90++0x03
line.long 0x00 "DSS0_COMMON_DISPC_SECURE_DISABLE,Disable security settings throughout DSS IP"
bitfld.long 0x00 0. "SECURE_DISABLE,Secure disable bit" "0,1"
group.long 0x98++0x1B
line.long 0x00 "DSS0_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register"
bitfld.long 0x00 6. "MFLAG_START,MFLAG_START for DMA master port" "0,1"
bitfld.long 0x00 0.--1. "MFLAG_CTRL,MFLAG_CTRL for DMA master port" "0,1,2,3"
line.long 0x04 "DSS0_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE,DISPC global output enable register"
bitfld.long 0x04 16.--19. "VP_GO,Global GO Command for the VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "VP_ENABLE,Global VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DSS0_COMMON_DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipelines for DMA"
bitfld.long 0x08 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "0,1"
bitfld.long 0x08 30. "SHAREDBUFENABLE,Enable Shared DMA Buffer feature" "0,1"
bitfld.long 0x08 12.--14. "WB_BUFFER,WB DMA buffer allocation to one of the pipelines if WB pipeline is present" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 9.--11. "VIDL2_BUFFER,VIDL2 DMA buffer allocation to one of the pipelines if VIDL2 is present" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--8. "VID2_BUFFER,VID2 DMA buffer allocation to one of the pipelines if VID2 is present" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 3.--5. "VIDL1_BUFFER,VIDL1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "VID1_BUFFER,VID1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7"
line.long 0x0C "DSS0_COMMON_DSS_CBA_CFG,This register contains CBA specific config bits in DSS"
bitfld.long 0x0C 7.--8. "DMA_BACKLOGSTATUS_DISABLE_VAL,IP Internal - Tie-off value on DMA_BACKLOGSTATUS pins when DMA Backlog Status reporting is disabled" "0,1,2,3"
bitfld.long 0x0C 6. "DMA_BACKLOGSTATUS_DISABLE,IP Internal - Disable generation of DMA Backlog Status reporting to interconnect" "0,1"
bitfld.long 0x0C 3.--5. "PRI_HI,The value sent out on the PRI_HI bus from DSS to CBA Indicates the priority level for high-priority [MFLAG] transactions" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0.--2. "PRI_LO,The value sent out on the PRI_LO bus from DSS to CBA Indicates the priority level for normal [non-MFLAG] transactions" "0,1,2,3,4,5,6,7"
line.long 0x10 "DSS0_COMMON_DISPC_DBG_CONTROL,DISPC debug status control register"
hexmask.long.byte 0x10 1.--8. 1. "DBGMUXSEL,Mux select for the debug status"
bitfld.long 0x10 0. "DBGEN,Enable debug ports" "0,1"
line.long 0x14 "DSS0_COMMON_DISPC_DBG_STATUS,DISPC debug status register"
line.long 0x18 "DSS0_COMMON_DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level"
bitfld.long 0x18 18.--21. "VP,Clock gating control for VP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 14.--17. "OVR,Clock gating control for OVR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 13. "WB,Clock gating control for WB if WB pipeline is present" "0,1"
newline
bitfld.long 0x18 3.--6. "VID,Clock gating control for VID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0. "DMA,Clock gating control for DMA" "0,1"
rgroup.long 0xB8++0x23
line.long 0x00 "DSS0_COMMON_FBDC_REVISION_1,This register contains the FBDC Product Code"
hexmask.long.word 0x00 0.--15. 1. "PRODUCTCODE,FBDC Product Code"
line.long 0x04 "DSS0_COMMON_FBDC_REVISION_2,This register contains the FBDC Branch Code"
hexmask.long.word 0x04 0.--15. 1. "BRANCHCODE,FBDC Branch Code"
line.long 0x08 "DSS0_COMMON_FBDC_REVISION_3,This register contains the FBDC Version Code"
hexmask.long.word 0x08 0.--15. 1. "VERSIONCODE,FBDC Version Code"
line.long 0x0C "DSS0_COMMON_FBDC_REVISION_4,This register contains the FBDC Scalable Core Code"
hexmask.long.word 0x0C 0.--15. 1. "CORECODE,FBDC Scalable Core Code"
line.long 0x10 "DSS0_COMMON_FBDC_REVISION_5,This register contains the FBDC Configuration Code"
hexmask.long.word 0x10 0.--15. 1. "CONFIGCODE,FBDC Configuration Code"
line.long 0x14 "DSS0_COMMON_FBDC_REVISION_6,This register contains the FBDC Changelist Code"
line.long 0x18 "DSS0_COMMON_FBDC_COMMON_CONTROL,This register contains the common control signals for FBDC"
bitfld.long 0x18 2. "GPUTYPE,GPU Selection" "0,1"
bitfld.long 0x18 1. "CLKGATE,Reserved" "0,1"
bitfld.long 0x18 0. "IDLEGATE,Reserved" "0,1"
line.long 0x1C "DSS0_COMMON_FBDC_CONSTANT_COLOR_0,Defines the Constant Color-0 value to be used for the FBDC"
line.long 0x20 "DSS0_COMMON_FBDC_CONSTANT_COLOR_1,Defines the Constant Color-1 value to be used for the FBDC"
group.long 0xE4++0x03
line.long 0x00 "DSS0_COMMON_DISPC_CONNECTIONS,Connections of various sub-modules within DISPC. as well as some peripherals outside"
bitfld.long 0x00 24.--27. "VIRTUALVP_CONN,Defines the connection to VIRTUAL_VP output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "WB_CONN,Defines the connection to WB pipe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DPI_1_CONN,Defines the connection to DPI-1 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DPI_0_CONN,Defines the connection to DPI-0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF0++0x0B
line.long 0x00 "DSS0_COMMON_GLOBAL_DMA_THREADSIZE,This register configures the DMA buffer size allocated to the different threads - Shared memory feature"
bitfld.long 0x00 20.--24. "WBTHREADSIZE,Total DMA buffer size for all the pipelines connected to WB THREAD4.If the value programmed is n then the allocated buffer size is 16KB*n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15.--19. "VP3THREADSIZE,Total DMA buffer size for all the pipelines connected to VP3 THREAD3.If the value programmed is n then the allocated buffer size is 16KB*n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--14. "VP2THREADSIZE,Total DMA buffer size for all the pipelines connected to VP2 THREAD2.If the value programmed is n then the allocated buffer size is 16KB*n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "VP1THREADSIZE,Total DMA buffer size for all the pipelines connected to VP1 THREAD1.If the value programmed is n then the allocated buffer size is 16KB*n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "VP0THREADSIZE,Total DMA buffer size for all the pipelines connected to VP0 THREAD0.If the value programmed is n then the allocated buffer size is 16KB*n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DSS0_COMMON_GLOBAL_DMA_THREADSIZESTATUS,This register read the synchronized value of DMA buffer size allocated to the different threads - Shared memory feature"
bitfld.long 0x04 20.--24. "WBTHREADSIZE,Synchronized version of WB THREADSIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 15.--19. "VP3THREADSIZE,Synchronized version of VP3 THREADSIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 10.--14. "VP2THREADSIZE,Synchronized version of VP2 THREADSIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 5.--9. "VP1THREADSIZE,Synchronized version of VP1 THREADSIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "VP0THREADSIZE,Synchronized version of VP0 THREADSIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DSS0_COMMON_GLOBAL_GOBITMODE,settings"
bitfld.long 0x08 0. "MODE,Go bit" "0,1"
repeat 2. (list 1. 3. )(list 0x00 0x04 )
group.long ($2+0xE8)++0x03
line.long 0x00 "DSS0_COMMON_DISPC_MSS_VP$1,This register controls the Merge_Split_Sync operation for VP1"
bitfld.long 0x00 3. "MSSFORMAT,Merge Split format" "0,1"
bitfld.long 0x00 1.--2. "MSSTYPE,Merge-Split-Sync operation type" "0,1,2,3"
newline
bitfld.long 0x00 0. "MSSENABLE,Merge-Split-Sync operation Enable" "0,1"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x48)++0x03
line.long 0x00 "DSS0_COMMON_VID_IRQSTATUS_$1,This register groups all the status of the VID internal events that generate an interrupt"
bitfld.long 0x00 4. "FBDC_ILLEGALTILEREQ_IRQ,FBDC IRQ Illegal tile req detected" "0,1"
bitfld.long 0x00 3. "FBDC_CORRUPTTILE_IRQ,FBDC IRQ" "0,1"
newline
bitfld.long 0x00 2. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1"
bitfld.long 0x00 1. "VIDENDWINDOW_IRQ,Video End Window" "0,1"
newline
bitfld.long 0x00 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "0,1"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x38)++0x03
line.long 0x00 "DSS0_COMMON_VID_IRQENABLE_$1,This register allows to mask/unmask the VID internal sources of interrupt. on an event-by-event basis.[0] -> VID1. [1] -> VIDL1. [2] -> VID2. [3] -> VIDL2"
bitfld.long 0x00 4. "FBDC_ILLEGALTILEREQ_EN,FBDC IRQ Illegal tile req detected" "0,1"
bitfld.long 0x00 3. "FBDC_CORRUPTTILE_EN,FBDC IRQ" "0,1"
newline
bitfld.long 0x00 2. "SAFETYREGION_EN,Safety Feature IRQ" "0,1"
bitfld.long 0x00 1. "VIDENDWINDOW_EN,Video End Window" "0,1"
newline
bitfld.long 0x00 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "0,1"
repeat.end
tree.end
tree.end
tree "DSS_OVR"
repeat 4. (list 1. 2. 3. 4. )(list ad:0x4A70000 ad:0x4A90000 ad:0x4AB0000 ad:0x4AD0000 )
tree "DSS0_OVR$1"
base $2
group.long 0x00++0x4B
line.long 0x00 "DSS0_OVR_CONFIG,The control register configures the Display Controller module for the VP output"
bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1"
bitfld.long 0x00 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1"
bitfld.long 0x00 1. "COLORBAREN,Enable the Color-Bar" "0,1"
line.long 0x04 "DSS0_OVR_VIRTUALVP,Configures the new VIRTUAL VP operation"
bitfld.long 0x04 31. "ENABLE,Enable the Virtual VP Operation" "0,1"
hexmask.long.word 0x04 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines on the Virtual VP [program to value minus 1]"
hexmask.long.word 0x04 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the Virtual VP [program to value minus 1]"
line.long 0x08 "DSS0_OVR_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]"
line.long 0x0C "DSS0_OVR_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]"
hexmask.long.word 0x0C 0.--15. 1. "DEFAULTCOLOR,"
line.long 0x10 "DSS0_OVR_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays"
line.long 0x14 "DSS0_OVR_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays"
bitfld.long 0x14 0.--3. "TRANSCOLORKEY,MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DSS0_OVR_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays"
line.long 0x1C "DSS0_OVR_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays"
bitfld.long 0x1C 0.--3. "TRANSCOLORKEY,MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DSS0_OVR_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager"
bitfld.long 0x20 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1"
line.long 0x24 "DSS0_OVR_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager"
bitfld.long 0x24 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1"
line.long 0x28 "DSS0_OVR_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager"
bitfld.long 0x28 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 0. "ENABLE,Layer Enable" "0,1"
line.long 0x2C "DSS0_OVR_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager"
bitfld.long 0x2C 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0. "ENABLE,Layer Enable" "0,1"
line.long 0x30 "DSS0_OVR_ATTRIBUTES_4,The register configures the attributes of layer-4. ZORDER= 4. of the Overlay manager"
bitfld.long 0x30 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0. "ENABLE,Layer Enable" "0,1"
line.long 0x34 "DSS0_OVR_ATTRIBUTES2_0,The register configures the additional attributes of layer-0. ZORDER= 0. of the Overlay manager"
hexmask.long.word 0x34 16.--29. 1. "POSY,Y position of the layer"
hexmask.long.word 0x34 0.--13. 1. "POSX,X position of the layer"
line.long 0x38 "DSS0_OVR_ATTRIBUTES2_1,The register configures the additional attributes of layer-1. ZORDER= 1. of the Overlay manager"
hexmask.long.word 0x38 16.--29. 1. "POSY,Y position of the layer"
hexmask.long.word 0x38 0.--13. 1. "POSX,X position of the layer"
line.long 0x3C "DSS0_OVR_ATTRIBUTES2_2,The register configures the additional attributes of layer-2. ZORDER= 2. of the Overlay manager"
hexmask.long.word 0x3C 16.--29. 1. "POSY,Y position of the layer"
hexmask.long.word 0x3C 0.--13. 1. "POSX,X position of the layer"
line.long 0x40 "DSS0_OVR_ATTRIBUTES2_3,The register configures the additional attributes of layer-3. ZORDER= 3. of the Overlay manager"
hexmask.long.word 0x40 16.--29. 1. "POSY,Y position of the layer"
hexmask.long.word 0x40 0.--13. 1. "POSX,X position of the layer"
line.long 0x44 "DSS0_OVR_ATTRIBUTES2_4,The register configures the additional attributes of layer-4. ZORDER= 4. of the Overlay manager"
hexmask.long.word 0x44 16.--29. 1. "POSY,Y position of the layer"
hexmask.long.word 0x44 0.--13. 1. "POSX,X position of the layer"
line.long 0x48 "DSS0_OVR_SECURE,Security bit settings for the sub-module"
bitfld.long 0x48 0. "SECURE," "0,1"
tree.end
repeat.end
tree.end
tree "DSS_VID"
repeat 2. (list 1. 2. )(list ad:0x4A50000 ad:0x4A60000 )
tree "DSS0_VID$1"
base $2
group.long 0x20++0x07
line.long 0x00 "DSS0_VID_ATTRIBUTES,The register configures the of the video window"
bitfld.long 0x00 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1"
bitfld.long 0x00 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1"
bitfld.long 0x00 29. "GAMMAINVERSIONPOS,Position of Inverse Gamma operation" "0,1"
bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data" "0,1"
bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1"
newline
bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "0,1"
bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "0,1"
bitfld.long 0x00 19. "BUFPRELOAD,Video" "0,1"
bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1"
bitfld.long 0x00 13. "CROP,Enables cropping operation at the output of Video Pipeline" "0,1"
newline
bitfld.long 0x00 12. "FLIP,Describes the frame buffer flip operation" "0,1"
bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 10. "NIBBLEMODE,Video Nibble mode [only for" "0,1"
bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "0,1"
bitfld.long 0x00 7.--8. "RESIZEENABLE,Video Resize Enable" "0,1,2,3"
newline
bitfld.long 0x00 1.--6. "FORMAT,Video Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0. "ENABLE,Video pipeline Enable" "0,1"
line.long 0x04 "DSS0_VID_ATTRIBUTES2,The register configures the of the video window"
bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 25. "MPORTSEL,Master-Port Selection" "0,1"
bitfld.long 0x04 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1"
bitfld.long 0x04 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1"
bitfld.long 0x04 7.--8. "YUV_SIZE," "0,1,2,3"
newline
bitfld.long 0x04 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "0,1"
rgroup.long 0x38++0x33
line.long 0x00 "DSS0_VID_BUF_SIZE_STATUS,The register returns the Video buffer for the video pipeline"
hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,Video DMA buffer"
line.long 0x04 "DSS0_VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline"
hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold"
hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold"
line.long 0x08 "DSS0_VID_CSC_COEF0,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "DSS0_VID_CSC_COEF1,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "DSS0_VID_CSC_COEF2,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
line.long 0x14 "DSS0_VID_CSC_COEF3,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x14 16.--26. 1. "C21,C21 coefficient"
hexmask.long.word 0x14 0.--10. 1. "C20,C20 coefficient"
line.long 0x18 "DSS0_VID_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x18 0.--10. 1. "C22,C22 Coefficient"
line.long 0x1C "DSS0_VID_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
line.long 0x20 "DSS0_VID_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
hexmask.long.word 0x20 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
line.long 0x24 "DSS0_VID_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter"
line.long 0x28 "DSS0_VID_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x28 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr"
line.long 0x2C "DSS0_VID_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter"
line.long 0x30 "DSS0_VID_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x30 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr"
group.long 0x1FC++0x03
line.long 0x00 "DSS0_VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline"
hexmask.long.byte 0x00 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255"
group.long 0x208++0x0B
line.long 0x00 "DSS0_VID_MFLAG_THRESHOLD,Register"
hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,MFlag High Threshold"
hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,MFlag Low Threshold"
line.long 0x04 "DSS0_VID_PICTURE_SIZE,The register configures the of the video picture associated with the video layer before up/down-scaling"
hexmask.long.word 0x04 16.--29. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 16384] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents"
hexmask.long.word 0x04 0.--13. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 16384] to specify the number of pixels of the video picture in memory [program to value minus one]"
line.long 0x08 "DSS0_VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window"
hexmask.long.byte 0x08 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer"
group.long 0x218++0x0B
line.long 0x00 "DSS0_VID_PRELOAD,The register configures the DMA buffer of the video pipeline"
hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer"
line.long 0x04 "DSS0_VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window"
line.long 0x08 "DSS0_VID_SIZE,The register configures the of the video window"
hexmask.long.word 0x08 16.--29. 1. "SIZEY,Number of lines of the video window Encoded value [from 1 to 16384] to specify the number of lines of the video window [program"
hexmask.long.word 0x08 0.--13. 1. "SIZEX,Number of pixels of the video window Encoded value [from 1 to 16384] to specify the number of pixels of the video window [program"
group.long 0x23C++0x03
line.long 0x00 "DSS0_VID_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x00 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
hexmask.long.word 0x00 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
group.long 0x248++0x13
line.long 0x00 "DSS0_VID_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats"
line.long 0x04 "DSS0_VID_TILE,Defines the characteristics of the position of the first pixel inside the compressed frame buffer"
hexmask.long.tbyte 0x04 0.--22. 1. "TILEINDEX,Defines"
line.long 0x08 "DSS0_VID_TILE2,Defines the number of tiles in the frame buffer"
hexmask.long.tbyte 0x08 0.--22. 1. "NUM_TILES,Defines the total number of tiles in the compressed frame buffer"
line.long 0x0C "DSS0_VID_FBDC_ATTRIBUTES,Defines the for the compression engine -FBDC"
bitfld.long 0x0C 8.--9. "TILETYPE,FBDC" "0,1,2,3"
hexmask.long.byte 0x0C 1.--7. 1. "FORMAT,FBDC format"
bitfld.long 0x0C 0. "ENABLE,Frame Buffer Compression is Enabled" "0,1"
line.long 0x10 "DSS0_VID_FBDC_CLEAR_COLOR,Defines the Clear Color value to be used for the channel in FBDC"
group.long 0x2A0++0x2B
line.long 0x00 "DSS0_VID_SAFETY_ATTRIBUTES,The register configures the safety sub-region"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature"
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection control" "0,1"
bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region" "0,1"
line.long 0x04 "DSS0_VID_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region"
line.long 0x08 "DSS0_VID_SAFETY_POSITION,The register configures the position of the safety sub-region"
hexmask.long.word 0x08 16.--29. 1. "POSY,Y position of the safety sub-region"
hexmask.long.word 0x08 0.--13. 1. "POSX,X position of the safety sub-region"
line.long 0x0C "DSS0_VID_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region"
line.long 0x10 "DSS0_VID_SAFETY_SIZE,The register configures the of the safety sub-region"
hexmask.long.word 0x10 16.--29. 1. "SIZEY,Height of the safety sub-region"
hexmask.long.word 0x10 0.--13. 1. "SIZEX,Width of the safety sub-region"
line.long 0x14 "DSS0_VID_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR"
line.long 0x18 "DSS0_VID_LUMAKEY,The register configures the LUMA KEY transparency min and max values"
hexmask.long.word 0x18 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value"
hexmask.long.word 0x18 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value"
line.long 0x1C "DSS0_VID_DMA_BUFSIZE,The register configures the DMA buffer allocated to the pipeline - New Shared memory feature"
bitfld.long 0x1C 0.--4. "BUFSIZE,DMA buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "DSS0_VID_CROP,Defines the for the output cropping in Video Pipe"
bitfld.long 0x20 24.--28. "CROPBOTTOM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 16.--20. "CROPTOP," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 8.--12. "CROPRIGHT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 0.--4. "CROPLEFT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "DSS0_VID_SECURE,Security bit settings for the sub-module"
bitfld.long 0x24 0. "SECURE," "0,1"
line.long 0x28 "DSS0_VID_PIPE_GO,PIPE GO bit settings"
bitfld.long 0x28 0. "GOBIT,Go bit" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x260)++0x03
line.long 0x00 "DSS0_VID_CLUT_$1,The register configures the Color Look Up Table CLUT for VID pipeline"
bitfld.long 0x00 31. "INDEX,Write 1 to reset the index" "0,1"
hexmask.long.word 0x00 20.--29. 1. "VALUE_R,"
newline
hexmask.long.word 0x00 10.--19. 1. "VALUE_G,"
hexmask.long.word 0x00 0.--9. 1. "VALUE_B,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x234)++0x03
line.long 0x00 "DSS0_VID_BA_UV_EXT_$1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8"
hexmask.long.word 0x00 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x22C)++0x03
line.long 0x00 "DSS0_VID_BA_EXT_$1,The register configures the 16-bit base address extension"
hexmask.long.word 0x00 0.--15. 1. "BA_EXT,Video base address extension [16 bits]"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1BC)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_V12_C_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x17C)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_V12_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x158)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_V0_C_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x134)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_V0_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xF4)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_H12_C_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB4)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_H12_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x90)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_H0_C_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x6C)++0x03
line.long 0x00 "DSS0_VID_FIR_COEF_H0_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "DSS0_VID_BA_UV_$1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x28)++0x03
line.long 0x00 "DSS0_VID_BA_$1,The register configures the base address of the single video buffer"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x18)++0x03
line.long 0x00 "DSS0_VID_ACCUV2_$1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x10)++0x03
line.long 0x00 "DSS0_VID_ACCUV_$1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x08)++0x03
line.long 0x00 "DSS0_VID_ACCUH2_$1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x00)++0x03
line.long 0x00 "DSS0_VID_ACCUH_$1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
repeat.end
tree.end
repeat.end
repeat 2. (list 1. 2. )(list ad:0x4A20000 ad:0x4A30000 )
tree "DSS0_VIDL$1"
base $2
group.long 0x20++0x07
line.long 0x00 "DSS0_VID_ATTRIBUTES,The register configures the of the video window"
bitfld.long 0x00 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1"
bitfld.long 0x00 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1"
bitfld.long 0x00 29. "GAMMAINVERSIONPOS,Position of Inverse Gamma operation" "0,1"
bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data" "0,1"
bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1"
newline
bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "0,1"
bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "0,1"
bitfld.long 0x00 19. "BUFPRELOAD,Video" "0,1"
bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1"
bitfld.long 0x00 13. "CROP,Enables cropping operation at the output of Video Pipeline" "0,1"
newline
bitfld.long 0x00 12. "FLIP,Describes the frame buffer flip operation" "0,1"
bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 10. "NIBBLEMODE,Video Nibble mode [only for" "0,1"
bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "0,1"
bitfld.long 0x00 7.--8. "RESIZEENABLE,Video Resize Enable" "0,1,2,3"
newline
bitfld.long 0x00 1.--6. "FORMAT,Video Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0. "ENABLE,Video pipeline Enable" "0,1"
line.long 0x04 "DSS0_VID_ATTRIBUTES2,The register configures the of the video window"
bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 25. "MPORTSEL,Master-Port Selection" "0,1"
bitfld.long 0x04 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1"
bitfld.long 0x04 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1"
bitfld.long 0x04 7.--8. "YUV_SIZE," "0,1,2,3"
newline
bitfld.long 0x04 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "0,1"
rgroup.long 0x38++0x23
line.long 0x00 "DSS0_VID_BUF_SIZE_STATUS,The register returns the Video buffer for the video pipeline"
hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,Video DMA buffer"
line.long 0x04 "DSS0_VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline"
hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold"
hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold"
line.long 0x08 "DSS0_VID_CSC_COEF0,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "DSS0_VID_CSC_COEF1,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "DSS0_VID_CSC_COEF2,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
line.long 0x14 "DSS0_VID_CSC_COEF3,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x14 16.--26. 1. "C21,C21 coefficient"
hexmask.long.word 0x14 0.--10. 1. "C20,C20 coefficient"
line.long 0x18 "DSS0_VID_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x18 0.--10. 1. "C22,C22 Coefficient"
line.long 0x1C "DSS0_VID_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
line.long 0x20 "DSS0_VID_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
hexmask.long.word 0x20 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
group.long 0x1FC++0x03
line.long 0x00 "DSS0_VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline"
hexmask.long.byte 0x00 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255"
group.long 0x208++0x0B
line.long 0x00 "DSS0_VID_MFLAG_THRESHOLD,Register"
hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,MFlag High Threshold"
hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,MFlag Low Threshold"
line.long 0x04 "DSS0_VID_PICTURE_SIZE,The register configures the of the video picture associated with the video layer before up/down-scaling"
hexmask.long.word 0x04 16.--29. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 16384] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents"
hexmask.long.word 0x04 0.--13. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 16384] to specify the number of pixels of the video picture in memory [program to value minus one]"
line.long 0x08 "DSS0_VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window"
hexmask.long.byte 0x08 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer"
group.long 0x218++0x0B
line.long 0x00 "DSS0_VID_PRELOAD,The register configures the DMA buffer of the video pipeline"
hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer"
line.long 0x04 "DSS0_VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window"
line.long 0x08 "DSS0_VID_SIZE,The register configures the of the video window"
hexmask.long.word 0x08 16.--29. 1. "SIZEY,Number of lines of the video window Encoded value [from 1 to 16384] to specify the number of lines of the video window [program"
hexmask.long.word 0x08 0.--13. 1. "SIZEX,Number of pixels of the video window Encoded value [from 1 to 16384] to specify the number of pixels of the video window [program"
group.long 0x23C++0x03
line.long 0x00 "DSS0_VID_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x00 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
hexmask.long.word 0x00 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
group.long 0x248++0x13
line.long 0x00 "DSS0_VID_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats"
line.long 0x04 "DSS0_VID_TILE,Defines the characteristics of the position of the first pixel inside the compressed frame buffer"
hexmask.long.tbyte 0x04 0.--22. 1. "TILEINDEX,Defines"
line.long 0x08 "DSS0_VID_TILE2,Defines the number of tiles in the frame buffer"
hexmask.long.tbyte 0x08 0.--22. 1. "NUM_TILES,Defines the total number of tiles in the compressed frame buffer"
line.long 0x0C "DSS0_VID_FBDC_ATTRIBUTES,Defines the for the compression engine -FBDC"
bitfld.long 0x0C 8.--9. "TILETYPE,FBDC" "0,1,2,3"
hexmask.long.byte 0x0C 1.--7. 1. "FORMAT,FBDC format"
bitfld.long 0x0C 0. "ENABLE,Frame Buffer Compression is Enabled" "0,1"
line.long 0x10 "DSS0_VID_FBDC_CLEAR_COLOR,Defines the Clear Color value to be used for the channel in FBDC"
group.long 0x2A0++0x2B
line.long 0x00 "DSS0_VID_SAFETY_ATTRIBUTES,The register configures the safety sub-region"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature"
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection control" "0,1"
bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region" "0,1"
line.long 0x04 "DSS0_VID_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region"
line.long 0x08 "DSS0_VID_SAFETY_POSITION,The register configures the position of the safety sub-region"
hexmask.long.word 0x08 16.--29. 1. "POSY,Y position of the safety sub-region"
hexmask.long.word 0x08 0.--13. 1. "POSX,X position of the safety sub-region"
line.long 0x0C "DSS0_VID_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region"
line.long 0x10 "DSS0_VID_SAFETY_SIZE,The register configures the of the safety sub-region"
hexmask.long.word 0x10 16.--29. 1. "SIZEY,Height of the safety sub-region"
hexmask.long.word 0x10 0.--13. 1. "SIZEX,Width of the safety sub-region"
line.long 0x14 "DSS0_VID_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR"
line.long 0x18 "DSS0_VID_LUMAKEY,The register configures the LUMA KEY transparency min and max values"
hexmask.long.word 0x18 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value"
hexmask.long.word 0x18 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value"
line.long 0x1C "DSS0_VID_DMA_BUFSIZE,The register configures the DMA buffer allocated to the pipeline - New Shared memory feature"
bitfld.long 0x1C 0.--4. "BUFSIZE,DMA buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "DSS0_VID_CROP,Defines the for the output cropping in Video Pipe"
bitfld.long 0x20 24.--28. "CROPBOTTOM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 16.--20. "CROPTOP," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 8.--12. "CROPRIGHT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 0.--4. "CROPLEFT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "DSS0_VID_SECURE,Security bit settings for the sub-module"
bitfld.long 0x24 0. "SECURE," "0,1"
line.long 0x28 "DSS0_VID_PIPE_GO,PIPE GO bit settings"
bitfld.long 0x28 0. "GOBIT,Go bit" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x260)++0x03
line.long 0x00 "DSS0_VID_CLUT_$1,The register configures the Color Look Up Table CLUT for VID pipeline"
bitfld.long 0x00 31. "INDEX,Write 1 to reset the index" "0,1"
hexmask.long.word 0x00 20.--29. 1. "VALUE_R,"
newline
hexmask.long.word 0x00 10.--19. 1. "VALUE_G,"
hexmask.long.word 0x00 0.--9. 1. "VALUE_B,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x234)++0x03
line.long 0x00 "DSS0_VID_BA_UV_EXT_$1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8"
hexmask.long.word 0x00 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x22C)++0x03
line.long 0x00 "DSS0_VID_BA_EXT_$1,The register configures the 16-bit base address extension"
hexmask.long.word 0x00 0.--15. 1. "BA_EXT,Video base address extension [16 bits]"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "DSS0_VID_BA_UV_$1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x28)++0x03
line.long 0x00 "DSS0_VID_BA_$1,The register configures the base address of the single video buffer"
repeat.end
tree.end
repeat.end
tree.end
tree "DSS_VP"
repeat 4. (list 1. 2. 3. 4. )(list ad:0x4A80000 ad:0x4AA0000 ad:0x4AC0000 ad:0x4AE0000 )
tree "DSS0_VP$1"
base $2
group.long 0x00++0x13
line.long 0x00 "DSS0_VP_CONFIG,The register configures the Display Controller module for the VP output"
bitfld.long 0x00 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1"
bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "0,1"
newline
bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "0,1"
bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1"
bitfld.long 0x00 21. "BT1120ENABLE,Selects BT-1120 format on the VP output" "0,1"
newline
bitfld.long 0x00 20. "BT656ENABLE,Selects BT-656 format on the VP output" "0,1"
bitfld.long 0x00 16. "BUFFERHANDSHAKE,Deprecated" "0,1"
bitfld.long 0x00 15. "CPR,Deprecated" "0,1"
newline
bitfld.long 0x00 8. "EXTERNALSYNCEN,Deprecated" "0,1"
bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]" "0,1"
newline
bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 3. "HDMIMODE,Deprecated" "0,1"
newline
bitfld.long 0x00 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1"
bitfld.long 0x00 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1"
bitfld.long 0x00 0. "PIXELGATED,Pixel Gated Enable" "0,1"
line.long 0x04 "DSS0_VP_CONTROL,The register configures the Display Controller module for the VP output"
bitfld.long 0x04 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
newline
bitfld.long 0x04 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1"
bitfld.long 0x04 14.--16. "HT,Hold Time for output" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "STALLMODETYPE,The type of transfer in STALLMODE - If STALLMODE is enabled" "0,1"
bitfld.long 0x04 11. "STALLMODE,Enable the STALLMODE on DPI output" "0,1"
bitfld.long 0x04 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1"
bitfld.long 0x04 6. "DPIENABLE,Enable the DPI output" "0,1"
bitfld.long 0x04 5. "GOBIT,GO Command for the VP output" "0,1"
newline
bitfld.long 0x04 4. "M8B,Deprecated" "0,1"
bitfld.long 0x04 3. "STN,Deprecated" "0,1"
bitfld.long 0x04 2. "MONOCOLOR,Deprecated" "0,1"
newline
bitfld.long 0x04 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1"
bitfld.long 0x04 0. "ENABLE,Enable the video port output" "0,1"
line.long 0x08 "DSS0_VP_CSC_COEF0,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "DSS0_VP_CSC_COEF1,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "DSS0_VP_CSC_COEF2,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
group.long 0x44++0x03
line.long 0x00 "DSS0_VP_LINE_NUMBER,The register indicates the panel display line number for the interrupt and the DMA request"
hexmask.long.word 0x00 0.--13. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs"
group.long 0x4C++0x23
line.long 0x00 "DSS0_VP_POL_FREQ,The register configures the signal configuration"
bitfld.long 0x00 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1"
bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC Pixel clock" "0,1"
bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1"
newline
bitfld.long 0x00 15. "IEO,Invert output enable" "0,1"
bitfld.long 0x00 14. "IPC,Invert pixel clock" "0,1"
bitfld.long 0x00 13. "IHS,Invert HSYNC" "0,1"
newline
bitfld.long 0x00 12. "IVS,Invert VSYNC" "0,1"
bitfld.long 0x00 8.--11. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin"
line.long 0x04 "DSS0_VP_SIZE_SCREEN,The register configures the panel size horizontal and vertical"
hexmask.long.word 0x04 16.--29. 1. "LPP,Lines per panel Encoded value [from 1 to 16384] to specify the number of lines per panel [program to value minus one]"
bitfld.long 0x04 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3"
hexmask.long.word 0x04 0.--13. 1. "PPL,Pixels per line Encoded value [from 1 to 16384] to specify the number of pixels contains within each line on the display [program to value minus one]"
line.long 0x08 "DSS0_VP_TIMING_H,The register configures the timing logic for the HSYNC signal"
hexmask.long.word 0x08 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.."
hexmask.long.word 0x08 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.."
hexmask.long.byte 0x08 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB"
line.long 0x0C "DSS0_VP_TIMING_V,The register configures the timing logic for the VSYNC signal"
hexmask.long.word 0x0C 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.."
hexmask.long.word 0x0C 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.."
hexmask.long.byte 0x0C 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.."
line.long 0x10 "DSS0_VP_CSC_COEF3,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient"
hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient"
line.long 0x14 "DSS0_VP_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient"
line.long 0x18 "DSS0_VP_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
line.long 0x1C "DSS0_VP_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
line.long 0x20 "DSS0_VP_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
group.long 0x110++0x03
line.long 0x00 "DSS0_VP_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value"
group.long 0x178++0x03
line.long 0x00 "DSS0_VP_SECURE,Security bit settings for the sub-module"
bitfld.long 0x00 0. "SECURE," "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x120)++0x03
line.long 0x00 "DSS0_VP_GAMMA_TABLE_$1,The register configures the gamma table on VP output"
bitfld.long 0x00 31. "INDEX,Write 1 to reset the index" "0,1"
hexmask.long.word 0x00 20.--29. 1. "VALUE_R,"
newline
hexmask.long.word 0x00 10.--19. 1. "VALUE_G,"
hexmask.long.word 0x00 0.--9. 1. "VALUE_B,"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xF0)++0x03
line.long 0x00 "DSS0_VP_SAFETY_SIZE_$1,The register configures the size of the safety sub-region n Shadow register"
hexmask.long.word 0x00 16.--29. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 16383] to specify the height of the sub-region on the screen One line height region has value of 0"
hexmask.long.word 0x00 0.--13. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 16383] to specify the width of the sub-region on the screen One pixel wide region has value of 0"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xD0)++0x03
line.long 0x00 "DSS0_VP_SAFETY_REF_SIGNATURE_$1,The register configures the reference signature of the safety sub-region n"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xB0)++0x03
line.long 0x00 "DSS0_VP_SAFETY_POSITION_$1,The register configures the position of the safety sub-region n"
hexmask.long.word 0x00 16.--29. 1. "POSY,Y position of the safety sub-region n"
hexmask.long.word 0x00 0.--13. 1. "POSX,X position of the safety sub-region n"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x90)++0x03
line.long 0x00 "DSS0_VP_SAFETY_CAPT_SIGNATURE_$1,The register captures the signature from the MISR of the safety sub-region n"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x70)++0x03
line.long 0x00 "DSS0_VP_SAFETY_ATTRIBUTES_$1,The register configures the safety sub-region n"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "0,1,2,3"
hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.."
newline
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection" "0,1"
bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
newline
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x14)++0x03
line.long 0x00 "DSS0_VP_DATA_CYCLE_$1,The register configures the output data format over up to 3 cycles"
bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
tree.end
repeat.end
tree.end
tree "DSS_WB"
tree "DSS0_WB"
base ad:0x4AF0000
group.long 0x20++0x07
line.long 0x00 "DSS0_WB_ATTRIBUTES,The register configures the of the write back pipeline"
bitfld.long 0x00 28.--31. "IDLENUMBER,Determines the number of idles between requests on the L3 interconnect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 27. "IDLESIZE,Determines if the IDLENUMBER corresponds to a number of bursts or singles" "0,1"
bitfld.long 0x00 24.--26. "CAPTUREMODE,Defines the frame rate capture" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the write-back pipeline" "0,1"
bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "0,1"
newline
bitfld.long 0x00 20. "GOBIT,GO Command for the WB output" "0,1"
bitfld.long 0x00 19. "WRITEBACKMODE,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory [composition engine] or as a capture channel" "0,1"
bitfld.long 0x00 12. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 11. "COLORCONVENABLE,Enable the color space conversion" "0,1"
bitfld.long 0x00 9. "ALPHAENABLE,Alpha enable on WB output" "0,1"
newline
bitfld.long 0x00 7.--8. "RESIZEENABLE,Resize Enable" "0,1,2,3"
bitfld.long 0x00 1.--6. "FORMAT,Write-back Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0. "ENABLE,Write-back Enable wr: immediate" "0,1"
line.long 0x04 "DSS0_WB_ATTRIBUTES2,The register configures the of the write back pipeline"
bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline [0x0 to 0xF]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1"
bitfld.long 0x04 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1"
bitfld.long 0x04 7.--8. "YUV_SIZE," "0,1,2,3"
rgroup.long 0x38++0x33
line.long 0x00 "DSS0_WB_BUF_SIZE_STATUS,The register defines the DMA buffer for the write back pipeline"
hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,DMA buffer"
line.long 0x04 "DSS0_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline"
hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold Number of"
hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer High Threshold Number of"
line.long 0x08 "DSS0_WB_CSC_COEF0,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "DSS0_WB_CSC_COEF1,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "DSS0_WB_CSC_COEF2,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
line.long 0x14 "DSS0_WB_CSC_COEF3,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x14 16.--26. 1. "C21,C21 coefficient"
hexmask.long.word 0x14 0.--10. 1. "C20,C20 coefficient"
line.long 0x18 "DSS0_WB_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x18 0.--10. 1. "C22,C22 Coefficient"
line.long 0x1C "DSS0_WB_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
line.long 0x20 "DSS0_WB_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
hexmask.long.word 0x20 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
line.long 0x24 "DSS0_WB_FIRH,The register configures the resize factor for horizontal up/down-sampling of the write-back window"
hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter"
line.long 0x28 "DSS0_WB_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the write-back window"
hexmask.long.tbyte 0x28 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr"
line.long 0x2C "DSS0_WB_FIRV,The register configures the resize factor for vertical up/down-sampling of the write-back window"
hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter"
line.long 0x30 "DSS0_WB_FIRV2,The register configures the resize factor for vertical up/down-sampling of the write-back window"
hexmask.long.tbyte 0x30 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr"
group.long 0x204++0x07
line.long 0x00 "DSS0_WB_MFLAG_THRESHOLD,Register"
hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,MFlag High Threshold"
hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,MFlag Low Threshold"
line.long 0x04 "DSS0_WB_PICTURE_SIZE,The register configures the of the write-back picture associated with the write back pipeline after up/down-scaling of the image stored in DDR memory. generated by WB pipe"
hexmask.long.word 0x04 16.--29. 1. "MEMSIZEY,Number of lines of the wb picture in memory Encoded value [from 1 to 16384] to specify the number of lines of the picture store in memory [program to value minus one]"
hexmask.long.word 0x04 0.--13. 1. "MEMSIZEX,Number of pixels of the wb picture in memory Encoded value [from 1 to 16384] to specify the number of pixels of the picture stored in memory [program to value minus one]"
group.long 0x210++0x07
line.long 0x00 "DSS0_WB_SIZE,The register configures the of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline"
hexmask.long.word 0x00 16.--29. 1. "SIZEY,Number of lines of the Write-back picture Encoded value [from 1 to 16384] to specify the number of lines of the write-back picture from overlay or pipeline"
hexmask.long.word 0x00 0.--13. 1. "SIZEX,Number of pixels of the Write-back picture Encoded value [from 1 to 16384] to specify the number of pixels of the write-back picture from overlay or pipeline"
line.long 0x04 "DSS0_WB_POSITION,The register configures the start of the window on overlay which wb will capture"
hexmask.long.word 0x04 16.--29. 1. "POSY,Y"
hexmask.long.word 0x04 0.--13. 1. "POSX,X"
group.long 0x21C++0x03
line.long 0x00 "DSS0_WB_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x00 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
hexmask.long.word 0x00 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
group.long 0x224++0x07
line.long 0x00 "DSS0_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the WB window"
line.long 0x04 "DSS0_WB_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the WB window for YUV420 formats"
group.long 0x248++0x03
line.long 0x00 "DSS0_WB_SECURE,Security bit settings for the sub-module"
bitfld.long 0x00 0. "SECURE," "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x234)++0x03
line.long 0x00 "DSS0_WB_BA_UV_EXT_$1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8"
hexmask.long.word 0x00 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x22C)++0x03
line.long 0x00 "DSS0_WB_BA_EXT_$1,The register configures the 16-bit base address extension"
hexmask.long.word 0x00 0.--15. 1. "BA_EXT,Video base address extension [16 bits]"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1BC)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_V12_C_$1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x17C)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_V12_$1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n"
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase n"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x158)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_V0_C_$1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x134)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_V0_$1,The bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase n"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xF4)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_H12_C_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB4)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_H12_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase n"
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x90)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_H0_C_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x6C)++0x03
line.long 0x00 "DSS0_WB_FIR_COEF_H0_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase n"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "DSS0_WB_BA_UV_$1,The register configures the base address of the UV buffer for the write-back pipeline"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x28)++0x03
line.long 0x00 "DSS0_WB_BA_$1,The register configures the base address of the WB buffer"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x18)++0x03
line.long 0x00 "DSS0_WB_ACCUV2_$1,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window"
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x10)++0x03
line.long 0x00 "DSS0_WB_ACCUV_$1,The register configures the resize accumulator init value for vertical up/down-sampling of the write-back window"
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x08)++0x03
line.long 0x00 "DSS0_WB_ACCUH2_$1,The register configures the resize accumulator init value for horizontal up/down-sampling of the write-back window"
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x00)++0x03
line.long 0x00 "DSS0_WB_ACCUH_$1,The register configures the resize accumulator init values for horizontal up/down-sampling of the write-back window"
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
repeat.end
tree.end
tree.end
tree "ECAP"
repeat 3. (list 0. 1. 2. )(list ad:0x3100000 ad:0x3110000 ad:0x3120000 )
tree "ECAP$1"
base $2
group.long 0x00++0x17
line.long 0x00 "ECAP_TSCNT,Time Stamp Counter Register"
line.long 0x04 "ECAP_CNTPHS,Counter Phase Control Register"
line.long 0x08 "ECAP_CAP1,Capture-1 Register"
line.long 0x0C "ECAP_CAP2,Capture-2 Register"
line.long 0x10 "ECAP_CAP3,Capture-3 Register"
line.long 0x14 "ECAP_CAP4,Capture-4 Register"
group.long 0x28++0x0B
line.long 0x00 "ECAP_ECCTL,ECAP Control Register"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select" "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (" "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,SyncOut select" "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot 'Re-arming' control i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1 and 4) of captures allowed to occur before" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control (applicable only in Capture mode)" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1"
line.long 0x04 "ECAP_ECINT_EN_FLG,ECAP Interrupt Enable and Flag Register"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable" "0,1"
line.long 0x08 "ECAP_ECINT_CLR_FRC,ECAP Interrupt Clear and Forcing Register"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event 4" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event 3" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event 2" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event 1" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "ECAP_PID,Peripheral ID Register"
tree.end
repeat.end
tree.end
tree "EDP_CFG"
tree "DSS_EDP0_INTG_CFG_VP"
base ad:0x4F40000
rgroup.long 0x00++0x1F
line.long 0x00 "EDP_REVISION,The Register contains the major and minor revisions for the VPAC dptx HWA module"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "EDP_DPTX_IPCFG,The Register - Configures DPTX Core security mode and fw memory clock enable"
bitfld.long 0x04 1. "FW_MEM_CLK_EN,DPTX firmware memory (I/Dram) clock enable (set to 1 by default after a reset)" "0,1"
bitfld.long 0x04 0. "APB_SECURE_REG_BLOCK_EN,DPTX - APB secure region access block enable mode" "0,1"
line.long 0x08 "EDP_ECC_MEM_CFG,The Register - Enables clocks to the ECC-aggregator/memories for ECC logic access"
bitfld.long 0x08 0. "CLK_EN,Clk Force Enable for ECC access\n" "0,1"
line.long 0x0C "EDP_DPTX_DSC_CFG,The Register - Configures DSC usaged of the DPTX Core"
bitfld.long 0x0C 6. "DSC_1_10BPC,DPTX - DSC encoder" "0,1"
bitfld.long 0x0C 5. "DSC_0_10BPC,DPTX - DSC encoder" "0,1"
bitfld.long 0x0C 4. "BOTH_CLK_EN,DPTX - DSC force both clock on whenever DSC is active" "0,1"
bitfld.long 0x0C 2. "SPLIT_PANEL_EN,DPTX - DSC encoder mode select" "0,1"
newline
bitfld.long 0x0C 0.--1. "MODE_SEL,DPTX - DSC encoder mode select" "0,1,2,3"
line.long 0x10 "EDP_DPTX_SRC_CFG,The Register - Configures VIF and AIF port channel enables (for memory clock gating) and VIF source mux selection (for mapping DPI to VIF ports)"
bitfld.long 0x10 28.--31. "VIF_FMT_SEL,Reserved - must be set to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 16. "AIF_EN,DPTX Audio I2S channel memory clk enable" "0,1"
bitfld.long 0x10 11. "VIF_3_IN30B,DPTX vif_3 source data width is 30 bits" "0,1"
bitfld.long 0x10 10. "VIF_2_IN30B,DPTX vif_2 source data width is 30 bits" "0,1"
newline
bitfld.long 0x10 9. "VIF_1_IN30B,DPTX vif_1 source data width is 30 bits" "0,1"
bitfld.long 0x10 8. "VIF_0_IN30B,DPTX vif_0 source data width is 30 bits" "0,1"
bitfld.long 0x10 7. "VIF_3_SEL,DPTX vif_3 source select - between dpi_3 or dpi_5" "0,1"
bitfld.long 0x10 6. "VIF_2_SEL,DPTX vif_2 source select - between dpi_2 or dpi_4" "0,1"
newline
bitfld.long 0x10 5. "VIF_1_SEL,DPTX vif_1 source select - between dpi_1 or dpi_3" "0,1"
bitfld.long 0x10 4. "VIF_0_SEL,DPTX vif_0 source select - between dpi_0 or dpi_2\n" "0,1"
bitfld.long 0x10 3. "VIF_3_EN,DPTX vif_3 channel memory clk enable" "0,1"
bitfld.long 0x10 2. "VIF_2_EN,DPTX vif_2 channel memory clk enable" "0,1"
newline
bitfld.long 0x10 1. "VIF_1_EN,DPTX vif_1 channel memory clk enable" "0,1"
bitfld.long 0x10 0. "VIF_0_EN,DPTX vif_0 channel memory clk enable" "0,1"
line.long 0x14 "EDP_DPTX_VIF_SECURE_MODE_CFG,The Register - Configures the security level of the VIF channel (for protecting secure content from going to a non-protected display interface)"
bitfld.long 0x14 3. "VIF_3,vif_3 channel secure mode" "0,1"
bitfld.long 0x14 2. "VIF_2,vif_2 channel secure mode" "0,1"
bitfld.long 0x14 1. "VIF_1,vif_1 channel secure mode" "0,1"
bitfld.long 0x14 0. "VIF_0,vif_0 channel secure mode" "0,1"
line.long 0x18 "EDP_DPTX_VIF_CONN_STATUS,The Register - Returns the status of DPI-VIF connection based on the security mode check.\n 0 indicates that the connection is allowed\n 1 indicates that the connection is not allowed due to security setting mismatch\n When a.."
bitfld.long 0x18 3. "VIF_3,vif_0 security check status" "0,1"
bitfld.long 0x18 2. "VIF_2,vif_0 security check status" "0,1"
bitfld.long 0x18 1. "VIF_1,vif_0 security check status" "0,1"
bitfld.long 0x18 0. "VIF_0,vif_0 security check status" "0,1"
line.long 0x1C "EDP_PHY_CLK_STATUS,The Register - Returns the current status of the phy data clock from DP phy"
bitfld.long 0x1C 0. "VALID,Phy Data Clock Valid Status" "0,1"
tree.end
tree.end
tree "EDP_CORE_APB"
tree "DSS_EDP0_V2A_CORE_VP_REGS_APB"
base ad:0xA000000
group.long 0x00++0x53
line.long 0x00 "EDP_CORE_APB_CTRL_P,APB main control register"
bitfld.long 0x00 3. "APB_XT_RUNSTALL,When 1 stalls the CPU from executing further instructions" "0,1"
bitfld.long 0x00 2. "APB_IRAM_PATH,Unused" "0,1"
newline
bitfld.long 0x00 1. "APB_DRAM_PATH,Unused" "0,1"
bitfld.long 0x00 0. "APB_XT_RESET,Internal uCPU reset" "0,1"
line.long 0x04 "EDP_CORE_XT_INT_CTRL_P,Inernal CPU Interrupt Polarity Control Register"
bitfld.long 0x04 0.--1. "XT_INT_POLARITY,Each bit inverts appropriate interrupt signal provided do internal CPU interrupt input" "0,1,2,3"
line.long 0x08 "EDP_CORE_MAILBOX_FULL_ADDR_P,Mailbox full indication status register"
bitfld.long 0x08 0. "MAILBOX_FULL,Mailbox full indication" "0,1"
line.long 0x0C "EDP_CORE_MAILBOX_EMPTY_ADDR_P,Mailbox empty indication status register"
bitfld.long 0x0C 0. "MAILBOX_EMPTY,Mailbox empty indication" "0,1"
line.long 0x10 "EDP_CORE_MAILBOX0_WR_DATA_P,Mailbox write data register"
hexmask.long.byte 0x10 0.--7. 1. "MAILBOX0_WR_DATA,Mailbox write data"
line.long 0x14 "EDP_CORE_MAILBOX0_RD_DATA_P,Mailbox Read data register"
hexmask.long.byte 0x14 0.--7. 1. "MAILBOX0_RD_DATA,Mailbox Read data"
line.long 0x18 "EDP_CORE_KEEP_ALIVE_P,Software keep alive counter"
hexmask.long.byte 0x18 0.--7. 1. "KEEP_ALIVE_CNT,Software keep alive counter"
line.long 0x1C "EDP_CORE_VER_l_P,Software Version Register"
hexmask.long.byte 0x1C 0.--7. 1. "VER_LSB,Software Version lower byte"
line.long 0x20 "EDP_CORE_VER_H_P,Software Version Register"
hexmask.long.byte 0x20 0.--7. 1. "VER_MSB,Software Version higher byte"
line.long 0x24 "EDP_CORE_VER_LIB_L_ADDR_P,Software Library Version Register"
hexmask.long.byte 0x24 0.--7. 1. "SW_LIB_VER_L,Software Library Version lower byte"
line.long 0x28 "EDP_CORE_VER_LIB_H_ADDR_P,Software Library Version Register"
hexmask.long.byte 0x28 0.--7. 1. "SW_LIB_VER_H,Software Library Version higher byte"
line.long 0x2C "EDP_CORE_SW_DEBUG_l_P,Software/Firmware Debug Register"
hexmask.long.byte 0x2C 0.--7. 1. "SW_DEBUG_7_0,Register used for debug purposes [lower byte]"
line.long 0x30 "EDP_CORE_SW_DEBUG_H_P,Software/Firmware Debug Register"
hexmask.long.byte 0x30 0.--7. 1. "SW_DEBUG_15_8,Register used for debug purposes [higher byte]"
line.long 0x34 "EDP_CORE_MAILBOX_INT_MASK_P,Mailbox Interrupt mask register"
bitfld.long 0x34 1. "MAILBOX_FULL_INT_MASK,Mailbox Full Interrupt mask" "0,1"
bitfld.long 0x34 0. "MAILBOX_EMPTY_INT_MASK,Mailbox Not-empty Interrupt mask" "0,1"
line.long 0x38 "EDP_CORE_MAILBOX_INT_STATUS_P,Mailbox Interrupt Status register"
bitfld.long 0x38 1. "MAILBOX_FULL_INT_STATUS,Mailbox full interrupt" "0,1"
bitfld.long 0x38 0. "MAILBOX_EMPTY_INT_STATUS,Mailbox not-empty interrupt" "0,1"
line.long 0x3C "EDP_CORE_SW_CLK_l_P,Core Clock frequency"
hexmask.long.byte 0x3C 0.--7. 1. "SW_CLOCK_VAL_L,Fractional of the clock decimal value"
line.long 0x40 "EDP_CORE_SW_CLK_H_P,Core Clock frequency"
hexmask.long.byte 0x40 0.--7. 1. "SW_CLOCK_VAL_H,Clock frequency in decimal values"
line.long 0x44 "EDP_CORE_SW_EVENTS0_P,Bits [7:0] of the software events status vector"
hexmask.long.byte 0x44 0.--7. 1. "SW_EVENTS7_0,Each bit represents a separate event reported by the internal uCPU"
line.long 0x48 "EDP_CORE_SW_EVENTS1_P,SW Event 1 register"
hexmask.long.byte 0x48 0.--7. 1. "SW_EVENTS15_8,Each bit represents a separate event reported by the internal uCPU"
line.long 0x4C "EDP_CORE_SW_EVENTS2_P,SW Event 2 register"
hexmask.long.byte 0x4C 0.--7. 1. "SW_EVENTS23_16,Each bit represents a separate event reported by the internal uCPU"
line.long 0x50 "EDP_CORE_SW_EVENTS3_P,SW Event 3 register"
hexmask.long.byte 0x50 0.--7. 1. "SW_EVENTS31_24,Each bit represents a separate event reported by the internal uCPU"
group.long 0x60++0x07
line.long 0x00 "EDP_CORE_XT_OCD_CTRL_P,Internal CPU - On Chip Debug (OCD) Ctrl Register"
bitfld.long 0x00 1. "XT_OCDHALTONRESET,Internal CPU - Halt On Reget configuration register" "0,1"
bitfld.long 0x00 0. "XT_DRESET,Internal CPU - Dreset control register" "0,1"
line.long 0x04 "EDP_CORE_XT_OCD_CTRL_RO_P,Internal CPU - OCD R0 mode configuration"
bitfld.long 0x04 0. "XT_XOCDMODE,Internal CPU - OCD mode configuration" "0,1"
group.long 0x6C++0x07
line.long 0x00 "EDP_CORE_APB_INT_MASK_P,APB Interrupt Mask Register"
bitfld.long 0x00 3. "APB_CEC_INTR_MASK,Reserved field" "0,1"
bitfld.long 0x00 2. "APB_PIF_INTR_MASK,PIF module Interrupt mask" "0,1"
newline
bitfld.long 0x00 1. "APB_SW_INTR_MASK,SW Event Interrupt mask" "0,1"
bitfld.long 0x00 0. "APB_MAILBOX_INTR_MASK,Mailbox Interrupt mask" "0,1"
line.long 0x04 "EDP_CORE_APB_INT_STATUS_P,APB interrupt status register"
bitfld.long 0x04 3. "APB_CEC_INTR_STATUS,Reserved" "0,1"
bitfld.long 0x04 2. "APB_PIF_INTR_STATUS,PIF module Interrupt status" "0,1"
newline
bitfld.long 0x04 1. "APB_SW_INTR_STATUS,SW Events Interrupt status" "0,1"
bitfld.long 0x04 0. "APB_MAILBOX_INTR_STATUS,Mailbox Interrupt status" "0,1"
rgroup.long 0xA0++0x13
line.long 0x00 "EDP_CORE_CDNS_DID_P,Number identifying the IP.Corresponds to IP Part Number"
line.long 0x04 "EDP_CORE_CDNS_RID0_P,Number identifying IP version"
hexmask.long.word 0x04 0.--15. 1. "IP_VERSION,IP version: r"
line.long 0x08 "EDP_CORE_CDNS_RID1_P,Numbers identifying PHY and AUX version"
hexmask.long.word 0x08 16.--31. 1. "AUX_VERSION,AUX version: r"
hexmask.long.word 0x08 0.--15. 1. "PHY_VERSION,PHY version: r"
line.long 0x0C "EDP_CORE_CDNS_CFGS0_P,Numbers identifying the capabilities/configuration of the MHDP controller"
bitfld.long 0x0C 24.--27. "AUDIO_STREAM_NUMBER,Secondary configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 20.--23. "VIDEO_STREAM_NUMBER,Secondary configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 18.--19. "ASF_SUPPORT,Secondary configuration" "0,1,2,3"
bitfld.long 0x0C 16.--17. "DSC_SUPPORT,Secondary configuration" "0,1,2,3"
newline
hexmask.long.byte 0x0C 8.--15. 1. "IP_NUMBER_FAMILY,Main configuration"
hexmask.long.byte 0x0C 0.--7. 1. "IP_NUMBER_CONFIGURATION,Main configuration"
line.long 0x10 "EDP_CORE_CDNS_CFGS1_P,Numbers identifying type of PHY and AUX are integrated in the IPS"
hexmask.long.word 0x10 16.--31. 1. "AUX_NUMBER,AUX IP Number according to versioning scheme"
hexmask.long.word 0x10 0.--15. 1. "PHY_NUMBER,PHY IP Number according to versioning scheme"
group.long 0x800++0x1F
line.long 0x00 "EDP_CORE_SHIFT_PATTERN_IN_3_0_P,HDMI shift pattern 3-0"
hexmask.long.byte 0x00 24.--31. 1. "SOURCE_PHY_SHIFT_PATTERN3,Input to hdmi_pattern_shift"
hexmask.long.byte 0x00 16.--23. 1. "SOURCE_PHY_SHIFT_PATTERN2,Input to hdmi_pattern_shift"
newline
hexmask.long.byte 0x00 8.--15. 1. "SOURCE_PHY_SHIFT_PATTERN1,Input to hdmi_pattern_shift"
hexmask.long.byte 0x00 0.--7. 1. "SOURCE_PHY_SHIFT_PATTERN0,Input to hdmi_pattern_shift"
line.long 0x04 "EDP_CORE_SHIFT_PATTERN_IN_4_7_P,HDMI shift pattern 4-7"
hexmask.long.byte 0x04 24.--31. 1. "SOURCE_PHY_SHIFT_PATTERN7,Input to hdmi_pattern_shift"
hexmask.long.byte 0x04 16.--23. 1. "SOURCE_PHY_SHIFT_PATTERN6,Input to hdmi_pattern_shift"
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hexmask.long.byte 0x04 8.--15. 1. "SOURCE_PHY_SHIFT_PATTERN5,Input to hdmi_pattern_shift"
hexmask.long.byte 0x04 0.--7. 1. "SOURCE_PHY_SHIFT_PATTERN4,Input to hdmi_pattern_shift"
line.long 0x08 "EDP_CORE_SHIFT_PATTERN_IN9_8_P,HDMI shift pattern 9-8 with control bits"
bitfld.long 0x08 18.--20. "SOURCE_PHY_SHIFT_REPETITION,Shift repetition Number" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 17. "SOURCE_PHY_SHIFT_EN,When 1 enable the Shift pattern Mechanism" "0,1"
newline
bitfld.long 0x08 16. "SOURCE_PHY_SHIFT_LOAD,When 1 load the 80 bits of data" "0,1"
hexmask.long.byte 0x08 8.--15. 1. "SOURCE_PHY_SHIFT_PATTERN9,Input to hdmi_pattern_shift"
newline
hexmask.long.byte 0x08 0.--7. 1. "SOURCE_PHY_SHIFT_PATTERN8,Input to hdmi_pattern_shift"
line.long 0x0C "EDP_CORE_PRBS_CNTRL_P,PRBS control"
bitfld.long 0x0C 14.--15. "SOURCE_PHY_PRBS3_OUT_MODE," "0,1,2,3"
bitfld.long 0x0C 12.--13. "SOURCE_PHY_PRBS3_MODE," "0,1,2,3"
newline
bitfld.long 0x0C 10.--11. "SOURCE_PHY_PRBS2_OUT_MODE," "0,1,2,3"
bitfld.long 0x0C 8.--9. "SOURCE_PHY_PRBS2_MODE," "0,1,2,3"
newline
bitfld.long 0x0C 6.--7. "SOURCE_PHY_PRBS1_OUT_MODE," "0,1,2,3"
bitfld.long 0x0C 4.--5. "SOURCE_PHY_PRBS1_MODE," "0,1,2,3"
newline
bitfld.long 0x0C 2.--3. "SOURCE_PHY_PRBS0_OUT_MODE," "0,1,2,3"
bitfld.long 0x0C 0.--1. "SOURCE_PHY_PRBS0_MODE," "0,1,2,3"
line.long 0x10 "EDP_CORE_PRBS_ERR_INSERTION_P,PRBS error insertion"
bitfld.long 0x10 19.--23. "NUMBER_OF_ERRORS3,The number of errors to be inserted when add_error is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 18. "ADD_ERROR3,When high the PRBS generator inserts the number of errors written in number_of_errors field" "0,1"
newline
bitfld.long 0x10 13.--17. "NUMBER_OF_ERRORS2,The number of errors to be inserted when add_error is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 12. "ADD_ERROR2,When high the PRBS generator inserts the number of errors written in number_of_errors field" "0,1"
newline
bitfld.long 0x10 7.--11. "NUMBER_OF_ERRORS1,The number of errors to be inserted when add_error is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 6. "ADD_ERROR1,When high the PRBS generator inserts the number of errors written in number_of_errors field" "0,1"
newline
bitfld.long 0x10 1.--5. "NUMBER_OF_ERRORS0,The number of errors to be inserted when add_error is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0. "ADD_ERROR0,When high the PRBS generator inserts the number of errors written in number_of_errors field" "0,1"
line.long 0x14 "EDP_CORE_LANES_CONFIG_P,Lane control register: swap. order. polarity"
bitfld.long 0x14 22. "SOURCE_PHY_20_10,1'b" "0,1"
bitfld.long 0x14 21. "SOURCE_PHY_COMB_BYPASS,Bypass swap invert and all combination" "0,1"
newline
bitfld.long 0x14 20. "SOURCE_PHY_DATA_DEL_EN,enable configurable delay of lanes to be activated.if this bit is 0 the delay is only activated for DisplayPort mode with source_phy_data_sel=prbs or shift-mem" "0,1"
bitfld.long 0x14 19. "SOURCE_PHY_LANE3_POLARITY,Reverse polarity of data lane3" "0,1"
newline
bitfld.long 0x14 18. "SOURCE_PHY_LANE2_POLARITY,Reverse polarity of data lane2" "0,1"
bitfld.long 0x14 17. "SOURCE_PHY_LANE1_POLARITY,Reverse polarity of data lane1" "0,1"
newline
bitfld.long 0x14 16. "SOURCE_PHY_LANE0_POLARITY,Reverse polarity of data lane0" "0,1"
bitfld.long 0x14 12.--15. "SOURCE_PHY_AUX_SPARE,Spare bits for aux **1.1**" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 11. "SOURCE_PHY_LANE3_LSB_MSB,Reverse order of data lane3" "0,1"
bitfld.long 0x14 10. "SOURCE_PHY_LANE2_LSB_MSB,Reverse order of data lane2" "0,1"
newline
bitfld.long 0x14 9. "SOURCE_PHY_LANE1_LSB_MSB,Reverse order of data lane1" "0,1"
bitfld.long 0x14 8. "SOURCE_PHY_LANE0_LSB_MSB,Reverse order of data lane0" "0,1"
newline
bitfld.long 0x14 6.--7. "SOURCE_PHY_LANE3_SWAP,Swap control lane3" "0,1,2,3"
bitfld.long 0x14 4.--5. "SOURCE_PHY_LANE2_SWAP,Swap control lane2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "SOURCE_PHY_LANE1_SWAP,Swap control lane1" "0,1,2,3"
bitfld.long 0x14 0.--1. "SOURCE_PHY_LANE0_SWAP,Swap control lane0" "0,1,2,3"
line.long 0x18 "EDP_CORE_PHY_DATA_SEL_P,PHY data select DP/HDMI and HDMI data source"
bitfld.long 0x18 3.--4. "SOURCE_PHY_MHDP_SEL,3'd" "0,1,2,3"
bitfld.long 0x18 0.--2. "SOURCE_PHY_DATA_SEL,3'd" "0,1,2,3,4,5,6,7"
line.long 0x1C "EDP_CORE_LANES_DEL_VAL_P,Lane delay control"
bitfld.long 0x1C 12.--15. "SOURCE_PHY_LANE3_DEL_VAL,delay for lane 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "SOURCE_PHY_LANE2_DEL_VAL,delay for lane 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "SOURCE_PHY_LANE1_DEL_VAL,delay for lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "SOURCE_PHY_LANE0_DEL_VAL,delay for lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x904++0x07
line.long 0x00 "EDP_CORE_SOURCE_DPTX_CAR_P,DP TX clock and reset ctrl register"
bitfld.long 0x00 25. "CFG_DPTX_VIF_CLK_RSTN_EN7,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 24. "CFG_DPTX_VIF_CLK_EN7,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 23. "CFG_DPTX_VIF_CLK_RSTN_EN6,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 22. "CFG_DPTX_VIF_CLK_EN6,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 21. "CFG_DPTX_VIF_CLK_RSTN_EN5,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 20. "CFG_DPTX_VIF_CLK_EN5,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 19. "CFG_DPTX_VIF_CLK_RSTN_EN4,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 18. "CFG_DPTX_VIF_CLK_EN4,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 17. "CFG_DPTX_VIF_CLK_RSTN_EN3,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 16. "CFG_DPTX_VIF_CLK_EN3,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 15. "CFG_DPTX_VIF_CLK_RSTN_EN2,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 14. "CFG_DPTX_VIF_CLK_EN2,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 13. "CFG_DPTX_VIF_CLK_RSTN_EN1,dptx_vif_clk_rstn enable for stream number" "0,1"
bitfld.long 0x00 12. "CFG_DPTX_VIF_CLK_EN1,dptx_vif_clk enable for stream number" "0,1"
newline
bitfld.long 0x00 11. "DPTX_FRMR_DATA_CLK_RSTN_EN,dptx_frmr_data_clk_rstn enable - active low" "0,1"
bitfld.long 0x00 10. "DPTX_FRMR_DATA_CLK_EN,dptx_frmr_data_clk enable - active high" "0,1"
newline
bitfld.long 0x00 9. "DPTX_PHY_DATA_RSTN_EN,dptx_phy_data_rstn enable - active low" "0,1"
bitfld.long 0x00 8. "DPTX_PHY_DATA_CLK_EN,dptx_phy_data_clk enable - active high" "0,1"
newline
bitfld.long 0x00 7. "DPTX_PHY_CHAR_RSTN_EN,dptx_phy_char_rstn enable - active low" "0,1"
bitfld.long 0x00 6. "DPTX_PHY_CHAR_CLK_EN,dptx_phy_char_clk enable - active high" "0,1"
newline
bitfld.long 0x00 5. "SOURCE_AUX_SYS_CLK_RSTN_EN,source_aux_sys_clk_rstn enable - active low" "0,1"
bitfld.long 0x00 4. "SOURCE_AUX_SYS_CLK_EN,source_aux_sys_clk enable - active high" "0,1"
newline
bitfld.long 0x00 3. "DPTX_SYS_CLK_RSTN_EN,dptx_sys_clk_rstn enable - active low" "0,1"
bitfld.long 0x00 2. "DPTX_SYS_CLK_EN,dptx_sys_clk enable - active high" "0,1"
newline
bitfld.long 0x00 1. "CFG_DPTX_VIF_CLK_RSTN_EN,dptx_vif_clk_rstn enable - active low" "0,1"
bitfld.long 0x00 0. "CFG_DPTX_VIF_CLK_EN,dptx_vif_clk enable - active high" "0,1"
line.long 0x04 "EDP_CORE_SOURCE_PHY_CAR_P,Source PHY clock and reset ctrl register"
bitfld.long 0x04 3. "SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN,source_phy_char_out_clk_rstn enable - active low" "0,1"
bitfld.long 0x04 2. "SOURCE_PHY_CHAR_OUT_CLK_EN,source_phy_char_out_clk enable - active high" "0,1"
newline
bitfld.long 0x04 1. "SOURCE_PHY_DATA_OUT_CLK_RSTN_EN,source_phy_data_out_clk_rstn enable - active low" "0,1"
bitfld.long 0x04 0. "SOURCE_PHY_DATA_OUT_CLK_EN,source_phy_data_out_clk enable - active high" "0,1"
group.long 0x918++0x13
line.long 0x00 "EDP_CORE_SOURCE_PKT_CAR_P,PKT clock and reset ctrl register"
bitfld.long 0x00 17. "SOURCE_PKT_DATA_RSTN_EN7,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 16. "SOURCE_PKT_DATA_CLK_EN7,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 15. "SOURCE_PKT_DATA_RSTN_EN6,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 14. "SOURCE_PKT_DATA_CLK_EN6,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 13. "SOURCE_PKT_DATA_RSTN_EN5,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 12. "SOURCE_PKT_DATA_CLK_EN5,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 11. "SOURCE_PKT_DATA_RSTN_EN4,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 10. "SOURCE_PKT_DATA_CLK_EN4,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 9. "SOURCE_PKT_DATA_RSTN_EN3,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 8. "SOURCE_PKT_DATA_CLK_EN3,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 7. "SOURCE_PKT_DATA_RSTN_EN2,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 6. "SOURCE_PKT_DATA_CLK_EN2,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 5. "SOURCE_PKT_DATA_RSTN_EN1,source_pkt_data_rstn_en" "0,1"
bitfld.long 0x00 4. "SOURCE_PKT_DATA_CLK_EN1,source_pkt_data_clk_en" "0,1"
newline
bitfld.long 0x00 3. "SOURCE_PKT_SYS_RSTN_EN,source_pkt_sys_rstn_en - active low" "0,1"
bitfld.long 0x00 2. "SOURCE_PKT_SYS_CLK_EN,source_pkt_sys_clk_en - active high" "0,1"
newline
bitfld.long 0x00 1. "SOURCE_PKT_DATA_RSTN_EN,source_pkt_data_rstn_en - active low" "0,1"
bitfld.long 0x00 0. "SOURCE_PKT_DATA_CLK_EN,source_pkt_data_clk_en - active high" "0,1"
line.long 0x04 "EDP_CORE_SOURCE_AIF_CAR_P,AIF clock and reset ctrl register"
bitfld.long 0x04 3. "SOURCE_AIF_SYS_RSTN_EN,source_aif_sys_rstn enable - active low" "0,1"
bitfld.long 0x04 2. "SOURCE_AIF_SYS_CLK_EN,source_aif_sys_clk enable - active high" "0,1"
newline
bitfld.long 0x04 1. "SOURCE_AIF_PKT_CLK_RSTN_EN,source_aif_pkt_clk_rstn enable - active low" "0,1"
bitfld.long 0x04 0. "SOURCE_AIF_PKT_CLK_EN,source_aif_pkt_clk enable - active high" "0,1"
line.long 0x08 "EDP_CORE_SOURCE_CIPHER_CAR_P,Cipher clock and reset ctrl register"
bitfld.long 0x08 3. "SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN,source_cipher_system_clk_rstn enable - active low [Only when HDCP used]" "0,1"
bitfld.long 0x08 2. "SOURCE_CIPHER_SYS_CLK_EN,source_cipher_sys_clk enable - active high [Only when HDCP used]" "0,1"
newline
bitfld.long 0x08 1. "SOURCE_CIPHER_CHAR_CLK_RSTN_EN,source_cipher_char_clk_rstn enable - active low [Only when HDCP used]" "0,1"
bitfld.long 0x08 0. "SOURCE_CIPHER_CHAR_CLK_EN,source_cipher_char_clk enable - active high [Only when HDCP used]" "0,1"
line.long 0x0C "EDP_CORE_SOURCE_CRYPTO_CAR_P,Crypto clock and reset ctrl register"
bitfld.long 0x0C 1. "SOURCE_CRYPTO_SYS_CLK_RSTN_EN,source_crypto_sys_clk_rstn enable - active low [Only when HDCP used]" "0,1"
bitfld.long 0x0C 0. "SOURCE_CRYPTO_SYS_CLK_EN,source_crypto_sys_clk enable - active high [Only when HDCP used]" "0,1"
line.long 0x10 "EDP_CORE_SOURCE_SPDIF_CAR_P,SPDIF clock and reset ctrl register"
bitfld.long 0x10 3. "SPDIF_MCLK_RSTN_EN0,spdif_mclk_rstn enable" "0,1"
bitfld.long 0x10 2. "SPDIF_MCLK_EN0,spdif_mclk enable" "0,1"
newline
bitfld.long 0x10 1. "SPDIF_CDR_CLK_RSTN_EN0,spdif_cdr_clk_rstn enable" "0,1"
bitfld.long 0x10 0. "SPDIF_CDR_CLK_EN0,spdif_cdr_clk enable" "0,1"
group.long 0xA00++0x3B
line.long 0x00 "EDP_CORE_CM_CTRL_P,Clock Meter control"
bitfld.long 0x00 4.--6. "I2S_MULT,Select the division of N value for different I2S TDM configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "SEL_AUD_LANE_REF,When 1 Select Audio CLK as a reference [HDMI]" "0,1"
newline
bitfld.long 0x00 2. "I2S_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for I2S" "0,1"
bitfld.long 0x00 1. "SPDIF_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for SPDIF" "0,1"
newline
bitfld.long 0x00 0. "NMVID_SEL_EXTERNAL,When 1 Select external values of NMVID [N/A]" "0,1"
line.long 0x04 "EDP_CORE_CM_I2S_CTRL_P,I2S clock control"
bitfld.long 0x04 24.--27. "I2S_MEAS_TOLERANCE,Measurement tolerance of Audio clock to be stable in clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x04 0.--23. 1. "I2S_REF_CYC,Reference cycles for I2S Audio meter"
line.long 0x08 "EDP_CORE_CM_SPDIF_CTRL_P,SPDIF clock control"
bitfld.long 0x08 24.--27. "SPDIF_MEAS_TOLERANCE,SPDIF measurement tolerance to be stable in clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x08 0.--23. 1. "SPDIF_REF_CYC,Reference cycles of SPDIF measurement"
line.long 0x0C "EDP_CORE_CM_VID_CTRL_P,Video clock control"
bitfld.long 0x0C 24.--27. "NMVID_MEAS_TOLERANCE,Video measurement tolerance in pixel clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x0C 0.--23. 1. "NMVID_REF_CYC,Video Reference cycles"
line.long 0x10 "EDP_CORE_CM_LANE_CTRL_P,Lane control"
hexmask.long.tbyte 0x10 0.--23. 1. "LANE_REF_CYC,Reference cycles when using lane clock as Reference [DP]"
line.long 0x14 "EDP_CORE_I2S_NM_STABLE_P,I2S clock stable. audio clock measured"
bitfld.long 0x14 0. "I2S_MNAUD_STABLE,I2S NMAUD Mesurment stable" "0,1"
line.long 0x18 "EDP_CORE_I2S_NCTS_STABLE_P,I2S clock stable. lane clock measured"
bitfld.long 0x18 0. "I2S_NCTS_STABLE,i2s CTS measurement stable" "0,1"
line.long 0x1C "EDP_CORE_SPDIF_NM_STABLE_P,SPDIF clock stable. audio clock measured"
bitfld.long 0x1C 0. "SPDIF_MNAUD_STABLE,SPDIF NMAUD measurement stable" "0,1"
line.long 0x20 "EDP_CORE_SPDIF_NCTS_STABLE_P,SPDIF clock stable. lane clock measured"
bitfld.long 0x20 0. "SPDIF_NCTS_STABLE,SPDIF CTS measurement stable" "0,1"
line.long 0x24 "EDP_CORE_NMVID_MEAS_STABLE_P,Video clock stable"
bitfld.long 0x24 0. "ST_NMVID_MEAS_STABLE,Pixel clock NMVID measurement stable" "0,1"
line.long 0x28 "EDP_CORE_CM_VID_MEAS_P,Video cycles measure"
bitfld.long 0x28 24. "NMVID_MEAS_VALID_INDC,When Toggle Valid pulse is generated to sample MNVID fix value" "0,1"
hexmask.long.tbyte 0x28 0.--23. 1. "NMVID_MEAS_CYC,Fixed Value for NVID The MVID is nmvid_ref_cyc"
line.long 0x2C "EDP_CORE_CM_AUD_MEAS_P,Audio cycles measure"
bitfld.long 0x2C 24. "NMAUD_MEAS_VALID_INDC,When Toggle Valid pulse is generated to sample MNAUD fix value" "0,1"
hexmask.long.tbyte 0x2C 0.--23. 1. "NMAUD_MEAS_CYC,Fixed Value for NAUD The MAUD is lane_ref_cyc"
line.long 0x30 "EDP_CORE_I2S_MEAS_P,I2S clock measurement HDMI"
hexmask.long.tbyte 0x30 0.--23. 1. "I2_MEAS,I2S measurement value"
line.long 0x34 "EDP_CORE_SPDIF_MEAS_P,SPDIF clock measurement HDMI"
hexmask.long.tbyte 0x34 0.--23. 1. "SPDIF_MEAS,SPDIF Clock Meter measurement value [in DP]"
line.long 0x38 "EDP_CORE_NMVID_MEAS_P,Video clock measurement"
hexmask.long.tbyte 0x38 0.--23. 1. "NMVID_MEAS,Video clock measurement value"
group.long 0xA40++0x03
line.long 0x00 "EDP_CORE_CM_CTRL_P_j,Clock Meter control Offset = A40h + (j * 40h); where j = 0h to 2h"
bitfld.long 0x00 4.--6. "I2S_MULT,Select the division of N value for different I2S TDM configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "SEL_AUD_LANE_REF,When 1 Select Audio CLK as a reference [HDMI]" "0,1"
newline
bitfld.long 0x00 2. "I2S_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for I2S" "0,1"
bitfld.long 0x00 1. "SPDIF_SEL_EXTERNAL,When 1 Select external values of NMAUD [N/A] for SPDIF" "0,1"
newline
bitfld.long 0x00 0. "NMVID_SEL_EXTERNAL,When 1 Select external values of NMVID [N/A]" "0,1"
group.long 0xA4C++0x03
line.long 0x00 "EDP_CORE_CM_VID_CTRL_P_j,Video clock control Offset = A4Ch + (j * 40h); where j = 0h to 2h"
bitfld.long 0x00 24.--27. "NMVID_MEAS_TOLERANCE,Video measurement tolerance in pixel clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--23. 1. "NMVID_REF_CYC,Video Reference cycles"
rgroup.long 0xA64++0x07
line.long 0x00 "EDP_CORE_NMVID_MEAS_STABLE_P_J,Video clock stable Offset = A64h + (j * 40h); where j = 0h to 2h"
bitfld.long 0x00 0. "ST_NMVID_MEAS_STABLE,Pixel clock NMVID measurement stable" "0,1"
line.long 0x04 "EDP_CORE_CM_VID_MEAS_P_J,Video cycles measure Offset = A68h + (j * 40h); where j = 0h to 2h"
bitfld.long 0x04 24. "NMVID_MEAS_VALID_INDC,When Toggle Valid pulse is generated to sample MNVID fix value" "0,1"
hexmask.long.tbyte 0x04 0.--23. 1. "NMVID_MEAS_CYC,Fixed Value for NVID The MVID is nmvid_ref_cyc"
rgroup.long 0xA78++0x03
line.long 0x00 "EDP_CORE_NMVID_MEAS_P_J,Video clock measurement Offset = A78h + (j * 40h); where j = 0h to 2h"
hexmask.long.tbyte 0x00 0.--23. 1. "NMVID_MEAS,Video clock measurement value"
group.long 0xB00++0x17
line.long 0x00 "EDP_CORE_BND_HSYNC2VSYNC_P_j,Video Input Interface Setting Register Offset = B00h + (j * 20h); where j = 0h to 3h"
bitfld.long 0x00 14. "IP_VIF_ALIGNMENT,Alignment of the input pixel data at the pixel interface" "0,1"
bitfld.long 0x00 13. "IP_VIF_BYPASS,Bypass video interface" "0,1"
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bitfld.long 0x00 12. "IP_DET_EN,Enable detection of Interlace formats after decided if the polarity is Automatic or Manual detection" "0,1"
hexmask.long.word 0x00 0.--11. 1. "IP_DTCT_WIN,Bound for HSYNC to VSYNC for all fields"
line.long 0x04 "EDP_CORE_HSYNC2VSYNC_F1_L1_P_J,Status of HSYNC to VSYNC Distance Counter 1"
hexmask.long.word 0x04 0.--15. 1. "IP_DTCT_HSYNC2VSYNC_F1,Value of HSYNC to VSYNC field 1"
line.long 0x08 "EDP_CORE_HSYNC2VSYNC_F2_L1_P_J,Status of HSYNC to VSYNC Distance Counter 2 Offset = B08h + (j * 20h); where j = 0h to 3h"
hexmask.long.word 0x08 0.--15. 1. "IP_DTCT_HSYNC2VSYNC_F2,Value of HSYNC to VSYNC field 2"
line.long 0x0C "EDP_CORE_HSYNC2VSYNC_STATUS_P_j,Video Interface Status Register Offset = B0Ch + (j * 20h); where j = 0h to 3h"
bitfld.long 0x0C 3. "IP_DTCT_HJITTER,Asserted when jitter is observed on htotal i.e" "0,1"
bitfld.long 0x0C 2. "IP_DTCT_VJITTER,Asserted when jitter is observed on vtotal i.e" "0,1"
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bitfld.long 0x0C 1. "IP_DCT_IP,When asserted interlaced format is detected else progressive format" "0,1"
bitfld.long 0x0C 0. "IP_DTCT_ERR,Asserted when HSYNC to VSYNC bound is violated" "0,1"
line.long 0x10 "EDP_CORE_HSYNC2VSYNC_POL_CTRL_P_j,Setting Polarity of HSYNC and VSYNC Offset = B10h + (j * 20h); where j = 0h to 3h"
bitfld.long 0x10 2. "VPOL,VSYNC polarity" "0,1"
bitfld.long 0x10 1. "HPOL,HSYNC polarity" "0,1"
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bitfld.long 0x10 0. "VIF_AUTO_MODE,Automatic or Manual configuration of the polarity" "0,1"
line.long 0x14 "EDP_CORE_DSC_CTRL_P_j,DSC Setting Register Offset = B14h + (j * 20h); where j = 0h to 3h"
bitfld.long 0x14 2. "DSC_REG_UPDATE,DSC registers update: active HIGH" "0,1"
bitfld.long 0x14 1. "DSC_SW_RST,DSC software reset: active HIGH" "0,1"
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bitfld.long 0x14 0. "DSC_EN,DSC enable bit" "0,1"
group.long 0x2000++0x1F
line.long 0x00 "EDP_CORE_DP_TX_PHY_CONFIG_REG_P,DPTX PHY control"
bitfld.long 0x00 21. "DP_TX_PHY_10BIT_ENABLE,Used to enable" "0,1"
bitfld.long 0x00 18.--20. "DP_TX_PHY_LANE3_SKEW,Specifies the programmable lane3 skew" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15.--17. "DP_TX_PHY_LANE2_SKEW,Specifies the programmable lane2 skew" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "DP_TX_PHY_LANE1_SKEW,Specifies the programmable lane1 skew" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "DP_TX_PHY_LANE0_SKEW,Specifies the programmable lane0 skew" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "DP_TX_PHY_TRAINING_AUTOMATIC,When set the dp_tx_phy_scrambler_bypass and the dp_tx_phy_encoder_bypass bits are ignored during training pattern generation" "0,1"
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bitfld.long 0x00 7. "DP_TX_PHY_SKEW_BYPASS,Used to bypass the lane skew" "0,1"
bitfld.long 0x00 6. "DP_TX_PHY_ENCODER_BYPASS,Used to bypass the encoder" "0,1"
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bitfld.long 0x00 5. "DP_TX_PHY_SCRAMBLER_BYPASS,Used to bypass the scrambler" "0,1"
bitfld.long 0x00 1.--4. "DP_TX_PHY_TRAINING_TYPE,Specifies the training pattern type used as follows" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "DP_TX_PHY_TRAINING_ENABLE,Enables the training sequence [when set to 1]" "0,1"
line.long 0x04 "EDP_CORE_DP_TX_PHY_SW_RESET_P,DPTC PHY software reset"
bitfld.long 0x04 0. "DP_TX_PHY_SW_RST,Software reset" "0,1"
line.long 0x08 "EDP_CORE_DP_TX_PHY_SCRAMBLER_SEED_P,Scrambler seed"
hexmask.long.word 0x08 0.--15. 1. "DP_TX_PHY_SCRAMBLER_SEED,Scrambler seed range"
line.long 0x0C "EDP_CORE_DP_TX_PHY_TRAINING_01_04_P,Custom training value bytes 1-4"
hexmask.long.byte 0x0C 24.--31. 1. "DP_TX_PHY_TRAINING_04,Byte 4 of"
hexmask.long.byte 0x0C 16.--23. 1. "DP_TX_PHY_TRAINING_03,Byte 3 of"
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hexmask.long.byte 0x0C 8.--15. 1. "DP_TX_PHY_TRAINING_02,Byte 2 of"
hexmask.long.byte 0x0C 0.--7. 1. "DP_TX_PHY_TRAINING_01,Byte 1 of"
line.long 0x10 "EDP_CORE_DP_TX_PHY_TRAINING_05_08_P,Custom training value bytes 5-8"
hexmask.long.byte 0x10 24.--31. 1. "DP_TX_PHY_TRAINING_08,Byte 8 of"
hexmask.long.byte 0x10 16.--23. 1. "DP_TX_PHY_TRAINING_07,Byte 7 of"
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hexmask.long.byte 0x10 8.--15. 1. "DP_TX_PHY_TRAINING_06,Byte 6 of"
hexmask.long.byte 0x10 0.--7. 1. "DP_TX_PHY_TRAINING_05,Byte 5 of"
line.long 0x14 "EDP_CORE_DP_TX_PHY_TRAINING_09_10_P,Custom training value bytes 9-10"
hexmask.long.byte 0x14 8.--15. 1. "DP_TX_PHY_TRAINING_10,Byte 10 of"
hexmask.long.byte 0x14 0.--7. 1. "DP_TX_PHY_TRAINING_09,Byte 9 of"
line.long 0x18 "EDP_CORE_DP_TX_PHY_SR_INTERVAL_P,Custom CP2520 SR interval"
hexmask.long.word 0x18 0.--15. 1. "DP_TX_PHY_SR_INTERVAL,CP2520 test pattern SR Interval definition"
line.long 0x1C "EDP_CORE_DP_TX_PHY_FEC_TEST_P,FEC IP test register"
bitfld.long 0x1C 9. "FEC_L23_EXT_DIAG_TEST_EN,Encoder 1 external diagnostic test enable" "0,1"
bitfld.long 0x1C 8. "FEC_L01_EXT_DIAG_TEST_EN,Encoder 0 external diagnostic test enable" "0,1"
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bitfld.long 0x1C 7. "FEC_L23_8B10B_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the 8b10b check of the FEC IP datapath for lanes 2 and 3" "0,1"
bitfld.long 0x1C 6. "FEC_L23_PARITY_ENC_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity enc check of the FEC IP datapath for lanes 2 and 3" "0,1"
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bitfld.long 0x1C 5. "FEC_L23_PARITY_GEN_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity gen check of the FEC IP datapaths for lanes 2 and 3" "0,1"
bitfld.long 0x1C 4. "FEC_L23_DATA_BYPASS_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the bypass check for of the FEC IP datapathe for lanes 2 and 3" "0,1"
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bitfld.long 0x1C 3. "FEC_L01_8B10B_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the 8b10b check of the FEC IP datapath for lanes 0 and 1" "0,1"
bitfld.long 0x1C 2. "FEC_L01_PARITY_ENC_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity enc check of the FEC IP datapath for lanes 0 and 1" "0,1"
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bitfld.long 0x1C 1. "FEC_L01_PARITY_GEN_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the parity gen check of the FEC IP datapath for lanes 0 and 1" "0,1"
bitfld.long 0x1C 0. "FEC_L01_DATA_BYPASS_TEST,When asserted a corruption is injected at the interface of the internal diagnostic module which generate a fault in the bypass check for of the FEC IP datapath for lanes 0 and 1" "0,1"
group.long 0x2100++0x17
line.long 0x00 "EDP_CORE_HPD_IRQ_DET_MIN_TIMER_P,HPD min timer for irq. define the minimum pclk cycles that the HPD pulse will be considered as IRQ"
hexmask.long.tbyte 0x00 0.--23. 1. "HPD_IRQ_DET_MIN_TIMER,HPD min timer for interrupt"
line.long 0x04 "EDP_CORE_HPD_IRQ_DET_MAX_TIMER_P,HPD max timer for irq. define the maximum pclk cycles that the HPD pulse will be considered as IRQ"
hexmask.long.tbyte 0x04 0.--23. 1. "HPD_IRQ_DET_MAX_TIMER,HPD max timer"
line.long 0x08 "EDP_CORE_HPD_UNPLGED_DET_MIN_TIMER_P,HPD min timer for HPD detect. define the minimum pclk cycles that the HPD is low"
hexmask.long.tbyte 0x08 0.--23. 1. "HPD_UNPLGED_DET_MIN_TIMER,HPD unplugged timer"
line.long 0x0C "EDP_CORE_HPD_STABLE_TIMER_P,Timer for detecting HPD stable. count in system clock cycles"
hexmask.long.tbyte 0x0C 0.--23. 1. "HPD_STABLE_TIMER,HPD stable timer counter setup"
line.long 0x10 "EDP_CORE_HPD_FILTER_TIMER_P,Timer for filtering small pulses on HPD input"
hexmask.long.tbyte 0x10 0.--23. 1. "HPD_FILTER_TIMER,HPD glitch filter counter setup"
line.long 0x14 "EDP_CORE_HPD_DBNC_TIMER_P,HPD debouncer control"
bitfld.long 0x14 24. "SEL_HPDTX_DB_22,Debouncer enable" "0,1"
hexmask.long.tbyte 0x14 0.--23. 1. "HPD_DEBOUNCE_TIMER,HPD debounce timer setup"
group.long 0x211C++0x07
line.long 0x00 "EDP_CORE_HPD_EVENT_MASK_P,Mask of HPD interrupt and status"
bitfld.long 0x00 0.--3. "HPD_EVENTS_MASK,HPD mask events" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "EDP_CORE_HPD_EVENT_DET_P,HPD interrupt and status"
bitfld.long 0x04 4. "HPD_IN_SYNC,HDP in sync detected" "0,1"
bitfld.long 0x04 3. "HPD_RE_PLGED_DET_EVENT,HPD Re-Plugged event detected" "0,1"
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bitfld.long 0x04 2. "HPD_UNPLUGGED_DET_ACLK,HPD Un-Plugged event detected" "0,1"
bitfld.long 0x04 1. "HPD_STABLE,HPD Stable indication" "0,1"
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bitfld.long 0x04 0. "HPD_IRQ_DET_EVENT,Bit" "0,1"
group.long 0x2200++0x0B
line.long 0x00 "EDP_CORE_DP_FRAMER_GLOBAL_CONFIG_P,Global configuration of the framer module"
bitfld.long 0x00 7. "WR_VHSYNC_FALL,When set to 1 change the write state machine to sync on falling edge of vsync" "0,1"
bitfld.long 0x00 6. "ENC_RST_DIS,Unused" "0,1"
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bitfld.long 0x00 5. "NO_VIDEO,No-video mode configuration bit" "0,1"
bitfld.long 0x00 3. "GLOBAL_EN,Global enable for complete Framer module active high" "0,1"
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bitfld.long 0x00 2. "MST_SST,Mode select" "0,1"
bitfld.long 0x00 0.--1. "NUM_LANES,Number of lanes" "0,1,2,3"
line.long 0x04 "EDP_CORE_DP_SW_RESET_P,Unused"
bitfld.long 0x04 0. "SW_RST,Unused" "0,1"
line.long 0x08 "EDP_CORE_DP_FRAMER_TU_P,Transfer Unit configuration register"
hexmask.long.word 0x08 16.--24. 1. "BS_SR_REPLACE_POSITION,Static debug register"
bitfld.long 0x08 15. "TU_CNT_RST_EN,Unused" "0,1"
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hexmask.long.byte 0x08 8.--14. 1. "TU_SIZE,Transfer Unit size"
bitfld.long 0x08 6. "TU_SST_FAST_DRAIN,Allow the video FIFO to drain faster at end of line" "0,1"
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bitfld.long 0x08 0.--5. "TU_VALID_SYMBOLS,Number of valid symbols per Transfer Unit [TU]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2218++0x03
line.long 0x00 "EDP_CORE_DP_FRAMER_BS_SR_INTRVL_P,SR insertion interval for SST mode"
hexmask.long.word 0x00 0.--9. 1. "BS_SR_INTERVAL,Static debug register"
group.long 0x2258++0x0F
line.long 0x00 "EDP_CORE_DP_MTPH_ECF_SLOTS_31_0_P,Bits [31:1] contains which MST timeslot 31-1 should be encrypted.Bit [0] must be set to 1 to enable encryption.Relevant only in MST mode"
line.long 0x04 "EDP_CORE_DP_MTPH_ECF_SLOTS_63_32_P,Contains which MST timeslot 63-32 should be encrypted"
line.long 0x08 "EDP_CORE_DP_MTPH_LVP_SYMBOL_P,Link Verification Pattern value to be inserted in the MTP header"
hexmask.long.word 0x08 0.--15. 1. "MTPH_LVP_SYM,Symbol value for LINK VERIFICATION PATTERN [LVP]"
line.long 0x0C "EDP_CORE_DP_MTPH_CONTROL_P,MTP header control"
bitfld.long 0x0C 2. "MTPH_LVP_EN,Unused" "0,1"
bitfld.long 0x0C 1. "MTPH_ACT_EN,MST feature when written with value 1 an ACT sequence will be triggered for slot allocation control" "0,1"
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bitfld.long 0x0C 0. "MTPH_ECF_EN,Unused" "0,1"
rgroup.long 0x226C++0x03
line.long 0x00 "EDP_CORE_DP_MTPH_STATUS_P,MTP header status"
bitfld.long 0x00 0. "MTPH_ACT_STATUS,Status of ACT insertion" "0,1"
group.long 0x2300++0x17
line.long 0x00 "EDP_CORE_DPTX_LANE_EN_P,DPTX lane enable"
bitfld.long 0x00 0.--3. "DPTX_LANE_ENABLE,DPTX lane enable each lane as a bit when 1 lane is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "EDP_CORE_DPTX_ENHNCD_P,DPTX enhanced mode control register"
bitfld.long 0x04 0. "DPTX_ENHANCED_MODE,Enhanced mode control" "0,1"
line.long 0x08 "EDP_CORE_DPTX_INT_MASK_P,DPTX Interrupt mask"
bitfld.long 0x08 1. "FRAMER_SRC_INT_MASK,Framer mask interrupt" "0,1"
bitfld.long 0x08 0. "HPD_SRC_INT_MASK,HPD mask interrupt" "0,1"
line.long 0x0C "EDP_CORE_DPTX_INT_STATUS_P,DPTX interrupt status register"
bitfld.long 0x0C 1. "FRAMER_SRC_INT,Framer interrupt - not used" "0,1"
bitfld.long 0x0C 0. "HPD_SRC_INT,HPD interrupt" "0,1"
line.long 0x10 "EDP_CORE_DPTX_FEC_CTRL_P,DPTX FEC control register"
bitfld.long 0x10 1. "CFG_FEC_READY,Equivalent DPCD register FEC_READY enable alternative CP coding" "0,1"
bitfld.long 0x10 0. "CFG_FEC_EN,FEC Enable" "0,1"
line.long 0x14 "EDP_CORE_DPTX_FEC_STATUS_P,FEC status register"
bitfld.long 0x14 1.--4. "FEC_FSM_STATUS,FEC FSM status " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0. "FEC_BUSY,FEC Active status" "0,1"
rgroup.long 0x2400++0x0F
line.long 0x00 "EDP_CORE_HDCP_DP_STATUS_P,HDCP DP status register"
bitfld.long 0x00 5. "PSLVERR_HDCP,APB slave error status from HDCP module has been reported when this bit is set to 1" "0,1"
bitfld.long 0x00 1.--4. "HDCP_DP_ENCRYPTION_ENABLE,Encryption is enabled when this bit is set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "HDCP_DP_AUTHENTICATED,HDCP 1.3 authentication is enabled when this bit is set to 1" "0,1"
line.long 0x04 "EDP_CORE_HDCP_DP_CONFIG_P,HDCP DP config register"
bitfld.long 0x04 6. "SST_HDCP_ENCRYPT_DIS,Disable automatic HDCP encryption in SST mode when cipher is authenticated" "0,1"
bitfld.long 0x04 5. "HDCP_VBID5_ALIGN_DIS,Debug register no longer used" "0,1"
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bitfld.long 0x04 3.--4. "HDCP_DP_BYPASS,HDCP DP bypass" "0,1,2,3"
bitfld.long 0x04 0.--2. "HDCP_DP_VERSION,HDCP version" "0,1,2,3,4,5,6,7"
line.long 0x08 "EDP_CORE_HDCP_DP_SW_RST_P,HDCP DP software reset register"
bitfld.long 0x08 1. "CIPHER_CTRL_SW_RST,Software reset of cipher control logic only" "0,1"
bitfld.long 0x08 0. "SW_RST,Software reset" "0,1"
line.long 0x0C "EDP_CORE_HDCP_DP_FIFO_STATUS_P,HDCP DP FIFO status register"
bitfld.long 0x0C 11. "HDCP_DP_SST_1_4_FIFO1_UNDERFLOW,SST HDCP1.4 fifo1 underflow" "0,1"
bitfld.long 0x0C 10. "HDCP_DP_SST_1_4_FIFO1_OVERFLOW,SST HDCP1.4 fifo1 overflow" "0,1"
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bitfld.long 0x0C 9. "HDCP_DP_SST_1_4_FIFO0_UNDERFLOW,SST HDCP1.4 fifo0 underflow" "0,1"
bitfld.long 0x0C 8. "HDCP_DP_SST_1_4_FIFO0_OVERFLOW,SST HDCP1.4 fifo0 overflow" "0,1"
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bitfld.long 0x0C 7. "HDCP_DP_SST_2_2_FIFO3_UNDERFLOW,SST HDCP2.2 fifo3 underflow" "0,1"
bitfld.long 0x0C 6. "HDCP_DP_SST_2_2_FIFO3_OVERFLOW,SST HDCP2.2 fifo3 overflow" "0,1"
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bitfld.long 0x0C 5. "HDCP_DP_SST_2_2_FIFO2_UNDERFLOW,SST HDCP2.2 fifo2 underflow" "0,1"
bitfld.long 0x0C 4. "HDCP_DP_SST_2_2_FIFO2_OVERFLOW,SST HDCP2.2 fifo2 overflow" "0,1"
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bitfld.long 0x0C 3. "HDCP_DP_SST_2_2_FIFO1_UNDERFLOW,SST HDCP2.2 fifo1 underflow" "0,1"
bitfld.long 0x0C 2. "HDCP_DP_SST_2_2_FIFO1_OVERFLOW,SST HDCP2.2 fifo1 overflow" "0,1"
newline
bitfld.long 0x0C 1. "HDCP_DP_SST_2_2_FIFO0_UNDERFLOW,SST HDCP2.2 fifo0 underflow" "0,1"
bitfld.long 0x0C 0. "HDCP_DP_SST_2_2_FIFO0_OVERFLOW,SST HDCP2.2 fifo0 overflow" "0,1"
group.long 0x2800++0x67
line.long 0x00 "EDP_CORE_DP_AUX_HOST_CONTROL_P,DP AUX control register"
bitfld.long 0x00 2. "AUX_HOST_TRANSMIT_IMMEDIATE,This bit is used only in DP_OUT mode" "0,1"
bitfld.long 0x00 1. "AUX_HOST_PRECHARGE_ENABLE,According to the current standard the tx precharge is done by sending 10 to 16 data_0 on the line before the SYNC" "0,1"
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bitfld.long 0x00 0. "AUX_HOST_ALWAYS_READ,Normally the aux_rx is disabled during transmit" "0,1"
line.long 0x04 "EDP_CORE_DP_AUX_INTERRUPT_SOURCE_P,Status of the DP_AUX interrupt sources"
bitfld.long 0x04 9. "AUX_MAIN_EXPIRE_TX,Timer expire [external] in DP_OUT" "0,1"
bitfld.long 0x04 8. "AUX_RX_ERROR_CYCLE_TIME,Cycle time error" "0,1"
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bitfld.long 0x04 7. "AUX_MAIN_RX_STATUS_CORRUPTED,The received transaction corrupted during the data phase [bad STOP or unaligned STOP]" "0,1"
bitfld.long 0x04 6. "AUX_MAIN_RX_STATUS_LONG_DATA,The received transaction had more than 20 data bytes" "0,1"
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bitfld.long 0x04 5. "AUX_MAIN_RX_STATUS_LONG_PREAMBLE,The received transaction had preamble greater than the preamble_max" "0,1"
bitfld.long 0x04 4. "AUX_MAIN_RX_STATUS_SHORT_PREAMBLE,The received transaction had preamble shorter than the preamble_max" "0,1"
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bitfld.long 0x04 3. "AUX_MAIN_RX_STATUS_DONE,This module control the packet extraction and packet read from the memory" "0,1"
bitfld.long 0x04 2. "AUX_RX_DATA_TRANSFER_INIT,Rx data transfer may be initiated" "0,1"
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bitfld.long 0x04 1. "AUX_TX_DONE,Tx data transfer finished" "0,1"
bitfld.long 0x04 0. "PSLVERR_DPAUX,APB slave error interrupt from DP AUX module" "0,1"
line.long 0x08 "EDP_CORE_DP_AUX_INTERRUPT_MASK_P,Mask vector of the DP_AUX interrupt sources"
bitfld.long 0x08 9. "AUX_MAIN_EXPIRE_TX_MASK,aux_main_expire_external mask" "0,1"
bitfld.long 0x08 8. "AUX_RX_ERROR_CYCLE_TIME_MASK,aux_rx_error_cycle_time mask" "0,1"
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bitfld.long 0x08 7. "AUX_MAIN_RX_STATUS_CORRUPTED_MASK,aux_main_rx_status_corrupted_mask" "0,1"
bitfld.long 0x08 6. "AUX_MAIN_RX_STATUS_LONG_DATA_MASK,aux_main_rx_status_long_data_mask" "0,1"
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bitfld.long 0x08 5. "AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK,aux_main_rx_status_long_preamble_mask" "0,1"
bitfld.long 0x08 4. "AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK,aux_main_rx_status_short_preamble_mask" "0,1"
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bitfld.long 0x08 3. "AUX_MAIN_RX_STATUS_DONE_MASK,aux_main_rx_status_done_mask" "0,1"
bitfld.long 0x08 2. "AUX_RX_DATA_TRANSFER_INIT_MASK,rx_data_transfer_init mask" "0,1"
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bitfld.long 0x08 1. "AUX_TX_DONE_MASK,aux_tx_done_mask" "0,1"
bitfld.long 0x08 0. "PSLVERR_MASK,Mask for pslverr_dpaux interrupt" "0,1"
line.long 0x0C "EDP_CORE_DP_AUX_SWAP_INVERSION_CONTROL_P,Ordering and inversion of transmit/receive on Auxiliary Channel"
bitfld.long 0x0C 3. "AUX_HOST_RX_SWAP,Shift right [LSB first] of the income data" "0,1"
bitfld.long 0x0C 2. "AUX_HOST_TX_SWAP,Shift right the output data [LSB first]" "0,1"
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bitfld.long 0x0C 1. "AUX_HOST_RX_INVERT,Invert rx input and output data to AUXILIARY CHANNEL" "0,1"
bitfld.long 0x0C 0. "AUX_HOST_TX_INVERT,Invert tx input and output data to AUXILIARY CHANNEL" "0,1"
line.long 0x10 "EDP_CORE_DP_AUX_SEND_NACK_TRANSACTION_P,NACK transaction send"
bitfld.long 0x10 0. "AUX_HOST_SEND_NACK_TRANSACTION,Send nack transaction by AUX_TX" "0,1"
line.long 0x14 "EDP_CORE_DP_AUX_CLEAR_RX_P,RX bits clear"
bitfld.long 0x14 0. "AUX_HOST_CLEAR_RX,Clear all rx bits in register 64 65.This command is an indication that the processing of last receive transaction was completed and the AUX_RX can start looking for new receive transaction" "0,1"
line.long 0x18 "EDP_CORE_DP_AUX_CLEAR_TX_P,TX bits clear"
bitfld.long 0x18 0. "AUX_HOST_CLEAR_TX,Clear all external bits in registers 64 67.This command used in DP_IN mode" "0,1"
line.long 0x1C "EDP_CORE_DP_AUX_TIMER_STOP_P,Stop timer operation"
bitfld.long 0x1C 0. "AUX_HOST_STOP_TIMER,Stop timer operation" "0,1"
line.long 0x20 "EDP_CORE_DP_AUX_TIMER_CLEAR_P,Clear timer operation"
bitfld.long 0x20 0. "AUX_HOST_CLEAR_TIMER,Stop timer operation" "0,1"
line.long 0x24 "EDP_CORE_DP_AUX_RESET_SW_P,Soft reset of the DP_AUX"
bitfld.long 0x24 0. "AUX_HOST_SW_RESET,Reset all DP_AUX state machines and clear all the status bits" "0,1"
line.long 0x28 "EDP_CORE_DP_AUX_DIVIDE_2M_P,SYS_CLK and 2 MHz clock ratio"
hexmask.long.byte 0x28 0.--7. 1. "AUX_HOST_DIVIDE_2M,The ratio between sys_clk and 2MHz [[sys_clk frequency/2MHz] - 1] for 25MHz sys_clk the value is 11"
line.long 0x2C "EDP_CORE_DP_AUX_TX_PREACHARGE_LENGTH_P,Pre charge field length"
bitfld.long 0x2C 0.--5. "AUX_HOST_PRECHARGE_LENGTH,Length of pre charge field standard definition is 10 to 16 bits/clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "EDP_CORE_DP_AUX_FREQUENCY_1M_MAX_P,Maximum legal receiving frequency"
hexmask.long.word 0x30 0.--10. 1. "AUX_HOST_1M_MAX,The maximum legal frequency receiving from the line by the standard is 1.25MHz.The calculation is:[1.25 MHz cycle time]/[sys_clk[-15%] cycle time] 800/"
line.long 0x34 "EDP_CORE_DP_AUX_FREQUENCY_1M_MIN_P,Minimum legal receiving frequency"
hexmask.long.word 0x34 0.--10. 1. "AUX_HOST_1M_MIN,The minimum legal frequency receiving from the line by the standard is 0.83MHz.The calculation is:[0.83 MHz cycle time]/[sys_clk[+15%] cycle time] 1200/"
line.long 0x38 "EDP_CORE_DP_AUX_RX_PRE_MIN_P,Minimum received preamble length"
bitfld.long 0x38 0.--5. "AUX_HOST_PRE_MIN,Valid minimum length of preamble during receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "EDP_CORE_DP_AUX_RX_PRE_MAX_P,Maximum received preamble length"
bitfld.long 0x3C 0.--5. "AUX_HOST_PRE_MAX,Valid maximum length of preamble during receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x40 "EDP_CORE_DP_AUX_TIMER_PRESET_P,DP_AUX_MAIN start value"
hexmask.long.word 0x40 0.--15. 1. "AUX_HOST_TIMER_PRESET,The preset value of the timer in DP_IN mode"
line.long 0x44 "EDP_CORE_DP_AUX_NACK_FORMAT_P,Transmit pattern"
hexmask.long.byte 0x44 0.--7. 1. "AUX_HOST_NACK_FORMAT,Nack or defer pattern for transmit [ 00100000 for defer 00010000 for nack]"
line.long 0x48 "EDP_CORE_DP_AUX_TX_DATA_P,AUX Mailbox write data"
hexmask.long.word 0x48 0.--9. 1. "MAILBOX_TX_DATA,TX data byte written to the mailbox"
line.long 0x4C "EDP_CORE_DP_AUX_RX_DATA_P,AUX Mailbox read data"
hexmask.long.word 0x4C 0.--9. 1. "MAILBOX_RX_DATA,Read data from the mailbox"
line.long 0x50 "EDP_CORE_DP_AUX_TX_STATUS_P,AUX_TX status"
bitfld.long 0x50 9. "MAILBOX_TX_FULL,AUX Mailbox TX full flag" "0,1"
bitfld.long 0x50 8. "MAILBOX_TX_EMPTY,AUX Mailbox TX empty flag" "0,1"
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bitfld.long 0x50 7. "AUX_TX_FRAME_ONGOING,Frame transmission status" "0,1"
hexmask.long.byte 0x50 0.--6. 1. "AUX_TX_STATE,Aux_tx state machine register"
line.long 0x54 "EDP_CORE_DP_AUX_RX_STATUS_P,AUX_RX status"
hexmask.long.byte 0x54 24.--31. 1. "AUX_RX_DATA_STATE,AUX_RX SM state"
bitfld.long 0x54 23. "AUX_MAIN_RX_STATUS_LAST_EQUAL,The receive transaction is equal to the previous transaction" "0,1"
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bitfld.long 0x54 16.--19. "AUX_RX_HHLL_STATE,AUX_RX hhll state machine register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x54 8.--13. "AUX_RX_PREAMBLE_STATE,AUX_RX preamble state machine register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x54 7. "MAILBOX_RX_FULL,AUX Mailbox RX full flag" "0,1"
bitfld.long 0x54 6. "MAILBOX_RX_EMPTY,AUX Mailbox RX empty flag" "0,1"
newline
bitfld.long 0x54 5. "AUX_RX_FRAME_ONGOING,Frame reception status" "0,1"
bitfld.long 0x54 0.--4. "AUX_RX_MAIN_STATE,AUX_RX main state machine register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x58 "EDP_CORE_DP_AUX_RX_CYCLE_COUNTER_P,AUX RX counter status"
hexmask.long.word 0x58 0.--10. 1. "AUX_RX_CYCLE_COUNTER,Count system clocks from last change in the auxiliary line input"
line.long 0x5C "EDP_CORE_DP_AUX_MAIN_STATES_P,DP_AUX MAIN State Machines status"
bitfld.long 0x5C 10.--13. "AUX_MAIN_EXTERNAL_STATE,AUX_MAIN external state machine register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x5C 8.--9. "AUX_MAIN_TIMER_STATE,AUX_MAIN timer state machine" "0,1,2,3"
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bitfld.long 0x5C 5.--6. "AUX_MAIN_DP_STATE,AUX_MAIN dp state machine" "0,1,2,3"
bitfld.long 0x5C 2.--4. "AUX_MAIN_RX_STATE,AUX_MAIN rx state machine" "0,1,2,3,4,5,6,7"
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bitfld.long 0x5C 0.--1. "AUX_MAIN_TX_STATE,AUX_MAIN tx state machine" "0,1,2,3"
line.long 0x60 "EDP_CORE_DP_AUX_MAIN_TIMER_P,DP_AUX MAIN timer status"
hexmask.long.word 0x60 0.--15. 1. "AUX_MAIN_TIMER,DP_AUX MAIN timer status"
line.long 0x64 "EDP_CORE_DP_AUX_AFE_OUT_P,Test mode configuration"
bitfld.long 0x64 3. "AUX_HOST_AUX_AFE_PRECH,Drive the aux_data_prech output to the AFE when aux_host_afe_if_test_en [bit 0 ] is set" "0,1"
bitfld.long 0x64 2. "AUX_HOST_AUX_AFE_DATA,Drive the aux_data_out output to the AFE when aux_host_afe_if_test_en [bit 0 ] is set" "0,1"
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bitfld.long 0x64 1. "AUX_HOST_AUX_AFE_CLK,Drive the aux_clk_out output to the AFE when aux_host_afe_if_test_en [bit 0 ] is set" "0,1"
bitfld.long 0x64 0. "AUX_HOST_AFE_IF_TEST_EN,TESTER mode enable" "0,1"
group.long 0x3000++0x3F
line.long 0x00 "EDP_CORE_MSA_HORIZONTAL_0_P_j,MSA horizontal parameters"
hexmask.long.word 0x00 16.--31. 1. "PCK_STUFF_HSTART,MSA Hstart value"
hexmask.long.word 0x00 0.--15. 1. "PCK_STUFF_HTOTAL,MSA HTotal value"
line.long 0x04 "EDP_CORE_MSA_HORIZONTAL_1_P_j,MSA horizontal parameters"
hexmask.long.word 0x04 16.--31. 1. "PCK_STUFF_HWIDTH,MSA Hwidth parameter"
bitfld.long 0x04 15. "PCK_STUFF_HSYNCPOLARITY,MSA HSync Polarity" "0,1"
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hexmask.long.word 0x04 0.--14. 1. "PCK_STUFF_HSYNCWIDTH,MSA HSyncWidth parameter"
line.long 0x08 "EDP_CORE_MSA_VERTICAL_0_P_j,MSA vertical parameters"
hexmask.long.word 0x08 16.--31. 1. "PCK_STUFF_VSTART,MSA Vstart parameter"
hexmask.long.word 0x08 0.--15. 1. "PCK_STUFF_VTOTAL,MSA Vtotal parameter"
line.long 0x0C "EDP_CORE_MSA_VERTICAL_1_P_j,MSA vertical parameters"
hexmask.long.word 0x0C 16.--31. 1. "PCK_STUFF_VHEIGHT,MSA VHeigh parameter"
bitfld.long 0x0C 15. "PCK_STUFF_VSYNCPOLARITY,MSA VSyncPolarity" "0,1"
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hexmask.long.word 0x0C 0.--14. 1. "PCK_STUFF_VSYNCWIDTH,MSA VSyncWidth parameter"
line.long 0x10 "EDP_CORE_MSA_MISC_P_J,MSA MISC0 and MISC1 control register"
bitfld.long 0x10 17. "MSA_IN_MID_INTERLACE_EN,MSA transmission control in interlaced mode" "0,1"
bitfld.long 0x10 16. "MSA_MISC1_INV,L/R toggle for interlaced and field sequential video" "0,1"
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hexmask.long.byte 0x10 8.--15. 1. "MSA_MISC1,MAS Miscellaneous1 as described in DisplayPort specification"
hexmask.long.byte 0x10 0.--7. 1. "MSA_MISC0,MSA Miscellaneous0 as described in DisplayPort specification"
line.long 0x14 "EDP_CORE_STREAM_CONFIG_P_j,Stream configuration register"
bitfld.long 0x14 1. "NO_VIDEO,Stream no video mode" "0,1"
bitfld.long 0x14 0. "STREAM_EN,Stream enable" "0,1"
line.long 0x18 "EDP_CORE_AUDIO_PACK_STATUS_P_j,Status signals for the audio pack"
bitfld.long 0x18 16.--21. "AUDIO_TS_VERSION,Audio timestamp version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x18 10.--12. "AP_PARITY_FSM_CURRENT_STATE,Audio pack parity calc fsm state" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x18 8.--9. "AP_FIFO_WR_FSM_CURR_ST,Audio pack FIFO write fsm state" "0,1,2,3"
rbitfld.long 0x18 6.--7. "AP_FIFO_RD_FSM_CURR_ST,Audio pack FIFO read fsm state" "0,1,2,3"
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rbitfld.long 0x18 3.--5. "AP_SDP_TRANSFER_FSM_CURR_ST,Audio pack sdp transfer fsm state" "0,1,2,3,4,5,6,7"
rbitfld.long 0x18 2. "AP_AIF_FSM_CURR_ST,Audio pack aif fsm state" "0,1"
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rbitfld.long 0x18 1. "AP_FIFO_FULL,Audio Pack Sync FIFO full flag active high" "0,1"
rbitfld.long 0x18 0. "AP_FIFO_EMPTY,Audio Pack Sync FIFO empty flag active high" "0,1"
line.long 0x1C "EDP_CORE_VIF_STATUS_P_j,Status signals for the VIF module"
hexmask.long.tbyte 0x1C 8.--27. 1. "VIF_RD_CTRL_STATE,VIF rd fsm current state"
bitfld.long 0x1C 2.--7. "VIF_WR_CTRL_STATE,VIF wr fsm current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x1C 1. "VIF_FIFO_FULL,VIF ASync FIFO full flag active high" "0,1"
bitfld.long 0x1C 0. "VIF_FIFO_EMPTY,VIF ASync FIFO empty flag active high" "0,1"
line.long 0x20 "EDP_CORE_PCK_STUFF_STATUS_0_P_j,Status of the the video stuff module (0)"
hexmask.long.byte 0x20 24.--30. 1. "MSA_GEN_STATE,Secondary Data generator FSM status"
hexmask.long.byte 0x20 8.--14. 1. "SST_VIDEO_GEN_STATE,SST video generator FSM status"
newline
bitfld.long 0x20 0.--4. "NO_VIDEO_GEN_STATE,No video generator FSM status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "EDP_CORE_PCK_STUFF_STATUS_1_P_j,Status of the the video stuff module (1)"
bitfld.long 0x24 0.--5. "SST_SS_GEN_STATE,MSA generator FSM status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "EDP_CORE_INFO_PACK_STATUS_P_j,Status signals for the info pack module. as well as final VB-ID value"
hexmask.long.byte 0x28 24.--31. 1. "IN_VBID,Value of the sent VB-ID [vb_id_final]"
bitfld.long 0x28 12.--15. "IP_SEND_DATA_FSM_CURRENT_STATE,State of the send_data FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 8.--11. "IP_FIFO_RD_FSM_CURRENT_STATE,State of the fifo_rd FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 5.--7. "IP_FIFO_WR_FSM_CURRENT_STATE,State of the fifo_wr FSM" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 2.--4. "IP_PARITY_FSM_CURRENT_STATE,State of the parity FSM" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 1. "INFO_PACK_FIFO_EMPTY,Info_pack fifo empty flag active high" "0,1"
newline
bitfld.long 0x28 0. "INFO_PACK_FIFO_FULL,Info_pack fifo full flag active high" "0,1"
line.long 0x2C "EDP_CORE_STREAM_CONFIG_2_P_j,Additional video stream configuration"
bitfld.long 0x2C 24. "CFG_EN_HSYNC_DELAY,Unused" "0,1"
hexmask.long.byte 0x2C 16.--23. 1. "CFG_HSYNC_DELAY,Unused"
newline
bitfld.long 0x2C 10.--15. "MST_SF_EVAL_VAL_SYM,Number of valid symbols to output during stream fill evaluation period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x2C 8.--9. "CFG_TU_VS_DIFF,Unused" "0,1,2,3"
newline
bitfld.long 0x2C 7. "MST_SF_EVAL_OVR_EN,Enable override of mst_sf_eval_period mst_sf_eval_val_sym and cfg_tu_vs_diff when in MST mode" "0,1"
hexmask.long.byte 0x2C 0.--6. 1. "MST_SF_EVAL_PERIOD,Stream fill evaluation period when in MST mode and mst_sf_eval_ovr_en bit is set"
line.long 0x30 "EDP_CORE_DP_HORIZONTAL_P_j,Video Horizontal parameters"
hexmask.long.word 0x30 16.--31. 1. "HWIDTH,Horizontal Active Video Width"
hexmask.long.word 0x30 0.--14. 1. "HSYNCWIDTH,Horizontal Sync Width"
line.long 0x34 "EDP_CORE_DP_VERTICAL_0_P_j,Video Vertical parameters"
hexmask.long.word 0x34 16.--31. 1. "VSTART,Vertical Active Start [VSTART]"
hexmask.long.word 0x34 0.--15. 1. "VHEIGHT,Vertical Active High [VACTIVE]"
line.long 0x38 "EDP_CORE_DP_VERTICAL_1_P_j,Video Vertical parameters"
bitfld.long 0x38 16. "VTOTAL_EVEN,Indicate Vtotal is an even number as described in MISC1[0] in DisplayPort specification" "0,1"
hexmask.long.word 0x38 0.--15. 1. "VTOTAL,Vertical Total Heigh [HTOTAL]"
line.long 0x3C "EDP_CORE_DP_BLOCK_SDP_P_j,SDP scheduling control register"
bitfld.long 0x3C 31. "BS_SDP_STOP_OVR_EN,Enable override settings" "0,1"
hexmask.long.word 0x3C 16.--30. 1. "BS_SDP_STOP_ACTIVE,Block SDP scheduling after specified cycles after BS during horizontal blank lines"
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hexmask.long.word 0x3C 0.--15. 1. "BS_SDP_STOP_BLANK,Block SDP scheduling after specified cycles after BS during vertical blank lines"
group.long 0x3044++0x13
line.long 0x00 "EDP_CORE_DP_MST_SLOT_ALLOCATE_P_J,Stream slots allocation in MST mode"
bitfld.long 0x00 8.--13. "STREAM_END_SLOT,Stream end slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "STREAM_START_SLOT,Stream start slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "EDP_CORE_RATE_GOVERNING_CTRL_P_j,Control rate governing for stream in MST mode"
bitfld.long 0x04 10. "RATE_GOV_EN,Enable rate governing" "0,1"
bitfld.long 0x04 4.--9. "TARG_AV_SLOTS_X,Target average number of slots per MTP configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 0.--3. "TARG_AV_SLOTS_Y,Target average number of slots per MTP configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "EDP_CORE_DP_FRAMER_PXL_REPR_P_j,Video pixel format configuration"
hexmask.long.byte 0x08 24.--30. 1. "DIFF,Difference between Denominator and Numerator of the ratio that describes valid symbols distribution"
hexmask.long.byte 0x08 16.--22. 1. "M,Numerator of the ratio that describes valid symbols distribution"
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bitfld.long 0x08 8.--12. "PXL_ENC_FORMAT,Pixel encoding format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "COLOR_DEPTH,Color depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "EDP_CORE_DP_FRAMER_SP_P_j,Synchronization signals polarity and 3D control"
bitfld.long 0x0C 4. "STACKED_3D_EN,Unused" "0,1"
bitfld.long 0x0C 3. "FRAMER_3D_EN,3D video enable active high" "0,1"
newline
bitfld.long 0x0C 2. "INTERLACE_EN,Interlaced video enable" "0,1"
bitfld.long 0x0C 1. "HSP,Video interface HSYNC polarity" "0,1"
newline
bitfld.long 0x0C 0. "VSP,Video interface VSYNC polarity" "0,1"
line.long 0x10 "EDP_CORE_AUDIO_PACK_CONTROL_P_j,Audio packet configuration"
bitfld.long 0x10 9. "MONO,In case of" "0,1"
bitfld.long 0x10 8. "AUDIO_PACK_EN,Enables the Audio_Pack module active high" "0,1"
newline
hexmask.long.byte 0x10 0.--7. 1. "MST_SDP_ID,Secondary-Data Packet ID"
group.long 0x3064++0x0B
line.long 0x00 "EDP_CORE_LINE_THRESH_P_j,Video FIFO latency threshold Offset = 3064h + (j * 80h); where j = 0h to 3h"
bitfld.long 0x00 0.--5. "CFG_ACTIVE_LINE_TRESH,Video Fifo Latency threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "EDP_CORE_DP_VB_ID_P_J,Vertical blanking ID Offset = 3068h + (j * 80h); where j = 0h to 3h"
hexmask.long.byte 0x04 0.--7. 1. "VB_ID,VB-ID as described in the DisplayPort specification"
line.long 0x08 "EDP_CORE_DP_FIELDSEQ_3D_P_j,Supporting configuration to switch from top/bottom on the input to field sequential on the output Offset = 306Ch + (j * 80h); where j = 0h to 3h"
hexmask.long.word 0x08 16.--31. 1. "FIELD_SEQ_END,Number of line in the frame where the Vblank part in the field sequential format ends"
hexmask.long.word 0x08 0.--15. 1. "FIELD_SEQ_START,Number of line in the frame where the Vblank part in the field sequential format starts"
group.long 0x3078++0x07
line.long 0x00 "EDP_CORE_DP_FRONT_BACK_PORCH_P_j,Front and Back Porch configuration register.In case of compressed stream transmission (DSC) and split panel mode values in this register must be divided by 2 since VIF interface operates at pixel clock divided by 2"
hexmask.long.word 0x00 16.--31. 1. "FRONT_PORCH,Value of the front porch"
hexmask.long.word 0x00 0.--15. 1. "BACK_PORCH,Value of the back porch"
line.long 0x04 "EDP_CORE_DP_BYTE_COUNT_P_j,Number of bytes per lane/chunk parameters Offset = 307Ch + (j * 80h); where j = 0h to 3h"
hexmask.long.word 0x04 16.--31. 1. "BYTES_IN_CHUNK,Number of bytes in chunk per lane including additional EOC symbol"
hexmask.long.word 0x04 0.--15. 1. "BYTE_COUNT,Total number of bytes in a line in case of non-DSC video"
rgroup.long 0x4000++0x0F
line.long 0x00 "EDP_CORE_CRYPTO_HDCP_REVISION_P,Contains the revision of the internal HDCP 1.4 and 2.2 module"
hexmask.long.word 0x00 20.--29. 1. "HDCP_CRYP_REV,Revision of the HDCP Crypto block"
hexmask.long.word 0x00 10.--19. 1. "CRYPTO_HDCP_22_REV,Revision of the HDCP Crypto 2.2 block"
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hexmask.long.word 0x00 0.--9. 1. "CRYPTO_HDCP_14_REV,Revision of the HDCP Crypto 1.4 block"
line.long 0x04 "EDP_CORE_HDCP_CRYPTO_CONFIG_P,Contains global configuration information for the HDCP Crypto module"
bitfld.long 0x04 3. "CRYPTO_SW_RST,Software reset for the Crypto module" "0,1"
bitfld.long 0x04 0.--2. "CRYPTO_HDCP_FUNCTION,Enables a version of the Crypto function" "0,1,2,3,4,5,6,7"
line.long 0x08 "EDP_CORE_CRYPTO_INTERRUPT_SOURCE_P,Contains the status of the HDCP interrupt sources"
bitfld.long 0x08 10. "CRYPTO14_PRNM_DONE,LFSR and block output finished calculation" "0,1"
bitfld.long 0x08 9. "CRYPTO14_KM_DONE,Done reading/calculating Km" "0,1"
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bitfld.long 0x08 8. "AES_32_DONE,Asserted when the rising edge of the AES-32 done output is detected" "0,1"
bitfld.long 0x08 1. "APB_SLVERR,APB slave error" "0,1"
newline
bitfld.long 0x08 0. "SHA256_NEXT_MESSAGE,Asserted when the rising edge of the SHA256 done output is detected" "0,1"
line.long 0x0C "EDP_CORE_CRYPTO_INTERRUPT_MASK_P,Contains the mask vector of the HDCP interrupt sources"
bitfld.long 0x0C 10. "CRYPTO14_PRNM_DONE_MASK,Set to 1 to mask the crypto14_prnm_done interrupt" "0,1"
bitfld.long 0x0C 9. "CRYPTO14_KM_DONE_MASK,Set to 1 to mask the crypto14_km_done interrupt" "0,1"
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bitfld.long 0x0C 8. "AES_32_DONE_MASK,Set to 1 to mask the AES32_done interrupt" "0,1"
bitfld.long 0x0C 1. "APB_SLVERR_MASK,Set to 1 for the apb_slverr interrupt" "0,1"
newline
bitfld.long 0x0C 0. "SHA256_NEXT_MESSAGE_MASK,Set to 1 to mask the SHA256_done interrupt" "0,1"
group.long 0x4018++0x07
line.long 0x00 "EDP_CORE_CRYPTO22_CONFIG_P,Contains global configuration information for the HDCP 2.2 Crypto module"
bitfld.long 0x00 0. "SHA_256_START,Set to 1 for Sha-256 start" "0,1"
line.long 0x04 "EDP_CORE_CRYPTO22_STATUS_P,Crypto 2.2 global status register"
bitfld.long 0x04 9. "AES_32_DONE_ST,Asserted when the rising edge of the AES-32 done output is detected" "0,1"
bitfld.long 0x04 8. "SHA256_NEXT_MESSAGE_ST,Asserted when the SHA-256 module is ready to receive the next message" "0,1"
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bitfld.long 0x04 4.--7. "AES_32_STATE,AES-32 current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "SHA_256_STATE,SHA-256 current state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x403C++0x03
line.long 0x00 "EDP_CORE_SHA_256_DATA_IN_P,Holds 32-bit input data word of the SHA-256 module"
rgroup.long 0x4050++0x43
line.long 0x00 "EDP_CORE_SHA_256_DATA_OUT_0_P,Result of operation SHA-256 - 1' dw"
line.long 0x04 "EDP_CORE_SHA_256_DATA_OUT_1_P,Result of operation SHA-256 - 2' dw"
line.long 0x08 "EDP_CORE_SHA_256_DATA_OUT_2_P,Result of operation SHA-256 - 3' dw"
line.long 0x0C "EDP_CORE_SHA_256_DATA_OUT_3_P,Result of operation SHA-256 - 4' dw"
line.long 0x10 "EDP_CORE_SHA_256_DATA_OUT_4_P,Result of operation SHA-256 - 5' dw"
line.long 0x14 "EDP_CORE_SHA_256_DATA_OUT_5_P,Result of operation SHA-256 - 6' dw"
line.long 0x18 "EDP_CORE_SHA_256_DATA_OUT_6_P,Result of operation SHA-256 - 7' dw"
line.long 0x1C "EDP_CORE_SHA_256_DATA_OUT_7_P,Result of operation SHA-256 - 8' dw"
line.long 0x20 "EDP_CORE_AES_32_KEY_0_P,Input key word of the AES-32 module - 1' dw"
line.long 0x24 "EDP_CORE_AES_32_KEY_1_P,Input key word of the AES-32 module - 2' dw"
line.long 0x28 "EDP_CORE_AES_32_KEY_2_P,Input key word of the AES-32 module - 3' dw"
line.long 0x2C "EDP_CORE_AES_32_KEY_3_P,Input key word of the AES-32 module - 4' dw"
line.long 0x30 "EDP_CORE_AES_32_DATA_IN_P,Input data word to the AES-32 module"
line.long 0x34 "EDP_CORE_AES_32_DATA_OUT_0_P,AES-32 module - 128-bits output data word - 1' dw"
line.long 0x38 "EDP_CORE_AES_32_DATA_OUT_1_P,AES-32 module - 128-bits output data word - 2' dw"
line.long 0x3C "EDP_CORE_AES_32_DATA_OUT_2_P,AES-32 module - 128-bits output data word - 3' dw"
line.long 0x40 "EDP_CORE_AES_32_DATA_OUT_3_P,AES-32 module - 128-bits output data word - 4' dw"
group.long 0x40A0++0x5B
line.long 0x00 "EDP_CORE_CRYPTO14_CONFIG_P,Contains global configuration information for the HDCP 1.4 Crypto module"
bitfld.long 0x00 6. "HDCP_AUTHENTICATED,Authenticated finished" "0,1"
bitfld.long 0x00 5. "HDCP_REPEATER,Repeater bit" "0,1"
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bitfld.long 0x00 4. "START_REKEY,Crypto 1.4 command to start hdcpRekeyCipher" "0,1"
bitfld.long 0x00 3. "CRYPTO_START_FREE_RUN,Crypto 1.4 command to start free running enable for operation hdcpRngCipher" "0,1"
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bitfld.long 0x00 2. "START_BLOCK_SEQ,Crypto 1.4 command to start LFSR calculation" "0,1"
bitfld.long 0x00 1. "GET_KSV,Read it's own KSV enable bit.'0' reading not allowed'1' start reading" "0,1"
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bitfld.long 0x00 0. "VALID_KSV,Enable for Km calculation" "0,1"
line.long 0x04 "EDP_CORE_CRYPTO14_STATUS_P,Contains global status information for the HDCP 1.4 Crypto module"
bitfld.long 0x04 19.--20. "CRYPTO14_STATE,Crypto operation SM state: Possible values" "0,1,2,3"
bitfld.long 0x04 18. "SHA1_V_READY,Indication that V value from SHA-1 CRYPTO14_SHA1_V_VALUE_4 is ready" "0,1"
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bitfld.long 0x04 17. "SHA1_NEXT_MSG,Request for the next message block" "0,1"
bitfld.long 0x04 9.--11. "SHA1_STATE,Current state for Crypto 1.4 SHA-1 FSM" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 3.--5. "DKS_STATE,Crypto 1.4 DKS current state" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 2. "PRNM_DONE,LFSR and block output finished calculation" "0,1"
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bitfld.long 0x04 0. "KM_DONE,Done reading/calculating Km" "0,1"
line.long 0x08 "EDP_CORE_CRYPTO14_PRNM_OUT_P,Contains 24-bit pseudo random data"
hexmask.long.tbyte 0x08 0.--23. 1. "PRNM_OUT,"
line.long 0x0C "EDP_CORE_CRYPTO14_KM_0_P,Contains the first word of the Km value"
line.long 0x10 "EDP_CORE_CRYPTO14_KM_1_P,Contains the most significant 3 bytes of the Km value"
hexmask.long.tbyte 0x10 0.--23. 1. "CRYPTO14_KM_1,Holds the most significant 3 bytes of the Km value"
line.long 0x14 "EDP_CORE_CRYPTO14_AN_0_P,First word of An value generated by hdcpRngCipher operation"
line.long 0x18 "EDP_CORE_CRYPTO14_AN_1_P,Second word of An value generated by hdcpRngCipher operation"
line.long 0x1C "EDP_CORE_CRYPTO14_YOUR_KSV_0_P,First 32 bits of the KSV from the other HDCP device"
line.long 0x20 "EDP_CORE_CRYPTO14_YOUR_KSV_1_P,Last byte of the KSV from other HDCP device"
hexmask.long.byte 0x20 0.--7. 1. "CRYPTO14_YOUR_KSV_1,Holds the last byte of the KSV from other HDCP device"
line.long 0x24 "EDP_CORE_CRYPTO14_MI_0_P,Mi value - 1' dw"
line.long 0x28 "EDP_CORE_CRYPTO14_MI_1_P,Mi value - 2' dw"
line.long 0x2C "EDP_CORE_CRYPTO14_TI_0_P,Ti value"
hexmask.long.word 0x2C 0.--15. 1. "CRYPTO14_TI_0,Ti value"
line.long 0x30 "EDP_CORE_CRYPTO14_KI_0_P,First 32 bits of the Ki frame key from this HDCP device"
line.long 0x34 "EDP_CORE_CRYPTO14_KI_1_P,Last 3 bytes of the Ki frame key from this HDCP device"
hexmask.long.tbyte 0x34 0.--23. 1. "CRYPTO14_KI_1,Holds the last 3 bytes of the Ki frame key from this HDCP device"
line.long 0x38 "EDP_CORE_CRYPTO14_BLOCKS_NUM_P,This register defines number of iterations for SHA-1 calculations"
line.long 0x3C "EDP_CORE_CRYPTO14_KEY_MEM_DATA_0_P,Key memory control register"
line.long 0x40 "EDP_CORE_CRYPTO14_KEY_MEM_DATA_1_P,Key memory control register"
hexmask.long.tbyte 0x40 0.--23. 1. "KEY_MEM_DATA_1,Output data from keys RAM"
line.long 0x44 "EDP_CORE_CRYPTO14_SHA1_MSG_DATA_P,SHA1 message control register"
line.long 0x48 "EDP_CORE_CRYPTO14_SHA1_V_VALUE_0_P,SHA1 message status register"
line.long 0x4C "EDP_CORE_CRYPTO14_SHA1_V_VALUE_1_P,SHA1 message status register"
line.long 0x50 "EDP_CORE_CRYPTO14_SHA1_V_VALUE_2_P,SHA1 message status register"
line.long 0x54 "EDP_CORE_CRYPTO14_SHA1_V_VALUE_3_P,SHA1 message status register"
line.long 0x58 "EDP_CORE_CRYPTO14_SHA1_V_VALUE_4_P,SHA1 message status register"
group.long 0x10000++0x03
line.long 0x00 "EDP_CORE_IRAM_REG_P_y,Xtensa Instruction RAM address space"
group.long 0x20000++0x03
line.long 0x00 "EDP_CORE_DRAM_REG_P_y,Xtensa Data RAM address space"
group.long 0x30000++0x93
line.long 0x00 "EDP_CORE_AUDIO_SRC_CNTL_P,Audio source control"
bitfld.long 0x00 6. "VALID_ALL,valid bit for all samples" "0,1"
bitfld.long 0x00 5. "VALID_BITS_FORCE,Force valid bits of the channels" "0,1"
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bitfld.long 0x00 4. "I2S_TS_EN,Enable I2S Time Stamp when decoders are disabled" "0,1"
bitfld.long 0x00 3. "SPDIF_TS_EN,Enable SPDIF Time Stamp when decoders are disabled" "0,1"
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bitfld.long 0x00 2. "I2S_BLOCK_START_FORCE,Force a Block Start in the audio stream" "0,1"
bitfld.long 0x00 1. "I2S_DEC_START,When high Source Decoder starts" "0,1"
newline
bitfld.long 0x00 0. "SW_RST,Software reset" "0,1"
line.long 0x04 "EDP_CORE_AUDIO_SRC_CNFG_P,Audio source configuration"
bitfld.long 0x04 17.--20. "I2S_DEC_PORT_EN,Enables the I2S Decoder ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 13.--16. "AUDIO_CHANNEL_TYPE,Set the transmission type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 11.--12. "TRANS_SMPL_WIDTH,Decoder Word Select width" "0,1,2,3"
bitfld.long 0x04 9.--10. "AUDIO_SAMPLE_WIDTH,Decoder sample width" "0,1,2,3"
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bitfld.long 0x04 7.--8. "AUDIO_SAMPLE_JUST,Data justification setting" "0,1,2,3"
bitfld.long 0x04 2.--6. "AUDIO_CH_NUM,Number of channels to decode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 1. "WS_POLARITY,Word Select Polarity" "0,1"
bitfld.long 0x04 0. "LOW_INDEX_MSB,When low MSB is transmitted first" "0,1"
line.long 0x08 "EDP_CORE_COM_CH_STTS_BITS_P,Common channels configuration"
bitfld.long 0x08 24.--27. "ORIGINAL_SAMP_FREQ,Original Sampling Freq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 20.--23. "CLOCK_ACCURACY,Clock Accuracy of transmitted channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "SAMPLING_FREQ,Sampling Frequency of transmitted channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x08 8.--15. 1. "CATEGORY_CODE,Category Code of transmitted channel"
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hexmask.long.byte 0x08 0.--7. 1. "BYTE0,Byte 0 of transmitted channel"
line.long 0x0C "EDP_CORE_STTS_BIT_CH01_P,Channels 0.1 configuration"
bitfld.long 0x0C 24.--25. "VALID_BITS1_0,Valid Bits for channel 1 and 0 if force is enabled" "0,1,2,3"
bitfld.long 0x0C 20.--23. "WORD_LENGTH_CH1,Channel 1 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "CHANNEL_NUM_CH1,Channel 1 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 12.--15. "SOURCE_NUM_CH1,Channel 1 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. "WORD_LENGTH_CH0,Channel 0 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "CHANNEL_NUM_CH0,Channel 0 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "SOURCE_NUM_CH0,Channel 0 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "EDP_CORE_STTS_BIT_CH23_P,Channels 2.3 configuration"
bitfld.long 0x10 24.--25. "VALID_BITS3_2,Valid Bits for channel 3 and 2 if force is enabled" "0,1,2,3"
bitfld.long 0x10 20.--23. "WORD_LENGTH_CH3,Channel 3 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "CHANNEL_NUM_CH3,Channel 3 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 12.--15. "SOURCE_NUM_CH3,Channel 3 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 8.--11. "WORD_LENGTH_CH2,Channel 2 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 4.--7. "CHANNEL_NUM_CH2,Channel 2 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "SOURCE_NUM_CH2,Channel 2 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "EDP_CORE_STTS_BIT_CH45_P,Channels 4.5 configuration"
bitfld.long 0x14 24.--25. "VALID_BITS5_4,Valid Bits for channel 5 and 4 if force is enabled" "0,1,2,3"
bitfld.long 0x14 20.--23. "WORD_LENGTH_CH5,Channel 5 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 16.--19. "CHANNEL_NUM_CH5,Channel 5 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 12.--15. "SOURCE_NUM_CH5,Channel 5 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 8.--11. "WORD_LENGTH_CH4,Channel 4 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 4.--7. "CHANNEL_NUM_CH4,Channel 4 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0.--3. "SOURCE_NUM_CH4,Channel 4 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "EDP_CORE_STTS_BIT_CH67_P,Channels 6.7 configuration"
bitfld.long 0x18 24.--25. "VALID_BITS7_6,Valid Bits for channel 7 and 6 if force is enabled" "0,1,2,3"
bitfld.long 0x18 20.--23. "WORD_LENGTH_CH7,Channel 7 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 16.--19. "CHANNEL_NUM_CH7,Channel 7 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 12.--15. "SOURCE_NUM_CH7,Channel 7 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "WORD_LENGTH_CH6,Channel 6 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "CHANNEL_NUM_CH6,Channel 6 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "SOURCE_NUM_CH6,Channel 6 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "EDP_CORE_STTS_BIT_CH89_P,Channels 8.9 configuration"
bitfld.long 0x1C 24.--25. "VALID_BITS9_8,Valid Bits for channel 9 and 8 if force is enabled" "0,1,2,3"
bitfld.long 0x1C 20.--23. "WORD_LENGTH_CH9,Channel 9 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 16.--19. "CHANNEL_NUM_CH9,Channel 9 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 12.--15. "SOURCE_NUM_CH9,Channel 9 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "WORD_LENGTH_CH8,Channel 8 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 4.--7. "CHANNEL_NUM_CH8,Channel 8 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 0.--3. "SOURCE_NUM_CH8,Channel 8 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "EDP_CORE_STTS_BIT_CH1011_P,Channels 10.11 configuration"
bitfld.long 0x20 24.--25. "VALID_BITS11_10,Valid Bits for channel 11 and 10 if force is enabled" "0,1,2,3"
bitfld.long 0x20 20.--23. "WORD_LENGTH_CH11,Channel 11 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 16.--19. "CHANNEL_NUM_CH11,Channel 11 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 12.--15. "SOURCE_NUM_CH11,Channel 11 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 8.--11. "WORD_LENGTH_CH10,Channel 10 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 4.--7. "CHANNEL_NUM_CH10,Channel 10 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--3. "SOURCE_NUM_CH10,Channel 10 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "EDP_CORE_STTS_BIT_CH1213_P,Channels 12.13 configuration"
bitfld.long 0x24 24.--25. "VALID_BITS13_12,Valid Bits for channel 13 and 12 if force is enabled" "0,1,2,3"
bitfld.long 0x24 20.--23. "WORD_LENGTH_CH13,Channel 13 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 16.--19. "CHANNEL_NUM_CH13,Channel 13 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 12.--15. "SOURCE_NUM_CH13,Channel 13 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 8.--11. "WORD_LENGTH_CH12,Channel 12 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 4.--7. "CHANNEL_NUM_CH12,Channel 12 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0.--3. "SOURCE_NUM_CH12,Channel 12 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "EDP_CORE_STTS_BIT_CH1415_P,Channels 14.15 configuration"
bitfld.long 0x28 24.--25. "VALID_BITS15_14,Valid Bits for channel 15 and 14 if force is enabled" "0,1,2,3"
bitfld.long 0x28 20.--23. "WORD_LENGTH_CH15,Channel 15 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. "CHANNEL_NUM_CH15,Channel 15 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 12.--15. "SOURCE_NUM_CH15,Channel 15 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 8.--11. "WORD_LENGTH_CH14,Channel 14 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 4.--7. "CHANNEL_NUM_CH14,Channel 14 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "SOURCE_NUM_CH14,Channel 14 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "EDP_CORE_STTS_BIT_CH1617_P,Channels 16.17 configuration"
bitfld.long 0x2C 24.--25. "VALID_BITS17_16,Valid Bits for channel 17 and 16 if force is enabled" "0,1,2,3"
bitfld.long 0x2C 20.--23. "WORD_LENGTH_CH17,Channel 17 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--19. "CHANNEL_NUM_CH17,Channel 17 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 12.--15. "SOURCE_NUM_CH17,Channel 17 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 8.--11. "WORD_LENGTH_CH16,Channel 16 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 4.--7. "CHANNEL_NUM_CH16,Channel 16 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "SOURCE_NUM_CH16,Channel 16 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "EDP_CORE_STTS_BIT_CH1819_P,Channels 18.19 configuration"
bitfld.long 0x30 24.--25. "VALID_BITS19_18,Valid Bits for channel 19 and 18 if force is enabled" "0,1,2,3"
bitfld.long 0x30 20.--23. "WORD_LENGTH_CH19,Channel 19 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--19. "CHANNEL_NUM_CH19,Channel 19 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 12.--15. "SOURCE_NUM_CH19,Channel 19 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 8.--11. "WORD_LENGTH_CH18,Channel 18 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 4.--7. "CHANNEL_NUM_CH18,Channel 18 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "SOURCE_NUM_CH18,Channel 18 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "EDP_CORE_STTS_BIT_CH2021_P,Channels 20.21 configuration"
bitfld.long 0x34 24.--25. "VALID_BITS21_20,Valid Bits for channel 21 and 20 if force is enabled" "0,1,2,3"
bitfld.long 0x34 20.--23. "WORD_LENGTH_CH21,Channel 21 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 16.--19. "CHANNEL_NUM_CH21,Channel 21 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 12.--15. "SOURCE_NUM_CH21,Channel 21 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 8.--11. "WORD_LENGTH_CH20,Channel 20 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 4.--7. "CHANNEL_NUM_CH20,Channel 20 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x34 0.--3. "SOURCE_NUM_CH20,Channel 20 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "EDP_CORE_STTS_BIT_CH2223_P,Channels 22.23 configuration"
bitfld.long 0x38 24.--25. "VALID_BITS23_22,Valid Bits for channel 23 and 22 if force is enabled" "0,1,2,3"
bitfld.long 0x38 20.--23. "WORD_LENGTH_CH23,Channel 23 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "CHANNEL_NUM_CH23,Channel 23 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 12.--15. "SOURCE_NUM_CH23,Channel 23 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 8.--11. "WORD_LENGTH_CH22,Channel 22 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 4.--7. "CHANNEL_NUM_CH22,Channel 22 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 0.--3. "SOURCE_NUM_CH22,Channel 22 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "EDP_CORE_STTS_BIT_CH2425_P,Channels 24.25 configuration"
bitfld.long 0x3C 24.--25. "VALID_BITS25_24,Valid Bits for channel 25 and 24 if force is enabled" "0,1,2,3"
bitfld.long 0x3C 20.--23. "WORD_LENGTH_CH25,Channel 25 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 16.--19. "CHANNEL_NUM_CH25,Channel 25 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x3C 12.--15. "SOURCE_NUM_CH25,Channel 25 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 8.--11. "WORD_LENGTH_CH24,Channel 24 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x3C 4.--7. "CHANNEL_NUM_CH24,Channel 24 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0.--3. "SOURCE_NUM_CH24,Channel 24 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "EDP_CORE_STTS_BIT_CH2627_P,Channels 26.27 configuration"
bitfld.long 0x40 24.--25. "VALID_BITS27_26,Valid Bits for channel 27 and 26 if force is enabled" "0,1,2,3"
bitfld.long 0x40 20.--23. "WORD_LENGTH_CH27,Channel 27 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x40 16.--19. "CHANNEL_NUM_CH27,Channel 27 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x40 12.--15. "SOURCE_NUM_CH27,Channel 27 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x40 8.--11. "WORD_LENGTH_CH26,Channel 26 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x40 4.--7. "CHANNEL_NUM_CH26,Channel 26 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x40 0.--3. "SOURCE_NUM_CH26,Channel 26 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "EDP_CORE_STTS_BIT_CH2829_P,Channels 28.29 configuration"
bitfld.long 0x44 24.--25. "VALID_BITS29_28,Valid Bits for channel 29 and 28 if force is enabled" "0,1,2,3"
bitfld.long 0x44 20.--23. "WORD_LENGTH_CH29,Channel 29 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 16.--19. "CHANNEL_NUM_CH29,Channel 29 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 12.--15. "SOURCE_NUM_CH29,Channel 29 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 8.--11. "WORD_LENGTH_CH28,Channel 28 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 4.--7. "CHANNEL_NUM_CH28,Channel 28 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 0.--3. "SOURCE_NUM_CH28,Channel 28 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "EDP_CORE_STTS_BIT_CH3031_P,Channels 30.31 configuration"
bitfld.long 0x48 24.--25. "VALID_BITS31_30,Valid Bits for channel 31 and 30 if force is enabled" "0,1,2,3"
bitfld.long 0x48 20.--23. "WORD_LENGTH_CH31,Channel 31 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 16.--19. "CHANNEL_NUM_CH31,Channel 31 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x48 12.--15. "SOURCE_NUM_CH31,Channel 31 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 8.--11. "WORD_LENGTH_CH30,Channel 30 word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x48 4.--7. "CHANNEL_NUM_CH30,Channel 30 channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x48 0.--3. "SOURCE_NUM_CH30,Channel 30 Source number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "EDP_CORE_SPDIF_CTRL_ADDR_P,SPDIF control"
rbitfld.long 0x4C 22.--25. "SPDIF_JITTER_STATUS,SPDIF Jitter Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4C 21. "SPDIF_ENABLE,SPDIF Enable" "0,1"
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bitfld.long 0x4C 20. "SPDIF_AVG_SEL,SPDIF average Select" "0,1"
bitfld.long 0x4C 19. "SPDIF_JITTER_BYPASS,SPDIF Jitter Bypass" "0,1"
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hexmask.long.byte 0x4C 11.--18. 1. "SPDIF_FIFO_MID_RANGE,SPDIF fifo mid range"
hexmask.long.byte 0x4C 3.--10. 1. "SPDIF_JITTER_THRSH,SPDIF Jitter threshold"
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bitfld.long 0x4C 0.--2. "SPDIF_JITTER_AVG_WIN,Spdif Jitter AVG Window" "0,1,2,3,4,5,6,7"
line.long 0x50 "EDP_CORE_SPDIF_CH1_CS_3100_ADDR_P,SPDIF channel 1 status [31:00]"
line.long 0x54 "EDP_CORE_SPDIF_CH1_CS_6332_ADDR_P,SPDIF channel 1 status [63:32]"
line.long 0x58 "EDP_CORE_SPDIF_CH1_CS_9564_ADDR_P,SPDIF channel 1 status [95:64]"
line.long 0x5C "EDP_CORE_SPDIF_CH1_CS_12796_ADDR_P,SPDIF channel 1 status [127:96]"
line.long 0x60 "EDP_CORE_SPDIF_CH1_CS_159128_ADDR_P,SPDIF channel 1 status [159:128]"
line.long 0x64 "EDP_CORE_SPDIF_CH1_CS_191160_ADDR_P,SPDIF channel 1 status [191:160]"
line.long 0x68 "EDP_CORE_SPDIF_CH2_CS_3100_ADDR_P,SPDIF channel 2 status [31:00]"
line.long 0x6C "EDP_CORE_SPDIF_CH2_CS_6332_ADDR_P,SPDIF channel 2 status [63:32]"
line.long 0x70 "EDP_CORE_SPDIF_CH2_CS_9564_ADDR_P,SPDIF channel 2 status [95:64]"
line.long 0x74 "EDP_CORE_SPDIF_CH2_CS_12796_ADDR_P,SPDIF channel 2 status [127:96]"
line.long 0x78 "EDP_CORE_SPDIF_CH2_CS_159128_ADDR_P,SPDIF channel 2 status [159:128]"
line.long 0x7C "EDP_CORE_SPDIF_CH2_CS_191160_ADDR_P,SPDIF channel 2 status [191:160]"
line.long 0x80 "EDP_CORE_SMPL2PKT_CNTL_P,Sample 2 Packets Control Register"
bitfld.long 0x80 1. "SMPL2PKT_EN,When high Sample to Packets Block starts" "0,1"
bitfld.long 0x80 0. "SW_RST,Software reset" "0,1"
line.long 0x84 "EDP_CORE_SMPL2PKT_CNFG_P,Sample 2 Packets Config Register"
bitfld.long 0x84 20. "CFG_SAMPLE_PRESENT_FORCE,Force sample present bits" "0,1"
bitfld.long 0x84 16.--19. "CFG_SAMPLE_PRESENT,Sample present bits if force them is active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x84 15. "CFG_EN_AUTO_SUB_PCKT_NUM,Enable automatics sub packet number" "0,1"
bitfld.long 0x84 14. "CFG_BLOCK_LPCM_FIRST_PKT," "0,1"
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bitfld.long 0x84 11.--13. "CFG_SUB_PCKT_NUM,Number of sub-packets in HDMI audio" "0,1,2,3,4,5,6,7"
bitfld.long 0x84 7.--10. "AUDIO_TYPE,Audio Type setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x84 5.--6. "NUM_OF_I2S_PORTS,Number ofactive I2S ports" "0,1,2,3"
bitfld.long 0x84 0.--4. "MAX_NUM_CH,Number of channels to decode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x88 "EDP_CORE_FIFO_CNTL_P,FIFO control register"
bitfld.long 0x88 4. "CFG_DIS_PORT3," "0,1"
bitfld.long 0x88 3. "FIFO_EMPTY_CALC," "0,1"
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bitfld.long 0x88 2. "FIFO_DIR," "0,1"
bitfld.long 0x88 1. "SYNC_WR_TO_CH_ZERO,When high the last channel index synchronizes the write addresses [to the next channel group]" "0,1"
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bitfld.long 0x88 0. "FIFO_SW_RST,Resets Fifo's write and read pointers" "0,1"
line.long 0x8C "EDP_CORE_FIFO_STTS_P,FIFO Status register"
bitfld.long 0x8C 3. "UNDERRUN,Indicates a FIFO underrun error has occured - FIFO read when it was empty" "0,1"
bitfld.long 0x8C 2. "OVERRUN,Indicates a FIFO overrun error has occured - FIFO written to when it was full" "0,1"
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bitfld.long 0x8C 1. "REMPTY,Indicates FIFO Empty" "0,1"
bitfld.long 0x8C 0. "WFULL,Indicates FIFO Full" "0,1"
line.long 0x90 "EDP_CORE_SUB_PCKT_THRSH_P,SUB Packet Threshold register"
hexmask.long.byte 0x90 16.--23. 1. "CFG_MEM_FIFO_THRSH3,If number of samples in MEM FIFO is below Threshold"
hexmask.long.byte 0x90 8.--15. 1. "CFG_MEM_FIFO_THRSH2,If number of samples in MEM FIFO is below Threshold"
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hexmask.long.byte 0x90 0.--7. 1. "CFG_MEM_FIFO_THRSH1,If number of samples in MEM FIFO is below Threshold"
group.long 0x30800++0x3F
line.long 0x00 "EDP_CORE_SOURCE_PIF_WR_ADDR_P_j,4 MSB of the packet memory address in which the data is written"
bitfld.long 0x00 0.--3. "WR_ADDR,4 MSB of the packet memory address in which the data is written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "EDP_CORE_SOURCE_PIF_WR_REQ_P_j,Write request bit for the host write transaction"
bitfld.long 0x04 0. "HOST_WR,Write request bit for the host write transaction active high" "0,1"
line.long 0x08 "EDP_CORE_SOURCE_PIF_RD_ADDR_P_j,4 MSB of the packet memory address from which the data is"
bitfld.long 0x08 0.--3. "RD_ADDR,4 MSB of the packet memory address from which the data is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "EDP_CORE_SOURCE_PIF_RD_REQ_P_j,Read request bit for the host read transaction"
bitfld.long 0x0C 0. "HOST_RD,Read request bit for the host read transaction active high" "0,1"
line.long 0x10 "EDP_CORE_SOURCE_PIF_DATA_WR_P_j,The 32 bits of the data to be written to the packet memory"
line.long 0x14 "EDP_CORE_SOURCE_PIF_DATA_RD_P_j,The 32 bits of the data to be read from the packet memory"
line.long 0x18 "EDP_CORE_SOURCE_PIF_FIFO1_FLUSH_P_j,Fifo1 flush Offset = 00030818h + (j * 40h); where j = 0h to 3h"
bitfld.long 0x18 0. "FIFO1_FLUSH,Fifo1 flush bit active high" "0,1"
line.long 0x1C "EDP_CORE_SOURCE_PIF_FIFO2_FLUSH_P_j,Fifo2 flush Offset = 0003081Ch + (j * 40h); where j = 0h to 3h"
bitfld.long 0x1C 0. "FIFO2_FLUSH,Fifo2 flush bit active high" "0,1"
line.long 0x20 "EDP_CORE_SOURCE_PIF_STATUS_P_j,Status bits for the PIF module Offset = 00030820h + (j * 40h); where j = 0h to 3h"
bitfld.long 0x20 4. "FIFO2_EMPTY,Fifo2 empty indication when high indicates that FIFO2 is empty" "0,1"
bitfld.long 0x20 3. "FIFO1_FULL,Fifo1 full indication when high indicates that FIFO1 is full" "0,1"
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bitfld.long 0x20 0.--2. "SOURCE_PKT_MEM_CTRL_FSM_STATE,State of the FSM that controls packet memory transactions" "0,1,2,3,4,5,6,7"
line.long 0x24 "EDP_CORE_SOURCE_PIF_INTERRUPT_SOURCE_P_J,Interrupt sources of the PIF module. active high"
bitfld.long 0x24 10. "PPS_SENT,PPS sent to framer indication" "0,1"
bitfld.long 0x24 9. "FIFO2_UNDERFLOW,Fifo2 underflow indication" "0,1"
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bitfld.long 0x24 8. "FIFO2_OVERFLOW,Fifo2 overflow indication" "0,1"
bitfld.long 0x24 7. "FIFO1_UNDERFLOW,Fifo1 underflow indication" "0,1"
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bitfld.long 0x24 6. "FIFO1_OVERFLOW,Fifo1 overflow indication" "0,1"
bitfld.long 0x24 5. "ALLOC_WR_ERROR,Error happened invalid write to the allocation table" "0,1"
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bitfld.long 0x24 4. "ALLOC_WR_DONE,Successful write to the allocation table" "0,1"
bitfld.long 0x24 2. "NONVALID_TYPE_REQUESTED_INT,Indication that nonvalid type of packet is requested by the packet interface" "0,1"
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bitfld.long 0x24 1. "HOST_RD_DONE_INT,Indication that the host read transaction finished" "0,1"
bitfld.long 0x24 0. "HOST_WR_DONE_INT,Indication that the host write transaction finished" "0,1"
line.long 0x28 "EDP_CORE_SOURCE_PIF_INTERRUPT_MASK_P_J,Masks for the interrupt sources in the SOURCE_PIF_INTERRUPT_SOURCE register. when set high. these bits disable the corresponding interrupts Offset = 00030828h + (j * 40h); where j = 0h to 3h"
bitfld.long 0x28 10. "PPS_SENT_MASK,Masks the pps_sent interrupt" "0,1"
bitfld.long 0x28 9. "FIFO2_UNDERFLOW_MASK,Masks the fifo2_underflow interrupt" "0,1"
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bitfld.long 0x28 8. "FIFO2_OVERFLOW_MASK,Masks the fifo2_overflow interrupt" "0,1"
bitfld.long 0x28 7. "FIFO1_UNDERFLOW_MASK,Masks the fifo1_underflow interrupt" "0,1"
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bitfld.long 0x28 6. "FIFO1_OVERFLOW_MASK,Masks the fifo1_overflow interrupt" "0,1"
bitfld.long 0x28 5. "ALLOC_WR_ERROR_MASK,Masks the alloc_wr_error interrupt" "0,1"
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bitfld.long 0x28 4. "ALLOC_WR_DONE_MASK,Masks the alloc_wr_done interrupt" "0,1"
bitfld.long 0x28 2. "NONVALID_TYPE_REQUESTED_INT_MASK,Masks the nonvalid_type_requested_int interrupt" "0,1"
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bitfld.long 0x28 1. "HOST_RD_DONE_INT_MASK,Masks the host_rd_done_int interrupt" "0,1"
bitfld.long 0x28 0. "HOST_WR_DONE_INT_MASK,Masks the host_wr_done_int interrupt" "0,1"
line.long 0x2C "EDP_CORE_SOURCE_PIF_PKT_ALLOC_REG_P_j,Packet configuration to be stored in the allocation table Offset = 0003082Ch + (j * 40h); where j = 0h to 3h"
bitfld.long 0x2C 17. "ACTIVE_IDLE_TYPE,Indicates in which mode the SDP will be sent" "0,1"
bitfld.long 0x2C 16. "TYPE_VALID,1 for valid 0 for nonvalid" "0,1"
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hexmask.long.byte 0x2C 8.--15. 1. "PACKET_TYPE,"
bitfld.long 0x2C 0.--3. "PKT_ALLOC_ADDRESS,Address of the register in the source allocation table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "EDP_CORE_SOURCE_PIF_PKT_ALLOC_WR_EN_P_j,Enable bit for writing to the allocation table Offset = 00030830h + (j * 40h); where j = 0h to 3h"
bitfld.long 0x30 0. "PKT_ALLOC_WR_EN,Enable bit for writing to the allocation table active high" "0,1"
line.long 0x34 "EDP_CORE_SOURCE_PIF_SW_RESET_P_j,Software reset"
bitfld.long 0x34 0. "SW_RST,Software reset active high" "0,1"
line.long 0x38 "EDP_CORE_SOURCE_PIF_PPS_HEADER_P_j,PPS header Offset = 00030838h + (j * 40h); where j = 0h to 3h"
line.long 0x3C "EDP_CORE_SOURCE_PIF_PPS_P_j,PPS SDP indication Offset = 0003083Ch + (j * 40h); where j = 0h to 3h"
bitfld.long 0x3C 0. "PPS,PPS SDP indication active high" "0,1"
group.long 0x30A00++0x13
line.long 0x00 "EDP_CORE_AUX_CONFIG_P,AUX Configuration Register"
bitfld.long 0x00 24.--28. "TERM_SEG_EN,Enables output resistor segments for termination impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "TX_CURR_CTRL,TX current for output diff pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--14. "TX_SLEW_RATE,TX slew rate adjust" "0,1,2,3"
bitfld.long 0x00 12. "TX_REDUCED_SWING,Control for lowering AUX transmitter swing level" "0,1"
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bitfld.long 0x00 8.--10. "RX_HYST_LVL,Hysteresis control for AUX receiver front end" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--5. "RX_DEGLITCH_FILTER,Suppresses high-frequency pulses on AUX receiver output" "0,1,2,3"
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bitfld.long 0x00 2. "RX_OFFSET_DIS,Disables internal receiver cmn mode offset" "0,1"
bitfld.long 0x00 0.--1. "BANDGAP_ADJUST,Bandgap startup circuit adjust" "0,1,2,3"
line.long 0x04 "EDP_CORE_AUX_CTRL_P,AUX Control Register"
bitfld.long 0x04 1. "DECAP_EN,Decap enable" "0,1"
bitfld.long 0x04 0. "BANDGAP_EN,Bandgap enable" "0,1"
line.long 0x08 "EDP_CORE_AUX_ATBSEL_P,AUX_ATBSEL"
hexmask.long.byte 0x08 0.--7. 1. "AUXIP_ATBSEL_ONEHOT,auxip_atbsel_onehot"
line.long 0x0C "EDP_CORE_AUX_TESTMODE_CTL_P,AUX IP test control register"
bitfld.long 0x0C 4. "DECAP_EN_DEL,decap_en_del test value" "0,1"
bitfld.long 0x0C 3. "AUX_DATA_IN,aux_data_in test value" "0,1"
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bitfld.long 0x0C 2. "TX_EN_CTRL,tx_en test value" "0,1"
bitfld.long 0x0C 1. "RX_EN_CTRL,rx_en test value" "0,1"
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bitfld.long 0x0C 0. "AUX_TESTMODE_EN,AUX test enable" "0,1"
line.long 0x10 "EDP_CORE_AUX_TESTMODE_ST_P,AUX IP interface status"
bitfld.long 0x10 1. "AUX_DATA_OUT,Raw status of aux_data_out output from AUX IP" "0,1"
bitfld.long 0x10 0. "HPD_DATA_OUT,Raw status of HPD output from AUX IP" "0,1"
group.long 0x30A20++0x1F
line.long 0x00 "EDP_CORE_PHY_RESET_P,PHY Reset Control Register"
bitfld.long 0x00 8. "PHY_RESET," "0,1"
bitfld.long 0x00 7. "PMA_TX_ELEC_IDLE_LN_3,PMA Tx electrical idle for line 3" "0,1"
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bitfld.long 0x00 6. "PMA_TX_ELEC_IDLE_LN_2,PMA Tx electrical idle for line 2" "0,1"
bitfld.long 0x00 5. "PMA_TX_ELEC_IDLE_LN_1,PMA Tx electrical idle for line 1" "0,1"
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bitfld.long 0x00 4. "PMA_TX_ELEC_IDLE_LN_0,PMA Tx electrical idle for line 0" "0,1"
bitfld.long 0x00 3. "PHY_L03_RESET_N," "0,1"
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bitfld.long 0x00 2. "PHY_L02_RESET_N," "0,1"
bitfld.long 0x00 1. "PHY_L01_RESET_N," "0,1"
newline
bitfld.long 0x00 0. "PHY_L00_RESET_N," "0,1"
line.long 0x04 "EDP_CORE_PMA_PLLCLK_EN_P,PHY Link PLL Clock Enable Register"
bitfld.long 0x04 3. "PMA_XCVR_PLLCLK_EN_LN_3,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 3 " "0,1"
bitfld.long 0x04 2. "PMA_XCVR_PLLCLK_EN_LN_2,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 2 " "0,1"
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bitfld.long 0x04 1. "PMA_XCVR_PLLCLK_EN_LN_1,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 1 " "0,1"
bitfld.long 0x04 0. "PMA_XCVR_PLLCLK_EN_LN_0,Link PLL clock enable used to cleanly turn off the data rate clock in the PMA for line 0 " "0,1"
line.long 0x08 "EDP_CORE_PMA_PLLCLK_EN_ACK_P,PHY Link PLL Clock Status Register"
bitfld.long 0x08 3. "PMA_XCVR_PLLCLK_EN_ACK_LN_3,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 3 is running" "0,1"
bitfld.long 0x08 2. "PMA_XCVR_PLLCLK_EN_ACK_LN_2,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 2 is running" "0,1"
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bitfld.long 0x08 1. "PMA_XCVR_PLLCLK_EN_ACK_LN_1,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 1 is running" "0,1"
bitfld.long 0x08 0. "PMA_XCVR_PLLCLK_EN_ACK_LN_0,Link PLL clock enable acknowledgement indicates whether the data rate clock in the PMA for line 0 is running" "0,1"
line.long 0x0C "EDP_CORE_PMA_POWER_STATE_REQ_P,PHY Link Power State Request Register"
bitfld.long 0x0C 24.--29. "PMA_XCVR_POWER_STATE_REQ_LN_3,Change the link power state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 16.--21. "PMA_XCVR_POWER_STATE_REQ_LN_2,Change the link power state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 8.--13. "PMA_XCVR_POWER_STATE_REQ_LN_1,Change the link power state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--5. "PMA_XCVR_POWER_STATE_REQ_LN_0,Change the link power state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "EDP_CORE_PMA_POWER_STATE_ACK_P,PHY Link Power State Status Register"
bitfld.long 0x10 24.--29. "PMA_XCVR_POWER_STATE_ACK_LN_3,Link power state acknowledgement this signal provides indication that a power state change request has completed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 16.--21. "PMA_XCVR_POWER_STATE_ACK_LN_2,Link power state acknowledgement this signal provides indication that a power state change request has completed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 8.--13. "PMA_XCVR_POWER_STATE_ACK_LN_1,Link power state acknowledgement this signal provides indication that a power state change request has completed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 0.--5. "PMA_XCVR_POWER_STATE_ACK_LN_0,Link power state acknowledgement this signal provides indication that a power state change request has completed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "EDP_CORE_PMA_CMN_READY_P,PMA Operation Status Register"
bitfld.long 0x14 0. "PMA_CMN_READY,PMA common ready " "0,1"
line.long 0x18 "EDP_CORE_PMA_TX_VMARGIN_P,PMA Tx Voltage Margin Control Register"
bitfld.long 0x18 24.--25. "PMA_TX_VMARGIN_LN_3,Drives PMA input tx_vmargin_ln_3 for the associated lane" "0,1,2,3"
bitfld.long 0x18 16.--17. "PMA_TX_VMARGIN_LN_2,Drives PMA input tx_vmargin_ln_2 for the associated lane" "0,1,2,3"
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bitfld.long 0x18 8.--9. "PMA_TX_VMARGIN_LN_1,Drives PMA input tx_vmargin_ln_1 for the associated lane" "0,1,2,3"
bitfld.long 0x18 0.--1. "PMA_TX_VMARGIN_LN_0,Drives PMA input tx_vmargin_ln_0 for the associated lane" "0,1,2,3"
line.long 0x1C "EDP_CORE_PMA_TX_DEEMPH_P,PMA Tx Deemphasis Level Control Register"
bitfld.long 0x1C 24.--25. "PMA_TX_DEEMPHASIS_LN_3,Drives PMA input tx_deemphasis_ln_3 for the associated lane" "0,1,2,3"
bitfld.long 0x1C 16.--17. "PMA_TX_DEEMPHASIS_LN_2,Drives PMA input tx_deemphasis_ln_2 for the associated lane" "0,1,2,3"
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bitfld.long 0x1C 8.--9. "PMA_TX_DEEMPHASIS_LN_1,Drives PMA input tx_deemphasis_ln_1 for the associated lane" "0,1,2,3"
bitfld.long 0x1C 0.--1. "PMA_TX_DEEMPHASIS_LN_0,Drives PMA input tx_deemphasis_ln_0 for the associated lane" "0,1,2,3"
group.long 0x30A60++0x03
line.long 0x00 "EDP_CORE_ASF_IPS_CTRL,ASF control register. imlemented only when ASF support is enabled in IP configuration"
bitfld.long 0x00 0. "IF_ADDR_PARCHECK_EN,When set enables parity check at APB/SAPB address bus" "0,1"
group.long 0x30B00++0x13
line.long 0x00 "EDP_CORE_ASF_INT_STATUS,ASF Interrupt Status Register"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and status registers error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt 1 is active 0 is not active" "0,1"
line.long 0x04 "EDP_CORE_ASF_INT_RAW_STATUS,ASF Interrupt Raw Status Register"
bitfld.long 0x04 6. "SF_INTEGRITY_ERR,Integrity error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt 1 is active 0 is not active" "0,1"
line.long 0x08 "EDP_CORE_ASF_INT_MASK,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for Integrity error interrupt 0 is active 1 is not active" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for Protocol error interrupt 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1"
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bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for Transaction timeouts error interrupt 0 is active 1 is not active" "0,1"
bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for Configuration and status registers error interrupt 0 is active 1 is not active" "0,1"
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bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for Data and address paths parity error interrupt 0 is active 1 is not active" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt 0 is active 1 is not active" "0,1"
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bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt 0 is active 1 is not active" "0,1"
line.long 0x0C "EDP_CORE_ASF_INT_TEST,The ASF interrupt test register emulate hardware even"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for Integrity error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for Protocol error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for Transaction timeouts error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for Configuration and status registers error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for Data and address paths parity error interrupt 1 is active 0 is not active" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt 1 is active 0 is not active" "0,1"
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bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt 1 is active 0 is not active" "0,1"
line.long 0x10 "EDP_CORE_ASF_FATAL_NONFATAL_SELECT,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable Integrity error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable Protocol error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
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bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable Transaction timeouts error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable Configuration and status registers error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
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bitfld.long 0x10 2. "ASF_DAP_ERR,Enable Data and address paths parity error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
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bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal 1 is fatal interrupt 0 is non-fatal" "0,1"
rgroup.long 0x30B20++0x0B
line.long 0x00 "EDP_CORE_ASF_SRAM_CORR_FAULT_STATUS,Status register for SRAM correctable fault"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "EDP_CORE_ASF_SRAM_UNCORR_FAULT_STATUS,Status register for SRAM uncorrectable fault"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "EDP_CORE_ASF_SRAM_FAULT_STATUS,Statistics register for SRAM faults"
hexmask.long.word 0x08 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x30B30++0x0B
line.long 0x00 "EDP_CORE_ASF_TRANS_TO_CTRL,Control register to configure the ASF transaction timeout monitors"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring 1 is active 0 is not active" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "EDP_CORE_ASF_TRANS_TO_FAULT_MASK,Control register to mask out ASF transaction timeout faults from triggering interrupts"
bitfld.long 0x04 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for SAPB interface for transaction timeout fault 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1"
bitfld.long 0x04 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for APB interface for transaction timeout fault 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1"
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bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for Xtensa watchdog error for transaction timeout fault 0 is active 1 is not active.Interrupt from source which mask is 0 is permitted otherwise interrupt is not permitted" "0,1"
line.long 0x08 "EDP_CORE_ASF_TRANS_TO_FAULT_STATUS,Status register for transaction timeouts fault"
bitfld.long 0x08 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for SAPB interface for transaction timeout fault 1 is active 0 is not active" "0,1"
bitfld.long 0x08 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for APB interface for transaction timeout fault 1 is active 0 is not active" "0,1"
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bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for Xtensa watchdog error for transaction timeout fault 1 is active 0 is not active" "0,1"
group.long 0x30B40++0x07
line.long 0x00 "EDP_CORE_ASF_PROTOCOL_FAULT_MASK,Control register to mask out ASF Protocol faults from triggering interrupts"
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask bit for FEC FSM fault" "0,1"
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask bit for 8b10b Encoding fault from FEC module" "0,1"
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bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask bit for Party Encoding fault from FEC module" "0,1"
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask bit for Parity Generation fault from FEC module" "0,1"
line.long 0x04 "EDP_CORE_ASF_PROTOCOL_FAULT_STATUS,Status register for protocol faults"
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_3_STATUS,FEC symbol injection fault" "0,1"
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_2_STATUS,8b10b Encoding fault in FEC module" "0,1"
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bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_1_STATUS,Party Encoding fault in FEC module" "0,1"
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_0_STATUS,Parity Generation fault in FEC module" "0,1"
group.long 0x30C00++0x03
line.long 0x00 "EDP_CORE_COM_MAIN_CONF_P,Encoder common configuration values"
bitfld.long 0x00 6. "AUTO_REGS_DB_UPDATE,Active-High to enable auto update double buffer regs on vsync falling edge" "0,1"
bitfld.long 0x00 5. "MULTIPLEX_MODE_EOC_ENABLE,When split_panel and multiplex_mode are set indicates that multiplexer output separated chunks [inserts zeros on partial words at each end of chunk] and signal end of chunks" "0,1"
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bitfld.long 0x00 4. "INPUT_MODE,Video input interface mode" "0,1"
bitfld.long 0x00 3. "REGS_DE_RASTER_ENABLE,Indicates if the De-Rasterization Buffer is used or bypassed: '1' Active '0' Bypassed" "0,1"
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bitfld.long 0x00 2. "REGS_MULTIPLEX_SEL_OUT,When split_panel and multiplex_mode are set indicates to which output the multiplexed stream is sent: '0': enc0_data_out '1': enc1_data_out" "0,1"
bitfld.long 0x00 1. "REGS_MULTIPLEX_MODE,Active-High indicates that both encoders are used to produce a multiplex stream on a single Transport link" "0,1"
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bitfld.long 0x00 0. "REGS_SPLIT_PANEL,Active-High indicates that both encoders are used in parallel for one video stream [L and R split]" "0,1"
group.long 0x30D20++0x6B
line.long 0x00 "EDP_CORE_ENC0_MAIN_CONF_P,Encoder Main Configuration values"
hexmask.long.byte 0x00 24.--31. 1. "INITIAL_LINES,Number of lines to wait before initiating transport in Command Mode"
bitfld.long 0x00 20. "ICH_RST_EOL,Forces the ICH to reset at EOL [when not in split mode]" "0,1"
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bitfld.long 0x00 19. "VIDEO_MODE,MIPI Video/Command mode: '0' Command mode '1' Video mode" "0,1"
bitfld.long 0x00 18. "BLOCK_PRED_ENABLE,Active-High input Block Prediction Enable" "0,1"
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hexmask.long.word 0x00 8.--17. 1. "BITS_PER_PIXEL,Target bits per pixel"
bitfld.long 0x00 4.--7. "LINEBUF_DEPTH,Depth of the line buffer used by the decoder [i.e. the number of bits stored for each component of the pixels on the previous line]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "ENABLE_422,Active-High input to indicate the data_in pixels are" "0,1"
bitfld.long 0x00 2. "CONVERT_RGB,Active-High input to indicate the data_in pixels are RGB" "0,1"
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bitfld.long 0x00 0.--1. "INPUT_BPC,Indicates the current input pixel stream bits per component" "0,1,2,3"
line.long 0x04 "EDP_CORE_ENC0_PICTURE_SIZE_P,Encoder Picture configuration"
hexmask.long.word 0x04 16.--31. 1. "PICTURE_HEIGHT,Picture height"
hexmask.long.word 0x04 0.--15. 1. "PICTURE_WIDTH,Picture width"
line.long 0x08 "EDP_CORE_ENC0_SLICE_SIZE_P,Encoder Slice(s) configuration"
hexmask.long.word 0x08 16.--31. 1. "SLICE_HEIGHT,Slice height"
hexmask.long.word 0x08 0.--15. 1. "SLICE_WIDTH,Slice width"
line.long 0x0C "EDP_CORE_ENC0_MISC_SIZE_P,Encoder Group. Output Buffer(s). and Transport Chunk Size"
hexmask.long.word 0x0C 16.--31. 1. "CHUNK_SIZE,Chunk size in bytes"
hexmask.long.word 0x0C 2.--15. 1. "OB_MAX_ADDR,Output Buffer[s] max pointer address[es]"
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bitfld.long 0x0C 0.--1. "SLICE_LAST_GROUP_SIZE,Size of last group of the slice line" "0,1,2,3"
line.long 0x10 "EDP_CORE_ENC0_HRD_DELAYS_P,Hypothetical Reference Decoder delays"
hexmask.long.word 0x10 16.--31. 1. "INITIAL_DEC_DELAY,Initial Decoder delay"
hexmask.long.word 0x10 0.--9. 1. "INITIAL_XMIT_DELAY,Initial Decoder Transmit delay"
line.long 0x14 "EDP_CORE_ENC0_RC_SCALE_P,RC Calculate Buffer Fullness and Offset. Scale value"
bitfld.long 0x14 0.--5. "INITIAL_SCALE_VALUE,Three fractional bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "EDP_CORE_ENC0_RC_SCALE_INC_DEC_P,RC Calculate Buffer Fullness and Offset. Increment and Decrement Scale values"
hexmask.long.word 0x18 16.--27. 1. "SCALE_DECREMENT_INTERVAL,RC scale decrement value"
hexmask.long.word 0x18 0.--15. 1. "SCALE_INCREMENT_INTERVAL,RC scale increment value"
line.long 0x1C "EDP_CORE_ENC0_RC_OFFSETS_1_P,RC Calculate Buffer Fullness and Offset. Various Offset control values 1"
bitfld.long 0x1C 0.--4. "FIRST_LINE_BPG_OFFSET,First Line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "EDP_CORE_ENC0_RC_OFFSETS_2_P,RC Calculate Buffer Fullness and Offset. Various Offset control values 2"
hexmask.long.word 0x20 16.--31. 1. "SLICE_BPG_OFFSET,Extra budget per group [11 fractional bits]"
hexmask.long.word 0x20 0.--15. 1. "NFL_BPG_OFFSET,Non First Line [11 fractional bits]"
line.long 0x24 "EDP_CORE_ENC0_RC_OFFSETS_3_P,RC Calculate Buffer Fullness and Offset. Various Offset control values 3"
hexmask.long.word 0x24 16.--31. 1. "FINAL_OFFSET,Final Offset"
hexmask.long.word 0x24 0.--15. 1. "INITIAL_OFFSET,Initial Offset"
line.long 0x28 "EDP_CORE_ENC0_FLATNESS_DETECTION_P,Flatness Signaling QP Override thresholds"
hexmask.long.byte 0x28 10.--17. 1. "FLATNESS_DET_THRESH,Flatness Detection Threshold as defined in PPS table of the DSC specification"
bitfld.long 0x28 5.--9. "FLATNESS_MAX_QP,Maximum threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 0.--4. "FLATNESS_MIN_QP,Minimum threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "EDP_CORE_ENC0_RC_MODEL_SIZE_P,RC Model Size"
hexmask.long.word 0x2C 0.--15. 1. "RC_MODEL_SIZE,RC Model Size"
line.long 0x30 "EDP_CORE_ENC0_RC_CONFIG_P,RC Model Various Config"
bitfld.long 0x30 24.--27. "RC_TGT_OFFSET_LO,RC Target offset low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 20.--23. "RC_TGT_OFFSET_HI,RC Target offset high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 13.--17. "RC_QUANT_INCR_LIMIT1,RC quantization increment limit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 8.--12. "RC_QUANT_INCR_LIMIT0,RC quantization increment limit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 0.--3. "RC_EDGE_FACTOR,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "EDP_CORE_ENC0_RC_BUF_THRESH_0_P,RC Model Buffer Thresholds 0"
hexmask.long.byte 0x34 24.--31. 1. "RC_BUF_THRESH_3,8 MSBs of the value"
hexmask.long.byte 0x34 16.--23. 1. "RC_BUF_THRESH_2,8 MSBs of the value"
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hexmask.long.byte 0x34 8.--15. 1. "RC_BUF_THRESH_1,8 MSBs of the value"
hexmask.long.byte 0x34 0.--7. 1. "RC_BUF_THRESH_0,8 MSBs of the value"
line.long 0x38 "EDP_CORE_ENC0_RC_BUF_THRESH_1_P,RC Model Buffer Thresholds 1"
hexmask.long.byte 0x38 24.--31. 1. "RC_BUF_THRESH_7,8 MSBs of the value"
hexmask.long.byte 0x38 16.--23. 1. "RC_BUF_THRESH_6,8 MSBs of the value"
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hexmask.long.byte 0x38 8.--15. 1. "RC_BUF_THRESH_5,8 MSBs of the value"
hexmask.long.byte 0x38 0.--7. 1. "RC_BUF_THRESH_4,8 MSBs of the value"
line.long 0x3C "EDP_CORE_ENC0_RC_BUF_THRESH_2_P,RC Model Buffer Thresholds 2"
hexmask.long.byte 0x3C 24.--31. 1. "RC_BUF_THRESH_11,8 MSBs of the value"
hexmask.long.byte 0x3C 16.--23. 1. "RC_BUF_THRESH_10,8 MSBs of the value"
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hexmask.long.byte 0x3C 8.--15. 1. "RC_BUF_THRESH_9,8 MSBs of the value"
hexmask.long.byte 0x3C 0.--7. 1. "RC_BUF_THRESH_8,8 MSBs of the value"
line.long 0x40 "EDP_CORE_ENC0_RC_BUF_THRESH_3_P,RC Model Buffer Thresholds 3"
hexmask.long.byte 0x40 8.--15. 1. "RC_BUF_THRESH_13,8 MSBs of the value"
hexmask.long.byte 0x40 0.--7. 1. "RC_BUF_THRESH_12,8 MSBs of the value"
line.long 0x44 "EDP_CORE_ENC0_RC_MIN_QP_0_P,RC Min QP 0"
bitfld.long 0x44 20.--24. "RANGE_MIN_QP_4,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 15.--19. "RANGE_MIN_QP_3,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 10.--14. "RANGE_MIN_QP_2,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 5.--9. "RANGE_MIN_QP_1,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 0.--4. "RANGE_MIN_QP_0,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x48 "EDP_CORE_ENC0_RC_MIN_QP_1_P,RC Min QP 1"
bitfld.long 0x48 20.--24. "RANGE_MIN_QP_9,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 15.--19. "RANGE_MIN_QP_8,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 10.--14. "RANGE_MIN_QP_7,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 5.--9. "RANGE_MIN_QP_6,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 0.--4. "RANGE_MIN_QP_5,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x4C "EDP_CORE_ENC0_RC_MIN_QP_2_P,RC Min QP 2"
bitfld.long 0x4C 20.--24. "RANGE_MIN_QP_14,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 15.--19. "RANGE_MIN_QP_13,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 10.--14. "RANGE_MIN_QP_12,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 5.--9. "RANGE_MIN_QP_11,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 0.--4. "RANGE_MIN_QP_10,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x50 "EDP_CORE_ENC0_RC_MAX_QP_0_P,RC Max QP 0"
bitfld.long 0x50 20.--24. "RANGE_MAX_QP_4,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 15.--19. "RANGE_MAX_QP_3,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 10.--14. "RANGE_MAX_QP_2,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 5.--9. "RANGE_MAX_QP_1,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 0.--4. "RANGE_MAX_QP_0,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x54 "EDP_CORE_ENC0_RC_MAX_QP_1_P,RC Max QP 1"
bitfld.long 0x54 20.--24. "RANGE_MAX_QP_9,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 15.--19. "RANGE_MAX_QP_8,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 10.--14. "RANGE_MAX_QP_7,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 5.--9. "RANGE_MAX_QP_6,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0.--4. "RANGE_MAX_QP_5,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x58 "EDP_CORE_ENC0_RC_MAX_QP_2_P,RC Max QP 2"
bitfld.long 0x58 20.--24. "RANGE_MAX_QP_14,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 15.--19. "RANGE_MAX_QP_13,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 10.--14. "RANGE_MAX_QP_12,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 5.--9. "RANGE_MAX_QP_11,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 0.--4. "RANGE_MAX_QP_10,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x5C "EDP_CORE_ENC0_RC_RANGE_BPG_OFFSETS_0_P,RC Range bpg Offsets 0"
bitfld.long 0x5C 24.--29. "RANGE_BPG_OFFSET_4,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x5C 18.--23. "RANGE_BPG_OFFSET_3,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x5C 12.--17. "RANGE_BPG_OFFSET_2,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x5C 6.--11. "RANGE_BPG_OFFSET_1,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x5C 0.--5. "RANGE_BPG_OFFSET_0,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "EDP_CORE_ENC0_RC_RANGE_BPG_OFFSETS_1_P,RC Range bpg Offsets 1"
bitfld.long 0x60 24.--29. "RANGE_BPG_OFFSET_9,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x60 18.--23. "RANGE_BPG_OFFSET_8,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x60 12.--17. "RANGE_BPG_OFFSET_7,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x60 6.--11. "RANGE_BPG_OFFSET_6,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x60 0.--5. "RANGE_BPG_OFFSET_5,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x64 "EDP_CORE_ENC0_RC_RANGE_BPG_OFFSETS_2_P,RC Range bpg Offsets 2"
bitfld.long 0x64 24.--29. "RANGE_BPG_OFFSET_14,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x64 18.--23. "RANGE_BPG_OFFSET_13,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x64 12.--17. "RANGE_BPG_OFFSET_12,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x64 6.--11. "RANGE_BPG_OFFSET_11,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x64 0.--5. "RANGE_BPG_OFFSET_10,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x68 "EDP_CORE_ENC0_DPI_CTRL_OUT_DELAY_P,Delay applied to DPI input control signals to generate DPI output control signals"
hexmask.long.word 0x68 0.--15. 1. "DPI_CTRL_OUT_DELAY,Delay in number of encx clock cycles"
rgroup.long 0x30DC0++0x1B
line.long 0x00 "EDP_CORE_ENC0_GENERAL_STATUS_P,General Encoder Status"
bitfld.long 0x00 6. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] is full.For Debug purposes only" "0,1"
bitfld.long 0x00 5. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] is full.For Debug purposes only" "0,1"
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bitfld.long 0x00 4. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] is empty.For Debug purposes only" "0,1"
bitfld.long 0x00 3. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] is empty.For Debug purposes only" "0,1"
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bitfld.long 0x00 2. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x00 1. "FRAME_STARTED,Encoder is currently processing a frame" "0,1"
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bitfld.long 0x00 0. "CE,Flow control internal clock enable status.For Debug purposes only" "0,1"
line.long 0x04 "EDP_CORE_ENC0_HSLICE_STATUS_P,Hard Slice Encoded Status"
hexmask.long.word 0x04 16.--31. 1. "SLICE_COUNT_ENCODED,Actual slice number of current frame being processed at VLC encoder.Not re-synchronized in register clock domain"
hexmask.long.word 0x04 0.--15. 1. "SLICE_LINE_COUNT_ENCODED,Actual line number of current slice being processed at VLC encoder.Not re-synchronized in register clock domain"
line.long 0x08 "EDP_CORE_ENC0_OUT_STATUS_P,Outputted Slice Status"
hexmask.long.word 0x08 16.--31. 1. "SLICE_COUNT_OUT,Actual slice number of current frame being read at output interface.Not re-synchronized in register clock domain"
hexmask.long.word 0x08 0.--15. 1. "SLICE_LINE_COUNT_OUT,Actual line number of current slice being read at output interface.Not re-synchronized in register clock domain"
line.long 0x0C "EDP_CORE_ENC0_INT_STAT_P,Encoder Interrupt Status"
bitfld.long 0x0C 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1"
bitfld.long 0x0C 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1"
newline
bitfld.long 0x0C 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1"
bitfld.long 0x0C 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1"
newline
bitfld.long 0x0C 6. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x0C 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1"
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bitfld.long 0x0C 4. "CE,Flow control internal clock enable becomes high" "0,1"
bitfld.long 0x0C 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc_model_buffer 1 [soft slice 1] overflow" "0,1"
newline
bitfld.long 0x0C 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc_model_buffer 0 [soft slice 0] overflow" "0,1"
bitfld.long 0x0C 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 [soft slice 1] underflow" "0,1"
newline
bitfld.long 0x0C 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 [soft slice 0] underflow" "0,1"
line.long 0x10 "EDP_CORE_ENC0_INT_CLR_P,Encoder Interrupt Clear"
bitfld.long 0x10 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1"
bitfld.long 0x10 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1"
newline
bitfld.long 0x10 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1"
bitfld.long 0x10 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1"
newline
bitfld.long 0x10 6. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x10 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1"
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bitfld.long 0x10 4. "CE,Flow control internal clock enable" "0,1"
bitfld.long 0x10 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1"
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bitfld.long 0x10 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1"
bitfld.long 0x10 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 underflow" "0,1"
newline
bitfld.long 0x10 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 underflow" "0,1"
line.long 0x14 "EDP_CORE_ENC0_INT_MASK_P,Encoder Interrupt Mask"
bitfld.long 0x14 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1"
bitfld.long 0x14 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1"
newline
bitfld.long 0x14 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1"
bitfld.long 0x14 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1"
newline
bitfld.long 0x14 6. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x14 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1"
newline
bitfld.long 0x14 4. "CE,Flow control internal clock enable" "0,1"
bitfld.long 0x14 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1"
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bitfld.long 0x14 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1"
bitfld.long 0x14 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow" "0,1"
newline
bitfld.long 0x14 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow" "0,1"
line.long 0x18 "EDP_CORE_ENC0_INT_TEST_P,Encoder Interrupt Test"
bitfld.long 0x18 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full test" "0,1"
bitfld.long 0x18 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full test" "0,1"
newline
bitfld.long 0x18 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty test" "0,1"
bitfld.long 0x18 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty test" "0,1"
newline
bitfld.long 0x18 6. "FRAME_DONE,Encoder finished a frame test" "0,1"
bitfld.long 0x18 5. "FRAME_STARTED,Encoder is started to process a frame test" "0,1"
newline
bitfld.long 0x18 4. "CE,Flow control internal clock enable test" "0,1"
bitfld.long 0x18 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow test" "0,1"
newline
bitfld.long 0x18 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow test" "0,1"
bitfld.long 0x18 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow test" "0,1"
newline
bitfld.long 0x18 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow test" "0,1"
group.long 0x30E20++0x6B
line.long 0x00 "EDP_CORE_ENC1_MAIN_CONF_P,Encoder Main Configuration values test"
hexmask.long.byte 0x00 24.--31. 1. "INITIAL_LINES,Number of lines to wait before initiating transport in Command Mode"
bitfld.long 0x00 20. "ICH_RST_EOL,Forces the ICH to reset at EOL [when not in split mode]" "0,1"
newline
bitfld.long 0x00 19. "VIDEO_MODE,MIPI Video/Command mode: '0' Command mode '1' Video mode" "0,1"
bitfld.long 0x00 18. "BLOCK_PRED_ENABLE,Active-High input Block Prediction Enable" "0,1"
newline
hexmask.long.word 0x00 8.--17. 1. "BITS_PER_PIXEL,Target bits per pixel"
bitfld.long 0x00 4.--7. "LINEBUF_DEPTH,Depth of the line buffer used by the decoder [i.e. the number of bits stored for each component of the pixels on the previous line]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "ENABLE_422,Active-High input to indicate the data_in pixels are" "0,1"
bitfld.long 0x00 2. "CONVERT_RGB,Active-High input to indicate the data_in pixels are RGB" "0,1"
newline
bitfld.long 0x00 0.--1. "INPUT_BPC,Indicates the current input pixel stream bits per component" "0,1,2,3"
line.long 0x04 "EDP_CORE_ENC1_PICTURE_SIZE_P,Encoder Picture configuration"
hexmask.long.word 0x04 16.--31. 1. "PICTURE_HEIGHT,Picture height"
hexmask.long.word 0x04 0.--15. 1. "PICTURE_WIDTH,Picture width"
line.long 0x08 "EDP_CORE_ENC1_SLICE_SIZE_P,Encoder Slice(s) configuration"
hexmask.long.word 0x08 16.--31. 1. "SLICE_HEIGHT,Slice height"
hexmask.long.word 0x08 0.--15. 1. "SLICE_WIDTH,Slice width"
line.long 0x0C "EDP_CORE_ENC1_MISC_SIZE_P,Encoder Group. Output Buffer(s). and Transport Chunk Size"
hexmask.long.word 0x0C 16.--31. 1. "CHUNK_SIZE,Chunk size in bytes"
hexmask.long.word 0x0C 2.--15. 1. "OB_MAX_ADDR,Output Buffer[s] max pointer address[es]"
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bitfld.long 0x0C 0.--1. "SLICE_LAST_GROUP_SIZE,Size of last group of the slice line" "0,1,2,3"
line.long 0x10 "EDP_CORE_ENC1_HRD_DELAYS_P,Hypothetical Reference Decoder delays"
hexmask.long.word 0x10 16.--31. 1. "INITIAL_DEC_DELAY,Initial Decoder delay"
hexmask.long.word 0x10 0.--9. 1. "INITIAL_XMIT_DELAY,Initial Decoder Transmit delay"
line.long 0x14 "EDP_CORE_ENC1_RC_SCALE_P,RC Calculate Buffer Fullness and Offset. Scale value"
bitfld.long 0x14 0.--5. "INITIAL_SCALE_VALUE,Three fractional bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "EDP_CORE_ENC1_RC_SCALE_INC_DEC_P,RC Calculate Buffer Fullness and Offset. Increment and Decrement Scale values"
hexmask.long.word 0x18 16.--27. 1. "SCALE_DECREMENT_INTERVAL,RC scale decrement value"
hexmask.long.word 0x18 0.--15. 1. "SCALE_INCREMENT_INTERVAL,RC scale increment value"
line.long 0x1C "EDP_CORE_ENC1_RC_OFFSETS_1_P,RC Calculate Buffer Fullness and Offset. Various Offset control values 1"
bitfld.long 0x1C 0.--4. "FIRST_LINE_BPG_OFFSET,First Line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "EDP_CORE_ENC1_RC_OFFSETS_2_P,RC Calculate Buffer Fullness and Offset. Various Offset control values 2"
hexmask.long.word 0x20 16.--31. 1. "SLICE_BPG_OFFSET,Extra budget per group [11 fractional bits]"
hexmask.long.word 0x20 0.--15. 1. "NFL_BPG_OFFSET,Non First Line [11 fractional bits]"
line.long 0x24 "EDP_CORE_ENC1_RC_OFFSETS_3_P,RC Calculate Buffer Fullness and Offset. Various Offset control values 3"
hexmask.long.word 0x24 16.--31. 1. "FINAL_OFFSET,Final Offset"
hexmask.long.word 0x24 0.--15. 1. "INITIAL_OFFSET,Initial Offset"
line.long 0x28 "EDP_CORE_ENC1_FLATNESS_DETECTION_P,Flatness Signaling QP Override thresholds"
hexmask.long.byte 0x28 10.--17. 1. "FLATNESS_DET_THRESH,Flatness Detection Threshold as defined in PPS table of the DSC specification"
bitfld.long 0x28 5.--9. "FLATNESS_MAX_QP,Maximum threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x28 0.--4. "FLATNESS_MIN_QP,Minimum threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "EDP_CORE_ENC1_RC_MODEL_SIZE_P,RC Model Size"
hexmask.long.word 0x2C 0.--15. 1. "RC_MODEL_SIZE,RC Model Size"
line.long 0x30 "EDP_CORE_ENC1_RC_CONFIG_P,RC Model Various Config"
bitfld.long 0x30 24.--27. "RC_TGT_OFFSET_LO,RC Target offset low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 20.--23. "RC_TGT_OFFSET_HI,RC Target offset high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x30 13.--17. "RC_QUANT_INCR_LIMIT1,RC quantization increment limit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 8.--12. "RC_QUANT_INCR_LIMIT0,RC quantization increment limit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x30 0.--3. "RC_EDGE_FACTOR,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "EDP_CORE_ENC1_RC_BUF_THRESH_0_P,RC Model Buffer Thresholds 0"
hexmask.long.byte 0x34 24.--31. 1. "RC_BUF_THRESH_3,8 MSBs of the value"
hexmask.long.byte 0x34 16.--23. 1. "RC_BUF_THRESH_2,8 MSBs of the value"
newline
hexmask.long.byte 0x34 8.--15. 1. "RC_BUF_THRESH_1,8 MSBs of the value"
hexmask.long.byte 0x34 0.--7. 1. "RC_BUF_THRESH_0,8 MSBs of the value"
line.long 0x38 "EDP_CORE_ENC1_RC_BUF_THRESH_1_P,RC Model Buffer Thresholds 1"
hexmask.long.byte 0x38 24.--31. 1. "RC_BUF_THRESH_7,8 MSBs of the value"
hexmask.long.byte 0x38 16.--23. 1. "RC_BUF_THRESH_6,8 MSBs of the value"
newline
hexmask.long.byte 0x38 8.--15. 1. "RC_BUF_THRESH_5,8 MSBs of the value"
hexmask.long.byte 0x38 0.--7. 1. "RC_BUF_THRESH_4,8 MSBs of the value"
line.long 0x3C "EDP_CORE_ENC1_RC_BUF_THRESH_2_P,RC Model Buffer Thresholds 2"
hexmask.long.byte 0x3C 24.--31. 1. "RC_BUF_THRESH_11,8 MSBs of the value"
hexmask.long.byte 0x3C 16.--23. 1. "RC_BUF_THRESH_10,8 MSBs of the value"
newline
hexmask.long.byte 0x3C 8.--15. 1. "RC_BUF_THRESH_9,8 MSBs of the value"
hexmask.long.byte 0x3C 0.--7. 1. "RC_BUF_THRESH_8,8 MSBs of the value"
line.long 0x40 "EDP_CORE_ENC1_RC_BUF_THRESH_3_P,RC Model Buffer Thresholds 3"
hexmask.long.byte 0x40 8.--15. 1. "RC_BUF_THRESH_13,8 MSBs of the value"
hexmask.long.byte 0x40 0.--7. 1. "RC_BUF_THRESH_12,8 MSBs of the value"
line.long 0x44 "EDP_CORE_ENC1_RC_MIN_QP_0_P,RC Min QP 0"
bitfld.long 0x44 20.--24. "RANGE_MIN_QP_4,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 15.--19. "RANGE_MIN_QP_3,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x44 10.--14. "RANGE_MIN_QP_2,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 5.--9. "RANGE_MIN_QP_1,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x44 0.--4. "RANGE_MIN_QP_0,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x48 "EDP_CORE_ENC1_RC_MIN_QP_1_P,RC Min QP 1"
bitfld.long 0x48 20.--24. "RANGE_MIN_QP_9,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 15.--19. "RANGE_MIN_QP_8,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x48 10.--14. "RANGE_MIN_QP_7,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 5.--9. "RANGE_MIN_QP_6,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x48 0.--4. "RANGE_MIN_QP_5,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x4C "EDP_CORE_ENC1_RC_MIN_QP_2_P,RC Min QP 2"
bitfld.long 0x4C 20.--24. "RANGE_MIN_QP_14,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 15.--19. "RANGE_MIN_QP_13,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x4C 10.--14. "RANGE_MIN_QP_12,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 5.--9. "RANGE_MIN_QP_11,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x4C 0.--4. "RANGE_MIN_QP_10,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x50 "EDP_CORE_ENC1_RC_MAX_QP_0_P,RC Max QP 0"
bitfld.long 0x50 20.--24. "RANGE_MAX_QP_4,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 15.--19. "RANGE_MAX_QP_3,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x50 10.--14. "RANGE_MAX_QP_2,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 5.--9. "RANGE_MAX_QP_1,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x50 0.--4. "RANGE_MAX_QP_0,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x54 "EDP_CORE_ENC1_RC_MAX_QP_1_P,RC Max QP 1"
bitfld.long 0x54 20.--24. "RANGE_MAX_QP_9,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 15.--19. "RANGE_MAX_QP_8,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 10.--14. "RANGE_MAX_QP_7,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 5.--9. "RANGE_MAX_QP_6,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x54 0.--4. "RANGE_MAX_QP_5,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x58 "EDP_CORE_ENC1_RC_MAX_QP_2_P,RC Max QP 2"
bitfld.long 0x58 20.--24. "RANGE_MAX_QP_14,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 15.--19. "RANGE_MAX_QP_13,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x58 10.--14. "RANGE_MAX_QP_12,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 5.--9. "RANGE_MAX_QP_11,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x58 0.--4. "RANGE_MAX_QP_10,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x5C "EDP_CORE_ENC1_RC_RANGE_BPG_OFFSETS_0_P,RC Range bpg Offsets 0"
bitfld.long 0x5C 24.--29. "RANGE_BPG_OFFSET_4,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x5C 18.--23. "RANGE_BPG_OFFSET_3,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 12.--17. "RANGE_BPG_OFFSET_2,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x5C 6.--11. "RANGE_BPG_OFFSET_1,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 0.--5. "RANGE_BPG_OFFSET_0,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "EDP_CORE_ENC1_RC_RANGE_BPG_OFFSETS_1_P,RC Range bpg Offsets 1"
bitfld.long 0x60 24.--29. "RANGE_BPG_OFFSET_9,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x60 18.--23. "RANGE_BPG_OFFSET_8,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x60 12.--17. "RANGE_BPG_OFFSET_7,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x60 6.--11. "RANGE_BPG_OFFSET_6,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x60 0.--5. "RANGE_BPG_OFFSET_5,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x64 "EDP_CORE_ENC1_RC_RANGE_BPG_OFFSETS_2_P,RC Range bpg Offsets 2"
bitfld.long 0x64 24.--29. "RANGE_BPG_OFFSET_14,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x64 18.--23. "RANGE_BPG_OFFSET_13,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x64 12.--17. "RANGE_BPG_OFFSET_12,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x64 6.--11. "RANGE_BPG_OFFSET_11,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x64 0.--5. "RANGE_BPG_OFFSET_10,As per DSC specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x68 "EDP_CORE_ENC1_DPI_CTRL_OUT_DELAY_P,Delay applied to DPI input control signals to generate DPI output control signals"
hexmask.long.word 0x68 0.--15. 1. "DPI_CTRL_OUT_DELAY,Delay in number of encx clock cycles"
rgroup.long 0x30EC0++0x1B
line.long 0x00 "EDP_CORE_ENC1_GENERAL_STATUS_P,General Encoder Status"
bitfld.long 0x00 6. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] is full.For Debug purposes only" "0,1"
bitfld.long 0x00 5. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] is full.For Debug purposes only" "0,1"
newline
bitfld.long 0x00 4. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] is empty.For Debug purposes only" "0,1"
bitfld.long 0x00 3. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] is empty.For Debug purposes only" "0,1"
newline
bitfld.long 0x00 2. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x00 1. "FRAME_STARTED,Encoder is currently processing a frame" "0,1"
newline
bitfld.long 0x00 0. "CE,Flow control internal clock enable status.For Debug purposes only" "0,1"
line.long 0x04 "EDP_CORE_ENC1_HSLICE_STATUS_P,Hard Slice Encoded Status"
hexmask.long.word 0x04 16.--31. 1. "SLICE_COUNT_ENCODED,Actual slice number of current frame being processed at VLC encoder.Not re-synchronized in register clock domain"
hexmask.long.word 0x04 0.--15. 1. "SLICE_LINE_COUNT_ENCODED,Actual line number of current slice being processed at VLC encoder.Not re-synchronized in register clock domain"
line.long 0x08 "EDP_CORE_ENC1_OUT_STATUS_P,Outputted Slice Status"
hexmask.long.word 0x08 16.--31. 1. "SLICE_COUNT_OUT,Actual slice number of current frame being read at output interface.Not re-synchronized in register clock domain"
hexmask.long.word 0x08 0.--15. 1. "SLICE_LINE_COUNT_OUT,Actual line number of current slice being read at output interface.Not re-synchronized in register clock domain"
line.long 0x0C "EDP_CORE_ENC1_INT_STAT_P,Encoder Interrupt Status"
bitfld.long 0x0C 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1"
bitfld.long 0x0C 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1"
newline
bitfld.long 0x0C 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1"
bitfld.long 0x0C 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1"
newline
bitfld.long 0x0C 6. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x0C 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1"
newline
bitfld.long 0x0C 4. "CE,Flow control internal clock enable becomes high" "0,1"
bitfld.long 0x0C 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,output buffer 1 [soft slice 1] underflow" "0,1"
newline
bitfld.long 0x0C 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,output buffer 0 [soft slice 0] underflow" "0,1"
bitfld.long 0x0C 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 [soft slice 1] underflow" "0,1"
newline
bitfld.long 0x0C 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 [soft slice 0] underflow" "0,1"
line.long 0x10 "EDP_CORE_ENC1_INT_CLR_P,Encoder Interrupt Clear"
bitfld.long 0x10 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1"
bitfld.long 0x10 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1"
newline
bitfld.long 0x10 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1"
bitfld.long 0x10 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1"
newline
bitfld.long 0x10 6. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x10 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1"
newline
bitfld.long 0x10 4. "CE,Flow control internal clock enable" "0,1"
bitfld.long 0x10 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1"
newline
bitfld.long 0x10 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1"
bitfld.long 0x10 1. "ENC_UNDERFLOW_CONTEXT_1,output buffer 1 underflow" "0,1"
newline
bitfld.long 0x10 0. "ENC_UNDERFLOW_CONTEXT_0,output buffer 0 underflow" "0,1"
line.long 0x14 "EDP_CORE_ENC1_INT_MASK_P,Encoder Interrupt Mask"
bitfld.long 0x14 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full" "0,1"
bitfld.long 0x14 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full" "0,1"
newline
bitfld.long 0x14 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty" "0,1"
bitfld.long 0x14 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty" "0,1"
newline
bitfld.long 0x14 6. "FRAME_DONE,Encoder finished a frame" "0,1"
bitfld.long 0x14 5. "FRAME_STARTED,Encoder is started to process a frame" "0,1"
newline
bitfld.long 0x14 4. "CE,Flow control internal clock enable" "0,1"
bitfld.long 0x14 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow" "0,1"
newline
bitfld.long 0x14 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow" "0,1"
bitfld.long 0x14 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow" "0,1"
newline
bitfld.long 0x14 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow" "0,1"
line.long 0x18 "EDP_CORE_ENC1_INT_TEST_P,Encoder Interrupt Test"
bitfld.long 0x18 10. "OUT_BUFF_FULL_CONTEXT_1,Output buffer 1 [soft slice 1] became full test" "0,1"
bitfld.long 0x18 9. "OUT_BUFF_FULL_CONTEXT_0,Output buffer 0 [soft slice 0] became full test" "0,1"
newline
bitfld.long 0x18 8. "OUT_BUFF_EMPTY_CONTEXT_1,Output buffer 1 [soft slice 1] became empty test" "0,1"
bitfld.long 0x18 7. "OUT_BUFF_EMPTY_CONTEXT_0,Output buffer 0 [soft slice 0] became empty test" "0,1"
newline
bitfld.long 0x18 6. "FRAME_DONE,Encoder finished a frame test" "0,1"
bitfld.long 0x18 5. "FRAME_STARTED,Encoder is started to process a frame test" "0,1"
newline
bitfld.long 0x18 4. "CE,Flow control internal clock enable test" "0,1"
bitfld.long 0x18 3. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1,rc model buffer 1 overflow test" "0,1"
newline
bitfld.long 0x18 2. "RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0,rc model buffer 0 overflow test" "0,1"
bitfld.long 0x18 1. "ENC_UNDERFLOW_CONTEXT_1,enc underflow 1 underflow test" "0,1"
newline
bitfld.long 0x18 0. "ENC_UNDERFLOW_CONTEXT_0,enc underflow 0 underflow test" "0,1"
group.long 0x30F00++0x0F
line.long 0x00 "EDP_CORE_ENC_ASF_INT_STAT_P,Encoder ASF Interrupt Status"
rbitfld.long 0x00 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt" "0,1"
rbitfld.long 0x00 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt" "0,1"
rbitfld.long 0x00 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt" "0,1"
rbitfld.long 0x00 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt" "0,1"
bitfld.long 0x00 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt" "0,1"
newline
rbitfld.long 0x00 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt" "0,1"
line.long 0x04 "EDP_CORE_ENC_ASF_INT_MASK_P,Encoder ASF Interrupt Mask"
bitfld.long 0x04 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt" "0,1"
bitfld.long 0x04 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt" "0,1"
bitfld.long 0x04 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt" "0,1"
bitfld.long 0x04 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt" "0,1"
bitfld.long 0x04 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt" "0,1"
line.long 0x08 "EDP_CORE_ENC_ASF_INT_CLR_P,Encoder ASF Interrupt Clear"
bitfld.long 0x08 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt" "0,1"
bitfld.long 0x08 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt" "0,1"
bitfld.long 0x08 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt" "0,1"
bitfld.long 0x08 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt" "0,1"
bitfld.long 0x08 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt" "0,1"
line.long 0x0C "EDP_CORE_ENC_ASF_INT_TEST_P,Encoder ASF Interrupt Test"
bitfld.long 0x0C 8. "ASF_CSR_ERR,Configuration and status registers uncorrectable error interrupt test" "0,1"
bitfld.long 0x0C 7. "ENC1_SELF_CHK_ERR,Hard Slice 1 Encoder self-check uncorrectable error interrupt test" "0,1"
newline
bitfld.long 0x0C 6. "ENC1_OUT_CHK_ERR,Hard Slice 1 Encoder output checker uncorrectable error interrupt test" "0,1"
bitfld.long 0x0C 5. "ENC1_ASF_SRAM_UNCORR_ERR,Hard Slice 1 SRAM uncorrectable error interrupt test" "0,1"
newline
bitfld.long 0x0C 4. "ENC1_ASF_SRAM_CORR_ERR,Hard Slice 1 SRAM correctable error interrupt test" "0,1"
bitfld.long 0x0C 3. "ENC0_SELF_CHK_ERR,Hard Slice 0 Encoder self-check uncorrectable error interrupt test" "0,1"
newline
bitfld.long 0x0C 2. "ENC0_OUT_CHK_ERR,Hard Slice 0 Encoder output checker uncorrectable error interrupt test" "0,1"
bitfld.long 0x0C 1. "ENC0_ASF_SRAM_UNCORR_ERR,Hard Slice 0 SRAM uncorrectable error interrupt test" "0,1"
newline
bitfld.long 0x0C 0. "ENC0_ASF_SRAM_CORR_ERR,Hard Slice 0 SRAM correctable error interrupt test" "0,1"
rgroup.long 0x30F20++0x27
line.long 0x00 "EDP_CORE_ENC0_ASF_SRAM_CORR_P,Hard Slice 0 Status register for SRAM uncorrectable fault"
bitfld.long 0x00 24.--25. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "EDP_CORE_ENC0_ASF_SRAM_UNCORR_P,Hard Slice 0 Status register for SRAM uncorrectable fault"
bitfld.long 0x04 24.--25. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault" "0,1,2,3"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "EDP_CORE_ENC1_ASF_SRAM_CORR_P,Hard Slice 1 Status register for SRAM uncorrectable fault"
bitfld.long 0x08 24.--25. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault" "0,1,2,3"
hexmask.long.tbyte 0x08 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x0C "EDP_CORE_ENC1_ASF_SRAM_UNCORR_P,Hard Slice 1 Status register for SRAM uncorrectable fault"
bitfld.long 0x0C 24.--25. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault" "0,1,2,3"
hexmask.long.tbyte 0x0C 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x10 "EDP_CORE_ENC0_ASF_CSR_CHK_TEST_P,Hard Slice 0 Test for CSR protection expected CRC"
hexmask.long.word 0x10 0.--15. 1. "ENC0_ASF_CSR_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register"
line.long 0x14 "EDP_CORE_ENC1_ASF_CSR_CHK_TEST_P,Hard Slice 1 Test for CSR protection expected CRC"
hexmask.long.word 0x14 0.--15. 1. "ENC1_ASF_CSR_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register"
line.long 0x18 "EDP_CORE_ENC0_ASF_SELF_CHK_TEST_P,Hard Slice 0 Test for Self Check expected CRC"
hexmask.long.word 0x18 0.--15. 1. "ENC0_ASF_SELF_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register"
line.long 0x1C "EDP_CORE_ENC1_ASF_SELF_CHK_TEST_P,Hard Slice 1 Test for Self Check expected CRC"
hexmask.long.word 0x1C 0.--15. 1. "ENC1_ASF_SELF_CHK_TEST,Each bit of the expected CRC can be corrupted separately [one bit at a time] using this register"
line.long 0x20 "EDP_CORE_ENC0_ASF_OUT_CHK_TEST_P,Hard Slice 0 Test for Output Checker"
bitfld.long 0x20 8. "END_FRAME_OUT_STUCK1_ERR," "0,1"
bitfld.long 0x20 7. "END_LINE_OUT_STUCK1_ERR," "0,1"
newline
bitfld.long 0x20 6. "END_CHUNK_STUCK1_ERR," "0,1"
bitfld.long 0x20 5. "VALID_OUT_STUCK1_ERR," "0,1"
newline
bitfld.long 0x20 4. "DATA_OUT_STUCK1_ERR," "0,1"
bitfld.long 0x20 3. "VALID_STUCK0_ERR," "0,1"
newline
bitfld.long 0x20 2. "NVB_VALUE_ERR," "0,1"
bitfld.long 0x20 1. "LINE_CNT_ERR," "0,1"
newline
bitfld.long 0x20 0. "BYTE_CNT_ERR," "0,1"
line.long 0x24 "EDP_CORE_ENC1_ASF_OUT_CHK_TEST_P,Hard Slice 1 Test for Output Checker"
bitfld.long 0x24 8. "END_FRAME_OUT_STUCK1_ERR," "0,1"
bitfld.long 0x24 7. "END_LINE_OUT_STUCK1_ERR," "0,1"
newline
bitfld.long 0x24 6. "END_CHUNK_STUCK1_ERR," "0,1"
bitfld.long 0x24 5. "VALID_OUT_STUCK1_ERR," "0,1"
newline
bitfld.long 0x24 4. "DATA_OUT_STUCK1_ERR," "0,1"
bitfld.long 0x24 3. "VALID_STUCK0_ERR," "0,1"
newline
bitfld.long 0x24 2. "NVB_VALUE_ERR," "0,1"
bitfld.long 0x24 1. "LINE_CNT_ERR," "0,1"
newline
bitfld.long 0x24 0. "BYTE_CNT_ERR," "0,1"
tree.end
tree.end
tree "EDP_CORE_SAPB"
tree "DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB"
base ad:0x4F48000
group.long 0x00++0x53
line.long 0x00 "EDP_CORE_APB_CTRL_S,APB control register (SAPB)"
bitfld.long 0x00 3. "APB_XT_RUNSTALL,Not used" "0,1"
bitfld.long 0x00 2. "APB_IRAM_PATH,Not used" "0,1"
bitfld.long 0x00 1. "APB_DRAM_PATH,Not used" "0,1"
bitfld.long 0x00 0. "APB_XT_RESET,Not used" "0,1"
line.long 0x04 "EDP_CORE_XT_INT_CTRL_S,Internal CPU Interrupt Polarity Control Register"
bitfld.long 0x04 0.--1. "XT_INT_POLARITY,Not used" "0,1,2,3"
line.long 0x08 "EDP_CORE_MAILBOX_FULL_ADDR_S,Mailbox full indication status register"
bitfld.long 0x08 0. "MAILBOX_FULL,Mailbox full indication" "0,1"
line.long 0x0C "EDP_CORE_MAILBOX_EMPTY_ADDR_S,Mailbox empty indication status register"
bitfld.long 0x0C 0. "MAILBOX_EMPTY,Mailbox Empty indication" "0,1"
line.long 0x10 "EDP_CORE_MAILBOX0_WR_DATA_S,Mailbox write data register"
hexmask.long.byte 0x10 0.--7. 1. "MAILBOX0_WR_DATA,Mailbox write Data"
line.long 0x14 "EDP_CORE_MAILBOX0_RD_DATA_S,Mailbox Read data register"
hexmask.long.byte 0x14 0.--7. 1. "MAILBOX0_RD_DATA,Mailbox Read data"
line.long 0x18 "EDP_CORE_KEEP_ALIVE_S,Software keep alive counter"
hexmask.long.byte 0x18 0.--7. 1. "KEEP_ALIVE_CNT,Software keep alive counter"
line.long 0x1C "EDP_CORE_VER_l_S,Software Version Register"
hexmask.long.byte 0x1C 0.--7. 1. "VER_LSB,Software Version lower byte"
line.long 0x20 "EDP_CORE_VER_H_S,Software Version Register"
hexmask.long.byte 0x20 0.--7. 1. "VER_MSB,Software Version higher byte"
line.long 0x24 "EDP_CORE_VER_LIB_L_ADDR_S,Software Library Version Register"
hexmask.long.byte 0x24 0.--7. 1. "SW_LIB_VER_L,Software Library Version lower byte"
line.long 0x28 "EDP_CORE_VER_LIB_H_ADDR_S,Software Library Version Register"
hexmask.long.byte 0x28 0.--7. 1. "SW_LIB_VER_H,Software Library Version higher byte"
line.long 0x2C "EDP_CORE_SW_DEBUG_l_S,Software/Firmware Debug Register"
hexmask.long.byte 0x2C 0.--7. 1. "SW_DEBUG_7_0,Register used for debug purposes [lower byte]"
line.long 0x30 "EDP_CORE_SW_DEBUG_H_S,Software/Firmware Debug Register"
hexmask.long.byte 0x30 0.--7. 1. "SW_DEBUG_15_8,Register used for debug purposes [higher byte]"
line.long 0x34 "EDP_CORE_MAILBOX_INT_MASK_S,Mailbox Interrupt mask register"
bitfld.long 0x34 1. "MAILBOX_FULL_INT_MASK,Mailbox Full Interrupt mask" "0,1"
bitfld.long 0x34 0. "MAILBOX_EMPTY_INT_MASK,Mailbox Not-empty Interrupt mask" "0,1"
line.long 0x38 "EDP_CORE_MAILBOX_INT_STATUS_S,Mailbox Interrupt Status register"
bitfld.long 0x38 1. "MAILBOX_FULL_INT_STATUS,Mailbox full interrupt" "0,1"
bitfld.long 0x38 0. "MAILBOX_EMPTY_INT_STATUS,Mailbox not-empty interrupt" "0,1"
line.long 0x3C "EDP_CORE_SW_CLK_l_S,Core Clock frequency"
hexmask.long.byte 0x3C 0.--7. 1. "SW_CLOCK_VAL_L,Not used"
line.long 0x40 "EDP_CORE_SW_CLK_H_S,Core Clock frequency"
hexmask.long.byte 0x40 0.--7. 1. "SW_CLOCK_VAL_H,Not used"
line.long 0x44 "EDP_CORE_SW_EVENTS0_S,Not used"
hexmask.long.byte 0x44 0.--7. 1. "SW_EVENTS7_0,Not used"
line.long 0x48 "EDP_CORE_SW_EVENTS1_S,Not used"
hexmask.long.byte 0x48 0.--7. 1. "SW_EVENTS15_8,Not used"
line.long 0x4C "EDP_CORE_SW_EVENTS2_S,Not used"
hexmask.long.byte 0x4C 0.--7. 1. "SW_EVENTS23_16,Not used"
line.long 0x50 "EDP_CORE_SW_EVENTS3_S,Not used"
hexmask.long.byte 0x50 0.--7. 1. "SW_EVENTS31_24,Not used"
group.long 0x60++0x07
line.long 0x00 "EDP_CORE_XT_OCD_CTRL_S,Internal CPU - On Chip Debug (OCD) Ctrl Register"
bitfld.long 0x00 1. "XT_OCDHALTONRESET,Not used" "0,1"
bitfld.long 0x00 0. "XT_DRESET,Not used" "0,1"
line.long 0x04 "EDP_CORE_XT_OCD_CTRL_RO_S,Internal CPU - OCD R0 mode configuration"
bitfld.long 0x04 0. "XT_XOCDMODE,Internal CPU - OCD mode configuration" "0,1"
group.long 0x6C++0x07
line.long 0x00 "EDP_CORE_APB_INT_MASK_S,APB Interrupt Mask Register"
bitfld.long 0x00 1. "APB_SW_INTR_MASK,Not used" "0,1"
bitfld.long 0x00 0. "APB_MAILBOX_INTR_MASK,Mailbox Interrupt mask" "0,1"
line.long 0x04 "EDP_CORE_APB_STATUS_S,APB interrupt status register"
bitfld.long 0x04 1. "APB_SW_INTR_STATUS,Not used" "0,1"
bitfld.long 0x04 0. "APB_MAILBOX_INTR_STATUS,Mailbox Interrupt status" "0,1"
tree.end
tree.end
tree "EDP_ECC_CORE"
tree "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG"
base ad:0x2AC0000
rgroup.long 0x00++0x03
line.long 0x00 "EDP_ECC_CORE_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "EDP_ECC_CORE_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "EDP_ECC_CORE_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "EDP_ECC_CORE_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "EDP_ECC_CORE_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "EDP_ECC_CORE_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 2. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "RAMECC_DRAM_PEND,Interrupt Pending Status for ramecc_dram_pend" "0,1"
bitfld.long 0x04 0. "RAMECC_IRAM_PEND,Interrupt Pending Status for ramecc_iram_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "EDP_ECC_CORE_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "RAMECC_DRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_dram_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_IRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_iram_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "EDP_ECC_CORE_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "RAMECC_DRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_dram_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_iram_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "EDP_ECC_CORE_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "EDP_ECC_CORE_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 2. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
bitfld.long 0x04 1. "RAMECC_DRAM_PEND,Interrupt Pending Status for ramecc_dram_pend" "0,1"
bitfld.long 0x04 0. "RAMECC_IRAM_PEND,Interrupt Pending Status for ramecc_iram_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "EDP_ECC_CORE_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "RAMECC_DRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_dram_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_IRAM_ENABLE_SET,Interrupt Enable Set Register for ramecc_iram_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "EDP_ECC_CORE_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
bitfld.long 0x00 1. "RAMECC_DRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_dram_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_iram_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "EDP_ECC_CORE_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "EDP_ECC_CORE_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "EDP_ECC_CORE_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "EDP_ECC_CORE_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "EDP_ECC_DSC"
tree "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG"
base ad:0x2AC2000
rgroup.long 0x00++0x03
line.long 0x00 "EDP_ECC_DSC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "EDP_ECC_DSC_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "EDP_ECC_DSC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "EDP_ECC_DSC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "EDP_ECC_DSC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "EDP_ECC_DSC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 7. "RAMECC_ENC1_OB0_PEND,Interrupt Pending Status for ramecc_enc1_ob0_pend" "0,1"
bitfld.long 0x04 6. "RAMECC_ENC1_SSM_D_PEND,Interrupt Pending Status for ramecc_enc1_ssm_d_pend" "0,1"
bitfld.long 0x04 5. "RAMECC_ENC1_SSM_S_PEND,Interrupt Pending Status for ramecc_enc1_ssm_s_pend" "0,1"
newline
bitfld.long 0x04 4. "RAMECC_ENC1_LB_PEND,Interrupt Pending Status for ramecc_enc1_lb_pend" "0,1"
bitfld.long 0x04 3. "RAMECC_ENC0_OB0_PEND,Interrupt Pending Status for ramecc_enc0_ob0_pend" "0,1"
bitfld.long 0x04 2. "RAMECC_ENC0_SSM_D_PEND,Interrupt Pending Status for ramecc_enc0_ssm_d_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC_ENC0_SSM_S_PEND,Interrupt Pending Status for ramecc_enc0_ssm_s_pend" "0,1"
bitfld.long 0x04 0. "RAMECC_ENC0_LB_PEND,Interrupt Pending Status for ramecc_enc0_lb_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "EDP_ECC_DSC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "RAMECC_ENC1_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ob0_pend" "0,1"
bitfld.long 0x00 6. "RAMECC_ENC1_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_d_pend" "0,1"
bitfld.long 0x00 5. "RAMECC_ENC1_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_s_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC_ENC1_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_lb_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_ENC0_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ob0_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_ENC0_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_d_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_ENC0_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_s_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_ENC0_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_lb_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "EDP_ECC_DSC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "RAMECC_ENC1_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ob0_pend" "0,1"
bitfld.long 0x00 6. "RAMECC_ENC1_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_d_pend" "0,1"
bitfld.long 0x00 5. "RAMECC_ENC1_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_s_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC_ENC1_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_lb_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_ENC0_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ob0_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_ENC0_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_d_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_ENC0_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_s_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_ENC0_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_lb_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "EDP_ECC_DSC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "EDP_ECC_DSC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 7. "RAMECC_ENC1_OB0_PEND,Interrupt Pending Status for ramecc_enc1_ob0_pend" "0,1"
bitfld.long 0x04 6. "RAMECC_ENC1_SSM_D_PEND,Interrupt Pending Status for ramecc_enc1_ssm_d_pend" "0,1"
bitfld.long 0x04 5. "RAMECC_ENC1_SSM_S_PEND,Interrupt Pending Status for ramecc_enc1_ssm_s_pend" "0,1"
newline
bitfld.long 0x04 4. "RAMECC_ENC1_LB_PEND,Interrupt Pending Status for ramecc_enc1_lb_pend" "0,1"
bitfld.long 0x04 3. "RAMECC_ENC0_OB0_PEND,Interrupt Pending Status for ramecc_enc0_ob0_pend" "0,1"
bitfld.long 0x04 2. "RAMECC_ENC0_SSM_D_PEND,Interrupt Pending Status for ramecc_enc0_ssm_d_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC_ENC0_SSM_S_PEND,Interrupt Pending Status for ramecc_enc0_ssm_s_pend" "0,1"
bitfld.long 0x04 0. "RAMECC_ENC0_LB_PEND,Interrupt Pending Status for ramecc_enc0_lb_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "EDP_ECC_DSC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "RAMECC_ENC1_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ob0_pend" "0,1"
bitfld.long 0x00 6. "RAMECC_ENC1_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_d_pend" "0,1"
bitfld.long 0x00 5. "RAMECC_ENC1_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_ssm_s_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC_ENC1_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc1_lb_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_ENC0_OB0_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ob0_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_ENC0_SSM_D_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_d_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_ENC0_SSM_S_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_ssm_s_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_ENC0_LB_ENABLE_SET,Interrupt Enable Set Register for ramecc_enc0_lb_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "EDP_ECC_DSC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "RAMECC_ENC1_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ob0_pend" "0,1"
bitfld.long 0x00 6. "RAMECC_ENC1_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_d_pend" "0,1"
bitfld.long 0x00 5. "RAMECC_ENC1_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_ssm_s_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC_ENC1_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc1_lb_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_ENC0_OB0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ob0_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_ENC0_SSM_D_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_d_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_ENC0_SSM_S_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_ssm_s_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_ENC0_LB_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_enc0_lb_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "EDP_ECC_DSC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "EDP_ECC_DSC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "EDP_ECC_DSC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "EDP_ECC_DSC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "EDP_ECC_PHY"
tree "DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG"
base ad:0x2AC1000
rgroup.long 0x00++0x03
line.long 0x00 "EDP_ECC_PHY_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "EDP_ECC_PHY_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "EDP_ECC_PHY_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "EDP_ECC_PHY_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "EDP_ECC_PHY_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "EDP_ECC_PHY_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 4. "RAMECC_AIF_MEM_PEND,Interrupt Pending Status for ramecc_aif_mem_pend" "0,1"
bitfld.long 0x04 3. "RAMECC_PKT_MEM_3_PEND,Interrupt Pending Status for ramecc_pkt_mem_3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC_PKT_MEM_2_PEND,Interrupt Pending Status for ramecc_pkt_mem_2_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC_PKT_MEM_1_PEND,Interrupt Pending Status for ramecc_pkt_mem_1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC_PKT_MEM_0_PEND,Interrupt Pending Status for ramecc_pkt_mem_0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "EDP_ECC_PHY_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 4. "RAMECC_AIF_MEM_ENABLE_SET,Interrupt Enable Set Register for ramecc_aif_mem_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_PKT_MEM_3_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_PKT_MEM_2_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_PKT_MEM_1_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_PKT_MEM_0_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "EDP_ECC_PHY_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 4. "RAMECC_AIF_MEM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_aif_mem_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_PKT_MEM_3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_PKT_MEM_2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_PKT_MEM_1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_PKT_MEM_0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "EDP_ECC_PHY_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "EDP_ECC_PHY_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 4. "RAMECC_AIF_MEM_PEND,Interrupt Pending Status for ramecc_aif_mem_pend" "0,1"
bitfld.long 0x04 3. "RAMECC_PKT_MEM_3_PEND,Interrupt Pending Status for ramecc_pkt_mem_3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC_PKT_MEM_2_PEND,Interrupt Pending Status for ramecc_pkt_mem_2_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC_PKT_MEM_1_PEND,Interrupt Pending Status for ramecc_pkt_mem_1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC_PKT_MEM_0_PEND,Interrupt Pending Status for ramecc_pkt_mem_0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "EDP_ECC_PHY_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 4. "RAMECC_AIF_MEM_ENABLE_SET,Interrupt Enable Set Register for ramecc_aif_mem_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_PKT_MEM_3_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_PKT_MEM_2_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_PKT_MEM_1_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_PKT_MEM_0_ENABLE_SET,Interrupt Enable Set Register for ramecc_pkt_mem_0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "EDP_ECC_PHY_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 4. "RAMECC_AIF_MEM_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_aif_mem_pend" "0,1"
bitfld.long 0x00 3. "RAMECC_PKT_MEM_3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC_PKT_MEM_2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC_PKT_MEM_1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC_PKT_MEM_0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pkt_mem_0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "EDP_ECC_PHY_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "EDP_ECC_PHY_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "EDP_ECC_PHY_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "EDP_ECC_PHY_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "ELM"
tree "ELM0"
base ad:0x5380000
rgroup.long 0x00++0x03
line.long 0x00 "ELM_REVISION,This register contains the IP revision code"
group.long 0x10++0x13
line.long 0x00 "ELM_SYSCONFIG,This register controls ELM local power management and software reset"
bitfld.long 0x00 8. "CLOCKACTIVITYOCP,ELM_FICLK activity when module is in IDLE mode 0h (R/W) = ELM_FICLK can be switched off" "CLOCKACTIVITYOCP_0,CLOCKACTIVITYOCP_1"
bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (clock stop req/ack control) 0h (R/W) = Force-idle" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
bitfld.long 0x00 1. "SOFTRESET,Module software reset 0h (R/W) = Normal mode 1h (R/W) = Start soft reset sequence" "SOFTRESET_0,SOFTRESET_1"
newline
bitfld.long 0x00 0. "AUTOGATING,Internal ELM_FICLK gating strategy 0h (R/W) = ELM_FICLK is free-running" "AUTOGATING_0,AUTOGATING_1"
line.long 0x04 "ELM_SYSSTATUS,Internal reset monitoring Undefined since: From hardware perspective. the reset state is 0"
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring 0h (R) = Reset is ongoing" "RESETDONE_0,RESETDONE_1"
line.long 0x08 "ELM_IRQSTATUS,Interrupt status"
bitfld.long 0x08 8. "PAGE_VALID,Error-location status for a full page based on the mask definition" "PAGE_VALID_0,PAGE_VALID_1"
bitfld.long 0x08 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "LOC_VALID_7_0,LOC_VALID_7_1"
bitfld.long 0x08 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "LOC_VALID_6_0,LOC_VALID_6_1"
newline
bitfld.long 0x08 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "LOC_VALID_5_0,LOC_VALID_5_1"
bitfld.long 0x08 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "LOC_VALID_4_0,LOC_VALID_4_1"
bitfld.long 0x08 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "LOC_VALID_3_0,LOC_VALID_3_1"
newline
bitfld.long 0x08 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "LOC_VALID_2_0,LOC_VALID_2_1"
bitfld.long 0x08 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "LOC_VALID_1_0,LOC_VALID_1_1"
bitfld.long 0x08 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "LOC_VALID_0_0,LOC_VALID_0_1"
line.long 0x0C "ELM_IRQENABLE,Interrupt enable"
bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "PAGE_MASK_0,PAGE_MASK_1"
bitfld.long 0x0C 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "LOCATION_MASK_7_0,LOCATION_MASK_7_1"
bitfld.long 0x0C 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "LOCATION_MASK_6_0,LOCATION_MASK_6_1"
newline
bitfld.long 0x0C 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "LOCATION_MASK_5_0,LOCATION_MASK_5_1"
bitfld.long 0x0C 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "LOCATION_MASK_4_0,LOCATION_MASK_4_1"
bitfld.long 0x0C 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "LOCATION_MASK_3_0,LOCATION_MASK_3_1"
newline
bitfld.long 0x0C 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "LOCATION_MASK_2_0,LOCATION_MASK_2_1"
bitfld.long 0x0C 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "LOCATION_MASK_1_0,LOCATION_MASK_1_1"
bitfld.long 0x0C 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "LOCATION_MASK_0_0,LOCATION_MASK_0_1"
line.long 0x10 "ELM_LOCATION_CONFIG,ECC algorithm parameters"
hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)"
bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "ECC_BCH_LEVEL_0,ECC_BCH_LEVEL_1,ECC_BCH_LEVEL_2,ECC_BCH_LEVEL_3"
group.long 0x80++0x03
line.long 0x00 "ELM_PAGE_CTRL,Page definition"
bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode" "SECTOR_7_0,SECTOR_7_1"
bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode" "SECTOR_6_0,SECTOR_6_1"
bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode" "SECTOR_5_0,SECTOR_5_1"
newline
bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode" "SECTOR_4_0,SECTOR_4_1"
bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode" "SECTOR_3_0,SECTOR_3_1"
bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode" "SECTOR_2_0,SECTOR_2_1"
newline
bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode" "SECTOR_1_0,SECTOR_1_1"
bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode" "SECTOR_0_0,SECTOR_0_1"
group.long 0x400++0x1B
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i,Input syndrome polynomial bits 64 to 95"
line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "0,1"
hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207"
rgroup.long 0x800++0x03
line.long 0x00 "ELM_LOCATION_STATUS_i,Exit status for the syndrome polynomial processing"
bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "0,1"
bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x880++0x3F
line.long 0x00 "ELM_ERROR_LOCATION_0_i,Error-location register 0"
hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_i,Error-location register 1"
hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_i,Error-location register 2"
hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x0C "ELM_ERROR_LOCATION_3_i,Error-location register 3"
hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_i,Error-location register 4"
hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_i,Error-location register 5"
hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_i,Error-location register 6"
hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x1C "ELM_ERROR_LOCATION_7_i,Error-location register 7"
hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_i,Error-location register 8"
hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_i,Error-location register 9"
hexmask.long.word 0x24 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_i,Error-location register 10"
hexmask.long.word 0x28 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x2C "ELM_ERROR_LOCATION_11_i,Error-location register 11"
hexmask.long.word 0x2C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_i,Error-location register 12"
hexmask.long.word 0x30 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_i,Error-location register 13"
hexmask.long.word 0x34 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_i,Error-location register 14"
hexmask.long.word 0x38 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
line.long 0x3C "ELM_ERROR_LOCATION_15_i,Error-location register 15"
hexmask.long.word 0x3C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address"
tree.end
tree.end
tree "ENCODER"
tree "ENCODER0_REG_AXI"
base ad:0x4205000
group.long 0x04++0x03
line.long 0x00 "ENCODER0_AXI_EXACCESS,"
bitfld.long 0x00 0. "ENABLE,enable the exclusive access logic in the module img2_axi2img.vhd" "0,1"
tree.end
tree.end
tree "EPWM"
repeat 6. (increment 0 1) (increment ad:0x3000000 0x10000)
tree "EHRPWM$1_EPWM"
base $2
group.word 0x00++0x0B
line.word 0x00 "EPWM_TBCTL,"
bitfld.word 0x00 14.--15. "FREE_SOFT," "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR," "0,1"
newline
bitfld.word 0x00 10.--12. "CLKDIV," "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV," "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x00 6. "SWFSYNC," "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL," "0,1,2,3"
newline
bitfld.word 0x00 3. "PRDLD," "0,1"
bitfld.word 0x00 2. "PHSEN," "0,1"
newline
bitfld.word 0x00 0.--1. "CTRMODE," "0,1,2,3"
line.word 0x02 "EPWM_TBSTS,"
bitfld.word 0x02 2. "CTRMAX," "0,1"
bitfld.word 0x02 1. "SYNCI," "0,1"
newline
rbitfld.word 0x02 0. "CTRDIR," "0,1"
line.word 0x04 "HRPWM_TBPHSHR,"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_TBPHS,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved"
line.word 0x08 "EPWM_TBCNT,"
line.word 0x0A "EPWM_TBPRD,"
group.word 0x0E++0x17
line.word 0x00 "EPWM_CMPCTL,"
rbitfld.word 0x00 9. "SHDWBFULL," "0,1"
rbitfld.word 0x00 8. "SHDWAFULL," "0,1"
newline
bitfld.word 0x00 6. "SHDWBMODE," "0,1"
bitfld.word 0x00 4. "SHDWAMODE," "0,1"
newline
bitfld.word 0x00 2.--3. "LOADBMODE," "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE," "0,1,2,3"
line.word 0x02 "HRPWM_CMPAHR,This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,"
line.word 0x04 "EPWM_CMPA,"
line.word 0x06 "EPWM_CMPB,"
line.word 0x08 "EPWM_AQCTLA,"
bitfld.word 0x08 10.--11. "CBD," "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU," "0,1,2,3"
newline
bitfld.word 0x08 6.--7. "CAD," "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU," "0,1,2,3"
newline
bitfld.word 0x08 2.--3. "PRD," "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO," "0,1,2,3"
line.word 0x0A "EPWM_AQCTLB,"
bitfld.word 0x0A 10.--11. "CBD," "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU," "0,1,2,3"
newline
bitfld.word 0x0A 6.--7. "CAD," "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU," "0,1,2,3"
newline
bitfld.word 0x0A 2.--3. "PRD," "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO," "0,1,2,3"
line.word 0x0C "EPWM_AQSFRC,"
bitfld.word 0x0C 6.--7. "RLDCSF," "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB," "0,1"
newline
bitfld.word 0x0C 3.--4. "ACTSFB," "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA," "0,1"
newline
bitfld.word 0x0C 0.--1. "ACTSFA," "0,1,2,3"
line.word 0x0E "EPWM_AQCSFRC,"
bitfld.word 0x0E 2.--3. "CSFB," "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA," "0,1,2,3"
line.word 0x10 "EPWM_DBCTL,"
bitfld.word 0x10 4.--5. "IN_MODE," "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL," "0,1,2,3"
newline
bitfld.word 0x10 0.--1. "OUT_MODE," "0,1,2,3"
line.word 0x12 "EPWM_DBRED,"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count"
line.word 0x14 "EPWM_DBFED,"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count"
line.word 0x16 "EPWM_TZSEL,"
bitfld.word 0x16 13. "OSHT6," "0,1"
bitfld.word 0x16 12. "OSHT5," "0,1"
newline
bitfld.word 0x16 11. "OSHT4," "0,1"
bitfld.word 0x16 10. "OSHT3," "0,1"
newline
bitfld.word 0x16 9. "OSHT2," "0,1"
bitfld.word 0x16 8. "OSHT1," "0,1"
newline
bitfld.word 0x16 5. "CBC5," "0,1"
bitfld.word 0x16 4. "CBC4," "0,1"
newline
bitfld.word 0x16 3. "CBC3," "0,1"
bitfld.word 0x16 2. "CBC2," "0,1"
newline
bitfld.word 0x16 1. "CBC1," "0,1"
bitfld.word 0x16 0. "CBC0," "0,1"
group.word 0x28++0x15
line.word 0x00 "EPWM_TZCTL,"
bitfld.word 0x00 2.--3. "TZB," "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA," "0,1,2,3"
line.word 0x02 "EPWM_TZEINT,"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation"
line.word 0x04 "EPWM_TZFLG,"
bitfld.word 0x04 2. "OST," "0,1"
bitfld.word 0x04 1. "CBC," "0,1"
newline
bitfld.word 0x04 0. "INT," "0,1"
line.word 0x06 "EPWM_TZCLR,"
bitfld.word 0x06 2. "OST," "0,1"
bitfld.word 0x06 1. "CBC," "0,1"
newline
bitfld.word 0x06 0. "INT," "0,1"
line.word 0x08 "EPWM_TZFRC,"
bitfld.word 0x08 2. "OST," "0,1"
bitfld.word 0x08 1. "CBC," "0,1"
line.word 0x0A "EPWM_ETSEL,"
bitfld.word 0x0A 15. "SOCB,Enable SOCB pulse when set to 1" "0,1"
bitfld.word 0x0A 12.--14. "SOCBSEL,EPWMxSOCB Selection Options" "Reserved,Enable event time-base counter equal to zero..,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPB..,Enable event time-base counter equal to CMPB.."
newline
bitfld.word 0x0A 11. "SOCA,Enable SOCA pulse when set to 1" "0,1"
bitfld.word 0x0A 8.--10. "SOCASEL,EPWMxSOCA Selection Options" "Reserved,Enable event time-base counter equal to zero..,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPB..,Enable event time-base counter equal to CMPB.."
newline
bitfld.word 0x0A 3. "INTEN," "0,1"
bitfld.word 0x0A 0.--2. "INTSEL," "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_ETPS,"
bitfld.word 0x0C 14.--15. "SOCBCNT,EPWMxSOCB Counter Register: These bits indicate how many selected events have occurred" "No events,1 events,2 events,3 event"
bitfld.word 0x0C 12.--13. "SOCBPRD,EPWMxSOCB Period Select: These bits select how many selected event need to occur before an SOCB pulse is generated" "Disable counter,Generate pulse on SOCBCNT = 1 (1st event),Generate pulse on SOCBCNT = 2 (2nd event),Generate pulse on SOCBCNT = 3 (3rd event)"
newline
bitfld.word 0x0C 10.--11. "SOCACNT,EPWMxSOCA Counter Register: These bits indicate how many selected events have occurred" "No events,1 events,2 events,3 events"
bitfld.word 0x0C 8.--9. "SOCAPRD,EPWMxSOCA Period Select: These bits select how many selected event need to occur before an SOCA pulse is generated" "Disable counter,Generate pulse on SOCACNT = 1 (1st event),Generate pulse on SOCACNT = 2 (2nd event),Generate pulse on SOCACNT = 3 (3rd event)"
newline
rbitfld.word 0x0C 2.--3. "INTCNT," "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD," "0,1,2,3"
line.word 0x0E "EPWM_ETFLG,"
bitfld.word 0x0E 3. "SOCB,Latched SOCB Flag Bit Status" "Indicates no event occurred,Indicates that a start of conversion pulse was.."
bitfld.word 0x0E 2. "SOCA,Latched SOCA Flag Bit Status" "Indicates no event occurred,Indicates that a start of conversion pulse was.."
newline
bitfld.word 0x0E 0. "INT," "0,1"
line.word 0x10 "EPWM_ETCLR,"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_ETFRC,"
bitfld.word 0x12 3. "SOCB,SOCB Flag Clear Bit" "Writing a 0 has no effect,Writing a 1 clears the EPWM_ETFLG[3] SOCB flag bit"
bitfld.word 0x12 2. "SOCA,SOCA Flag Clear Bit" "Writing a 0 has no effect,Writing a 1 clears the EPWM_ETFLG[2] SOCA flag bit"
newline
bitfld.word 0x12 0. "INT," "0,1"
line.word 0x14 "EPWM_PCCTL,"
bitfld.word 0x14 8.--10. "CHPDUTY," "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ," "0,1,2,3,4,5,6,7"
newline
bitfld.word 0x14 1.--4. "OSHTWTH," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN," "0,1"
group.word 0x40++0x01
line.word 0x00 "HRPWM_HRCTL,This register is only available on EPWM instances that include the high-resolution PWM (HRPWM) extension"
bitfld.word 0x00 3. "PULSESEL," "0,1"
bitfld.word 0x00 2. "DELBUSSEL," "0,1"
newline
bitfld.word 0x00 0.--1. "DELMODE,Edge Mode Bits" "0,1,2,3"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_PID,The IP revision register is used by software to track features. bugs. and compatibility"
tree.end
repeat.end
tree.end
tree "EQEP"
repeat 3. (list 0. 1. 2. )(list ad:0x3200000 ad:0x3210000 ad:0x3220000 )
tree "EQEP$1"
base $2
group.long 0x00++0x43
line.long 0x00 "EQEP_QPOSCNT,QEP Position Counter"
line.long 0x04 "EQEP_QPOSINIT,Position Counter Initialization Register"
line.long 0x08 "EQEP_QPOSMAX,Maximum Position Count Register"
line.long 0x0C "EQEP_QPOSCMP,Position Compare Register"
line.long 0x10 "EQEP_QPOSILAT,Index Position Latch Register"
line.long 0x14 "EQEP_QPOSSLAT,Strobe Position Latch Register"
line.long 0x18 "EQEP_QPOSLAT,QEP Position Counter Latch"
line.long 0x1C "EQEP_QUTMR,QEP Unit Timer"
line.long 0x20 "EQEP_QUPRD,QEP Unit Period Register"
line.long 0x24 "EQEP_QWD_TMR_PRD,QEP Watchdog Timer and Period Register"
hexmask.long.word 0x24 16.--31. 1. "QWDPRD,This field contains the time-out count for the QEP peripheral watch dog timer"
hexmask.long.word 0x24 0.--15. 1. "QWDTMR,This field acts as time base for watch dog to detect stalls"
line.long 0x28 "EQEP_QDEC_QEP_CTL,Quadrature Decoder and QEP Control Register"
bitfld.long 0x28 30.--31. "FREE_SOFT,POSCNT Behavior" "0,1,2,3"
bitfld.long 0x28 28.--29. "PCRM,Position Counter Reset mode" "0,1,2,3"
bitfld.long 0x28 26.--27. "SEI,Strobe Event Initialization of Position Counter" "0,1,2,3"
bitfld.long 0x28 24.--25. "IEI,Index Event Initialization of Position Counter" "0,1,2,3"
bitfld.long 0x28 23. "SWI,Software Initialization of Position Counter" "0,1"
bitfld.long 0x28 22. "SEL,Strobe Event Latch of Position Counter" "0,1"
bitfld.long 0x28 20.--21. "IEL,Index Event Latch of Position Counter (Software Index Marker)" "0,1,2,3"
bitfld.long 0x28 19. "QPEN,Quadrature Position counter Enable/Software Reset" "0,1"
bitfld.long 0x28 18. "QCLM,EQEP Capture Latch mode" "0,1"
newline
bitfld.long 0x28 17. "UTE,QEP Unit Timer Enable" "0,1"
bitfld.long 0x28 16. "WDE,QEP Watchdog Enable" "0,1"
bitfld.long 0x28 14.--15. "QSRC,Position Counter Source selection" "0,1,2,3"
bitfld.long 0x28 13. "SOEN,Enable Position Compare Sync Output" "0,1"
bitfld.long 0x28 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.long 0x28 11. "XCR,External Clock Rate" "0,1"
bitfld.long 0x28 10. "SWAP,CLK/DIR signal source for Position Counter: 0 Quadrature clock inputs are not swapped 1 Quadrature clock inputs are swapped" "0,1"
bitfld.long 0x28 9. "IGATE,Index Pulse Gating Option" "0,1"
bitfld.long 0x28 8. "QAP,QEPA input polarity" "0,1"
newline
bitfld.long 0x28 7. "QBP,QEPB input polarity" "0,1"
bitfld.long 0x28 6. "QIP,QEPI input polarity" "0,1"
bitfld.long 0x28 5. "QSP,QEPS input polarity" "0,1"
line.long 0x2C "EQEP_QCAP_QPOS_CTL,QEP Capture and Position Compare Control Register"
bitfld.long 0x2C 31. "PCSHDW,Position-compare shadow enable" "0,1"
bitfld.long 0x2C 30. "PCLOAD,Position Compare Shadow Load Mode" "0,1"
bitfld.long 0x2C 29. "PCPOL,Polarity of sync output" "0,1"
bitfld.long 0x2C 28. "PCE,Position compare enable/disable" "0,1"
hexmask.long.word 0x2C 16.--27. 1. "PCSPW,Select pulse width period in EQEP_FICLK cycles"
bitfld.long 0x2C 15. "CEN,Enable EQEP Capture" "0,1"
bitfld.long 0x2C 4.--6. "CCPS,EQEP Capture timer clock prescalar" "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 0.--3. "UPPS,Unit Position Event prescalar" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "EQEP_QINT_EN_FLG,QEP Interrupt Control and Flag Register"
rbitfld.long 0x30 27. "UTOI_FLG,Unit Time Out Interrupt Flag" "0,1"
rbitfld.long 0x30 26. "IELI_FLG,Index Event Latch Interrupt Flag" "0,1"
rbitfld.long 0x30 25. "SELI_FLG,Strobe Event Latch Interrupt Flag" "0,1"
rbitfld.long 0x30 24. "PCMI_FLG,EQEP Compare Match Event Interrupt Flag" "0,1"
rbitfld.long 0x30 23. "PCRI_FLG,Position Compare Ready Interrupt Flag" "0,1"
rbitfld.long 0x30 22. "PCOI_FLG,Position Counter Overflow Interrupt Flag" "0,1"
rbitfld.long 0x30 21. "PCUI_FLG,Position Counter Underflow Interrupt Flag" "0,1"
rbitfld.long 0x30 20. "WTOI_FLG,Watchdog Timeout Interrupt Flag" "0,1"
rbitfld.long 0x30 19. "QDCI_FLG,Quadrature Direction Change Interrupt Flag" "0,1"
newline
rbitfld.long 0x30 18. "QPEI_FLG,Quadrature Phase Error Interrupt Flag" "0,1"
rbitfld.long 0x30 17. "PCEI_FLG,Position Counter Error Interrupt Flag" "0,1"
rbitfld.long 0x30 16. "INT_FLG,Global Interrupt Status Flag" "0,1"
bitfld.long 0x30 11. "UTOI_EN,Unit Time Out Interrupt Enable" "0,1"
bitfld.long 0x30 10. "IELI_EN,Index Event Latch Interrupt Enable" "0,1"
bitfld.long 0x30 9. "SELI_EN,Strobe Event Latch Interrupt Enable" "0,1"
bitfld.long 0x30 8. "PCMI_EN,Position Compare Match Interrupt Enable" "0,1"
bitfld.long 0x30 7. "PCRI_EN,Position Compare Ready Interrupt Enable" "0,1"
bitfld.long 0x30 6. "PCOI_EN,Position Counter Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x30 5. "PCUI_EN,Position Counter Underflow Interrupt Enable" "0,1"
bitfld.long 0x30 4. "WTOI_EN,Watchdog Time Out Interrupt Enable" "0,1"
bitfld.long 0x30 3. "QDCI_EN,Quadrature Direction Change Interrupt Enable" "0,1"
bitfld.long 0x30 2. "QPEI_EN,Quadrature Phase Error Interrupt Enable" "0,1"
bitfld.long 0x30 1. "PCEI_EN,Position Counter Error Interrupt Enable" "0,1"
line.long 0x34 "EQEP_QINT_CLR_FRC,QEP Interrupt Clear and Forcing Register"
bitfld.long 0x34 27. "UTOI_FRC,Unit Time Out Interrupt Force" "0,1"
bitfld.long 0x34 26. "IELI_FRC,Index Event Latch Interrupt Force" "0,1"
bitfld.long 0x34 25. "SELI_FRC,Strobe Event Latch Interrupt Force" "0,1"
bitfld.long 0x34 24. "PCMI_FRC,Position Compare Match Interrupt Force" "0,1"
bitfld.long 0x34 23. "PCRI_FRC,Position Compare Ready Interrupt Force" "0,1"
bitfld.long 0x34 22. "PCOI_FRC,Position Counter Overflow Interrupt Force" "0,1"
bitfld.long 0x34 21. "PCUI_FRC,Position Counter Underflow Interrupt Force" "0,1"
bitfld.long 0x34 20. "WTOI_FRC,Watchdog Time Out Interrupt Force" "0,1"
bitfld.long 0x34 19. "QDCI_FRC,Quadrature Direction Change Interrupt Force" "0,1"
newline
bitfld.long 0x34 18. "QPEI_FRC,Quadrature Phase Error Interrupt Force" "0,1"
bitfld.long 0x34 17. "PCEI_FRC,Position Counter Error Interrupt Force" "0,1"
bitfld.long 0x34 11. "UTOI_CLR,Clear Unit Time Out Interrupt Flag" "0,1"
bitfld.long 0x34 10. "IELI_CLR,Clear Index Event Latch Interrupt Flag" "0,1"
bitfld.long 0x34 9. "SELI_CLR,Clear Strobe Event Latch Interrupt Flag" "0,1"
bitfld.long 0x34 8. "PCMI_CLR,Clear QEP Compare Match Event Interrupt Flag" "0,1"
bitfld.long 0x34 7. "PCRI_CLR,Clear Position Compare Ready Interrupt Flag" "0,1"
bitfld.long 0x34 6. "PCOI_CLR,Clear Position Counter Overflow Interrupt Flag" "0,1"
bitfld.long 0x34 5. "PCUI_CLR,Clear Position Counter Underflow Interrupt Flag" "0,1"
newline
bitfld.long 0x34 4. "WTOI_CLR,Clear Watchdog Timeout Interrupt Flag" "0,1"
bitfld.long 0x34 3. "QDCI_CLR,Clear Quadrature Direction Change Interrupt Flag" "0,1"
bitfld.long 0x34 2. "QPEI_CLR,Clear Quadrature Phase Error Interrupt Flag" "0,1"
bitfld.long 0x34 1. "PCEI_CLR,Clear Position Counter Error Interrupt Flag" "0,1"
bitfld.long 0x34 0. "INT_CLR,Global Interrupt Clear Flag" "0,1"
line.long 0x38 "EQEP_QEP_STS_CT,QEP Status and Capture Timer Register"
hexmask.long.word 0x38 16.--31. 1. "QCTMR,This field provides time base for edge capture unit"
rbitfld.long 0x38 6. "FIDF,Direction on First Index Marker" "0,1"
rbitfld.long 0x38 5. "QDF,Quadrature Direction flag" "0,1"
rbitfld.long 0x38 4. "QDLF,EQEP Direction Latch Flag" "0,1"
bitfld.long 0x38 3. "COEF,Capture Overflow Error Flag" "0,1"
bitfld.long 0x38 2. "CDEF,Capture Direction Error" "0,1"
bitfld.long 0x38 1. "FIMF,First Index Marker Flag" "0,1"
rbitfld.long 0x38 0. "PCEF,Position Counter Error Flag" "0,1"
line.long 0x3C "EQEP_QC_PRD_TLAT,QEP Capture Period and Timer Latch Register"
hexmask.long.word 0x3C 16.--31. 1. "QCTMRLAT,QEP Capture timer value can be latched into this register on two events"
hexmask.long.word 0x3C 0.--15. 1. "QCPRD,This field holds the period count value between the last successive EQEP position events"
line.long 0x40 "EQEP_QCPRDLAT,QEP Capture Period Latch"
hexmask.long.word 0x40 0.--15. 1. "QCPRDLAT,EQEP capture period value can be latched into this register on two events"
rgroup.long 0x5C++0x03
line.long 0x00 "EQEP_PID,Peripheral ID Register"
tree.end
repeat.end
tree.end
tree "ESM"
tree "ESM0_CFG"
base ad:0x700000
rgroup.long 0x00++0x33
line.long 0x00 "ESM_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Always reads as 1h" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:2h = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ESM_INFO,The Info Register gives the configuration information of this ESM"
bitfld.long 0x04 31. "LAST_RESET,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "PULSE_GROUPS,Indicates the number of event groups that are pulse (as opposed to level) driven"
hexmask.long.byte 0x04 0.--7. 1. "GROUPS,Indicates the total number of groups that exist in the ESM"
line.long 0x08 "ESM_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x08 0.--3. "KEY,This field is the global mask for all interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x0C 0.--3. "KEY,Global Soft Reset field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x10 0.--7. 1. "STS,This is the raw status for errors in the configuration for Group N"
line.long 0x14 "ESM_ERR_STS,Config Error Enable and Clear Register"
hexmask.long.byte 0x14 0.--7. 1. "MSK,This is the masked status for errors in the configuration for Group N"
line.long 0x18 "ESM_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x18 0.--7. 1. "MSK,This is the mask enable for errors in the configuration for Group N"
line.long 0x1C "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
hexmask.long.byte 0x1C 0.--7. 1. "MSK,This is the mask clear for errors in the configuration for Group N"
line.long 0x20 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x20 16.--31. 1. "PLS,Indicates what the highest priority low priority interrupt caused by a pulse number is"
hexmask.long.word 0x20 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is"
line.long 0x24 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x24 16.--31. 1. "PLS,Indicates what the highest priority high priority interrupt caused by a pulse number is"
hexmask.long.word 0x24 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is"
line.long 0x28 "ESM_LOW,Shows which groups have outstanding low priority interrupts"
line.long 0x2C "ESM_HI,Shows which groups have outstanding high priority interrupts"
line.long 0x30 "ESM_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x30 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x0F
line.long 0x00 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output"
bitfld.long 0x00 0.--3. "KEY,Pin control key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ESM_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x04 0. "VAL,This field indicates the status of the error pin as looped back from the I/O" "0,1"
line.long 0x08 "ESM_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x08 0.--23. 1. "COUNT,This field indicates the current value of the time interval counter"
line.long 0x0C "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0C 0.--23. 1. "COUNT,This is the value that will be pre-loaded in to the counter field of"
group.long 0x400++0x1B
line.long 0x00 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x04 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x08 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x0C "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x10 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x14 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x18 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
tree.end
tree "MCU_ESM0_CFG"
base ad:0x40800000
rgroup.long 0x00++0x33
line.long 0x00 "ESM_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Always reads as 1h" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:2h = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ESM_INFO,The Info Register gives the configuration information of this ESM"
bitfld.long 0x04 31. "LAST_RESET,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "PULSE_GROUPS,Indicates the number of event groups that are pulse (as opposed to level) driven"
hexmask.long.byte 0x04 0.--7. 1. "GROUPS,Indicates the total number of groups that exist in the ESM"
line.long 0x08 "ESM_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x08 0.--3. "KEY,This field is the global mask for all interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x0C 0.--3. "KEY,Global Soft Reset field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x10 0.--7. 1. "STS,This is the raw status for errors in the configuration for Group N"
line.long 0x14 "ESM_ERR_STS,Config Error Enable and Clear Register"
hexmask.long.byte 0x14 0.--7. 1. "MSK,This is the masked status for errors in the configuration for Group N"
line.long 0x18 "ESM_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x18 0.--7. 1. "MSK,This is the mask enable for errors in the configuration for Group N"
line.long 0x1C "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
hexmask.long.byte 0x1C 0.--7. 1. "MSK,This is the mask clear for errors in the configuration for Group N"
line.long 0x20 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x20 16.--31. 1. "PLS,Indicates what the highest priority low priority interrupt caused by a pulse number is"
hexmask.long.word 0x20 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is"
line.long 0x24 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x24 16.--31. 1. "PLS,Indicates what the highest priority high priority interrupt caused by a pulse number is"
hexmask.long.word 0x24 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is"
line.long 0x28 "ESM_LOW,Shows which groups have outstanding low priority interrupts"
line.long 0x2C "ESM_HI,Shows which groups have outstanding high priority interrupts"
line.long 0x30 "ESM_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x30 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x0F
line.long 0x00 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output"
bitfld.long 0x00 0.--3. "KEY,Pin control key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ESM_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x04 0. "VAL,This field indicates the status of the error pin as looped back from the I/O" "0,1"
line.long 0x08 "ESM_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x08 0.--23. 1. "COUNT,This field indicates the current value of the time interval counter"
line.long 0x0C "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0C 0.--23. 1. "COUNT,This is the value that will be pre-loaded in to the counter field of"
group.long 0x400++0x1B
line.long 0x00 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x04 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x08 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x0C "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x10 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x14 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x18 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
tree.end
tree "WKUP_ESM0_CFG"
base ad:0x42080000
rgroup.long 0x00++0x33
line.long 0x00 "ESM_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Always reads as 1h" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:2h = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ESM_INFO,The Info Register gives the configuration information of this ESM"
bitfld.long 0x04 31. "LAST_RESET,This bit indicates whether the last reset was a Warm or Power-On Rest" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "PULSE_GROUPS,Indicates the number of event groups that are pulse (as opposed to level) driven"
hexmask.long.byte 0x04 0.--7. 1. "GROUPS,Indicates the total number of groups that exist in the ESM"
line.long 0x08 "ESM_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x08 0.--3. "KEY,This field is the global mask for all interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ESM_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x0C 0.--3. "KEY,Global Soft Reset field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ESM_ERR_RAW,Raw Status/Set Register for Configuration Errors"
hexmask.long.byte 0x10 0.--7. 1. "STS,This is the raw status for errors in the configuration for Group N"
line.long 0x14 "ESM_ERR_STS,Config Error Enable and Clear Register"
hexmask.long.byte 0x14 0.--7. 1. "MSK,This is the masked status for errors in the configuration for Group N"
line.long 0x18 "ESM_ERR_EN_SET,Config Error Enable Set Register"
hexmask.long.byte 0x18 0.--7. 1. "MSK,This is the mask enable for errors in the configuration for Group N"
line.long 0x1C "ESM_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
hexmask.long.byte 0x1C 0.--7. 1. "MSK,This is the mask clear for errors in the configuration for Group N"
line.long 0x20 "ESM_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x20 16.--31. 1. "PLS,Indicates what the highest priority low priority interrupt caused by a pulse number is"
hexmask.long.word 0x20 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is"
line.long 0x24 "ESM_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x24 16.--31. 1. "PLS,Indicates what the highest priority high priority interrupt caused by a pulse number is"
hexmask.long.word 0x24 0.--15. 1. "LVL,Indicates what the highest priority low priority interrupt caused by a level number is"
line.long 0x28 "ESM_LOW,Shows which groups have outstanding low priority interrupts"
line.long 0x2C "ESM_HI,Shows which groups have outstanding high priority interrupts"
line.long 0x30 "ESM_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x30 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x0F
line.long 0x00 "ESM_PIN_CTRL,This register controls the SAFETY_ERRORn pin output"
bitfld.long 0x00 0.--3. "KEY,Pin control key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ESM_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x04 0. "VAL,This field indicates the status of the error pin as looped back from the I/O" "0,1"
line.long 0x08 "ESM_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x08 0.--23. 1. "COUNT,This field indicates the current value of the time interval counter"
line.long 0x0C "ESM_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0C 0.--23. 1. "COUNT,This is the value that will be pre-loaded in to the counter field of"
group.long 0x400++0x1B
line.long 0x00 "ESM_RAW_j,Raw Status/Set Register for Group A Errors Offset = 400h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x04 "ESM_STS_j,Error Enable and Clear Register Offset = 404h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x08 "ESM_INTR_EN_SET_j,Level Error Enable Set Register Offset = 408h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x0C "ESM_INTR_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 40Ch + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x10 "ESM_INT_PRIO_j,Level Error Interrupt Enabled Clear register Offset = 410h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x14 "ESM_PIN_EN_SET_j,Level Error Interrupt Enabled Clear register Offset = 414h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
line.long 0x18 "ESM_PIN_EN_CLR_j,Level Error Interrupt Enabled Clear register Offset = 418h + (j * 20h); where j = 0h to 3h for WKUP_ESM0_CFG j = 0h to 4h for MCU_ESM0_CFG j = 0h to 7h for ESM0_CFG"
tree.end
tree.end
tree "Firewall_Exception"
tree "CBASS_AASRC0_GLB"
base ad:0x45B20000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_AC0_GLB"
base ad:0x45B08000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_CSI0_GLB"
base ad:0x45B20400
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_DATADEBUG0_GLB"
base ad:0x45B20800
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_HC0_GLB"
base ad:0x45B20C00
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_HC2_0_GLB"
base ad:0x45B22800
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_HC_CFG0_GLB"
base ad:0x45B21000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_INFRA0_GLB"
base ad:0x45B0C000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_IPPHY0_GLB"
base ad:0x45B21400
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_MCASP_G0_0_GLB"
base ad:0x45B21800
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_MCASP_G1_0_GLB"
base ad:0x45B21C00
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_RC0_GLB"
base ad:0x45B22000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_RC_CFG0_GLB"
base ad:0x45B22400
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "CBASS_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "CBASS_EXCEPTION_PEND_SET,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "CBASS_EXCEPTION_PEND_CLEAR,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree.end
tree "FSS"
tree "MCU_FSS0_CFG"
base ad:0x47000000
rgroup.long 0x00++0x07
line.long 0x00 "MCU_FSS0_REVISION,Revision Register Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCU_FSS0_SYSCONFIG,Configuration Register Controls various parameters of the cotroller state"
bitfld.long 0x04 3. "ECC_DISABLE_ADR,Block Address ECC Calculation" "Block address within ECC calculation,Block address not within ECC calculation"
bitfld.long 0x04 1. "HB_OSPI,Path Select" "Select OSPI path,Select HyperBus interface path"
newline
bitfld.long 0x04 0. "ECC_EN,ECC Enable" "ECC disabled,ECC enabled"
group.long 0x10++0x13
line.long 0x00 "MCU_FSS0_EOI,End Of Interrupt (EOI) MISC Register The End Of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to it for misc interrupt sources"
bitfld.long 0x00 0. "EOI_VECTOR,EOI Vector Write with bit position of targeted interrupt (example: external FSS ECC is bit 0)" "0,1"
line.long 0x04 "MCU_FSS0_STATUS_RAW,Interrupt Source Set Register The Interrupt Source Set Register allows the interrupt sources to be manually set when writing 1h to a specific bit"
bitfld.long 0x04 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte" "0,1"
bitfld.long 0x04 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable" "0,1"
newline
bitfld.long 0x04 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable" "0,1"
line.long 0x08 "MCU_FSS0_STATUS,Interrupt Source Clear Register The Interrupt Source Clear Register allows the interrupt sources to be manually cleared when writing 1h to a specific bit"
bitfld.long 0x08 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte" "0,1"
bitfld.long 0x08 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable" "0,1"
newline
bitfld.long 0x08 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable" "0,1"
line.long 0x0C "MCU_FSS0_ENABLE_SET,Interrupt Source Enable Register The Interrupt Source Enable Register allows the interrupt sources to be manually enabled when writing 1h to a specific bit"
bitfld.long 0x0C 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte" "0,1"
bitfld.long 0x0C 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable" "0,1"
newline
bitfld.long 0x0C 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable" "0,1"
line.long 0x10 "MCU_FSS0_ENABLE_CLR,Interrupt Source Disable Register The Interrupt Source Disable Register allows the interrupt sources to be manually disabled when writing 1h to a specific bit"
bitfld.long 0x10 2. "ECC_WRITE_NONALIGN,ECC Write Non Aligned Write is not aligned to 32-byte boundary or not a multiple of 32-byte" "0,1"
bitfld.long 0x10 1. "ECC_ERROR_2BIT,ECC Error on 2 Bits Not correctable" "0,1"
newline
bitfld.long 0x10 0. "ECC_ERROR_1BIT,ECC Error on 1 Bit Correctable" "0,1"
group.long 0x30++0x07
line.long 0x00 "MCU_FSS0_ECC_RGSTRT_j,ECC Region Start Register The ECC Region Start Register defines the start of the ECC region in 4 KB steps"
abitfld.long 0x00 0.--19. "R_START,ECC Region Start Address This bit field defines the start of the ECC region in 4 KB steps" "0x00000=start is 0000 0000h,0x00001=start is 0000 1000h,0x0000A=start is 0000 A000h"
line.long 0x04 "MCU_FSS0_ECC_RGSIZ_j,ECC Region Size Register The ECC Region Size Register defines the size of the ECC region in 4 KB steps"
abitfld.long 0x04 0.--19. "R_SIZE,ECC Region Size This bit field defines the size of the ECC region in 4 KB steps" "0x00000=size is zero and disabled,0x00001=size is 4 KB,0x0000A=size is 40 KB F,0x0FFFF=size is 4 GB"
rgroup.long 0x70++0x0B
line.long 0x00 "MCU_FSS0_ECC_BLOCK_ADR,ECC Error Block Address Register The ECC Error Block Address Register holds the current top of stack ECC error block address. this is only valid when the [31] ECC_ERR_VALID bit is set"
hexmask.long 0x00 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC Error Block Address ECC 32-byte aligned block address"
line.long 0x04 "MCU_FSS0_ECC_TYPE,ECC Error Type Register The ECC Error Type Register holds the current top of stack ECC error info. this is only valid when the [31] ECC_ERR_VALID bit is set"
bitfld.long 0x04 31. "ECC_ERR_VALID,ECC Error Valid When set indicates that there is valid ECC error information available" "0,1"
rbitfld.long 0x04 5. "ECC_ERR_ADR,ECC Error Address When set indicates that there was a single error detected within the address field" "0,1"
newline
rbitfld.long 0x04 4. "ECC_ERR_MAC,ECC Error MAC When set indicates that there was a single error detected within the MAC field" "0,1"
rbitfld.long 0x04 3. "ECC_ERR_DA1,ECC Error High Data Word When set indicates that there was a single error detected within the High Data word" "0,1"
newline
rbitfld.long 0x04 2. "ECC_ERR_DA0,ECC Error Low Data Word When set indicates that there was a single error detected within the Low Data word" "0,1"
rbitfld.long 0x04 1. "ECC_ERR_DED,ECC Error (DED) When set indicates that there was a double error detected for the block" "0,1"
newline
rbitfld.long 0x04 0. "ECC_ERR_SEC,ECC Error (SEC) When set indicates that there was a single error detected for the block" "0,1"
line.long 0x08 "MCU_FSS0_WRT_TYPE,Error Write Type Register The Error Write Type Register holds the current top of stack write error info. this is only valid when the [31] WRT_ERR_VALID bit is set"
bitfld.long 0x08 31. "WRT_ERR_VALID,Write Error Valid When set indicates that there is valid write error information available" "0,1"
rbitfld.long 0x08 13. "WRT_ERR_BEN,Write Error Non-Contiguous Byte Enables When set indicates that there was a write error due to a non-contiguous byte enables" "0,1"
newline
rbitfld.long 0x08 12. "WRT_ERR_ADR,Write Error Address When set indicates that there was a write error due to a non-aligned address" "0,1"
hexmask.long.word 0x08 0.--11. 1. "WRT_ERR_ROUTEID,Write Error Route ID Indicates the Route ID for the Master that caused the write error"
tree.end
tree.end
tree "GIC_ECC_AGGR"
tree "COMPUTE_CLUSTER0_ECC_AGGR"
base ad:0x4D200C0000
rgroup.long 0x00++0x03
line.long 0x00 "GIC_ECC_AGGR_REV,IP revision register"
group.long 0x08++0x07
line.long 0x00 "GIC_ECC_AGGR_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "GIC_ECC_AGGR_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "GIC_ECC_AGGR_SEC_EOI_REG,EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "GIC_ECC_AGGR_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 5. "WRITE_PEND,Interrupt pending status for write_pend" "0,1"
bitfld.long 0x04 4. "READ_PEND,Interrupt pending status for read_pend" "0,1"
bitfld.long 0x04 3. "EDC_CTRL_PEND,Interrupt pending status for edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "LPI_RAMECC_PEND,Interrupt pending status for lpi_ramecc_pend" "0,1"
newline
bitfld.long 0x04 1. "ITE_RAMECC_PEND,Interrupt pending status for ite_ramecc_pend" "0,1"
bitfld.long 0x04 0. "ICB_RAMECC_PEND,Interrupt pending status for icb_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "GIC_ECC_AGGR_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0"
bitfld.long 0x00 5. "WRITE_ENABLE_SET,Interrupt enable set for write_pend" "0,1"
bitfld.long 0x00 4. "READ_ENABLE_SET,Interrupt enable set for read_pend" "0,1"
bitfld.long 0x00 3. "EDC_CTRL_ENABLE_SET,Interrupt enable set for edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_SET,Interrupt enable set for lpi_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_SET,Interrupt enable set for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_SET,Interrupt enable set for icb_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "GIC_ECC_AGGR_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0"
bitfld.long 0x00 5. "WRITE_ENABLE_CLR,Interrupt enable clear for write_pend" "0,1"
bitfld.long 0x00 4. "READ_ENABLE_CLR,Interrupt enable clear for read_pend" "0,1"
bitfld.long 0x00 3. "EDC_CTRL_ENABLE_CLR,Interrupt enable clear for edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_CLR,Interrupt enable clear for lpi_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_CLR,Interrupt enable clear for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_CLR,Interrupt enable clear for icb_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "GIC_ECC_AGGR_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "GIC_ECC_AGGR_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 5. "WRITE_PEND,Interrupt pending status for write_pend" "0,1"
bitfld.long 0x04 4. "READ_PEND,Interrupt pending status for read_pend" "0,1"
bitfld.long 0x04 3. "EDC_CTRL_PEND,Interrupt pending status for edc_ctrl_pend" "0,1"
bitfld.long 0x04 2. "LPI_RAMECC_PEND,Interrupt pending status for lpi_ramecc_pend" "0,1"
newline
bitfld.long 0x04 1. "ITE_RAMECC_PEND,Interrupt pending status for ite_ramecc_pend" "0,1"
bitfld.long 0x04 0. "ICB_RAMECC_PEND,Interrupt pending status for icb_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "GIC_ECC_AGGR_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 5. "WRITE_ENABLE_SET,Interrupt enable set for write_pend" "0,1"
bitfld.long 0x00 4. "READ_ENABLE_SET,Interrupt enable set for read_pend" "0,1"
bitfld.long 0x00 3. "EDC_CTRL_ENABLE_SET,Interrupt enable set for edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_SET,Interrupt enable set for lpi_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_SET,Interrupt enable set for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_SET,Interrupt enable set for icb_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "GIC_ECC_AGGR_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 5. "WRITE_ENABLE_CLR,Interrupt enable clear for write_pend" "0,1"
bitfld.long 0x00 4. "READ_ENABLE_CLR,Interrupt enable clear for read_pend" "0,1"
bitfld.long 0x00 3. "EDC_CTRL_ENABLE_CLR,Interrupt enable clear for edc_ctrl_pend" "0,1"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_CLR,Interrupt enable clear for lpi_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_CLR,Interrupt enable clear for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_CLR,Interrupt enable clear for icb_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "GIC_ECC_AGGR_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "GIC_ECC_AGGR_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "GIC_ECC_AGGR_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "GIC_ECC_AGGR_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "GPIO"
repeat 2. (list 1. 0. )(list ad:0x42100000 ad:0x42110000 )
tree "WKUP_GPIO$1"
base $2
rgroup.long 0x00++0x0B
line.long 0x00 "GPIO_PID,GPIO Periperal ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function code assigned to TCP3"
bitfld.long 0x00 11.--15. "RTL,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GPIO_PCR,Peripheral Control Register"
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x04 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1"
line.long 0x08 "GPIO_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x08 0.--15. 1. "EN,Per bank interrupt enable"
group.long 0x10++0xC7
line.long 0x00 "GPIO_DIR01,Direction Register"
hexmask.long.word 0x00 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits "
hexmask.long.word 0x00 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits "
line.long 0x04 "GPIO_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x04 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x04 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x08 "GPIO_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x08 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x08 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
line.long 0x0C "GPIO_CLR_DATA01,Clear Output Drive State Register"
hexmask.long.word 0x0C 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x0C 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x10 "GPIO_IN_DATA01,Bank Status Register"
hexmask.long.word 0x10 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x10 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
line.long 0x14 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x14 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x14 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x18 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x18 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x18 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x1C "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x1C 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x1C 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0x20 "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0x20 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x20 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x24 "GPIO_INTSTAT01,Bank Interrupt Status Register"
hexmask.long.word 0x24 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back"
hexmask.long.word 0x24 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back"
line.long 0x28 "GPIO_DIR23,Direction Register"
hexmask.long.word 0x28 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits "
hexmask.long.word 0x28 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits "
line.long 0x2C "GPIO_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x2C 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x2C 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x30 "GPIO_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x30 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x30 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
line.long 0x34 "GPIO_CLR_DATA23,Clear Output Drive State Register"
hexmask.long.word 0x34 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x34 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x38 "GPIO_IN_DATA23,Bank Status Register"
hexmask.long.word 0x38 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x38 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
line.long 0x3C "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x3C 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x3C 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x40 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x40 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x40 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x44 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x44 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x44 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0x48 "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0x48 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x48 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x4C "GPIO_INTSTAT23,Bank Interrupt Status Register"
hexmask.long.word 0x4C 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back"
hexmask.long.word 0x4C 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back"
line.long 0x50 "GPIO_DIR45,Direction Register"
hexmask.long.word 0x50 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits "
hexmask.long.word 0x50 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits "
line.long 0x54 "GPIO_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x54 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x54 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x58 "GPIO_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x58 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x58 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
line.long 0x5C "GPIO_CLR_DATA45,Clear Output Drive State Register"
hexmask.long.word 0x5C 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x5C 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x60 "GPIO_IN_DATA45,Bank Status Register"
hexmask.long.word 0x60 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x60 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
line.long 0x64 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x64 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x64 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x68 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x68 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x68 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x6C "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x6C 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x6C 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0x70 "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0x70 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x70 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x74 "GPIO_INTSTAT45,Bank Interrupt Status Register"
hexmask.long.word 0x74 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back"
hexmask.long.word 0x74 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back"
line.long 0x78 "GPIO_DIR67,Direction Register"
hexmask.long.word 0x78 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits "
hexmask.long.word 0x78 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits "
line.long 0x7C "GPIO_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x7C 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x7C 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x80 "GPIO_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x80 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x80 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
line.long 0x84 "GPIO_CLR_DATA67,Clear Output Drive State Register"
hexmask.long.word 0x84 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x84 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x88 "GPIO_IN_DATA67,Bank Status Register"
hexmask.long.word 0x88 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x88 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
line.long 0x8C "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x8C 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x8C 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x90 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x90 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x90 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x94 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x94 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x94 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0x98 "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0x98 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x98 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x9C "GPIO_INTSTAT67,Bank Interrupt Status Register"
hexmask.long.word 0x9C 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back"
hexmask.long.word 0x9C 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back"
line.long 0xA0 "GPIO_DIR8,Direction Register"
hexmask.long.word 0xA0 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits "
line.long 0xA4 "GPIO_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0xA4 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0xA8 "GPIO_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0xA8 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0xAC "GPIO_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0xAC 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0xB0 "GPIO_IN_DATA8,Bank Status Register"
hexmask.long.word 0xB0 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
line.long 0xB4 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0xB4 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0xB8 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0xB8 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0xBC "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0xBC 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0xC0 "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0xC0 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0xC4 "GPIO_INTSTAT8,Bank Interrupt Status Register"
hexmask.long.word 0xC4 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back"
tree.end
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list ad:0x600000 ad:0x601000 ad:0x610000 ad:0x611000 ad:0x620000 ad:0x621000 ad:0x630000 ad:0x680000 )
tree "GPIO$1"
base $2
rgroup.long 0x00++0x0B
line.long 0x00 "GPIO_PID,GPIO Periperal ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function code assigned to TCP3"
bitfld.long 0x00 11.--15. "RTL,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GPIO_PCR,Peripheral Control Register"
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x04 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1"
line.long 0x08 "GPIO_BINTEN,Bit Interrupt Enable Register"
hexmask.long.word 0x08 0.--15. 1. "EN,Per bank interrupt enable"
group.long 0x10++0xC7
line.long 0x00 "GPIO_DIR01,Direction Register"
hexmask.long.word 0x00 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits "
hexmask.long.word 0x00 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits "
line.long 0x04 "GPIO_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x04 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x04 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x08 "GPIO_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x08 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x08 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
line.long 0x0C "GPIO_CLR_DATA01,Clear Output Drive State Register"
hexmask.long.word 0x0C 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x0C 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x10 "GPIO_IN_DATA01,Bank Status Register"
hexmask.long.word 0x10 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x10 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
line.long 0x14 "GPIO_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x14 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x14 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x18 "GPIO_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x18 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x18 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x1C "GPIO_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x1C 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x1C 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0x20 "GPIO_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0x20 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x20 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x24 "GPIO_INTSTAT01,Bank Interrupt Status Register"
hexmask.long.word 0x24 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt Reading back"
hexmask.long.word 0x24 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt Reading back"
line.long 0x28 "GPIO_DIR23,Direction Register"
hexmask.long.word 0x28 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits "
hexmask.long.word 0x28 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits "
line.long 0x2C "GPIO_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x2C 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x2C 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x30 "GPIO_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x30 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x30 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
line.long 0x34 "GPIO_CLR_DATA23,Clear Output Drive State Register"
hexmask.long.word 0x34 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x34 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x38 "GPIO_IN_DATA23,Bank Status Register"
hexmask.long.word 0x38 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x38 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
line.long 0x3C "GPIO_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x3C 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x3C 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x40 "GPIO_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x40 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x40 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x44 "GPIO_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x44 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x44 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0x48 "GPIO_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0x48 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x48 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x4C "GPIO_INTSTAT23,Bank Interrupt Status Register"
hexmask.long.word 0x4C 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt Reading back"
hexmask.long.word 0x4C 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt Reading back"
line.long 0x50 "GPIO_DIR45,Direction Register"
hexmask.long.word 0x50 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits "
hexmask.long.word 0x50 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits "
line.long 0x54 "GPIO_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x54 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x54 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x58 "GPIO_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x58 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x58 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
line.long 0x5C "GPIO_CLR_DATA45,Clear Output Drive State Register"
hexmask.long.word 0x5C 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x5C 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x60 "GPIO_IN_DATA45,Bank Status Register"
hexmask.long.word 0x60 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x60 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
line.long 0x64 "GPIO_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x64 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x64 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x68 "GPIO_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x68 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x68 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x6C "GPIO_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x6C 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x6C 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0x70 "GPIO_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0x70 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x70 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x74 "GPIO_INTSTAT45,Bank Interrupt Status Register"
hexmask.long.word 0x74 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt Reading back"
hexmask.long.word 0x74 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt Reading back"
line.long 0x78 "GPIO_DIR67,Direction Register"
hexmask.long.word 0x78 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits "
hexmask.long.word 0x78 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits "
line.long 0x7C "GPIO_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x7C 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x7C 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x80 "GPIO_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x80 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x80 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
line.long 0x84 "GPIO_CLR_DATA67,Clear Output Drive State Register"
hexmask.long.word 0x84 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x84 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x88 "GPIO_IN_DATA67,Bank Status Register"
hexmask.long.word 0x88 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x88 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
line.long 0x8C "GPIO_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x8C 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x8C 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x90 "GPIO_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x90 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x90 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x94 "GPIO_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x94 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x94 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0x98 "GPIO_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0x98 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x98 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x9C "GPIO_INTSTAT67,Bank Interrupt Status Register"
hexmask.long.word 0x9C 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt Reading back"
hexmask.long.word 0x9C 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt Reading back"
line.long 0xA0 "GPIO_DIR8,Direction Register"
hexmask.long.word 0xA0 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits "
line.long 0xA4 "GPIO_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0xA4 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0xA8 "GPIO_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0xA8 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0xAC "GPIO_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0xAC 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0xB0 "GPIO_IN_DATA8,Bank Status Register"
hexmask.long.word 0xB0 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
line.long 0xB4 "GPIO_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0xB4 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0xB8 "GPIO_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0xB8 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0xBC "GPIO_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0xBC 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0xC0 "GPIO_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0xC0 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0xC4 "GPIO_INTSTAT8,Bank Interrupt Status Register"
hexmask.long.word 0xC4 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt Reading back"
tree.end
repeat.end
tree.end
tree "GPMC"
tree "GPMC0_CFG"
base ad:0x5390000
rgroup.long 0x00++0x03
line.long 0x00 "GPMC_REVISION,This register contains the IP revision code"
group.long 0x10++0x0F
line.long 0x00 "GPMC_SYSCONFIG,Register related to module software reset and local power management"
bitfld.long 0x00 3.--4. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
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bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
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bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running" "AUTOIDLE_0,AUTOIDLE_1"
line.long 0x04 "GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information"
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing" "RESETDONE_0,RESETDONE_1"
line.long 0x08 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt"
bitfld.long 0x08 11. "WAIT3EDGEDETECTIONSTATUS,Status of the Wait3 Edge Detection interrupt Write" "A transition on WAIT3 input pin has not been..,A transition on WAIT3 input pin has been detected"
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bitfld.long 0x08 10. "WAIT2EDGEDETECTIONSTATUS,Status of the Wait2 Edge Detection interrupt Write" "A transition on WAIT2 input pin has not been..,A transition on WAIT2 input pin has been detected"
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bitfld.long 0x08 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt Write" "A transition on WAIT1 input pin has not been..,A transition on WAIT1 input pin has been detected"
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bitfld.long 0x08 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt Write" "A transition on WAIT0 input pin has not been..,A transition on WAIT0 input pin has been detected"
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bitfld.long 0x08 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt Write" "Indicates that CountValue is greater than 0,Indicates that CountValue is equal to 0"
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bitfld.long 0x08 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt Write" "Indicates that less than,Indicates that at least"
line.long 0x0C "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis"
bitfld.long 0x0C 11. "WAIT3EDGEDETECTIONENABLE,Enables the Wait3 Edge Detection interrupt 0h (R/W) = Wait3EdgeDetection interrupt is masked" "WAIT3EDGEDETECTIONENABLE_0,WAIT3EDGEDETECTIONENABLE_1"
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bitfld.long 0x0C 10. "WAIT2EDGEDETECTIONENABLE,Enables the Wait2 Edge Detection interrupt 0h (R/W) = Wait2EdgeDetection interrupt is masked" "WAIT2EDGEDETECTIONENABLE_0,WAIT2EDGEDETECTIONENABLE_1"
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bitfld.long 0x0C 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt 0h (R/W) = Wait1EdgeDetection interrupt is masked" "WAIT1EDGEDETECTIONENABLE_0,WAIT1EDGEDETECTIONENABLE_1"
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bitfld.long 0x0C 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt 0h (R/W) = Wait0EdgeDetection interrupt is masked" "WAIT0EDGEDETECTIONENABLE_0,WAIT0EDGEDETECTIONENABLE_1"
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bitfld.long 0x0C 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode 0h (R/W) = TerminalCountEvent interrupt is masked" "TERMINALCOUNTEVENTENABLE_0,TERMINALCOUNTEVENTENABLE_1"
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bitfld.long 0x0C 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt 0h (R/W) = FIFOEvent interrupt is masked" "FIFOEVENTENABLE_0,FIFOEVENTENABLE_1"
group.long 0x40++0x0B
line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter"
hexmask.long.word 0x00 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter"
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bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature 0h (R/W) = TimeOut feature is disabled" "TIMEOUTENABLE_0,TIMEOUTENABLE_1"
line.long 0x04 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs"
hexmask.long 0x04 0.--30. 1. "ILLEGALADD,Address of illegal access"
line.long 0x08 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs"
rbitfld.long 0x08 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "ILLEGALMCMD_0,ILLEGALMCMD_1,ILLEGALMCMD_2,ILLEGALMCMD_3,ILLEGALMCMD_4,ILLEGALMCMD_5,ILLEGALMCMD_6,ILLEGALMCMD_7"
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rbitfld.long 0x08 4. "ERRORNOTSUPPADD,Not supported address error 0h (R) = No error occurs" "ERRORNOTSUPPADD_0,ERRORNOTSUPPADD_1"
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rbitfld.long 0x08 3. "ERRORNOTSUPPMCMD,Not supported command error 0h (R) = No error occurs" "ERRORNOTSUPPMCMD_0,ERRORNOTSUPPMCMD_1"
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rbitfld.long 0x08 2. "ERRORTIMEOUT,Time-out error 0h (R) = No error occurs" "ERRORTIMEOUT_0,ERRORTIMEOUT_1"
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bitfld.long 0x08 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction 0h (R/W) = All error fields no longer valid 1h (R/W) = Error detected and logged in the other error fields" "ERRORVALID_0,ERRORVALID_1"
group.long 0x50++0x07
line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC"
bitfld.long 0x00 11. "WAIT3PINPOLARITY,Selects the polarity of input pin WAIT3 0h (R/W) = WAIT3 active low 1h (R/W) = WAIT3 active high" "WAIT3PINPOLARITY_0,WAIT3PINPOLARITY_1"
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bitfld.long 0x00 10. "WAIT2PINPOLARITY,Selects the polarity of input pin WAIT2 0h (R/W) = WAIT2 active low 1h (R/W) = WAIT2 active high" "WAIT2PINPOLARITY_0,WAIT2PINPOLARITY_1"
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bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1 0h (R/W) = WAIT1 active low 1h (R/W) = WAIT1 active high" "WAIT1PINPOLARITY_0,WAIT1PINPOLARITY_1"
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bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0 0h (R/W) = WAIT0 active low 1h (R/W) = WAIT0 active high" "WAIT0PINPOLARITY_0,WAIT0PINPOLARITY_1"
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bitfld.long 0x00 4. "WRITEPROTECT,Controls the WP output pin level 0h (R/W) = nWP output pin is low 1h (R/W) = nWP output pin is high" "WRITEPROTECT_0,WRITEPROTECT_1"
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bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location 0h (R/W) = Disables Force Posted Write 1h (R/W) = Enables Force Posted" "NANDFORCEPOSTEDWRITE_0,NANDFORCEPOSTEDWRITE_1"
line.long 0x04 "GPMC_STATUS,The status register provides global status bits of the GPMC"
bitfld.long 0x04 11. "WAIT3STATUS,Is a copy of input pin WAIT3" "WAIT3STATUS_0,WAIT3STATUS_1"
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bitfld.long 0x04 10. "WAIT2STATUS,Is a copy of input pin WAIT2" "WAIT2STATUS_0,WAIT2STATUS_1"
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bitfld.long 0x04 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "WAIT1STATUS_0,WAIT1STATUS_1"
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bitfld.long 0x04 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "WAIT0STATUS_0,WAIT0STATUS_1"
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bitfld.long 0x04 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer 0h (R) = Write buffer is not empty" "EMPTYWRITEBUFFERSTATUS_0,EMPTYWRITEBUFFERSTATUS_1"
group.long 0x60++0x27
line.long 0x00 "GPMC_CONFIG1_i,The configuration register 1 sets signal control parameters per chip-select"
bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "0,1"
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bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous page if asynchronous)" "0,1"
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bitfld.long 0x00 29. "READTYPE,Selects the read mode operation 0h (R/W) = Read asynchronous 1h (R/W) = Read synchronous" "0,1"
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bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous considered as single if asynchronous)" "0,1"
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bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation 0h (R/W) = Write asynchronous 1h (R/W) = Write synchronous" "0,1"
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bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time 0h (R/W) = First rising edge of GPMC_CLK at start access time 1h (R/W) = First rising edge of GPMC_CLK one GPMC_FCLK cycle after start access time 2h (R/W) = First rising edge of GPMC_CLK two GPMC_FCLK.." "0,1,2,3"
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bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length 0h (R/W) = 4 words 1h (R/W) = 8 words 2h (R/W) = 16 words 3h (R/W) = Reserved (1 word = interface size)" "0,1,2,3"
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bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses 0h (R/W) = WAIT pin is not monitored for read accesses" "0,1"
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bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses 0h (R/W) = WAIT pin is not monitored for write accesses" "0,1"
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bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time 0h (R/W) = WAIT pin is monitored with valid data" "0,1,2,3"
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bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input WAIT pin for this chip-select 0h (R/W) = Wait input pin is WAIT0" "0,1,2,3"
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bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached 0h (R/W) = 8 bit 1h (R/W) = 16 bit 2h (R/W) = Reserved 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type 0h (R/W) = NOR flash-like asynchronous and synchronous devices 1h (R/W) = Reserved 2h (R/W) = NAND flash-like devices stream mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol 0h (R/W) = Nonmultiplexed attached device 1h (R/W) = AAD-multiplexed protocol device 2h (R/W) = Address and data multiplexed attached device 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "0,1"
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bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock 0h (R/W) = GPMC_CLK frequency = GPMC_FCLK frequency 1h (R/W) = GPMC_CLK frequency = GPMC_FCLK frequency / 2 2h (R/W) = GPMC_CLK frequency = GPMC_FCLK frequency / 3 3h (R/W) = GPMC_CLK frequency = GPMC_FCLK.." "0,1,2,3"
line.long 0x04 "GPMC_CONFIG2_i,CS signal timing parameter configuration Offset = 64h + (i * 30h). where: i = 0 to 3"
bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle 0h (R/W) = CS i Timing control signal is not delayed 1h (R/W) = CS i Timing control signal is delayed of half GPMC_FCLK clock cycle" "0,1"
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bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "GPMC_CONFIG3_i,nADV signal timing parameter configuration Offset = 68h + (i * 30h). where: i = 0 to 3"
bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle 0h (R/W) = nADV timing control signal is not delayed 1h (R/W) = nADV timing control signal is delayed of half GPMC_FCLK clock cycle" "0,1"
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bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "GPMC_CONFIG4_i,nWE and nOE signals timing parameter configuration Offset = 6Ch + (i * 30h). where: i = 0 to 3"
bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle 0h (R/W) = nWE timing control signal is not delayed 1h (R/W) = nWE timing control signal is delayed of half-GPMC_FCLK clock cycle" "0,1"
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bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 13.--15. "OEAADMUX_OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle 0h (R/W) = nOE timing control signal is not delayed 1h (R/W) = nOE timing control signal is delayed of half-GPMC_FCLK clock cycle" "0,1"
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bitfld.long 0x0C 4.--6. "OEAADMUX_ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "GPMC_CONFIG5_i,RdAccessTime and CycleTime timing parameters configuration Offset = 70h + (i * 30h). where: i = 0 to 3"
bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "GPMC_CONFIG6_i,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration Offset = 74h + (i * 30h). where: i = 0 to 3"
bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY" "0,1"
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bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY" "0,1"
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bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "GPMC_CONFIG7_i,CS address mapping configuration Offset = 78h + (i * 30h). where: i = 0 to 3"
bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 6. "CSVALID,CS enable 0h (R/W) = CS disabled 1h (R/W) = CS enabled" "0,1"
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bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 3 (16-MB minimum granularity) bits [5-0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "GPMC_NAND_COMMAND_i,This register is not a true register. only an address location"
line.long 0x20 "GPMC_NAND_ADDRESS_i,This register is not a true register. only an address location"
line.long 0x24 "GPMC_NAND_DATA_i,This register is not a true register. only an address location"
group.long 0x1E0++0x07
line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1 Some of the GPMC features described in this section may not be supported on this family of devices"
bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "CYCLEOPTIMIZATION_0,CYCLEOPTIMIZATION_1,CYCLEOPTIMIZATION_2,CYCLEOPTIMIZATION_3,CYCLEOPTIMIZATION_4,CYCLEOPTIMIZATION_5,CYCLEOPTIMIZATION_6,CYCLEOPTIMIZATION_7"
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bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization 0h (R/W) = Access cycle optimization is disabled" "ENABLEOPTIMIZEDACCESS_0,ENABLEOPTIMIZEDACCESS_1"
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bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "ENGINECSSELECTOR_0,ENGINECSSELECTOR_1,ENGINECSSELECTOR_2,ENGINECSSELECTOR_3,ENGINECSSELECTOR_4,ENGINECSSELECTOR_5,ENGINECSSELECTOR_6,ENGINECSSELECTOR_7"
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bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration 0h (R/W) = Prefetch Postwrite engine round robin arbitration is disabled" "PFPWENROUNDROBIN_0,PFPWENROUNDROBIN_1"
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bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced" "PFPWWEIGHTEDPRIO_0,PFPWWEIGHTEDPRIO_1,PFPWWEIGHTEDPRIO_2,PFPWWEIGHTEDPRIO_3,PFPWWEIGHTEDPRIO_4,PFPWWEIGHTEDPRIO_5,PFPWWEIGHTEDPRIO_6,PFPWWEIGHTEDPRIO_7,PFPWWEIGHTEDPRIO_8,PFPWWEIGHTEDPRIO_9,PFPWWEIGHTEDPRIO_10,PFPWWEIGHTEDPRIO_11,PFPWWEIGHTEDPRIO_12,PFPWWEIGHTEDPRIO_13,PFPWWEIGHTEDPRIO_14,PFPWWEIGHTEDPRIO_15"
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hexmask.long.byte 0x00 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request"
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bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine 0h (R/W) = Prefetch Postwrite engine is disabled" "ENABLEENGINE_0,ENABLEENGINE_1"
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bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode 0h (R/W) = Selects Wait0 EdgeDetection 1h (R/W) = Selects Wait1 EdgeDetection2h (R/W) = Selects Wait2 EdgeDetection 3h (R/W) = Selects Wait3 EdgeDetection" "WAITPINSELECTOR_0,WAITPINSELECTOR_1,WAITPINSELECTOR_2,WAITPINSELECTOR_3"
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bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to chip-select 0h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set 1h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set AND wait to nonwait.." "SYNCHROMODE_0,SYNCHROMODE_1"
newline
bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization 0h (R/W) = Interrupt synchronization is enabled" "DMAMODE_0,DMAMODE_1"
newline
bitfld.long 0x00 0. "ACCESSMODE,Selects prefetch read or write-posting accesses 0h (R/W) = Prefetch read mode 1h (R/W) = Write-posting mode" "ACCESSMODE_0,ACCESSMODE_1"
line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2"
hexmask.long.word 0x04 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select"
group.long 0x1EC++0x17
line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control"
bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engine Write" "Engine is stopped,Engine is running"
line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch engine status"
hexmask.long.byte 0x04 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written"
newline
bitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value 0h (R) = FIFOPointer smaller or equal to FIFOThreshold" "FIFOTHRESHOLDSTATUS_0,FIFOTHRESHOLDSTATUS_1"
newline
hexmask.long.word 0x04 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value"
line.long 0x08 "GPMC_ECC_CONFIG,ECC configuration"
bitfld.long 0x08 16. "ECCALGORITHM,ECC algorithm used 0h (R/W) = Hamming code 1h (R/W) = BCH code" "ECCALGORITHM_0,ECCALGORITHM_1"
newline
bitfld.long 0x08 12.--13. "ECCBCHTSEL,Error correction capability used for BCH 0h (R/W) = Up to 4 bits error correction (t = 4) 1h (R/W) = Up to 8 bits error correction (t = 8) 2h (R/W) = Up to 16 bits error correction (t = 16) 3h (R/W) = Reserved" "ECCBCHTSEL_0,ECCBCHTSEL_1,ECCBCHTSEL_2,ECCBCHTSEL_3"
newline
bitfld.long 0x08 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "ECCWRAPMODE_0,ECCWRAPMODE_1,ECCWRAPMODE_2,ECCWRAPMODE_3,ECCWRAPMODE_4,ECCWRAPMODE_5,ECCWRAPMODE_6,ECCWRAPMODE_7,ECCWRAPMODE_8,ECCWRAPMODE_9,ECCWRAPMODE_10,ECCWRAPMODE_11,ECCWRAPMODE_12,ECCWRAPMODE_13,ECCWRAPMODE_14,ECCWRAPMODE_15"
newline
bitfld.long 0x08 7. "ECC16B,Selects an ECC calculated on 16 columns 0h (R/W) = ECC calculated on 8 columns 1h (R/W) = ECC calculated on 16 columns" "ECC16B_0,ECC16B_1"
newline
bitfld.long 0x08 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm" "ECCTOPSECTOR_0,ECCTOPSECTOR_1,ECCTOPSECTOR_2,ECCTOPSECTOR_3,ECCTOPSECTOR_4,ECCTOPSECTOR_5,ECCTOPSECTOR_6,ECCTOPSECTOR_7"
newline
bitfld.long 0x08 1.--3. "ECCCS,Selects the CS where ECC is computed 0h (R/W) = CS0 1h (R/W) = CS1 2h (R/W) = CS2 3h (R/W) = CS3 Other: Reserved" "ECCCS_0,ECCCS_1,ECCCS_2,ECCCS_3,ECCCS_4,ECCCS_5,ECCCS_6,ECCCS_7"
newline
bitfld.long 0x08 0. "ECCENABLE,Enables the ECC feature 0h (R/W) = ECC disabled 1h (R/W) = ECC enabled" "ECCENABLE_0,ECCENABLE_1"
line.long 0x0C "GPMC_ECC_CONTROL,ECC control"
bitfld.long 0x0C 8. "ECCCLEAR,Clear all ECC result registers" "ECCCLEAR_0,ECCCLEAR_1"
newline
bitfld.long 0x0C 0.--3. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Writing other values disables the ECC engine.." "ECCPOINTER_0,ECCPOINTER_1,ECCPOINTER_2,ECCPOINTER_3,ECCPOINTER_4,ECCPOINTER_5,ECCPOINTER_6,ECCPOINTER_7,ECCPOINTER_8,ECCPOINTER_9,ECCPOINTER_10,ECCPOINTER_11,ECCPOINTER_12,ECCPOINTER_13,ECCPOINTER_14,ECCPOINTER_15"
line.long 0x10 "GPMC_ECC_SIZE_CONFIG,ECC size"
hexmask.long.byte 0x10 22.--29. 1. "ECCSIZE1,Defines Hamming code ECC size 1 in bytes"
newline
hexmask.long.byte 0x10 12.--19. 1. "ECCSIZE0,Defines Hamming code ECC size 0 in bytes"
newline
bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC9RESULTSIZE_0,ECC9RESULTSIZE_1"
newline
bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC8RESULTSIZE_0,ECC8RESULTSIZE_1"
newline
bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC7RESULTSIZE_0,ECC7RESULTSIZE_1"
newline
bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC6RESULTSIZE_0,ECC6RESULTSIZE_1"
newline
bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC5RESULTSIZE_0,ECC5RESULTSIZE_1"
newline
bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC4RESULTSIZE_0,ECC4RESULTSIZE_1"
newline
bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC3RESULTSIZE_0,ECC3RESULTSIZE_1"
newline
bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC2RESULTSIZE_0,ECC2RESULTSIZE_1"
newline
bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected" "ECC1RESULTSIZE_0,ECC1RESULTSIZE_1"
line.long 0x14 "GPMC_ECCj_RESULT,ECC result register Offset = 200h + (j * 4h). where: j = 0 to 8"
bitfld.long 0x14 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1"
newline
bitfld.long 0x14 26. "P1024O,Odd row parity bit 1024" "0,1"
newline
bitfld.long 0x14 25. "P512O,Odd row parity bit 512" "0,1"
newline
bitfld.long 0x14 24. "P256O,Odd row parity bit 256" "0,1"
newline
bitfld.long 0x14 23. "P128O,Odd row parity bit 128" "0,1"
newline
bitfld.long 0x14 22. "P64O,Odd row parity bit 64" "0,1"
newline
bitfld.long 0x14 21. "P32O,Odd row parity bit 32" "0,1"
newline
bitfld.long 0x14 20. "P16O,Odd row parity bit 16" "0,1"
newline
bitfld.long 0x14 19. "P8O,Odd row parity bit 8" "0,1"
newline
bitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1"
newline
bitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1"
newline
bitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1"
newline
bitfld.long 0x14 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1"
newline
bitfld.long 0x14 10. "P1024E,Even row parity bit 1024" "0,1"
newline
bitfld.long 0x14 9. "P512E,Even row parity bit 512" "0,1"
newline
bitfld.long 0x14 8. "P256E,Even row parity bit 256" "0,1"
newline
bitfld.long 0x14 7. "P128E,Even row parity bit 128" "0,1"
newline
bitfld.long 0x14 6. "P64E,Even row parity bit 64" "0,1"
newline
bitfld.long 0x14 5. "P32E,Even row parity bit 32" "0,1"
newline
bitfld.long 0x14 4. "P16E,Even row parity bit 16" "0,1"
newline
bitfld.long 0x14 3. "P8E,Even row parity bit 8" "0,1"
newline
bitfld.long 0x14 2. "P4E,Even column parity bit 4" "0,1"
newline
bitfld.long 0x14 1. "P2E,Even column parity bit 2" "0,1"
newline
bitfld.long 0x14 0. "P1E,Even column parity bit 1" "0,1"
rgroup.long 0x240++0x0F
line.long 0x00 "GPMC_BCH_RESULT0_i,BCH ECC result (bits 0 to 31) Offset = 240h + (i * 10h). where: i = 0 to 3"
line.long 0x04 "GPMC_BCH_RESULT1_i,BCH ECC result (bits 32 to 63) Offset = 244h + (i * 10h). where: i = 0 to 3"
line.long 0x08 "GPMC_BCH_RESULT2_i,BCH ECC result (bits 64 to 95) Offset = 248h + (i * 10h). where: i = 0 to 3"
line.long 0x0C "GPMC_BCH_RESULT3_i,BCH ECC result (bits 96 to 127) Offset = 24Ch + (i * 10h). where: i = 0 to 3"
group.long 0x2D0++0x03
line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface"
hexmask.long.word 0x00 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation"
rgroup.long 0x300++0x0B
line.long 0x00 "GPMC_BCH_RESULT4_i,BCH ECC result (bits 128 to 159) Offset = 300h + (i * 10h). where: i = 0 to 3"
line.long 0x04 "GPMC_BCH_RESULT5_i,BCH ECC result (bits 160 to 191) Offset = 304h + (i * 10h). where: i = 0 to 3"
line.long 0x08 "GPMC_BCH_RESULT6_i,BCH ECC result (bits 192 to 207) Offset = 308h + (i * 10h). where: i = 0 to 3"
hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)"
tree.end
tree.end
tree "GPU"
tree "GPU0_PBIST_CFG"
base ad:0x33A0000
group.long 0x120++0x07
line.long 0x00 "GPU0_D,Return to"
hexmask.long.word 0x00 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)"
hexmask.long.word 0x00 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)"
line.long 0x04 "GPU0_E,Return to"
hexmask.long.word 0x04 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)"
hexmask.long.word 0x04 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)"
group.long 0x160++0x0F
line.long 0x00 "GPU0_RAMT,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RGS,RAM Group Select RGS"
hexmask.long.byte 0x00 16.--23. 1. "RDS,Return Data select RDS"
hexmask.long.byte 0x00 8.--15. 1. "DWR,Data Width Register DWR"
bitfld.long 0x00 2.--5. "PLS,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "RLS,RAM Latency Select" "0,1,2,3"
line.long 0x04 "GPU0_DLR,Return to"
hexmask.long.byte 0x04 16.--23. 1. "BRP,Datalogger 2 (BRP)"
bitfld.long 0x04 10. "DLR1_RTM,Retention testing mode" "0,1"
bitfld.long 0x04 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1"
bitfld.long 0x04 8. "DLR1_MISR,MISR testing mode (mainly for" "0,1"
bitfld.long 0x04 7. "DLR0_TSM,Time stamp mode" "0,1"
bitfld.long 0x04 6. "DLR0_CFMM,Column Fail Masking mode" "0,1"
newline
bitfld.long 0x04 5. "DLR0_ECAM,Emulation cache access mode" "0,1"
bitfld.long 0x04 4. "DLR0_CAM,Config access mode" "0,1"
bitfld.long 0x04 3. "DLR0_TCK,TCK Gated mode" "0,1"
bitfld.long 0x04 2. "DLR0_ROM," "0,1"
bitfld.long 0x04 1. "DLR0_IDDQ,IDDQ testing mode" "0,1"
bitfld.long 0x04 0. "DLR0_DCM,Distributed Compare mode" "0,1"
line.long 0x08 "GPU0_CMS,Return to"
bitfld.long 0x08 0.--3. "CMS,Clock Mux Select (" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "GPU0_STR,Return to"
bitfld.long 0x0C 4. "CHK,Check MISR mode" "0,1"
bitfld.long 0x0C 3. "STEP,Step / Step for emulation mode" "0,1"
bitfld.long 0x0C 2. "STOP,Stop" "0,1"
bitfld.long 0x0C 1. "RES,Resume / Emulation read" "0,1"
bitfld.long 0x0C 0. "START,Start / Time Stamp mode restart" "0,1"
group.quad 0x170++0x07
line.quad 0x00 "GPU0_SCR,Return to"
hexmask.quad.byte 0x00 56.--63. 1. "SCR7,Address Scrambling Register 7"
hexmask.quad.byte 0x00 48.--55. 1. "SCR6,Address Scrambling Register 6"
hexmask.quad.byte 0x00 40.--47. 1. "SCR5,Address Scrambling Register 5"
hexmask.quad.byte 0x00 32.--39. 1. "SCR4,Address Scrambling Register 4"
hexmask.quad.byte 0x00 24.--31. 1. "SCR3,Address Scrambling Register 3"
hexmask.quad.byte 0x00 16.--23. 1. "SCR2,Address Scrambling Register 2"
newline
hexmask.quad.byte 0x00 8.--15. 1. "SCR1,Address Scrambling Register 1"
hexmask.quad.byte 0x00 0.--7. 1. "SCR0,Address Scrambling Register 0"
group.long 0x178++0x13
line.long 0x00 "GPU0_CSR,Return to"
hexmask.long.byte 0x00 24.--31. 1. "CSR3,Chip Select 3 (CSR3)"
hexmask.long.byte 0x00 16.--23. 1. "CSR2,Chip Select 2 (CSR2)"
hexmask.long.byte 0x00 8.--15. 1. "CSR1,Chip Select 1(CSR1)"
hexmask.long.byte 0x00 0.--7. 1. "CSR0,Chip Select 0 (CSR0)"
line.long 0x04 "GPU0_FDLY,Return to"
hexmask.long.byte 0x04 0.--7. 1. "FDLY,Fail Delay ("
line.long 0x08 "GPU0_PACT,Return to"
bitfld.long 0x08 0. "PACT,PBIST Activate (" "0,1"
line.long 0x0C "GPU0_PID,Return to"
bitfld.long 0x0C 0.--4. "PID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "GPU0_OVER,Return to"
bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1"
bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1"
bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1"
bitfld.long 0x10 0. "RINFO,PBIST Override" "0,1"
rgroup.quad 0x190++0x17
line.quad 0x00 "GPU0_FSRF,Return to"
bitfld.quad 0x00 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1"
bitfld.quad 0x00 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1"
line.quad 0x08 "GPU0_FSRC,Return to"
bitfld.quad 0x08 32.--35. "FSRC1,Fail Status Count - Port 1 (FSRC1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 0.--3. "FSRC0,Fail Status Count - Port 0 (FSRC0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x10 "GPU0_FSRA,Return to"
hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)"
hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)"
rgroup.long 0x1B4++0x13
line.long 0x00 "GPU0_MARGIN_MODE,Return to"
bitfld.long 0x00 2.--3. "PBIST_DFT_READ,pbist_dft_read" "0,1,2,3"
bitfld.long 0x00 0.--1. "PBIST_DFT_WRITE,pbist_dft_" "0,1,2,3"
line.long 0x04 "GPU0_WRENZ,Return to"
bitfld.long 0x04 0.--1. "WRENZ,pbist_ram_wrenz" "0,1,2,3"
line.long 0x08 "GPU0_PAGE_PGS,Return to"
bitfld.long 0x08 0.--1. "PGS,pbist_ram_pgs" "0,1,2,3"
line.long 0x0C "GPU0_ROM,Return to"
bitfld.long 0x0C 0.--1. "ROM," "0,1,2,3"
line.long 0x10 "GPU0_ALGO,Return to"
hexmask.long.byte 0x10 24.--31. 1. "ALGO_3,"
hexmask.long.byte 0x10 16.--23. 1. "ALGO_2,"
hexmask.long.byte 0x10 8.--15. 1. "ALGO_1,"
hexmask.long.byte 0x10 0.--7. 1. "ALGO_0,"
group.quad 0x1C8++0x07
line.quad 0x00 "GPU0_RINFO,Return to"
hexmask.quad.byte 0x00 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)"
hexmask.quad.byte 0x00 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)"
hexmask.quad.byte 0x00 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)"
hexmask.quad.byte 0x00 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)"
hexmask.quad.byte 0x00 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)"
hexmask.quad.byte 0x00 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)"
newline
hexmask.quad.byte 0x00 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)"
hexmask.quad.byte 0x00 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "GPU0_FSRDL$1,Return to"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x150)++0x03
line.long 0x00 "GPU0_I$1,Return to"
hexmask.long.word 0x00 0.--15. 1. "I0,Constant Increment Register 0 ("
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x140)++0x03
line.long 0x00 "GPU0_CL$1,Return to"
hexmask.long.word 0x00 0.--15. 1. "CL0,Constant Loop Count Register 0 ("
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x130)++0x03
line.long 0x00 "GPU0_CA$1,Return to"
hexmask.long.word 0x00 0.--15. 1. "CA0,Constant Address Register 0 ("
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x110)++0x03
line.long 0x00 "GPU0_L$1,Return to"
hexmask.long.word 0x00 0.--15. 1. "L0,Variable Loop Count Register 0 ("
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x100)++0x03
line.long 0x00 "GPU0_A$1,Return to"
hexmask.long.word 0x00 0.--15. 1. "A0,Variable Address Register 0 ("
repeat.end
tree.end
tree.end
tree "GTC0_GTC_CFG0"
tree "GTC0_GTC_CFG0"
base ad:0xA80000
rgroup.long 0x00++0x0B
line.long 0x00 "GTC_PID,This is the standard platform IP revision register which contains the ID and revision information of the MMR generator"
line.long 0x04 "GTC_GTC_PID,This is the standard platform IP revision register which contains the ID and revision information of the GTC peripheral"
line.long 0x08 "GTC_PUSHEVT,Selects which bit of the count value to output as a push event for global timesync"
bitfld.long 0x08 0.--5. "EXPBIT_SEL,This field controls the mux that selects which bit [63:0] of the system counter value is exported on the0h = Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "GTC0_GTC_CFG1"
tree "GTC0_GTC_CFG1"
base ad:0xA90000
group.long 0x00++0x0F
line.long 0x00 "GTC_CNTCR,This register enables the system counter and controls counter operation during debug"
hexmask.long.tbyte 0x00 8.--31. 1. "FCREQ,Frequency change request"
bitfld.long 0x00 1. "HDBG,Halt on debug0 = System counter ignores debug halt1 = System counter is halted when debug halt is asserted" "0,1"
bitfld.long 0x00 0. "EN,Enable system counter0 = System counter is disabled1 = System counter is enabled" "0,1"
line.long 0x04 "GTC_CNTSR,This register provides system counter frequency status information"
hexmask.long.tbyte 0x04 8.--31. 1. "FCACK,Frequency change ackowledge"
bitfld.long 0x04 1. "DBGH,Debug halt" "0,1"
line.long 0x08 "GTC_CNTCV_LO,Indicates the current system counter count value and can be used to set the system counter count value"
line.long 0x0C "GTC_CNTCV_HI,Indicates the current system counter count value and can be used to set the system counter count value"
group.long 0x20++0x07
line.long 0x00 "GTC_CNTFID0,Indicates base frequency of the system counter"
line.long 0x04 "GTC_CNTFID1,Indicates the system counter increment frequency"
tree.end
tree.end
tree "GTC0_GTC_CFG2"
tree "GTC0_GTC_CFG2"
base ad:0xAA0000
rgroup.long 0x00++0x07
line.long 0x00 "GTC_CNTCVS_LO,Indicates the current system counter count value"
line.long 0x04 "GTC_CNTCVS_HI,Indicates the current system counter count value"
tree.end
tree.end
tree "GTC0_GTC_CFG3"
tree "GTC0_GTC_CFG3"
base ad:0xAB0000
rgroup.long 0x00++0x03
line.long 0x00 "GTC_CNTTIDR,Indicates the implemented timers in the memory map and their features"
bitfld.long 0x00 28.--31. "FRAME7,Indicates the features of timer frame 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "FRAME6,Indicates the features of timer frame 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "FRAME5,Indicates the features of timer frame 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "FRAME4,Indicates the features of timer frame 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "FRAME3,Indicates the features of timer frame 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "FRAME2,Indicates the features of timer frame 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "FRAME1,Indicates the features of timer frame 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "FRAME0,Indicates the features of timer frame 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "HyperBus"
tree "MCU_FSS0_HPB_CTRL"
base ad:0x47034000
rgroup.long 0x00++0x0B
line.long 0x00 "MCU_FSS0_HPB0_MC_CSR,Controller Status Register The Controller Status Register is used to access the internal status of the HBMC"
bitfld.long 0x00 26. "WRSTOERR,Write RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest write operation" "Normal operation,HyperBus memory is under reset"
bitfld.long 0x00 25. "WTRSERR,Write Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest write transaction" "Normal operation,This protocol is not supported"
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bitfld.long 0x00 24. "WDECERR,Write Decode Error This bit indicates whether access address is acceptable in the latest write transaction" "Normal operation,Access address is not reachable"
bitfld.long 0x00 16. "WACT,Write Active This bit indicates whether write transaction is in progress or not" "Write is idle,Write is active"
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bitfld.long 0x00 11. "RDSSTALL,RDS Stall This bit indicates whether read data transfer from HyperBus memory is stalled (RDS Stall remains LOW) in the latest read transaction" "Normal operation,RDS is stalled"
bitfld.long 0x00 10. "RRSTOERR,Read RSTO Error This bit indicates whether HyperBus memory is under reset state in the latest read operation" "Normal operation,HyperBus memory is under reset"
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bitfld.long 0x00 9. "RTRSERR,Read Transaction Error This bit indicates whether AXI protocol is acceptable by HBMC in the latest read transaction" "Normal operation,This protocol is not supported"
bitfld.long 0x00 8. "RDECERR,Read Decode Error This bit indicates whether access address is acceptable in the latest read transaction" "Normal operation,Access address is not reachable"
newline
bitfld.long 0x00 0. "RACT,Read Active This bit indicates whether read transaction is in progress or not" "Read is idle,Read is active"
line.long 0x04 "MCU_FSS0_HPB0_MC_IER,Interrupt Enable Register The HBMC outputs optional interrupt signal by condition enabled by the Interrupt Enable Register"
bitfld.long 0x04 31. "INTP,Interrupt Polarity Control This bit is used to choose the polarity of optional interrupt signal (IENOn)" "IENOn signal is active low,IENOn signal is active high (Reversed mode)"
bitfld.long 0x04 0. "RPCINTE,HyperBus Memory Interrupt Enable" "Disable interrupt,Enable interrupt by INT# signal of HyperBus memory"
line.long 0x08 "MCU_FSS0_HPB0_MC_ISR,Interrupt Status Register The Interrupt Status Register is used to read the status for the interrupts generated"
bitfld.long 0x08 0. "RPCINTS,HyperBus Memory Interrupt" "No interrupt,This bit displays interrupt from.."
group.long 0x10++0x03
line.long 0x00 "MCU_FSS0_HPB0_MC_MBAR_y,Memory Base Address Register for device connected to CS# The base address of addressable region to Hyperflash memory can be set-up using this register"
hexmask.long.byte 0x00 24.--31. 1. "A_MSB,MSB 8 bit of the base address of addressable region to HyperBus memory"
hexmask.long.tbyte 0x00 0.--23. 1. "A_LSB,Since register can be set in 16 MB boundary lower 24 bit is fixed to 0h if read this field will always return 0h"
group.long 0x20++0x03
line.long 0x00 "MCU_FSS0_HPB0_MC_MCR_y,Memory Configuration Register for CS# Offset = 20h + (y x 4h); where y = 0h to 1h"
bitfld.long 0x00 31. "MAXEN,Maximum Length Enable When this bit is set to 1h CS# low time can be configurable by MAXLEN bit" "No configurable CS# low time,Configurable CS# low time"
abitfld.long 0x00 18.--26. "MAXLEN,Maximum Length This bit indicates maximum read/write transaction length to memory" "0x000=2 Byte (1 HyperBus CK),0x001=4 Byte (2 HyperBus CK),0x002=6 Byte (3 HyperBus CK),0x1FF=1024 Byte (512 HyperBus CK)"
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bitfld.long 0x00 17. "TCMO,True Continuous Merge Option Note that this function can be used with the HyperFlash with specific function" "No merging WRAP and INCR,Merging WRAP and INCR"
bitfld.long 0x00 16. "ACS,Asymmetry Cache Support This function should be disabled if the HyperBus memory itself supports the asymmetry cache system" "No asymmetry cache system support,Asymmetry cache system support"
newline
bitfld.long 0x00 5. "CRT,Configuration Register Target This bit indicates whether the read or write operation accesses the memory or CR space" "Memory space,CR space"
bitfld.long 0x00 4. "DEVTYPE,Device Type Device type for control target" "HyperFlash,HyperRAM"
newline
bitfld.long 0x00 0.--1. "WRAPSIZE,Wrap Size The wrap burst length of HyperBus memory" "Reserved,64 Bytes,16 Bytes,32 Bytes"
group.long 0x30++0x03
line.long 0x00 "MCU_FSS0_HPB0_MC_MTR_y,Memory Timing Register Memory access timings for CS# can be configured using the Memory Timing Register"
bitfld.long 0x00 28.--31. "RCSHI,Read Chip Select High Between Operations This bit indicates CS# high time for read between operations" "corresponds to 1.5 clock cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,corresponds to 16.5 clock cycle"
bitfld.long 0x00 24.--27. "WCSHI,Write Chip Select High Between Operations This bit indicates CS# high time for write between operations" "corresponds to 1.5 clock cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,corresponds to 16.5 clock cycle"
newline
bitfld.long 0x00 20.--23. "RCSS,Read Chip Select Setup to next CK rising edge This bit indicates CS# setup time for read from CS# assertion" "corresponds to 1 clock cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,corresponds to 16 clock cycle"
bitfld.long 0x00 16.--19. "WCSS,Write Chip Select Setup to next CK rising edge This bit indicates CS# setup time for write from CS# assertion" "corresponds to 1 clock cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,corresponds to 16 clock cycle"
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bitfld.long 0x00 12.--15. "RCSH,Read Chip Select Hold after CK falling edge This bit indicates CS# hold time for read to CS# de-assertion" "corresponds to 1 clock cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,corresponds to 16 clock cycle"
bitfld.long 0x00 8.--11. "WCSH,Write Chip Select Hold after CK falling edge This bit indicates CS# hold time for write to CS# de-assertion" "corresponds to 1 clock cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,corresponding to 16 clock cycle"
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bitfld.long 0x00 0.--3. "LTCY,Latency Cycle Only uses in HyperRAM This bit indicates initial latency code for read/write access" "5 clock latency,6 clock latency,Reserved,?,?,?,?,?,?,?,?,?,?,Reserved,3 clock latency,4 clock latency"
group.long 0x40++0x0B
line.long 0x00 "MCU_FSS0_HPB0_MC_GPOR,General Purpose Output Register Output signal polarity can be configured using the General Purpose Output Register"
bitfld.long 0x00 0.--1. "GPO,General Purpose Output Interface" "Output signal polarity is LOW,Output signal polarity is HIGH,?..."
line.long 0x04 "MCU_FSS0_HPB0_MC_WPR,Write Protection Register Write protection can be configured using the Write Protection Register"
bitfld.long 0x04 0. "WP,Write Protection Control" "Not Protected WP# signal is HIGH,Protected WP# signal is LOW"
line.long 0x08 "MCU_FSS0_HPB0_MC_LBR,Loop Back Register Loopback settings can be configured using the Loop Back Register"
bitfld.long 0x08 0. "LOOPBACK,The write transaction data written on AXI bus is looped back as the read data from RPC bus" "Disable loopback,Enable loopback"
tree.end
tree "MCU_FSS0_HPB_ECC_AGGR"
base ad:0x47060000
rgroup.long 0x00++0x03
line.long 0x00 "MCU_FSS0_HPB0_ECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MCU_FSS0_HPB0_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MCU_FSS0_HPB0_ECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator"
group.long 0x3C++0x07
line.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_EOI_REG,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI" "0,1"
line.long 0x04 "MCU_FSS0_HPB0_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 14. "MEM_ARID_FIFO_PEND,Interrupt Pending Status for mem_arid_fifo_pend" "0,1"
bitfld.long 0x04 13. "MEM_AR_FIFO_PEND,Interrupt Pending Status for mem_ar_fifo_pend" "0,1"
bitfld.long 0x04 12. "MEM_AWID1_FIFO_PEND,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1"
newline
bitfld.long 0x04 11. "MEM_WID1_FIFO_PEND,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1"
bitfld.long 0x04 10. "MEM_AW1_FIFO_PEND,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x04 9. "MEM_AWID0_FIFO_PEND,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1"
newline
bitfld.long 0x04 8. "MEM_WID0_FIFO_PEND,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x04 7. "MEM_AW0_FIFO_PEND,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1"
bitfld.long 0x04 6. "MEM_RX_FIFO_PEND,Interrupt Pending Status for mem_rx_fifo_pend" "0,1"
newline
bitfld.long 0x04 5. "MEM_RDAT_FIFO_PEND,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1"
bitfld.long 0x04 4. "MEM_BDAT1_FIFO_PEND,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x04 3. "MEM_BDAT0_FIFO_PEND,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1"
newline
bitfld.long 0x04 2. "MEM_WDAT1_FIFO_PEND,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x04 1. "MEM_WDAT0_FIFO_PEND,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1"
bitfld.long 0x04 0. "MEM_ADR_FIFO_PEND,Interrupt Pending Status for mem_adr_fifo_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 14. "MEM_ARID_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "MEM_AR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1"
bitfld.long 0x00 12. "MEM_AWID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_WID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1"
bitfld.long 0x00 10. "MEM_AW1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "MEM_AWID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1"
newline
bitfld.long 0x00 8. "MEM_WID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "MEM_AW0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1"
bitfld.long 0x00 6. "MEM_RX_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1"
newline
bitfld.long 0x00 5. "MEM_RDAT_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1"
bitfld.long 0x00 4. "MEM_BDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "MEM_BDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1"
newline
bitfld.long 0x00 2. "MEM_WDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1"
bitfld.long 0x00 0. "MEM_ADR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MCU_FSS0_HPB0_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 14. "MEM_ARID_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "MEM_AR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_ar_fifo_pend" "0,1"
bitfld.long 0x00 12. "MEM_AWID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid1_fifo_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_WID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid1_fifo_pend" "0,1"
bitfld.long 0x00 10. "MEM_AW1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "MEM_AWID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid0_fifo_pend" "0,1"
newline
bitfld.long 0x00 8. "MEM_WID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "MEM_AW0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw0_fifo_pend" "0,1"
bitfld.long 0x00 6. "MEM_RX_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rx_fifo_pend" "0,1"
newline
bitfld.long 0x00 5. "MEM_RDAT_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rdat_fifo_pend" "0,1"
bitfld.long 0x00 4. "MEM_BDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "MEM_BDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat0_fifo_pend" "0,1"
newline
bitfld.long 0x00 2. "MEM_WDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat0_fifo_pend" "0,1"
bitfld.long 0x00 0. "MEM_ADR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_adr_fifo_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MCU_FSS0_HPB0_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI" "0,1"
line.long 0x04 "MCU_FSS0_HPB0_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 14. "MEM_ARID_FIFO_PEND,Interrupt Pending Status for mem_arid_fifo_pend" "0,1"
bitfld.long 0x04 13. "MEM_AR_FIFO_PEND,Interrupt Pending Status for mem_ar_fifo_pend" "0,1"
bitfld.long 0x04 12. "MEM_AWID1_FIFO_PEND,Interrupt Pending Status for mem_awid1_fifo_pend" "0,1"
newline
bitfld.long 0x04 11. "MEM_WID1_FIFO_PEND,Interrupt Pending Status for mem_wid1_fifo_pend" "0,1"
bitfld.long 0x04 10. "MEM_AW1_FIFO_PEND,Interrupt Pending Status for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x04 9. "MEM_AWID0_FIFO_PEND,Interrupt Pending Status for mem_awid0_fifo_pend" "0,1"
newline
bitfld.long 0x04 8. "MEM_WID0_FIFO_PEND,Interrupt Pending Status for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x04 7. "MEM_AW0_FIFO_PEND,Interrupt Pending Status for mem_aw0_fifo_pend" "0,1"
bitfld.long 0x04 6. "MEM_RX_FIFO_PEND,Interrupt Pending Status for mem_rx_fifo_pend" "0,1"
newline
bitfld.long 0x04 5. "MEM_RDAT_FIFO_PEND,Interrupt Pending Status for mem_rdat_fifo_pend" "0,1"
bitfld.long 0x04 4. "MEM_BDAT1_FIFO_PEND,Interrupt Pending Status for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x04 3. "MEM_BDAT0_FIFO_PEND,Interrupt Pending Status for mem_bdat0_fifo_pend" "0,1"
newline
bitfld.long 0x04 2. "MEM_WDAT1_FIFO_PEND,Interrupt Pending Status for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x04 1. "MEM_WDAT0_FIFO_PEND,Interrupt Pending Status for mem_wdat0_fifo_pend" "0,1"
bitfld.long 0x04 0. "MEM_ADR_FIFO_PEND,Interrupt Pending Status for mem_adr_fifo_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MCU_FSS0_HPB0_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 14. "MEM_ARID_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "MEM_AR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_ar_fifo_pend" "0,1"
bitfld.long 0x00 12. "MEM_AWID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid1_fifo_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_WID1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid1_fifo_pend" "0,1"
bitfld.long 0x00 10. "MEM_AW1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "MEM_AWID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_awid0_fifo_pend" "0,1"
newline
bitfld.long 0x00 8. "MEM_WID0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "MEM_AW0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_aw0_fifo_pend" "0,1"
bitfld.long 0x00 6. "MEM_RX_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rx_fifo_pend" "0,1"
newline
bitfld.long 0x00 5. "MEM_RDAT_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_rdat_fifo_pend" "0,1"
bitfld.long 0x00 4. "MEM_BDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "MEM_BDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_bdat0_fifo_pend" "0,1"
newline
bitfld.long 0x00 2. "MEM_WDAT1_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDAT0_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_wdat0_fifo_pend" "0,1"
bitfld.long 0x00 0. "MEM_ADR_FIFO_ENABLE_SET,Interrupt Enable Set Register for mem_adr_fifo_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MCU_FSS0_HPB0_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 14. "MEM_ARID_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_arid_fifo_pend" "0,1"
bitfld.long 0x00 13. "MEM_AR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_ar_fifo_pend" "0,1"
bitfld.long 0x00 12. "MEM_AWID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid1_fifo_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_WID1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid1_fifo_pend" "0,1"
bitfld.long 0x00 10. "MEM_AW1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw1_fifo_pend" "0,1"
bitfld.long 0x00 9. "MEM_AWID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_awid0_fifo_pend" "0,1"
newline
bitfld.long 0x00 8. "MEM_WID0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wid0_fifo_pend" "0,1"
bitfld.long 0x00 7. "MEM_AW0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_aw0_fifo_pend" "0,1"
bitfld.long 0x00 6. "MEM_RX_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rx_fifo_pend" "0,1"
newline
bitfld.long 0x00 5. "MEM_RDAT_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_rdat_fifo_pend" "0,1"
bitfld.long 0x00 4. "MEM_BDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat1_fifo_pend" "0,1"
bitfld.long 0x00 3. "MEM_BDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_bdat0_fifo_pend" "0,1"
newline
bitfld.long 0x00 2. "MEM_WDAT1_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat1_fifo_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDAT0_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_wdat0_fifo_pend" "0,1"
bitfld.long 0x00 0. "MEM_ADR_FIFO_ENABLE_CLR,Interrupt Enable Clear Register for mem_adr_fifo_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MCU_FSS0_HPB0_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MCU_FSS0_HPB0_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MCU_FSS0_HPB0_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MCU_FSS0_HPB0_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_FSS0_HPB_SS_CFG"
base ad:0x47030000
rgroup.long 0x00++0x0B
line.long 0x00 "MCU_FSS0_HPB0_SS_REVISION_REG,Revision Register The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCU_FSS0_HPB0_SS_DLL_STAT_REG,DLL Status Register"
hexmask.long.word 0x04 2.--10. 1. "MDLL_CODE,MDLL Code The slave delay line length that is currently enabled is determined by the MDLL Code value"
bitfld.long 0x04 1. "SDL_LOCK,SDL Lock When this bit is set it indicates that the slave delay line in the MDLL is locked" "0,1"
bitfld.long 0x04 0. "MDLL_LOCK,MDLL Lock When this bit is set it indicates that the master delay line in the MDLL is locked" "0,1"
line.long 0x08 "MCU_FSS0_HPB0_SS_RAM_STAT_REG,RAM Status Register"
bitfld.long 0x08 0. "INIT_DONE,FIFO RAM Initialization Done When this bit is set it indicates that all the FIFO RAM auto initialization is complete" "0,1"
tree.end
tree.end
tree "I2C"
repeat 7. (increment 0 1) (increment ad:0x2000000 0x10000)
tree "I2C$1_CFG"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "ENAWAKEUP_0,ENAWAKEUP_1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "SRST_0,SRST_1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "AUTOIDLE_0,AUTOIDLE_1"
group.long 0x20++0x2F
line.long 0x00 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "BB_0,BB_1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1"
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bitfld.long 0x04 8. "BF,Bus Free IRQ status" "BF_0,BF_1"
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "STC_0,STC_1"
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bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
line.long 0x08 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "BB_0,BB_1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1"
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bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1"
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1"
newline
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
line.long 0x0C "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
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bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
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bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "DMARX_ENABLE_SET_0,DMARX_ENABLE_SET_1"
line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "DMATX_ENABLE_SET_0,DMATX_ENABLE_SET_1"
line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "DMARX_ENABLE_CLEAR_0,DMARX_ENABLE_CLEAR_1"
line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "DMATX_ENABLE_CLEAR_0,DMATX_ENABLE_CLEAR_1"
line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
group.long 0x84++0x07
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "XDR_IE_0,XDR_IE_1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "RDR_IE_0,RDR_IE_1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "XUDF_0,XUDF_1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "ASS_IE_0,ASS_IE_1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "BF_IE_0,BF_IE_1"
newline
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "AERR_IE_0,AERR_IE_1"
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "STC_IE_0,STC_IE_1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "GC_IE_0,GC_IE_1"
newline
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "XRDY_IE_0,XRDY_IE_1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "RRDY_IE_0,RRDY_IE_1"
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "ARDY_IE_0,ARDY_IE_1"
newline
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "NACK_IE_0,NACK_IE_1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "AL_IE_0,AL_IE_1"
line.long 0x04 "I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "BB_0,BB_1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1"
newline
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "BF_0,BF_1"
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "STC_0,STC_1"
newline
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
rgroup.long 0x90++0x0F
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "RDONE_0,RDONE_1"
line.long 0x04 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "RDMA_EN_0,RDMA_EN_1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "RXFIFO_CLR_0,RXFIFO_CLR_1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "XDMA_EN_0,XDMA_EN_1"
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "TXFIFO_CLR_0,TXFIFO_CLR_1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
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bitfld.long 0x00 10. "MST,Master/slave mode" "MST_0,MST_1"
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1"
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bitfld.long 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1"
bitfld.long 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1"
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bitfld.long 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "MCODE_0,MCODE_1,MCODE_2,MCODE_3,MCODE_4,MCODE_5,MCODE_6,MCODE_7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x0C 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x"
line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "FREE_0,FREE_1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3"
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bitfld.long 0x18 11. "SSB,Set status bits" "SSB_0,SSB_1"
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "SCL_I_FUNC_0,SCL_I_FUNC_1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "SCL_O_FUNC_0,SCL_O_FUNC_1"
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rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "SDA_I_FUNC_0,SDA_I_FUNC_1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "SDA_O_FUNC_0,SDA_O_FUNC_1"
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "SCCB_E_O_0,SCCB_E_O_1"
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rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "SCL_I_0,SCL_I_1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "SDA_I_0,SDA_I_1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1"
line.long 0x1C "I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0,OA3_ACT_1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0,OA2_ACT_1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0,OA1_ACT_1"
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bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0,OA0_ACT_1"
line.long 0x30 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1"
newline
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1"
tree.end
repeat.end
repeat 2. (increment 0 1) (increment ad:0x40B00000 0x10000)
tree "MCU_I2C$1_CFG"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "ENAWAKEUP_0,ENAWAKEUP_1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "SRST_0,SRST_1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "AUTOIDLE_0,AUTOIDLE_1"
group.long 0x20++0x2F
line.long 0x00 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "BB_0,BB_1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1"
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bitfld.long 0x04 8. "BF,Bus Free IRQ status" "BF_0,BF_1"
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "STC_0,STC_1"
newline
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
line.long 0x08 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "BB_0,BB_1"
newline
bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1"
newline
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1"
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1"
newline
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
line.long 0x0C "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "DMARX_ENABLE_SET_0,DMARX_ENABLE_SET_1"
line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "DMATX_ENABLE_SET_0,DMATX_ENABLE_SET_1"
line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "DMARX_ENABLE_CLEAR_0,DMARX_ENABLE_CLEAR_1"
line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "DMATX_ENABLE_CLEAR_0,DMATX_ENABLE_CLEAR_1"
line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
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bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
group.long 0x84++0x07
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "XDR_IE_0,XDR_IE_1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "RDR_IE_0,RDR_IE_1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "ROVR_0,ROVR_1"
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bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "XUDF_0,XUDF_1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "ASS_IE_0,ASS_IE_1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "BF_IE_0,BF_IE_1"
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bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "AERR_IE_0,AERR_IE_1"
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "STC_IE_0,STC_IE_1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "GC_IE_0,GC_IE_1"
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bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "XRDY_IE_0,XRDY_IE_1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "RRDY_IE_0,RRDY_IE_1"
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "ARDY_IE_0,ARDY_IE_1"
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bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "NACK_IE_0,NACK_IE_1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "AL_IE_0,AL_IE_1"
line.long 0x04 "I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "BB_0,BB_1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1"
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bitfld.long 0x04 8. "BF,Bus Free IRQ status" "BF_0,BF_1"
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "STC_0,STC_1"
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bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
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bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
rgroup.long 0x90++0x0F
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "RDONE_0,RDONE_1"
line.long 0x04 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "RDMA_EN_0,RDMA_EN_1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "RXFIFO_CLR_0,RXFIFO_CLR_1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "XDMA_EN_0,XDMA_EN_1"
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "TXFIFO_CLR_0,TXFIFO_CLR_1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
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bitfld.long 0x00 10. "MST,Master/slave mode" "MST_0,MST_1"
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1"
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bitfld.long 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1"
bitfld.long 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1"
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bitfld.long 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "MCODE_0,MCODE_1,MCODE_2,MCODE_3,MCODE_4,MCODE_5,MCODE_6,MCODE_7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x0C 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x"
line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "FREE_0,FREE_1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3"
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bitfld.long 0x18 11. "SSB,Set status bits" "SSB_0,SSB_1"
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "SCL_I_FUNC_0,SCL_I_FUNC_1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "SCL_O_FUNC_0,SCL_O_FUNC_1"
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rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "SDA_I_FUNC_0,SDA_I_FUNC_1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "SDA_O_FUNC_0,SDA_O_FUNC_1"
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "SCCB_E_O_0,SCCB_E_O_1"
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rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "SCL_I_0,SCL_I_1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "SDA_I_0,SDA_I_1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1"
line.long 0x1C "I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0,OA3_ACT_1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0,OA2_ACT_1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0,OA1_ACT_1"
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bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0,OA0_ACT_1"
line.long 0x30 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1"
newline
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1"
tree.end
repeat.end
tree "WKUP_I2C0_CFG"
base ad:0x42120000
rgroup.long 0x00++0x07
line.long 0x00 "I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "ENAWAKEUP_0,ENAWAKEUP_1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "SRST_0,SRST_1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "AUTOIDLE_0,AUTOIDLE_1"
group.long 0x20++0x2F
line.long 0x00 "I2C_EOI,End Of Interrupt number specification The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "BB_0,BB_1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1"
newline
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "BF_0,BF_1"
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "STC_0,STC_1"
newline
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
line.long 0x08 "I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "BB_0,BB_1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1"
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bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1"
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1"
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bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
line.long 0x0C "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
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bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
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bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in" "0,1"
line.long 0x10 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
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bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
newline
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in" "0,1"
line.long 0x14 "I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
line.long 0x18 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "DMARX_ENABLE_SET_0,DMARX_ENABLE_SET_1"
line.long 0x1C "I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "DMATX_ENABLE_SET_0,DMATX_ENABLE_SET_1"
line.long 0x20 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "DMARX_ENABLE_CLEAR_0,DMARX_ENABLE_CLEAR_1"
line.long 0x24 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "DMATX_ENABLE_CLEAR_0,DMATX_ENABLE_CLEAR_1"
line.long 0x28 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
line.long 0x2C "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1"
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1"
newline
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "GC_0,GC_1"
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1"
newline
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1"
group.long 0x84++0x07
line.long 0x00 "I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "XDR_IE_0,XDR_IE_1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in" "RDR_IE_0,RDR_IE_1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "ROVR_0,ROVR_1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "XUDF_0,XUDF_1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in" "ASS_IE_0,ASS_IE_1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in" "BF_IE_0,BF_IE_1"
newline
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in" "AERR_IE_0,AERR_IE_1"
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in" "STC_IE_0,STC_IE_1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in" "GC_IE_0,GC_IE_1"
newline
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "XRDY_IE_0,XRDY_IE_1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in" "RRDY_IE_0,RRDY_IE_1"
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in" "ARDY_IE_0,ARDY_IE_1"
newline
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in" "NACK_IE_0,NACK_IE_1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in" "AL_IE_0,AL_IE_1"
line.long 0x04 "I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "BB_0,BB_1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "ROVR_0,ROVR_1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "XUDF_0,XUDF_1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1"
newline
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "BF_0,BF_1"
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "STC_0,STC_1"
newline
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "GC_0,GC_1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "XRDY_0,XRDY_1"
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "RRDY_0,RRDY_1"
newline
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "ARDY_0,ARDY_1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "NACK_0,NACK_1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "AL_0,AL_1"
rgroup.long 0x90++0x0F
line.long 0x00 "I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "RDONE_0,RDONE_1"
line.long 0x04 "I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "RDMA_EN_0,RDMA_EN_1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "RXFIFO_CLR_0,RXFIFO_CLR_1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "XDMA_EN_0,XDMA_EN_1"
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "TXFIFO_CLR_0,TXFIFO_CLR_1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
newline
bitfld.long 0x00 10. "MST,Master/slave mode" "MST_0,MST_1"
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1"
newline
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1"
bitfld.long 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1"
newline
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "MCODE_0,MCODE_1,MCODE_2,MCODE_3,MCODE_4,MCODE_5,MCODE_6,MCODE_7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x0C 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x"
line.long 0x10 "I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "FREE_0,FREE_1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3"
newline
bitfld.long 0x18 11. "SSB,Set status bits" "SSB_0,SSB_1"
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "SCL_I_FUNC_0,SCL_I_FUNC_1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "SCL_O_FUNC_0,SCL_O_FUNC_1"
newline
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "SDA_I_FUNC_0,SDA_I_FUNC_1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "SDA_O_FUNC_0,SDA_O_FUNC_1"
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "SCCB_E_O_0,SCCB_E_O_1"
newline
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "SCL_I_0,SCL_I_1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "SDA_I_0,SDA_I_1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1"
line.long 0x1C "I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0,OA3_ACT_1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0,OA2_ACT_1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0,OA1_ACT_1"
newline
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0,OA0_ACT_1"
line.long 0x30 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1"
newline
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1"
tree.end
tree.end
tree "I3C"
tree "I3C0_MMR_MMRVBP"
base ad:0x20A0000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_PID,Return to"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "MCU_I3C0_MMR_MMRVBP"
base ad:0x40B80000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_PID,Return to"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "MCU_I3C1_MMR_MMRVBP"
base ad:0x40B90000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_PID,Return to"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "I3C0_P_ECC_AGGR_CFG"
base ad:0x2A74000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "I3C0_S_ECC_AGGR_CFG"
base ad:0x2A75000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_I3C0_P_ECC_AGGR_CFG"
base ad:0x40720000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_I3C0_S_ECC_AGGR_CFG"
base ad:0x40721000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_I3C1_P_ECC_AGGR_CFG"
base ad:0x40722000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_I3C1_S_ECC_AGGR_CFG"
base ad:0x40723000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "I3C0_S_ECC_AGGR_CFG"
base ad:0x2A75000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1"
bitfld.long 0x04 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1"
bitfld.long 0x04 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1"
bitfld.long 0x04 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1"
bitfld.long 0x04 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1"
newline
bitfld.long 0x04 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1"
bitfld.long 0x04 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1"
bitfld.long 0x04 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1"
bitfld.long 0x04 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1"
bitfld.long 0x04 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1"
bitfld.long 0x04 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1"
bitfld.long 0x04 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1"
bitfld.long 0x04 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1"
newline
bitfld.long 0x04 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1"
bitfld.long 0x04 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1"
bitfld.long 0x04 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1"
bitfld.long 0x04 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_I3C0_S_ECC_AGGR_CFG"
base ad:0x40721000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1"
bitfld.long 0x04 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1"
bitfld.long 0x04 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1"
bitfld.long 0x04 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1"
bitfld.long 0x04 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1"
newline
bitfld.long 0x04 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1"
bitfld.long 0x04 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1"
bitfld.long 0x04 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1"
bitfld.long 0x04 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1"
bitfld.long 0x04 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1"
bitfld.long 0x04 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1"
bitfld.long 0x04 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1"
bitfld.long 0x04 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1"
newline
bitfld.long 0x04 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1"
bitfld.long 0x04 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1"
bitfld.long 0x04 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1"
bitfld.long 0x04 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_I3C1_S_ECC_AGGR_CFG"
base ad:0x40723000
rgroup.long 0x00++0x03
line.long 0x00 "I3C_REV,Return to"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "I3C_VECTOR,Return to"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "I3C_STAT,Return to"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "I3C_RESERVED_SVBUS_y,Return to"
group.long 0x3C++0x07
line.long 0x00 "I3C_SEC_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_SEC_STATUS_REG0,Return to"
bitfld.long 0x04 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1"
bitfld.long 0x04 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1"
bitfld.long 0x04 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1"
bitfld.long 0x04 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1"
bitfld.long 0x04 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1"
newline
bitfld.long 0x04 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1"
bitfld.long 0x04 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1"
bitfld.long 0x04 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1"
bitfld.long 0x04 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "I3C_SEC_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "I3C_SEC_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "I3C_DED_EOI_REG,Return to"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "I3C_DED_STATUS_REG0,Return to"
bitfld.long 0x04 8. "RX_DATA_PEND,Interrupt Pending Status for rx_data_pend" "0,1"
bitfld.long 0x04 7. "CMD_WRD0_PEND,Interrupt Pending Status for cmd_wrd0_pend" "0,1"
bitfld.long 0x04 6. "TX_DATA_PEND,Interrupt Pending Status for tx_data_pend" "0,1"
bitfld.long 0x04 5. "CMD_WRD1_PEND,Interrupt Pending Status for cmd_wrd1_pend" "0,1"
bitfld.long 0x04 4. "IBI_PEND,Interrupt Pending Status for ibi_pend" "0,1"
newline
bitfld.long 0x04 3. "SLV_DDR_TX_PEND,Interrupt Pending Status for slv_ddr_tx_pend" "0,1"
bitfld.long 0x04 2. "CMDR_QUEUE_PEND,Interrupt Pending Status for cmdr_queue_pend" "0,1"
bitfld.long 0x04 1. "SLV_DDR_RX_PEND,Interrupt Pending Status for slv_ddr_rx_pend" "0,1"
bitfld.long 0x04 0. "IBIR_QUEUE_PEND,Interrupt Pending Status for ibir_queue_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "I3C_DED_ENABLE_SET_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_SET,Interrupt Enable Set Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_SET,Interrupt Enable Set Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_SET,Interrupt Enable Set Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_SET,Interrupt Enable Set Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_SET,Interrupt Enable Set Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_SET,Interrupt Enable Set Register for ibir_queue_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "I3C_DED_ENABLE_CLR_REG0,Return to"
bitfld.long 0x00 8. "RX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for rx_data_pend" "0,1"
bitfld.long 0x00 7. "CMD_WRD0_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd0_pend" "0,1"
bitfld.long 0x00 6. "TX_DATA_ENABLE_CLR,Interrupt Enable Clear Register for tx_data_pend" "0,1"
bitfld.long 0x00 5. "CMD_WRD1_ENABLE_CLR,Interrupt Enable Clear Register for cmd_wrd1_pend" "0,1"
bitfld.long 0x00 4. "IBI_ENABLE_CLR,Interrupt Enable Clear Register for ibi_pend" "0,1"
newline
bitfld.long 0x00 3. "SLV_DDR_TX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_tx_pend" "0,1"
bitfld.long 0x00 2. "CMDR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for cmdr_queue_pend" "0,1"
bitfld.long 0x00 1. "SLV_DDR_RX_ENABLE_CLR,Interrupt Enable Clear Register for slv_ddr_rx_pend" "0,1"
bitfld.long 0x00 0. "IBIR_QUEUE_ENABLE_CLR,Interrupt Enable Clear Register for ibir_queue_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "I3C_AGGR_ENABLE_SET,Return to"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "I3C_AGGR_ENABLE_CLR,Return to"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "I3C_AGGR_STATUS_SET,Return to"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "I3C_AGGR_STATUS_CLR,Return to"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST"
base ad:0x20A8000
rgroup.long 0x00++0x1B
line.long 0x00 "I3C_DEV_ID,Return to"
hexmask.long.word 0x00 16.--31. 1. "RSVD0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "DEV_ID,Unique IP identifier within Cadence IP portfolio"
line.long 0x04 "I3C_CONF_STATUS0,Return to"
bitfld.long 0x04 29.--31. "CMDR_MEM_DEPTH,CMD Resp MEM depth coded into 3 bits" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 24.--28. "ASF,Indicates supported ASF checks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 16.--23. 1. "GPO_NUM,Returns the value of User GPO"
hexmask.long.byte 0x04 8.--15. 1. "GPI_NUM,Returns the value of User GPI"
newline
bitfld.long 0x04 6.--7. "IBIR_MEM_DEPTH,IBI Resp MEM depth coded into 2 bits" "0,1,2,3"
bitfld.long 0x04 5. "DDR,Indicates if DDR is supported" "0,1"
newline
bitfld.long 0x04 4. "DEV_ROLE,Returns status of Device Role [Main/Secondary Master]" "0,1"
bitfld.long 0x04 0.--3. "DEVS_NUM,Returns the number of retaining registers for I3C Slave devices [Addresses and Characteristics] the max value is 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "I3C_CONF_STATUS1,Return to"
bitfld.long 0x08 28.--31. "IBI_HW_RES,IBI resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 26.--27. "CMD_MEM_DEPTH,CMD FIFO depth coded into 3 bits" "0,1,2,3"
newline
bitfld.long 0x08 21.--25. "SLV_DDR_RX_MEM_DEPTH,SLV DDR RX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "SLV_DDR_TX_MEM_DEPTH,SLV DDR TX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 13.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 10.--12. "IBI_MEM_DEPTH,IBI FIFO depth coded into 3 bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 5.--9. "RX_MEM_DEPTH,RX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "TX_MEM_DEPTH,TX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "I3C_REV_ID,Return to"
hexmask.long.word 0x0C 20.--31. 1. "VID,VENDOR_ID: IP vendor ID affected to CadenceIP [reset = 0xCAD]"
hexmask.long.word 0x0C 8.--19. 1. "PID,PRODUCT_ID: unique IP identifier within CDNS IP portfolio [reset = 0x13C]"
newline
bitfld.long 0x0C 5.--7. "REV_MAJOR,X: Major revision value" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--4. "REV_MINOR,Y: Minor revision value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "I3C_CTRL,Return to"
bitfld.long 0x10 31. "DEV_EN,When set HIGH the I3C-Master is enabled and it can initiates the I3C/I2C transactions" "0,1"
bitfld.long 0x10 30. "HALT_EN,Enable halt on abort behavior" "0,1"
newline
bitfld.long 0x10 29. "MCS,Manual Command Start writing 1 starts execution of the commands currently in CMD Memories" "0,1"
bitfld.long 0x10 28. "MCS_EN,Manual Command Start Enable if set 1 the IP will wait with starting of command execution until MCS but [" "0,1"
newline
rbitfld.long 0x10 27. "RSVD2,Reserved" "0,1"
bitfld.long 0x10 26. "I3C_11_SUPP,Enables support for timing parameter that has been changed in v1.1 i.e" "0,1"
newline
bitfld.long 0x10 24.--25. "THD_DEL,Field that provides option to add data hold delay with respect to the SCL clock on which data on SDA is launched [applied only during actual Data transfer]" "0,1,2,3"
hexmask.long.word 0x10 9.--23. 1. "RSVD1,Reserved"
newline
bitfld.long 0x10 8. "HJ_DISEC,This bit controls the HW response for ACK'ed HJ request" "0,1"
bitfld.long 0x10 7. "MST_ACK,Specifies ACK response type for GETACCMST CCC it can be either ACK response type [mst_ack = 1] or NACK response type [mst_ack = 0]" "0,1"
newline
bitfld.long 0x10 6. "HJ_ACK,Specifies ACK response type for HJ request it can be either ACK response type [hj_ack = 1] or NACK response type [hj_ack = 0]" "0,1"
bitfld.long 0x10 5. "HJ_INIT,Initiate HJ request - applicable only for Secondary master in slave mode" "0,1"
newline
bitfld.long 0x10 4. "MST_INIT,Initiate Mastership request - applicable only in slave mode" "0,1"
bitfld.long 0x10 3. "AHDR_OPT,Enable[1]/Disable[0] the Address Header optimization" "0,1"
newline
rbitfld.long 0x10 2. "RSVD0,Reserved" "0,1"
bitfld.long 0x10 0.--1. "BUS_MODE,Bus Mode" "0,1,2,3"
line.long 0x14 "I3C_PRESCL_CTRL0,Return to"
hexmask.long.word 0x14 16.--31. 1. "I2C,Prescaler value for I2C SCL clock generation"
rbitfld.long 0x14 10.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x14 0.--9. 1. "I3C,Prescaler value for I3C Push-Pull SDR Mode SCL clock generation"
line.long 0x18 "I3C_PRESCL_CTRL1,Return to"
hexmask.long.byte 0x18 8.--15. 1. "PP_LOW,Counter for low period of SCL clock for Push Pull in I3C"
hexmask.long.byte 0x18 0.--7. 1. "OD_LOW,Counter for low period of SCL clock for Open Drain in I3C"
group.long 0x20++0x3B
line.long 0x00 "I3C_MST_IER,Return to"
hexmask.long.word 0x00 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x00 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x00 17. "MR_DONE,Mastership handoff done Enable" "0,1"
bitfld.long 0x00 16. "IMM_COMP,Immediate Commmand Completed Enable" "0,1"
newline
bitfld.long 0x00 15. "TX_THR,Tx Data Threshold Enable" "0,1"
bitfld.long 0x00 14. "TX_OVF,Tx Data MEM Underflow Enable" "0,1"
newline
bitfld.long 0x00 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x00 12. "IBID_THR,IBI Data MEM threshold Enable" "0,1"
newline
bitfld.long 0x00 11. "IBID_UNF,IBI Data MEM underflow Enable" "0,1"
bitfld.long 0x00 10. "IBIR_THR,IBI Response Queue threshold Enable" "0,1"
newline
bitfld.long 0x00 9. "IBIR_UNF,IBI Response Queue underflow Enable" "0,1"
bitfld.long 0x00 8. "IBIR_OVF,IBI Response Queue onverflow Enable" "0,1"
newline
bitfld.long 0x00 7. "RX_THR,Rx Data MEM threshold Enable" "0,1"
bitfld.long 0x00 6. "RX_UNF,Rx Data MEM underflow Enable" "0,1"
newline
bitfld.long 0x00 5. "CMDD_EMP,Command Request Queue Empty Enable" "0,1"
bitfld.long 0x00 4. "CMDD_THR,Command Request Queue Threshold Enable" "0,1"
newline
bitfld.long 0x00 3. "CMDD_OVF,Command Request Queue Overflow Enable" "0,1"
bitfld.long 0x00 2. "CMDR_THR,Command Response Queue Threshold Enable" "0,1"
newline
bitfld.long 0x00 1. "CMDR_UNF,Command Response Queue Underflow Enable" "0,1"
bitfld.long 0x00 0. "CMDR_OVF,Command Response Queue Overflow Enable" "0,1"
line.long 0x04 "I3C_MST_IDR,Return to"
hexmask.long.word 0x04 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x04 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x04 17. "MR_DONE,Mastership handoff done Disable" "0,1"
bitfld.long 0x04 16. "IMM_COMP,Immediate Commmand Completed Disable" "0,1"
newline
bitfld.long 0x04 15. "TX_THR,Tx Data Threshold Disable" "0,1"
bitfld.long 0x04 14. "TX_OVF,Tx Data MEM Underflow Disable" "0,1"
newline
bitfld.long 0x04 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x04 12. "IBID_THR,IBI Data MEM threshold Disable" "0,1"
newline
bitfld.long 0x04 11. "IBID_UNF,IBI Data MEM underflow Disable" "0,1"
bitfld.long 0x04 10. "IBIR_THR,IBI Response Queue threshold Disable" "0,1"
newline
bitfld.long 0x04 9. "IBIR_UNF,IBI Response Queue underflow Disable" "0,1"
bitfld.long 0x04 8. "IBIR_OVF,IBI Response Queue onverflow Disable" "0,1"
newline
bitfld.long 0x04 7. "RX_THR,Rx Data MEM threshold Disable" "0,1"
bitfld.long 0x04 6. "RX_UNF,Rx Data MEM underflow Disable" "0,1"
newline
bitfld.long 0x04 5. "CMDD_EMP,Command Request Queue Empty Disable" "0,1"
bitfld.long 0x04 4. "CMDD_THR,Command Request Queue Threshold Disable" "0,1"
newline
bitfld.long 0x04 3. "CMDD_OVF,Command Request Queue Overflow Disable" "0,1"
bitfld.long 0x04 2. "CMDR_THR,Command Response Queue Threshold Disable" "0,1"
newline
bitfld.long 0x04 1. "CMDR_UNF,Command Response Queue Underflow Disable" "0,1"
bitfld.long 0x04 0. "CMDR_OVF,Command Response Queue Overflow Disable" "0,1"
line.long 0x08 "I3C_MST_IMR,Return to"
hexmask.long.word 0x08 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x08 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x08 17. "MR_DONE,Mastership handoff done Mask" "0,1"
bitfld.long 0x08 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1"
newline
bitfld.long 0x08 15. "TX_THR,Tx Data Threshold Mask" "0,1"
bitfld.long 0x08 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1"
newline
bitfld.long 0x08 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x08 12. "IBID_THR,IBI Data MEM threshold Mask" "0,1"
newline
bitfld.long 0x08 11. "IBID_UNF,IBI Data MEM underflow Mask" "0,1"
bitfld.long 0x08 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1"
newline
bitfld.long 0x08 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1"
bitfld.long 0x08 8. "IBIR_OVF,IBI Response Queue onverflow Mask" "0,1"
newline
bitfld.long 0x08 7. "RX_THR,Rx Data MEM threshold Mask" "0,1"
bitfld.long 0x08 6. "RX_UNF,Rx Data MEM underflow Mask" "0,1"
newline
bitfld.long 0x08 5. "CMDD_EMP,Command Request Queue Empty Mask" "0,1"
bitfld.long 0x08 4. "CMDD_THR,Command Request Queue Threshold Mask" "0,1"
newline
bitfld.long 0x08 3. "CMDD_OVF,Command Request Queue Overflow Mask" "0,1"
bitfld.long 0x08 2. "CMDR_THR,Command Response Queue Threshold Mask" "0,1"
newline
bitfld.long 0x08 1. "CMDR_UNF,Command Response Queue Underflow Mask" "0,1"
bitfld.long 0x08 0. "CMDR_OVF,Command Response Queue Overflow Mask" "0,1"
line.long 0x0C "I3C_MST_ICR,Return to"
hexmask.long.word 0x0C 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x0C 18. "HALTED,Controller is in halted state" "0,1"
newline
bitfld.long 0x0C 17. "MR_DONE,Mastership handoff done Mask" "0,1"
bitfld.long 0x0C 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1"
newline
bitfld.long 0x0C 15. "TX_THR,Tx Data Threshold Mask" "0,1"
bitfld.long 0x0C 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1"
newline
bitfld.long 0x0C 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x0C 12. "IBID_THR,IBI Data MEM threshold Mask" "0,1"
newline
bitfld.long 0x0C 11. "IBID_UNF,IBI Data MEM underflow Mask" "0,1"
bitfld.long 0x0C 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1"
newline
bitfld.long 0x0C 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1"
bitfld.long 0x0C 8. "IBIR_OVF,IBI Response Queue onverflow Mask" "0,1"
newline
bitfld.long 0x0C 7. "RX_THR,Rx Data MEM threshold Mask" "0,1"
bitfld.long 0x0C 6. "RX_UNF,Rx Data MEM underflow Mask" "0,1"
newline
bitfld.long 0x0C 5. "CMDD_EMP,Command Request Queue Empty Mask" "0,1"
bitfld.long 0x0C 4. "CMDD_THR,Command Request Queue Threshold Mask" "0,1"
newline
bitfld.long 0x0C 3. "CMDD_OVF,Command Request Queue Overflow Mask" "0,1"
bitfld.long 0x0C 2. "CMDR_THR,Command Response Queue Threshold Mask" "0,1"
newline
bitfld.long 0x0C 1. "CMDR_UNF,Command Response Queue Underflow Mask" "0,1"
bitfld.long 0x0C 0. "CMDR_OVF,Command Response Queue Overflow Mask" "0,1"
line.long 0x10 "I3C_MST_ISR,Return to"
hexmask.long.word 0x10 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x10 18. "HALTED,Controller in Halted state" "0,1"
newline
bitfld.long 0x10 17. "MR_DONE,Mastership handoff done" "0,1"
bitfld.long 0x10 16. "IMM_COMP,Immediate Commmand Completed" "0,1"
newline
bitfld.long 0x10 15. "TX_THR,Tx Data Threshold" "0,1"
bitfld.long 0x10 14. "TX_OVF,Tx Data MEM overflow" "0,1"
newline
bitfld.long 0x10 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x10 12. "IBID_THR,IBI Data MEM threshold" "0,1"
newline
bitfld.long 0x10 11. "IBID_UNF,IBI Data MEM underflow" "0,1"
bitfld.long 0x10 10. "IBIR_THR,IBI Response Queue threshold" "0,1"
newline
bitfld.long 0x10 9. "IBIR_UNF,IBI Response Queue underflow" "0,1"
bitfld.long 0x10 8. "IBIR_OVF,IBI Response Queue onverflow" "0,1"
newline
bitfld.long 0x10 7. "RX_THR,Rx Data MEM threshold" "0,1"
bitfld.long 0x10 6. "RX_UNF,Rx Data MEM underflow" "0,1"
newline
bitfld.long 0x10 5. "CMDD_EMP,Command Request Queue Empty" "0,1"
bitfld.long 0x10 4. "CMDD_THR,Command Request Queue Threshold" "0,1"
newline
bitfld.long 0x10 3. "CMDD_OVF,Command Request Queue Overflow" "0,1"
bitfld.long 0x10 2. "CMDR_THR,Command Response Queue Threshold" "0,1"
newline
bitfld.long 0x10 1. "CMDR_UNF,Command Response Queue Underflow" "0,1"
bitfld.long 0x10 0. "CMDR_OVF,Command Response Queue Overflow" "0,1"
line.long 0x14 "I3C_MST_STATUS0,Return to"
hexmask.long.word 0x14 19.--31. 1. "RSVD2,Reserved"
rbitfld.long 0x14 18. "IDLE,Indicates when the core is IDLE and ready to accept new commands" "0,1"
newline
bitfld.long 0x14 17. "HALTED,Core Halted" "0,1"
rbitfld.long 0x14 16. "OP_MODE,Indicates current mode of the controller" "0,1"
newline
rbitfld.long 0x14 14.--15. "RSVD1,Reserved" "0,1,2,3"
rbitfld.long 0x14 13. "TX_FULL,TX Full" "0,1"
newline
rbitfld.long 0x14 12. "IBID_FULL,IBID Full" "0,1"
rbitfld.long 0x14 11. "IBIR_FULL," "0,1"
newline
rbitfld.long 0x14 10. "RX_FULL,RX Full" "0,1"
rbitfld.long 0x14 9. "CMDD_FULL,CMDD Full" "0,1"
newline
rbitfld.long 0x14 8. "CMDR_FULL," "0,1"
rbitfld.long 0x14 6.--7. "RSVD0,Reserved" "0,1,2,3"
newline
rbitfld.long 0x14 5. "TX_EMP,TX Empty" "0,1"
rbitfld.long 0x14 4. "IBID_EMP,IBID Empty" "0,1"
newline
rbitfld.long 0x14 3. "IBIR_EMP," "0,1"
rbitfld.long 0x14 2. "RX_EMP,RX Empty" "0,1"
newline
rbitfld.long 0x14 1. "CMDD_EMP,CMDD Empty" "0,1"
rbitfld.long 0x14 0. "CMDR_EMP," "0,1"
line.long 0x18 "I3C_CMDR,Return to"
bitfld.long 0x18 28.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "ERROR,This field contains the code of an error that has occured during the last transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 8.--19. 1. "XFER_BYTES,The number of transferred bytes [SDR] or transferred words [DDR] during the last command"
newline
hexmask.long.byte 0x18 0.--7. 1. "CMD_ID,CMD_ID - command identifier"
line.long 0x1C "I3C_IBIR,Return to"
hexmask.long.tbyte 0x1C 13.--31. 1. "RSVD0,Reserved"
bitfld.long 0x1C 12. "RESP,If HIGH IBI has been ACKed NACK response otherwise" "0,1"
newline
bitfld.long 0x1C 8.--11. "SLV_ID,ID of a Slave that has issued an IBI request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 7. "ERROR,Set to 1 if IBI Data FIFO overflow has occured during the transaction" "0,1"
newline
bitfld.long 0x1C 2.--6. "XFER_BYTES,Number of received DATA bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--1. "IBI_TYPE,This field contains the type of an IBI" "0,1,2,3"
line.long 0x20 "I3C_SLV_IER,Return to"
bitfld.long 0x20 21. "DEFSLVS,DEFSLVS interrupt Enable" "0,1"
bitfld.long 0x20 20. "TM,TM interrupt Enable" "0,1"
newline
bitfld.long 0x20 19. "ERROR,ERROR interrupt Enable" "0,1"
bitfld.long 0x20 18. "EVENT_UP,EVENT_UP interrupt Enable" "0,1"
newline
bitfld.long 0x20 17. "HJ_DONE,HJ_DONE interrupt Enable" "0,1"
bitfld.long 0x20 16. "MR_DONE,MR_DONE interrupt Enable" "0,1"
newline
bitfld.long 0x20 15. "DA_UPDATE,DA_UPDATE interrupt Enable" "0,1"
bitfld.long 0x20 14. "SDR_FAIL,SDR_FAIL interrupt Enable" "0,1"
newline
bitfld.long 0x20 13. "DDR_FAIL,DDR_FAIL interrupt Enable" "0,1"
bitfld.long 0x20 12. "M_RD_ABORT,M_RD_ABORT interrupt Enable" "0,1"
newline
bitfld.long 0x20 11. "DDR_RX_THR,DDR_RX_THR interrupt Enable" "0,1"
bitfld.long 0x20 10. "DDR_TX_THR,DDR_TX_THR interrupt Enable" "0,1"
newline
bitfld.long 0x20 9. "SDR_RX_THR,SDR_RX_THR interrupt Enable" "0,1"
bitfld.long 0x20 8. "SDR_TX_THR,SLV_SDR_TX_THR interrupt Enable" "0,1"
newline
bitfld.long 0x20 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Enable" "0,1"
bitfld.long 0x20 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Enable" "0,1"
newline
bitfld.long 0x20 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Enable" "0,1"
bitfld.long 0x20 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Enable" "0,1"
newline
bitfld.long 0x20 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Enable" "0,1"
bitfld.long 0x20 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Enable" "0,1"
newline
bitfld.long 0x20 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Enable" "0,1"
bitfld.long 0x20 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Enable" "0,1"
line.long 0x24 "I3C_SLV_IDR,Return to"
bitfld.long 0x24 21. "DEFSLVS,DEFSLVS interrupt Disable" "0,1"
bitfld.long 0x24 20. "TM,TM interrupt Disable" "0,1"
newline
bitfld.long 0x24 19. "ERROR,ERROR interrupt Disable" "0,1"
bitfld.long 0x24 18. "EVENT_UP,EVENT_UP interrupt Disable" "0,1"
newline
bitfld.long 0x24 17. "HJ_DONE,HJ_DONE interrupt Disable" "0,1"
bitfld.long 0x24 16. "MR_DONE,MR_DONE interrupt Disable" "0,1"
newline
bitfld.long 0x24 15. "DA_UPDATE,DA_UPDATE interrupt Disable" "0,1"
bitfld.long 0x24 14. "SDR_FAIL,SDR_FAIL interrupt Disable" "0,1"
newline
bitfld.long 0x24 13. "DDR_FAIL,DDR_FAIL interrupt Disable" "0,1"
bitfld.long 0x24 12. "M_RD_ABORT,M_RD_ABORT interrupt Disable" "0,1"
newline
bitfld.long 0x24 11. "DDR_RX_THR,DDR_RX_THR interrupt Disable" "0,1"
bitfld.long 0x24 10. "DDR_TX_THR,DDR_TX_THR interrupt Disable" "0,1"
newline
bitfld.long 0x24 9. "SDR_RX_THR,SDR_RX_THR interrupt Disable" "0,1"
bitfld.long 0x24 8. "SDR_TX_THR,SDR_TX_THR interrupt Disable" "0,1"
newline
bitfld.long 0x24 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Disable" "0,1"
bitfld.long 0x24 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Disable" "0,1"
newline
bitfld.long 0x24 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Disable" "0,1"
bitfld.long 0x24 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Disable" "0,1"
newline
bitfld.long 0x24 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Disable" "0,1"
bitfld.long 0x24 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Disable" "0,1"
newline
bitfld.long 0x24 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Disable" "0,1"
bitfld.long 0x24 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Disable" "0,1"
line.long 0x28 "I3C_SLV_IMR,Return to"
bitfld.long 0x28 21. "DEFSLVS,DEFSLVS interrupt Mask" "0,1"
bitfld.long 0x28 20. "TM,TM interrupt Mask" "0,1"
newline
bitfld.long 0x28 19. "ERROR,ERROR interrupt Mask" "0,1"
bitfld.long 0x28 18. "EVENT_UP,EVENT_UP interrupt Mask" "0,1"
newline
bitfld.long 0x28 17. "HJ_DONE,HJ_DONE interrupt Mask" "0,1"
bitfld.long 0x28 16. "MR_DONE,MR_DONE interrupt Mask" "0,1"
newline
bitfld.long 0x28 15. "DA_UPDATE,DA_UPDATE interrupt Mask" "0,1"
bitfld.long 0x28 14. "SDR_FAIL,SDR_FAIL interrupt Mask" "0,1"
newline
bitfld.long 0x28 13. "DDR_FAIL,DDR_FAIL interrupt Mask" "0,1"
bitfld.long 0x28 12. "M_RD_ABORT,M_RD_ABORT interrupt Mask" "0,1"
newline
bitfld.long 0x28 11. "DDR_RX_THR,DDR_RX_THR interrupt Mask" "0,1"
bitfld.long 0x28 10. "DDR_TX_THR,DDR_TX_THR interrupt Mask" "0,1"
newline
bitfld.long 0x28 9. "SDR_RX_THR,SDR_RX_THR interrupt Mask" "0,1"
bitfld.long 0x28 8. "SDR_TX_THR,SDR_TX_THR interrupt Mask" "0,1"
newline
bitfld.long 0x28 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Mask" "0,1"
bitfld.long 0x28 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Mask" "0,1"
newline
bitfld.long 0x28 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Mask" "0,1"
bitfld.long 0x28 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Mask" "0,1"
newline
bitfld.long 0x28 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Mask" "0,1"
bitfld.long 0x28 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Mask" "0,1"
newline
bitfld.long 0x28 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Mask" "0,1"
bitfld.long 0x28 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Mask" "0,1"
line.long 0x2C "I3C_SLV_ICR,Return to"
bitfld.long 0x2C 21. "DEFSLVS,DEFSLVS interrupt Clear" "0,1"
bitfld.long 0x2C 20. "TM,TM interrupt Clear" "0,1"
newline
bitfld.long 0x2C 19. "ERROR,ERROR interrupt Clear" "0,1"
bitfld.long 0x2C 18. "EVENT_UP,EVENT_UP interrupt Clear" "0,1"
newline
bitfld.long 0x2C 17. "HJ_DONE,HJ_DONE interrupt Clear" "0,1"
bitfld.long 0x2C 16. "MR_DONE,MR_DONE interrupt Clear" "0,1"
newline
bitfld.long 0x2C 15. "DA_UPDATE,DA_UPDATE interrupt Clear" "0,1"
bitfld.long 0x2C 14. "SDR_FAIL,SDR_FAIL interrupt Clear" "0,1"
newline
bitfld.long 0x2C 13. "DDR_FAIL,DDR_FAIL interrupt Clear" "0,1"
bitfld.long 0x2C 12. "M_RD_ABORT,M_RD_ABORT interrupt Clear" "0,1"
newline
bitfld.long 0x2C 11. "DDR_RX_THR,DDR_RX_THR interrupt Clear" "0,1"
bitfld.long 0x2C 10. "DDR_TX_THR,DDR_TX_THR interrupt Clear" "0,1"
newline
bitfld.long 0x2C 9. "SDR_RX_THR,SDR_RX_THR interrupt Clear" "0,1"
bitfld.long 0x2C 8. "SDR_TX_THR,SDR_TX_THR interrupt Clear" "0,1"
newline
bitfld.long 0x2C 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Clear" "0,1"
bitfld.long 0x2C 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Clear" "0,1"
newline
bitfld.long 0x2C 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Clear" "0,1"
bitfld.long 0x2C 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Clear" "0,1"
newline
bitfld.long 0x2C 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Clear" "0,1"
bitfld.long 0x2C 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Clear" "0,1"
newline
bitfld.long 0x2C 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Clear" "0,1"
bitfld.long 0x2C 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Clear" "0,1"
line.long 0x30 "I3C_SLV_ISR,Return to"
bitfld.long 0x30 21. "DEFSLVS,This interrupt is triggered whenever I3C-Slave DEFSLVS CCC command is received" "0,1"
bitfld.long 0x30 20. "TM,This interrupt is triggered whenever I3C-Slave is not in Test Mode and ENTTM CCC command with byte value of 0x01 [general Test Mode] is received" "0,1"
newline
bitfld.long 0x30 19. "ERROR,This event is triggered whenever SDR Error is detected - applicable for S0 S1 S2 S4 and S5 Errors from MIPI spec" "0,1"
bitfld.long 0x30 18. "EVENT_UP,This event is triggered whenever DISEC CCC or ENEC CCC is received" "0,1"
newline
bitfld.long 0x30 17. "HJ_DONE,This event is triggered whenever Hot-Join request is completed" "0,1"
bitfld.long 0x30 16. "MR_DONE,This event is triggered whenever Mastership Request is completed" "0,1"
newline
bitfld.long 0x30 15. "DA_UPDATE,This event is triggered whenever Dynamic Address of the device has been updated" "0,1"
bitfld.long 0x30 14. "SDR_FAIL,This event is triggered whenever fail event during SDR transfer is detected [applicable for Private Write transfers only]" "0,1"
newline
bitfld.long 0x30 13. "DDR_FAIL,This event is triggered whenever fail event during DDR transfer is detected" "0,1"
bitfld.long 0x30 12. "M_RD_ABORT,Read Transfer Aborted by Master" "0,1"
newline
bitfld.long 0x30 11. "DDR_RX_THR,This event is triggered whenever threshold level for DDR Rx DATA Buffer is reached" "0,1"
bitfld.long 0x30 10. "DDR_TX_THR,This event is triggered whenever threshold level for DDR Tx DATA Buffer is reached" "0,1"
newline
bitfld.long 0x30 9. "SDR_RX_THR,Rx DATA Buffer Threshold" "0,1"
bitfld.long 0x30 8. "SDR_TX_THR,Tx DATA Buffer Threshold" "0,1"
newline
bitfld.long 0x30 7. "DDR_RX_UNF,Set if the host attempts to read from the DDR_RX_FIFO register when there is no more data" "0,1"
bitfld.long 0x30 6. "DDR_TX_OVF,Set if the host attempts to write to DDR_TX_FIFO register more times than the FIFO depth" "0,1"
newline
bitfld.long 0x30 5. "SDR_RX_UNF,Rx DATA Buffer Underflow" "0,1"
bitfld.long 0x30 4. "SDR_TX_OVF,Tx DATA Buffer Overflow" "0,1"
newline
bitfld.long 0x30 3. "DDR_RD_COMP,This bit is set whenever the Slave terminates the DDR Read transfer" "0,1"
bitfld.long 0x30 2. "DDR_WR_COMP,This bit is set whenever the Master terminates the DDR Write transfer" "0,1"
newline
bitfld.long 0x30 1. "SDR_RD_COMP,This bit is set whenever the Slave terminates the SDR Private Read transfer" "0,1"
bitfld.long 0x30 0. "SDR_WR_COMP,This bit is set whenever the Master terminates the SDR Private Write transfer" "0,1"
line.long 0x34 "I3C_SLV_STATUS0,Return to"
hexmask.long.byte 0x34 24.--31. 1. "RSVD0,Reserved"
hexmask.long.byte 0x34 16.--23. 1. "REG_ADDR,Private Read/Write Address"
newline
hexmask.long.word 0x34 0.--15. 1. "XFERRED_BYTES,Number of transferred bytes in SDR transactions"
line.long 0x38 "I3C_SLV_STATUS1,Return to"
hexmask.long.word 0x38 22.--31. 1. "RSVD1,Reserved"
bitfld.long 0x38 20.--21. "ENTAS,Bits that indicate current Activity State" "0,1,2,3"
newline
bitfld.long 0x38 19. "VEN_TM,Vendor Test Mode" "0,1"
bitfld.long 0x38 18. "HJ_DIS,Hot-Join Disabled" "0,1"
newline
bitfld.long 0x38 17. "MR_DIS,This bit is set whenever MR request is disabled by Current I3C-Master using DISEC CCC" "0,1"
bitfld.long 0x38 16. "PROT_ERROR,Protocol Error Condition Indicator" "0,1"
newline
hexmask.long.byte 0x38 9.--15. 1. "DA,Slave Dynamic Address"
bitfld.long 0x38 8. "HAS_DA,This bit is set whenever Slave has Dynamic Address assigned" "0,1"
newline
bitfld.long 0x38 7. "DDRRX_FULL,This bit is set whenever" "0,1"
bitfld.long 0x38 6. "DDRTX_FULL,This bit is set whenever" "0,1"
newline
bitfld.long 0x38 5. "DDRRX_EMPTY,This bit is set whenever" "0,1"
bitfld.long 0x38 4. "DDRTX_EMPTY,This bit is set whenever" "0,1"
newline
bitfld.long 0x38 3. "SDRRX_FULL,This bit is set whenever SDR_RX_FIFO is full" "0,1"
bitfld.long 0x38 2. "SDRTX_FULL,This bit is set whenever SDR_TX_FIFO is full" "0,1"
newline
bitfld.long 0x38 1. "SDRRX_EMPTY,This bit is set whenever SDR_RX_FIFO is empty" "0,1"
bitfld.long 0x38 0. "SDRTX_EMPTY,This bit is set whenever SDR_TX_FIFO is empty" "0,1"
group.long 0x60++0x0B
line.long 0x00 "I3C_CMD0_FIFO,Return to"
bitfld.long 0x00 31. "IS_DDR,IS_DDR - DDR command" "0,1"
bitfld.long 0x00 30. "IS_CCC,IsCCC" "0,1"
newline
bitfld.long 0x00 29. "BCH,BCH - Broadcast Header" "0,1"
bitfld.long 0x00 27.--28. "XMIT_MODE,Defines transfer modes for I3C private read/write commands [not CCC] the following options are available" "0,1,2,3"
newline
bitfld.long 0x00 26. "SBCA,SBCA - Sixteen Bits CSR Addressing" "0,1"
bitfld.long 0x00 25. "RSBC,RSBC - Repeated Start Between Commands" "0,1"
newline
bitfld.long 0x00 24. "IS10B,Is10B - Normal/Extended Address" "0,1"
hexmask.long.word 0x00 12.--23. 1. "PL_LEN,PL_LEN - Payload Length"
newline
bitfld.long 0x00 8.--10. "DEV_ADDR_MSB,DEV_ADDR_MSB - legacy I2C Extended Address" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address"
newline
bitfld.long 0x00 0. "RNW,RnW - Read no" "0,1"
line.long 0x04 "I3C_CMD1_FIFO,Return to"
hexmask.long.byte 0x04 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]"
hexmask.long.byte 0x04 16.--23. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x04 8.--15. 1. "CSRADDR1,CSR ADDR"
hexmask.long.byte 0x04 0.--7. 1. "CCC_CSRADDR0,CCC/CSR ADDR"
line.long 0x08 "I3C_TX_FIFO,Return to"
group.long 0x70++0x0B
line.long 0x00 "I3C_IMD_CMD0,Return to"
bitfld.long 0x00 12.--14. "PL_LEN,PL_LEN - Payload Length" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address"
newline
bitfld.long 0x00 0. "RNW,RnW - Read no" "0,1"
line.long 0x04 "I3C_IMD_CMD1,Return to"
hexmask.long.byte 0x04 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]"
hexmask.long.word 0x04 8.--23. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x04 0.--7. 1. "CCC,CCC code"
line.long 0x08 "I3C_IMD_DATA,Return to"
rgroup.long 0x80++0x1F
line.long 0x00 "I3C_RX_FIFO,Return to"
line.long 0x04 "I3C_IBI_DATA_FIFO,Return to"
line.long 0x08 "I3C_SLV_DDR_TX_FIFO,Return to"
hexmask.long.tbyte 0x08 0.--19. 1. "DDR_SLAVE_TX_DATA_FIFO,DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode"
line.long 0x0C "I3C_SLV_DDR_RX_FIFO,Return to"
hexmask.long.tbyte 0x0C 0.--19. 1. "DDR_SLAVE_RX_DATA_FIFO,DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode"
line.long 0x10 "I3C_CMD_IBI_THR_CTRL,Return to"
rbitfld.long 0x10 30.--31. "RSVD3,Reserved" "0,1,2,3"
bitfld.long 0x10 24.--29. "IBIR_THR,Threshold configuration value for IBI RESP memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--20. "CMDR_THR,Threshold configuration value for Command RESP memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x10 14.--15. "RSVD1,Reserved" "0,1,2,3"
bitfld.long 0x10 8.--13. "IBID_THR,Threshold configuration value for IBI DATA memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 5.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--4. "CMDD_THR,Threshold configuration value for Command REQ memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "I3C_TX_RX_THR_CTRL,Return to"
hexmask.long.word 0x14 16.--31. 1. "RX_THR,Threshold configuration value for Rx Data memory block"
hexmask.long.word 0x14 0.--15. 1. "TX_THR,Threshold configuration value for Tx Data memory block"
line.long 0x18 "I3C_SLV_DDR_TX_RX_THR_CTRL,Return to"
hexmask.long.word 0x18 16.--31. 1. "SLV_DDR_RX_THR,Threshold configuration value for Slave Mode DDR Rx Data memory block"
hexmask.long.word 0x18 0.--15. 1. "SLV_DDR_TX_THR,Threshold configuration value for Slave Mode DDR Tx Data memory block"
line.long 0x1C "I3C_FLUSH_CTRL,Return to"
bitfld.long 0x1C 24. "IBI_RESP_FLUSH,When asserted while controller is disabled the IBI Response Queue read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
bitfld.long 0x1C 23. "CMD_RESP_FLUSH,When asserted while controller is disabled the Command Response Queue read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
newline
bitfld.long 0x1C 22. "SLV_DDR_RX_FLUSH,When asserted while controller is disabled the SLV DDR Rx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
bitfld.long 0x1C 21. "SLV_DDR_TX_FLUSH,When asserted while controller is disabled the SLV DDR Tx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
newline
bitfld.long 0x1C 20. "IMM_CMD_FLUSH,When asserted while controller is disabled the immediate command/data register will be cleared" "0,1"
bitfld.long 0x1C 19. "IBI_FLUSH,When asserted while controller is disabled the IBI data memory block read/write pointers will be set to 0" "0,1"
newline
bitfld.long 0x1C 18. "RX_FLUSH,When asserted while controller is disabled the Rx Data memory block read/write pointers will be set to 0" "0,1"
bitfld.long 0x1C 17. "TX_FLUSH,When asserted while controller is disabled the Tx Data memory block read/write pointers will be set to 0" "0,1"
newline
bitfld.long 0x1C 16. "CMD_FLUSH,When asserted while controller is disabled the command Command memory block read/write pointers will be set to 0" "0,1"
group.long 0xB0++0x0B
line.long 0x00 "I3C_TTO_PRESCL_CTRL0,Return to"
rbitfld.long 0x00 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "DIV_B,Divider B"
newline
rbitfld.long 0x00 11.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "DIV_A,Divider A"
line.long 0x04 "I3C_TTO_PRESCL_CTRL1,Return to"
rbitfld.long 0x04 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x04 16.--25. 1. "DIV_B,Divider B"
newline
hexmask.long.byte 0x04 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "DIV_A,Divider A"
line.long 0x08 "I3C_DEVS_CTRL,Return to"
rbitfld.long 0x08 28.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 27. "DEV11_CLR,Clear DevID11 retaining registers set" "0,1"
newline
bitfld.long 0x08 26. "DEV10_CLR,Clear DevID10 retaining registers set" "0,1"
bitfld.long 0x08 25. "DEV9_CLR,Clear DevID9 retaining registers set" "0,1"
newline
bitfld.long 0x08 24. "DEV8_CLR,Clear DevID8 retaining registers set" "0,1"
bitfld.long 0x08 23. "DEV7_CLR,Clear DevID7 retaining registers set" "0,1"
newline
bitfld.long 0x08 22. "DEV6_CLR,Clear DevID6 retaining registers set" "0,1"
bitfld.long 0x08 21. "DEV5_CLR,Clear DevID5 retaining registers set" "0,1"
newline
bitfld.long 0x08 20. "DEV4_CLR,Clear DevID4 retaining registers set" "0,1"
bitfld.long 0x08 19. "DEV3_CLR,Clear DevID3 retaining registers set" "0,1"
newline
bitfld.long 0x08 18. "DEV2_CLR,Clear DevID2 retaining registers set" "0,1"
bitfld.long 0x08 17. "DEV1_CLR,Clear DevID1 retaining registers set" "0,1"
newline
rbitfld.long 0x08 12.--16. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 11. "DEV11_ACTIVE,DevID11 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 10. "DEV10_ACTIVE,DevID10 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 9. "DEV9_ACTIVE,DevID9 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 8. "DEV8_ACTIVE,DevID8 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 7. "DEV7_ACTIVE,DevID7 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 6. "DEV6_ACTIVE,DevID6 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 5. "DEV5_ACTIVE,DevID5 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 4. "DEV4_ACTIVE,DevID4 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 3. "DEV3_ACTIVE,DevID3 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 2. "DEV2_ACTIVE,DevID2 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 1. "DEV1_ACTIVE,DevID1 is active - has either valid DA or SA" "0,1"
newline
rbitfld.long 0x08 0. "DEV0_ACTIVE,DevID0 is active - has either valid DA or SA" "0,1"
group.long 0xC0++0x0B
line.long 0x00 "I3C_DEV_ID0_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 0 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "IS_I3C,Device 0 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 0 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID0_RR1,Return to"
line.long 0x08 "I3C_DEV_ID0_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 0 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 0 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 0 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xD0++0x0B
line.long 0x00 "I3C_DEV_ID1_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 1 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 1 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 1 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID1_RR1,Return to"
line.long 0x08 "I3C_DEV_ID1_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 1 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 1 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 1 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xE0++0x0B
line.long 0x00 "I3C_DEV_ID2_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 2 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 2 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 2 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID2_RR1,Return to"
line.long 0x08 "I3C_DEV_ID2_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 2 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 2 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 2 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xF0++0x0B
line.long 0x00 "I3C_DEV_ID3_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 3 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 3 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 3 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID3_RR1,Return to"
line.long 0x08 "I3C_DEV_ID3_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 3 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 3 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 3 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x100++0x0B
line.long 0x00 "I3C_DEV_ID4_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 4 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 4 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 4 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID4_RR1,Return to"
line.long 0x08 "I3C_DEV_ID4_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 4 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 4 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 4 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x110++0x0B
line.long 0x00 "I3C_DEV_ID5_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 5 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 5 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 5 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID5_RR1,Return to"
line.long 0x08 "I3C_DEV_ID5_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 5 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 5 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 5 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x120++0x0B
line.long 0x00 "I3C_DEV_ID6_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 6 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 6 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 6 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID6_RR1,Return to"
line.long 0x08 "I3C_DEV_ID6_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 6 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 6 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 6 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x130++0x0B
line.long 0x00 "I3C_DEV_ID7_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 7 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 7 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 7 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID7_RR1,Return to"
line.long 0x08 "I3C_DEV_ID7_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 7 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 7 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 7 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x140++0x0B
line.long 0x00 "I3C_DEV_ID8_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 8 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 8 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 8 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID8_RR1,Return to"
line.long 0x08 "I3C_DEV_ID8_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 8 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 8 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 8 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x150++0x0B
line.long 0x00 "I3C_DEV_ID9_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 9 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 9 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 9 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID9_RR1,Return to"
line.long 0x08 "I3C_DEV_ID9_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 9 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 9 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 9 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x160++0x0B
line.long 0x00 "I3C_DEV_ID10_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 10 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 10 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 10 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID10_RR1,Return to"
line.long 0x08 "I3C_DEV_ID10_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 10 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 10 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 10 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x170++0x0B
line.long 0x00 "I3C_DEV_ID11_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 11 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 11 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 11 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID11_RR1,Return to"
line.long 0x08 "I3C_DEV_ID11_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 11 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 11 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 11 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x180++0x17
line.long 0x00 "I3C_SIR_MAP0,Return to"
bitfld.long 0x00 30.--31. "DEVID1_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3"
bitfld.long 0x00 29. "DEVID1_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x00 24.--28. "DEVID1_PL,Slave-initiated request Device ID0 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 17.--23. 1. "DEVID1_DA,Slave-initiated request Device ID0 DA"
newline
bitfld.long 0x00 16. "DEVID1_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1"
bitfld.long 0x00 14.--15. "DEVID0_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3"
newline
bitfld.long 0x00 13. "DEVID0_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1"
bitfld.long 0x00 8.--12. "DEVID0_PL,Slave-initiated request Device ID0 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 1.--7. 1. "DEVID0_DA,Slave-initiated request Device ID0 DA"
bitfld.long 0x00 0. "DEVID0_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1"
line.long 0x04 "I3C_SIR_MAP1,Return to"
bitfld.long 0x04 30.--31. "DEVID3_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3"
bitfld.long 0x04 29. "DEVID3_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x04 24.--28. "DEVID3_PL,Slave-initiated request Device ID2 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x04 17.--23. 1. "DEVID3_DA,Slave-initiated request Device ID2 DA"
newline
bitfld.long 0x04 16. "DEVID3_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1"
bitfld.long 0x04 14.--15. "DEVID2_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3"
newline
bitfld.long 0x04 13. "DEVID2_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1"
bitfld.long 0x04 8.--12. "DEVID2_PL,Slave-initiated request Device ID2 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 1.--7. 1. "DEVID2_DA,Slave-initiated request Device ID2 DA"
bitfld.long 0x04 0. "DEVID2_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1"
line.long 0x08 "I3C_SIR_MAP2,Return to"
bitfld.long 0x08 30.--31. "DEVID5_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3"
bitfld.long 0x08 29. "DEVID5_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x08 24.--28. "DEVID5_PL,Slave-initiated request Device ID4 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x08 17.--23. 1. "DEVID5_DA,Slave-initiated request Device ID4 DA"
newline
bitfld.long 0x08 16. "DEVID5_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1"
bitfld.long 0x08 14.--15. "DEVID4_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3"
newline
bitfld.long 0x08 13. "DEVID4_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1"
bitfld.long 0x08 8.--12. "DEVID4_PL,Slave-initiated request Device ID4 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x08 1.--7. 1. "DEVID4_DA,Slave-initiated request Device ID4 DA"
bitfld.long 0x08 0. "DEVID4_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1"
line.long 0x0C "I3C_SIR_MAP3,Return to"
bitfld.long 0x0C 30.--31. "DEVID7_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3"
bitfld.long 0x0C 29. "DEVID7_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x0C 24.--28. "DEVID7_PL,Slave-initiated request Device ID6 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 17.--23. 1. "DEVID7_DA,Slave-initiated request Device ID6 DA"
newline
bitfld.long 0x0C 16. "DEVID7_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1"
bitfld.long 0x0C 14.--15. "DEVID6_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3"
newline
bitfld.long 0x0C 13. "DEVID6_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1"
bitfld.long 0x0C 8.--12. "DEVID6_PL,Slave-initiated request Device ID6 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x0C 1.--7. 1. "DEVID6_DA,Slave-initiated request Device ID6 DA"
bitfld.long 0x0C 0. "DEVID6_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1"
line.long 0x10 "I3C_SIR_MAP4,Return to"
bitfld.long 0x10 30.--31. "DEVID9_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3"
bitfld.long 0x10 29. "DEVID9_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x10 24.--28. "DEVID9_PL,Slave-initiated request Device ID8 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x10 17.--23. 1. "DEVID9_DA,Slave-initiated request Device ID8 DA"
newline
bitfld.long 0x10 16. "DEVID9_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1"
bitfld.long 0x10 14.--15. "DEVID8_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3"
newline
bitfld.long 0x10 13. "DEVID8_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1"
bitfld.long 0x10 8.--12. "DEVID8_PL,Slave-initiated request Device ID8 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x10 1.--7. 1. "DEVID8_DA,Slave-initiated request Device ID8 DA"
bitfld.long 0x10 0. "DEVID8_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1"
line.long 0x14 "I3C_SIR_MAP5,Return to"
bitfld.long 0x14 14.--15. "DEVID10_ROLE,Slave-initiated request Device ID10 BCR role" "0,1,2,3"
bitfld.long 0x14 13. "DEVID10_SLOW,Slave-initiated request Device ID10 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x14 8.--12. "DEVID10_PL,Slave-initiated request Device ID10 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 1.--7. 1. "DEVID10_DA,Slave-initiated request Device ID10 DA"
newline
bitfld.long 0x14 0. "DEVID10_RESP,Slave-initiated request Device ID10 Ack/Nack response" "0,1"
rgroup.long 0x1A0++0x03
line.long 0x00 "I3C_GPIR_WORD0,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RSVD2,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "GPI0,User Defined GPI Register 0"
rgroup.long 0x220++0x03
line.long 0x00 "I3C_GPOR_WORD0,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RSVD2,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "GPO0,User Defined GPO Register 0"
group.long 0x300++0x13
line.long 0x00 "I3C_ASF_INT_STATUS,Return to"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "I3C_ASF_INT_RAW_STATUS,Return to"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "I3C_ASF_INT_MASK,Return to"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "I3C_ASF_INT_TEST,Return to"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "I3C_ASF_FATAL_NONFATAL_SELECT,Return to"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x320++0x0B
line.long 0x00 "I3C_ASF_SRAM_CORR_FAULT_STATUS,Return to"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "I3C_ASF_SRAM_UNCORR_FAULT_STATUS,Return to"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "I3C_ASF_SRAM_FAULT_STATS,Return to"
hexmask.long.word 0x08 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x330++0x0B
line.long 0x00 "I3C_ASF_TRANS_TO_CTRL,Return to"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "I3C_ASF_TRANS_TO_FAULT_MASK,Return to"
bitfld.long 0x04 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask bit for apb transaction timeout fault" "0,1"
bitfld.long 0x04 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for I3C transaction SCL low timeout fault" "0,1"
newline
bitfld.long 0x04 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for I3C transaction SCL high timeout fault" "0,1"
bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for I3C transaction first SCL high timeout fault" "0,1"
line.long 0x08 "I3C_ASF_TRANS_TO_FAULT_STATUS,Return to"
bitfld.long 0x08 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for apb transaction timeout fault" "0,1"
bitfld.long 0x08 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for I3C transaction SCL low timeout fault" "0,1"
newline
bitfld.long 0x08 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for I3C transaction SCL high timeout fault" "0,1"
bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for I3C transaction first SCL high timeout fault" "0,1"
group.long 0x340++0x07
line.long 0x00 "I3C_ASF_PROTOCOL_FAULT_MASK,Return to"
bitfld.long 0x00 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_MASK,Mask bit for slv_sdr_rd_abort protocol fault source" "0,1"
bitfld.long 0x00 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_MASK,Mask bit for slv_ddr_fail protocol fault source" "0,1"
newline
bitfld.long 0x00 10. "ASF_PROTOCOL_FAULT_S5_MASK,Mask bit for s5 protocol fault source" "0,1"
bitfld.long 0x00 9. "ASF_PROTOCOL_FAULT_S4_MASK,Mask bit for s4 protocol fault source" "0,1"
newline
bitfld.long 0x00 8. "ASF_PROTOCOL_FAULT_S3_MASK,Mask bit for s3 protocol fault source" "0,1"
bitfld.long 0x00 7. "ASF_PROTOCOL_FAULT_S2_MASK,Mask bit for s2 protocol fault source" "0,1"
newline
bitfld.long 0x00 6. "ASF_PROTOCOL_FAULT_S1_MASK,Mask bit for s1 protocol fault source" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_FAULT_S0_MASK,Mask bit for s0 protocol fault source" "0,1"
newline
bitfld.long 0x00 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_MASK,Mask bit for mst_sdr_rd_abort protocol fault source" "0,1"
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_MASK,Mask bit for mst_ddr_fail protocol fault source" "0,1"
newline
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_M2_MASK,Mask bit for m2 protocol fault source" "0,1"
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_M1_MASK,Mask bit for m1 protocol fault source" "0,1"
newline
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_M0_MASK,Mask bit for m0 protocol fault source" "0,1"
line.long 0x04 "I3C_ASF_PROTOCOL_FAULT_STATUS,Return to"
bitfld.long 0x04 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_STATUS,Status bit for slv_sdr_rd_abort protocol fault" "0,1"
bitfld.long 0x04 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_STATUS,Status bit for slv_ddr_fail protocol fault" "0,1"
newline
bitfld.long 0x04 10. "ASF_PROTOCOL_FAULT_S5_STATUS,Status bit for s5 protocol fault" "0,1"
bitfld.long 0x04 9. "ASF_PROTOCOL_FAULT_S4_STATUS,Status bit for s4 protocol fault" "0,1"
newline
bitfld.long 0x04 8. "ASF_PROTOCOL_FAULT_S3_STATUS,Status bit for s3 protocol fault" "0,1"
bitfld.long 0x04 7. "ASF_PROTOCOL_FAULT_S2_STATUS,Status bit for s2 protocol fault" "0,1"
newline
bitfld.long 0x04 6. "ASF_PROTOCOL_FAULT_S1_STATUS,Status bit for s1 protocol fault" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_FAULT_S0_STATUS,Status bit for s0 protocol fault" "0,1"
newline
bitfld.long 0x04 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_STATUS,Status bit for mst_sdr_rd_abort protocol fault" "0,1"
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_STATUS,Status bit for mst_ddr_fail protocol fault" "0,1"
newline
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_M2_STATUS,Status bit for m2 protocol fault" "0,1"
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_M1_STATUS,Status bit for m1 protocol fault" "0,1"
newline
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_M0_STATUS,Status bit for m0 protocol fault" "0,1"
tree.end
tree "MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST"
base ad:0x40B88000
rgroup.long 0x00++0x1B
line.long 0x00 "I3C_DEV_ID,Return to"
hexmask.long.word 0x00 16.--31. 1. "RSVD0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "DEV_ID,Unique IP identifier within Cadence IP portfolio"
line.long 0x04 "I3C_CONF_STATUS0,Return to"
bitfld.long 0x04 29.--31. "CMDR_MEM_DEPTH,CMD Resp MEM depth coded into 3 bits" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 24.--28. "ASF,Indicates supported ASF checks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 16.--23. 1. "GPO_NUM,Returns the value of User GPO"
hexmask.long.byte 0x04 8.--15. 1. "GPI_NUM,Returns the value of User GPI"
newline
bitfld.long 0x04 6.--7. "IBIR_MEM_DEPTH,IBI Resp MEM depth coded into 2 bits" "0,1,2,3"
bitfld.long 0x04 5. "DDR,Indicates if DDR is supported" "0,1"
newline
bitfld.long 0x04 4. "DEV_ROLE,Returns status of Device Role [Main/Secondary Master]" "0,1"
bitfld.long 0x04 0.--3. "DEVS_NUM,Returns the number of retaining registers for I3C Slave devices [Addresses and Characteristics] the max value is 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "I3C_CONF_STATUS1,Return to"
bitfld.long 0x08 28.--31. "IBI_HW_RES,IBI resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 26.--27. "CMD_MEM_DEPTH,CMD FIFO depth coded into 3 bits" "0,1,2,3"
newline
bitfld.long 0x08 21.--25. "SLV_DDR_RX_MEM_DEPTH,SLV DDR RX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "SLV_DDR_TX_MEM_DEPTH,SLV DDR TX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 13.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 10.--12. "IBI_MEM_DEPTH,IBI FIFO depth coded into 3 bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 5.--9. "RX_MEM_DEPTH,RX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "TX_MEM_DEPTH,TX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "I3C_REV_ID,Return to"
hexmask.long.word 0x0C 20.--31. 1. "VID,VENDOR_ID: IP vendor ID affected to CadenceIP [reset = 0xCAD]"
hexmask.long.word 0x0C 8.--19. 1. "PID,PRODUCT_ID: unique IP identifier within CDNS IP portfolio [reset = 0x13C]"
newline
bitfld.long 0x0C 5.--7. "REV_MAJOR,X: Major revision value" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--4. "REV_MINOR,Y: Minor revision value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "I3C_CTRL,Return to"
bitfld.long 0x10 31. "DEV_EN,When set HIGH the I3C-Master is enabled and it can initiates the I3C/I2C transactions" "0,1"
bitfld.long 0x10 30. "HALT_EN,Enable halt on abort behavior" "0,1"
newline
bitfld.long 0x10 29. "MCS,Manual Command Start writing 1 starts execution of the commands currently in CMD Memories" "0,1"
bitfld.long 0x10 28. "MCS_EN,Manual Command Start Enable if set 1 the IP will wait with starting of command execution until MCS but [" "0,1"
newline
rbitfld.long 0x10 27. "RSVD2,Reserved" "0,1"
bitfld.long 0x10 26. "I3C_11_SUPP,Enables support for timing parameter that has been changed in v1.1 i.e" "0,1"
newline
bitfld.long 0x10 24.--25. "THD_DEL,Field that provides option to add data hold delay with respect to the SCL clock on which data on SDA is launched [applied only during actual Data transfer]" "0,1,2,3"
hexmask.long.word 0x10 9.--23. 1. "RSVD1,Reserved"
newline
bitfld.long 0x10 8. "HJ_DISEC,This bit controls the HW response for ACK'ed HJ request" "0,1"
bitfld.long 0x10 7. "MST_ACK,Specifies ACK response type for GETACCMST CCC it can be either ACK response type [mst_ack = 1] or NACK response type [mst_ack = 0]" "0,1"
newline
bitfld.long 0x10 6. "HJ_ACK,Specifies ACK response type for HJ request it can be either ACK response type [hj_ack = 1] or NACK response type [hj_ack = 0]" "0,1"
bitfld.long 0x10 5. "HJ_INIT,Initiate HJ request - applicable only for Secondary master in slave mode" "0,1"
newline
bitfld.long 0x10 4. "MST_INIT,Initiate Mastership request - applicable only in slave mode" "0,1"
bitfld.long 0x10 3. "AHDR_OPT,Enable[1]/Disable[0] the Address Header optimization" "0,1"
newline
rbitfld.long 0x10 2. "RSVD0,Reserved" "0,1"
bitfld.long 0x10 0.--1. "BUS_MODE,Bus Mode" "0,1,2,3"
line.long 0x14 "I3C_PRESCL_CTRL0,Return to"
hexmask.long.word 0x14 16.--31. 1. "I2C,Prescaler value for I2C SCL clock generation"
rbitfld.long 0x14 10.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x14 0.--9. 1. "I3C,Prescaler value for I3C Push-Pull SDR Mode SCL clock generation"
line.long 0x18 "I3C_PRESCL_CTRL1,Return to"
hexmask.long.byte 0x18 8.--15. 1. "PP_LOW,Counter for low period of SCL clock for Push Pull in I3C"
hexmask.long.byte 0x18 0.--7. 1. "OD_LOW,Counter for low period of SCL clock for Open Drain in I3C"
group.long 0x20++0x3B
line.long 0x00 "I3C_MST_IER,Return to"
hexmask.long.word 0x00 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x00 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x00 17. "MR_DONE,Mastership handoff done Enable" "0,1"
bitfld.long 0x00 16. "IMM_COMP,Immediate Commmand Completed Enable" "0,1"
newline
bitfld.long 0x00 15. "TX_THR,Tx Data Threshold Enable" "0,1"
bitfld.long 0x00 14. "TX_OVF,Tx Data MEM Underflow Enable" "0,1"
newline
bitfld.long 0x00 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x00 12. "IBID_THR,IBI Data MEM threshold Enable" "0,1"
newline
bitfld.long 0x00 11. "IBID_UNF,IBI Data MEM underflow Enable" "0,1"
bitfld.long 0x00 10. "IBIR_THR,IBI Response Queue threshold Enable" "0,1"
newline
bitfld.long 0x00 9. "IBIR_UNF,IBI Response Queue underflow Enable" "0,1"
bitfld.long 0x00 8. "IBIR_OVF,IBI Response Queue onverflow Enable" "0,1"
newline
bitfld.long 0x00 7. "RX_THR,Rx Data MEM threshold Enable" "0,1"
bitfld.long 0x00 6. "RX_UNF,Rx Data MEM underflow Enable" "0,1"
newline
bitfld.long 0x00 5. "CMDD_EMP,Command Request Queue Empty Enable" "0,1"
bitfld.long 0x00 4. "CMDD_THR,Command Request Queue Threshold Enable" "0,1"
newline
bitfld.long 0x00 3. "CMDD_OVF,Command Request Queue Overflow Enable" "0,1"
bitfld.long 0x00 2. "CMDR_THR,Command Response Queue Threshold Enable" "0,1"
newline
bitfld.long 0x00 1. "CMDR_UNF,Command Response Queue Underflow Enable" "0,1"
bitfld.long 0x00 0. "CMDR_OVF,Command Response Queue Overflow Enable" "0,1"
line.long 0x04 "I3C_MST_IDR,Return to"
hexmask.long.word 0x04 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x04 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x04 17. "MR_DONE,Mastership handoff done Disable" "0,1"
bitfld.long 0x04 16. "IMM_COMP,Immediate Commmand Completed Disable" "0,1"
newline
bitfld.long 0x04 15. "TX_THR,Tx Data Threshold Disable" "0,1"
bitfld.long 0x04 14. "TX_OVF,Tx Data MEM Underflow Disable" "0,1"
newline
bitfld.long 0x04 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x04 12. "IBID_THR,IBI Data MEM threshold Disable" "0,1"
newline
bitfld.long 0x04 11. "IBID_UNF,IBI Data MEM underflow Disable" "0,1"
bitfld.long 0x04 10. "IBIR_THR,IBI Response Queue threshold Disable" "0,1"
newline
bitfld.long 0x04 9. "IBIR_UNF,IBI Response Queue underflow Disable" "0,1"
bitfld.long 0x04 8. "IBIR_OVF,IBI Response Queue onverflow Disable" "0,1"
newline
bitfld.long 0x04 7. "RX_THR,Rx Data MEM threshold Disable" "0,1"
bitfld.long 0x04 6. "RX_UNF,Rx Data MEM underflow Disable" "0,1"
newline
bitfld.long 0x04 5. "CMDD_EMP,Command Request Queue Empty Disable" "0,1"
bitfld.long 0x04 4. "CMDD_THR,Command Request Queue Threshold Disable" "0,1"
newline
bitfld.long 0x04 3. "CMDD_OVF,Command Request Queue Overflow Disable" "0,1"
bitfld.long 0x04 2. "CMDR_THR,Command Response Queue Threshold Disable" "0,1"
newline
bitfld.long 0x04 1. "CMDR_UNF,Command Response Queue Underflow Disable" "0,1"
bitfld.long 0x04 0. "CMDR_OVF,Command Response Queue Overflow Disable" "0,1"
line.long 0x08 "I3C_MST_IMR,Return to"
hexmask.long.word 0x08 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x08 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x08 17. "MR_DONE,Mastership handoff done Mask" "0,1"
bitfld.long 0x08 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1"
newline
bitfld.long 0x08 15. "TX_THR,Tx Data Threshold Mask" "0,1"
bitfld.long 0x08 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1"
newline
bitfld.long 0x08 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x08 12. "IBID_THR,IBI Data MEM threshold Mask" "0,1"
newline
bitfld.long 0x08 11. "IBID_UNF,IBI Data MEM underflow Mask" "0,1"
bitfld.long 0x08 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1"
newline
bitfld.long 0x08 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1"
bitfld.long 0x08 8. "IBIR_OVF,IBI Response Queue onverflow Mask" "0,1"
newline
bitfld.long 0x08 7. "RX_THR,Rx Data MEM threshold Mask" "0,1"
bitfld.long 0x08 6. "RX_UNF,Rx Data MEM underflow Mask" "0,1"
newline
bitfld.long 0x08 5. "CMDD_EMP,Command Request Queue Empty Mask" "0,1"
bitfld.long 0x08 4. "CMDD_THR,Command Request Queue Threshold Mask" "0,1"
newline
bitfld.long 0x08 3. "CMDD_OVF,Command Request Queue Overflow Mask" "0,1"
bitfld.long 0x08 2. "CMDR_THR,Command Response Queue Threshold Mask" "0,1"
newline
bitfld.long 0x08 1. "CMDR_UNF,Command Response Queue Underflow Mask" "0,1"
bitfld.long 0x08 0. "CMDR_OVF,Command Response Queue Overflow Mask" "0,1"
line.long 0x0C "I3C_MST_ICR,Return to"
hexmask.long.word 0x0C 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x0C 18. "HALTED,Controller is in halted state" "0,1"
newline
bitfld.long 0x0C 17. "MR_DONE,Mastership handoff done Mask" "0,1"
bitfld.long 0x0C 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1"
newline
bitfld.long 0x0C 15. "TX_THR,Tx Data Threshold Mask" "0,1"
bitfld.long 0x0C 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1"
newline
bitfld.long 0x0C 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x0C 12. "IBID_THR,IBI Data MEM threshold Mask" "0,1"
newline
bitfld.long 0x0C 11. "IBID_UNF,IBI Data MEM underflow Mask" "0,1"
bitfld.long 0x0C 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1"
newline
bitfld.long 0x0C 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1"
bitfld.long 0x0C 8. "IBIR_OVF,IBI Response Queue onverflow Mask" "0,1"
newline
bitfld.long 0x0C 7. "RX_THR,Rx Data MEM threshold Mask" "0,1"
bitfld.long 0x0C 6. "RX_UNF,Rx Data MEM underflow Mask" "0,1"
newline
bitfld.long 0x0C 5. "CMDD_EMP,Command Request Queue Empty Mask" "0,1"
bitfld.long 0x0C 4. "CMDD_THR,Command Request Queue Threshold Mask" "0,1"
newline
bitfld.long 0x0C 3. "CMDD_OVF,Command Request Queue Overflow Mask" "0,1"
bitfld.long 0x0C 2. "CMDR_THR,Command Response Queue Threshold Mask" "0,1"
newline
bitfld.long 0x0C 1. "CMDR_UNF,Command Response Queue Underflow Mask" "0,1"
bitfld.long 0x0C 0. "CMDR_OVF,Command Response Queue Overflow Mask" "0,1"
line.long 0x10 "I3C_MST_ISR,Return to"
hexmask.long.word 0x10 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x10 18. "HALTED,Controller in Halted state" "0,1"
newline
bitfld.long 0x10 17. "MR_DONE,Mastership handoff done" "0,1"
bitfld.long 0x10 16. "IMM_COMP,Immediate Commmand Completed" "0,1"
newline
bitfld.long 0x10 15. "TX_THR,Tx Data Threshold" "0,1"
bitfld.long 0x10 14. "TX_OVF,Tx Data MEM overflow" "0,1"
newline
bitfld.long 0x10 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x10 12. "IBID_THR,IBI Data MEM threshold" "0,1"
newline
bitfld.long 0x10 11. "IBID_UNF,IBI Data MEM underflow" "0,1"
bitfld.long 0x10 10. "IBIR_THR,IBI Response Queue threshold" "0,1"
newline
bitfld.long 0x10 9. "IBIR_UNF,IBI Response Queue underflow" "0,1"
bitfld.long 0x10 8. "IBIR_OVF,IBI Response Queue onverflow" "0,1"
newline
bitfld.long 0x10 7. "RX_THR,Rx Data MEM threshold" "0,1"
bitfld.long 0x10 6. "RX_UNF,Rx Data MEM underflow" "0,1"
newline
bitfld.long 0x10 5. "CMDD_EMP,Command Request Queue Empty" "0,1"
bitfld.long 0x10 4. "CMDD_THR,Command Request Queue Threshold" "0,1"
newline
bitfld.long 0x10 3. "CMDD_OVF,Command Request Queue Overflow" "0,1"
bitfld.long 0x10 2. "CMDR_THR,Command Response Queue Threshold" "0,1"
newline
bitfld.long 0x10 1. "CMDR_UNF,Command Response Queue Underflow" "0,1"
bitfld.long 0x10 0. "CMDR_OVF,Command Response Queue Overflow" "0,1"
line.long 0x14 "I3C_MST_STATUS0,Return to"
hexmask.long.word 0x14 19.--31. 1. "RSVD2,Reserved"
rbitfld.long 0x14 18. "IDLE,Indicates when the core is IDLE and ready to accept new commands" "0,1"
newline
bitfld.long 0x14 17. "HALTED,Core Halted" "0,1"
rbitfld.long 0x14 16. "OP_MODE,Indicates current mode of the controller" "0,1"
newline
rbitfld.long 0x14 14.--15. "RSVD1,Reserved" "0,1,2,3"
rbitfld.long 0x14 13. "TX_FULL,TX Full" "0,1"
newline
rbitfld.long 0x14 12. "IBID_FULL,IBID Full" "0,1"
rbitfld.long 0x14 11. "IBIR_FULL," "0,1"
newline
rbitfld.long 0x14 10. "RX_FULL,RX Full" "0,1"
rbitfld.long 0x14 9. "CMDD_FULL,CMDD Full" "0,1"
newline
rbitfld.long 0x14 8. "CMDR_FULL," "0,1"
rbitfld.long 0x14 6.--7. "RSVD0,Reserved" "0,1,2,3"
newline
rbitfld.long 0x14 5. "TX_EMP,TX Empty" "0,1"
rbitfld.long 0x14 4. "IBID_EMP,IBID Empty" "0,1"
newline
rbitfld.long 0x14 3. "IBIR_EMP," "0,1"
rbitfld.long 0x14 2. "RX_EMP,RX Empty" "0,1"
newline
rbitfld.long 0x14 1. "CMDD_EMP,CMDD Empty" "0,1"
rbitfld.long 0x14 0. "CMDR_EMP," "0,1"
line.long 0x18 "I3C_CMDR,Return to"
bitfld.long 0x18 28.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "ERROR,This field contains the code of an error that has occured during the last transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 8.--19. 1. "XFER_BYTES,The number of transferred bytes [SDR] or transferred words [DDR] during the last command"
newline
hexmask.long.byte 0x18 0.--7. 1. "CMD_ID,CMD_ID - command identifier"
line.long 0x1C "I3C_IBIR,Return to"
hexmask.long.tbyte 0x1C 13.--31. 1. "RSVD0,Reserved"
bitfld.long 0x1C 12. "RESP,If HIGH IBI has been ACKed NACK response otherwise" "0,1"
newline
bitfld.long 0x1C 8.--11. "SLV_ID,ID of a Slave that has issued an IBI request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 7. "ERROR,Set to 1 if IBI Data FIFO overflow has occured during the transaction" "0,1"
newline
bitfld.long 0x1C 2.--6. "XFER_BYTES,Number of received DATA bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--1. "IBI_TYPE,This field contains the type of an IBI" "0,1,2,3"
line.long 0x20 "I3C_SLV_IER,Return to"
bitfld.long 0x20 21. "DEFSLVS,DEFSLVS interrupt Enable" "0,1"
bitfld.long 0x20 20. "TM,TM interrupt Enable" "0,1"
newline
bitfld.long 0x20 19. "ERROR,ERROR interrupt Enable" "0,1"
bitfld.long 0x20 18. "EVENT_UP,EVENT_UP interrupt Enable" "0,1"
newline
bitfld.long 0x20 17. "HJ_DONE,HJ_DONE interrupt Enable" "0,1"
bitfld.long 0x20 16. "MR_DONE,MR_DONE interrupt Enable" "0,1"
newline
bitfld.long 0x20 15. "DA_UPDATE,DA_UPDATE interrupt Enable" "0,1"
bitfld.long 0x20 14. "SDR_FAIL,SDR_FAIL interrupt Enable" "0,1"
newline
bitfld.long 0x20 13. "DDR_FAIL,DDR_FAIL interrupt Enable" "0,1"
bitfld.long 0x20 12. "M_RD_ABORT,M_RD_ABORT interrupt Enable" "0,1"
newline
bitfld.long 0x20 11. "DDR_RX_THR,DDR_RX_THR interrupt Enable" "0,1"
bitfld.long 0x20 10. "DDR_TX_THR,DDR_TX_THR interrupt Enable" "0,1"
newline
bitfld.long 0x20 9. "SDR_RX_THR,SDR_RX_THR interrupt Enable" "0,1"
bitfld.long 0x20 8. "SDR_TX_THR,SLV_SDR_TX_THR interrupt Enable" "0,1"
newline
bitfld.long 0x20 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Enable" "0,1"
bitfld.long 0x20 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Enable" "0,1"
newline
bitfld.long 0x20 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Enable" "0,1"
bitfld.long 0x20 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Enable" "0,1"
newline
bitfld.long 0x20 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Enable" "0,1"
bitfld.long 0x20 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Enable" "0,1"
newline
bitfld.long 0x20 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Enable" "0,1"
bitfld.long 0x20 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Enable" "0,1"
line.long 0x24 "I3C_SLV_IDR,Return to"
bitfld.long 0x24 21. "DEFSLVS,DEFSLVS interrupt Disable" "0,1"
bitfld.long 0x24 20. "TM,TM interrupt Disable" "0,1"
newline
bitfld.long 0x24 19. "ERROR,ERROR interrupt Disable" "0,1"
bitfld.long 0x24 18. "EVENT_UP,EVENT_UP interrupt Disable" "0,1"
newline
bitfld.long 0x24 17. "HJ_DONE,HJ_DONE interrupt Disable" "0,1"
bitfld.long 0x24 16. "MR_DONE,MR_DONE interrupt Disable" "0,1"
newline
bitfld.long 0x24 15. "DA_UPDATE,DA_UPDATE interrupt Disable" "0,1"
bitfld.long 0x24 14. "SDR_FAIL,SDR_FAIL interrupt Disable" "0,1"
newline
bitfld.long 0x24 13. "DDR_FAIL,DDR_FAIL interrupt Disable" "0,1"
bitfld.long 0x24 12. "M_RD_ABORT,M_RD_ABORT interrupt Disable" "0,1"
newline
bitfld.long 0x24 11. "DDR_RX_THR,DDR_RX_THR interrupt Disable" "0,1"
bitfld.long 0x24 10. "DDR_TX_THR,DDR_TX_THR interrupt Disable" "0,1"
newline
bitfld.long 0x24 9. "SDR_RX_THR,SDR_RX_THR interrupt Disable" "0,1"
bitfld.long 0x24 8. "SDR_TX_THR,SDR_TX_THR interrupt Disable" "0,1"
newline
bitfld.long 0x24 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Disable" "0,1"
bitfld.long 0x24 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Disable" "0,1"
newline
bitfld.long 0x24 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Disable" "0,1"
bitfld.long 0x24 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Disable" "0,1"
newline
bitfld.long 0x24 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Disable" "0,1"
bitfld.long 0x24 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Disable" "0,1"
newline
bitfld.long 0x24 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Disable" "0,1"
bitfld.long 0x24 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Disable" "0,1"
line.long 0x28 "I3C_SLV_IMR,Return to"
bitfld.long 0x28 21. "DEFSLVS,DEFSLVS interrupt Mask" "0,1"
bitfld.long 0x28 20. "TM,TM interrupt Mask" "0,1"
newline
bitfld.long 0x28 19. "ERROR,ERROR interrupt Mask" "0,1"
bitfld.long 0x28 18. "EVENT_UP,EVENT_UP interrupt Mask" "0,1"
newline
bitfld.long 0x28 17. "HJ_DONE,HJ_DONE interrupt Mask" "0,1"
bitfld.long 0x28 16. "MR_DONE,MR_DONE interrupt Mask" "0,1"
newline
bitfld.long 0x28 15. "DA_UPDATE,DA_UPDATE interrupt Mask" "0,1"
bitfld.long 0x28 14. "SDR_FAIL,SDR_FAIL interrupt Mask" "0,1"
newline
bitfld.long 0x28 13. "DDR_FAIL,DDR_FAIL interrupt Mask" "0,1"
bitfld.long 0x28 12. "M_RD_ABORT,M_RD_ABORT interrupt Mask" "0,1"
newline
bitfld.long 0x28 11. "DDR_RX_THR,DDR_RX_THR interrupt Mask" "0,1"
bitfld.long 0x28 10. "DDR_TX_THR,DDR_TX_THR interrupt Mask" "0,1"
newline
bitfld.long 0x28 9. "SDR_RX_THR,SDR_RX_THR interrupt Mask" "0,1"
bitfld.long 0x28 8. "SDR_TX_THR,SDR_TX_THR interrupt Mask" "0,1"
newline
bitfld.long 0x28 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Mask" "0,1"
bitfld.long 0x28 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Mask" "0,1"
newline
bitfld.long 0x28 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Mask" "0,1"
bitfld.long 0x28 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Mask" "0,1"
newline
bitfld.long 0x28 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Mask" "0,1"
bitfld.long 0x28 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Mask" "0,1"
newline
bitfld.long 0x28 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Mask" "0,1"
bitfld.long 0x28 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Mask" "0,1"
line.long 0x2C "I3C_SLV_ICR,Return to"
bitfld.long 0x2C 21. "DEFSLVS,DEFSLVS interrupt Clear" "0,1"
bitfld.long 0x2C 20. "TM,TM interrupt Clear" "0,1"
newline
bitfld.long 0x2C 19. "ERROR,ERROR interrupt Clear" "0,1"
bitfld.long 0x2C 18. "EVENT_UP,EVENT_UP interrupt Clear" "0,1"
newline
bitfld.long 0x2C 17. "HJ_DONE,HJ_DONE interrupt Clear" "0,1"
bitfld.long 0x2C 16. "MR_DONE,MR_DONE interrupt Clear" "0,1"
newline
bitfld.long 0x2C 15. "DA_UPDATE,DA_UPDATE interrupt Clear" "0,1"
bitfld.long 0x2C 14. "SDR_FAIL,SDR_FAIL interrupt Clear" "0,1"
newline
bitfld.long 0x2C 13. "DDR_FAIL,DDR_FAIL interrupt Clear" "0,1"
bitfld.long 0x2C 12. "M_RD_ABORT,M_RD_ABORT interrupt Clear" "0,1"
newline
bitfld.long 0x2C 11. "DDR_RX_THR,DDR_RX_THR interrupt Clear" "0,1"
bitfld.long 0x2C 10. "DDR_TX_THR,DDR_TX_THR interrupt Clear" "0,1"
newline
bitfld.long 0x2C 9. "SDR_RX_THR,SDR_RX_THR interrupt Clear" "0,1"
bitfld.long 0x2C 8. "SDR_TX_THR,SDR_TX_THR interrupt Clear" "0,1"
newline
bitfld.long 0x2C 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Clear" "0,1"
bitfld.long 0x2C 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Clear" "0,1"
newline
bitfld.long 0x2C 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Clear" "0,1"
bitfld.long 0x2C 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Clear" "0,1"
newline
bitfld.long 0x2C 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Clear" "0,1"
bitfld.long 0x2C 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Clear" "0,1"
newline
bitfld.long 0x2C 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Clear" "0,1"
bitfld.long 0x2C 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Clear" "0,1"
line.long 0x30 "I3C_SLV_ISR,Return to"
bitfld.long 0x30 21. "DEFSLVS,This interrupt is triggered whenever I3C-Slave DEFSLVS CCC command is received" "0,1"
bitfld.long 0x30 20. "TM,This interrupt is triggered whenever I3C-Slave is not in Test Mode and ENTTM CCC command with byte value of 0x01 [general Test Mode] is received" "0,1"
newline
bitfld.long 0x30 19. "ERROR,This event is triggered whenever SDR Error is detected - applicable for S0 S1 S2 S4 and S5 Errors from MIPI spec" "0,1"
bitfld.long 0x30 18. "EVENT_UP,This event is triggered whenever DISEC CCC or ENEC CCC is received" "0,1"
newline
bitfld.long 0x30 17. "HJ_DONE,This event is triggered whenever Hot-Join request is completed" "0,1"
bitfld.long 0x30 16. "MR_DONE,This event is triggered whenever Mastership Request is completed" "0,1"
newline
bitfld.long 0x30 15. "DA_UPDATE,This event is triggered whenever Dynamic Address of the device has been updated" "0,1"
bitfld.long 0x30 14. "SDR_FAIL,This event is triggered whenever fail event during SDR transfer is detected [applicable for Private Write transfers only]" "0,1"
newline
bitfld.long 0x30 13. "DDR_FAIL,This event is triggered whenever fail event during DDR transfer is detected" "0,1"
bitfld.long 0x30 12. "M_RD_ABORT,Read Transfer Aborted by Master" "0,1"
newline
bitfld.long 0x30 11. "DDR_RX_THR,This event is triggered whenever threshold level for DDR Rx DATA Buffer is reached" "0,1"
bitfld.long 0x30 10. "DDR_TX_THR,This event is triggered whenever threshold level for DDR Tx DATA Buffer is reached" "0,1"
newline
bitfld.long 0x30 9. "SDR_RX_THR,Rx DATA Buffer Threshold" "0,1"
bitfld.long 0x30 8. "SDR_TX_THR,Tx DATA Buffer Threshold" "0,1"
newline
bitfld.long 0x30 7. "DDR_RX_UNF,Set if the host attempts to read from the DDR_RX_FIFO register when there is no more data" "0,1"
bitfld.long 0x30 6. "DDR_TX_OVF,Set if the host attempts to write to DDR_TX_FIFO register more times than the FIFO depth" "0,1"
newline
bitfld.long 0x30 5. "SDR_RX_UNF,Rx DATA Buffer Underflow" "0,1"
bitfld.long 0x30 4. "SDR_TX_OVF,Tx DATA Buffer Overflow" "0,1"
newline
bitfld.long 0x30 3. "DDR_RD_COMP,This bit is set whenever the Slave terminates the DDR Read transfer" "0,1"
bitfld.long 0x30 2. "DDR_WR_COMP,This bit is set whenever the Master terminates the DDR Write transfer" "0,1"
newline
bitfld.long 0x30 1. "SDR_RD_COMP,This bit is set whenever the Slave terminates the SDR Private Read transfer" "0,1"
bitfld.long 0x30 0. "SDR_WR_COMP,This bit is set whenever the Master terminates the SDR Private Write transfer" "0,1"
line.long 0x34 "I3C_SLV_STATUS0,Return to"
hexmask.long.byte 0x34 24.--31. 1. "RSVD0,Reserved"
hexmask.long.byte 0x34 16.--23. 1. "REG_ADDR,Private Read/Write Address"
newline
hexmask.long.word 0x34 0.--15. 1. "XFERRED_BYTES,Number of transferred bytes in SDR transactions"
line.long 0x38 "I3C_SLV_STATUS1,Return to"
hexmask.long.word 0x38 22.--31. 1. "RSVD1,Reserved"
bitfld.long 0x38 20.--21. "ENTAS,Bits that indicate current Activity State" "0,1,2,3"
newline
bitfld.long 0x38 19. "VEN_TM,Vendor Test Mode" "0,1"
bitfld.long 0x38 18. "HJ_DIS,Hot-Join Disabled" "0,1"
newline
bitfld.long 0x38 17. "MR_DIS,This bit is set whenever MR request is disabled by Current I3C-Master using DISEC CCC" "0,1"
bitfld.long 0x38 16. "PROT_ERROR,Protocol Error Condition Indicator" "0,1"
newline
hexmask.long.byte 0x38 9.--15. 1. "DA,Slave Dynamic Address"
bitfld.long 0x38 8. "HAS_DA,This bit is set whenever Slave has Dynamic Address assigned" "0,1"
newline
bitfld.long 0x38 7. "DDRRX_FULL,This bit is set whenever" "0,1"
bitfld.long 0x38 6. "DDRTX_FULL,This bit is set whenever" "0,1"
newline
bitfld.long 0x38 5. "DDRRX_EMPTY,This bit is set whenever" "0,1"
bitfld.long 0x38 4. "DDRTX_EMPTY,This bit is set whenever" "0,1"
newline
bitfld.long 0x38 3. "SDRRX_FULL,This bit is set whenever SDR_RX_FIFO is full" "0,1"
bitfld.long 0x38 2. "SDRTX_FULL,This bit is set whenever SDR_TX_FIFO is full" "0,1"
newline
bitfld.long 0x38 1. "SDRRX_EMPTY,This bit is set whenever SDR_RX_FIFO is empty" "0,1"
bitfld.long 0x38 0. "SDRTX_EMPTY,This bit is set whenever SDR_TX_FIFO is empty" "0,1"
group.long 0x60++0x0B
line.long 0x00 "I3C_CMD0_FIFO,Return to"
bitfld.long 0x00 31. "IS_DDR,IS_DDR - DDR command" "0,1"
bitfld.long 0x00 30. "IS_CCC,IsCCC" "0,1"
newline
bitfld.long 0x00 29. "BCH,BCH - Broadcast Header" "0,1"
bitfld.long 0x00 27.--28. "XMIT_MODE,Defines transfer modes for I3C private read/write commands [not CCC] the following options are available" "0,1,2,3"
newline
bitfld.long 0x00 26. "SBCA,SBCA - Sixteen Bits CSR Addressing" "0,1"
bitfld.long 0x00 25. "RSBC,RSBC - Repeated Start Between Commands" "0,1"
newline
bitfld.long 0x00 24. "IS10B,Is10B - Normal/Extended Address" "0,1"
hexmask.long.word 0x00 12.--23. 1. "PL_LEN,PL_LEN - Payload Length"
newline
bitfld.long 0x00 8.--10. "DEV_ADDR_MSB,DEV_ADDR_MSB - legacy I2C Extended Address" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address"
newline
bitfld.long 0x00 0. "RNW,RnW - Read no" "0,1"
line.long 0x04 "I3C_CMD1_FIFO,Return to"
hexmask.long.byte 0x04 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]"
hexmask.long.byte 0x04 16.--23. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x04 8.--15. 1. "CSRADDR1,CSR ADDR"
hexmask.long.byte 0x04 0.--7. 1. "CCC_CSRADDR0,CCC/CSR ADDR"
line.long 0x08 "I3C_TX_FIFO,Return to"
group.long 0x70++0x0B
line.long 0x00 "I3C_IMD_CMD0,Return to"
bitfld.long 0x00 12.--14. "PL_LEN,PL_LEN - Payload Length" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address"
newline
bitfld.long 0x00 0. "RNW,RnW - Read no" "0,1"
line.long 0x04 "I3C_IMD_CMD1,Return to"
hexmask.long.byte 0x04 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]"
hexmask.long.word 0x04 8.--23. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x04 0.--7. 1. "CCC,CCC code"
line.long 0x08 "I3C_IMD_DATA,Return to"
rgroup.long 0x80++0x1F
line.long 0x00 "I3C_RX_FIFO,Return to"
line.long 0x04 "I3C_IBI_DATA_FIFO,Return to"
line.long 0x08 "I3C_SLV_DDR_TX_FIFO,Return to"
hexmask.long.tbyte 0x08 0.--19. 1. "DDR_SLAVE_TX_DATA_FIFO,DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode"
line.long 0x0C "I3C_SLV_DDR_RX_FIFO,Return to"
hexmask.long.tbyte 0x0C 0.--19. 1. "DDR_SLAVE_RX_DATA_FIFO,DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode"
line.long 0x10 "I3C_CMD_IBI_THR_CTRL,Return to"
rbitfld.long 0x10 30.--31. "RSVD3,Reserved" "0,1,2,3"
bitfld.long 0x10 24.--29. "IBIR_THR,Threshold configuration value for IBI RESP memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--20. "CMDR_THR,Threshold configuration value for Command RESP memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x10 14.--15. "RSVD1,Reserved" "0,1,2,3"
bitfld.long 0x10 8.--13. "IBID_THR,Threshold configuration value for IBI DATA memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 5.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--4. "CMDD_THR,Threshold configuration value for Command REQ memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "I3C_TX_RX_THR_CTRL,Return to"
hexmask.long.word 0x14 16.--31. 1. "RX_THR,Threshold configuration value for Rx Data memory block"
hexmask.long.word 0x14 0.--15. 1. "TX_THR,Threshold configuration value for Tx Data memory block"
line.long 0x18 "I3C_SLV_DDR_TX_RX_THR_CTRL,Return to"
hexmask.long.word 0x18 16.--31. 1. "SLV_DDR_RX_THR,Threshold configuration value for Slave Mode DDR Rx Data memory block"
hexmask.long.word 0x18 0.--15. 1. "SLV_DDR_TX_THR,Threshold configuration value for Slave Mode DDR Tx Data memory block"
line.long 0x1C "I3C_FLUSH_CTRL,Return to"
bitfld.long 0x1C 24. "IBI_RESP_FLUSH,When asserted while controller is disabled the IBI Response Queue read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
bitfld.long 0x1C 23. "CMD_RESP_FLUSH,When asserted while controller is disabled the Command Response Queue read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
newline
bitfld.long 0x1C 22. "SLV_DDR_RX_FLUSH,When asserted while controller is disabled the SLV DDR Rx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
bitfld.long 0x1C 21. "SLV_DDR_TX_FLUSH,When asserted while controller is disabled the SLV DDR Tx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
newline
bitfld.long 0x1C 20. "IMM_CMD_FLUSH,When asserted while controller is disabled the immediate command/data register will be cleared" "0,1"
bitfld.long 0x1C 19. "IBI_FLUSH,When asserted while controller is disabled the IBI data memory block read/write pointers will be set to 0" "0,1"
newline
bitfld.long 0x1C 18. "RX_FLUSH,When asserted while controller is disabled the Rx Data memory block read/write pointers will be set to 0" "0,1"
bitfld.long 0x1C 17. "TX_FLUSH,When asserted while controller is disabled the Tx Data memory block read/write pointers will be set to 0" "0,1"
newline
bitfld.long 0x1C 16. "CMD_FLUSH,When asserted while controller is disabled the command Command memory block read/write pointers will be set to 0" "0,1"
group.long 0xB0++0x0B
line.long 0x00 "I3C_TTO_PRESCL_CTRL0,Return to"
rbitfld.long 0x00 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "DIV_B,Divider B"
newline
rbitfld.long 0x00 11.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "DIV_A,Divider A"
line.long 0x04 "I3C_TTO_PRESCL_CTRL1,Return to"
rbitfld.long 0x04 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x04 16.--25. 1. "DIV_B,Divider B"
newline
hexmask.long.byte 0x04 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "DIV_A,Divider A"
line.long 0x08 "I3C_DEVS_CTRL,Return to"
rbitfld.long 0x08 28.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 27. "DEV11_CLR,Clear DevID11 retaining registers set" "0,1"
newline
bitfld.long 0x08 26. "DEV10_CLR,Clear DevID10 retaining registers set" "0,1"
bitfld.long 0x08 25. "DEV9_CLR,Clear DevID9 retaining registers set" "0,1"
newline
bitfld.long 0x08 24. "DEV8_CLR,Clear DevID8 retaining registers set" "0,1"
bitfld.long 0x08 23. "DEV7_CLR,Clear DevID7 retaining registers set" "0,1"
newline
bitfld.long 0x08 22. "DEV6_CLR,Clear DevID6 retaining registers set" "0,1"
bitfld.long 0x08 21. "DEV5_CLR,Clear DevID5 retaining registers set" "0,1"
newline
bitfld.long 0x08 20. "DEV4_CLR,Clear DevID4 retaining registers set" "0,1"
bitfld.long 0x08 19. "DEV3_CLR,Clear DevID3 retaining registers set" "0,1"
newline
bitfld.long 0x08 18. "DEV2_CLR,Clear DevID2 retaining registers set" "0,1"
bitfld.long 0x08 17. "DEV1_CLR,Clear DevID1 retaining registers set" "0,1"
newline
rbitfld.long 0x08 12.--16. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 11. "DEV11_ACTIVE,DevID11 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 10. "DEV10_ACTIVE,DevID10 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 9. "DEV9_ACTIVE,DevID9 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 8. "DEV8_ACTIVE,DevID8 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 7. "DEV7_ACTIVE,DevID7 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 6. "DEV6_ACTIVE,DevID6 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 5. "DEV5_ACTIVE,DevID5 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 4. "DEV4_ACTIVE,DevID4 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 3. "DEV3_ACTIVE,DevID3 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 2. "DEV2_ACTIVE,DevID2 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 1. "DEV1_ACTIVE,DevID1 is active - has either valid DA or SA" "0,1"
newline
rbitfld.long 0x08 0. "DEV0_ACTIVE,DevID0 is active - has either valid DA or SA" "0,1"
group.long 0xC0++0x0B
line.long 0x00 "I3C_DEV_ID0_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 0 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "IS_I3C,Device 0 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 0 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID0_RR1,Return to"
line.long 0x08 "I3C_DEV_ID0_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 0 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 0 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 0 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xD0++0x0B
line.long 0x00 "I3C_DEV_ID1_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 1 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 1 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 1 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID1_RR1,Return to"
line.long 0x08 "I3C_DEV_ID1_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 1 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 1 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 1 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xE0++0x0B
line.long 0x00 "I3C_DEV_ID2_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 2 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 2 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 2 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID2_RR1,Return to"
line.long 0x08 "I3C_DEV_ID2_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 2 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 2 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 2 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xF0++0x0B
line.long 0x00 "I3C_DEV_ID3_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 3 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 3 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 3 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID3_RR1,Return to"
line.long 0x08 "I3C_DEV_ID3_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 3 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 3 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 3 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x100++0x0B
line.long 0x00 "I3C_DEV_ID4_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 4 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 4 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 4 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID4_RR1,Return to"
line.long 0x08 "I3C_DEV_ID4_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 4 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 4 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 4 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x110++0x0B
line.long 0x00 "I3C_DEV_ID5_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 5 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 5 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 5 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID5_RR1,Return to"
line.long 0x08 "I3C_DEV_ID5_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 5 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 5 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 5 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x120++0x0B
line.long 0x00 "I3C_DEV_ID6_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 6 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 6 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 6 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID6_RR1,Return to"
line.long 0x08 "I3C_DEV_ID6_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 6 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 6 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 6 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x130++0x0B
line.long 0x00 "I3C_DEV_ID7_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 7 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 7 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 7 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID7_RR1,Return to"
line.long 0x08 "I3C_DEV_ID7_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 7 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 7 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 7 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x140++0x0B
line.long 0x00 "I3C_DEV_ID8_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 8 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 8 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 8 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID8_RR1,Return to"
line.long 0x08 "I3C_DEV_ID8_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 8 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 8 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 8 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x150++0x0B
line.long 0x00 "I3C_DEV_ID9_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 9 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 9 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 9 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID9_RR1,Return to"
line.long 0x08 "I3C_DEV_ID9_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 9 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 9 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 9 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x160++0x0B
line.long 0x00 "I3C_DEV_ID10_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 10 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 10 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 10 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID10_RR1,Return to"
line.long 0x08 "I3C_DEV_ID10_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 10 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 10 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 10 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x170++0x0B
line.long 0x00 "I3C_DEV_ID11_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 11 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 11 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 11 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID11_RR1,Return to"
line.long 0x08 "I3C_DEV_ID11_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 11 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 11 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 11 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x180++0x17
line.long 0x00 "I3C_SIR_MAP0,Return to"
bitfld.long 0x00 30.--31. "DEVID1_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3"
bitfld.long 0x00 29. "DEVID1_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x00 24.--28. "DEVID1_PL,Slave-initiated request Device ID0 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 17.--23. 1. "DEVID1_DA,Slave-initiated request Device ID0 DA"
newline
bitfld.long 0x00 16. "DEVID1_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1"
bitfld.long 0x00 14.--15. "DEVID0_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3"
newline
bitfld.long 0x00 13. "DEVID0_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1"
bitfld.long 0x00 8.--12. "DEVID0_PL,Slave-initiated request Device ID0 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 1.--7. 1. "DEVID0_DA,Slave-initiated request Device ID0 DA"
bitfld.long 0x00 0. "DEVID0_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1"
line.long 0x04 "I3C_SIR_MAP1,Return to"
bitfld.long 0x04 30.--31. "DEVID3_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3"
bitfld.long 0x04 29. "DEVID3_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x04 24.--28. "DEVID3_PL,Slave-initiated request Device ID2 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x04 17.--23. 1. "DEVID3_DA,Slave-initiated request Device ID2 DA"
newline
bitfld.long 0x04 16. "DEVID3_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1"
bitfld.long 0x04 14.--15. "DEVID2_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3"
newline
bitfld.long 0x04 13. "DEVID2_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1"
bitfld.long 0x04 8.--12. "DEVID2_PL,Slave-initiated request Device ID2 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 1.--7. 1. "DEVID2_DA,Slave-initiated request Device ID2 DA"
bitfld.long 0x04 0. "DEVID2_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1"
line.long 0x08 "I3C_SIR_MAP2,Return to"
bitfld.long 0x08 30.--31. "DEVID5_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3"
bitfld.long 0x08 29. "DEVID5_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x08 24.--28. "DEVID5_PL,Slave-initiated request Device ID4 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x08 17.--23. 1. "DEVID5_DA,Slave-initiated request Device ID4 DA"
newline
bitfld.long 0x08 16. "DEVID5_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1"
bitfld.long 0x08 14.--15. "DEVID4_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3"
newline
bitfld.long 0x08 13. "DEVID4_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1"
bitfld.long 0x08 8.--12. "DEVID4_PL,Slave-initiated request Device ID4 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x08 1.--7. 1. "DEVID4_DA,Slave-initiated request Device ID4 DA"
bitfld.long 0x08 0. "DEVID4_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1"
line.long 0x0C "I3C_SIR_MAP3,Return to"
bitfld.long 0x0C 30.--31. "DEVID7_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3"
bitfld.long 0x0C 29. "DEVID7_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x0C 24.--28. "DEVID7_PL,Slave-initiated request Device ID6 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 17.--23. 1. "DEVID7_DA,Slave-initiated request Device ID6 DA"
newline
bitfld.long 0x0C 16. "DEVID7_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1"
bitfld.long 0x0C 14.--15. "DEVID6_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3"
newline
bitfld.long 0x0C 13. "DEVID6_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1"
bitfld.long 0x0C 8.--12. "DEVID6_PL,Slave-initiated request Device ID6 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x0C 1.--7. 1. "DEVID6_DA,Slave-initiated request Device ID6 DA"
bitfld.long 0x0C 0. "DEVID6_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1"
line.long 0x10 "I3C_SIR_MAP4,Return to"
bitfld.long 0x10 30.--31. "DEVID9_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3"
bitfld.long 0x10 29. "DEVID9_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x10 24.--28. "DEVID9_PL,Slave-initiated request Device ID8 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x10 17.--23. 1. "DEVID9_DA,Slave-initiated request Device ID8 DA"
newline
bitfld.long 0x10 16. "DEVID9_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1"
bitfld.long 0x10 14.--15. "DEVID8_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3"
newline
bitfld.long 0x10 13. "DEVID8_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1"
bitfld.long 0x10 8.--12. "DEVID8_PL,Slave-initiated request Device ID8 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x10 1.--7. 1. "DEVID8_DA,Slave-initiated request Device ID8 DA"
bitfld.long 0x10 0. "DEVID8_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1"
line.long 0x14 "I3C_SIR_MAP5,Return to"
bitfld.long 0x14 14.--15. "DEVID10_ROLE,Slave-initiated request Device ID10 BCR role" "0,1,2,3"
bitfld.long 0x14 13. "DEVID10_SLOW,Slave-initiated request Device ID10 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x14 8.--12. "DEVID10_PL,Slave-initiated request Device ID10 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 1.--7. 1. "DEVID10_DA,Slave-initiated request Device ID10 DA"
newline
bitfld.long 0x14 0. "DEVID10_RESP,Slave-initiated request Device ID10 Ack/Nack response" "0,1"
rgroup.long 0x1A0++0x03
line.long 0x00 "I3C_GPIR_WORD0,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RSVD2,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "GPI0,User Defined GPI Register 0"
rgroup.long 0x220++0x03
line.long 0x00 "I3C_GPOR_WORD0,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RSVD2,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "GPO0,User Defined GPO Register 0"
group.long 0x300++0x13
line.long 0x00 "I3C_ASF_INT_STATUS,Return to"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "I3C_ASF_INT_RAW_STATUS,Return to"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "I3C_ASF_INT_MASK,Return to"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "I3C_ASF_INT_TEST,Return to"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "I3C_ASF_FATAL_NONFATAL_SELECT,Return to"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x320++0x0B
line.long 0x00 "I3C_ASF_SRAM_CORR_FAULT_STATUS,Return to"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "I3C_ASF_SRAM_UNCORR_FAULT_STATUS,Return to"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "I3C_ASF_SRAM_FAULT_STATS,Return to"
hexmask.long.word 0x08 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x330++0x0B
line.long 0x00 "I3C_ASF_TRANS_TO_CTRL,Return to"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "I3C_ASF_TRANS_TO_FAULT_MASK,Return to"
bitfld.long 0x04 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask bit for apb transaction timeout fault" "0,1"
bitfld.long 0x04 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for I3C transaction SCL low timeout fault" "0,1"
newline
bitfld.long 0x04 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for I3C transaction SCL high timeout fault" "0,1"
bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for I3C transaction first SCL high timeout fault" "0,1"
line.long 0x08 "I3C_ASF_TRANS_TO_FAULT_STATUS,Return to"
bitfld.long 0x08 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for apb transaction timeout fault" "0,1"
bitfld.long 0x08 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for I3C transaction SCL low timeout fault" "0,1"
newline
bitfld.long 0x08 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for I3C transaction SCL high timeout fault" "0,1"
bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for I3C transaction first SCL high timeout fault" "0,1"
group.long 0x340++0x07
line.long 0x00 "I3C_ASF_PROTOCOL_FAULT_MASK,Return to"
bitfld.long 0x00 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_MASK,Mask bit for slv_sdr_rd_abort protocol fault source" "0,1"
bitfld.long 0x00 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_MASK,Mask bit for slv_ddr_fail protocol fault source" "0,1"
newline
bitfld.long 0x00 10. "ASF_PROTOCOL_FAULT_S5_MASK,Mask bit for s5 protocol fault source" "0,1"
bitfld.long 0x00 9. "ASF_PROTOCOL_FAULT_S4_MASK,Mask bit for s4 protocol fault source" "0,1"
newline
bitfld.long 0x00 8. "ASF_PROTOCOL_FAULT_S3_MASK,Mask bit for s3 protocol fault source" "0,1"
bitfld.long 0x00 7. "ASF_PROTOCOL_FAULT_S2_MASK,Mask bit for s2 protocol fault source" "0,1"
newline
bitfld.long 0x00 6. "ASF_PROTOCOL_FAULT_S1_MASK,Mask bit for s1 protocol fault source" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_FAULT_S0_MASK,Mask bit for s0 protocol fault source" "0,1"
newline
bitfld.long 0x00 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_MASK,Mask bit for mst_sdr_rd_abort protocol fault source" "0,1"
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_MASK,Mask bit for mst_ddr_fail protocol fault source" "0,1"
newline
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_M2_MASK,Mask bit for m2 protocol fault source" "0,1"
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_M1_MASK,Mask bit for m1 protocol fault source" "0,1"
newline
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_M0_MASK,Mask bit for m0 protocol fault source" "0,1"
line.long 0x04 "I3C_ASF_PROTOCOL_FAULT_STATUS,Return to"
bitfld.long 0x04 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_STATUS,Status bit for slv_sdr_rd_abort protocol fault" "0,1"
bitfld.long 0x04 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_STATUS,Status bit for slv_ddr_fail protocol fault" "0,1"
newline
bitfld.long 0x04 10. "ASF_PROTOCOL_FAULT_S5_STATUS,Status bit for s5 protocol fault" "0,1"
bitfld.long 0x04 9. "ASF_PROTOCOL_FAULT_S4_STATUS,Status bit for s4 protocol fault" "0,1"
newline
bitfld.long 0x04 8. "ASF_PROTOCOL_FAULT_S3_STATUS,Status bit for s3 protocol fault" "0,1"
bitfld.long 0x04 7. "ASF_PROTOCOL_FAULT_S2_STATUS,Status bit for s2 protocol fault" "0,1"
newline
bitfld.long 0x04 6. "ASF_PROTOCOL_FAULT_S1_STATUS,Status bit for s1 protocol fault" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_FAULT_S0_STATUS,Status bit for s0 protocol fault" "0,1"
newline
bitfld.long 0x04 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_STATUS,Status bit for mst_sdr_rd_abort protocol fault" "0,1"
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_STATUS,Status bit for mst_ddr_fail protocol fault" "0,1"
newline
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_M2_STATUS,Status bit for m2 protocol fault" "0,1"
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_M1_STATUS,Status bit for m1 protocol fault" "0,1"
newline
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_M0_STATUS,Status bit for m0 protocol fault" "0,1"
tree.end
tree "MCU_I3C1_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST"
base ad:0x40B98000
rgroup.long 0x00++0x1B
line.long 0x00 "I3C_DEV_ID,Return to"
hexmask.long.word 0x00 16.--31. 1. "RSVD0,Reserved"
hexmask.long.word 0x00 0.--15. 1. "DEV_ID,Unique IP identifier within Cadence IP portfolio"
line.long 0x04 "I3C_CONF_STATUS0,Return to"
bitfld.long 0x04 29.--31. "CMDR_MEM_DEPTH,CMD Resp MEM depth coded into 3 bits" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 24.--28. "ASF,Indicates supported ASF checks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 16.--23. 1. "GPO_NUM,Returns the value of User GPO"
hexmask.long.byte 0x04 8.--15. 1. "GPI_NUM,Returns the value of User GPI"
newline
bitfld.long 0x04 6.--7. "IBIR_MEM_DEPTH,IBI Resp MEM depth coded into 2 bits" "0,1,2,3"
bitfld.long 0x04 5. "DDR,Indicates if DDR is supported" "0,1"
newline
bitfld.long 0x04 4. "DEV_ROLE,Returns status of Device Role [Main/Secondary Master]" "0,1"
bitfld.long 0x04 0.--3. "DEVS_NUM,Returns the number of retaining registers for I3C Slave devices [Addresses and Characteristics] the max value is 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "I3C_CONF_STATUS1,Return to"
bitfld.long 0x08 28.--31. "IBI_HW_RES,IBI resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 26.--27. "CMD_MEM_DEPTH,CMD FIFO depth coded into 3 bits" "0,1,2,3"
newline
bitfld.long 0x08 21.--25. "SLV_DDR_RX_MEM_DEPTH,SLV DDR RX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "SLV_DDR_TX_MEM_DEPTH,SLV DDR TX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 13.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 10.--12. "IBI_MEM_DEPTH,IBI FIFO depth coded into 3 bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 5.--9. "RX_MEM_DEPTH,RX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "TX_MEM_DEPTH,TX FIFO depth coded into 5 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "I3C_REV_ID,Return to"
hexmask.long.word 0x0C 20.--31. 1. "VID,VENDOR_ID: IP vendor ID affected to CadenceIP [reset = 0xCAD]"
hexmask.long.word 0x0C 8.--19. 1. "PID,PRODUCT_ID: unique IP identifier within CDNS IP portfolio [reset = 0x13C]"
newline
bitfld.long 0x0C 5.--7. "REV_MAJOR,X: Major revision value" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--4. "REV_MINOR,Y: Minor revision value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "I3C_CTRL,Return to"
bitfld.long 0x10 31. "DEV_EN,When set HIGH the I3C-Master is enabled and it can initiates the I3C/I2C transactions" "0,1"
bitfld.long 0x10 30. "HALT_EN,Enable halt on abort behavior" "0,1"
newline
bitfld.long 0x10 29. "MCS,Manual Command Start writing 1 starts execution of the commands currently in CMD Memories" "0,1"
bitfld.long 0x10 28. "MCS_EN,Manual Command Start Enable if set 1 the IP will wait with starting of command execution until MCS but [" "0,1"
newline
rbitfld.long 0x10 27. "RSVD2,Reserved" "0,1"
bitfld.long 0x10 26. "I3C_11_SUPP,Enables support for timing parameter that has been changed in v1.1 i.e" "0,1"
newline
bitfld.long 0x10 24.--25. "THD_DEL,Field that provides option to add data hold delay with respect to the SCL clock on which data on SDA is launched [applied only during actual Data transfer]" "0,1,2,3"
hexmask.long.word 0x10 9.--23. 1. "RSVD1,Reserved"
newline
bitfld.long 0x10 8. "HJ_DISEC,This bit controls the HW response for ACK'ed HJ request" "0,1"
bitfld.long 0x10 7. "MST_ACK,Specifies ACK response type for GETACCMST CCC it can be either ACK response type [mst_ack = 1] or NACK response type [mst_ack = 0]" "0,1"
newline
bitfld.long 0x10 6. "HJ_ACK,Specifies ACK response type for HJ request it can be either ACK response type [hj_ack = 1] or NACK response type [hj_ack = 0]" "0,1"
bitfld.long 0x10 5. "HJ_INIT,Initiate HJ request - applicable only for Secondary master in slave mode" "0,1"
newline
bitfld.long 0x10 4. "MST_INIT,Initiate Mastership request - applicable only in slave mode" "0,1"
bitfld.long 0x10 3. "AHDR_OPT,Enable[1]/Disable[0] the Address Header optimization" "0,1"
newline
rbitfld.long 0x10 2. "RSVD0,Reserved" "0,1"
bitfld.long 0x10 0.--1. "BUS_MODE,Bus Mode" "0,1,2,3"
line.long 0x14 "I3C_PRESCL_CTRL0,Return to"
hexmask.long.word 0x14 16.--31. 1. "I2C,Prescaler value for I2C SCL clock generation"
rbitfld.long 0x14 10.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x14 0.--9. 1. "I3C,Prescaler value for I3C Push-Pull SDR Mode SCL clock generation"
line.long 0x18 "I3C_PRESCL_CTRL1,Return to"
hexmask.long.byte 0x18 8.--15. 1. "PP_LOW,Counter for low period of SCL clock for Push Pull in I3C"
hexmask.long.byte 0x18 0.--7. 1. "OD_LOW,Counter for low period of SCL clock for Open Drain in I3C"
group.long 0x20++0x3B
line.long 0x00 "I3C_MST_IER,Return to"
hexmask.long.word 0x00 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x00 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x00 17. "MR_DONE,Mastership handoff done Enable" "0,1"
bitfld.long 0x00 16. "IMM_COMP,Immediate Commmand Completed Enable" "0,1"
newline
bitfld.long 0x00 15. "TX_THR,Tx Data Threshold Enable" "0,1"
bitfld.long 0x00 14. "TX_OVF,Tx Data MEM Underflow Enable" "0,1"
newline
bitfld.long 0x00 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x00 12. "IBID_THR,IBI Data MEM threshold Enable" "0,1"
newline
bitfld.long 0x00 11. "IBID_UNF,IBI Data MEM underflow Enable" "0,1"
bitfld.long 0x00 10. "IBIR_THR,IBI Response Queue threshold Enable" "0,1"
newline
bitfld.long 0x00 9. "IBIR_UNF,IBI Response Queue underflow Enable" "0,1"
bitfld.long 0x00 8. "IBIR_OVF,IBI Response Queue onverflow Enable" "0,1"
newline
bitfld.long 0x00 7. "RX_THR,Rx Data MEM threshold Enable" "0,1"
bitfld.long 0x00 6. "RX_UNF,Rx Data MEM underflow Enable" "0,1"
newline
bitfld.long 0x00 5. "CMDD_EMP,Command Request Queue Empty Enable" "0,1"
bitfld.long 0x00 4. "CMDD_THR,Command Request Queue Threshold Enable" "0,1"
newline
bitfld.long 0x00 3. "CMDD_OVF,Command Request Queue Overflow Enable" "0,1"
bitfld.long 0x00 2. "CMDR_THR,Command Response Queue Threshold Enable" "0,1"
newline
bitfld.long 0x00 1. "CMDR_UNF,Command Response Queue Underflow Enable" "0,1"
bitfld.long 0x00 0. "CMDR_OVF,Command Response Queue Overflow Enable" "0,1"
line.long 0x04 "I3C_MST_IDR,Return to"
hexmask.long.word 0x04 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x04 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x04 17. "MR_DONE,Mastership handoff done Disable" "0,1"
bitfld.long 0x04 16. "IMM_COMP,Immediate Commmand Completed Disable" "0,1"
newline
bitfld.long 0x04 15. "TX_THR,Tx Data Threshold Disable" "0,1"
bitfld.long 0x04 14. "TX_OVF,Tx Data MEM Underflow Disable" "0,1"
newline
bitfld.long 0x04 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x04 12. "IBID_THR,IBI Data MEM threshold Disable" "0,1"
newline
bitfld.long 0x04 11. "IBID_UNF,IBI Data MEM underflow Disable" "0,1"
bitfld.long 0x04 10. "IBIR_THR,IBI Response Queue threshold Disable" "0,1"
newline
bitfld.long 0x04 9. "IBIR_UNF,IBI Response Queue underflow Disable" "0,1"
bitfld.long 0x04 8. "IBIR_OVF,IBI Response Queue onverflow Disable" "0,1"
newline
bitfld.long 0x04 7. "RX_THR,Rx Data MEM threshold Disable" "0,1"
bitfld.long 0x04 6. "RX_UNF,Rx Data MEM underflow Disable" "0,1"
newline
bitfld.long 0x04 5. "CMDD_EMP,Command Request Queue Empty Disable" "0,1"
bitfld.long 0x04 4. "CMDD_THR,Command Request Queue Threshold Disable" "0,1"
newline
bitfld.long 0x04 3. "CMDD_OVF,Command Request Queue Overflow Disable" "0,1"
bitfld.long 0x04 2. "CMDR_THR,Command Response Queue Threshold Disable" "0,1"
newline
bitfld.long 0x04 1. "CMDR_UNF,Command Response Queue Underflow Disable" "0,1"
bitfld.long 0x04 0. "CMDR_OVF,Command Response Queue Overflow Disable" "0,1"
line.long 0x08 "I3C_MST_IMR,Return to"
hexmask.long.word 0x08 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x08 18. "HALTED,Controller in halted state" "0,1"
newline
bitfld.long 0x08 17. "MR_DONE,Mastership handoff done Mask" "0,1"
bitfld.long 0x08 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1"
newline
bitfld.long 0x08 15. "TX_THR,Tx Data Threshold Mask" "0,1"
bitfld.long 0x08 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1"
newline
bitfld.long 0x08 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x08 12. "IBID_THR,IBI Data MEM threshold Mask" "0,1"
newline
bitfld.long 0x08 11. "IBID_UNF,IBI Data MEM underflow Mask" "0,1"
bitfld.long 0x08 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1"
newline
bitfld.long 0x08 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1"
bitfld.long 0x08 8. "IBIR_OVF,IBI Response Queue onverflow Mask" "0,1"
newline
bitfld.long 0x08 7. "RX_THR,Rx Data MEM threshold Mask" "0,1"
bitfld.long 0x08 6. "RX_UNF,Rx Data MEM underflow Mask" "0,1"
newline
bitfld.long 0x08 5. "CMDD_EMP,Command Request Queue Empty Mask" "0,1"
bitfld.long 0x08 4. "CMDD_THR,Command Request Queue Threshold Mask" "0,1"
newline
bitfld.long 0x08 3. "CMDD_OVF,Command Request Queue Overflow Mask" "0,1"
bitfld.long 0x08 2. "CMDR_THR,Command Response Queue Threshold Mask" "0,1"
newline
bitfld.long 0x08 1. "CMDR_UNF,Command Response Queue Underflow Mask" "0,1"
bitfld.long 0x08 0. "CMDR_OVF,Command Response Queue Overflow Mask" "0,1"
line.long 0x0C "I3C_MST_ICR,Return to"
hexmask.long.word 0x0C 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x0C 18. "HALTED,Controller is in halted state" "0,1"
newline
bitfld.long 0x0C 17. "MR_DONE,Mastership handoff done Mask" "0,1"
bitfld.long 0x0C 16. "IMM_COMP,Immediate Commmand Completed Mask" "0,1"
newline
bitfld.long 0x0C 15. "TX_THR,Tx Data Threshold Mask" "0,1"
bitfld.long 0x0C 14. "TX_OVF,Tx Data MEM Underflow Mask" "0,1"
newline
bitfld.long 0x0C 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x0C 12. "IBID_THR,IBI Data MEM threshold Mask" "0,1"
newline
bitfld.long 0x0C 11. "IBID_UNF,IBI Data MEM underflow Mask" "0,1"
bitfld.long 0x0C 10. "IBIR_THR,IBI Response Queue threshold Mask" "0,1"
newline
bitfld.long 0x0C 9. "IBIR_UNF,IBI Response Queue underflow Mask" "0,1"
bitfld.long 0x0C 8. "IBIR_OVF,IBI Response Queue onverflow Mask" "0,1"
newline
bitfld.long 0x0C 7. "RX_THR,Rx Data MEM threshold Mask" "0,1"
bitfld.long 0x0C 6. "RX_UNF,Rx Data MEM underflow Mask" "0,1"
newline
bitfld.long 0x0C 5. "CMDD_EMP,Command Request Queue Empty Mask" "0,1"
bitfld.long 0x0C 4. "CMDD_THR,Command Request Queue Threshold Mask" "0,1"
newline
bitfld.long 0x0C 3. "CMDD_OVF,Command Request Queue Overflow Mask" "0,1"
bitfld.long 0x0C 2. "CMDR_THR,Command Response Queue Threshold Mask" "0,1"
newline
bitfld.long 0x0C 1. "CMDR_UNF,Command Response Queue Underflow Mask" "0,1"
bitfld.long 0x0C 0. "CMDR_OVF,Command Response Queue Overflow Mask" "0,1"
line.long 0x10 "I3C_MST_ISR,Return to"
hexmask.long.word 0x10 19.--31. 1. "RSVD1,Reserved"
bitfld.long 0x10 18. "HALTED,Controller in Halted state" "0,1"
newline
bitfld.long 0x10 17. "MR_DONE,Mastership handoff done" "0,1"
bitfld.long 0x10 16. "IMM_COMP,Immediate Commmand Completed" "0,1"
newline
bitfld.long 0x10 15. "TX_THR,Tx Data Threshold" "0,1"
bitfld.long 0x10 14. "TX_OVF,Tx Data MEM overflow" "0,1"
newline
bitfld.long 0x10 13. "RSVD0,Reserved" "0,1"
bitfld.long 0x10 12. "IBID_THR,IBI Data MEM threshold" "0,1"
newline
bitfld.long 0x10 11. "IBID_UNF,IBI Data MEM underflow" "0,1"
bitfld.long 0x10 10. "IBIR_THR,IBI Response Queue threshold" "0,1"
newline
bitfld.long 0x10 9. "IBIR_UNF,IBI Response Queue underflow" "0,1"
bitfld.long 0x10 8. "IBIR_OVF,IBI Response Queue onverflow" "0,1"
newline
bitfld.long 0x10 7. "RX_THR,Rx Data MEM threshold" "0,1"
bitfld.long 0x10 6. "RX_UNF,Rx Data MEM underflow" "0,1"
newline
bitfld.long 0x10 5. "CMDD_EMP,Command Request Queue Empty" "0,1"
bitfld.long 0x10 4. "CMDD_THR,Command Request Queue Threshold" "0,1"
newline
bitfld.long 0x10 3. "CMDD_OVF,Command Request Queue Overflow" "0,1"
bitfld.long 0x10 2. "CMDR_THR,Command Response Queue Threshold" "0,1"
newline
bitfld.long 0x10 1. "CMDR_UNF,Command Response Queue Underflow" "0,1"
bitfld.long 0x10 0. "CMDR_OVF,Command Response Queue Overflow" "0,1"
line.long 0x14 "I3C_MST_STATUS0,Return to"
hexmask.long.word 0x14 19.--31. 1. "RSVD2,Reserved"
rbitfld.long 0x14 18. "IDLE,Indicates when the core is IDLE and ready to accept new commands" "0,1"
newline
bitfld.long 0x14 17. "HALTED,Core Halted" "0,1"
rbitfld.long 0x14 16. "OP_MODE,Indicates current mode of the controller" "0,1"
newline
rbitfld.long 0x14 14.--15. "RSVD1,Reserved" "0,1,2,3"
rbitfld.long 0x14 13. "TX_FULL,TX Full" "0,1"
newline
rbitfld.long 0x14 12. "IBID_FULL,IBID Full" "0,1"
rbitfld.long 0x14 11. "IBIR_FULL," "0,1"
newline
rbitfld.long 0x14 10. "RX_FULL,RX Full" "0,1"
rbitfld.long 0x14 9. "CMDD_FULL,CMDD Full" "0,1"
newline
rbitfld.long 0x14 8. "CMDR_FULL," "0,1"
rbitfld.long 0x14 6.--7. "RSVD0,Reserved" "0,1,2,3"
newline
rbitfld.long 0x14 5. "TX_EMP,TX Empty" "0,1"
rbitfld.long 0x14 4. "IBID_EMP,IBID Empty" "0,1"
newline
rbitfld.long 0x14 3. "IBIR_EMP," "0,1"
rbitfld.long 0x14 2. "RX_EMP,RX Empty" "0,1"
newline
rbitfld.long 0x14 1. "CMDD_EMP,CMDD Empty" "0,1"
rbitfld.long 0x14 0. "CMDR_EMP," "0,1"
line.long 0x18 "I3C_CMDR,Return to"
bitfld.long 0x18 28.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "ERROR,This field contains the code of an error that has occured during the last transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 8.--19. 1. "XFER_BYTES,The number of transferred bytes [SDR] or transferred words [DDR] during the last command"
newline
hexmask.long.byte 0x18 0.--7. 1. "CMD_ID,CMD_ID - command identifier"
line.long 0x1C "I3C_IBIR,Return to"
hexmask.long.tbyte 0x1C 13.--31. 1. "RSVD0,Reserved"
bitfld.long 0x1C 12. "RESP,If HIGH IBI has been ACKed NACK response otherwise" "0,1"
newline
bitfld.long 0x1C 8.--11. "SLV_ID,ID of a Slave that has issued an IBI request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 7. "ERROR,Set to 1 if IBI Data FIFO overflow has occured during the transaction" "0,1"
newline
bitfld.long 0x1C 2.--6. "XFER_BYTES,Number of received DATA bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--1. "IBI_TYPE,This field contains the type of an IBI" "0,1,2,3"
line.long 0x20 "I3C_SLV_IER,Return to"
bitfld.long 0x20 21. "DEFSLVS,DEFSLVS interrupt Enable" "0,1"
bitfld.long 0x20 20. "TM,TM interrupt Enable" "0,1"
newline
bitfld.long 0x20 19. "ERROR,ERROR interrupt Enable" "0,1"
bitfld.long 0x20 18. "EVENT_UP,EVENT_UP interrupt Enable" "0,1"
newline
bitfld.long 0x20 17. "HJ_DONE,HJ_DONE interrupt Enable" "0,1"
bitfld.long 0x20 16. "MR_DONE,MR_DONE interrupt Enable" "0,1"
newline
bitfld.long 0x20 15. "DA_UPDATE,DA_UPDATE interrupt Enable" "0,1"
bitfld.long 0x20 14. "SDR_FAIL,SDR_FAIL interrupt Enable" "0,1"
newline
bitfld.long 0x20 13. "DDR_FAIL,DDR_FAIL interrupt Enable" "0,1"
bitfld.long 0x20 12. "M_RD_ABORT,M_RD_ABORT interrupt Enable" "0,1"
newline
bitfld.long 0x20 11. "DDR_RX_THR,DDR_RX_THR interrupt Enable" "0,1"
bitfld.long 0x20 10. "DDR_TX_THR,DDR_TX_THR interrupt Enable" "0,1"
newline
bitfld.long 0x20 9. "SDR_RX_THR,SDR_RX_THR interrupt Enable" "0,1"
bitfld.long 0x20 8. "SDR_TX_THR,SLV_SDR_TX_THR interrupt Enable" "0,1"
newline
bitfld.long 0x20 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Enable" "0,1"
bitfld.long 0x20 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Enable" "0,1"
newline
bitfld.long 0x20 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Enable" "0,1"
bitfld.long 0x20 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Enable" "0,1"
newline
bitfld.long 0x20 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Enable" "0,1"
bitfld.long 0x20 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Enable" "0,1"
newline
bitfld.long 0x20 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Enable" "0,1"
bitfld.long 0x20 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Enable" "0,1"
line.long 0x24 "I3C_SLV_IDR,Return to"
bitfld.long 0x24 21. "DEFSLVS,DEFSLVS interrupt Disable" "0,1"
bitfld.long 0x24 20. "TM,TM interrupt Disable" "0,1"
newline
bitfld.long 0x24 19. "ERROR,ERROR interrupt Disable" "0,1"
bitfld.long 0x24 18. "EVENT_UP,EVENT_UP interrupt Disable" "0,1"
newline
bitfld.long 0x24 17. "HJ_DONE,HJ_DONE interrupt Disable" "0,1"
bitfld.long 0x24 16. "MR_DONE,MR_DONE interrupt Disable" "0,1"
newline
bitfld.long 0x24 15. "DA_UPDATE,DA_UPDATE interrupt Disable" "0,1"
bitfld.long 0x24 14. "SDR_FAIL,SDR_FAIL interrupt Disable" "0,1"
newline
bitfld.long 0x24 13. "DDR_FAIL,DDR_FAIL interrupt Disable" "0,1"
bitfld.long 0x24 12. "M_RD_ABORT,M_RD_ABORT interrupt Disable" "0,1"
newline
bitfld.long 0x24 11. "DDR_RX_THR,DDR_RX_THR interrupt Disable" "0,1"
bitfld.long 0x24 10. "DDR_TX_THR,DDR_TX_THR interrupt Disable" "0,1"
newline
bitfld.long 0x24 9. "SDR_RX_THR,SDR_RX_THR interrupt Disable" "0,1"
bitfld.long 0x24 8. "SDR_TX_THR,SDR_TX_THR interrupt Disable" "0,1"
newline
bitfld.long 0x24 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Disable" "0,1"
bitfld.long 0x24 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Disable" "0,1"
newline
bitfld.long 0x24 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Disable" "0,1"
bitfld.long 0x24 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Disable" "0,1"
newline
bitfld.long 0x24 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Disable" "0,1"
bitfld.long 0x24 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Disable" "0,1"
newline
bitfld.long 0x24 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Disable" "0,1"
bitfld.long 0x24 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Disable" "0,1"
line.long 0x28 "I3C_SLV_IMR,Return to"
bitfld.long 0x28 21. "DEFSLVS,DEFSLVS interrupt Mask" "0,1"
bitfld.long 0x28 20. "TM,TM interrupt Mask" "0,1"
newline
bitfld.long 0x28 19. "ERROR,ERROR interrupt Mask" "0,1"
bitfld.long 0x28 18. "EVENT_UP,EVENT_UP interrupt Mask" "0,1"
newline
bitfld.long 0x28 17. "HJ_DONE,HJ_DONE interrupt Mask" "0,1"
bitfld.long 0x28 16. "MR_DONE,MR_DONE interrupt Mask" "0,1"
newline
bitfld.long 0x28 15. "DA_UPDATE,DA_UPDATE interrupt Mask" "0,1"
bitfld.long 0x28 14. "SDR_FAIL,SDR_FAIL interrupt Mask" "0,1"
newline
bitfld.long 0x28 13. "DDR_FAIL,DDR_FAIL interrupt Mask" "0,1"
bitfld.long 0x28 12. "M_RD_ABORT,M_RD_ABORT interrupt Mask" "0,1"
newline
bitfld.long 0x28 11. "DDR_RX_THR,DDR_RX_THR interrupt Mask" "0,1"
bitfld.long 0x28 10. "DDR_TX_THR,DDR_TX_THR interrupt Mask" "0,1"
newline
bitfld.long 0x28 9. "SDR_RX_THR,SDR_RX_THR interrupt Mask" "0,1"
bitfld.long 0x28 8. "SDR_TX_THR,SDR_TX_THR interrupt Mask" "0,1"
newline
bitfld.long 0x28 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Mask" "0,1"
bitfld.long 0x28 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Mask" "0,1"
newline
bitfld.long 0x28 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Mask" "0,1"
bitfld.long 0x28 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Mask" "0,1"
newline
bitfld.long 0x28 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Mask" "0,1"
bitfld.long 0x28 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Mask" "0,1"
newline
bitfld.long 0x28 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Mask" "0,1"
bitfld.long 0x28 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Mask" "0,1"
line.long 0x2C "I3C_SLV_ICR,Return to"
bitfld.long 0x2C 21. "DEFSLVS,DEFSLVS interrupt Clear" "0,1"
bitfld.long 0x2C 20. "TM,TM interrupt Clear" "0,1"
newline
bitfld.long 0x2C 19. "ERROR,ERROR interrupt Clear" "0,1"
bitfld.long 0x2C 18. "EVENT_UP,EVENT_UP interrupt Clear" "0,1"
newline
bitfld.long 0x2C 17. "HJ_DONE,HJ_DONE interrupt Clear" "0,1"
bitfld.long 0x2C 16. "MR_DONE,MR_DONE interrupt Clear" "0,1"
newline
bitfld.long 0x2C 15. "DA_UPDATE,DA_UPDATE interrupt Clear" "0,1"
bitfld.long 0x2C 14. "SDR_FAIL,SDR_FAIL interrupt Clear" "0,1"
newline
bitfld.long 0x2C 13. "DDR_FAIL,DDR_FAIL interrupt Clear" "0,1"
bitfld.long 0x2C 12. "M_RD_ABORT,M_RD_ABORT interrupt Clear" "0,1"
newline
bitfld.long 0x2C 11. "DDR_RX_THR,DDR_RX_THR interrupt Clear" "0,1"
bitfld.long 0x2C 10. "DDR_TX_THR,DDR_TX_THR interrupt Clear" "0,1"
newline
bitfld.long 0x2C 9. "SDR_RX_THR,SDR_RX_THR interrupt Clear" "0,1"
bitfld.long 0x2C 8. "SDR_TX_THR,SDR_TX_THR interrupt Clear" "0,1"
newline
bitfld.long 0x2C 7. "DDR_RX_UNF,DDR_RX_UNF interrupt Clear" "0,1"
bitfld.long 0x2C 6. "DDR_TX_OVF,DDR_TX_OVF interrupt Clear" "0,1"
newline
bitfld.long 0x2C 5. "SDR_RX_UNF,SDR_RX_UNF interrupt Clear" "0,1"
bitfld.long 0x2C 4. "SDR_TX_OVF,SDR_TX_OVF interrupt Clear" "0,1"
newline
bitfld.long 0x2C 3. "DDR_RD_COMP,DDR_RD_COMP interrupt Clear" "0,1"
bitfld.long 0x2C 2. "DDR_WR_COMP,DDR_WR_COMP interrupt Clear" "0,1"
newline
bitfld.long 0x2C 1. "SDR_RD_COMP,SDR_RD_COMP interrupt Clear" "0,1"
bitfld.long 0x2C 0. "SDR_WR_COMP,SDR_WR_COMP interrupt Clear" "0,1"
line.long 0x30 "I3C_SLV_ISR,Return to"
bitfld.long 0x30 21. "DEFSLVS,This interrupt is triggered whenever I3C-Slave DEFSLVS CCC command is received" "0,1"
bitfld.long 0x30 20. "TM,This interrupt is triggered whenever I3C-Slave is not in Test Mode and ENTTM CCC command with byte value of 0x01 [general Test Mode] is received" "0,1"
newline
bitfld.long 0x30 19. "ERROR,This event is triggered whenever SDR Error is detected - applicable for S0 S1 S2 S4 and S5 Errors from MIPI spec" "0,1"
bitfld.long 0x30 18. "EVENT_UP,This event is triggered whenever DISEC CCC or ENEC CCC is received" "0,1"
newline
bitfld.long 0x30 17. "HJ_DONE,This event is triggered whenever Hot-Join request is completed" "0,1"
bitfld.long 0x30 16. "MR_DONE,This event is triggered whenever Mastership Request is completed" "0,1"
newline
bitfld.long 0x30 15. "DA_UPDATE,This event is triggered whenever Dynamic Address of the device has been updated" "0,1"
bitfld.long 0x30 14. "SDR_FAIL,This event is triggered whenever fail event during SDR transfer is detected [applicable for Private Write transfers only]" "0,1"
newline
bitfld.long 0x30 13. "DDR_FAIL,This event is triggered whenever fail event during DDR transfer is detected" "0,1"
bitfld.long 0x30 12. "M_RD_ABORT,Read Transfer Aborted by Master" "0,1"
newline
bitfld.long 0x30 11. "DDR_RX_THR,This event is triggered whenever threshold level for DDR Rx DATA Buffer is reached" "0,1"
bitfld.long 0x30 10. "DDR_TX_THR,This event is triggered whenever threshold level for DDR Tx DATA Buffer is reached" "0,1"
newline
bitfld.long 0x30 9. "SDR_RX_THR,Rx DATA Buffer Threshold" "0,1"
bitfld.long 0x30 8. "SDR_TX_THR,Tx DATA Buffer Threshold" "0,1"
newline
bitfld.long 0x30 7. "DDR_RX_UNF,Set if the host attempts to read from the DDR_RX_FIFO register when there is no more data" "0,1"
bitfld.long 0x30 6. "DDR_TX_OVF,Set if the host attempts to write to DDR_TX_FIFO register more times than the FIFO depth" "0,1"
newline
bitfld.long 0x30 5. "SDR_RX_UNF,Rx DATA Buffer Underflow" "0,1"
bitfld.long 0x30 4. "SDR_TX_OVF,Tx DATA Buffer Overflow" "0,1"
newline
bitfld.long 0x30 3. "DDR_RD_COMP,This bit is set whenever the Slave terminates the DDR Read transfer" "0,1"
bitfld.long 0x30 2. "DDR_WR_COMP,This bit is set whenever the Master terminates the DDR Write transfer" "0,1"
newline
bitfld.long 0x30 1. "SDR_RD_COMP,This bit is set whenever the Slave terminates the SDR Private Read transfer" "0,1"
bitfld.long 0x30 0. "SDR_WR_COMP,This bit is set whenever the Master terminates the SDR Private Write transfer" "0,1"
line.long 0x34 "I3C_SLV_STATUS0,Return to"
hexmask.long.byte 0x34 24.--31. 1. "RSVD0,Reserved"
hexmask.long.byte 0x34 16.--23. 1. "REG_ADDR,Private Read/Write Address"
newline
hexmask.long.word 0x34 0.--15. 1. "XFERRED_BYTES,Number of transferred bytes in SDR transactions"
line.long 0x38 "I3C_SLV_STATUS1,Return to"
hexmask.long.word 0x38 22.--31. 1. "RSVD1,Reserved"
bitfld.long 0x38 20.--21. "ENTAS,Bits that indicate current Activity State" "0,1,2,3"
newline
bitfld.long 0x38 19. "VEN_TM,Vendor Test Mode" "0,1"
bitfld.long 0x38 18. "HJ_DIS,Hot-Join Disabled" "0,1"
newline
bitfld.long 0x38 17. "MR_DIS,This bit is set whenever MR request is disabled by Current I3C-Master using DISEC CCC" "0,1"
bitfld.long 0x38 16. "PROT_ERROR,Protocol Error Condition Indicator" "0,1"
newline
hexmask.long.byte 0x38 9.--15. 1. "DA,Slave Dynamic Address"
bitfld.long 0x38 8. "HAS_DA,This bit is set whenever Slave has Dynamic Address assigned" "0,1"
newline
bitfld.long 0x38 7. "DDRRX_FULL,This bit is set whenever" "0,1"
bitfld.long 0x38 6. "DDRTX_FULL,This bit is set whenever" "0,1"
newline
bitfld.long 0x38 5. "DDRRX_EMPTY,This bit is set whenever" "0,1"
bitfld.long 0x38 4. "DDRTX_EMPTY,This bit is set whenever" "0,1"
newline
bitfld.long 0x38 3. "SDRRX_FULL,This bit is set whenever SDR_RX_FIFO is full" "0,1"
bitfld.long 0x38 2. "SDRTX_FULL,This bit is set whenever SDR_TX_FIFO is full" "0,1"
newline
bitfld.long 0x38 1. "SDRRX_EMPTY,This bit is set whenever SDR_RX_FIFO is empty" "0,1"
bitfld.long 0x38 0. "SDRTX_EMPTY,This bit is set whenever SDR_TX_FIFO is empty" "0,1"
group.long 0x60++0x0B
line.long 0x00 "I3C_CMD0_FIFO,Return to"
bitfld.long 0x00 31. "IS_DDR,IS_DDR - DDR command" "0,1"
bitfld.long 0x00 30. "IS_CCC,IsCCC" "0,1"
newline
bitfld.long 0x00 29. "BCH,BCH - Broadcast Header" "0,1"
bitfld.long 0x00 27.--28. "XMIT_MODE,Defines transfer modes for I3C private read/write commands [not CCC] the following options are available" "0,1,2,3"
newline
bitfld.long 0x00 26. "SBCA,SBCA - Sixteen Bits CSR Addressing" "0,1"
bitfld.long 0x00 25. "RSBC,RSBC - Repeated Start Between Commands" "0,1"
newline
bitfld.long 0x00 24. "IS10B,Is10B - Normal/Extended Address" "0,1"
hexmask.long.word 0x00 12.--23. 1. "PL_LEN,PL_LEN - Payload Length"
newline
bitfld.long 0x00 8.--10. "DEV_ADDR_MSB,DEV_ADDR_MSB - legacy I2C Extended Address" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address"
newline
bitfld.long 0x00 0. "RNW,RnW - Read no" "0,1"
line.long 0x04 "I3C_CMD1_FIFO,Return to"
hexmask.long.byte 0x04 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]"
hexmask.long.byte 0x04 16.--23. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x04 8.--15. 1. "CSRADDR1,CSR ADDR"
hexmask.long.byte 0x04 0.--7. 1. "CCC_CSRADDR0,CCC/CSR ADDR"
line.long 0x08 "I3C_TX_FIFO,Return to"
group.long 0x70++0x0B
line.long 0x00 "I3C_IMD_CMD0,Return to"
bitfld.long 0x00 12.--14. "PL_LEN,PL_LEN - Payload Length" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--7. 1. "DEV_ADDR,DEV_ADDR - Static/Dynamic slave Address"
newline
bitfld.long 0x00 0. "RNW,RnW - Read no" "0,1"
line.long 0x04 "I3C_IMD_CMD1,Return to"
hexmask.long.byte 0x04 24.--31. 1. "CMD_ID,COMMAND ID - generated by the host and used by the DMA to sort incoming read data to different consumers [channelization]"
hexmask.long.word 0x04 8.--23. 1. "RSVD0,Reserved"
newline
hexmask.long.byte 0x04 0.--7. 1. "CCC,CCC code"
line.long 0x08 "I3C_IMD_DATA,Return to"
rgroup.long 0x80++0x1F
line.long 0x00 "I3C_RX_FIFO,Return to"
line.long 0x04 "I3C_IBI_DATA_FIFO,Return to"
line.long 0x08 "I3C_SLV_DDR_TX_FIFO,Return to"
hexmask.long.tbyte 0x08 0.--19. 1. "DDR_SLAVE_TX_DATA_FIFO,DDR Tx Data FIFO stores number of words to be sent with particular DDR command in slave mode"
line.long 0x0C "I3C_SLV_DDR_RX_FIFO,Return to"
hexmask.long.tbyte 0x0C 0.--19. 1. "DDR_SLAVE_RX_DATA_FIFO,DDR Rx Data FIFO stores number of words to be received with particular DDR command in slave mode"
line.long 0x10 "I3C_CMD_IBI_THR_CTRL,Return to"
rbitfld.long 0x10 30.--31. "RSVD3,Reserved" "0,1,2,3"
bitfld.long 0x10 24.--29. "IBIR_THR,Threshold configuration value for IBI RESP memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 21.--23. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--20. "CMDR_THR,Threshold configuration value for Command RESP memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x10 14.--15. "RSVD1,Reserved" "0,1,2,3"
bitfld.long 0x10 8.--13. "IBID_THR,Threshold configuration value for IBI DATA memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x10 5.--7. "RSVD0,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--4. "CMDD_THR,Threshold configuration value for Command REQ memory block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "I3C_TX_RX_THR_CTRL,Return to"
hexmask.long.word 0x14 16.--31. 1. "RX_THR,Threshold configuration value for Rx Data memory block"
hexmask.long.word 0x14 0.--15. 1. "TX_THR,Threshold configuration value for Tx Data memory block"
line.long 0x18 "I3C_SLV_DDR_TX_RX_THR_CTRL,Return to"
hexmask.long.word 0x18 16.--31. 1. "SLV_DDR_RX_THR,Threshold configuration value for Slave Mode DDR Rx Data memory block"
hexmask.long.word 0x18 0.--15. 1. "SLV_DDR_TX_THR,Threshold configuration value for Slave Mode DDR Tx Data memory block"
line.long 0x1C "I3C_FLUSH_CTRL,Return to"
bitfld.long 0x1C 24. "IBI_RESP_FLUSH,When asserted while controller is disabled the IBI Response Queue read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
bitfld.long 0x1C 23. "CMD_RESP_FLUSH,When asserted while controller is disabled the Command Response Queue read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
newline
bitfld.long 0x1C 22. "SLV_DDR_RX_FLUSH,When asserted while controller is disabled the SLV DDR Rx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
bitfld.long 0x1C 21. "SLV_DDR_TX_FLUSH,When asserted while controller is disabled the SLV DDR Tx Data memory block read/write pointers will be set to 0 effectively make the FIFO empty" "0,1"
newline
bitfld.long 0x1C 20. "IMM_CMD_FLUSH,When asserted while controller is disabled the immediate command/data register will be cleared" "0,1"
bitfld.long 0x1C 19. "IBI_FLUSH,When asserted while controller is disabled the IBI data memory block read/write pointers will be set to 0" "0,1"
newline
bitfld.long 0x1C 18. "RX_FLUSH,When asserted while controller is disabled the Rx Data memory block read/write pointers will be set to 0" "0,1"
bitfld.long 0x1C 17. "TX_FLUSH,When asserted while controller is disabled the Tx Data memory block read/write pointers will be set to 0" "0,1"
newline
bitfld.long 0x1C 16. "CMD_FLUSH,When asserted while controller is disabled the command Command memory block read/write pointers will be set to 0" "0,1"
group.long 0xB0++0x0B
line.long 0x00 "I3C_TTO_PRESCL_CTRL0,Return to"
rbitfld.long 0x00 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 16.--25. 1. "DIV_B,Divider B"
newline
rbitfld.long 0x00 11.--15. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--10. 1. "DIV_A,Divider A"
line.long 0x04 "I3C_TTO_PRESCL_CTRL1,Return to"
rbitfld.long 0x04 26.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x04 16.--25. 1. "DIV_B,Divider B"
newline
hexmask.long.byte 0x04 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "DIV_A,Divider A"
line.long 0x08 "I3C_DEVS_CTRL,Return to"
rbitfld.long 0x08 28.--31. "RSVD1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 27. "DEV11_CLR,Clear DevID11 retaining registers set" "0,1"
newline
bitfld.long 0x08 26. "DEV10_CLR,Clear DevID10 retaining registers set" "0,1"
bitfld.long 0x08 25. "DEV9_CLR,Clear DevID9 retaining registers set" "0,1"
newline
bitfld.long 0x08 24. "DEV8_CLR,Clear DevID8 retaining registers set" "0,1"
bitfld.long 0x08 23. "DEV7_CLR,Clear DevID7 retaining registers set" "0,1"
newline
bitfld.long 0x08 22. "DEV6_CLR,Clear DevID6 retaining registers set" "0,1"
bitfld.long 0x08 21. "DEV5_CLR,Clear DevID5 retaining registers set" "0,1"
newline
bitfld.long 0x08 20. "DEV4_CLR,Clear DevID4 retaining registers set" "0,1"
bitfld.long 0x08 19. "DEV3_CLR,Clear DevID3 retaining registers set" "0,1"
newline
bitfld.long 0x08 18. "DEV2_CLR,Clear DevID2 retaining registers set" "0,1"
bitfld.long 0x08 17. "DEV1_CLR,Clear DevID1 retaining registers set" "0,1"
newline
rbitfld.long 0x08 12.--16. "RSVD0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 11. "DEV11_ACTIVE,DevID11 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 10. "DEV10_ACTIVE,DevID10 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 9. "DEV9_ACTIVE,DevID9 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 8. "DEV8_ACTIVE,DevID8 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 7. "DEV7_ACTIVE,DevID7 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 6. "DEV6_ACTIVE,DevID6 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 5. "DEV5_ACTIVE,DevID5 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 4. "DEV4_ACTIVE,DevID4 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 3. "DEV3_ACTIVE,DevID3 is active - has either valid DA or SA" "0,1"
newline
bitfld.long 0x08 2. "DEV2_ACTIVE,DevID2 is active - has either valid DA or SA" "0,1"
bitfld.long 0x08 1. "DEV1_ACTIVE,DevID1 is active - has either valid DA or SA" "0,1"
newline
rbitfld.long 0x08 0. "DEV0_ACTIVE,DevID0 is active - has either valid DA or SA" "0,1"
group.long 0xC0++0x0B
line.long 0x00 "I3C_DEV_ID0_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 0 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
rbitfld.long 0x00 9. "IS_I3C,Device 0 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 0 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID0_RR1,Return to"
line.long 0x08 "I3C_DEV_ID0_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 0 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 0 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 0 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xD0++0x0B
line.long 0x00 "I3C_DEV_ID1_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 1 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 1 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 1 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID1_RR1,Return to"
line.long 0x08 "I3C_DEV_ID1_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 1 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 1 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 1 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xE0++0x0B
line.long 0x00 "I3C_DEV_ID2_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 2 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 2 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 2 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID2_RR1,Return to"
line.long 0x08 "I3C_DEV_ID2_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 2 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 2 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 2 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0xF0++0x0B
line.long 0x00 "I3C_DEV_ID3_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 3 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 3 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 3 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID3_RR1,Return to"
line.long 0x08 "I3C_DEV_ID3_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 3 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 3 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 3 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x100++0x0B
line.long 0x00 "I3C_DEV_ID4_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 4 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 4 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 4 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID4_RR1,Return to"
line.long 0x08 "I3C_DEV_ID4_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 4 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 4 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 4 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x110++0x0B
line.long 0x00 "I3C_DEV_ID5_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 5 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 5 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 5 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID5_RR1,Return to"
line.long 0x08 "I3C_DEV_ID5_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 5 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 5 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 5 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x120++0x0B
line.long 0x00 "I3C_DEV_ID6_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 6 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 6 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 6 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID6_RR1,Return to"
line.long 0x08 "I3C_DEV_ID6_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 6 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 6 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 6 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x130++0x0B
line.long 0x00 "I3C_DEV_ID7_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 7 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 7 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 7 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID7_RR1,Return to"
line.long 0x08 "I3C_DEV_ID7_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 7 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 7 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 7 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x140++0x0B
line.long 0x00 "I3C_DEV_ID8_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 8 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 8 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 8 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID8_RR1,Return to"
line.long 0x08 "I3C_DEV_ID8_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 8 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 8 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 8 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x150++0x0B
line.long 0x00 "I3C_DEV_ID9_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 9 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 9 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 9 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID9_RR1,Return to"
line.long 0x08 "I3C_DEV_ID9_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 9 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 9 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 9 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x160++0x0B
line.long 0x00 "I3C_DEV_ID10_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 10 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 10 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 10 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID10_RR1,Return to"
line.long 0x08 "I3C_DEV_ID10_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 10 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 10 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 10 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x170++0x0B
line.long 0x00 "I3C_DEV_ID11_RR0,Return to"
bitfld.long 0x00 13.--15. "LVR_SA_MSB,MSB bits of Legacy I2C Device with" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 12. "RSVD2,Reserved" "0,1"
newline
bitfld.long 0x00 11. "LVR_EXT_ADDR,Device 11 Address mode used" "0,1"
rbitfld.long 0x00 10. "RSVD1,Reserved" "0,1"
newline
bitfld.long 0x00 9. "IS_I3C,Device 11 I3C mode Operation" "0,1"
rbitfld.long 0x00 8. "RSVD0,Reserved" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DEV_ADDR,Device 11 Slave Dynamic [Static/Legacy] Address bits"
line.long 0x04 "I3C_DEV_ID11_RR1,Return to"
line.long 0x08 "I3C_DEV_ID11_RR2,Return to"
hexmask.long.word 0x08 16.--31. 1. "PID_LSB,Device 11 15 to 0 Dev ID bits"
hexmask.long.byte 0x08 8.--15. 1. "BCR,Device 11 BCR register"
newline
hexmask.long.byte 0x08 0.--7. 1. "DCR_LVR,Device 11 DCR [if I3C device] or LVR [if I2C device] register"
group.long 0x180++0x17
line.long 0x00 "I3C_SIR_MAP0,Return to"
bitfld.long 0x00 30.--31. "DEVID1_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3"
bitfld.long 0x00 29. "DEVID1_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x00 24.--28. "DEVID1_PL,Slave-initiated request Device ID0 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 17.--23. 1. "DEVID1_DA,Slave-initiated request Device ID0 DA"
newline
bitfld.long 0x00 16. "DEVID1_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1"
bitfld.long 0x00 14.--15. "DEVID0_ROLE,Slave-initiated request Device ID0 BCR role" "0,1,2,3"
newline
bitfld.long 0x00 13. "DEVID0_SLOW,Slave-initiated request Device ID0 Max Data Speed Limitation" "0,1"
bitfld.long 0x00 8.--12. "DEVID0_PL,Slave-initiated request Device ID0 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 1.--7. 1. "DEVID0_DA,Slave-initiated request Device ID0 DA"
bitfld.long 0x00 0. "DEVID0_RESP,Slave-initiated request Device ID0 Ack/Nack response" "0,1"
line.long 0x04 "I3C_SIR_MAP1,Return to"
bitfld.long 0x04 30.--31. "DEVID3_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3"
bitfld.long 0x04 29. "DEVID3_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x04 24.--28. "DEVID3_PL,Slave-initiated request Device ID2 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x04 17.--23. 1. "DEVID3_DA,Slave-initiated request Device ID2 DA"
newline
bitfld.long 0x04 16. "DEVID3_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1"
bitfld.long 0x04 14.--15. "DEVID2_ROLE,Slave-initiated request Device ID2 BCR role" "0,1,2,3"
newline
bitfld.long 0x04 13. "DEVID2_SLOW,Slave-initiated request Device ID2 Max Data Speed Limitation" "0,1"
bitfld.long 0x04 8.--12. "DEVID2_PL,Slave-initiated request Device ID2 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 1.--7. 1. "DEVID2_DA,Slave-initiated request Device ID2 DA"
bitfld.long 0x04 0. "DEVID2_RESP,Slave-initiated request Device ID2 Ack/Nack response" "0,1"
line.long 0x08 "I3C_SIR_MAP2,Return to"
bitfld.long 0x08 30.--31. "DEVID5_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3"
bitfld.long 0x08 29. "DEVID5_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x08 24.--28. "DEVID5_PL,Slave-initiated request Device ID4 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x08 17.--23. 1. "DEVID5_DA,Slave-initiated request Device ID4 DA"
newline
bitfld.long 0x08 16. "DEVID5_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1"
bitfld.long 0x08 14.--15. "DEVID4_ROLE,Slave-initiated request Device ID4 BCR role" "0,1,2,3"
newline
bitfld.long 0x08 13. "DEVID4_SLOW,Slave-initiated request Device ID4 Max Data Speed Limitation" "0,1"
bitfld.long 0x08 8.--12. "DEVID4_PL,Slave-initiated request Device ID4 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x08 1.--7. 1. "DEVID4_DA,Slave-initiated request Device ID4 DA"
bitfld.long 0x08 0. "DEVID4_RESP,Slave-initiated request Device ID4 Ack/Nack response" "0,1"
line.long 0x0C "I3C_SIR_MAP3,Return to"
bitfld.long 0x0C 30.--31. "DEVID7_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3"
bitfld.long 0x0C 29. "DEVID7_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x0C 24.--28. "DEVID7_PL,Slave-initiated request Device ID6 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 17.--23. 1. "DEVID7_DA,Slave-initiated request Device ID6 DA"
newline
bitfld.long 0x0C 16. "DEVID7_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1"
bitfld.long 0x0C 14.--15. "DEVID6_ROLE,Slave-initiated request Device ID6 BCR role" "0,1,2,3"
newline
bitfld.long 0x0C 13. "DEVID6_SLOW,Slave-initiated request Device ID6 Max Data Speed Limitation" "0,1"
bitfld.long 0x0C 8.--12. "DEVID6_PL,Slave-initiated request Device ID6 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x0C 1.--7. 1. "DEVID6_DA,Slave-initiated request Device ID6 DA"
bitfld.long 0x0C 0. "DEVID6_RESP,Slave-initiated request Device ID6 Ack/Nack response" "0,1"
line.long 0x10 "I3C_SIR_MAP4,Return to"
bitfld.long 0x10 30.--31. "DEVID9_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3"
bitfld.long 0x10 29. "DEVID9_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x10 24.--28. "DEVID9_PL,Slave-initiated request Device ID8 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x10 17.--23. 1. "DEVID9_DA,Slave-initiated request Device ID8 DA"
newline
bitfld.long 0x10 16. "DEVID9_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1"
bitfld.long 0x10 14.--15. "DEVID8_ROLE,Slave-initiated request Device ID8 BCR role" "0,1,2,3"
newline
bitfld.long 0x10 13. "DEVID8_SLOW,Slave-initiated request Device ID8 Max Data Speed Limitation" "0,1"
bitfld.long 0x10 8.--12. "DEVID8_PL,Slave-initiated request Device ID8 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x10 1.--7. 1. "DEVID8_DA,Slave-initiated request Device ID8 DA"
bitfld.long 0x10 0. "DEVID8_RESP,Slave-initiated request Device ID8 Ack/Nack response" "0,1"
line.long 0x14 "I3C_SIR_MAP5,Return to"
bitfld.long 0x14 14.--15. "DEVID10_ROLE,Slave-initiated request Device ID10 BCR role" "0,1,2,3"
bitfld.long 0x14 13. "DEVID10_SLOW,Slave-initiated request Device ID10 Max Data Speed Limitation" "0,1"
newline
bitfld.long 0x14 8.--12. "DEVID10_PL,Slave-initiated request Device ID10 payload length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 1.--7. 1. "DEVID10_DA,Slave-initiated request Device ID10 DA"
newline
bitfld.long 0x14 0. "DEVID10_RESP,Slave-initiated request Device ID10 Ack/Nack response" "0,1"
rgroup.long 0x1A0++0x03
line.long 0x00 "I3C_GPIR_WORD0,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RSVD2,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "GPI0,User Defined GPI Register 0"
rgroup.long 0x220++0x03
line.long 0x00 "I3C_GPOR_WORD0,Return to"
hexmask.long.byte 0x00 24.--31. 1. "RSVD2,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "RSVD1,Reserved"
newline
hexmask.long.byte 0x00 8.--15. 1. "RSVD0,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "GPO0,User Defined GPO Register 0"
group.long 0x300++0x13
line.long 0x00 "I3C_ASF_INT_STATUS,Return to"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "I3C_ASF_INT_RAW_STATUS,Return to"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
newline
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "I3C_ASF_INT_MASK,Return to"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "I3C_ASF_INT_TEST,Return to"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt" "0,1"
newline
bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
newline
bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "I3C_ASF_FATAL_NONFATAL_SELECT,Return to"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x320++0x0B
line.long 0x00 "I3C_ASF_SRAM_CORR_FAULT_STATUS,Return to"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "I3C_ASF_SRAM_UNCORR_FAULT_STATUS,Return to"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "I3C_ASF_SRAM_FAULT_STATS,Return to"
hexmask.long.word 0x08 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x330++0x0B
line.long 0x00 "I3C_ASF_TRANS_TO_CTRL,Return to"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "I3C_ASF_TRANS_TO_FAULT_MASK,Return to"
bitfld.long 0x04 3. "ASF_TRANS_TO_FAULT_3_MASK,Mask bit for apb transaction timeout fault" "0,1"
bitfld.long 0x04 2. "ASF_TRANS_TO_FAULT_2_MASK,Mask bit for I3C transaction SCL low timeout fault" "0,1"
newline
bitfld.long 0x04 1. "ASF_TRANS_TO_FAULT_1_MASK,Mask bit for I3C transaction SCL high timeout fault" "0,1"
bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask bit for I3C transaction first SCL high timeout fault" "0,1"
line.long 0x08 "I3C_ASF_TRANS_TO_FAULT_STATUS,Return to"
bitfld.long 0x08 3. "ASF_TRANS_TO_FAULT_3_STATUS,Status bits for apb transaction timeout fault" "0,1"
bitfld.long 0x08 2. "ASF_TRANS_TO_FAULT_2_STATUS,Status bits for I3C transaction SCL low timeout fault" "0,1"
newline
bitfld.long 0x08 1. "ASF_TRANS_TO_FAULT_1_STATUS,Status bits for I3C transaction SCL high timeout fault" "0,1"
bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for I3C transaction first SCL high timeout fault" "0,1"
group.long 0x340++0x07
line.long 0x00 "I3C_ASF_PROTOCOL_FAULT_MASK,Return to"
bitfld.long 0x00 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_MASK,Mask bit for slv_sdr_rd_abort protocol fault source" "0,1"
bitfld.long 0x00 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_MASK,Mask bit for slv_ddr_fail protocol fault source" "0,1"
newline
bitfld.long 0x00 10. "ASF_PROTOCOL_FAULT_S5_MASK,Mask bit for s5 protocol fault source" "0,1"
bitfld.long 0x00 9. "ASF_PROTOCOL_FAULT_S4_MASK,Mask bit for s4 protocol fault source" "0,1"
newline
bitfld.long 0x00 8. "ASF_PROTOCOL_FAULT_S3_MASK,Mask bit for s3 protocol fault source" "0,1"
bitfld.long 0x00 7. "ASF_PROTOCOL_FAULT_S2_MASK,Mask bit for s2 protocol fault source" "0,1"
newline
bitfld.long 0x00 6. "ASF_PROTOCOL_FAULT_S1_MASK,Mask bit for s1 protocol fault source" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_FAULT_S0_MASK,Mask bit for s0 protocol fault source" "0,1"
newline
bitfld.long 0x00 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_MASK,Mask bit for mst_sdr_rd_abort protocol fault source" "0,1"
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_MASK,Mask bit for mst_ddr_fail protocol fault source" "0,1"
newline
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_M2_MASK,Mask bit for m2 protocol fault source" "0,1"
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_M1_MASK,Mask bit for m1 protocol fault source" "0,1"
newline
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_M0_MASK,Mask bit for m0 protocol fault source" "0,1"
line.long 0x04 "I3C_ASF_PROTOCOL_FAULT_STATUS,Return to"
bitfld.long 0x04 12. "ASF_PROTOCOL_FAULT_SLV_SDR_RD_ABORT_STATUS,Status bit for slv_sdr_rd_abort protocol fault" "0,1"
bitfld.long 0x04 11. "ASF_PROTOCOL_FAULT_SLV_DDR_FAIL_STATUS,Status bit for slv_ddr_fail protocol fault" "0,1"
newline
bitfld.long 0x04 10. "ASF_PROTOCOL_FAULT_S5_STATUS,Status bit for s5 protocol fault" "0,1"
bitfld.long 0x04 9. "ASF_PROTOCOL_FAULT_S4_STATUS,Status bit for s4 protocol fault" "0,1"
newline
bitfld.long 0x04 8. "ASF_PROTOCOL_FAULT_S3_STATUS,Status bit for s3 protocol fault" "0,1"
bitfld.long 0x04 7. "ASF_PROTOCOL_FAULT_S2_STATUS,Status bit for s2 protocol fault" "0,1"
newline
bitfld.long 0x04 6. "ASF_PROTOCOL_FAULT_S1_STATUS,Status bit for s1 protocol fault" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_FAULT_S0_STATUS,Status bit for s0 protocol fault" "0,1"
newline
bitfld.long 0x04 4. "ASF_PROTOCOL_FAULT_MST_SDR_RD_ABORT_STATUS,Status bit for mst_sdr_rd_abort protocol fault" "0,1"
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_MST_DDR_FAIL_STATUS,Status bit for mst_ddr_fail protocol fault" "0,1"
newline
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_M2_STATUS,Status bit for m2 protocol fault" "0,1"
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_M1_STATUS,Status bit for m1 protocol fault" "0,1"
newline
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_M0_STATUS,Status bit for m0 protocol fault" "0,1"
tree.end
tree.end
tree "INTR0_INTR_ROUTER_CFG"
tree "MCU_NAVSS0_INTR0_CFG"
base ad:0x28540000
rgroup.long 0x00++0x07
line.long 0x00 "INTR_ROUTER_PID,Identification register"
bitfld.long 0x00 30.--31. "SCHEME,PID scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function"
bitfld.long 0x00 11.--15. "RTL,RTL version" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,MCU_NAVSS0,NAVSS0,?..."
bitfld.long 0x00 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom id" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INTR_ROUTER_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4); where y = 0h to 1FFh for NAVSS0 Offset = 4h + (y * 4); where y = 0h to 3Fh for MCU_NAVSS0"
bitfld.long 0x04 16. "INT_ENABLE,Interrupt output enable for interrupt y" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt y"
tree.end
tree "NAVSS0_INTR0_INTR_ROUTER_CFG"
base ad:0x310E0000
rgroup.long 0x00++0x07
line.long 0x00 "INTR_ROUTER_PID,Identification register"
bitfld.long 0x00 30.--31. "SCHEME,PID scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function"
bitfld.long 0x00 11.--15. "RTL,RTL version" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,MCU_NAVSS0,NAVSS0,?..."
bitfld.long 0x00 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom id" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INTR_ROUTER_MUXCNTL_y,Interrupt mux control register Offset = 4h + (y * 4); where y = 0h to 1FFh for NAVSS0 Offset = 4h + (y * 4); where y = 0h to 3Fh for MCU_NAVSS0"
bitfld.long 0x04 16. "INT_ENABLE,Interrupt output enable for interrupt y" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt y"
tree.end
tree.end
tree "Mailbox"
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list ad:0x31F80000 ad:0x31F81000 ad:0x31F82000 ad:0x31F83000 ad:0x31F84000 ad:0x31F85000 ad:0x31F86000 ad:0x31F87000 ad:0x31F88000 ad:0x31F89000 ad:0x31F8A000 ad:0x31F8B000 )
tree "MAILBOX0_REGS$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "MAILBOX_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3"
bitfld.long 0x00 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module family"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Special version number" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3"
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system"
bitfld.long 0x00 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware" "0,1"
group.long 0x40++0x03
line.long 0x00 "MAILBOX_MESSAGE_y,The message register stores the next to-be-read message of the mailbox"
rgroup.long 0x80++0x03
line.long 0x00 "MAILBOX_FIFO_STATUS_y,The FIFO status register has the status of the Mailbox y FIFO Offset = 80h + (y * 4h); where y = 0h to Fh"
bitfld.long 0x00 0. "FULL,Full flag for Mailbox y" "0,1"
rgroup.long 0xC0++0x03
line.long 0x00 "MAILBOX_MSG_STATUS_y,The message status register has the status of the messages in Mailbox y Offset = C0h + (y * 4h); where y = 0h to Fh"
bitfld.long 0x00 0.--2. "NUM_MESSAGES,Number of messages in Mailbox y" "0,1,2,3,4,5,6,7"
group.long 0x100++0x0F
line.long 0x00 "MAILBOX_IRQ_STATUS_RAW_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user"
bitfld.long 0x00 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x00 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x00 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x00 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
bitfld.long 0x00 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
newline
bitfld.long 0x00 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x00 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x00 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
bitfld.long 0x00 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x00 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
newline
bitfld.long 0x00 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x00 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
bitfld.long 0x00 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x00 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x00 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
newline
bitfld.long 0x00 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
bitfld.long 0x00 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x00 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x00 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x00 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x00 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x00 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x00 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x00 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
bitfld.long 0x00 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
newline
bitfld.long 0x00 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x00 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x00 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
bitfld.long 0x00 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x00 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
newline
bitfld.long 0x00 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x00 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x04 "MAILBOX_IRQ_STATUS_CLR_j,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information"
bitfld.long 0x04 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x08 "MAILBOX_IRQ_ENABLE_SET_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j"
bitfld.long 0x08 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt" "0,1"
line.long 0x0C "MAILBOX_IRQ_ENABLE_CLR_j,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user j"
bitfld.long 0x0C 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt" "0,1"
group.long 0x140++0x03
line.long 0x00 "MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance"
bitfld.long 0x00 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x00 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x00 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x00 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
tree.end
repeat.end
tree.end
tree "MCAN_Core"
repeat 14. (increment 0 1) (increment ad:0x2701000 0x10000)
tree "MCAN$1_CFG"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded"
line.long 0x04 "MCAN_ENDN,Endian Register Constant 8765 4321h"
group.long 0x0C++0x23
line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "Transmitter Delay Compensation disabled,Transmitter Delay Compensation enabled"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_TEST,Test Register Test mode selection"
bitfld.long 0x04 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin" "The CAN bus is dominant (MCAN RX = 0h),The CAN bus is recessive (MCAN RX = 1h)"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "Reset value the MCAN TX pin controlled by the..,Sample Point can be monitored at the MCAN TX pin,Dominant ('0') level at the MCAN TX pin,Recessive ('1') at the MCAN TX pin"
newline
bitfld.long 0x04 4. "LBCK,Loopback Mode" "Reset value Loopback Mode is disabled,Loopback Mode is enabled (see Test Modes)"
line.long 0x08 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter"
line.long 0x0C "MCAN_CCCR,CC Control Register Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling)" "Transmit pause disabled,Transmit pause enabled"
newline
bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "Edge filtering disabled,Two consecutive dominant t"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "Protocol exception handling enabled,Protocol exception handling disabled"
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bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "Bit rate switching for transmissions disabled,Bit rate switching for transmissions enabled"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "FD operation disabled,FD operation enabled"
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bitfld.long 0x0C 7. "TEST,Test Mode Enable" "Normal operation,Test Mode"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "Automatic retransmission of messages not..,Automatic retransmission disabled"
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bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "Bus Monitoring Mode is disabled,Bus Monitoring Mode is enabled"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "No clock stop is requested,Clock stop requested"
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bitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "No clock stop acknowledged,The MCAN module may be set in power down by.."
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "Normal CAN operation,Restricted Operation Mode active"
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bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "The Host CPU has no write access to the..,The Host CPU has write access to the protected.."
bitfld.long 0x0C 0. "INIT,Initialization" "Normal Operation,Initialization is started"
line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh)"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta"
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh)"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh)"
line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "Timestamp counter value always 0h,Timestamp counter value incremented according to,External timestamp counter value used,Same as 0h"
line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)"
line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to" "Continuous operation,Timeout controlled by Tx Event FIFO,Timeout controlled by Rx FIFO 0,Timeout controlled by Rx FIFO 1"
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bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "Timeout Counter disabled,Timeout Counter enabled"
line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of"
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented"
bitfld.long 0x00 15. "RP,Receive Error Passive" "The Receive Error Counter is below the error..,The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255"
line.long 0x04 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "No protocol exception event occurred since last..,Protocol exception event occurred"
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bitfld.long 0x04 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering" "Since this bit was reset by the Host CPU no CAN..,Message in CAN FD format with FDF flag set has.."
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its BRS flag set"
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bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its ESI flag set"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7. "BO,Bus_Off Status" "The MCAN module is not Bus_Off,The MCAN module is in Bus_Off state"
bitfld.long 0x04 6. "EW,Warning Status" "Both error counters are below the Error_Warning..,At least one of error counter has reached the.."
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bitfld.long 0x04 5. "EP,Error Passive" "The MCAN module is in the Error_Active state,The MCAN module is in the Error_Passive state"
bitfld.long 0x04 3.--4. "ACT,Activity Monitors the module's CAN communication state" "Synchronizing - node is synchronizing on CAN..,Idle - node is neither receiver nor transmitter,Receiver - node is operating as receiver,Transmitter - node is operating as transmitter"
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bitfld.long 0x04 0.--2. "LEC,Last Error Code" "No Error,Stuff Error,Form Error,AckError,Bit1Error,Bit0Error,CRCError,NoChange"
line.long 0x08 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment"
group.long 0x50++0x0F
line.long 0x00 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive)"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "No access to reserved address occurred,Access to reserved address occurred"
bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "No protocol error in data phase,Protocol error in data phase detected ("
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bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "No protocol error in arbitration phase,Protocol error in arbitration phase detected ("
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "No Message RAM Watchdog event occurred,Message RAM Watchdog event due to missing READY"
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bitfld.long 0x00 25. "BO,Bus_Off Status" "Bus_Off status unchanged,Bus_Off status changed"
bitfld.long 0x00 24. "EW,Warning Status" "Error_Warning status unchanged,Error_Warning status changed"
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bitfld.long 0x00 23. "EP,Error Passive" "Error_Passive status unchanged,Error_Passive status changed"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "CAN Error Logging Counter did not overflow,Overflow of CAN Error Logging Counter occurred"
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bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "No bit error detected when reading from Message..,Bit error detected uncorrected (example: parity.."
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "No Rx Buffer updated,At least one received message stored into an Rx.."
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bitfld.long 0x00 18. "TOO,Timeout Occurred" "No timeout,Timeout reached"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "No Message RAM access failure occurred,Message RAM access failure occurred"
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bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "No timestamp counter wrap-around,Timestamp counter wrapped around"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.."
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bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "Tx Event FIFO fill level below watermark,Tx Event FIFO fill level reached watermark"
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bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "Tx Event FIFO unchanged,Tx Handler wrote Tx Event FIFO element"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "Tx FIFO non-empty,Tx FIFO empty"
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bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "No transmission cancellation finished,Transmission cancellation finished"
bitfld.long 0x00 9. "TC,Transmission Completed" "No transmission completed,Transmission completed"
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bitfld.long 0x00 8. "HPM,High Priority Message" "No high priority message received,High priority message received"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "Rx FIFO 1 fill level below watermark,Rx FIFO 1 fill level reached watermark"
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bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "No new message written to Rx FIFO 1,New message written to Rx FIFO 1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "Rx FIFO 0 fill level below watermark,Rx FIFO 0 fill level reached watermark"
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bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "No new message written to Rx FIFO 0,New message written to Rx FIFO 0"
line.long 0x04 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line"
bitfld.long 0x04 29. "ARAE,Access to Reserved Address Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 8. "HPME,High Priority Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
line.long 0x08 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines"
bitfld.long 0x08 29. "ARAL,Access to Reserved Address Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 8. "HPML,High Priority Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
line.long 0x0C "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "Interrupt line INT1 disabled,Interrupt line INT1 enabled"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "Interrupt line INT0 disabled,Interrupt line INT0 enabled"
group.long 0x80++0x0B
line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject"
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bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "Filter remote frames with 11-bit standard IDs,Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "Filter remote frames with 29-bit extended IDs,Reject all remote frames with 29-bit extended IDs"
line.long 0x04 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see"
line.long 0x08 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see"
group.long 0x90++0x57
line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame"
line.long 0x04 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List Indicates the filter list of the matching filter element" "Standard Filter List,Extended Filter List"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index Index of matching filter element"
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bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "No FIFO selected,FIFO message lost,Message stored in FIFO 0,Message stored in FIFO 1"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x08 31. "ND31,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 30. "ND30,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 29. "ND29,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 28. "ND28,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 27. "ND27,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 26. "ND26,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 25. "ND25,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 24. "ND24,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 23. "ND23,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 22. "ND22,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 21. "ND21,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 20. "ND20,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 19. "ND19,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 18. "ND18,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 17. "ND17,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 16. "ND16,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 15. "ND15,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 14. "ND14,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 13. "ND13,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 12. "ND12,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 11. "ND11,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 10. "ND10,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 9. "ND9,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 8. "ND8,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 7. "ND7,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 6. "ND6,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 5. "ND5,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 4. "ND4,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 3. "ND3,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 2. "ND2,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x08 1. "ND1,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 0. "ND0,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
line.long 0x0C "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63"
bitfld.long 0x0C 31. "ND63,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 30. "ND62,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
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bitfld.long 0x0C 29. "ND61,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 28. "ND60,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 27. "ND59,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 26. "ND58,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 25. "ND57,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 24. "ND56,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 23. "ND55,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 22. "ND54,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 21. "ND53,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 20. "ND52,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 19. "ND51,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 18. "ND50,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 17. "ND49,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 16. "ND48,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 15. "ND47,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 14. "ND46,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 13. "ND45,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 12. "ND44,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 11. "ND43,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 10. "ND42,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 9. "ND41,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 8. "ND40,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 7. "ND39,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 6. "ND38,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 5. "ND37,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 4. "ND36,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 3. "ND35,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 2. "ND34,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 1. "ND33,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 0. "ND32,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
line.long 0x10 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "FIFO 0 blocking mode,FIFO 0 overwrite mode"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
newline
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x10 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see"
line.long 0x14 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.."
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full"
newline
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64"
line.long 0x18 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see )"
line.long 0x20 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x20 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "FIFO 1 blocking mode,FIFO 1 overwrite mode"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
newline
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x20 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see"
line.long 0x24 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x24 30.--31. "DMS,Debug Message Status" "Idle state wait for reception of debug messages..,Debug message A received,Debug messages A B received,Debug messages A B C received DMA request is set"
bitfld.long 0x24 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.."
newline
bitfld.long 0x24 24. "F1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64"
line.long 0x28 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
line.long 0x30 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "Tx FIFO operation,Tx Queue operation"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.."
line.long 0x34 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "Tx FIFO/Queue not full,Tx FIFO/Queue full"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
line.long 0x3C "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request"
bitfld.long 0x3C 31. "TRP31,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 30. "TRP30,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 29. "TRP29,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 28. "TRP28,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 27. "TRP27,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 26. "TRP26,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 25. "TRP25,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 24. "TRP24,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 23. "TRP23,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 22. "TRP22,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 21. "TRP21,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 20. "TRP20,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 19. "TRP19,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 18. "TRP18,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 17. "TRP17,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 16. "TRP16,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 15. "TRP15,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 14. "TRP14,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 13. "TRP13,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 12. "TRP12,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 11. "TRP11,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 10. "TRP10,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 9. "TRP9,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 8. "TRP8,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 7. "TRP7,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 6. "TRP6,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 5. "TRP5,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 4. "TRP4,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 3. "TRP3,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 2. "TRP2,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 1. "TRP1,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 0. "TRP0,Transmission Request Pending" "No transmission request pending,Transmission request pending"
line.long 0x40 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests"
bitfld.long 0x40 31. "AR31,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 30. "AR30,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 29. "AR29,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 28. "AR28,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 27. "AR27,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 26. "AR26,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 25. "AR25,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 24. "AR24,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 23. "AR23,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 22. "AR22,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 21. "AR21,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 20. "AR20,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 19. "AR19,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 18. "AR18,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 17. "AR17,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 16. "AR16,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 15. "AR15,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 14. "AR14,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 13. "AR13,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 12. "AR12,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 11. "AR11,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 10. "AR10,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 9. "AR9,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 8. "AR8,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 7. "AR7,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 6. "AR6,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 5. "AR5,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 4. "AR4,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 3. "AR3,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 2. "AR2,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 1. "AR1,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 0. "AR0,Add Request" "No transmission request added,Transmission requested added"
line.long 0x44 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions"
bitfld.long 0x44 31. "CR31,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 30. "CR30,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 29. "CR29,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 28. "CR28,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 27. "CR27,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 26. "CR26,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 25. "CR25,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 24. "CR24,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 23. "CR23,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 22. "CR22,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 21. "CR21,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 20. "CR20,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 19. "CR19,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 18. "CR18,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 17. "CR17,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 16. "CR16,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 15. "CR15,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 14. "CR14,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 13. "CR13,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 12. "CR12,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 11. "CR11,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 10. "CR10,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 9. "CR9,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 8. "CR8,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 7. "CR7,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 6. "CR6,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 5. "CR5,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 4. "CR4,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 3. "CR3,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 2. "CR2,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 1. "CR1,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 0. "CR0,Cancellation Request" "No cancellation pending,Cancellation pending"
line.long 0x48 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared"
bitfld.long 0x48 31. "TO31,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 30. "TO30,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 29. "TO29,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 28. "TO28,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 27. "TO27,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 26. "TO26,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 25. "TO25,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 24. "TO24,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 23. "TO23,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 22. "TO22,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 21. "TO21,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 20. "TO20,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 19. "TO19,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 18. "TO18,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 17. "TO17,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 16. "TO16,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 15. "TO15,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 14. "TO14,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 13. "TO13,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 12. "TO12,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 11. "TO11,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 10. "TO10,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 9. "TO9,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 8. "TO8,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 7. "TO7,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 6. "TO6,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 5. "TO5,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 4. "TO4,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 3. "TO3,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 2. "TO2,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 1. "TO1,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 0. "TO0,Transmission Occurred" "No transmission occurred,Transmission occurred"
line.long 0x4C "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request"
bitfld.long 0x4C 31. "CF31,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 30. "CF30,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 29. "CF29,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 28. "CF28,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 27. "CF27,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 26. "CF26,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 25. "CF25,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 24. "CF24,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 23. "CF23,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 22. "CF22,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 21. "CF21,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 20. "CF20,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 19. "CF19,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 18. "CF18,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 17. "CF17,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 16. "CF16,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 15. "CF15,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 14. "CF14,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 13. "CF13,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 12. "CF12,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 11. "CF11,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 10. "CF10,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 9. "CF9,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 8. "CF8,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 7. "CF7,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 6. "CF6,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 5. "CF5,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 4. "CF4,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 3. "CF3,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 2. "CF2,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 1. "CF1,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 0. "CF0,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
line.long 0x50 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x50 31. "TIE31,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 30. "TIE30,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 29. "TIE29,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 28. "TIE28,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 27. "TIE27,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 26. "TIE26,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 25. "TIE25,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 24. "TIE24,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 23. "TIE23,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 22. "TIE22,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 21. "TIE21,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 20. "TIE20,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 19. "TIE19,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 18. "TIE18,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 17. "TIE17,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 16. "TIE16,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 15. "TIE15,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 14. "TIE14,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 13. "TIE13,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 12. "TIE12,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 11. "TIE11,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 10. "TIE10,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 9. "TIE9,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 8. "TIE8,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 7. "TIE7,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 6. "TIE6,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 5. "TIE5,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 4. "TIE4,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 3. "TIE3,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 2. "TIE2,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 1. "TIE1,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 0. "TIE0,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
line.long 0x54 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x54 31. "CFIE31,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 30. "CFIE30,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 29. "CFIE29,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 28. "CFIE28,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 27. "CFIE27,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 26. "CFIE26,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 25. "CFIE25,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 24. "CFIE24,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 23. "CFIE23,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 22. "CFIE22,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 21. "CFIE21,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 20. "CFIE20,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 19. "CFIE19,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 18. "CFIE18,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 17. "CFIE17,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 16. "CFIE16,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 15. "CFIE15,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 14. "CFIE14,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 13. "CFIE13,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 12. "CFIE12,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 11. "CFIE11,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 10. "CFIE10,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 9. "CFIE9,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 8. "CFIE8,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 7. "CFIE7,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 6. "CFIE6,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 5. "CFIE5,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 4. "CFIE4,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 3. "CFIE3,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 2. "CFIE2,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 1. "CFIE1,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 0. "CFIE0,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
group.long 0xF0++0x0B
line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see"
line.long 0x04 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,This bit is a copy of interrupt flag" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.."
bitfld.long 0x04 24. "EFF,Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full"
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bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
repeat.end
tree "MCU_MCAN0_CFG"
base ad:0x40528000
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded"
line.long 0x04 "MCAN_ENDN,Endian Register Constant 8765 4321h"
group.long 0x0C++0x23
line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "Transmitter Delay Compensation disabled,Transmitter Delay Compensation enabled"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_TEST,Test Register Test mode selection"
bitfld.long 0x04 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin" "The CAN bus is dominant (MCAN RX = 0h),The CAN bus is recessive (MCAN RX = 1h)"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "Reset value the MCAN TX pin controlled by the..,Sample Point can be monitored at the MCAN TX pin,Dominant ('0') level at the MCAN TX pin,Recessive ('1') at the MCAN TX pin"
newline
bitfld.long 0x04 4. "LBCK,Loopback Mode" "Reset value Loopback Mode is disabled,Loopback Mode is enabled (see Test Modes)"
line.long 0x08 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter"
line.long 0x0C "MCAN_CCCR,CC Control Register Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling)" "Transmit pause disabled,Transmit pause enabled"
newline
bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "Edge filtering disabled,Two consecutive dominant t"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "Protocol exception handling enabled,Protocol exception handling disabled"
newline
bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "Bit rate switching for transmissions disabled,Bit rate switching for transmissions enabled"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "FD operation disabled,FD operation enabled"
newline
bitfld.long 0x0C 7. "TEST,Test Mode Enable" "Normal operation,Test Mode"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "Automatic retransmission of messages not..,Automatic retransmission disabled"
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bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "Bus Monitoring Mode is disabled,Bus Monitoring Mode is enabled"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "No clock stop is requested,Clock stop requested"
newline
bitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "No clock stop acknowledged,The MCAN module may be set in power down by.."
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "Normal CAN operation,Restricted Operation Mode active"
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bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "The Host CPU has no write access to the..,The Host CPU has write access to the protected.."
bitfld.long 0x0C 0. "INIT,Initialization" "Normal Operation,Initialization is started"
line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh)"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta"
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh)"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh)"
line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "Timestamp counter value always 0h,Timestamp counter value incremented according to,External timestamp counter value used,Same as 0h"
line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)"
line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to" "Continuous operation,Timeout controlled by Tx Event FIFO,Timeout controlled by Rx FIFO 0,Timeout controlled by Rx FIFO 1"
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bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "Timeout Counter disabled,Timeout Counter enabled"
line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of"
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented"
bitfld.long 0x00 15. "RP,Receive Error Passive" "The Receive Error Counter is below the error..,The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255"
line.long 0x04 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "No protocol exception event occurred since last..,Protocol exception event occurred"
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bitfld.long 0x04 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering" "Since this bit was reset by the Host CPU no CAN..,Message in CAN FD format with FDF flag set has.."
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its BRS flag set"
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bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its ESI flag set"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7. "BO,Bus_Off Status" "The MCAN module is not Bus_Off,The MCAN module is in Bus_Off state"
bitfld.long 0x04 6. "EW,Warning Status" "Both error counters are below the Error_Warning..,At least one of error counter has reached the.."
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bitfld.long 0x04 5. "EP,Error Passive" "The MCAN module is in the Error_Active state,The MCAN module is in the Error_Passive state"
bitfld.long 0x04 3.--4. "ACT,Activity Monitors the module's CAN communication state" "Synchronizing - node is synchronizing on CAN..,Idle - node is neither receiver nor transmitter,Receiver - node is operating as receiver,Transmitter - node is operating as transmitter"
newline
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "No Error,Stuff Error,Form Error,AckError,Bit1Error,Bit0Error,CRCError,NoChange"
line.long 0x08 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment"
group.long 0x50++0x0F
line.long 0x00 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive)"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "No access to reserved address occurred,Access to reserved address occurred"
bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "No protocol error in data phase,Protocol error in data phase detected ("
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bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "No protocol error in arbitration phase,Protocol error in arbitration phase detected ("
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "No Message RAM Watchdog event occurred,Message RAM Watchdog event due to missing READY"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "Bus_Off status unchanged,Bus_Off status changed"
bitfld.long 0x00 24. "EW,Warning Status" "Error_Warning status unchanged,Error_Warning status changed"
newline
bitfld.long 0x00 23. "EP,Error Passive" "Error_Passive status unchanged,Error_Passive status changed"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "CAN Error Logging Counter did not overflow,Overflow of CAN Error Logging Counter occurred"
newline
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "No bit error detected when reading from Message..,Bit error detected uncorrected (example: parity.."
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "No Rx Buffer updated,At least one received message stored into an Rx.."
newline
bitfld.long 0x00 18. "TOO,Timeout Occurred" "No timeout,Timeout reached"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "No Message RAM access failure occurred,Message RAM access failure occurred"
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bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "No timestamp counter wrap-around,Timestamp counter wrapped around"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.."
newline
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "Tx Event FIFO fill level below watermark,Tx Event FIFO fill level reached watermark"
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bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "Tx Event FIFO unchanged,Tx Handler wrote Tx Event FIFO element"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "Tx FIFO non-empty,Tx FIFO empty"
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bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "No transmission cancellation finished,Transmission cancellation finished"
bitfld.long 0x00 9. "TC,Transmission Completed" "No transmission completed,Transmission completed"
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bitfld.long 0x00 8. "HPM,High Priority Message" "No high priority message received,High priority message received"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "Rx FIFO 1 fill level below watermark,Rx FIFO 1 fill level reached watermark"
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bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "No new message written to Rx FIFO 1,New message written to Rx FIFO 1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.."
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bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "Rx FIFO 0 fill level below watermark,Rx FIFO 0 fill level reached watermark"
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bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "No new message written to Rx FIFO 0,New message written to Rx FIFO 0"
line.long 0x04 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line"
bitfld.long 0x04 29. "ARAE,Access to Reserved Address Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 8. "HPME,High Priority Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
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bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
line.long 0x08 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines"
bitfld.long 0x08 29. "ARAL,Access to Reserved Address Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
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bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 8. "HPML,High Priority Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
line.long 0x0C "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "Interrupt line INT1 disabled,Interrupt line INT1 enabled"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "Interrupt line INT0 disabled,Interrupt line INT0 enabled"
group.long 0x80++0x0B
line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject"
newline
bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "Filter remote frames with 11-bit standard IDs,Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "Filter remote frames with 29-bit extended IDs,Reject all remote frames with 29-bit extended IDs"
line.long 0x04 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see"
line.long 0x08 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see"
group.long 0x90++0x57
line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame"
line.long 0x04 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List Indicates the filter list of the matching filter element" "Standard Filter List,Extended Filter List"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index Index of matching filter element"
newline
bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "No FIFO selected,FIFO message lost,Message stored in FIFO 0,Message stored in FIFO 1"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x08 31. "ND31,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 30. "ND30,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 29. "ND29,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 28. "ND28,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 27. "ND27,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 26. "ND26,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 25. "ND25,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 24. "ND24,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 23. "ND23,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 22. "ND22,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 21. "ND21,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 20. "ND20,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 19. "ND19,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 18. "ND18,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 17. "ND17,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 16. "ND16,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 15. "ND15,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 14. "ND14,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 13. "ND13,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 12. "ND12,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 11. "ND11,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 10. "ND10,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 9. "ND9,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 8. "ND8,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 7. "ND7,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 6. "ND6,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 5. "ND5,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 4. "ND4,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 3. "ND3,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 2. "ND2,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 1. "ND1,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 0. "ND0,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
line.long 0x0C "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63"
bitfld.long 0x0C 31. "ND63,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 30. "ND62,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 29. "ND61,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 28. "ND60,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 27. "ND59,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 26. "ND58,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 25. "ND57,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 24. "ND56,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 23. "ND55,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 22. "ND54,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 21. "ND53,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 20. "ND52,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 19. "ND51,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 18. "ND50,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 17. "ND49,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 16. "ND48,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 15. "ND47,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 14. "ND46,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 13. "ND45,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 12. "ND44,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 11. "ND43,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 10. "ND42,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 9. "ND41,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 8. "ND40,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 7. "ND39,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 6. "ND38,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 5. "ND37,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 4. "ND36,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 3. "ND35,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 2. "ND34,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 1. "ND33,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 0. "ND32,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
line.long 0x10 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "FIFO 0 blocking mode,FIFO 0 overwrite mode"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
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hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x10 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see"
line.long 0x14 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.."
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full"
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bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64"
line.long 0x18 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see )"
line.long 0x20 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x20 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "FIFO 1 blocking mode,FIFO 1 overwrite mode"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
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hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x20 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see"
line.long 0x24 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x24 30.--31. "DMS,Debug Message Status" "Idle state wait for reception of debug messages..,Debug message A received,Debug messages A B received,Debug messages A B C received DMA request is set"
bitfld.long 0x24 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.."
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bitfld.long 0x24 24. "F1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64"
line.long 0x28 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
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bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
line.long 0x30 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "Tx FIFO operation,Tx Queue operation"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.."
line.long 0x34 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "Tx FIFO/Queue not full,Tx FIFO/Queue full"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
line.long 0x3C "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request"
bitfld.long 0x3C 31. "TRP31,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 30. "TRP30,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 29. "TRP29,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 28. "TRP28,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 27. "TRP27,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 26. "TRP26,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 25. "TRP25,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 24. "TRP24,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 23. "TRP23,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 22. "TRP22,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 21. "TRP21,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 20. "TRP20,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 19. "TRP19,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 18. "TRP18,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 17. "TRP17,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 16. "TRP16,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 15. "TRP15,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 14. "TRP14,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 13. "TRP13,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 12. "TRP12,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 11. "TRP11,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 10. "TRP10,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 9. "TRP9,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 8. "TRP8,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 7. "TRP7,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 6. "TRP6,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 5. "TRP5,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 4. "TRP4,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 3. "TRP3,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 2. "TRP2,Transmission Request Pending" "No transmission request pending,Transmission request pending"
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bitfld.long 0x3C 1. "TRP1,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 0. "TRP0,Transmission Request Pending" "No transmission request pending,Transmission request pending"
line.long 0x40 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests"
bitfld.long 0x40 31. "AR31,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 30. "AR30,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 29. "AR29,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 28. "AR28,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 27. "AR27,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 26. "AR26,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 25. "AR25,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 24. "AR24,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 23. "AR23,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 22. "AR22,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 21. "AR21,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 20. "AR20,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 19. "AR19,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 18. "AR18,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 17. "AR17,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 16. "AR16,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 15. "AR15,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 14. "AR14,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 13. "AR13,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 12. "AR12,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 11. "AR11,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 10. "AR10,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 9. "AR9,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 8. "AR8,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 7. "AR7,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 6. "AR6,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 5. "AR5,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 4. "AR4,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 3. "AR3,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 2. "AR2,Add Request" "No transmission request added,Transmission requested added"
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bitfld.long 0x40 1. "AR1,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 0. "AR0,Add Request" "No transmission request added,Transmission requested added"
line.long 0x44 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions"
bitfld.long 0x44 31. "CR31,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 30. "CR30,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 29. "CR29,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 28. "CR28,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 27. "CR27,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 26. "CR26,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 25. "CR25,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 24. "CR24,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 23. "CR23,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 22. "CR22,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 21. "CR21,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 20. "CR20,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 19. "CR19,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 18. "CR18,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 17. "CR17,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 16. "CR16,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 15. "CR15,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 14. "CR14,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 13. "CR13,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 12. "CR12,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 11. "CR11,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 10. "CR10,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 9. "CR9,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 8. "CR8,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 7. "CR7,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 6. "CR6,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 5. "CR5,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 4. "CR4,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 3. "CR3,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 2. "CR2,Cancellation Request" "No cancellation pending,Cancellation pending"
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bitfld.long 0x44 1. "CR1,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 0. "CR0,Cancellation Request" "No cancellation pending,Cancellation pending"
line.long 0x48 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared"
bitfld.long 0x48 31. "TO31,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 30. "TO30,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 29. "TO29,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 28. "TO28,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 27. "TO27,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 26. "TO26,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 25. "TO25,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 24. "TO24,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 23. "TO23,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 22. "TO22,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 21. "TO21,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 20. "TO20,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 19. "TO19,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 18. "TO18,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 17. "TO17,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 16. "TO16,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 15. "TO15,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 14. "TO14,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 13. "TO13,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 12. "TO12,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 11. "TO11,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 10. "TO10,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 9. "TO9,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 8. "TO8,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 7. "TO7,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 6. "TO6,Transmission Occurred" "No transmission occurred,Transmission occurred"
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bitfld.long 0x48 5. "TO5,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 4. "TO4,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 3. "TO3,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 2. "TO2,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 1. "TO1,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 0. "TO0,Transmission Occurred" "No transmission occurred,Transmission occurred"
line.long 0x4C "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request"
bitfld.long 0x4C 31. "CF31,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 30. "CF30,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 29. "CF29,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 28. "CF28,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 27. "CF27,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 26. "CF26,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 25. "CF25,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 24. "CF24,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 23. "CF23,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 22. "CF22,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 21. "CF21,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 20. "CF20,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 19. "CF19,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 18. "CF18,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 17. "CF17,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 16. "CF16,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 15. "CF15,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 14. "CF14,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 13. "CF13,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 12. "CF12,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 11. "CF11,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 10. "CF10,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 9. "CF9,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 8. "CF8,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 7. "CF7,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 6. "CF6,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 5. "CF5,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 4. "CF4,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 3. "CF3,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 2. "CF2,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
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bitfld.long 0x4C 1. "CF1,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 0. "CF0,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
line.long 0x50 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x50 31. "TIE31,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 30. "TIE30,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 29. "TIE29,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 28. "TIE28,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 27. "TIE27,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 26. "TIE26,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 25. "TIE25,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 24. "TIE24,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 23. "TIE23,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 22. "TIE22,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 21. "TIE21,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 20. "TIE20,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 19. "TIE19,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 18. "TIE18,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 17. "TIE17,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 16. "TIE16,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 15. "TIE15,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 14. "TIE14,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 13. "TIE13,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 12. "TIE12,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 11. "TIE11,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 10. "TIE10,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 9. "TIE9,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 8. "TIE8,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 7. "TIE7,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 6. "TIE6,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 5. "TIE5,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 4. "TIE4,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 3. "TIE3,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 2. "TIE2,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
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bitfld.long 0x50 1. "TIE1,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 0. "TIE0,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
line.long 0x54 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x54 31. "CFIE31,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 30. "CFIE30,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 29. "CFIE29,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 28. "CFIE28,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 27. "CFIE27,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 26. "CFIE26,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 25. "CFIE25,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 24. "CFIE24,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 23. "CFIE23,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 22. "CFIE22,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 21. "CFIE21,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 20. "CFIE20,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 19. "CFIE19,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 18. "CFIE18,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 17. "CFIE17,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 16. "CFIE16,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 15. "CFIE15,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 14. "CFIE14,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 13. "CFIE13,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 12. "CFIE12,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 11. "CFIE11,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 10. "CFIE10,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 9. "CFIE9,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 8. "CFIE8,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 7. "CFIE7,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 6. "CFIE6,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 5. "CFIE5,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 4. "CFIE4,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 3. "CFIE3,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 2. "CFIE2,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
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bitfld.long 0x54 1. "CFIE1,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 0. "CFIE0,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
group.long 0xF0++0x0B
line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see"
line.long 0x04 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,This bit is a copy of interrupt flag" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.."
bitfld.long 0x04 24. "EFF,Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full"
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bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MCU_MCAN1_CFG"
base ad:0x40568000
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded"
line.long 0x04 "MCAN_ENDN,Endian Register Constant 8765 4321h"
group.long 0x0C++0x23
line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "Transmitter Delay Compensation disabled,Transmitter Delay Compensation enabled"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0h-1Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0h-Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0h-Fh)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_TEST,Test Register Test mode selection"
bitfld.long 0x04 7. "RX,Receive Pin Monitors the actual value of the MCAN RX pin" "The CAN bus is dominant (MCAN RX = 0h),The CAN bus is recessive (MCAN RX = 1h)"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "Reset value the MCAN TX pin controlled by the..,Sample Point can be monitored at the MCAN TX pin,Dominant ('0') level at the MCAN TX pin,Recessive ('1') at the MCAN TX pin"
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bitfld.long 0x04 4. "LBCK,Loopback Mode" "Reset value Loopback Mode is disabled,Loopback Mode is enabled (see Test Modes)"
line.long 0x08 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter"
line.long 0x0C "MCAN_CCCR,CC Control Register Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling)" "Transmit pause disabled,Transmit pause enabled"
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bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "Edge filtering disabled,Two consecutive dominant t"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "Protocol exception handling enabled,Protocol exception handling disabled"
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bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "Bit rate switching for transmissions disabled,Bit rate switching for transmissions enabled"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "FD operation disabled,FD operation enabled"
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bitfld.long 0x0C 7. "TEST,Test Mode Enable" "Normal operation,Test Mode"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "Automatic retransmission of messages not..,Automatic retransmission disabled"
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bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "Bus Monitoring Mode is disabled,Bus Monitoring Mode is enabled"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "No clock stop is requested,Clock stop requested"
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bitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "No clock stop acknowledged,The MCAN module may be set in power down by.."
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "Normal CAN operation,Restricted Operation Mode active"
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bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "The Host CPU has no write access to the..,The Host CPU has write access to the protected.."
bitfld.long 0x0C 0. "INIT,Initialization" "Normal Operation,Initialization is started"
line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0h-7Fh)"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta"
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hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (1h-FFh)"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0h-7Fh)"
line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "Timestamp counter value always 0h,Timestamp counter value incremented according to,External timestamp counter value used,Same as 0h"
line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)"
line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to" "Continuous operation,Timeout controlled by Tx Event FIFO,Timeout controlled by Rx FIFO 0,Timeout controlled by Rx FIFO 1"
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bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "Timeout Counter disabled,Timeout Counter enabled"
line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of"
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented"
bitfld.long 0x00 15. "RP,Receive Error Passive" "The Receive Error Counter is below the error..,The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255"
line.long 0x04 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "No protocol exception event occurred since last..,Protocol exception event occurred"
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bitfld.long 0x04 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering" "Since this bit was reset by the Host CPU no CAN..,Message in CAN FD format with FDF flag set has.."
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its BRS flag set"
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bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its ESI flag set"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7. "BO,Bus_Off Status" "The MCAN module is not Bus_Off,The MCAN module is in Bus_Off state"
bitfld.long 0x04 6. "EW,Warning Status" "Both error counters are below the Error_Warning..,At least one of error counter has reached the.."
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bitfld.long 0x04 5. "EP,Error Passive" "The MCAN module is in the Error_Active state,The MCAN module is in the Error_Passive state"
bitfld.long 0x04 3.--4. "ACT,Activity Monitors the module's CAN communication state" "Synchronizing - node is synchronizing on CAN..,Idle - node is neither receiver nor transmitter,Receiver - node is operating as receiver,Transmitter - node is operating as transmitter"
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bitfld.long 0x04 0.--2. "LEC,Last Error Code" "No Error,Stuff Error,Form Error,AckError,Bit1Error,Bit0Error,CRCError,NoChange"
line.long 0x08 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment"
group.long 0x50++0x0F
line.long 0x00 "MCAN_IR,Interrupt Register The flags are set when one of the listed conditions is detected (edge-sensitive)"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "No access to reserved address occurred,Access to reserved address occurred"
bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "No protocol error in data phase,Protocol error in data phase detected ("
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bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "No protocol error in arbitration phase,Protocol error in arbitration phase detected ("
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "No Message RAM Watchdog event occurred,Message RAM Watchdog event due to missing READY"
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bitfld.long 0x00 25. "BO,Bus_Off Status" "Bus_Off status unchanged,Bus_Off status changed"
bitfld.long 0x00 24. "EW,Warning Status" "Error_Warning status unchanged,Error_Warning status changed"
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bitfld.long 0x00 23. "EP,Error Passive" "Error_Passive status unchanged,Error_Passive status changed"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "CAN Error Logging Counter did not overflow,Overflow of CAN Error Logging Counter occurred"
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bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "No bit error detected when reading from Message..,Bit error detected uncorrected (example: parity.."
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "No Rx Buffer updated,At least one received message stored into an Rx.."
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bitfld.long 0x00 18. "TOO,Timeout Occurred" "No timeout,Timeout reached"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or.." "No Message RAM access failure occurred,Message RAM access failure occurred"
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bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "No timestamp counter wrap-around,Timestamp counter wrapped around"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.."
newline
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "Tx Event FIFO fill level below watermark,Tx Event FIFO fill level reached watermark"
newline
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "Tx Event FIFO unchanged,Tx Handler wrote Tx Event FIFO element"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "Tx FIFO non-empty,Tx FIFO empty"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "No transmission cancellation finished,Transmission cancellation finished"
bitfld.long 0x00 9. "TC,Transmission Completed" "No transmission completed,Transmission completed"
newline
bitfld.long 0x00 8. "HPM,High Priority Message" "No high priority message received,High priority message received"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.."
newline
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "Rx FIFO 1 fill level below watermark,Rx FIFO 1 fill level reached watermark"
newline
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "No new message written to Rx FIFO 1,New message written to Rx FIFO 1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.."
newline
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "Rx FIFO 0 fill level below watermark,Rx FIFO 0 fill level reached watermark"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "No new message written to Rx FIFO 0,New message written to Rx FIFO 0"
line.long 0x04 "MCAN_IE,Interrupt Enable The settings in the Interrupt Enable register determine which status changes in the register are signalled on an interrupt line"
bitfld.long 0x04 29. "ARAE,Access to Reserved Address Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 8. "HPME,High Priority Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled"
newline
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled"
line.long 0x08 "MCAN_ILS,Interrupt Line Select The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the register to one of the two module interrupt lines"
bitfld.long 0x08 29. "ARAL,Access to Reserved Address Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 8. "HPML,High Priority Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
newline
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1"
line.long 0x0C "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "Interrupt line INT1 disabled,Interrupt line INT1 enabled"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "Interrupt line INT0 disabled,Interrupt line INT0 enabled"
group.long 0x80++0x0B
line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject"
newline
bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "Filter remote frames with 11-bit standard IDs,Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "Filter remote frames with 29-bit extended IDs,Reject all remote frames with 29-bit extended IDs"
line.long 0x04 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see"
line.long 0x08 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see"
group.long 0x90++0x57
line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame"
line.long 0x04 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List Indicates the filter list of the matching filter element" "Standard Filter List,Extended Filter List"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index Index of matching filter element"
newline
bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "No FIFO selected,FIFO message lost,Message stored in FIFO 0,Message stored in FIFO 1"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x08 31. "ND31,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 30. "ND30,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 29. "ND29,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 28. "ND28,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 27. "ND27,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 26. "ND26,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 25. "ND25,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 24. "ND24,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 23. "ND23,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 22. "ND22,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 21. "ND21,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 20. "ND20,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 19. "ND19,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 18. "ND18,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 17. "ND17,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 16. "ND16,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 15. "ND15,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 14. "ND14,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 13. "ND13,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 12. "ND12,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 11. "ND11,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 10. "ND10,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 9. "ND9,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 8. "ND8,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 7. "ND7,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 6. "ND6,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 5. "ND5,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 4. "ND4,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 3. "ND3,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 2. "ND2,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x08 1. "ND1,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x08 0. "ND0,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
line.long 0x0C "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63"
bitfld.long 0x0C 31. "ND63,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 30. "ND62,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 29. "ND61,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 28. "ND60,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 27. "ND59,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 26. "ND58,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 25. "ND57,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 24. "ND56,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 23. "ND55,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 22. "ND54,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 21. "ND53,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 20. "ND52,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 19. "ND51,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 18. "ND50,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 17. "ND49,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 16. "ND48,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 15. "ND47,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 14. "ND46,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 13. "ND45,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 12. "ND44,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 11. "ND43,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 10. "ND42,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 9. "ND41,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 8. "ND40,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 7. "ND39,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 6. "ND38,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 5. "ND37,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 4. "ND36,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 3. "ND35,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 2. "ND34,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
newline
bitfld.long 0x0C 1. "ND33,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
bitfld.long 0x0C 0. "ND32,New Data" "Rx Buffer not updated,Rx Buffer updated from new message"
line.long 0x10 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0h = FIFO 0 blocking mode 1h = FIFO 0 overwrite mode" "FIFO 0 blocking mode,FIFO 0 overwrite mode"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
newline
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x10 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see"
line.long 0x14 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.."
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full"
newline
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64"
line.long 0x18 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address see )"
line.long 0x20 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x20 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0h = FIFO 1 blocking mode 1h = FIFO 1 overwrite mode" "FIFO 1 blocking mode,FIFO 1 overwrite mode"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
newline
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x20 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see"
line.long 0x24 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x24 30.--31. "DMS,Debug Message Status" "Idle state wait for reception of debug messages..,Debug message A received,Debug messages A B received,Debug messages A B C received DMA request is set"
bitfld.long 0x24 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.."
newline
bitfld.long 0x24 24. "F1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64"
line.long 0x28 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
line.long 0x30 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "Tx FIFO operation,Tx Queue operation"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Note:Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for.."
line.long 0x34 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "Tx FIFO/Queue not full,Tx FIFO/Queue full"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from the Note:In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field"
line.long 0x3C "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request"
bitfld.long 0x3C 31. "TRP31,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 30. "TRP30,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 29. "TRP29,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 28. "TRP28,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 27. "TRP27,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 26. "TRP26,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 25. "TRP25,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 24. "TRP24,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 23. "TRP23,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 22. "TRP22,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 21. "TRP21,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 20. "TRP20,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 19. "TRP19,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 18. "TRP18,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 17. "TRP17,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 16. "TRP16,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 15. "TRP15,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 14. "TRP14,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 13. "TRP13,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 12. "TRP12,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 11. "TRP11,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 10. "TRP10,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 9. "TRP9,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 8. "TRP8,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 7. "TRP7,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 6. "TRP6,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 5. "TRP5,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 4. "TRP4,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 3. "TRP3,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 2. "TRP2,Transmission Request Pending" "No transmission request pending,Transmission request pending"
newline
bitfld.long 0x3C 1. "TRP1,Transmission Request Pending" "No transmission request pending,Transmission request pending"
bitfld.long 0x3C 0. "TRP0,Transmission Request Pending" "No transmission request pending,Transmission request pending"
line.long 0x40 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests"
bitfld.long 0x40 31. "AR31,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 30. "AR30,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 29. "AR29,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 28. "AR28,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 27. "AR27,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 26. "AR26,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 25. "AR25,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 24. "AR24,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 23. "AR23,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 22. "AR22,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 21. "AR21,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 20. "AR20,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 19. "AR19,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 18. "AR18,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 17. "AR17,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 16. "AR16,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 15. "AR15,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 14. "AR14,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 13. "AR13,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 12. "AR12,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 11. "AR11,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 10. "AR10,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 9. "AR9,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 8. "AR8,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 7. "AR7,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 6. "AR6,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 5. "AR5,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 4. "AR4,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 3. "AR3,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 2. "AR2,Add Request" "No transmission request added,Transmission requested added"
newline
bitfld.long 0x40 1. "AR1,Add Request" "No transmission request added,Transmission requested added"
bitfld.long 0x40 0. "AR0,Add Request" "No transmission request added,Transmission requested added"
line.long 0x44 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions"
bitfld.long 0x44 31. "CR31,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 30. "CR30,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 29. "CR29,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 28. "CR28,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 27. "CR27,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 26. "CR26,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 25. "CR25,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 24. "CR24,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 23. "CR23,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 22. "CR22,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 21. "CR21,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 20. "CR20,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 19. "CR19,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 18. "CR18,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 17. "CR17,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 16. "CR16,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 15. "CR15,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 14. "CR14,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 13. "CR13,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 12. "CR12,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 11. "CR11,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 10. "CR10,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 9. "CR9,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 8. "CR8,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 7. "CR7,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 6. "CR6,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 5. "CR5,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 4. "CR4,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 3. "CR3,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 2. "CR2,Cancellation Request" "No cancellation pending,Cancellation pending"
newline
bitfld.long 0x44 1. "CR1,Cancellation Request" "No cancellation pending,Cancellation pending"
bitfld.long 0x44 0. "CR0,Cancellation Request" "No cancellation pending,Cancellation pending"
line.long 0x48 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared"
bitfld.long 0x48 31. "TO31,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 30. "TO30,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 29. "TO29,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 28. "TO28,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 27. "TO27,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 26. "TO26,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 25. "TO25,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 24. "TO24,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 23. "TO23,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 22. "TO22,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 21. "TO21,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 20. "TO20,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 19. "TO19,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 18. "TO18,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 17. "TO17,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 16. "TO16,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 15. "TO15,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 14. "TO14,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 13. "TO13,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 12. "TO12,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 11. "TO11,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 10. "TO10,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 9. "TO9,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 8. "TO8,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 7. "TO7,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 6. "TO6,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 5. "TO5,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 4. "TO4,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 3. "TO3,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 2. "TO2,Transmission Occurred" "No transmission occurred,Transmission occurred"
newline
bitfld.long 0x48 1. "TO1,Transmission Occurred" "No transmission occurred,Transmission occurred"
bitfld.long 0x48 0. "TO0,Transmission Occurred" "No transmission occurred,Transmission occurred"
line.long 0x4C "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding flag is cleared after cancellation request"
bitfld.long 0x4C 31. "CF31,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 30. "CF30,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 29. "CF29,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 28. "CF28,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 27. "CF27,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 26. "CF26,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 25. "CF25,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 24. "CF24,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 23. "CF23,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 22. "CF22,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 21. "CF21,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 20. "CF20,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 19. "CF19,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 18. "CF18,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 17. "CF17,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 16. "CF16,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 15. "CF15,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 14. "CF14,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 13. "CF13,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 12. "CF12,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 11. "CF11,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 10. "CF10,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 9. "CF9,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 8. "CF8,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 7. "CF7,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 6. "CF6,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 5. "CF5,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 4. "CF4,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 3. "CF3,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 2. "CF2,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
newline
bitfld.long 0x4C 1. "CF1,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
bitfld.long 0x4C 0. "CF0,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished"
line.long 0x50 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x50 31. "TIE31,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 30. "TIE30,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 29. "TIE29,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 28. "TIE28,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 27. "TIE27,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 26. "TIE26,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 25. "TIE25,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 24. "TIE24,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 23. "TIE23,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 22. "TIE22,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 21. "TIE21,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 20. "TIE20,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 19. "TIE19,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 18. "TIE18,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 17. "TIE17,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 16. "TIE16,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 15. "TIE15,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 14. "TIE14,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 13. "TIE13,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 12. "TIE12,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 11. "TIE11,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 10. "TIE10,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 9. "TIE9,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 8. "TIE8,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 7. "TIE7,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 6. "TIE6,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 5. "TIE5,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 4. "TIE4,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 3. "TIE3,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 2. "TIE2,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
newline
bitfld.long 0x50 1. "TIE1,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
bitfld.long 0x50 0. "TIE0,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable"
line.long 0x54 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x54 31. "CFIE31,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 30. "CFIE30,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 29. "CFIE29,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 28. "CFIE28,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 27. "CFIE27,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 26. "CFIE26,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 25. "CFIE25,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 24. "CFIE24,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 23. "CFIE23,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 22. "CFIE22,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 21. "CFIE21,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 20. "CFIE20,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 19. "CFIE19,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 18. "CFIE18,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 17. "CFIE17,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 16. "CFIE16,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 15. "CFIE15,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 14. "CFIE14,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 13. "CFIE13,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 12. "CFIE12,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 11. "CFIE11,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 10. "CFIE10,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 9. "CFIE9,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 8. "CFIE8,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 7. "CFIE7,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 6. "CFIE6,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 5. "CFIE5,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 4. "CFIE4,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 3. "CFIE3,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 2. "CFIE2,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
newline
bitfld.long 0x54 1. "CFIE1,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
bitfld.long 0x54 0. "CFIE0,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled"
group.long 0xF0++0x0B
line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see"
line.long 0x04 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,This bit is a copy of interrupt flag" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.."
bitfld.long 0x04 24. "EFF,Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full"
newline
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "MCAN_ECC_Aggregator"
repeat 6. (increment 8 1) (increment ad:0x2A40000 0x1000)
tree "MCAN$1_ECC_AGGR"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MCANSS_ECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator"
group.long 0x3C++0x07
line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x80++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x180++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1"
line.long 0x04 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1"
line.long 0x08 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3"
line.long 0x0C "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3"
tree.end
repeat.end
repeat 8. (increment 0 1) (increment ad:0x2A78000 0x1000)
tree "MCAN$1_ECC_AGGR"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MCANSS_ECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator"
group.long 0x3C++0x07
line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x80++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x180++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1"
line.long 0x04 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1"
line.long 0x08 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3"
line.long 0x0C "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3"
tree.end
repeat.end
tree "MCU_MCAN0_ECC_AGGR"
base ad:0x40700000
rgroup.long 0x00++0x03
line.long 0x00 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MCANSS_ECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator"
group.long 0x3C++0x07
line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x80++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x180++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1"
line.long 0x04 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1"
line.long 0x08 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3"
line.long 0x0C "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3"
tree.end
tree "MCU_MCAN1_ECC_AGGR"
base ad:0x40701000
rgroup.long 0x00++0x03
line.long 0x00 "MCANSS_ECC_REV,Aggregator Revision Register The Aggregator Revision Register contains the revision parameters for the ECC Aggregator"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MCANSS_ECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator"
group.long 0x3C++0x07
line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Single Error Correction End Of Interrupt (SEC EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x80++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MCANSS_ECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,Double Error Correction End Of Interrupt (DED EOI)" "0,1"
line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1"
group.long 0x180++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set for MSGMEM_PEND" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear for MSGMEM_PEND" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MCANSS_ECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set for Parity Errors" "0,1"
line.long 0x04 "MCANSS_ECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for Serial ECC Interface Timeout Errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for Parity Errors" "0,1"
line.long 0x08 "MCANSS_ECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt Status Set for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt Status Set for Parity Errors" "0,1,2,3"
line.long 0x0C "MCANSS_ECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt Status Clear for Serial ECC Interface Timeout Errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt Status Clear for Parity Errors" "0,1,2,3"
tree.end
tree.end
tree "MCAN_Subsystem"
tree "MCAN0_SS"
base ad:0x2700000
rgroup.long 0x00++0x2B
line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
newline
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,Debug Suspend" "Honor debug suspend,Disregard debug suspend"
line.long 0x08 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE,Memory Initialization" "Memory initialization is in progress,Memory intialization done"
line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits" "0,1"
line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits" "0,1"
line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits" "0,1"
line.long 0x18 "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits" "0,1"
line.long 0x1C "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
abitfld.long 0x20 0.--7. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0)" "0x00=EOI value for external timestamp interrupt,0x01=EOI value for mcan[0] interrupt,0x02=EOI value for mcan[1] interrupt"
line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h"
line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
repeat 14. (increment 0 1) (increment ad:0x2700000 0x10000)
tree "MCAN$1_SS"
base $2
rgroup.long 0x00++0x2B
line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
newline
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,Debug Suspend" "Honor debug suspend,Disregard debug suspend"
line.long 0x08 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE,Memory Initialization" "Memory initialization is in progress,Memory intialization done"
line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits" "0,1"
line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits" "0,1"
line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits" "0,1"
line.long 0x18 "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits" "0,1"
line.long 0x1C "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
abitfld.long 0x20 0.--7. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0)" "0x00=EOI value for external timestamp interrupt,0x01=EOI value for mcan[0] interrupt,0x02=EOI value for mcan[1] interrupt"
line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h"
line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
repeat.end
tree "MCU_MCAN0_SS"
base ad:0x40520000
rgroup.long 0x00++0x2B
line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
newline
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,Debug Suspend" "Honor debug suspend,Disregard debug suspend"
line.long 0x08 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE,Memory Initialization" "Memory initialization is in progress,Memory intialization done"
line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits" "0,1"
line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits" "0,1"
line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits" "0,1"
line.long 0x18 "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits" "0,1"
line.long 0x1C "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
abitfld.long 0x20 0.--7. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0)" "0x00=EOI value for external timestamp interrupt,0x01=EOI value for mcan[0] interrupt,0x02=EOI value for mcan[1] interrupt"
line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h"
line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MCU_MCAN1_SS"
base ad:0x40560000
rgroup.long 0x00++0x2B
line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the MCANSS"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit (2h = Processors)" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
newline
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,Debug Suspend" "Honor debug suspend,Disregard debug suspend"
line.long 0x08 "MCANSS_STAT,Status Register The Status Register provides general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port -h = mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE,Memory Initialization" "Memory initialization is in progress,Memory intialization done"
line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write 1h to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits" "0,1"
line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Write 1h to set interrupt bits"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Write 1h to set bits" "0,1"
line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write 1h to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to clear bits" "0,1"
line.long 0x18 "MCANSS_IE,Interrupt Enable Register Write 1h to set interrupt bits"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Write 1h to set bits" "0,1"
line.long 0x1C "MCANSS_IES,Interrupt Enable Status Register Read enabled interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MCANSS_EOI,End Of Interrupt (EOI) Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
abitfld.long 0x20 0.--7. "EOI,End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0)" "0x00=EOI value for external timestamp interrupt,0x01=EOI value for mcan[0] interrupt,0x02=EOI value for mcan[1] interrupt"
line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp Prescaler Register"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h"
line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp Unserviced Interrupts Counter Register"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "MCASP"
repeat 12. (increment 0 1) (increment ad:0x2B00000 0x10000)
tree "MCASP$1_CFG"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "MCASP_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3"
bitfld.long 0x00 28.--29. "RESV," "RESV_0,RESV_1,RESV_2,RESV_3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,McASP"
bitfld.long 0x00 11.--15. "RTL," "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31"
bitfld.long 0x00 8.--10. "REVMAJOR," "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3"
bitfld.long 0x00 0.--5. "REVMINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG register"
hexmask.long 0x04 6.--31. 1. "RSV,Reserved as per PDR 35"
bitfld.long 0x04 2.--5. "Other,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--1. "IDLE_MODE,Idle Mode" "0,1,2,3"
group.long 0x10++0x0F
line.long 0x00 "MCASP_PFUNC,"
bitfld.long 0x00 31. "AFSR,AFSR PFUNC 31" "AFSR_0,AFSR_1"
bitfld.long 0x00 30. "AHCLKR,AHCLKR PFUNC 30" "AHCLKR_0,AHCLKR_1"
bitfld.long 0x00 29. "ACLKR,ACLKR PFUNC 29" "ACLKR_0,ACLKR_1"
bitfld.long 0x00 28. "AFSX,AFSX PFUNC 28" "AFSX_0,AFSX_1"
bitfld.long 0x00 27. "AHCLKX,AHCLKX PFUNC 27" "AHCLKX_0,AHCLKX_1"
newline
bitfld.long 0x00 26. "ACLKX,ACLKX PFUNC 26" "ACLKX_0,ACLKX_1"
bitfld.long 0x00 25. "AMUTE,AMUTE PFUNC 25" "AMUTE_0,AMUTE_1"
hexmask.long.word 0x00 16.--24. 1. "RESV1,Reserved"
bitfld.long 0x00 15. "AXR15,AXR PFUNC BIT 15" "AXR15_0,AXR15_1"
bitfld.long 0x00 14. "AXR14,AXR PFUNC BIT 14" "AXR14_0,AXR14_1"
newline
bitfld.long 0x00 13. "AXR13,AXR PFUNC BIT 13" "AXR13_0,AXR13_1"
bitfld.long 0x00 12. "AXR12,AXR PFUNC BIT 12" "AXR12_0,AXR12_1"
bitfld.long 0x00 11. "AXR11,AXR PFUNC BIT 11" "AXR11_0,AXR11_1"
bitfld.long 0x00 10. "AXR10,AXR PFUNC BIT 10" "AXR10_0,AXR10_1"
bitfld.long 0x00 9. "AXR9,AXR PFUNC BIT 9" "AXR9_0,AXR9_1"
newline
bitfld.long 0x00 8. "AXR8,AXR PFUNC BIT 8" "AXR8_0,AXR8_1"
bitfld.long 0x00 7. "AXR7,AXR PFUNC BIT 7" "AXR7_0,AXR7_1"
bitfld.long 0x00 6. "AXR6,AXR PFUNC BIT 6" "AXR6_0,AXR6_1"
bitfld.long 0x00 5. "AXR5,AXR PFUNC BIT 5" "AXR5_0,AXR5_1"
bitfld.long 0x00 4. "AXR4,AXR PFUNC BIT 4" "AXR4_0,AXR4_1"
newline
bitfld.long 0x00 3. "AXR3,AXR PFUNC BIT 3" "AXR3_0,AXR3_1"
bitfld.long 0x00 2. "AXR2,AXR PFUNC BIT 2" "AXR2_0,AXR2_1"
bitfld.long 0x00 1. "AXR1,AXR PFUNC BIT 1" "AXR1_0,AXR1_1"
bitfld.long 0x00 0. "AXR0,AXR PFUNC BIT 0" "AXR0_0,AXR0_1"
line.long 0x04 "MCASP_PDIR,"
bitfld.long 0x04 31. "AFSR,AFSR PDIR 31" "AFSR_0,AFSR_1"
bitfld.long 0x04 30. "AHCLKR,AHCLKR PDIR 30" "AHCLKR_0,AHCLKR_1"
bitfld.long 0x04 29. "ACLKR,ACLKR PDIR 29" "ACLKR_0,ACLKR_1"
bitfld.long 0x04 28. "AFSX,AFSX PDIR 28" "AFSX_0,AFSX_1"
bitfld.long 0x04 27. "AHCLKX,AHCLKX PDIR 27" "AHCLKX_0,AHCLKX_1"
newline
bitfld.long 0x04 26. "ACLKX,ACLKX PDIR 26" "ACLKX_0,ACLKX_1"
bitfld.long 0x04 25. "AMUTE,AMUTE PDIR 25" "AMUTE_0,AMUTE_1"
hexmask.long.word 0x04 16.--24. 1. "RESV,Reserved"
bitfld.long 0x04 15. "AXR15,AXR PDIR BIT 15" "AXR15_0,AXR15_1"
bitfld.long 0x04 14. "AXR14,AXR PDIR BIT 14" "AXR14_0,AXR14_1"
newline
bitfld.long 0x04 13. "AXR13,AXR PDIR BIT 13" "AXR13_0,AXR13_1"
bitfld.long 0x04 12. "AXR12,AXR PDIR BIT 12" "AXR12_0,AXR12_1"
bitfld.long 0x04 11. "AXR11,AXR PDIR BIT 11" "AXR11_0,AXR11_1"
bitfld.long 0x04 10. "AXR10,AXR PDIR BIT 10" "AXR10_0,AXR10_1"
bitfld.long 0x04 9. "AXR9,AXR PDIR BIT 9" "AXR9_0,AXR9_1"
newline
bitfld.long 0x04 8. "AXR8,AXR PDIR BIT 8" "AXR8_0,AXR8_1"
bitfld.long 0x04 7. "AXR7,AXR PDIR BIT 7" "AXR7_0,AXR7_1"
bitfld.long 0x04 6. "AXR6,AXR PDIR BIT 6" "AXR6_0,AXR6_1"
bitfld.long 0x04 5. "AXR5,AXR PDIR BIT 5" "AXR5_0,AXR5_1"
bitfld.long 0x04 4. "AXR4,AXR PDIR BIT 4" "AXR4_0,AXR4_1"
newline
bitfld.long 0x04 3. "AXR3,AXR PDIR BIT 3" "AXR3_0,AXR3_1"
bitfld.long 0x04 2. "AXR2,AXR PDIR BIT 2" "AXR2_0,AXR2_1"
bitfld.long 0x04 1. "AXR1,AXR PDIR BIT 1" "AXR1_0,AXR1_1"
bitfld.long 0x04 0. "AXR0,AXR PDIR BIT 0" "AXR0_0,AXR0_1"
line.long 0x08 "MCASP_PDOUT,"
bitfld.long 0x08 31. "AFSR,AFSR PDOUT 31" "AFSR_0,AFSR_1"
bitfld.long 0x08 30. "AHCLKR,AHCLKR PDOUT 30" "AHCLKR_0,AHCLKR_1"
bitfld.long 0x08 29. "ACLKR,ACLKR PDOUT 29" "ACLKR_0,ACLKR_1"
bitfld.long 0x08 28. "AFSX,AFSX PDOUT 28" "AFSX_0,AFSX_1"
bitfld.long 0x08 27. "AHCLKX,AHCLKX PDOUT 27" "AHCLKX_0,AHCLKX_1"
newline
bitfld.long 0x08 26. "ACLKX,ACLKX PDOUT 26" "ACLKX_0,ACLKX_1"
bitfld.long 0x08 25. "AMUTE,AMUTE PDOUT 25" "AMUTE_0,AMUTE_1"
hexmask.long.word 0x08 16.--24. 1. "RESV,Reserved"
bitfld.long 0x08 15. "AXR15,AXR PDOUT BIT 15" "AXR15_0,AXR15_1"
bitfld.long 0x08 14. "AXR14,AXR PDOUT BIT 14" "AXR14_0,AXR14_1"
newline
bitfld.long 0x08 13. "AXR13,AXR PDOUT BIT 13" "AXR13_0,AXR13_1"
bitfld.long 0x08 12. "AXR12,AXR PDOUT BIT 12" "AXR12_0,AXR12_1"
bitfld.long 0x08 11. "AXR11,AXR PDOUT BIT 11" "AXR11_0,AXR11_1"
bitfld.long 0x08 10. "AXR10,AXR PDOUT BIT 10" "AXR10_0,AXR10_1"
bitfld.long 0x08 9. "AXR9,AXR PDOUT BIT 9" "AXR9_0,AXR9_1"
newline
bitfld.long 0x08 8. "AXR8,AXR PDOUT BIT 8" "AXR8_0,AXR8_1"
bitfld.long 0x08 7. "AXR7,AXR PDOUT BIT 7" "AXR7_0,AXR7_1"
bitfld.long 0x08 6. "AXR6,AXR PDOUT BIT 6" "AXR6_0,AXR6_1"
bitfld.long 0x08 5. "AXR5,AXR PDOUT BIT 5" "AXR5_0,AXR5_1"
bitfld.long 0x08 4. "AXR4,AXR PDOUT BIT 4" "AXR4_0,AXR4_1"
newline
bitfld.long 0x08 3. "AXR3,AXR PDOUT BIT 3" "AXR3_0,AXR3_1"
bitfld.long 0x08 2. "AXR2,AXR PDOUT BIT 2" "AXR2_0,AXR2_1"
bitfld.long 0x08 1. "AXR1,AXR PDOUT BIT 1" "AXR1_0,AXR1_1"
bitfld.long 0x08 0. "AXR0,AXR PDOUT BIT 0" "AXR0_0,AXR0_1"
line.long 0x0C "MCASP_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "AFSR,AFSR PDIN 31" "AFSR_0,AFSR_1"
bitfld.long 0x0C 30. "AHCLKR,AHCLKR PDIN 30" "AHCLKR_0,AHCLKR_1"
bitfld.long 0x0C 29. "ACLKR,ACLKR PDIN 29" "ACLKR_0,ACLKR_1"
bitfld.long 0x0C 28. "AFSX,AFSX PDIN 28" "AFSX_0,AFSX_1"
bitfld.long 0x0C 27. "AHCLKX,AHCLKX PDIN 27" "AHCLKX_0,AHCLKX_1"
newline
bitfld.long 0x0C 26. "ACLKX,ACLKX PDIN 26" "ACLKX_0,ACLKX_1"
bitfld.long 0x0C 25. "AMUTE,AMUTE PDIN 25" "AMUTE_0,AMUTE_1"
hexmask.long.word 0x0C 16.--24. 1. "RESV,Reserved"
bitfld.long 0x0C 15. "AXR15,AXR PDIN BIT 15" "AXR15_0,AXR15_1"
bitfld.long 0x0C 14. "AXR14,AXR PDIN BIT 14" "AXR14_0,AXR14_1"
newline
bitfld.long 0x0C 13. "AXR13,AXR PDIN BIT 13" "AXR13_0,AXR13_1"
bitfld.long 0x0C 12. "AXR12,AXR PDIN BIT 12" "AXR12_0,AXR12_1"
bitfld.long 0x0C 11. "AXR11,AXR PDIN BIT 11" "AXR11_0,AXR11_1"
bitfld.long 0x0C 10. "AXR10,AXR PDIN BIT 10" "AXR10_0,AXR10_1"
bitfld.long 0x0C 9. "AXR9,AXR PDIN BIT 9" "AXR9_0,AXR9_1"
newline
bitfld.long 0x0C 8. "AXR8,AXR PDIN BIT 8" "AXR8_0,AXR8_1"
bitfld.long 0x0C 7. "AXR7,AXR PDIN BIT 7" "AXR7_0,AXR7_1"
bitfld.long 0x0C 6. "AXR6,AXR PDIN BIT 6" "AXR6_0,AXR6_1"
bitfld.long 0x0C 5. "AXR5,AXR PDIN BIT 5" "AXR5_0,AXR5_1"
bitfld.long 0x0C 4. "AXR4,AXR PDIN BIT 4" "AXR4_0,AXR4_1"
newline
bitfld.long 0x0C 3. "AXR3,AXR PDIN BIT 3" "AXR3_0,AXR3_1"
bitfld.long 0x0C 2. "AXR2,AXR PDIN BIT 2" "AXR2_0,AXR2_1"
bitfld.long 0x0C 1. "AXR1,AXR PDIN BIT 1" "AXR1_0,AXR1_1"
bitfld.long 0x0C 0. "AXR0,AXR PDIN BIT 0" "AXR0_0,AXR0_1"
group.long 0x1C++0x07
line.long 0x00 "MCASP_PDSET,The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x00 31. "AFSR,AFSR PDSET 31" "AFSR_0,AFSR_1"
bitfld.long 0x00 30. "AHCLKR,AHCLKR PDSET 30" "AHCLKR_0,AHCLKR_1"
bitfld.long 0x00 29. "ACLKR,ACLKR PDSET 29" "ACLKR_0,ACLKR_1"
bitfld.long 0x00 28. "AFSX,AFSX PDSET 28" "AFSX_0,AFSX_1"
bitfld.long 0x00 27. "AHCLKX,AHCLKX PDSET 27" "AHCLKX_0,AHCLKX_1"
newline
bitfld.long 0x00 26. "ACLKX,ACLKX PDSET 26" "ACLKX_0,ACLKX_1"
bitfld.long 0x00 25. "AMUTE,AMUTE PDSET 25" "AMUTE_0,AMUTE_1"
hexmask.long.word 0x00 16.--24. 1. "RESV,Reserved"
bitfld.long 0x00 15. "AXR15,AXR PDSET BIT 15" "AXR15_0,AXR15_1"
bitfld.long 0x00 14. "AXR14,AXR PDSET BIT 14" "AXR14_0,AXR14_1"
newline
bitfld.long 0x00 13. "AXR13,AXR PDSET BIT 13" "AXR13_0,AXR13_1"
bitfld.long 0x00 12. "AXR12,AXR PDSET BIT 12" "AXR12_0,AXR12_1"
bitfld.long 0x00 11. "AXR11,AXR PDSET BIT 11" "AXR11_0,AXR11_1"
bitfld.long 0x00 10. "AXR10,AXR PDSET BIT 10" "AXR10_0,AXR10_1"
bitfld.long 0x00 9. "AXR9,AXR PDSET BIT 9" "AXR9_0,AXR9_1"
newline
bitfld.long 0x00 8. "AXR8,AXR PDSET BIT 8" "AXR8_0,AXR8_1"
bitfld.long 0x00 7. "AXR7,AXR PDSET BIT 7" "AXR7_0,AXR7_1"
bitfld.long 0x00 6. "AXR6,AXR PDSET BIT 6" "AXR6_0,AXR6_1"
bitfld.long 0x00 5. "AXR5,AXR PDSET BIT 5" "AXR5_0,AXR5_1"
bitfld.long 0x00 4. "AXR4,AXR PDSET BIT 4" "AXR4_0,AXR4_1"
newline
bitfld.long 0x00 3. "AXR3,AXR PDSET BIT 3" "AXR3_0,AXR3_1"
bitfld.long 0x00 2. "AXR2,AXR PDSET BIT 2" "AXR2_0,AXR2_1"
bitfld.long 0x00 1. "AXR1,AXR PDSET BIT 1" "AXR1_0,AXR1_1"
bitfld.long 0x00 0. "AXR0,AXR PDSET BIT 0" "AXR0_0,AXR0_1"
line.long 0x04 "MCASP_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x04 31. "AFSR,AFSR PDCLR 31" "AFSR_0,AFSR_1"
bitfld.long 0x04 30. "AHCLKR,AHCLKR PDCLR 30" "AHCLKR_0,AHCLKR_1"
bitfld.long 0x04 29. "ACLKR,ACLKR PDCLR 29" "ACLKR_0,ACLKR_1"
bitfld.long 0x04 28. "AFSX,AFSX PDCLR 28" "AFSX_0,AFSX_1"
bitfld.long 0x04 27. "AHCLKX,AHCLKX PDCLR 27" "AHCLKX_0,AHCLKX_1"
newline
bitfld.long 0x04 26. "ACLKX,ACLKX PDCLR 26" "ACLKX_0,ACLKX_1"
bitfld.long 0x04 25. "AMUTE,AMUTE PDCLR 25" "AMUTE_0,AMUTE_1"
hexmask.long.word 0x04 16.--24. 1. "RESV,Reserved"
bitfld.long 0x04 15. "AXR15,AXR PDCLR BIT 15" "AXR15_0,AXR15_1"
bitfld.long 0x04 14. "AXR14,AXR PDCLR BIT 14" "AXR14_0,AXR14_1"
newline
bitfld.long 0x04 13. "AXR13,AXR PDCLR BIT 13" "AXR13_0,AXR13_1"
bitfld.long 0x04 12. "AXR12,AXR PDCLR BIT 12" "AXR12_0,AXR12_1"
bitfld.long 0x04 11. "AXR11,AXR PDCLR BIT 11" "AXR11_0,AXR11_1"
bitfld.long 0x04 10. "AXR10,AXR PDCLR BIT 10" "AXR10_0,AXR10_1"
bitfld.long 0x04 9. "AXR9,AXR PDCLR BIT 9" "AXR9_0,AXR9_1"
newline
bitfld.long 0x04 8. "AXR8,AXR PDCLR BIT 8" "AXR8_0,AXR8_1"
bitfld.long 0x04 7. "AXR7,AXR PDCLR BIT 7" "AXR7_0,AXR7_1"
bitfld.long 0x04 6. "AXR6,AXR PDCLR BIT 6" "AXR6_0,AXR6_1"
bitfld.long 0x04 5. "AXR5,AXR PDCLR BIT 5" "AXR5_0,AXR5_1"
bitfld.long 0x04 4. "AXR4,AXR PDCLR BIT 4" "AXR4_0,AXR4_1"
newline
bitfld.long 0x04 3. "AXR3,AXR PDCLR BIT 3" "AXR3_0,AXR3_1"
bitfld.long 0x04 2. "AXR2,AXR PDCLR BIT 2" "AXR2_0,AXR2_1"
bitfld.long 0x04 1. "AXR1,AXR PDCLR BIT 1" "AXR1_0,AXR1_1"
bitfld.long 0x04 0. "AXR0,AXR PDCLR BIT 0" "AXR0_0,AXR0_1"
group.long 0x30++0x0B
line.long 0x00 "MCASP_TLGC,for IODFT"
hexmask.long.word 0x00 16.--31. 1. "RESV,Reserved"
bitfld.long 0x00 14.--15. "MT,MISR on/off trigger command" "MT_0,MT_1,MT_2,MT_3"
bitfld.long 0x00 9.--13. "RESV1,Reserved" "RESV1_0,RESV1_1,RESV1_2,RESV1_3,RESV1_4,RESV1_5,RESV1_6,RESV1_7,RESV1_8,RESV1_9,RESV1_10,RESV1_11,RESV1_12,RESV1_13,RESV1_14,RESV1_15,RESV1_16,RESV1_17,RESV1_18,RESV1_19,RESV1_20,RESV1_21,RESV1_22,RESV1_23,RESV1_24,RESV1_25,RESV1_26,RESV1_27,RESV1_28,RESV1_29,RESV1_30,RESV1_31"
bitfld.long 0x00 8. "MMS,Source of MISR input" "MMS_0,MMS_1"
bitfld.long 0x00 7. "ESEL,Output enable select" "ESEL_0,ESEL_1"
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bitfld.long 0x00 6. "TOEN,Test output enable control" "TOEN_0,TOEN_1"
bitfld.long 0x00 4.--5. "MC,States of MISR" "MC_0,MC_1,MC_2,MC_3"
bitfld.long 0x00 1.--3. "PC,Pattern code" "PC_0,PC_1,PC_2,PC_3,PC_4,PC_5,PC_6,PC_7"
bitfld.long 0x00 0. "TM,Tie high" "TM_0,TM_1"
line.long 0x04 "MCASP_TLMR,for IODFT"
line.long 0x08 "MCASP_TLEC,for IODFT"
group.long 0x44++0x0F
line.long 0x00 "MCASP_GBLCTL,"
bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1"
bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1"
bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1"
bitfld.long 0x00 9. "XHCLKRST,XMT High Freq clk Divider" "XHCLKRST_0,XHCLKRST_1"
bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1"
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bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1"
bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1"
bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1"
bitfld.long 0x00 1. "RHCLKRST,RCV High Freq clk Divider" "RHCLKRST_0,RHCLKRST_1"
bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1"
line.long 0x04 "MCASP_AMUTE,"
bitfld.long 0x04 12. "XDMAERR,MUTETXDMAERR occur" "XDMAERR_0,XDMAERR_1"
bitfld.long 0x04 11. "RDMAERR,MUTERXDMAERR occur" "RDMAERR_0,RDMAERR_1"
bitfld.long 0x04 10. "XCKFAIL,XMT bad clock" "XCKFAIL_0,XCKFAIL_1"
bitfld.long 0x04 9. "RCKFAIL,RCV bad clock" "RCKFAIL_0,RCKFAIL_1"
bitfld.long 0x04 8. "XSYNCERR,XMT unexpected FS" "XSYNCERR_0,XSYNCERR_1"
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bitfld.long 0x04 7. "RSYNCERR,RCV unexpected FS" "RSYNCERR_0,RSYNCERR_1"
bitfld.long 0x04 6. "XUNDRN,XMT underrun occurs" "XUNDRN_0,XUNDRN_1"
bitfld.long 0x04 5. "ROVRN,RCV overun occurs" "ROVRN_0,ROVRN_1"
rbitfld.long 0x04 4. "INSTAT,status of mute in pin" "INSTAT_0,INSTAT_1"
bitfld.long 0x04 3. "INEN,drive AMUTE active on mute in active" "INEN_0,INEN_1"
newline
bitfld.long 0x04 2. "INPOL,Mute input polarity" "INPOL_0,INPOL_1"
bitfld.long 0x04 0.--1. "MUTEN,AMUTE pin enable" "MUTEN_0,MUTEN_1,MUTEN_2,MUTEN_3"
line.long 0x08 "MCASP_LBCTL,"
bitfld.long 0x08 4. "IOLBEN,IO loopback enable" "IOLBEN_0,IOLBEN_1"
bitfld.long 0x08 2.--3. "MODE,Loop back clock source generator" "MODE_0,MODE_1,MODE_2,MODE_3"
bitfld.long 0x08 1. "ORD,Loopback order" "ORD_0,ORD_1"
bitfld.long 0x08 0. "DLBEN,Loop back mode" "DLBEN_0,DLBEN_1"
line.long 0x0C "MCASP_TXDITCTL,"
bitfld.long 0x0C 3. "VB,Valib bit for odd TDM" "VB_0,VB_1"
bitfld.long 0x0C 2. "VA,Valib bit for even TDM" "VA_0,VA_1"
bitfld.long 0x0C 0. "DITEN,XMT DIT Mode Enable" "DITEN_0,DITEN_1"
group.long 0x60++0x2F
line.long 0x00 "MCASP_GBLCTLR,"
rbitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1"
rbitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1"
rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1"
rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq clk Divider" "XHCLKRST_0,XHCLKRST_1"
rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1"
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bitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1"
bitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1"
bitfld.long 0x00 2. "RSRCLR,RCV serializer clear" "RSRCLR_0,RSRCLR_1"
bitfld.long 0x00 1. "RHCLKRST,RCV High Freq clk Divider" "RHCLKRST_0,RHCLKRST_1"
bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1"
line.long 0x04 "MCASP_RXMASK,"
bitfld.long 0x04 31. "RMASK31,RMASK BIT 31" "RMASK31_0,RMASK31_1"
bitfld.long 0x04 30. "RMASK30,RMASK BIT 30" "RMASK30_0,RMASK30_1"
bitfld.long 0x04 29. "RMASK29,RMASK BIT 29" "RMASK29_0,RMASK29_1"
bitfld.long 0x04 28. "RMASK28,RMASK BIT 28" "RMASK28_0,RMASK28_1"
bitfld.long 0x04 27. "RMASK27,RMASK BIT 27" "RMASK27_0,RMASK27_1"
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bitfld.long 0x04 26. "RMASK26,RMASK BIT 26" "RMASK26_0,RMASK26_1"
bitfld.long 0x04 25. "RMASK25,RMASK BIT 25" "RMASK25_0,RMASK25_1"
bitfld.long 0x04 24. "RMASK24,RMASK BIT 24" "RMASK24_0,RMASK24_1"
bitfld.long 0x04 23. "RMASK23,RMASK BIT 23" "RMASK23_0,RMASK23_1"
bitfld.long 0x04 22. "RMASK22,RMASK BIT 22" "RMASK22_0,RMASK22_1"
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bitfld.long 0x04 21. "RMASK21,RMASK BIT 21" "RMASK21_0,RMASK21_1"
bitfld.long 0x04 20. "RMASK20,RMASK BIT 20" "RMASK20_0,RMASK20_1"
bitfld.long 0x04 19. "RMASK19,RMASK BIT 19" "RMASK19_0,RMASK19_1"
bitfld.long 0x04 18. "RMASK18,RMASK BIT 18" "RMASK18_0,RMASK18_1"
bitfld.long 0x04 17. "RMASK17,RMASK BIT 17" "RMASK17_0,RMASK17_1"
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bitfld.long 0x04 16. "RMASK16,RMASK BIT 16" "RMASK16_0,RMASK16_1"
bitfld.long 0x04 15. "RMASK15,RMASK BIT 15" "RMASK15_0,RMASK15_1"
bitfld.long 0x04 14. "RMASK14,RMASK BIT 14" "RMASK14_0,RMASK14_1"
bitfld.long 0x04 13. "RMASK13,RMASK BIT 13" "RMASK13_0,RMASK13_1"
bitfld.long 0x04 12. "RMASK12,RMASK BIT 12" "RMASK12_0,RMASK12_1"
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bitfld.long 0x04 11. "RMASK11,RMASK BIT 11" "RMASK11_0,RMASK11_1"
bitfld.long 0x04 10. "RMASK10,RMASK BIT 10" "RMASK10_0,RMASK10_1"
bitfld.long 0x04 9. "RMASK9,RMASK BIT 9" "RMASK9_0,RMASK9_1"
bitfld.long 0x04 8. "RMASK8,RMASK BIT 8" "RMASK8_0,RMASK8_1"
bitfld.long 0x04 7. "RMASK7,RMASK BIT 7" "RMASK7_0,RMASK7_1"
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bitfld.long 0x04 6. "RMASK6,RMASK BIT 6" "RMASK6_0,RMASK6_1"
bitfld.long 0x04 5. "RMASK5,RMASK BIT 5" "RMASK5_0,RMASK5_1"
bitfld.long 0x04 4. "RMASK4,RMASK BIT 4" "RMASK4_0,RMASK4_1"
bitfld.long 0x04 3. "RMASK3,RMASK BIT 3" "RMASK3_0,RMASK3_1"
bitfld.long 0x04 2. "RMASK2,RMASK BIT 2" "RMASK2_0,RMASK2_1"
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bitfld.long 0x04 1. "RMASK1,RMASK BIT 1" "RMASK1_0,RMASK1_1"
bitfld.long 0x04 0. "RMASK0,RMASK BIT 0" "RMASK0_0,RMASK0_1"
line.long 0x08 "MCASP_RXFMT,"
bitfld.long 0x08 16.--17. "RDATDLY,RCV Frame sync delay" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3"
bitfld.long 0x08 15. "RRVRS,RCV serial stream bit order" "RRVRS_0,RRVRS_1"
bitfld.long 0x08 13.--14. "RPAD,Pad value" "RPAD_0,RPAD_1,RPAD_2,RPAD_3"
bitfld.long 0x08 8.--12. "RPBIT,Pad bit position" "RPBIT_0,RPBIT_1,RPBIT_2,RPBIT_3,RPBIT_4,RPBIT_5,RPBIT_6,RPBIT_7,RPBIT_8,RPBIT_9,RPBIT_10,RPBIT_11,RPBIT_12,RPBIT_13,RPBIT_14,RPBIT_15,RPBIT_16,RPBIT_17,RPBIT_18,RPBIT_19,RPBIT_20,RPBIT_21,RPBIT_22,RPBIT_23,RPBIT_24,RPBIT_25,RPBIT_26,RPBIT_27,RPBIT_28,RPBIT_29,RPBIT_30,RPBIT_31"
bitfld.long 0x08 4.--7. "RSSZ,RCV slot Size" "RSSZ_0,RSSZ_1,RSSZ_2,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15"
newline
bitfld.long 0x08 3. "RBUSEL,Write to RBUF using CPU/DMA" "RBUSEL_0,RBUSEL_1"
bitfld.long 0x08 0.--2. "RROT,Right Rotate Value" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7"
line.long 0x0C "MCASP_RXFMCTL,"
hexmask.long.word 0x0C 7.--15. 1. "RMOD,RCV Frame sync mode"
bitfld.long 0x0C 4. "FRWID,RCV Frame sync Duration" "FRWID_0,FRWID_1"
bitfld.long 0x0C 1. "FSRM,RCV frame sync External" "FSRM_0,FSRM_1"
bitfld.long 0x0C 0. "FSRP,RCV Frame sync Polarity" "FSRP_0,FSRP_1"
line.long 0x10 "MCASP_ACLKRCTL,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1"
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1"
bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "CLKRADJ_0,CLKRADJ_1,CLKRADJ_2,CLKRADJ_3"
bitfld.long 0x10 7. "CLKRP,RCV Clock Polarity" "CLKRP_0,CLKRP_1"
newline
bitfld.long 0x10 5. "CLKRM,RCV clock source" "CLKRM_0,CLKRM_1"
bitfld.long 0x10 0.--4. "CLKRDIV,RCV clock devide ratio" "CLKRDIV_0,CLKRDIV_1,CLKRDIV_2,CLKRDIV_3,CLKRDIV_4,CLKRDIV_5,CLKRDIV_6,CLKRDIV_7,CLKRDIV_8,CLKRDIV_9,CLKRDIV_10,CLKRDIV_11,CLKRDIV_12,CLKRDIV_13,CLKRDIV_14,CLKRDIV_15,CLKRDIV_16,CLKRDIV_17,CLKRDIV_18,CLKRDIV_19,CLKRDIV_20,CLKRDIV_21,CLKRDIV_22,CLKRDIV_23,CLKRDIV_24,CLKRDIV_25,CLKRDIV_26,CLKRDIV_27,CLKRDIV_28,CLKRDIV_29,CLKRDIV_30,CLKRDIV_31"
line.long 0x14 "MCASP_AHCLKRCTL,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1"
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1"
bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "HCLKRADJ_0,HCLKRADJ_1,HCLKRADJ_2,HCLKRADJ_3"
bitfld.long 0x14 15. "HCLKRM,High Freq RCV clock Source" "HCLKRM_0,HCLKRM_1"
newline
bitfld.long 0x14 14. "HCLKRP,High Freq clock Polarity Before diviser" "HCLKRP_0,HCLKRP_1"
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,RCV clock Divide Ratio"
line.long 0x18 "MCASP_RXTDM,"
bitfld.long 0x18 31. "RTDMS31,RCV mode during TDM time slot 31" "RTDMS31_0,RTDMS31_1"
bitfld.long 0x18 30. "RTDMS30,RCV mode during TDM time slot 30" "RTDMS30_0,RTDMS30_1"
bitfld.long 0x18 29. "RTDMS29,RCV mode during TDM time slot 29" "RTDMS29_0,RTDMS29_1"
bitfld.long 0x18 28. "RTDMS28,RCV mode during TDM time slot 28" "RTDMS28_0,RTDMS28_1"
bitfld.long 0x18 27. "RTDMS27,RCV mode during TDM time slot 27" "RTDMS27_0,RTDMS27_1"
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bitfld.long 0x18 26. "RTDMS26,RCV mode during TDM time slot 26" "RTDMS26_0,RTDMS26_1"
bitfld.long 0x18 25. "RTDMS25,RCV mode during TDM time slot 25" "RTDMS25_0,RTDMS25_1"
bitfld.long 0x18 24. "RTDMS24,RCV mode during TDM time slot 24" "RTDMS24_0,RTDMS24_1"
bitfld.long 0x18 23. "RTDMS23,RCV mode during TDM time slot 23" "RTDMS23_0,RTDMS23_1"
bitfld.long 0x18 22. "RTDMS22,RCV mode during TDM time slot 22" "RTDMS22_0,RTDMS22_1"
newline
bitfld.long 0x18 21. "RTDMS21,RCV mode during TDM time slot 21" "RTDMS21_0,RTDMS21_1"
bitfld.long 0x18 20. "RTDMS20,RCV mode during TDM time slot 20" "RTDMS20_0,RTDMS20_1"
bitfld.long 0x18 19. "RTDMS19,RCV mode during TDM time slot 19" "RTDMS19_0,RTDMS19_1"
bitfld.long 0x18 18. "RTDMS18,RCV mode during TDM time slot 18" "RTDMS18_0,RTDMS18_1"
bitfld.long 0x18 17. "RTDMS17,RCV mode during TDM time slot 17" "RTDMS17_0,RTDMS17_1"
newline
bitfld.long 0x18 16. "RTDMS16,RCV mode during TDM time slot 16" "RTDMS16_0,RTDMS16_1"
bitfld.long 0x18 15. "RTDMS15,RCV mode during TDM time slot 15" "RTDMS15_0,RTDMS15_1"
bitfld.long 0x18 14. "RTDMS14,RCV mode during TDM time slot 14" "RTDMS14_0,RTDMS14_1"
bitfld.long 0x18 13. "RTDMS13,RCV mode during TDM time slot 13" "RTDMS13_0,RTDMS13_1"
bitfld.long 0x18 12. "RTDMS12,RCV mode during TDM time slot 12" "RTDMS12_0,RTDMS12_1"
newline
bitfld.long 0x18 11. "RTDMS11,RCV mode during TDM time slot 11" "RTDMS11_0,RTDMS11_1"
bitfld.long 0x18 10. "RTDMS10,RCV mode during TDM time slot 10" "RTDMS10_0,RTDMS10_1"
bitfld.long 0x18 9. "RTDMS9,RCV mode during TDM time slot 9" "RTDMS9_0,RTDMS9_1"
bitfld.long 0x18 8. "RTDMS8,RCV mode during TDM time slot 8" "RTDMS8_0,RTDMS8_1"
bitfld.long 0x18 7. "RTDMS7,RCV mode during TDM time slot 7" "RTDMS7_0,RTDMS7_1"
newline
bitfld.long 0x18 6. "RTDMS6,RCV mode during TDM time slot 6" "RTDMS6_0,RTDMS6_1"
bitfld.long 0x18 5. "RTDMS5,RCV mode during TDM time slot 5" "RTDMS5_0,RTDMS5_1"
bitfld.long 0x18 4. "RTDMS4,RCV mode during TDM time slot 4" "RTDMS4_0,RTDMS4_1"
bitfld.long 0x18 3. "RTDMS3,RCV mode during TDM time slot 3" "RTDMS3_0,RTDMS3_1"
bitfld.long 0x18 2. "RTDMS2,RCV mode during TDM time slot 2" "RTDMS2_0,RTDMS2_1"
newline
bitfld.long 0x18 1. "RTDMS1,RCV mode during TDM time slot 1" "RTDMS1_0,RTDMS1_1"
bitfld.long 0x18 0. "RTDMS0,RCV mode during TDM time slot 0" "RTDMS0_0,RTDMS0_1"
line.long 0x1C "MCASP_EVTCTLR,"
bitfld.long 0x1C 7. "RSTAFRM,RCV Start of Frame Interrupt" "RSTAFRM_0,RSTAFRM_1"
bitfld.long 0x1C 5. "RDATA,RCV Data Interrupt" "RDATA_0,RDATA_1"
bitfld.long 0x1C 4. "RLAST,RCV Last Slot Interrupt" "RLAST_0,RLAST_1"
bitfld.long 0x1C 3. "RDMAERR,RCV DMA Bus Error" "RDMAERR_0,RDMAERR_1"
bitfld.long 0x1C 2. "RCKFAIL,Bad Clock Interrupt" "RCKFAIL_0,RCKFAIL_1"
newline
bitfld.long 0x1C 1. "RSYNCERR,RCV Unexpected FSR Interrupt" "RSYNCERR_0,RSYNCERR_1"
bitfld.long 0x1C 0. "ROVRN,RCV Underrun Flag" "ROVRN_0,ROVRN_1"
line.long 0x20 "MCASP_RXSTAT,"
bitfld.long 0x20 8. "RERR,RCV Error" "RERR_0,RERR_1"
bitfld.long 0x20 7. "RDMAERR,RCV DMA bus error" "RDMAERR_0,RDMAERR_1"
bitfld.long 0x20 6. "RSTAFRM,Start of Frame-RCV" "RSTAFRM_0,RSTAFRM_1"
bitfld.long 0x20 5. "RDATA,Data Ready Flag" "RDATA_0,RDATA_1"
bitfld.long 0x20 4. "RLAST,Last Slot Interrupt Flag" "RLAST_0,RLAST_1"
newline
bitfld.long 0x20 3. "RTDMSLOT,EvenOdd Slot" "RTDMSLOT_0,RTDMSLOT_1"
bitfld.long 0x20 2. "RCKFAIL,Bad Transmit Flag" "RCKFAIL_0,RCKFAIL_1"
bitfld.long 0x20 1. "RSYNCERR,Unexpected RCV Frame sync flag" "RSYNCERR_0,RSYNCERR_1"
bitfld.long 0x20 0. "ROVRN,RCV Underrun Flag" "ROVRN_0,ROVRN_1"
line.long 0x24 "MCASP_RXTDMSLOT,"
hexmask.long.word 0x24 0.--9. 1. "RSLOTCNT,Current RCV time slot count"
line.long 0x28 "MCASP_RXCLKCHK,"
hexmask.long.byte 0x28 24.--31. 1. "RCNT,RCV clock count value"
hexmask.long.byte 0x28 16.--23. 1. "RMAX,RCV clock maximum boundary"
hexmask.long.byte 0x28 8.--15. 1. "RMIN,RCV clock minimum boundary"
bitfld.long 0x28 0.--3. "RPS,RCV clock check prescaler" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,RPS_9,RPS_10,RPS_11,RPS_12,RPS_13,RPS_14,RPS_15"
line.long 0x2C "MCASP_REVTCTL,"
bitfld.long 0x2C 0. "RDATDMA,RCV data DMA request" "RDATDMA_0,RDATDMA_1"
group.long 0xA0++0x33
line.long 0x00 "MCASP_GBLCTLX,"
bitfld.long 0x00 12. "XFRST,Frame sync generator reset" "XFRST_0,XFRST_1"
bitfld.long 0x00 11. "XSMRST,XMT state machine reset" "XSMRST_0,XSMRST_1"
bitfld.long 0x00 10. "XSRCLR,XMT serializer clear" "XSRCLR_0,XSRCLR_1"
bitfld.long 0x00 9. "XHCLKRST,XMT High Freq clk Divider" "XHCLKRST_0,XHCLKRST_1"
bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset" "XCLKRST_0,XCLKRST_1"
newline
rbitfld.long 0x00 4. "RFRST,Frame sync generator reset" "RFRST_0,RFRST_1"
rbitfld.long 0x00 3. "RSMRST,RCV state machine reset" "RSMRST_0,RSMRST_1"
rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear" "RSRCLKR_0,RSRCLKR_1"
rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq clk Divider" "RHCLKRST_0,RHCLKRST_1"
rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset" "RCLKRST_0,RCLKRST_1"
line.long 0x04 "MCASP_TXMASK,"
bitfld.long 0x04 31. "XMASK31,XMASK BIT 31" "XMASK31_0,XMASK31_1"
bitfld.long 0x04 30. "XMASK30,XMASK BIT 30" "XMASK30_0,XMASK30_1"
bitfld.long 0x04 29. "XMASK29,XMASK BIT 29" "XMASK29_0,XMASK29_1"
bitfld.long 0x04 28. "XMASK28,XMASK BIT 28" "XMASK28_0,XMASK28_1"
bitfld.long 0x04 27. "XMASK27,XMASK BIT 27" "XMASK27_0,XMASK27_1"
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bitfld.long 0x04 26. "XMASK26,XMASK BIT 26" "XMASK26_0,XMASK26_1"
bitfld.long 0x04 25. "XMASK25,XMASK BIT 25" "XMASK25_0,XMASK25_1"
bitfld.long 0x04 24. "XMASK24,XMASK BIT 24" "XMASK24_0,XMASK24_1"
bitfld.long 0x04 23. "XMASK23,XMASK BIT 23" "XMASK23_0,XMASK23_1"
bitfld.long 0x04 22. "XMASK22,XMASK BIT 22" "XMASK22_0,XMASK22_1"
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bitfld.long 0x04 21. "XMASK21,XMASK BIT 21" "XMASK21_0,XMASK21_1"
bitfld.long 0x04 20. "XMASK20,XMASK BIT 20" "XMASK20_0,XMASK20_1"
bitfld.long 0x04 19. "XMASK19,XMASK BIT 19" "XMASK19_0,XMASK19_1"
bitfld.long 0x04 18. "XMASK18,XMASK BIT 18" "XMASK18_0,XMASK18_1"
bitfld.long 0x04 17. "XMASK17,XMASK BIT 17" "XMASK17_0,XMASK17_1"
newline
bitfld.long 0x04 16. "XMASK16,XMASK BIT 16" "XMASK16_0,XMASK16_1"
bitfld.long 0x04 15. "XMASK15,XMASK BIT 15" "XMASK15_0,XMASK15_1"
bitfld.long 0x04 14. "XMASK14,XMASK BIT 14" "XMASK14_0,XMASK14_1"
bitfld.long 0x04 13. "XMASK13,XMASK BIT 13" "XMASK13_0,XMASK13_1"
bitfld.long 0x04 12. "XMASK12,XMASK BIT 12" "XMASK12_0,XMASK12_1"
newline
bitfld.long 0x04 11. "XMASK11,XMASK BIT 11" "XMASK11_0,XMASK11_1"
bitfld.long 0x04 10. "XMASK10,XMASK BIT 10" "XMASK10_0,XMASK10_1"
bitfld.long 0x04 9. "XMASK9,XMASK BIT 9" "XMASK9_0,XMASK9_1"
bitfld.long 0x04 8. "XMASK8,XMASK BIT 8" "XMASK8_0,XMASK8_1"
bitfld.long 0x04 7. "XMASK7,XMASK BIT 7" "XMASK7_0,XMASK7_1"
newline
bitfld.long 0x04 6. "XMASK6,XMASK BIT 6" "XMASK6_0,XMASK6_1"
bitfld.long 0x04 5. "XMASK5,XMASK BIT 5" "XMASK5_0,XMASK5_1"
bitfld.long 0x04 4. "XMASK4,XMASK BIT 4" "XMASK4_0,XMASK4_1"
bitfld.long 0x04 3. "XMASK3,XMASK BIT 3" "XMASK3_0,XMASK3_1"
bitfld.long 0x04 2. "XMASK2,XMASK BIT 2" "XMASK2_0,XMASK2_1"
newline
bitfld.long 0x04 1. "XMASK1,XMASK BIT 1" "XMASK1_0,XMASK1_1"
bitfld.long 0x04 0. "XMASK0,XMASK BIT 0" "XMASK0_0,XMASK0_1"
line.long 0x08 "MCASP_TXFMT,"
bitfld.long 0x08 16.--17. "XDATDLY,XMT Frame sync delay" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3"
bitfld.long 0x08 15. "XRVRS,XMT serial stream bit order" "XRVRS_0,XRVRS_1"
bitfld.long 0x08 13.--14. "XPAD,Pad value" "XPAD_0,XPAD_1,XPAD_2,XPAD_3"
bitfld.long 0x08 8.--12. "XPBIT,Pad bit position" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31"
bitfld.long 0x08 4.--7. "XSSZ,XMT slot Size" "XSSZ_0,XSSZ_1,XSSZ_2,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15"
newline
bitfld.long 0x08 3. "XBUSEL,Write to XBUF using CPU/DMA" "XBUSEL_0,XBUSEL_1"
bitfld.long 0x08 0.--2. "XROT,Right Rotate Value" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7"
line.long 0x0C "MCASP_TXFMCTL,"
hexmask.long.word 0x0C 7.--15. 1. "XMOD,XMT Frame sync mode"
bitfld.long 0x0C 4. "FXWID,XMT Frame sync Duration" "FXWID_0,FXWID_1"
bitfld.long 0x0C 1. "FSXM,XMT frame sync External" "FSXM_0,FSXM_1"
bitfld.long 0x0C 0. "FSXP,XMT Frame sync Polarity" "FSXP_0,FSXP_1"
line.long 0x10 "MCASP_ACLKXCTL,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1"
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1"
bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "CLKXADJ_0,CLKXADJ_1,CLKXADJ_2,CLKXADJ_3"
bitfld.long 0x10 7. "CLKXP,XMT Clock Polarity" "CLKXP_0,CLKXP_1"
newline
bitfld.long 0x10 6. "ASYNC,XMT/RCV operation sync /Async" "ASYNC_0,ASYNC_1"
bitfld.long 0x10 5. "CLKXM,XMT clock source" "CLKXM_0,CLKXM_1"
bitfld.long 0x10 0.--4. "CLKXDIV,XMT clock devide ratio" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31"
line.long 0x14 "MCASP_AHCLKXCTL,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1"
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1"
bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "HCLKXADJ_0,HCLKXADJ_1,HCLKXADJ_2,HCLKXADJ_3"
bitfld.long 0x14 15. "HCLKXM,High Freq XMT clock Source" "HCLKXM_0,HCLKXM_1"
newline
bitfld.long 0x14 14. "HCLKXP,High Freq clock Polarity Before diviser" "HCLKXP_0,HCLKXP_1"
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,XMT clock Divide Ratio"
line.long 0x18 "MCASP_TXTDM,"
bitfld.long 0x18 31. "XTDMS31,XMT mode during TDM time slot 31" "XTDMS31_0,XTDMS31_1"
bitfld.long 0x18 30. "XTDMS30,XMT mode during TDM time slot 30" "XTDMS30_0,XTDMS30_1"
bitfld.long 0x18 29. "XTDMS29,XMT mode during TDM time slot 29" "XTDMS29_0,XTDMS29_1"
bitfld.long 0x18 28. "XTDMS28,XMT mode during TDM time slot 28" "XTDMS28_0,XTDMS28_1"
bitfld.long 0x18 27. "XTDMS27,XMT mode during TDM time slot 27" "XTDMS27_0,XTDMS27_1"
newline
bitfld.long 0x18 26. "XTDMS26,XMT mode during TDM time slot 26" "XTDMS26_0,XTDMS26_1"
bitfld.long 0x18 25. "XTDMS25,XMT mode during TDM time slot 25" "XTDMS25_0,XTDMS25_1"
bitfld.long 0x18 24. "XTDMS24,XMT mode during TDM time slot 24" "XTDMS24_0,XTDMS24_1"
bitfld.long 0x18 23. "XTDMS23,XMT mode during TDM time slot 23" "XTDMS23_0,XTDMS23_1"
bitfld.long 0x18 22. "XTDMS22,XMT mode during TDM time slot 22" "XTDMS22_0,XTDMS22_1"
newline
bitfld.long 0x18 21. "XTDMS21,XMT mode during TDM time slot 21" "XTDMS21_0,XTDMS21_1"
bitfld.long 0x18 20. "XTDMS20,XMT mode during TDM time slot 20" "XTDMS20_0,XTDMS20_1"
bitfld.long 0x18 19. "XTDMS19,XMT mode during TDM time slot 19" "XTDMS19_0,XTDMS19_1"
bitfld.long 0x18 18. "XTDMS18,XMT mode during TDM time slot 18" "XTDMS18_0,XTDMS18_1"
bitfld.long 0x18 17. "XTDMS17,XMT mode during TDM time slot 17" "XTDMS17_0,XTDMS17_1"
newline
bitfld.long 0x18 16. "XTDMS16,XMT mode during TDM time slot 16" "XTDMS16_0,XTDMS16_1"
bitfld.long 0x18 15. "XTDMS15,XMT mode during TDM time slot 15" "XTDMS15_0,XTDMS15_1"
bitfld.long 0x18 14. "XTDMS14,XMT mode during TDM time slot 14" "XTDMS14_0,XTDMS14_1"
bitfld.long 0x18 13. "XTDMS13,XMT mode during TDM time slot 13" "XTDMS13_0,XTDMS13_1"
bitfld.long 0x18 12. "XTDMS12,XMT mode during TDM time slot 12" "XTDMS12_0,XTDMS12_1"
newline
bitfld.long 0x18 11. "XTDMS11,XMT mode during TDM time slot 11" "XTDMS11_0,XTDMS11_1"
bitfld.long 0x18 10. "XTDMS10,XMT mode during TDM time slot 10" "XTDMS10_0,XTDMS10_1"
bitfld.long 0x18 9. "XTDMS9,XMT mode during TDM time slot 9" "XTDMS9_0,XTDMS9_1"
bitfld.long 0x18 8. "XTDMS8,XMT mode during TDM time slot 8" "XTDMS8_0,XTDMS8_1"
bitfld.long 0x18 7. "XTDMS7,XMT mode during TDM time slot 7" "XTDMS7_0,XTDMS7_1"
newline
bitfld.long 0x18 6. "XTDMS6,XMT mode during TDM time slot 6" "XTDMS6_0,XTDMS6_1"
bitfld.long 0x18 5. "XTDMS5,XMT mode during TDM time slot 5" "XTDMS5_0,XTDMS5_1"
bitfld.long 0x18 4. "XTDMS4,XMT mode during TDM time slot 4" "XTDMS4_0,XTDMS4_1"
bitfld.long 0x18 3. "XTDMS3,XMT mode during TDM time slot 3" "XTDMS3_0,XTDMS3_1"
bitfld.long 0x18 2. "XTDMS2,XMT mode during TDM time slot 2" "XTDMS2_0,XTDMS2_1"
newline
bitfld.long 0x18 1. "XTDMS1,XMT mode during TDM time slot 1" "XTDMS1_0,XTDMS1_1"
bitfld.long 0x18 0. "XTDMS0,XMT mode during TDM time slot 0" "XTDMS0_0,XTDMS0_1"
line.long 0x1C "MCASP_EVTCTLX,"
bitfld.long 0x1C 7. "XSTAFRM,XMT Start of Frame Interrupt" "XSTAFRM_0,XSTAFRM_1"
bitfld.long 0x1C 5. "XDATA,XMT Data Interrupt" "XDATA_0,XDATA_1"
bitfld.long 0x1C 4. "XLAST,XMT Last Slot Interrupt" "XLAST_0,XLAST_1"
bitfld.long 0x1C 3. "XDMAERR,XMT DMA Bus Error" "XDMAERR_0,XDMAERR_1"
bitfld.long 0x1C 2. "XCKFAIL,Bad Clock Interrupt" "XCKFAIL_0,XCKFAIL_1"
newline
bitfld.long 0x1C 1. "XSYNCERR,XMT Unexpected FSR Interrupt" "XSYNCERR_0,XSYNCERR_1"
bitfld.long 0x1C 0. "XUNDRN,XMT Underrun Interrupt" "XUNDRN_0,XUNDRN_1"
line.long 0x20 "MCASP_TXSTAT,"
bitfld.long 0x20 8. "XERR,XMT Error" "XERR_0,XERR_1"
bitfld.long 0x20 7. "XDMAERR,XMT DMA bus error" "XDMAERR_0,XDMAERR_1"
bitfld.long 0x20 6. "XSTAFRM,Start of Frame-XMT" "XSTAFRM_0,XSTAFRM_1"
bitfld.long 0x20 5. "XDATA,Data Ready Flag" "XDATA_0,XDATA_1"
bitfld.long 0x20 4. "XLAST,Last Slot Interrupt Flag" "XLAST_0,XLAST_1"
newline
bitfld.long 0x20 3. "XTDMSLOT,EvenOdd Slot" "XTDMSLOT_0,XTDMSLOT_1"
bitfld.long 0x20 2. "XCKFAIL,Bad Transmit Flag" "XCKFAIL_0,XCKFAIL_1"
bitfld.long 0x20 1. "XSYNCERR,Unexpected XMT Frame sync flag" "XSYNCERR_0,XSYNCERR_1"
bitfld.long 0x20 0. "XUNDRN,XMT Underrun Flag" "XUNDRN_0,XUNDRN_1"
line.long 0x24 "MCASP_TXTDMSLOT,"
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current XMT time slot count during reset the value of this register is 0b0101111111 [0x17f] and after reset 0"
line.long 0x28 "MCASP_TXCLKCHK,"
hexmask.long.byte 0x28 24.--31. 1. "XCNT,XMT clock count value"
hexmask.long.byte 0x28 16.--23. 1. "XMAX,XMT clock maximum boundary"
hexmask.long.byte 0x28 8.--15. 1. "XMIN,XMT clock minimum boundary"
bitfld.long 0x28 7. "RESV,Reserved" "RESV_0,RESV_1"
bitfld.long 0x28 0.--3. "XPS,XMT clock check prescaler" "XPS_0,XPS_1,XPS_2,XPS_3,XPS_4,XPS_5,XPS_6,XPS_7,XPS_8,XPS_9,XPS_10,XPS_11,XPS_12,XPS_13,XPS_14,XPS_15"
line.long 0x2C "MCASP_XEVTCTL,"
bitfld.long 0x2C 0. "XDATDMA,XMT data DMA request" "XDATDMA_0,XDATDMA_1"
line.long 0x30 "MCASP_CLKADJEN,"
bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "MCASP_RXBUF$1,"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "MCASP_TXBUF$1,"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "MCASP_XRSRCTL$1,"
rbitfld.long 0x00 5. "RRDY,Receive buffer ready" "RRDY_0,RRDY_1"
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready" "XRDY_0,XRDY_1"
newline
bitfld.long 0x00 2.--3. "DISMOD,Serializer drive state" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3"
bitfld.long 0x00 0.--1. "SRMOD,Serializer Mode" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "MCASP_DITUDRB$1,"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "MCASP_DITUDRA$1,"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "MCASP_DITCSRB$1,"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.long ($2+0x108)++0x03
line.long 0x00 "MCASP_DITCSRA$1,"
repeat.end
repeat 4. (list 0. 1. 4. 5. )(list 0x00 0x04 0x10 0x14 )
group.long ($2+0x100)++0x03
line.long 0x00 "MCASP_DITCSRA$1,"
repeat.end
tree.end
repeat.end
repeat 12. (increment 0 1) (increment ad:0x2B08000 0x10000)
tree "MCASP$1_DMA"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers"
group.long 0x00++0x03
line.long 0x00 "MCASP_TXBUF,Through the DATA port. the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers"
tree.end
repeat.end
tree.end
tree "MCSPI"
repeat 8. (increment 0 1) (increment ad:0x2100000 0x10000)
tree "MCSPI$1_CFG"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved"
bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "FFNBYTE_0,FFNBYTE_1,FFNBYTE_2,FFNBYTE_3,FFNBYTE_4,FFNBYTE_5,FFNBYTE_6,FFNBYTE_7,FFNBYTE_8,FFNBYTE_9,FFNBYTE_10,FFNBYTE_11,FFNBYTE_12,FFNBYTE_13,FFNBYTE_14,FFNBYTE_15,FFNBYTE_16,FFNBYTE_17,FFNBYTE_18,FFNBYTE_19,FFNBYTE_20,FFNBYTE_21,FFNBYTE_22,FFNBYTE_23,FFNBYTE_24,FFNBYTE_25,FFNBYTE_26,FFNBYTE_27,FFNBYTE_28,FFNBYTE_29,FFNBYTE_30,FFNBYTE_31"
newline
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "USEFIFO_0,USEFIFO_1"
group.long 0x10++0x03
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices"
hexmask.long 0x00 4.--31. 1. "RSVD,Reads returns 0"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1"
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
rgroup.long 0x100++0x03
line.long 0x00 "MCSPI_REVISION,This register contains the revision number"
group.long 0x110++0x73
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled" "ENAWAKEUP_0,ENAWAKEUP_1"
newline
bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running" "AUTOIDLE_0,AUTOIDLE_1"
line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "RESETDONE_0,RESETDONE_1"
line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "EOW_0,EOW_1"
bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "WKS_0,WKS_1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0,RX3_FULL_1"
newline
bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0,TX3_UNDERFLOW_1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0,TX3_EMPTY_1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0,RX2_FULL_1"
newline
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0,TX2_UNDERFLOW_1"
bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0,TX2_EMPTY_1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0,RX1_FULL_1"
newline
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0,TX1_UNDERFLOW_1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0,TX1_EMPTY_1"
bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0,RX0_OVERFLOW_1"
newline
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0,RX0_FULL_1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0,TX0_UNDERFLOW_1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0,TX0_EMPTY_1"
line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1"
bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "WKE_0,WKE_1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1"
newline
bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1"
newline
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1"
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bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1"
bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1"
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bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1"
line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis"
bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "WKEN_0,WKEN_1"
line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode"
bitfld.long 0x14 11. "SSB,Set status bit 0h (R/W) = No action" "SSB_0,SSB_1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1"
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bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1"
bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1"
bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value)" "SPICLK_0,SPICLK_1"
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bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "SPIDAT_1_0,SPIDAT_1_1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "SPIDAT_0_0,SPIDAT_0_1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value)" "SPIEN_3_0,SPIEN_3_1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value)" "SPIEN_2_0,SPIEN_2_1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value)" "SPIEN_1_0,SPIEN_1_1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value)" "SPIEN_0_0,SPIEN_0_1"
line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface"
bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers" "FDAA_0,FDAA_1"
bitfld.long 0x18 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "MOA_0,MOA_1"
bitfld.long 0x18 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,INITDLY_5,INITDLY_6,INITDLY_7"
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bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "SYSTEM_TEST_0,SYSTEM_TEST_1"
bitfld.long 0x18 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]" "MS_0,MS_1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select" "PIN34_0,PIN34_1"
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bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode" "SINGLE_0,SINGLE_1"
line.long 0x1C "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x1C 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x1C 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x1C 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x1C 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x1C 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x20 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x20 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x20 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x20 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x20 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x20 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x20 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x20 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x24 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x24 0. "EN,Channel enable 0h (R/W) = Channel i is not active" "0,1"
line.long 0x28 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is"
line.long 0x2C "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x30 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i"
bitfld.long 0x30 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x30 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x30 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x30 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x30 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x30 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x30 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x30 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x30 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x30 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x30 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x34 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x34 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x34 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x34 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x34 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x34 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x34 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x34 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x38 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x38 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active" "0,1"
line.long 0x3C "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is"
line.long 0x40 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x44 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x44 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x44 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x44 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x44 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x44 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x44 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x44 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x44 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x44 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x44 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x44 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x48 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x48 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x48 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x48 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x48 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x48 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x48 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x48 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x4C "MCSPI_CHCTRL_2,This register is dedicated to enable channel i"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x4C 0. "EN,Channel enable 0h (R/W) = Channel i is not active" "0,1"
line.long 0x50 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is"
line.long 0x54 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x58 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x58 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x58 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x58 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x58 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x58 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x58 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x58 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x58 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x58 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x58 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x58 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x5C "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x5C 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x5C 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x5C 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x5C 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x5C 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x5C 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x5C 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x60 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x60 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active" "0,1"
line.long 0x64 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is"
line.long 0x68 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x6C "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,SPI word counter"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer almost empty"
line.long 0x70 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit"
rgroup.long 0x1A0++0x03
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit"
tree.end
repeat.end
repeat 3. (increment 0 1) (increment ad:0x40300000 0x10000)
tree "MCU_MCSPI$1_CFG"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved"
bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter 1h (R) = FIFO 16 bytes depth 2h (R) = FIFO 32 bytes depth 4h (R) = FIFO 64 bytes depth 8h (R) = FIFO 128 bytes depth 10h (R) = FIFO 256 bytes depth" "FFNBYTE_0,FFNBYTE_1,FFNBYTE_2,FFNBYTE_3,FFNBYTE_4,FFNBYTE_5,FFNBYTE_6,FFNBYTE_7,FFNBYTE_8,FFNBYTE_9,FFNBYTE_10,FFNBYTE_11,FFNBYTE_12,FFNBYTE_13,FFNBYTE_14,FFNBYTE_15,FFNBYTE_16,FFNBYTE_17,FFNBYTE_18,FFNBYTE_19,FFNBYTE_20,FFNBYTE_21,FFNBYTE_22,FFNBYTE_23,FFNBYTE_24,FFNBYTE_25,FFNBYTE_26,FFNBYTE_27,FFNBYTE_28,FFNBYTE_29,FFNBYTE_30,FFNBYTE_31"
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bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: 0h (R) = FIFO not implemented in design 1h (R) = FIFO and its management implemented in design with depth defined by FFNBYTE generic" "USEFIFO_0,USEFIFO_1"
group.long 0x10++0x03
line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration Some of the MCSPI features described in this section may not be supported on this family of devices"
hexmask.long 0x00 4.--31. 1. "RSVD,Reads returns 0"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1"
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bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
rgroup.long 0x100++0x03
line.long 0x00 "MCSPI_REVISION,This register contains the revision number"
group.long 0x110++0x73
line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period 0h (R/W) = Interface and functional clocks may be switched off" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management 0h (R/W) = If an IDLE request is detected the MCSPI acknowledges it unconditionally and goes in inactive mode" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3"
bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control 0h (R/W) = Wake-up capability is disabled" "ENAWAKEUP_0,ENAWAKEUP_1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running" "AUTOIDLE_0,AUTOIDLE_1"
line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring 0h (R) = Internal module reset is ongoing 1h (R) = Reset completed" "RESETDONE_0,RESETDONE_1"
line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of MCSPI word defined by 0h (R/W) = Event false 1h (R/W) = Event status bit is reset" "EOW_0,EOW_1"
bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field 0h (R/W) = Event status bit unchanged 1h (R/W) = Event is pending" "WKS_0,WKS_1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0,RX3_FULL_1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0,TX3_UNDERFLOW_1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0,TX3_EMPTY_1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0,RX2_FULL_1"
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bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0,TX2_UNDERFLOW_1"
bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0,TX2_EMPTY_1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0,RX1_FULL_1"
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bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0,TX1_UNDERFLOW_1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0,TX1_EMPTY_1"
bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0,RX0_OVERFLOW_1"
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bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0,RX0_FULL_1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0,TX0_UNDERFLOW_1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0,TX0_EMPTY_1"
line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1"
bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = Interrupt disabled 1h (R/W) = Interrupt enabled" "WKE_0,WKE_1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1"
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bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1"
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bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1"
bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1"
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bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1"
line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis"
bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the 0h (R/W) = The event is not allowed to wake-up the system even if the global control bit 1h (R/W) = The event is allowed to wake-up.." "WKEN_0,WKEN_1"
line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode"
bitfld.long 0x14 11. "SSB,Set status bit 0h (R/W) = No action" "SSB_0,SSB_1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1"
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bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1"
bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1"
bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value)" "SPICLK_0,SPICLK_1"
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bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value)" "SPIDAT_1_0,SPIDAT_1_1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value)" "SPIDAT_0_0,SPIDAT_0_1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value)" "SPIEN_3_0,SPIEN_3_1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value)" "SPIEN_2_0,SPIEN_2_1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value)" "SPIEN_1_0,SPIEN_1_1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value)" "SPIEN_0_0,SPIEN_0_1"
line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface"
bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned 0h (R/W) = FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers" "FDAA_0,FDAA_1"
bitfld.long 0x18 7. "MOA,Multiple word configuration interface access: 0h (R/W) = Multiple word access disabled 1h (R/W) = Multiple word access enabled with FIFO" "MOA_0,MOA_1"
bitfld.long 0x18 4.--6. "INITDLY,Initial MCSPI delay for first transfer: 0h (R/W) = No delay for first MCSPI transfer" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,INITDLY_5,INITDLY_6,INITDLY_7"
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bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode 0h (R/W) = Functional mode 1h (R/W) = System test mode (SYSTEST)" "SYSTEM_TEST_0,SYSTEM_TEST_1"
bitfld.long 0x18 2. "MS,Master/slave 0h (R/W) = Master - The module generates the SPICLK and SPIEN[3:0]" "MS_0,MS_1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: 0h (R/W) = SPIEN is used as a chip-select" "PIN34_0,PIN34_1"
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bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only) 0h (R/W) = More than one channel will be used in master mode" "SINGLE_0,SINGLE_1"
line.long 0x1C "MCSPI_CHCONF_0,This register is dedicated to the configuration of the channel i"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x1C 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x1C 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x1C 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x1C 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x1C 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x20 "MCSPI_CHSTAT_0,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x20 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x20 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x20 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x20 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x20 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x20 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x20 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x24 "MCSPI_CHCTRL_0,This register is dedicated to enable channel i"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x24 0. "EN,Channel enable 0h (R/W) = Channel i is not active" "0,1"
line.long 0x28 "MCSPI_TX_0,This register contains a single MCSPI word for channel ito transmit on the serial link. whatever MCSPI word length is"
line.long 0x2C "MCSPI_RX_0,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x30 "MCSPI_CHCONF_1,This register is dedicated to the configuration of the channel i"
bitfld.long 0x30 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x30 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x30 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x30 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x30 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x30 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x30 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x30 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x30 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x30 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x30 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x34 "MCSPI_CHSTAT_1,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x34 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x34 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x34 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x34 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x34 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x34 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x34 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x38 "MCSPI_CHCTRL_1,This register is dedicated to enable channel i"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x38 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active" "0,1"
line.long 0x3C "MCSPI_TX_1,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is"
line.long 0x40 "MCSPI_RX_1,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x44 "MCSPI_CHCONF_2,This register is dedicated to the configuration of the channel i"
bitfld.long 0x44 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x44 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x44 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x44 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x44 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x44 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x44 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x44 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x44 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x44 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x44 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x44 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x48 "MCSPI_CHSTAT_2,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x48 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x48 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x48 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x48 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x48 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x48 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x48 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x4C "MCSPI_CHCTRL_2,This register is dedicated to enable channel i"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x4C 0. "EN,Channel enable 0h (R/W) = Channel i is not active" "0,1"
line.long 0x50 "MCSPI_TX_2,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is"
line.long 0x54 "MCSPI_RX_2,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x58 "MCSPI_CHCONF_3,This register is dedicated to the configuration of the channel i"
bitfld.long 0x58 29. "CLKG,Clock divider granularity 0h (R/W) = Clock granularity of power of 2 1h (R/W) = One clock cycle granularity" "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "0,1"
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bitfld.long 0x58 25.--26. "TCS0,Chip-select time control 0h (R/W) = 0.5 clock cycle 1h (R/W) = 1.5 clock cycles 2h (R/W) = 2.5 clock cycles 3h (R/W) = 3.5 clock cycles" "0,1,2,3"
bitfld.long 0x58 24. "SBPOL,Start-bit polarity 0h (R/W) = Start-bit polarity is held to 0 during MCSPI transfer" "0,1"
bitfld.long 0x58 23. "SBE,Start-bit enable for MCSPI transfer 0h (R/W) = Default MCSPI transfer length as specified by WL bit field 1h (R/W) = Start bit D/CX added before MCSPI transfer polarity is defined by" "0,1"
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bitfld.long 0x58 21.--22. "SPIENSLV,Channel 0 only and slave mode only: MCSPI slave select signal detection" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between MCSPI words (single channel master mode only)" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode 0h (R/W) = Turbo is deactivated (recommended for single MCSPI word transfer)" "0,1"
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bitfld.long 0x58 18. "IS,Input Select 0h (R/W) = Data line 0 (SPIDAT[0]) selected for reception 1h (R/W) = Data line 1 (SPIDAT[1]) selected for reception" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission enable for data line 1 0h (R/W) = Data line 1 (SPIDAT[1]) selected for transmission 1h (R/W) = No transmission on Data Line1 (SPIDAT[1])" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 0h (R/W) = Data Line0 (SPIDAT[0]) selected for transmission 1h (R/W) = No transmission on data line 0 (SPIDAT[0])" "0,1"
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bitfld.long 0x58 15. "DMAR,DMA read request 0h (R/W) = DMA read request disabled 1h (R/W) = DMA read request enabled" "0,1"
bitfld.long 0x58 14. "DMAW,DMA write request" "0,1"
bitfld.long 0x58 12.--13. "TRM,Transmit/receive modes 0h (R/W) = Transmit-and-receive mode 1h (R/W) = Receive-only mode 2h (R/W) = Transmit-only mode 3h (R/W) = Reserved" "0,1,2,3"
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bitfld.long 0x58 7.--11. "WL,SPI word length 0h (R/W) = Reserved 1h (R/W) = Reserved 2h (R/W) = Reserved 3h (R/W) = The MCSPI word is 4 bits long 4h (R/W) = The MCSPI word is 5 bits long 5h (R/W) = The MCSPI word is 6 bits long 6h (R/W) = The MCSPI word is 7 bits long 7h (R/W) =.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity 0h (R/W) = SPIEN is held high during the ACTIVE state" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master MCSPI device)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x58 1. "POL,SPICLK polarity (see 0h (R/W) = SPICLK is held low during the INACTIVE state 1h (R/W) = SPICLK is held high during the INACTIVE state" "0,1"
bitfld.long 0x58 0. "PHA,SPICLK phase (see 0h (R/W) = Data are latched on odd-numbered edges of SPICLK. 1h (R/W) = Data are latched on even-numbered edges of SPICLK" "0,1"
line.long 0x5C "MCSPI_CHSTAT_3,This register provides status information about transmitter and receiver registers of channel i"
bitfld.long 0x5C 6. "RXFFF,Channel i FIFO receive buffer full status 0h (R) = FIFO receive buffer is not full 1h (R) = FIFO receive buffer is full" "0,1"
bitfld.long 0x5C 5. "RXFFE,Channel i FIFO receive buffer empty status 0h (R) = FIFO receive buffer is not empty 1h (R) = FIFO receive buffer is empty" "0,1"
bitfld.long 0x5C 4. "TXFFF,Channel i FIFO transmit buffer full status 0h (R) = FIFO transmit buffer is not full 1h (R) = FIFO transmit buffer is full" "0,1"
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bitfld.long 0x5C 3. "TXFFE,Channel i FIFO transmit buffer empty status 0h (R) = FIFO transmit buffer is not empty 1h (R) = FIFO transmit buffer is empty" "0,1"
bitfld.long 0x5C 2. "EOT,Channel i end of transfer status" "0,1"
bitfld.long 0x5C 1. "TXS,Channel i transmitter register status 0h (R) = Register is full" "0,1"
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bitfld.long 0x5C 0. "RXS,Channel i receiver register status 0h (R) = Register is empty" "0,1"
line.long 0x60 "MCSPI_CHCTRL_3,This register is dedicated to enable channel i"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: 0h (R/W) = Clock ratio is CLKD + 1"
bitfld.long 0x60 0. "EN,Channel enable 0h (R/W) = Channel 'i' is not active" "0,1"
line.long 0x64 "MCSPI_TX_3,This register contains a single MCSPI word for channel i to transmit on the serial link. whatever MCSPI word length is"
line.long 0x68 "MCSPI_RX_3,This register contains a single MCSPI word for channel i received through the serial link. whatever MCSPI word length is"
line.long 0x6C "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,SPI word counter"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer almost full 0h (R/W) = 1 byte 1h (R/W) = 2 bytes FEh (R/W) = 255bytes FFh (R/W) = 256bytes"
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer almost empty"
line.long 0x70 "MCSPI_DAFTX,This register contains the MCSPI words to be transmitted on the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit"
rgroup.long 0x1A0++0x03
line.long 0x00 "MCSPI_DAFRX,This register contains the MCSPI words received from the MCSPI bus when FIFO is used and DMA address is aligned on 256 bit"
tree.end
repeat.end
tree.end
tree "MCU_CPSW0_ALE"
tree "MCU_CPSW0_NUSS_ALE"
base ad:0x46000000
rgroup.long 0x3E000++0x17
line.long 0x00 "CPSW_ALE_MOD_VER,The Module and Version Register identifies the module identifier of the ALE_2g64i module"
hexmask.long.word 0x00 16.--31. 1. "MODULE_ID,ALE module ID"
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bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_ALE_STATUS,The ALE status provides information on the ALE configuration and state"
hexmask.long.byte 0x04 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8.A value of 4 indicates 32 policer engines total"
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bitfld.long 0x04 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both RAMDEPTH128 and RAMDEPTH32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both RAMDEPTH128 and RAMDEPTH32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 0.--4. "KLUENTRIES,This is the number of table entries total divided by 1024.A value of 1h indicates 1024 table entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports"
bitfld.long 0x08 31. "ENABLE_ALE,Enable" "0,1"
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bitfld.long 0x08 30. "CLEAR_TABLE,Clear ALE address table" "0,1"
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bitfld.long 0x08 29. "AGE_OUT_NOW,Age Out Address Table Now" "0,1"
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bitfld.long 0x08 24. "MIRROR_DP,Mirror Destination Port" "0,1"
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bitfld.long 0x08 21.--23. "UPD_BW_CTRL,The UPD_BW_CTRL field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur.At frequencies of 350Mhz the table update rate should be at it lowest or 5 Million updates per second" "350Mhz 5M,359Mhz 11M,367Mhz 16M,375Mhz 22M,384Mhz 28M,392Mhz 34M,400Mhz 39M,409Mhz 45M"
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bitfld.long 0x08 16. "MIRROR_TOP,Mirror To Port" "0,1"
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bitfld.long 0x08 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable.When clear this bit will prevent any static entry (agable bit clear) from being updated due to port change" "0,1"
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bitfld.long 0x08 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn" "0,1"
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bitfld.long 0x08 12. "MIRROR_MEN,Mirror Match Entry Enable" "0,1"
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bitfld.long 0x08 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option.When this bit is set any traffic destined for the ~imirror_dp port will have its transmit traffic also sent to the ~imirror_top port" "0,1"
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bitfld.long 0x08 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option.When this bit is set any port with the Iy_REG_P0_MIRROR_SP set in the CPSW_Iy_ALE_PORTCTL0_y registers set will have its received traffic also sent to the MIRROR_TOP.." "0,1"
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bitfld.long 0x08 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host.0h = Unknown unicast packets are not sent to the host.1h = Unknown unicast packets flood to host port as well as other ports" "0,1"
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bitfld.long 0x08 7. "LEARN_NO_VLANID,Learn No VID.0h = VID is learned with the source" "0,1"
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bitfld.long 0x08 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode0h = Process the priority tagged packet with VID = PORT_VLAN[11:0]" "0,1"
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bitfld.long 0x08 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode.0h = Any packet source address matching an OUI address table entry will be dropped to the host unless the destination address matches with a supervisory destination address table" "0,1"
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bitfld.long 0x08 4. "ENABLE_BYPASS,ALE Bypass" "No bypass,Bypass the ALE"
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bitfld.long 0x08 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode.0h = Broadcast and multicast rate limit counters are received port" "0,1"
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bitfld.long 0x08 2. "ALE_VLAN_AWARE,ALE VLAN Aware" "0,1"
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bitfld.long 0x08 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode"
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bitfld.long 0x08 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit0h = Broadcast/Multicast rates not limited" "0,1"
line.long 0x0C "CPSW_ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports"
bitfld.long 0x0C 31. "TRK_EN_DST,Trunk Enable Destination Address.This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 30. "TRK_EN_SRC,Trunk Enable Source Address.This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 29. "TRK_EN_PRI,Trunk Enable Priority.This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN.This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 25. "TRK_EN_SIP,Trunk Enable Source IP Address.This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 24. "TRK_EN_DIP,Trunk Enable Destination IP Address.This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet.Ethertypes 0-1500 are 802.3 lengths all others are Ether types" "0,1"
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bitfld.long 0x0C 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set" "0,1"
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bitfld.long 0x0C 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found" "0,1"
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bitfld.long 0x0C 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match theCPSW_ALE_NXT_HDR register values" "0,1"
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bitfld.long 0x0C 16.--18. "TRK_BASE,Trunk Base" "?,00000000,01010101,02102102,03210321,?..."
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bitfld.long 0x0C 0.--5. "MIRROR_MIDX,Mirror Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "CPSW_ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value"
hexmask.long.tbyte 0x10 0.--19. 1. "ALE_PRESCALE,ALE Prescale"
line.long 0x14 "CPSW_ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur"
bitfld.long 0x14 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable.When set will divide the aging interval by 1000" "0,1"
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bitfld.long 0x14 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable" "0,1"
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hexmask.long.tbyte 0x14 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer"
group.long 0x3E01C++0x07
line.long 0x00 "CPSW_ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header"
hexmask.long.byte 0x00 24.--31. 1. "IP_NXT_HDR3,The IP_NXT_HDR3 is the forth protocol or next header compared when enabled"
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hexmask.long.byte 0x00 16.--23. 1. "IP_NXT_HDR2,The IP_NXT_HDR2 is the third protocol or next header compared when enabled"
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hexmask.long.byte 0x00 8.--15. 1. "IP_NXT_HDR1,The IP_NXT_HDR1 is the second protocol or next header compared when enabled"
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hexmask.long.byte 0x00 0.--7. 1. "IP_NXT_HDR0,The IP_NXT_HDR0 is the first protocol or next header compared when enabled"
line.long 0x04 "CPSW_ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries"
bitfld.long 0x04 31. "TABLEWR,Table" "0,1"
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bitfld.long 0x04 0.--5. "TABLEIDX,The table index is used to determine which lookup table entry is read or written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E034++0x0F
line.long 0x00 "CPSW_ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry"
hexmask.long.byte 0x00 0.--6. 1. "TABLEWRD2,Table Entry bits [71-64]"
line.long 0x04 "CPSW_ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry"
line.long 0x08 "CPSW_ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry"
line.long 0x0C "CPSW_Iy_ALE_PORTCTL0_y,The ALE Port Control Register sets the port specific modes of operation"
hexmask.long.byte 0x0C 24.--31. 1. "Iy_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter.The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.."
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hexmask.long.byte 0x0C 16.--23. 1. "Iy_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter.The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.."
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bitfld.long 0x0C 15. "Iy_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN.When set cause any received packet with double VLANs to be dropped" "0,1"
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bitfld.long 0x0C 14. "Iy_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN" "0,1"
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bitfld.long 0x0C 13. "Iy_REG_P0_MACONLY_CAF,Mac Only Copy All Frames.When set a Mac Only port will transfer all received good frames to the host" "0,1"
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bitfld.long 0x0C 12. "Iy_REG_P0_DIS_PAUTHMOD,Disable Port authorization" "0,1"
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bitfld.long 0x0C 11. "Iy_REG_P0_MACONLY,MAC Only.When set enables this port be treated like a MAC port for the host" "0,1"
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bitfld.long 0x0C 10. "Iy_REG_P0_TRUNKEN,Trunk Enable" "0,1"
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bitfld.long 0x0C 8.--9. "Iy_REG_P0_TRUNKNUM,Trunk Number" "0,1,2,3"
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bitfld.long 0x0C 7. "Iy_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option.When this bit is set any traffic received on the port with the Iy_REG_P0_MIRROR_SP bit set will have its received traffic also sent to the MIRROR_TOP port" "0,1"
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bitfld.long 0x0C 5. "Iy_REG_P0_NO_SA_UPDATE,No Source Address Update.When set will not update the source addresses for this port" "0,1"
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bitfld.long 0x0C 4. "Iy_REG_P0_NO_LEARN,No Learn.When set will not learn the source addresses for this port" "0,1"
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bitfld.long 0x0C 3. "Iy_REG_P0_VID_INGRESS_CHECK,VLAN Ingress Check.When set if a packet received is not a member of the VLAN the packet will be dropped" "0,1"
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bitfld.long 0x0C 2. "Iy_REG_P0_DROP_UN_TAGGED,If Drop Untagged" "0,1"
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bitfld.long 0x0C 0.--1. "Iy_REG_P0_PORTSTATE,Port State" "?,Blocked,Learning,Forwarding"
group.long 0x3E090++0x0F
line.long 0x00 "CPSW_ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID"
bitfld.long 0x00 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List" "0,1,2,3"
line.long 0x04 "CPSW_ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x04 0.--1. "UVLAN_UNREG_MCAST_FLOOD_MASK,Unknown VLAN Unregister Multicast Flood Mask" "0,1,2,3"
line.long 0x08 "CPSW_ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x08 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask" "0,1,2,3"
line.long 0x0C "CPSW_ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed"
bitfld.long 0x0C 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask" "0,1,2,3"
group.long 0x3E0B8++0x0F
line.long 0x00 "CPSW_ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters"
bitfld.long 0x00 15. "PBCAST_DIAG,When set and the PORT_DIAG is set to zero will allow all ports to see the same stat diagnostic increment" "0,1"
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bitfld.long 0x00 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1"
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bitfld.long 0x00 0.--3. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received.For the selected Port" "Disabled,Destination Equal Source Drop Stat will count,VLAN Ingress Check Drop Stat will count,Source Multicast Drop Stat will count,Dual VLAN Drop Stat will count,Ether Type length error Drop Stat will count,Next Hop Limit Drop Stat will count,IPv4 Fragment Drop Stat will count,Classifier Hit Stat will count,Classifier Red Drop Stat will count,?..."
line.long 0x04 "CPSW_ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port"
bitfld.long 0x04 0.--1. "OAM_LB_CTRL,The OAM_LB_CTRL bit field allows any port to be put into OAM loopback that is any packet received will be returned to the same port with anCPSW_ALE_EGRESSOP[31-24] EGRESS_OP of 0xFF which swaps the source (SA) and destination address (DA)" "0,1,2,3"
line.long 0x08 "CPSW_ALE_MSK_MUX0,VLAN Mask Mux 0"
bitfld.long 0x08 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux 0" "0,1,2,3"
line.long 0x0C "CPSW_Ix_ALE_MSK_MUXx,VLAN Mask Mux x (where x = 1 to 3)"
bitfld.long 0x0C 0.--1. "Ix_REG_VLAN_MASK_MUX_x,VLAN Mask Mux x (where x = 1 to 3)" "0,1,2,3"
group.long 0x3E0FC++0x17
line.long 0x00 "CPSW_ALE_EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions"
hexmask.long.byte 0x00 24.--31. 1. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations0h = NOP"
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bitfld.long 0x00 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well.The DA SA and VLAN are ignored for trunk generation on InterVLAN Routing so that this field is the.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions.The packet will be routed to the host it was destined to" "0,1"
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bitfld.long 0x00 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to.If a destination is a Trunk all the port bits for that trunck must be set" "0,1,2,3"
line.long 0x04 "CPSW_ALE_POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching"
bitfld.long 0x04 31. "PORT_MEN,Port Match Enable" "0,1"
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bitfld.long 0x04 30. "TRUNKID,Trunk ID" "0,1"
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bitfld.long 0x04 25. "PORT_NUM,Port Number" "0,1"
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bitfld.long 0x04 19. "PRI_MEN,Priority Match Enable" "0,1"
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bitfld.long 0x04 16.--18. "PRI_VAL,Priority Value" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 15. "ONU_MEN,OUI Match Enable" "0,1"
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bitfld.long 0x04 0.--5. "ONU_INDEX,OUI Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CPSW_ALE_POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses"
bitfld.long 0x08 31. "DST_MEN,Destination Address Match Enable" "0,1"
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bitfld.long 0x08 16.--21. "DST_INDEX,Destination Address Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 15. "SRC_MEN,Source Address Match Enable" "0,1"
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bitfld.long 0x08 0.--5. "SRC_INDEX,Source Address Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CPSW_ALE_POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses"
bitfld.long 0x0C 31. "OVLAN_MEN,Outer VLAN Match Enable" "0,1"
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bitfld.long 0x0C 16.--21. "OVLAN_INDEX,Outer VLAN Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 15. "IVLAN_MEN,Inner VLAN Match Enable" "0,1"
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bitfld.long 0x0C 0.--5. "IVLAN_INDEX,Inner VLAN Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "CPSW_ALE_POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address"
bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable" "0,1"
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bitfld.long 0x10 16.--21. "ETHERTYPE_INDEX,EtherType Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable" "0,1"
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bitfld.long 0x10 0.--5. "IPSRC_INDEX,IP Source Address Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "CPSW_ALE_POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address"
bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable" "0,1"
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bitfld.long 0x14 16.--21. "IPDST_INDEX,IP Destination Address Table Entry Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3E118++0x17
line.long 0x00 "CPSW_ALE_POLICECFG6,The PIR counter is a 37 bit internal counter where PIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time"
line.long 0x04 "CPSW_ALE_POLICECFG7,The CIR counter is a 37 bit internal counter where CIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time"
line.long 0x08 "CPSW_ALE_POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry"
bitfld.long 0x08 31. "WRITE_ENABLE,Write Enable" "0,1"
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bitfld.long 0x08 0.--2. "POL_TBL_IDX,Policer Entry Index" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPSW_ALE_POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules"
bitfld.long 0x0C 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities" "0,1"
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bitfld.long 0x0C 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets" "0,1"
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bitfld.long 0x0C 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the YELLOWTHRESH bit value.This field would normally not be used as to let the switch drop packets at a buffer threshold instead" "0,1"
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bitfld.long 0x0C 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the YELLOW_DROP_EN bit" "?,?,33%,25%,20%,17%,14%,13%"
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bitfld.long 0x0C 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier" "?,No Hit packets are marked YELLOW,No Hit packets are marked RED,No Hit packets are marked based on.."
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bitfld.long 0x0C 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled" "0,1"
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bitfld.long 0x0C 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports.That is the default thread will be {port priority}" "0,1"
line.long 0x10 "CPSW_ALE_POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition"
bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits.This bit is self clearing" "0,1"
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bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits.This bit is self clearing" "0,1"
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bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits.This bit is self clearing" "0,1"
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bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits.This bit is self clearing" "0,1"
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bitfld.long 0x10 0.--2. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written" "0,1,2,3,4,5,6,7"
line.long 0x14 "CPSW_ALE_POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier"
bitfld.long 0x14 31. "POL_HIT,Policer Hit" "0,1"
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bitfld.long 0x14 30. "POL_REDHIT,Policer Hit RED" "0,1"
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bitfld.long 0x14 29. "POL_YELLOWHIT,Policer Hit YELLOW" "0,1"
group.long 0x3E134++0x0B
line.long 0x00 "CPSW_ALE_THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched"
bitfld.long 0x00 15. "DEFTHREAD_EN,Default Tread Enable" "0,1"
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bitfld.long 0x00 0.--5. "DEFTHREADVAL,Default Thread Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_ALE_THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host"
bitfld.long 0x04 0.--2. "CLASSINDEX,Classifier Index" "0,1,2,3,4,5,6,7"
line.long 0x08 "CPSW_ALE_THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry"
bitfld.long 0x08 15. "THREAD_EN,Thread Enable" "0,1"
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bitfld.long 0x08 0.--5. "THREADVAL,Thread Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "MCU_CPSW0_CONTROL"
tree "MCU_CPSW0_NUSS_CONTROL"
base ad:0x46000000
rgroup.long 0x20000++0x07
line.long 0x00 "CPSW_CPSW_ID_VER_REG,CPSW ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification Value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_VER,Minor Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_CONTROL_REG,CPSW Switch Control Register"
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
bitfld.long 0x04 18. "EST_ENABLE,Enhanced Scheduled Traffic enable (EST)" "0,1"
bitfld.long 0x04 17. "IET_ENABLE,Intersperced Express Traffic enable (IET)" "0,1"
bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
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bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
bitfld.long 0x04 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
bitfld.long 0x04 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
bitfld.long 0x04 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
bitfld.long 0x04 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
bitfld.long 0x04 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
bitfld.long 0x04 0. "S_CN_SWITCH,Service or Customer VLAN switch" "0,1"
group.long 0x20010++0x37
line.long 0x00 "CPSW_EM_CONTROL_REG,CPSW Emulation Control Register"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "CPSW_STAT_PORT_EN_REG,CPSW Statistics Port Enable Register"
bitfld.long 0x04 8. "P8_STAT_EN,Port 8 Statistics Enable (if N > 8)" "0,1"
bitfld.long 0x04 7. "P7_STAT_EN,Port 7 Statistics Enable (if N > 7)" "0,1"
bitfld.long 0x04 6. "P6_STAT_EN,Port 6 Statistics Enable (if N > 6)" "0,1"
bitfld.long 0x04 5. "P5_STAT_EN,Port 5 Statistics Enable (if N > 5)" "0,1"
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bitfld.long 0x04 4. "P4_STAT_EN,Port 4 Statistics Enable (if N > 4)" "0,1"
bitfld.long 0x04 3. "P3_STAT_EN,Port 3 Statistics Enable (if N > 3)" "0,1"
bitfld.long 0x04 2. "P2_STAT_EN,Port 2 Statistics Enable (if N > 2)" "0,1"
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
newline
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x08 "CPSW_PTYPE_REG,CPSW Transmit Priority Type Register"
bitfld.long 0x08 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate (if N > 8)" "0,1"
bitfld.long 0x08 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate (if N > 7)" "0,1"
bitfld.long 0x08 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate (if N > 6)" "0,1"
bitfld.long 0x08 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate (if N > 5)" "0,1"
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bitfld.long 0x08 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate (if N > 4)" "0,1"
bitfld.long 0x08 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate (if N > 3)" "0,1"
bitfld.long 0x08 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate (if N > 2)" "0,1"
bitfld.long 0x08 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
bitfld.long 0x08 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_SOFT_IDLE_REG,CPSW Software Idle"
bitfld.long 0x0C 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "CPSW_THRU_RATE_REG,CPSW Thru Rate Register"
bitfld.long 0x10 12.--15. "SL_RX_THRU_RATE,Ethernet Port Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "P0_RX_THRU_RATE,CPPI FIFO (port 0) receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CPSW_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold Register"
bitfld.long 0x14 0.--4. "GAP_THRESH,Ethernet Port Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "CPSW_TX_START_WDS_REG,CPSW Transmit FIFO Start Words Register"
hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words"
line.long 0x1C "CPSW_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value Register"
hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x20 "CPSW_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x20 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "CPSW_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear Register"
bitfld.long 0x24 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "CPSW_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low Register"
hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x2C "CPSW_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High Register"
hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x30 "CPSW_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low Register"
hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x34 "CPSW_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High Register"
hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x07
line.long 0x00 "CPSW_VLAN_LTYPE_REG,VLAN LTYPE Outer and Inner Register"
hexmask.long.word 0x00 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LTYPE"
hexmask.long.word 0x00 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LTYPE"
line.long 0x04 "CPSW_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain Register"
hexmask.long.byte 0x04 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
group.long 0x20100++0x1F
line.long 0x00 "CPSW_TX_PRI0_MAXLEN_REG,Priority 0 Maximum Transmit Packet Length Register"
hexmask.long.word 0x00 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Packet Length"
line.long 0x04 "CPSW_TX_PRI1_MAXLEN_REG,Priority 1 Maximum Transmit Packet Length Register"
hexmask.long.word 0x04 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Packet Length"
line.long 0x08 "CPSW_TX_PRI2_MAXLEN_REG,Priority 2 Maximum Transmit Packet Length Register"
hexmask.long.word 0x08 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Packet Length"
line.long 0x0C "CPSW_TX_PRI3_MAXLEN_REG,Priority 3 Maximum Transmit Packet Length Register"
hexmask.long.word 0x0C 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Packet Length"
line.long 0x10 "CPSW_TX_PRI4_MAXLEN_REG,Priority 4 Maximum Transmit Packet Length Register"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Packet Length"
line.long 0x14 "CPSW_TX_PRI5_MAXLEN_REG,Priority 5 Maximum Transmit Packet Length Register"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Packet Length"
line.long 0x18 "CPSW_TX_PRI6_MAXLEN_REG,Priority 6 Maximum Transmit Packet Length Register"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Packet Length"
line.long 0x1C "CPSW_TX_PRI7_MAXLEN_REG,Priority 7 Maximum Transmit Packet Length Register"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Packet Length"
group.long 0x21004++0x07
line.long 0x00 "CPSW_P0_CONTROL_REG,CPPI Port 0 Control Register"
bitfld.long 0x00 18. "RX_REMAP_DSCP_V6,Port 0 receive remap thread to DSCP IPV6 priority" "0,1"
bitfld.long 0x00 17. "RX_REMAP_DSCP_V4,Port 0 receive remap thread to DSCP IPV6 priority" "0,1"
bitfld.long 0x00 16. "RX_REMAP_VLAN,Port 0 receive remap thread to VLAN" "0,1"
bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port 0 receive ECC Error Enable" "0,1"
newline
bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port 0 transmit ECC Error Enable" "0,1"
bitfld.long 0x00 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
bitfld.long 0x00 1. "DSCP_IPV4_EN,Port 0 IPV4 DSCP enable" "0,1"
bitfld.long 0x00 0. "RX_CHECKSUM_EN,Port 0 Receive (port 0 ingress) Checksum Enable" "0,1"
line.long 0x04 "CPSW_P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Transmit FLOW ID Offset Register"
hexmask.long.word 0x04 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
rgroup.long 0x21010++0x1B
line.long 0x00 "CPSW_P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count Register"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "RX_BLK_CNT,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_P0_PORT_VLAN_REG,CPPI Port 0 VLAN Register"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "CPSW_P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPSW_P0_PRI_CTL_REG,CPPI Port 0 Priority Control Register"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
bitfld.long 0x0C 8. "RX_PTYPE,Receive Priority Type" "0,1"
line.long 0x10 "CPSW_P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "CPSW_P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length"
line.long 0x18 "CPSW_P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority Register"
bitfld.long 0x18 28.--31. "PRI7,Port Transmit Blocks Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "PRI6,Port Transmit Blocks Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 20.--23. "PRI5,Port Transmit Blocks Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "PRI4,Port Transmit Blocks Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Port Transmit Blocks Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "PRI2,Port Transmit Blocks Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "PRI1,Port Transmit Blocks Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PRI0,Port Transmit Blocks Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21030++0x0F
line.long 0x00 "CPSW_P0_IDLE2LPI_REG,CPPI Port 0 EEE Idle to LPI Count Register"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value"
line.long 0x04 "CPSW_P0_LPI2WAKE_REG,CPPI Port 0 EEE LPI to Wakeup Count Register"
hexmask.long.tbyte 0x04 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value"
line.long 0x08 "CPSW_P0_EEE_STATUS_REG,CPPI Port 0 EEE Port Status Register"
bitfld.long 0x08 6. "TX_FIFO_EMPTY,Port 0 Transmit FIFO packet count zero" "0,1"
bitfld.long 0x08 5. "RX_FIFO_EMPTY,Port 0 Receive FIFO packet count zero" "0,1"
bitfld.long 0x08 4. "TX_FIFO_HOLD,Port 0 Transmit FIFO hold" "0,1"
bitfld.long 0x08 3. "TX_WAKE,Port 0 Receive Wake Time" "0,1"
newline
bitfld.long 0x08 2. "TX_LPI,Port 0 LPI" "0,1"
bitfld.long 0x08 1. "RX_LPI,Port 0 LPI" "0,1"
bitfld.long 0x08 0. "WAIT_IDLE2LPI,Transmit Wait Idle to LPI" "0,1"
line.long 0x0C "CPSW_P0_RX_PKTS_PRI_REG,CPPI Port 0 Receive Packets Per Priority Register"
bitfld.long 0x0C 28.--31. "PRI7,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 24.--27. "PRI6,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 20.--23. "PRI5,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 16.--19. "PRI4,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 12.--15. "PRI3,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "PRI2,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "PRI1,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "PRI0,Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2104C++0x07
line.long 0x00 "CPSW_P0_RX_GAP_REG,CPPI Port 0 Receive Gap Register"
hexmask.long.word 0x00 16.--25. 1. "RX_GAP_CNT,Receive Gap Count"
hexmask.long.byte 0x00 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable"
line.long 0x04 "CPSW_P0_FIFO_STATUS_REG,Port 0 FIFO Status"
hexmask.long.byte 0x04 0.--7. 1. "TX_PRI_ACTIVE,Port 0 Transmit FIFO Priority Active"
group.long 0x21120++0x03
line.long 0x00 "CPSW_P0_RX_DSCP_MAP_REG_y,CPPI Port 0 Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
group.long 0x21140++0x03
line.long 0x00 "CPSW_P0_PRI_CIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Committed Information Rate Registers"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority 'y' Committed Information Rate Count Value"
group.long 0x21160++0x03
line.long 0x00 "CPSW_P0_PRI_EIR_REG_y,CPPI Port 0 Rx Priority 0 to Priority 7 Excess Information Rate Registers"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority 'y' Excess Information Rate Count Value"
group.long 0x21180++0x1F
line.long 0x00 "CPSW_P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CPSW_P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "CPSW_P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CPSW_P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "CPSW_P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "CPSW_P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21300++0x03
line.long 0x00 "CPSW_P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
hexmask.long.byte 0x00 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
group.long 0x21320++0x03
line.long 0x00 "CPSW_P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
bitfld.long 0x00 28.--31. "PRI7,Host Blocks Per Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PRI6,Host Blocks Per Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "PRI5,Host Blocks Per Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PRI4,Host Blocks Per Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PRI3,Host Blocks Per Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PRI2,Host Blocks Per Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "PRI1,Host Blocks Per Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PRI0,Host Blocks Per Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x22000++0x03
hide.long 0x00 "CPSW_PN_RESERVED_REG,Reserved"
group.long 0x22004++0x07
line.long 0x00 "CPSW_PN_CONTROL_REG,Enet Port N Control"
bitfld.long 0x00 17. "EST_PORT_EN,EST Port Enable" "0,1"
bitfld.long 0x00 16. "IET_PORT_EN,Intersperced Express Traffic (IET) Port Enable" "0,1"
bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port N receive ECC Error Enable" "0,1"
bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port N transmit ECC Error Enable" "0,1"
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bitfld.long 0x00 12. "TX_LPI_CLKSTOP_EN,Transmit LPI Clock Stop Enable" "0,1"
bitfld.long 0x00 2. "DSCP_IPV6_EN,IPV6 DSCP enable" "0,1"
bitfld.long 0x00 1. "DSCP_IPV4_EN,IPV4 DSCP enable" "0,1"
line.long 0x04 "CPSW_PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
hexmask.long.byte 0x04 8.--15. 1. "TX_MAX_BLKS,Transmit Max Blocks"
hexmask.long.byte 0x04 0.--7. 1. "RX_MAX_BLKS,Receive Max Blocks"
rgroup.long 0x22010++0x2B
line.long 0x00 "CPSW_PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count"
bitfld.long 0x00 16.--21. "RX_BLK_CNT_P,Receive Express Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "RX_BLK_CNT_E,Receive Express Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_PN_PORT_VLAN_REG,Enet Port N VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "CPSW_PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPSW_PN_PRI_CTL_REG,Enet Port N Priority Control"
hexmask.long.byte 0x0C 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
bitfld.long 0x0C 12.--15. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CPSW_PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "CPSW_PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length"
line.long 0x18 "CPSW_PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Transmit Blocks Per Priority (subtract value) 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "PRI6,Transmit Blocks Per Priority (subtract value) 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 20.--23. "PRI5,Transmit Blocks Per Priority (subtract value) 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "PRI4,Transmit Blocks Per Priority (subtract value) 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 12.--15. "PRI3,Transmit Blocks Per Priority (subtract value) 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "PRI2,Transmit Blocks Per Priority (subtract value) 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "PRI1,Transmit Blocks Per Priority (subtract value) 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PRI0,Transmit Blocks Per Priority (subtract value) 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "CPSW_PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words"
hexmask.long.word 0x1C 0.--8. 1. "COUNT,Receive Flow Control Threshold in Words"
line.long 0x20 "CPSW_PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter"
hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE Idle to LPI counter load value"
line.long 0x24 "CPSW_PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter"
hexmask.long.tbyte 0x24 0.--23. 1. "COUNT,EEE LPI to wake counter load value"
line.long 0x28 "CPSW_PN_EEE_STATUS_REG,Enet Port N EEE status"
bitfld.long 0x28 6. "TX_FIFO_EMPTY,Port N Transmit FIFO packet count zero" "0,1"
bitfld.long 0x28 5. "RX_FIFO_EMPTY,Port N Receive FIFO packet count zero" "0,1"
bitfld.long 0x28 4. "TX_FIFO_HOLD,Port N Transmit FIFO hold" "0,1"
bitfld.long 0x28 3. "TX_WAKE,Port N Receive Wake Time" "0,1"
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bitfld.long 0x28 2. "TX_LPI,Port N Transmit LPI" "0,1"
bitfld.long 0x28 1. "RX_LPI,Port N Receive LPI" "0,1"
bitfld.long 0x28 0. "WAIT_IDLE2LPI,Transmit Wait Idle to LPI" "0,1"
group.long 0x22040++0x0B
line.long 0x00 "CPSW_PN_IET_CONTROL_REG,Enet Port N IET Control"
hexmask.long.byte 0x00 16.--23. 1. "MAC_PREMPT,Mac Preempt Queue - Indicates which transmit FIFO queues are sent to the preempt MAC"
bitfld.long 0x00 8.--10. "MAC_ADDFRAGSIZE,Mac Fragment Size - An integer in the range 0:7 indicating as a multiple of 64 the minimum additional length for nonfinal mPackets" "64,128,192,256,320,384,448,512"
bitfld.long 0x00 3. "MAC_LINKFAIL,Mac Link Fail - Link Fail Indicator to reset the verify state machine" "0,1"
bitfld.long 0x00 2. "MAC_DISABLEVERIFY,Mac Disable Verify - Disables verification on the port when set" "0,1"
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bitfld.long 0x00 1. "MAC_HOLD,Mac Hold - Hold Preemption on the port" "0,1"
bitfld.long 0x00 0. "MAC_PENABLE,Mac Preemption Enable - Port Preemption Enable" "0,1"
line.long 0x04 "CPSW_PN_IET_STATUS_REG,Enet Port N IET Status"
bitfld.long 0x04 3. "MAC_VERIFY_ERR,Mac Received Verify Packet with Errors - Set when a verify packet with errors is received" "0,1"
bitfld.long 0x04 2. "MAC_RESPOND_ERR,Mac Received Respond Packet with Errors - Set when a respond packet with errors is received" "0,1"
bitfld.long 0x04 1. "MAC_VERIFY_FAIL,Mac Verification Failed - Indication that verification was unsuccessful" "0,1"
bitfld.long 0x04 0. "MAC_VERIFIED,Mac Verified - Indication that verification was successful" "0,1"
line.long 0x08 "CPSW_PN_IET_VERIFY_REG,Enet Port N IET VERIFY"
hexmask.long.tbyte 0x08 0.--23. 1. "MAC_VERIFY_CNT,Mac Verify Timeout Count - The number of wireside clocks contained in the verify timeout counter"
rgroup.long 0x22050++0x03
line.long 0x00 "CPSW_PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS"
bitfld.long 0x00 18. "EST_BUFACT,EST RAM active buffer" "0,1"
bitfld.long 0x00 17. "EST_ADD_ERR,EST Address Error" "0,1"
bitfld.long 0x00 16. "EST_CNT_ERR,EST Fetch Count Error" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "TX_E_MAC_ALLOW,EST transmit MAC allow"
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hexmask.long.byte 0x00 0.--7. 1. "TX_PRI_ACTIVE,EST Transmit Priority Active"
group.long 0x22060++0x03
line.long 0x00 "CPSW_PN_EST_CONTROL_REG,Enet Port N EST CONTROL"
hexmask.long.word 0x00 16.--25. 1. "EST_FILL_MARGIN,EST Fill Margin"
bitfld.long 0x00 8. "EST_FILL_EN,EST Fill Enable" "0,1"
bitfld.long 0x00 5.--7. "EST_TS_PRI,EST Timestamp Express Priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "EST_TS_ONEPRI,EST Timestamp One Express Priority" "0,1"
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bitfld.long 0x00 3. "EST_TS_FIRST,EST Timestamp First Express Packet only" "0,1"
bitfld.long 0x00 2. "EST_TS_EN,EST Timestamp Enable" "0,1"
bitfld.long 0x00 1. "EST_BUFSEL,EST Buffer Select" "0,1"
bitfld.long 0x00 0. "EST_ONEBUF,EST One Fetch Buffer" "0,1"
group.long 0x22120++0x03
line.long 0x00 "CPSW_PN_RX_DSCP_MAP_REG_y,Enet Port N Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
group.long 0x22140++0x03
line.long 0x00 "CPSW_PN_PRI_CIR_REG_y,Ethernet Port N Rx Priority 0 to Priority 7 Committed Information Rate Registers"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority 'y' Committed Information Rate Count Value"
group.long 0x22160++0x03
line.long 0x00 "CPSW_PN_PRI_EIR_REG_y,Ethernet Port N Rx Priority 0 to Priority 7 Excess Information Rate Registers Offset = 00022160h + (y * 4h); where y = 0h to 7h"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority 'y' Excess Information Rate Count Value"
group.long 0x22180++0x1F
line.long 0x00 "CPSW_PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CPSW_PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "CPSW_PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CPSW_PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "CPSW_PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "CPSW_PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22300++0x23
line.long 0x00 "CPSW_PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low"
bitfld.long 0x00 24.--28. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CPSW_PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High"
bitfld.long 0x04 24.--28. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CPSW_PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low"
hexmask.long.byte 0x08 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)"
hexmask.long.byte 0x08 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15-8 (byte 1)"
line.long 0x0C "CPSW_PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High"
hexmask.long.byte 0x0C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23-16 (byte 2)"
hexmask.long.byte 0x0C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31-24 (byte 3)"
hexmask.long.byte 0x0C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39-32 (byte 4)"
hexmask.long.byte 0x0C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47-40 (byte 5)"
line.long 0x10 "CPSW_PN_TS_CTL_REG,Enet Port N Time Sync Control"
hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable"
bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Sync Transmit Annex E enable" "0,1"
bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Sync Receive Annex E enable" "0,1"
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bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable (transmit and receive)" "0,1"
bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Sync Transmit Annex D enable" "0,1"
bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_EN,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_EN,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Sync Transmit Annex F enable" "0,1"
bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Sync Receive Annex D enable" "0,1"
bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_EN,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_EN,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Sync Receive Annex F Enable" "0,1"
line.long 0x14 "CPSW_PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
bitfld.long 0x14 16.--21. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
line.long 0x18 "CPSW_PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2"
hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
line.long 0x1C "CPSW_PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2"
bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
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bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
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bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
line.long 0x20 "CPSW_PN_TS_CTL2_REG,Enet Port N Time Sync Control 2"
bitfld.long 0x20 16.--21. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
group.long 0x22330++0x13
line.long 0x00 "CPSW_PN_MAC_CONTROL_REG,Enet Port N Mac Control"
bitfld.long 0x00 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1"
bitfld.long 0x00 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1"
bitfld.long 0x00 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1"
bitfld.long 0x00 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1"
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bitfld.long 0x00 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
bitfld.long 0x00 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
bitfld.long 0x00 18. "CTL_EN,External Control Enable" "0,1"
bitfld.long 0x00 17. "GIG_FORCE,Gigabit Mode Force" "0,1"
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bitfld.long 0x00 16. "IFCTL_B,Interface Control B" "0,1"
bitfld.long 0x00 15. "IFCTL_A,Interface Control A" "0,1"
bitfld.long 0x00 12. "CRC_TYPE,Port CRC Type" "0,1"
bitfld.long 0x00 11. "CMD_IDLE,Command Idle" "0,1"
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bitfld.long 0x00 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1"
bitfld.long 0x00 7. "GIG,Gigabit Mode" "0,1"
bitfld.long 0x00 6. "TX_PACE,Transmit Pacing Enable" "0,1"
bitfld.long 0x00 5. "GMII_EN,GMII Enable" "0,1"
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bitfld.long 0x00 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1"
bitfld.long 0x00 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
bitfld.long 0x00 2. "MTEST,Manufacturing Test mode" "0,1"
bitfld.long 0x00 1. "LOOPBACK,Loop Back Mode" "0,1"
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bitfld.long 0x00 0. "FULLDUPLEX,Full Duplex mode" "0,1"
line.long 0x04 "CPSW_PN_MAC_STATUS_REG,Enet Port N Mac Status"
bitfld.long 0x04 31. "IDLE,Enet IDLE" "0,1"
bitfld.long 0x04 30. "E_IDLE,Express MAC is Idle" "0,1"
bitfld.long 0x04 29. "P_IDLE,Prempt MAC is Idle" "0,1"
bitfld.long 0x04 28. "TX_IDLE,Mac Transmit Idle" "0,1"
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bitfld.long 0x04 27. "TORF,Top of receive FIFO flow control trigger occurred" "0,1"
bitfld.long 0x04 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x04 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
hexmask.long.byte 0x04 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)"
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bitfld.long 0x04 6. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
bitfld.long 0x04 5. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
bitfld.long 0x04 4. "EXT_GIG,External GIG" "0,1"
bitfld.long 0x04 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1"
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bitfld.long 0x04 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1"
bitfld.long 0x04 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1"
line.long 0x08 "CPSW_PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset"
bitfld.long 0x08 0. "SOFT_RESET,Software reset" "0,1"
line.long 0x0C "CPSW_PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test"
bitfld.long 0x0C 26.--30. "PACEVAL,Pacing Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 16.--25. 1. "RNDNUM,Backoff Random Number Generator"
rbitfld.long 0x0C 12.--15. "COLL_COUNT,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--9. 1. "TX_BACKOFF,Backoff Count"
line.long 0x10 "CPSW_PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer"
hexmask.long.word 0x10 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
group.long 0x22350++0x03
line.long 0x00 "CPSW_PN_MAC_RXN_PAUSETIMER_REG_y,Ethernet Port N PFC Priority 0 to Priority 7 Rx Pause Timer Registers"
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSETIMER,Rx 'y' Pause Timer Value"
group.long 0x22370++0x03
line.long 0x00 "CPSW_PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,802.3 Tx Pause Timer Value"
group.long 0x22380++0x03
line.long 0x00 "CPSW_PN_MAC_TXN_PAUSETIMER_REG_y,Ethernet Port N PFC Priority 0 to Priority 7 Tx Pause Timer Registers"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,PFC Tx 'y' Pause Timer Value"
group.long 0x223A0++0x07
line.long 0x00 "CPSW_PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "CPSW_PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap"
hexmask.long.word 0x04 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap"
group.long 0x223AC++0x13
line.long 0x00 "CPSW_PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer"
bitfld.long 0x00 0.--2. "INTERVLAN_OPX_POINTER,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7"
line.long 0x04 "CPSW_PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A"
hexmask.long.byte 0x04 24.--31. 1. "DA_23_16,Destination Address bits 23-16 - DA byte 4 on wire"
hexmask.long.byte 0x04 16.--23. 1. "DA_31_24,Destination Address bits 31-24 - DA byte 3 on wire"
hexmask.long.byte 0x04 8.--15. 1. "DA_39_32,Destination Address bits 39-32 - DA byte 2 on wire"
hexmask.long.byte 0x04 0.--7. 1. "DA_47_40,Destination Address bits 47-40 - DA byte 1 on wire"
line.long 0x08 "CPSW_PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B"
hexmask.long.byte 0x08 24.--31. 1. "SA_39_32,Source Address bits 39-32 - SA byte 2 on wire"
hexmask.long.byte 0x08 16.--23. 1. "SA_47_40,Source Address bits 47-40 - SA byte 1 on wire"
hexmask.long.byte 0x08 8.--15. 1. "DA_7_0,Destination Address bits 7-0 - DA byte 6 on wire"
hexmask.long.byte 0x08 0.--7. 1. "DA_15_8,Destination Address bits 15-8 - DA byte 5 on wire"
line.long 0x0C "CPSW_PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C"
hexmask.long.byte 0x0C 24.--31. 1. "SA_7_0,Source Address bits 7-0 - SA byte 6 on wire"
hexmask.long.byte 0x0C 16.--23. 1. "SA_15_8,Source Address bits 15-8 - SA byte 5 on wire"
hexmask.long.byte 0x0C 8.--15. 1. "SA_23_16,Source Address bits 23-16 - SA byte 4 on wire"
hexmask.long.byte 0x0C 0.--7. 1. "SA_31_24,Source Address bits 31-24 - SA byte 3 on wire"
line.long 0x10 "CPSW_PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D"
hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D"
tree.end
tree.end
tree "MCU_CPSW0_CPINT"
tree "MCU_CPSW0_NUSS_CPINT"
base ad:0x46000000
rgroup.long 0x1000++0x03
line.long 0x00 "CPSW_INT_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJREV,MajorCPSW_INT_REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CustomCPSW_INT_REVISION" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINREV,MinorCPSW_INT_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1010++0x07
line.long 0x00 "CPSW_INT_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CPSW_INT_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x1100++0x03
line.long 0x00 "CPSW_INT_ENABLE_REG_OUT_PULSE_0,Enable Register 0"
bitfld.long 0x00 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1"
bitfld.long 0x00 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1"
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bitfld.long 0x00 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1"
group.long 0x1300++0x03
line.long 0x00 "CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0,Enable Clear Register 0"
bitfld.long 0x00 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1"
bitfld.long 0x00 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1"
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bitfld.long 0x00 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1500++0x03
line.long 0x00 "CPSW_INT_STATUS_REG_OUT_PULSE_0,Status Register 0"
bitfld.long 0x00 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1"
bitfld.long 0x00 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1"
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bitfld.long 0x00 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1A80++0x03
line.long 0x00 "CPSW_INT_INTR_VECTOR_REG_OUT_PULSE,Interrupt Vector for out_pulse"
tree.end
tree.end
tree "MCU_CPSW0_CPTS"
tree "MCU_CPSW0_NUSS_CPTS"
base ad:0x46000000
rgroup.long 0x3D000++0x5B
line.long 0x00 "CPSW_CPTS_IDVER_REG,MCU_CPSW0_NUSS CPTS Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,TX Identification Value"
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bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor Version Value"
line.long 0x04 "CPSW_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output time stamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 17. "TX_GENF_CLR_EN,GENF (and ESTF) Clear Enable" "A CPTS_GENFn output is not cleared when the..,A CPTS_GENFn output is cleared when the.."
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bitfld.long 0x04 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events" "0,1"
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bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
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bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
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bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
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bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
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bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
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bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
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bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
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bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
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bitfld.long 0x04 7. "TS_PPM_DIR,PPM Correction Direction" "0,1"
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bitfld.long 0x04 6. "TS_COMP_TOG,Time stamp Compare Toggle mode" "0,1"
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bitfld.long 0x04 5. "MODE,64-Bit Mode" "0,1"
newline
bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable" "0,1"
newline
bitfld.long 0x04 3. "TSTAMP_EN,Host Receive time stamp Enable" "0,1"
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bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP Polarity" "0,1"
newline
bitfld.long 0x04 1. "INT_TEST,Interrupt Test" "0,1"
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bitfld.long 0x04 0. "CPTS_EN,Time Sync Enable" "0,1"
line.long 0x08 "CPSW_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select" "Selects CPSWHSDIV_CLKOUT2 clock,Selects MAINHSDIV_CLKOUT3 clock,Selects MCU_CPTS0_RFT_CLK I/O pin,Selects CPTS0_RFT_CLK I/O pin,Selects MCU_EXT_REFCLK0 I/O pin,Selects EXT_REFCLK1 I/O pin,Selects PCIE0_TXI0_CLK clock,Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL..,?..."
line.long 0x0C "CPSW_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x10 "CPSW_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x14 "CPSW_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x14 0. "TS_LOAD_EN,Time Stamp Load Enable" "0,1"
line.long 0x18 "CPSW_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value (lower 32-bits) Register"
line.long 0x1C "CPSW_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x20 "CPSW_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x24 "CPSW_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x28 "CPSW_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x2C "CPSW_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Value Register"
hexmask.long.byte 0x2C 0.--7. 1. "NUDGE,Time stamp Comparison Nudge Value"
line.long 0x30 "CPSW_CPTS_EVENT_POP_REG,Event Interrupt Pop Register"
bitfld.long 0x30 0. "EVENT_POP,Event Pop" "0,1"
line.long 0x34 "CPSW_CPTS_EVENT_0_REG,Lower 32-bits of the Event Value Register"
line.long 0x38 "CPSW_CPTS_EVENT_1_REG,Lower Middle 32-bits of the Event Value Register"
bitfld.long 0x38 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
newline
bitfld.long 0x38 24.--28. "PORT_NUMBER,Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x38 20.--23. "EVENT_TYPE,Time Sync Event Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x3C "CPSW_CPTS_EVENT_2_REG,Upper Middle 32-bits of the Event Value Register"
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,Domain"
line.long 0x40 "CPSW_CPTS_EVENT_3_REG,Upper 32-bits of the Event Value Register"
line.long 0x44 "CPSW_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value (upper 32-bits) Register"
line.long 0x48 "CPSW_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value (upper 32-bits) Register"
line.long 0x4C "CPSW_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x4C 0.--2. "ADD_VAL,The ts_add_value[2:0] is added to 1 to comprise the time stamp increment value" "0,1,2,3,4,5,6,7"
line.long 0x50 "CPSW_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Load Low Value (lower 32-bits) Register"
line.long 0x54 "CPSW_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM Load High Value (upper 32-bits) Register"
hexmask.long.word 0x54 0.--9. 1. "TS_PPM_HIGH_VAL,Time Stamp PPM High Value"
line.long 0x58 "CPSW_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x58 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge Value"
group.long 0x3D0E0++0x1B
line.long 0x00 "CPSW_GENF0_COMP_LOW_REG_L,Time Stamp Generate Function (GENF0) Comparison Low Value (lower 32-bits)"
line.long 0x04 "CPSW_GENF0_COMP_HIGH_REG_L,Time Stamp Generate Function (GENF0) Comparison high Value (upper 32-bits)"
line.long 0x08 "CPSW_GENF0_TS_GENF_CONTROL_REG,Time Stamp Generate Function (GENF0) Control Registers"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
newline
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
line.long 0x0C "CPSW_GENF0_LENGTH_REG_L,Time Stamp Generate Function (GENF0) Length Value"
line.long 0x10 "CPSW_GENF0_PPM_LOW_REG_L,Time Stamp Generate Function (GENF0) PPM Low Value (lower 32-bits)"
line.long 0x14 "CPSW_GENF0_PPM_HIGH_REG_L,Time Stamp Generate Function (GENF0) PPM High Value (upper 32-bits)"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "CPSW_GENF0_NUDGE_REG_L,Time Stamp Generate Function (GENF0) Nudge Value Registers"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
group.long 0x3D100++0x1B
line.long 0x00 "CPSW_GENF1_COMP_LOW_REG,Time Stamp Generate Function (GENF1) Comparison Low Value"
line.long 0x04 "CPSW_GENF1_COMP_HIGH_REG,Time Stamp Generate Function (GENF1) Comparison high Value (upper 32-bits)"
line.long 0x08 "CPSW_GENF1_CONTROL_REG,Time Stamp Generate Function (GENF1) Control Register"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function (GENF1) Polarity Invert" "0,1"
newline
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function (GENF1) PPM Direction" "0,1"
line.long 0x0C "CPSW_GENF1_LENGTH_REG,Time Stamp Generate Function (GENF1) Length Value"
line.long 0x10 "CPSW_GENF1_PPM_LOW_REG,Time Stamp Generate Function (GENF1) PPM Low Value (lower 32-bits)"
line.long 0x14 "CPSW_GENF1_PPM_HIGH_REG,Time Stamp Generate Function (GENF1) PPM High Value (upper 32-bits)"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function (GENF1) PPM High Value"
line.long 0x18 "CPSW_GENF1_NUDGE_REG,Time Stamp Generate Function (GENF1) Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function (GENF1) Nudge Value"
group.long 0x3D200++0x1B
line.long 0x00 "CPSW_ESTF1_COMP_LOW_REG,Time Stamp Generate Function (ESTF1) Comparison Low Value"
line.long 0x04 "CPSW_ESTF1_COMP_HIGH_REG,Time Stamp Generate Function (ESTF1) Comparison high Value (upper 32-bits)"
line.long 0x08 "CPSW_ESTF1_CONTROL_REG,Time Stamp Generate Function (ESTF1) Control Register"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function (ESTF1) Polarity Invert" "0,1"
newline
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function (ESTF1) PPM Direction" "0,1"
line.long 0x0C "CPSW_ESTF1_LENGTH_REG,Time Stamp Generate Function (ESTF1) Length Value"
line.long 0x10 "CPSW_ESTF1_PPM_LOW_REG,Time Stamp Generate Function (ESTF1) PPM Low Value (lower 32-bits)"
line.long 0x14 "CPSW_ESTF1_PPM_HIGH_REG,Time Stamp Generate Function (ESTF1) PPM High Value (upper 32-bits)"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function (ESTF1) PPM High Value"
line.long 0x18 "CPSW_ESTF1_NUDGE_REG,Time Stamp Generate Function (ESTF1) Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function (ESTF1) Nudge Value"
tree.end
tree.end
tree "MCU_CPSW0_ECC"
tree "MCU_CPSW0_ECC"
base ad:0x40709000
rgroup.long 0x00++0x03
line.long 0x00 "CPSW_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CPSW_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPSW_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CPSW_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CPSW_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CPSW_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
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bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CPSW_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CPSW_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CPSW_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CPSW_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
newline
bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CPSW_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CPSW_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPSW_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPSW_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPSW_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPSW_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MCU_CPSW0_MDIO"
tree "MCU_CPSW0_NUSS_MDIO"
base ad:0x46000000
rgroup.long 0xF00++0x47
line.long 0x00 "CPSW_MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_MDIO_CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
line.long 0x08 "CPSW_MDIO_ALIVE_REG,MDIO Alive Register"
line.long 0x0C "CPSW_MDIO_LINK_REG,MDIO Link Register"
line.long 0x10 "CPSW_MDIO_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "CPSW_MDIO_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "CPSW_MDIO_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "CPSW_MDIO_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "CPSW_MDIO_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
line.long 0x24 "CPSW_MDIO_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0 respectively" "0,1,2,3"
line.long 0x28 "CPSW_MDIO_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for" "0,1,2,3"
line.long 0x2C "CPSW_MDIO_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for" "0,1,2,3"
line.long 0x30 "CPSW_MDIO_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x30 0. "MDIO_PIN,MDIO_Pin Value" "0,1"
line.long 0x34 "CPSW_MDIO_POLL_REG,MDIO Poll Register"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "IPG,Polling Inter Packet Gap Value"
line.long 0x38 "CPSW_MDIO_POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "CPSW_MDIO_CLAUS45_REG,MDIO Clause45 Enable Register"
line.long 0x40 "CPSW_MDIO_USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO User Address 0"
line.long 0x44 "CPSW_MDIO_USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO User Address 1"
group.long 0xF80++0x07
line.long 0x00 "CPSW_MDIO_USER_ACCESS_REG_k,MDIO User Access Register Offset = F80h + (k * 8h); where k = 0h to 1h"
bitfld.long 0x00 31. "GO,Go" "0,1"
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "CPSW_MDIO_USER_PHY_SEL_REG_k,MDIO User PHY Select Register Offset = F84h + (k * 8h); where k = 0h to 1h"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "MCU_CPSW0_NUSS_Subsystem__SS_"
tree "MCU_CPSW0_NUSS_SS"
base ad:0x46000000
rgroup.long 0x00++0x13
line.long 0x00 "CPSW_SS_CPSW_NUSS_IDVER_REG,CPSW_NUSS ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_SS_SYNCE_COUNT_REG,CPSW_NUSS SYNCE Count Register"
line.long 0x08 "CPSW_SS_SYNCE_MUX_REG,CPSW_NUSS Synce Mux Register"
bitfld.long 0x08 0.--5. "SYNCE_SEL,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CPSW_SS_CONTROL_REG,CPSW_NUSS Control Register"
bitfld.long 0x0C 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode:0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW " "0,1"
bitfld.long 0x0C 0. "EEE_EN,Energy Efficient Ethernet Enable:0=EEE is disabled " "0,1"
line.long 0x10 "CPSW_SS_SGMII_MODE_REG,CPSW_NUSS SyncE Mux Register Note: SGMII mode is not supported on the 2-port CPSW module"
bitfld.long 0x10 0. "SYNCE_SEL,SGMII_MODE InputNote: SGMII mode is not supported on the 2-port CPSW module" "0,1"
rgroup.long 0x18++0x07
line.long 0x00 "CPSW_SS_RGMII_STATUS_REG,CPSW_NUSS RGMII Status Register"
bitfld.long 0x00 3. "FULLDUPLEX,Rgmii full dulex:0=Half-duplex " "0,1"
bitfld.long 0x00 1.--2. "SPEED,Rgmii speed:00=10Mbps " "0,1,2,3"
bitfld.long 0x00 0. "LINK,Rgmii link indicator:0=Link is down " "0,1"
line.long 0x04 "CPSW_SS_SUBSSYSTEM_STATUS_REG,CPSW_NUSS Status Register"
bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
tree.end
tree.end
tree "MCU_CPSW0_RAM"
tree "MCU_CPSW0_NUSS_RAM"
base ad:0x46000000
group.long 0x32000++0x03
line.long 0x00 "CPSW_FETCH_LOC_y,These are the RAM locations for one Ethernet port"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
tree.end
tree.end
tree "MCU_CPSW0_SGMII"
tree "MCU_CPSW0_NUSS_SGMII"
base ad:0x46000000
rgroup.long 0x100++0x07
line.long 0x00 "CPSW_SGMII_IDVER_REG,SGMII IDVER register Note: SGMII mode is not supported on the 2-port CPSW module"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Module value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_SGMII_SOFT_RESET_REG,SGMII Soft Reset Register Note: SGMII mode is not supported on the 2-port CPSW module"
bitfld.long 0x04 1. "RT_SOFT_RESET,Transmit and Receive Software Reset.This bit is intended to be used when changing between loopback mode and normal mode of operation" "0,1"
bitfld.long 0x04 0. "SOFT_RESET,Software Reset" "0,1"
group.long 0x110++0x17
line.long 0x00 "CPSW_SGMII_CONTROL_REG,SGMII Control Register Note: SGMII mode is not supported on the 2-port CPSW module"
bitfld.long 0x00 6. "TEST_PATTERN_EN,Test Pattern Enable" "0,1"
bitfld.long 0x00 5. "MASTER,Master Mode" "0,1"
bitfld.long 0x00 4. "LOOPBACK,Loopback mode" "0,1"
bitfld.long 0x00 3. "MR_NP_LOADED,Next Page Loaded" "0,1"
bitfld.long 0x00 2. "FAST_LINK_TIMER,Fast Link Timer" "0,1"
newline
bitfld.long 0x00 1. "MR_AN_RESTART,Auto Negotiation Restart" "0,1"
bitfld.long 0x00 0. "MR_AN_ENABLE,Auto Negotiation Enable" "0,1"
line.long 0x04 "CPSW_SGMII_STATUS_REG,SGMII Status Register Note: SGMII mode is not supported on the 2-port CPSW module"
bitfld.long 0x04 5. "FIB_SIG_DETECT,Fiber Signal Detect" "0,1"
bitfld.long 0x04 4. "LOCK,Lock" "0,1"
bitfld.long 0x04 3. "MR_PAGE_RX,Next Page Received" "0,1"
bitfld.long 0x04 2. "MR_AN_COMPLETE,Auto negotiation complete" "0,1"
bitfld.long 0x04 1. "AN_ERROR,Auto negotiation error" "0,1"
newline
bitfld.long 0x04 0. "LINK,Link indicator" "0,1"
line.long 0x08 "CPSW_SGMII_MR_ADV_ABILITY_REG,SGMII MR Advertized Ability Register Note: SGMII mode is not supported on the 2-port CPSW module"
hexmask.long.word 0x08 0.--15. 1. "MR_ADV_ABILITY,Advertised Ability"
line.long 0x0C "CPSW_SGMII_MR_NP_TX_REG,SGMII Next Pate Transmit Register Note: SGMII mode is not supported on the 2-port CPSW module"
hexmask.long.word 0x0C 0.--15. 1. "MR_NP_TX,Next Page Transmit"
line.long 0x10 "CPSW_SGMII_MR_LP_ADV_ABILITY_REG,SGMII Link Partner Advertized Ability Register Note: SGMII mode is not supported on the 2-port CPSW module"
hexmask.long.word 0x10 0.--15. 1. "MR_LP_ADV_ABILITY,Link Partner Advertised Ability"
line.long 0x14 "CPSW_SGMII_MR_LP_NP_RX_REG,SGMII Link Partner Next Page Receive Register Note: SGMII mode is not supported on the 2-port CPSW module"
hexmask.long.word 0x14 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received"
group.long 0x130++0x0B
line.long 0x00 "CPSW_SGMII_TX_CFG_REG,SGMII Transmit Configuration Register Note: SGMII mode is not supported on the 2-port CPSW module"
line.long 0x04 "CPSW_SGMII_RX_CFG_REG,SGMII Receive Configuration Register Note: SGMII mode is not supported on the 2-port CPSW module"
line.long 0x08 "CPSW_SGMII_AUX_CFG_REG,SGMII Auxiliary Configuration Register Note: SGMII mode is not supported on the 2-port CPSW module"
group.long 0x140++0x0B
line.long 0x00 "CPSW_SGMII_DIAG_CLEAR_REG,SGMII Diagnostics Clear Register Note: SGMII mode is not supported on the 2-port CPSW module"
bitfld.long 0x00 0. "DIAG_CLEAR,Diagnostics Clear" "0,1"
line.long 0x04 "CPSW_SGMII_DIAG_CONTROL_REG,SGMII Diagnostics Control Register Note: SGMII mode is not supported on the 2-port CPSW module"
bitfld.long 0x04 4.--6. "DIAG_SM_SEL,Diagnostic Select" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--1. "DIAG_EDGE_SEL,Diagnostis Hold Signals Edge Select" "0,1,2,3"
line.long 0x08 "CPSW_SGMII_DIAG_STATUS_REG,SGMII Diagnostics Status Register Note: SGMII mode is not supported on the 2-port CPSW module"
hexmask.long.word 0x08 0.--15. 1. "DIAG_STATUS,Diagnostics status"
tree.end
tree.end
tree "MCU_CPSW0_STAT0"
tree "MCU_CPSW0_NUSS_STAT0"
base ad:0x46000000
group.long 0x3A000++0x0B
line.long 0x00 "CPSW_STAT0_RXGOODFRAMES,The total number of good frames received on the port"
line.long 0x04 "CPSW_STAT0_RXBROADCASTFRAMES,The total number of good broadcast frames received on the port"
line.long 0x08 "CPSW_STAT0_RXMULTICASTFRAMES,The total number of good multicast frames received on the port"
group.long 0x3A010++0x03
line.long 0x00 "CPSW_STAT0_RXCRCERRORS,The total number of frames received on the port that experienced a CRC error"
group.long 0x3A018++0x03
line.long 0x00 "CPSW_STAT0_RXOVERSIZEDFRAMES,The total number of oversized frames received on the port"
group.long 0x3A020++0x1F
line.long 0x00 "CPSW_STAT0_RXUNDERSIZEDFRAMES,The total number of undersized frames received on the port"
line.long 0x04 "CPSW_STAT0_RXFRAGMENTS,The total number of frame fragments received on the port"
line.long 0x08 "CPSW_STAT0_ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x0C "CPSW_STAT0_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x10 "CPSW_STAT0_RXOCTETS,The total number of bytes in all good frames received on the port"
line.long 0x14 "CPSW_STAT0_TXGOODFRAMES,The total number of good frames received on the port"
line.long 0x18 "CPSW_STAT0_TXBROADCASTFRAMES,The total number of good broadcast frames received on the port"
line.long 0x1C "CPSW_STAT0_TXMULTICASTFRAMES,The total number of good multicast frames received on the port"
group.long 0x3A064++0x7B
line.long 0x00 "CPSW_STAT0_TXOCTETS,The total number of bytes in all good frames transmitted on the port"
line.long 0x04 "CPSW_STAT0_OCTETFRAMES64,The total number of 64-byte frames received and transmitted on the port"
line.long 0x08 "CPSW_STAT0_OCTETFRAMES65T127,The total number of frames of size 65 to 127 bytes received and transmitted on the port"
line.long 0x0C "CPSW_STAT0_OCTETFRAMES128T255,The total number of frames of size 128 to 255 bytes received and transmitted on the port"
line.long 0x10 "CPSW_STAT0_OCTETFRAMES256T511,The total number of frames of size 256 to 511 bytes received and transmitted on the port"
line.long 0x14 "CPSW_STAT0_OCTETFRAMES512T1023,The total number of frames of size 512 to 1023 bytes received and transmitted on the port"
line.long 0x18 "CPSW_STAT0_OCTETFRAMES1024TUP,The total number of frames of size 1024 to [13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port"
line.long 0x1C "CPSW_STAT0_NETOCTETS,The total number of bytes of frame data received and transmitted on the port"
line.long 0x20 "CPSW_STAT0_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x24 "CPSW_STAT0_PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x28 "CPSW_STAT0_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x2C "CPSW_STAT0_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x30 "CPSW_STAT0_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x34 "CPSW_STAT0_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x38 "CPSW_STAT0_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0x3C "CPSW_STAT0_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0x40 "CPSW_STAT0_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0x44 "CPSW_STAT0_ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0x48 "CPSW_STAT0_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0x4C "CPSW_STAT0_ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0x50 "CPSW_STAT0_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0x54 "CPSW_STAT0_ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0x58 "CPSW_STAT0_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0x5C "CPSW_STAT0_ALE_POL_MATCH,ALE Policer Matched"
line.long 0x60 "CPSW_STAT0_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0x64 "CPSW_STAT0_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0x68 "CPSW_STAT0_ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0x6C "CPSW_STAT0_ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0x70 "CPSW_STAT0_ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0x74 "CPSW_STAT0_ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0x78 "CPSW_STAT0_ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A140++0x17
line.long 0x00 "CPSW_STAT0_IET_RX_ASSEMBLY_ERROR_REG,IET Receive Assembly Error"
line.long 0x04 "CPSW_STAT0_IET_RX_ASSEMBLY_OK_REG,IET Receive Assembly Ok"
line.long 0x08 "CPSW_STAT0_IET_RX_SMD_ERROR_REG,IET Receive Smd Error"
line.long 0x0C "CPSW_STAT0_IET_RX_FRAG_REG,IET Receive Frag"
line.long 0x10 "CPSW_STAT0_IET_TX_HOLD_REG,IET Transmit Hold"
line.long 0x14 "CPSW_STAT0_IET_TX_FRAG_REG,IET Transmit Frag"
group.long 0x3A17C++0x03
line.long 0x00 "CPSW_STAT0_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error.Note: If there is a memorry protect error then this COUNT value will increment and issue a STAT_PEND0 interrupt when this bit field is non-zero.That is different from the other stats which only issue an interrupt.."
tree.end
tree.end
tree "MCU_CPSW0_STAT1"
tree "MCU_CPSW0_NUSS"
base ad:0x46000000
group.long 0x3A200++0xDF
line.long 0x00 "CPSW_STAT1_RXGOODFRAMES,The total number of good frames received on the port"
line.long 0x04 "CPSW_STAT1_RXBROADCASTFRAMES,The total number of good broadcast frames received on the port"
line.long 0x08 "CPSW_STAT1_RXMULTICASTFRAMES,The total number of good multicast frames received on the port"
line.long 0x0C "CPSW_STAT1_RXPAUSEFRAMES,The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not)"
line.long 0x10 "CPSW_STAT1_RXCRCERRORS,The total number of frames received on the port that experienced a CRC error"
line.long 0x14 "CPSW_STAT1_RXALIGNCODEERRORS,The total number of frames received on the port that experienced an alignment error or code error"
line.long 0x18 "CPSW_STAT1_RXOVERSIZEDFRAMES,The total number of oversized frames received on the port"
line.long 0x1C "CPSW_STAT1_RXJABBERFRAMES,The total number of jabber frames received on the port"
line.long 0x20 "CPSW_STAT1_RXUNDERSIZEDFRAMES,The total number of undersized frames received on the port"
line.long 0x24 "CPSW_STAT1_RXFRAGMENTS,The total number of frame fragments received on the port"
line.long 0x28 "CPSW_STAT1_ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x2C "CPSW_STAT1_ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x30 "CPSW_STAT1_RXOCTETS,The total number of bytes in all good frames received on the port"
line.long 0x34 "CPSW_STAT1_TXGOODFRAMES,The total number of good frames received on the port"
line.long 0x38 "CPSW_STAT1_TXBROADCASTFRAMES,The total number of good broadcast frames received on the port"
line.long 0x3C "CPSW_STAT1_TXMULTICASTFRAMES,The total number of good multicast frames received on the port"
line.long 0x40 "CPSW_STAT1_TXPAUSEFRAMES,This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port"
line.long 0x44 "CPSW_STAT1_TXDEFERREDFRAMES,The total number of frames transmitted on the port that first experienced deferment"
line.long 0x48 "CPSW_STAT1_TXCOLLISIONFRAMES,This statistic records the total number of times that the port experienced a collision"
line.long 0x4C "CPSW_STAT1_TXSINGLECOLLFRAMES,The total number of frames transmitted on the port that experienced exactly one collision"
line.long 0x50 "CPSW_STAT1_TXMULTCOLLFRAMES,The total number of frames transmitted on the port that experienced multiple collisions"
line.long 0x54 "CPSW_STAT1_TXEXCESSIVECOLLISIONS,The total number of frames for which transmission was abandoned due to excessive collisions"
line.long 0x58 "CPSW_STAT1_TXLATECOLLISIONS,The total number of frames on the port for which transmission was abandoned because they experienced a late collision"
line.long 0x5C "CPSW_STAT1_RXIPGERROR,Total number of receive inter-packet gap errors (10G only)"
line.long 0x60 "CPSW_STAT1_TXCARRIERSENSEERRORS,The total number of frames received on the port that had a middle of frame (MOF) overrun"
line.long 0x64 "CPSW_STAT1_TXOCTETS,The total number of bytes in all good frames transmitted on the port"
line.long 0x68 "CPSW_STAT1_OCTETFRAMES64,The total number of 64-byte frames received and transmitted on the port"
line.long 0x6C "CPSW_STAT1_OCTETFRAMES65T127,The total number of frames of size 65 to 127 bytes received and transmitted on the port"
line.long 0x70 "CPSW_STAT1_OCTETFRAMES128T255,The total number of frames of size 128 to 255 bytes received and transmitted on the port"
line.long 0x74 "CPSW_STAT1_OCTETFRAMES256T511,The total number of frames of size 256 to 511 bytes received and transmitted on the port"
line.long 0x78 "CPSW_STAT1_OCTETFRAMES512T1023,The total number of frames of size 512 to 1023 bytes received and transmitted on the port"
line.long 0x7C "CPSW_STAT1_OCTETFRAMES1024TUP,The total number of frames of size 1024 to [13-0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port"
line.long 0x80 "CPSW_STAT1_NETOCTETS,The total number of bytes of frame data received and transmitted on the port"
line.long 0x84 "CPSW_STAT1_RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x88 "CPSW_STAT1_PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x8C "CPSW_STAT1_RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x90 "CPSW_STAT1_ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x94 "CPSW_STAT1_ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x98 "CPSW_STAT1_ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x9C "CPSW_STAT1_ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0xA0 "CPSW_STAT1_ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0xA4 "CPSW_STAT1_ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0xA8 "CPSW_STAT1_ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0xAC "CPSW_STAT1_ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0xB0 "CPSW_STAT1_ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0xB4 "CPSW_STAT1_ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0xB8 "CPSW_STAT1_ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0xBC "CPSW_STAT1_ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0xC0 "CPSW_STAT1_ALE_POL_MATCH,ALE Policer Matched"
line.long 0xC4 "CPSW_STAT1_ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0xC8 "CPSW_STAT1_ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0xCC "CPSW_STAT1_ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0xD0 "CPSW_STAT1_ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0xD4 "CPSW_STAT1_ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0xD8 "CPSW_STAT1_ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0xDC "CPSW_STAT1_ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A340++0x17
line.long 0x00 "CPSW_STAT1_IET_RX_ASSEMBLY_ERROR_REG,IET Receive Assembly Error"
line.long 0x04 "CPSW_STAT1_IET_RX_ASSEMBLY_OK_REG,IET Receive Assembly Ok"
line.long 0x08 "CPSW_STAT1_IET_RX_SMD_ERROR_REG,IET Receive Smd Error"
line.long 0x0C "CPSW_STAT1_IET_RX_FRAG_REG,IET Receive Frag"
line.long 0x10 "CPSW_STAT1_IET_TX_HOLD_REG,IET Transmit Hold"
line.long 0x14 "CPSW_STAT1_IET_TX_FRAG_REG,IET Transmit Frag"
group.long 0x3A37C++0x07
line.long 0x00 "CPSW_STAT1_TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
line.long 0x04 "CPSW_STAT1_ENET_PN_TX_PRI_REG_y,ENET Port n PRIORITY N Packet Count"
group.long 0x3A3A0++0x03
line.long 0x00 "CPSW_STAT1_ENET_PN_TX_PRI_BCNT_REG_y,ENET Port n PRIORITY N Packet Byte Count"
group.long 0x3A3C0++0x03
line.long 0x00 "CPSW_STAT1_ENET_PN_TX_PRI_DROP_REG_y,ENET Port n PRIORITY N Packet Drop Count"
group.long 0x3A3E0++0x03
line.long 0x00 "CPSW_STAT1_ENET_PN_TX_PRI_DROP_BCNT_REG_y,ENET Port n PRIORITY N Packet Drop Byte Count"
tree.end
tree.end
tree "MCU_CTRL_MMR0"
tree "MCU_CTRL_MMR0"
base ad:0x40F00000
rgroup.long 0x00++0x03
line.long 0x00 "CTRLMMR_MCU_PID,Peripheral release details"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business unit" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module functional identifier"
bitfld.long 0x00 11.--15. "R_RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CTRLMMR_MCU_MMR_CFG1,Indicates the MMR configuration"
hexmask.long.byte 0x00 0.--7. 1. "PARTITIONS,Indicates present partitions"
group.long 0x120++0x03
line.long 0x00 "CTRLMMR_MCU_IPC_SET8,Generate interprocessor communication interrupt to DMSC"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
group.long 0x1A0++0x03
line.long 0x00 "CTRLMMR_MCU_IPC_CLR8,Acknowledge interprocessor communication interrupt to DMSC"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
rgroup.long 0x200++0x07
line.long 0x00 "CTRLMMR_MCU_MAC_ID0,MCU Ethernet MAC address lower 32-bits"
line.long 0x04 "CTRLMMR_MCU_MAC_ID1,MCU Ethernet MAC address upper 16-bits"
hexmask.long.word 0x04 0.--15. 1. "MACID_HI,16 msbs of MAC address"
group.long 0x1008++0x2B
line.long 0x00 "CTRLMMR_MCU_LOCK0_KICK0,Lower 32-bits of Partition0 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_MCU_LOCK0_KICK1,Upper 32-bits of Partition 0 write lock key"
line.long 0x08 "CTRLMMR_MCU_INTR_RAW_STAT,Shows the interupt status (before enabling) and allows setting of the interrupt status (for test)"
bitfld.long 0x08 2. "LOCK_ERR,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1"
bitfld.long 0x08 1. "ADDR_ERR,Address violation occurred (attempt to read or write an invalid register address)" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation occurred (attempt to to read or write a register with insufficient sucurity or privilege access rights)" "0,1"
line.long 0x0C "CTRLMMR_MCU_INTR_STAT_CLR,Shows the enabled interrupt status and allows the interrupt to be cleared"
bitfld.long 0x0C 2. "EN_LOCK_ERR,Enabled lock interrupt event status" "0,1"
bitfld.long 0x0C 1. "EN_ADDR_ERR,Enabled address interrupt event status" "0,1"
newline
bitfld.long 0x0C 0. "EN_PROT_ERR,Enabled protection interrupt event status" "0,1"
line.long 0x10 "CTRLMMR_MCU_INTR_EN_SET,Allows interrupt enables to be set"
bitfld.long 0x10 2. "LOCK_ERR_EN_SET,Lock interrupt enable" "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN_SET,Address interrupt enable" "0,1"
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bitfld.long 0x10 0. "PROT_ERR_EN_SET,Protection interrupt enable" "0,1"
line.long 0x14 "CTRLMMR_MCU_INTR_EN_CLR,Allows interrupt enables to be cleared"
bitfld.long 0x14 2. "LOCK_ERR_EN_CLR,Lock interrupt disable" "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Address interrupt disable" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection interrupt disable" "0,1"
line.long 0x18 "CTRLMMR_MCU_EOI,Vector value This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,"
line.long 0x1C "CTRLMMR_MCU_FAULT_ADDR,Indicates the address of the first transfer that caused a fault to occur"
line.long 0x20 "CTRLMMR_MCU_FAULT_TYPE,Indicates the access type of the first transfer that caused a fault to occur"
bitfld.long 0x20 0.--5. "TYPE,Type of access which faulted" "No fault,User execute access,User write access,?,User read access,?,?,?,Supervisor execute access,?,?,?,?,?,?,?,Supervisor write access,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read access,?..."
line.long 0x24 "CTRLMMR_MCU_FAULT_ATTR,Indicates the attributes of the first transfer that caused a fault to occur"
hexmask.long.word 0x24 20.--31. 1. "XID,Transaction ID"
hexmask.long.word 0x24 8.--19. 1. "ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "PRIVID,Privilege ID"
line.long 0x28 "CTRLMMR_MCU_FAULT_CLR,Allows software to clear the current fault"
bitfld.long 0x28 0. "CLEAR,Fault clear" "0,1"
group.long 0x4030++0x03
line.long 0x00 "CTRLMMR_MCU_MSMC_CFG,Used to configure MSMC reset options"
bitfld.long 0x00 31. "DDR_ASSYM_EMIF_SEL,In the asymmetric interleave controls which EMIF controller implements the separated range of the memory window" "0,1"
bitfld.long 0x00 24.--29. "DDR_INTRLV_GRAN,Defines the size of each memory stripe for interleaved memory space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--21. "DDR_INTRLV_SIZE,Defines the memory window size for the interleaved region starting at the bottom of the external memory address range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4. "MEM_INIT_DIS,Disables MSMC SRAM initialization (Data Cache Tags and Snoop Filters)" "0,1"
group.long 0x4040++0x03
line.long 0x00 "CTRLMMR_MCU_ENET_CTRL,Controls MCU Ethernet Port1 operation"
bitfld.long 0x00 4. "RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "0,1"
bitfld.long 0x00 0.--1. "MODE_SEL,Selects ethernet switch Port1 interface" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported)"
group.long 0x4060++0x03
line.long 0x00 "CTRLMMR_MCU_SPI1_CTRL,Controls if MCU_SPI1 is directly connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1 and SPI3 are independently pinned out"
bitfld.long 0x00 0. "SPI1_LINKDIS,Disables direct connection of MCU_SPI1 to SPI3" "MCU_SPI1 is tied as a slave to SPI3,MCU_SPI1 is NOT tied as a slave to SPI3"
group.long 0x4070++0x13
line.long 0x00 "CTRLMMR_MCU_I3C0_CTRL0,Controls MCU I3C0 operation"
hexmask.long.word 0x00 16.--30. 1. "PID_MFR_ID,Manufacturer ID"
bitfld.long 0x00 8. "ROLE,Master Role" "0,1"
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bitfld.long 0x00 0.--3. "PID_INSTANCE,Provisional ID Instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CTRLMMR_MCU_I3C0_CTRL1,Controls MCU I3C0 operation"
hexmask.long.byte 0x04 24.--31. 1. "BUS_AVAIL_TIME,Indicates the number of pclk cycles in the Bus Available condition"
hexmask.long.tbyte 0x04 0.--17. 1. "BUS_IDLE_TIME,Indicates the number of pclk cycles in the Bus Idle condition"
line.long 0x08 "CTRLMMR_MCU_I3C1_CTRL0,Controls MCU I3C1 operation"
hexmask.long.word 0x08 16.--30. 1. "PID_MFR_ID,Manufacturer ID"
bitfld.long 0x08 8. "ROLE,Master Role" "0,1"
newline
bitfld.long 0x08 0.--3. "PID_INSTANCE,Provisional ID Instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CTRLMMR_MCU_I3C1_CTRL1,Controls MCU I3C1 operation"
hexmask.long.byte 0x0C 24.--31. 1. "BUS_AVAIL_TIME,Indicates the number of pclk cycles in the Bus Available condition"
hexmask.long.tbyte 0x0C 0.--17. 1. "BUS_IDLE_TIME,Indicates the number of pclk cycles in the Bus Idle condition"
line.long 0x10 "CTRLMMR_MCU_I2C0_CTRL,Controls MCU I2C0 operation"
bitfld.long 0x10 0. "HS_MCS_EN,HS Mode master current source enable" "0,1"
group.long 0x40A0++0x03
line.long 0x00 "CTRLMMR_MCU_FSS_CTRL,Controls Flash boot region size and placement"
bitfld.long 0x00 24. "S1_BOOT_SIZE,Selects the size of the boot block to be used for the S1 (OSPI1) flash interface" "0,1"
bitfld.long 0x00 16.--21. "S1_BOOT_SEG,Selects the boot block to be used for the S1 (OSPI1) flash interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8. "S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0 or HyperBus) flash interface" "0,1"
bitfld.long 0x00 0.--5. "S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0 or HyperBus) flash interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x40B0++0x07
line.long 0x00 "CTRLMMR_MCU_ADC0_CTRL,Controls operation of MCU ADC0"
bitfld.long 0x00 16. "GPI_MODE_EN,Enables MCU_ADC0 data pins to be used as general purpose inputs when set" "0,1"
bitfld.long 0x00 0.--4. "TRIG_SEL,Selects the source of the ADC hardware event trigger" "MCU_ADC_EXT_TRIGGER0 pin,MCU_ADC_EXT_TRIGGER1 pin,eHRPWM SOCA event,eHRPWM SOCB event,MCU Timer0 PWM output,MCU Timer1 PWM output,MCU Timer2 PWM output,MCU Timer3 PWM output,Timer0 PWM output,Timer1 PWM output,Timer2 PWM output,Timer3 PWM output,Timer4 PWM output,Timer5 PWM output,Timer6 PWM output,Timer7 PWM output,Timer8 PWM output,Timer9 PWM output,Timer10 PWM output,Timer11 PWM output,ICSS-G0 IEP0 CMP15 event,ICSS-G0 IEP1 CMP15 event,ICSS-G1 IEP0 CMP15 event,ICSS-G1 IEP1 CMP15 event,MCU Timer4 PWM output,MCU Timer5 PWM output,MCU Timer6 PWM output,MCU Timer7 PWM output,MCU Timer8 PWM output,MCU Timer9 PWM output,Reserved (tied 0h),Reserved (tied 0h)"
line.long 0x04 "CTRLMMR_MCU_ADC1_CTRL,Controls operation of MCU ADC1"
bitfld.long 0x04 16. "GPI_MODE_EN,Enables MCU_ADC1 data pins to be used as general purpose inputs when set" "0,1"
bitfld.long 0x04 0.--4. "TRIG_SEL,Selects the source of the ADC hardware event trigger" "MCU_ADC_EXT_TRIGGER0 pin,MCU_ADC_EXT_TRIGGER1 pin,eHRPWM SOCA event,eHRPWM SOCB event,MCU Timer0 PWM output,MCU Timer1 PWM output,MCU Timer2 PWM output,MCU Timer3 PWM output,Timer0 PWM output,Timer1 PWM output,Timer2 PWM output,Timer3 PWM output,Timer4 PWM output,Timer5 PWM output,Timer6 PWM output,Timer7 PWM output,Timer8 PWM output,Timer9 PWM output,Timer10 PWM output,Timer11 PWM output,ICSS-G0 IEP0 CMP15 event,ICSS-G0 IEP1 CMP15 event,ICSS-G1 IEP0 CMP15 event,ICSS-G1 IEP1 CMP15 event,MCU Timer4 PWM output,MCU Timer5 PWM output,MCU Timer6 PWM output,MCU Timer7 PWM output,MCU Timer8 PWM output,MCU Timer9 PWM output,Reserved (tied 0h),Reserved (tied 0h)"
group.long 0x4200++0x27
line.long 0x00 "CTRLMMR_MCU_TIMER0_CTRL,Controls MCU Timer0 operation"
bitfld.long 0x00 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x04 "CTRLMMR_MCU_TIMER1_CTRL,Controls MCU Timer1 operation"
bitfld.long 0x04 8. "CASCADE_EN,When set enables cascading of MCU_TIMER1 to MCU_TIMER0" "0,1"
bitfld.long 0x04 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x08 "CTRLMMR_MCU_TIMER2_CTRL,Controls MCU Timer2 operation"
bitfld.long 0x08 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x0C "CTRLMMR_MCU_TIMER3_CTRL,Controls MCU Timer3 operation"
bitfld.long 0x0C 8. "CASCADE_EN,When set enables cascading of MCU_TIMER3 to MCU_TIMER2" "0,1"
bitfld.long 0x0C 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x10 "CTRLMMR_MCU_TIMER4_CTRL,Controls MCU Timer4 operation"
bitfld.long 0x10 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x14 "CTRLMMR_MCU_TIMER5_CTRL,Controls MCU Timer5 operation"
bitfld.long 0x14 8. "CASCADE_EN,When set enables cascading of MCU_TIMER5 to MCU_TIMER4" "0,1"
bitfld.long 0x14 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x18 "CTRLMMR_MCU_TIMER6_CTRL,Controls MCU Timer6 operation"
bitfld.long 0x18 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x1C "CTRLMMR_MCU_TIMER7_CTRL,Controls MCU Timer7 operation"
bitfld.long 0x1C 8. "CASCADE_EN,When set enables cascading of MCU_TIMER7 to MCU_TIMER6" "0,1"
bitfld.long 0x1C 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x20 "CTRLMMR_MCU_TIMER8_CTRL,Controls MCU Timer8 operation"
bitfld.long 0x20 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
line.long 0x24 "CTRLMMR_MCU_TIMER9_CTRL,Controls MCU Timer9 operation"
bitfld.long 0x24 8. "CASCADE_EN,When set enables cascading of MCU_TIMER9 to MCU_TIMER8" "0,1"
bitfld.long 0x24 0.--3. "CAP_SEL,Selects the MCU_TIMERIO input pin for capture input signal" "Use MCU_TIMER_IO0 pin,Use MCU_TIMER_IO1 pin,Use MCU_TIMER_IO2 pin,Use MCU_TIMER_IO3 pin,Use MCU_TIMER_IO4 pin,Use MCU_TIMER_IO5 pin,Use MCU_TIMER_IO6 pin,Use MCU_TIMER_IO7 pin,Use MCU_TIMER_IO8 pin,Use MCU_TIMER_IO9 pin,?..."
group.long 0x4280++0x27
line.long 0x00 "CTRLMMR_MCU_TIMERIO0_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x00 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO0 output" "MCU_TIMERIO0 is driven by MCU_TIMER0 output,MCU_TIMERIO0 is driven by MCU_TIMER1 output,MCU_TIMERIO0 is driven by MCU_TIMER2 output,MCU_TIMERIO0 is driven by MCU_TIMER3 output,MCU_TIMERIO0 is driven by MCU_TIMER4 output,MCU_TIMERIO0 is driven by MCU_TIMER5 output,MCU_TIMERIO0 is driven by MCU_TIMER6 output,MCU_TIMERIO0 is driven by MCU_TIMER7 output,MCU_TIMERIO0 is driven by MCU_TIMER8 output,MCU_TIMERIO0 is driven by MCU_TIMER9 output,MCU_TIMERIO0 is driven low,MCU_TIMERIO0 is driven high,MCU_TIMERIO0 is driven low,MCU_TIMERIO0 is driven high,MCU_TIMERIO0 is driven low,MCU_TIMERIO0 is driven high"
line.long 0x04 "CTRLMMR_MCU_TIMERIO1_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x04 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO1 output" "MCU_TIMERIO1 is driven by MCU_TIMER0 output,MCU_TIMERIO1 is driven by MCU_TIMER1 output,MCU_TIMERIO1 is driven by MCU_TIMER2 output,MCU_TIMERIO1 is driven by MCU_TIMER3 output,MCU_TIMERIO1 is driven by MCU_TIMER4 output,MCU_TIMERIO1 is driven by MCU_TIMER5 output,MCU_TIMERIO1 is driven by MCU_TIMER6 output,MCU_TIMERIO1 is driven by MCU_TIMER7 output,MCU_TIMERIO1 is driven by MCU_TIMER8 output,MCU_TIMERIO1 is driven by MCU_TIMER9 output,MCU_TIMERIO1 is driven low,MCU_TIMERIO1 is driven high,MCU_TIMERIO1 is driven low,MCU_TIMERIO1 is driven high,MCU_TIMERIO1 is driven low,MCU_TIMERIO1 is driven high"
line.long 0x08 "CTRLMMR_MCU_TIMERIO2_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x08 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO2 output" "MCU_TIMERIO2 is driven by MCU_TIMER0 output,MCU_TIMERIO2 is driven by MCU_TIMER1 output,MCU_TIMERIO2 is driven by MCU_TIMER2 output,MCU_TIMERIO2 is driven by MCU_TIMER3 output,MCU_TIMERIO2 is driven by MCU_TIMER4 output,MCU_TIMERIO2 is driven by MCU_TIMER5 output,MCU_TIMERIO2 is driven by MCU_TIMER6 output,MCU_TIMERIO2 is driven by MCU_TIMER7 output,MCU_TIMERIO2 is driven by MCU_TIMER8 output,MCU_TIMERIO2 is driven by MCU_TIMER9 output,MCU_TIMERIO2 is driven low,MCU_TIMERIO2 is driven high,MCU_TIMERIO2 is driven low,MCU_TIMERIO2 is driven high,MCU_TIMERIO2 is driven low,MCU_TIMERIO2 is driven high"
line.long 0x0C "CTRLMMR_MCU_TIMERIO3_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x0C 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO3 output" "MCU_TIMERIO3 is driven by MCU_TIMER0 output,MCU_TIMERIO3 is driven by MCU_TIMER1 output,MCU_TIMERIO3 is driven by MCU_TIMER2 output,MCU_TIMERIO3 is driven by MCU_TIMER3 output,MCU_TIMERIO3 is driven by MCU_TIMER4 output,MCU_TIMERIO3 is driven by MCU_TIMER5 output,MCU_TIMERIO3 is driven by MCU_TIMER6 output,MCU_TIMERIO3 is driven by MCU_TIMER7 output,MCU_TIMERIO3 is driven by MCU_TIMER8 output,MCU_TIMERIO3 is driven by MCU_TIMER9 output,MCU_TIMERIO3 is driven low,MCU_TIMERIO3 is driven high,MCU_TIMERIO3 is driven low,MCU_TIMERIO3 is driven high,MCU_TIMERIO3 is driven low,MCU_TIMERIO3 is driven high"
line.long 0x10 "CTRLMMR_MCU_TIMERIO4_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x10 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO4 output" "MCU_TIMERIO4 is driven by MCU_TIMER0 output,MCU_TIMERIO4 is driven by MCU_TIMER1 output,MCU_TIMERIO4 is driven by MCU_TIMER2 output,MCU_TIMERIO4 is driven by MCU_TIMER3 output,MCU_TIMERIO4 is driven by MCU_TIMER4 output,MCU_TIMERIO4 is driven by MCU_TIMER5 output,MCU_TIMERIO4 is driven by MCU_TIMER6 output,MCU_TIMERIO4 is driven by MCU_TIMER7 output,MCU_TIMERIO4 is driven by MCU_TIMER8 output,MCU_TIMERIO4 is driven by MCU_TIMER9 output,MCU_TIMERIO4 is driven low,MCU_TIMERIO4 is driven high,MCU_TIMERIO4 is driven low,MCU_TIMERIO4 is driven high,MCU_TIMERIO4 is driven low,MCU_TIMERIO4 is driven high"
line.long 0x14 "CTRLMMR_MCU_TIMERIO5_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x14 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO5 output" "MCU_TIMERIO5 is driven by MCU_TIMER0 output,MCU_TIMERIO5 is driven by MCU_TIMER1 output,MCU_TIMERIO5 is driven by MCU_TIMER2 output,MCU_TIMERIO5 is driven by MCU_TIMER3 output,MCU_TIMERIO5 is driven by MCU_TIMER4 output,MCU_TIMERIO5 is driven by MCU_TIMER5 output,MCU_TIMERIO5 is driven by MCU_TIMER6 output,MCU_TIMERIO5 is driven by MCU_TIMER7 output,MCU_TIMERIO5 is driven by MCU_TIMER8 output,MCU_TIMERIO5 is driven by MCU_TIMER9 output,MCU_TIMERIO5 is driven low,MCU_TIMERIO5 is driven high,MCU_TIMERIO5 is driven low,MCU_TIMERIO5 is driven high,MCU_TIMERIO5 is driven low,MCU_TIMERIO5 is driven high"
line.long 0x18 "CTRLMMR_MCU_TIMERIO6_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x18 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO6 output" "MCU_TIMERIO6 is driven by MCU_TIMER0 output,MCU_TIMERIO6 is driven by MCU_TIMER1 output,MCU_TIMERIO6 is driven by MCU_TIMER2 output,MCU_TIMERIO6 is driven by MCU_TIMER3 output,MCU_TIMERIO6 is driven by MCU_TIMER4 output,MCU_TIMERIO6 is driven by MCU_TIMER5 output,MCU_TIMERIO6 is driven by MCU_TIMER6 output,MCU_TIMERIO6 is driven by MCU_TIMER7 output,MCU_TIMERIO6 is driven by MCU_TIMER8 output,MCU_TIMERIO6 is driven by MCU_TIMER9 output,MCU_TIMERIO6 is driven low,MCU_TIMERIO6 is driven high,MCU_TIMERIO6 is driven low,MCU_TIMERIO6 is driven high,MCU_TIMERIO6 is driven low,MCU_TIMERIO6 is driven high"
line.long 0x1C "CTRLMMR_MCU_TIMERIO7_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x1C 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO7 output" "MCU_TIMERIO7 is driven by MCU_TIMER0 output,MCU_TIMERIO7 is driven by MCU_TIMER1 output,MCU_TIMERIO7 is driven by MCU_TIMER2 output,MCU_TIMERIO7 is driven by MCU_TIMER3 output,MCU_TIMERIO7 is driven by MCU_TIMER4 output,MCU_TIMERIO7 is driven by MCU_TIMER5 output,MCU_TIMERIO7 is driven by MCU_TIMER6 output,MCU_TIMERIO7 is driven by MCU_TIMER7 output,MCU_TIMERIO7 is driven by MCU_TIMER8 output,MCU_TIMERIO7 is driven by MCU_TIMER9 output,MCU_TIMERIO7 is driven low,MCU_TIMERIO7 is driven high,MCU_TIMERIO7 is driven low,MCU_TIMERIO7 is driven high,MCU_TIMERIO7 is driven low,MCU_TIMERIO7 is driven high"
line.long 0x20 "CTRLMMR_MCU_TIMERIO8_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x20 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO8 output" "MCU_TIMERIO8 is driven by MCU_TIMER0 output,MCU_TIMERIO8 is driven by MCU_TIMER1 output,MCU_TIMERIO8 is driven by MCU_TIMER2 output,MCU_TIMERIO8 is driven by MCU_TIMER3 output,MCU_TIMERIO8 is driven by MCU_TIMER4 output,MCU_TIMERIO8 is driven by MCU_TIMER5 output,MCU_TIMERIO8 is driven by MCU_TIMER6 output,MCU_TIMERIO8 is driven by MCU_TIMER7 output,MCU_TIMERIO8 is driven by MCU_TIMER8 output,MCU_TIMERIO8 is driven by MCU_TIMER9 output,MCU_TIMERIO8 is driven low,MCU_TIMERIO8 is driven high,MCU_TIMERIO8 is driven low,MCU_TIMERIO8 is driven high,MCU_TIMERIO8 is driven low,MCU_TIMERIO8 is driven high"
line.long 0x24 "CTRLMMR_MCU_TIMERIO9_CTRL,Controls MCU TimerIO muxing"
bitfld.long 0x24 0.--3. "OUT_SEL,Selects the source of the MCU_TIMERIO9 output" "MCU_TIMERIO9 is driven by MCU_TIMER0 output,MCU_TIMERIO9 is driven by MCU_TIMER1 output,MCU_TIMERIO9 is driven by MCU_TIMER2 output,MCU_TIMERIO9 is driven by MCU_TIMER3 output,MCU_TIMERIO9 is driven by MCU_TIMER4 output,MCU_TIMERIO9 is driven by MCU_TIMER5 output,MCU_TIMERIO9 is driven by MCU_TIMER6 output,MCU_TIMERIO9 is driven by MCU_TIMER7 output,MCU_TIMERIO9 is driven by MCU_TIMER8 output,MCU_TIMERIO9 is driven by MCU_TIMER9 output,MCU_TIMERIO9 is driven low,MCU_TIMERIO9 is driven high,MCU_TIMERIO9 is driven low,MCU_TIMERIO9 is driven high,MCU_TIMERIO9 is driven low,MCU_TIMERIO9 is driven high"
group.long 0x5008++0x07
line.long 0x00 "CTRLMMR_MCU_LOCK1_KICK0,Lower 32-bits of Partition1 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_MCU_LOCK1_KICK1,Upper 32-bits of Partition 1 write lock key"
group.long 0x8010++0x03
line.long 0x00 "CTRLMMR_MCU_CLKOUT0_CTRL,Enables and selects clock source of CPSW MCU_CLKOUT0 pin"
bitfld.long 0x00 4. "CLK_EN,When set enables MCU_CLKOUT0 output" "0,1"
bitfld.long 0x00 0. "CLK_SEL,Selects MCU_CLKOUT0 clock source" "0,1"
group.long 0x8018++0x03
line.long 0x00 "CTRLMMR_MCU_EFUSE_CLKSEL,Selects the functional clock source for the MCU domain eFuse Controller"
bitfld.long 0x00 0. "CLK_SEL,Selects the clock source" "EFUSE_CLK (WKUP_HFOSC0_CLKOUT or CLK_12M_RC),MCU_SYSCLK0 / 8"
group.long 0x8020++0x07
line.long 0x00 "CTRLMMR_MCU_MCAN0_CLKSEL,Controls the functional clock source for MCU_MCAN0"
bitfld.long 0x00 0.--1. "CLK_SEL,MCU_MCAN MCAN_CLK selection" "0,1,2,3"
line.long 0x04 "CTRLMMR_MCU_MCAN1_CLKSEL,Controls the functional clock source for MCU_MCAN1"
bitfld.long 0x04 0.--1. "CLK_SEL,MCU_MCAN MCAN_CLK selection" "0,1,2,3"
group.long 0x8030++0x07
line.long 0x00 "CTRLMMR_MCU_OSPI0_CLKSEL,Controls the OSPI loopback clock source"
bitfld.long 0x00 4. "LOOPCLK_SEL,OBSPI0 Loopback clock source" "0,1"
bitfld.long 0x00 0. "CLK_SEL,OSPI0 reference clock selection" "0,1"
line.long 0x04 "CTRLMMR_MCU_OSPI1_CLKSEL,Controls the OSPI loopback clock source"
bitfld.long 0x04 4. "LOOPCLK_SEL,OBSPI1 Loopback clock source" "0,1"
bitfld.long 0x04 0. "CLK_SEL,OSPI1 reference clock selection" "0,1"
group.long 0x8040++0x07
line.long 0x00 "CTRLMMR_MCU_ADC0_CLKSEL,Controls the functional clock source for the MCU_ADC0"
bitfld.long 0x00 0.--1. "CLK_SEL,Selects the sampling clock source for ADC0" "WKUP_HFOSC0_CLKOUT,MCU_PLL1_HSDIV1_CLKOUT1,MCU_PLL0_HSDIV1_CLKOUT1,MCU_EXT_REFCLK0"
line.long 0x04 "CTRLMMR_MCU_ADC1_CLKSEL,Controls the functional clock source for the MCU_ADC1"
bitfld.long 0x04 0.--1. "CLK_SEL,Selects the sampling clock source for ADC1" "WKUP_HFOSC0_CLKOUT,MCU_PLL1_HSDIV1_CLKOUT1,MCU_PLL0_HSDIV1_CLKOUT1,MCU_EXT_REFCLK0"
group.long 0x8050++0x03
line.long 0x00 "CTRLMMR_MCU_ENET_CLKSEL,Controls selectable clock sources for the MCU Ethernet Port1"
bitfld.long 0x00 8.--11. "CPTS_CLKSEL,Selects the clock source for the CPSW2x Ethernet switch Common Platform Time Stamp module" "MAIN_PLL3_HSDIV1_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,MCU_CPTS_REF_CLK (pin),CPTS_RFT_CLK (pin),MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),SERDES0_IP2_LN0_TXMCLK,SERDES0_IP2_LN1_TXMCLK,SERDES1_IP2_LN0_TXMCLK,SERDES1_IP2_LN1_TXMCLK,SERDES2_IP2_LN0_TXMCLK,SERDES2_IP2_LN1_TXMCLK,SERDES3_IP2_LN0_TXMCLK,SERDES3_IP2_LN1_TXMCLK,MCU_PLL2_HSDIV1_CLKOUT,MCU_PLL2_HSDIV1_CLKOUT"
bitfld.long 0x00 0. "RMII_CLK_SEL,Selects the rmii clock (rmii_mhz_50_clk) source" "0,1"
group.long 0x8080++0x03
line.long 0x00 "CTRLMMR_MCU_R5_CORE0_CLKSEL,MCU Core 0 functional clock selection control"
bitfld.long 0x00 0. "CLK_SEL,Selects the Core 0 functional clock and mcu/interface clock ratio" "0,1"
group.long 0x8100++0x27
line.long 0x00 "CTRLMMR_MCU_TIMER0_CLKSEL,MCU Timer0 functional clock selection control"
bitfld.long 0x00 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x04 "CTRLMMR_MCU_TIMER1_CLKSEL,MCU Timer1 functional clock selection control"
bitfld.long 0x04 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x08 "CTRLMMR_MCU_TIMER2_CLKSEL,MCU Timer2 functional clock selection control"
bitfld.long 0x08 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x0C "CTRLMMR_MCU_TIMER3_CLKSEL,MCU Timer3 functional clock selection control"
bitfld.long 0x0C 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x10 "CTRLMMR_MCU_TIMER4_CLKSEL,MCU Timer4 functional clock selection control"
bitfld.long 0x10 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x14 "CTRLMMR_MCU_TIMER5_CLKSEL,MCU Timer5 functional clock selection control"
bitfld.long 0x14 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x18 "CTRLMMR_MCU_TIMER6_CLKSEL,MCU Timer6 functional clock selection control"
bitfld.long 0x18 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x1C "CTRLMMR_MCU_TIMER7_CLKSEL,MCU Timer7 functional clock selection control"
bitfld.long 0x1C 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x20 "CTRLMMR_MCU_TIMER8_CLKSEL,MCU Timer8 functional clock selection control"
bitfld.long 0x20 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
line.long 0x24 "CTRLMMR_MCU_TIMER9_CLKSEL,MCU Timer9 functional clock selection control"
bitfld.long 0x24 0.--2. "CLK_SEL,Timer functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,MCU_SYSCLK0 / 4,CLK_12M_RC,MCU_PLL2_HSDIV2_CLKOUT,MCU_EXT_REFCLK0,LPXOSC_CLKOUT,CPSW_GENF0,CLK_32K"
group.long 0x8180++0x07
line.long 0x00 "CTRLMMR_MCU_RTI0_CLKSEL,MCU RTI0 functional clock selection control"
bitfld.long 0x00 31. "WRTLOCK,When set locks further writes to" "0,1"
bitfld.long 0x00 0.--2. "CLK_SEL,RTI functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,?..."
line.long 0x04 "CTRLMMR_MCU_RTI1_CLKSEL,MCU RTI1 functional clock selection control"
bitfld.long 0x04 31. "WRTLOCK,When set locks further writes to" "0,1"
bitfld.long 0x04 0.--2. "CLK_SEL,RTI functional clock input select mux control" "WKUP_HFOSC0_CLKOUT,LPXOSC_CLKOUT,CLK_12M_RC,CLK_32K,?..."
group.long 0x81C0++0x03
line.long 0x00 "CTRLMMR_MCU_USART_CLKSEL,Controls the functional clock source for MCU_USART0"
bitfld.long 0x00 0. "CLK_SEL,MCU_USART0 FCLK selection" "0,1"
group.long 0x9008++0x07
line.long 0x00 "CTRLMMR_MCU_LOCK2_KICK0,Lower 32-bits of Partition2 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_MCU_LOCK2_KICK1,Upper 32-bits of Partition 2 write lock key"
group.long 0xC000++0x1F
line.long 0x00 "CTRLMMR_MCU_LBIST_CTRL,Configures and enables LBIST operation"
bitfld.long 0x00 31. "BIST_RESET,Reset LBIST macro" "0,1"
bitfld.long 0x00 24.--27. "BIST_RUN,Starts LBIST if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "RUNBIST_MODE,Runbist mode enable if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--9. "DC_DEF,Clock delay after scan_enable switching" "0,1,2,3"
newline
bitfld.long 0x00 7. "LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
bitfld.long 0x00 0.--4. "DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CTRLMMR_MCU_LBIST_PATCOUNT,Specifies the number of LBIST patterns to run"
hexmask.long.word 0x04 16.--29. 1. "STATIC_PC_DEF,Number of stuck-at patterns to run"
bitfld.long 0x04 8.--11. "SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 4.--7. "RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CTRLMMR_MCU_LBIST_SEED0,Specifies the 32 LSBs of the PRPG seed"
line.long 0x0C "CTRLMMR_MCU_LBIST_SEED1,Specifies the 21 MSBs of the PRPG seed"
hexmask.long.tbyte 0x0C 0.--20. 1. "PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CTRLMMR_MCU_LBIST_SPARE0,Spare LBIST control bits"
hexmask.long 0x10 2.--31. 1. "SPARE0,LBIST spare bits"
bitfld.long 0x10 1. "PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
newline
bitfld.long 0x10 0. "LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x14 "CTRLMMR_MCU_LBIST_SPARE1,Spare LBIST control bits"
line.long 0x18 "CTRLMMR_MCU_LBIST_STAT,Indicates LBIST status and provides MISR selection control"
rbitfld.long 0x18 31. "BIST_DONE,LBIST is done" "0,1"
rbitfld.long 0x18 15. "BIST_RUNNING,LBIST is running" "0,1"
newline
bitfld.long 0x18 8.--9. "OUT_MUX_CTL,Selects source of LBIST output" "0,1,2,3"
hexmask.long.byte 0x18 0.--7. 1. "MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x1C "CTRLMMR_MCU_LBIST_MISR,Contains LBIST MISR output value"
rgroup.long 0xC280++0x03
line.long 0x00 "CTRLMMR_MCU_LBIST_SIG,Contains expected MISR output value"
group.long 0xD008++0x07
line.long 0x00 "CTRLMMR_MCU_LOCK3_KICK0,Lower 32-bits of Partition3 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_MCU_LOCK3_KICK1,Upper 32-bits of Partition 3 write lock key"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x180)++0x03
line.long 0x00 "CTRLMMR_MCU_IPC_CLR$1,Acknowledge interprocessor communication interrupt to MCU R5 core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_CLR,Read returns current value"
bitfld.long 0x00 0. "IPC_CLR,Read returns current value" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x100)++0x03
line.long 0x00 "CTRLMMR_MCU_IPC_SET$1,Generate interprocessor communication interrupt to MCU R5 core0"
hexmask.long 0x00 4.--31. 1. "IPC_SRC_SET,Read returns current value"
bitfld.long 0x00 0. "IPC_SET,Read returns 0" "0,1"
repeat.end
tree.end
tree.end
tree "MCU_NAVSS0_UDMASS_ECCAGGR0"
tree "MCU_NAVSS0_UDMASS_ECCAGGR0"
base ad:0x28381000
rgroup.long 0x00++0x03
line.long 0x00 "MCU_NAVSS_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MCU_NAVSS_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MCU_NAVSS_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x13
line.long 0x00 "MCU_NAVSS_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MCU_NAVSS_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "UDMAP0_RPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 30. "UDMAP0_RPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 29. "UDMAP0_RFFW_RAMECC_PEND,Interrupt Pending Status for udmap0_rffw_ramecc_pend" "0,1"
newline
bitfld.long 0x04 28. "UDMAP0_TPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf4_ramecc_pend" "0,1"
newline
bitfld.long 0x04 27. "UDMAP0_TPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 26. "UDMAP0_TPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 25. "UDMAP0_TSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tstate_ramecc_pend" "0,1"
newline
bitfld.long 0x04 24. "UDMAP0_RPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend" "0,1"
newline
bitfld.long 0x04 23. "UDMAP0_RPCU_SB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 22. "UDMAP0_RPCU_SB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 21. "UDMAP0_RPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend" "0,1"
newline
bitfld.long 0x04 20. "UDMAP0_RPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend" "0,1"
newline
bitfld.long 0x04 19. "UDMAP0_RPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 18. "UDMAP0_RPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 17. "UDMAP0_TPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend" "0,1"
newline
bitfld.long 0x04 16. "UDMAP0_TPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend" "0,1"
newline
bitfld.long 0x04 15. "UDMAP0_TPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 14. "UDMAP0_TPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 13. "UDMAP0_RPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 12. "UDMAP0_RPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend" "0,1"
newline
bitfld.long 0x04 11. "UDMAP0_RPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 10. "UDMAP0_RPRQ_RAMECC_PEND,Interrupt Pending Status for udmap0_rprq_ramecc_pend" "0,1"
newline
bitfld.long 0x04 9. "UDMAP0_RPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcfg_ramecc_pend" "0,1"
newline
bitfld.long 0x04 8. "UDMAP0_RPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rpstate_ramecc_pend" "0,1"
newline
bitfld.long 0x04 7. "UDMAP0_TPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend" "0,1"
newline
bitfld.long 0x04 6. "UDMAP0_TPCU_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_ramecc_pend" "0,1"
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bitfld.long 0x04 5. "UDMAP0_TPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x04 4. "UDMAP0_TPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x04 3. "UDMAP0_TPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x04 2. "UDMAP0_TPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcfg_ramecc_pend" "0,1"
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bitfld.long 0x04 1. "UDMAP0_TPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tpstate_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
line.long 0x08 "MCU_NAVSS_SEC_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 31. "UDMASS_INTA0_SR_ECC_PEND,Interrupt Pending Status for udmass_inta0_sr_ecc_pend" "0,1"
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bitfld.long 0x08 30. "UDMASS_INTA0_IM_ECC_PEND,Interrupt Pending Status for udmass_inta0_im_ecc_pend" "0,1"
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bitfld.long 0x08 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 28. "RINGACC0_ECC_PEND,Interrupt Pending Status for ringacc0_ecc_pend" "0,1"
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bitfld.long 0x08 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x08 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x08 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x08 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x08 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x08 22. "UDMAP0_RRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_rrngocc_ramecc_pend" "0,1"
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bitfld.long 0x08 21. "UDMAP0_TRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_trngocc_ramecc_pend" "0,1"
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bitfld.long 0x08 20. "UDMAP0_PSILTID_RAMECC_PEND,Interrupt Pending Status for udmap0_psiltid_ramecc_pend" "0,1"
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bitfld.long 0x08 19. "UDMAP0_PSILR_RAMECC_PEND,Interrupt Pending Status for udmap0_psilr_ramecc_pend" "0,1"
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bitfld.long 0x08 18. "UDMAP0_SDEC3_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec3_ramecc_pend" "0,1"
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bitfld.long 0x08 17. "UDMAP0_SDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec0_ramecc_pend" "0,1"
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bitfld.long 0x08 16. "UDMAP0_RDEC2_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec2_ramecc_pend" "0,1"
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bitfld.long 0x08 15. "UDMAP0_RDEC1_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec1_ramecc_pend" "0,1"
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bitfld.long 0x08 14. "UDMAP0_RDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec0_ramecc_pend" "0,1"
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bitfld.long 0x08 13. "UDMAP0_REVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_revtcntr_ramecc_pend" "0,1"
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bitfld.long 0x08 12. "UDMAP0_TEVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend" "0,1"
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bitfld.long 0x08 11. "UDMAP0_STS_RAMECC3_PEND,Interrupt Pending Status for udmap0_sts_ramecc3_pend" "0,1"
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bitfld.long 0x08 10. "UDMAP0_STS_RAMECC2_PEND,Interrupt Pending Status for udmap0_sts_ramecc2_pend" "0,1"
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bitfld.long 0x08 9. "UDMAP0_STS_RAMECC1_PEND,Interrupt Pending Status for udmap0_sts_ramecc1_pend" "0,1"
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bitfld.long 0x08 8. "UDMAP0_STS_RAMECC0_PEND,Interrupt Pending Status for udmap0_sts_ramecc0_pend" "0,1"
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bitfld.long 0x08 7. "UDMAP0_EH_RAMECC_PEND,Interrupt Pending Status for udmap0_eh_ramecc_pend" "0,1"
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bitfld.long 0x08 6. "UDMAP0_PROXY_RAMECC_PEND,Interrupt Pending Status for udmap0_proxy_ramecc_pend" "0,1"
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bitfld.long 0x08 5. "UDMAP0_RSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rstate_ramecc_pend" "0,1"
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bitfld.long 0x08 4. "UDMAP0_RFLOW1_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow1_ramecc_pend" "0,1"
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bitfld.long 0x08 3. "UDMAP0_RFLOW0_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow0_ramecc_pend" "0,1"
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bitfld.long 0x08 2. "UDMAP0_RPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf4_ramecc_pend" "0,1"
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bitfld.long 0x08 1. "UDMAP0_RPCF3_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf3_ramecc_pend" "0,1"
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bitfld.long 0x08 0. "UDMAP0_RPCF2_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf2_ramecc_pend" "0,1"
line.long 0x0C "MCU_NAVSS_SEC_STATUS_REG2,Interrupt Status Register 2"
bitfld.long 0x0C 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 2. "UDMASS_INTA0_GC_ECC_PEND,Interrupt Pending Status for udmass_inta0_gc_ecc_pend" "0,1"
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bitfld.long 0x0C 1. "UDMASS_INTA0_MC_ECC_PEND,Interrupt Pending Status for udmass_inta0_mc_ecc_pend" "0,1"
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bitfld.long 0x0C 0. "UDMASS_INTA0_LC_ECC_PEND,Interrupt Pending Status for udmass_inta0_lc_ecc_pend" "0,1"
line.long 0x10 "MCU_NAVSS_SEC_STATUS_REG3,Interrupt Status Register 3"
bitfld.long 0x10 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1"
group.long 0x80++0x0F
line.long 0x00 "MCU_NAVSS_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "UDMAP0_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 30. "UDMAP0_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 29. "UDMAP0_RFFW_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rffw_ramecc_pend" "0,1"
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bitfld.long 0x00 28. "UDMAP0_TPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend" "0,1"
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bitfld.long 0x00 27. "UDMAP0_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 26. "UDMAP0_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 25. "UDMAP0_TSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tstate_ramecc_pend" "0,1"
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bitfld.long 0x00 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend" "0,1"
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bitfld.long 0x00 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend" "0,1"
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bitfld.long 0x00 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 10. "UDMAP0_RPRQ_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rprq_ramecc_pend" "0,1"
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bitfld.long 0x00 9. "UDMAP0_RPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 6. "UDMAP0_TPCU_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend" "0,1"
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bitfld.long 0x00 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 2. "UDMAP0_TPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
line.long 0x04 "MCU_NAVSS_SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 31. "UDMASS_INTA0_SR_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend" "0,1"
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bitfld.long 0x04 30. "UDMASS_INTA0_IM_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_im_ecc_pend" "0,1"
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bitfld.long 0x04 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 28. "RINGACC0_ECC_ENABLE_SET,Interrupt Enable Set Register for ringacc0_ecc_pend" "0,1"
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bitfld.long 0x04 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x04 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 20. "UDMAP0_PSILTID_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend" "0,1"
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bitfld.long 0x04 19. "UDMAP0_PSILR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psilr_ramecc_pend" "0,1"
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bitfld.long 0x04 18. "UDMAP0_SDEC3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend" "0,1"
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bitfld.long 0x04 17. "UDMAP0_SDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 16. "UDMAP0_RDEC2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend" "0,1"
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bitfld.long 0x04 15. "UDMAP0_RDEC1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend" "0,1"
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bitfld.long 0x04 14. "UDMAP0_RDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 11. "UDMAP0_STS_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc3_pend" "0,1"
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bitfld.long 0x04 10. "UDMAP0_STS_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc2_pend" "0,1"
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bitfld.long 0x04 9. "UDMAP0_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc1_pend" "0,1"
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bitfld.long 0x04 8. "UDMAP0_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc0_pend" "0,1"
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bitfld.long 0x04 7. "UDMAP0_EH_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_eh_ramecc_pend" "0,1"
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bitfld.long 0x04 6. "UDMAP0_PROXY_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_proxy_ramecc_pend" "0,1"
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bitfld.long 0x04 5. "UDMAP0_RSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rstate_ramecc_pend" "0,1"
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bitfld.long 0x04 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend" "0,1"
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bitfld.long 0x04 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend" "0,1"
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bitfld.long 0x04 2. "UDMAP0_RPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend" "0,1"
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bitfld.long 0x04 1. "UDMAP0_RPCF3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "UDMAP0_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend" "0,1"
line.long 0x08 "MCU_NAVSS_SEC_ENABLE_SET_REG2,Interrupt Enable Set Register 2"
bitfld.long 0x08 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 2. "UDMASS_INTA0_GC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend" "0,1"
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bitfld.long 0x08 1. "UDMASS_INTA0_MC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend" "0,1"
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bitfld.long 0x08 0. "UDMASS_INTA0_LC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_lc_ecc_pend" "0,1"
line.long 0x0C "MCU_NAVSS_SEC_ENABLE_SET_REG3,Interrupt Enable Set Register 3"
bitfld.long 0x0C 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
group.long 0xC0++0x0F
line.long 0x00 "MCU_NAVSS_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "UDMAP0_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 30. "UDMAP0_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 29. "UDMAP0_RFFW_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend" "0,1"
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bitfld.long 0x00 28. "UDMAP0_TPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend" "0,1"
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bitfld.long 0x00 27. "UDMAP0_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 26. "UDMAP0_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 25. "UDMAP0_TSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend" "0,1"
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bitfld.long 0x00 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend" "0,1"
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bitfld.long 0x00 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend" "0,1"
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bitfld.long 0x00 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 10. "UDMAP0_RPRQ_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend" "0,1"
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bitfld.long 0x00 9. "UDMAP0_RPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 6. "UDMAP0_TPCU_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend" "0,1"
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bitfld.long 0x00 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 2. "UDMAP0_TPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
line.long 0x04 "MCU_NAVSS_SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 31. "UDMASS_INTA0_SR_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend" "0,1"
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bitfld.long 0x04 30. "UDMASS_INTA0_IM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend" "0,1"
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bitfld.long 0x04 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 28. "RINGACC0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc0_ecc_pend" "0,1"
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bitfld.long 0x04 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x04 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 20. "UDMAP0_PSILTID_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend" "0,1"
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bitfld.long 0x04 19. "UDMAP0_PSILR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend" "0,1"
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bitfld.long 0x04 18. "UDMAP0_SDEC3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend" "0,1"
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bitfld.long 0x04 17. "UDMAP0_SDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 16. "UDMAP0_RDEC2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend" "0,1"
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bitfld.long 0x04 15. "UDMAP0_RDEC1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend" "0,1"
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bitfld.long 0x04 14. "UDMAP0_RDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 11. "UDMAP0_STS_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend" "0,1"
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bitfld.long 0x04 10. "UDMAP0_STS_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend" "0,1"
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bitfld.long 0x04 9. "UDMAP0_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend" "0,1"
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bitfld.long 0x04 8. "UDMAP0_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend" "0,1"
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bitfld.long 0x04 7. "UDMAP0_EH_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_eh_ramecc_pend" "0,1"
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bitfld.long 0x04 6. "UDMAP0_PROXY_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend" "0,1"
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bitfld.long 0x04 5. "UDMAP0_RSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend" "0,1"
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bitfld.long 0x04 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend" "0,1"
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bitfld.long 0x04 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend" "0,1"
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bitfld.long 0x04 2. "UDMAP0_RPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend" "0,1"
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bitfld.long 0x04 1. "UDMAP0_RPCF3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "UDMAP0_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend" "0,1"
line.long 0x08 "MCU_NAVSS_SEC_ENABLE_CLR_REG2,Interrupt Enable Clear Register 2"
bitfld.long 0x08 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 2. "UDMASS_INTA0_GC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend" "0,1"
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bitfld.long 0x08 1. "UDMASS_INTA0_MC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend" "0,1"
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bitfld.long 0x08 0. "UDMASS_INTA0_LC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_lc_ecc_pend" "0,1"
line.long 0x0C "MCU_NAVSS_SEC_ENABLE_CLR_REG3,Interrupt Enable Clear Register 3"
bitfld.long 0x0C 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
group.long 0x13C++0x13
line.long 0x00 "MCU_NAVSS_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MCU_NAVSS_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "UDMAP0_RPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf1_ramecc_pend" "0,1"
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bitfld.long 0x04 30. "UDMAP0_RPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf0_ramecc_pend" "0,1"
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bitfld.long 0x04 29. "UDMAP0_RFFW_RAMECC_PEND,Interrupt Pending Status for udmap0_rffw_ramecc_pend" "0,1"
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bitfld.long 0x04 28. "UDMAP0_TPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf4_ramecc_pend" "0,1"
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bitfld.long 0x04 27. "UDMAP0_TPCF1_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf1_ramecc_pend" "0,1"
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bitfld.long 0x04 26. "UDMAP0_TPCF0_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcf0_ramecc_pend" "0,1"
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bitfld.long 0x04 25. "UDMAP0_TSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tstate_ramecc_pend" "0,1"
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bitfld.long 0x04 24. "UDMAP0_RPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x04 23. "UDMAP0_RPCU_SB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb1_ramecc_pend" "0,1"
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bitfld.long 0x04 22. "UDMAP0_RPCU_SB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcu_sb0_ramecc_pend" "0,1"
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bitfld.long 0x04 21. "UDMAP0_RPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x04 20. "UDMAP0_RPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x04 19. "UDMAP0_RPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x04 18. "UDMAP0_RPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_rptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x04 17. "UDMAP0_TPTRCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x04 16. "UDMAP0_TPTRSB2_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x04 15. "UDMAP0_TPTRSB1_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x04 14. "UDMAP0_TPTRSB0_RAMECC_PEND,Interrupt Pending Status for udmap0_tptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x04 13. "UDMAP0_RPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x04 12. "UDMAP0_RPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x04 11. "UDMAP0_RPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_rpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x04 10. "UDMAP0_RPRQ_RAMECC_PEND,Interrupt Pending Status for udmap0_rprq_ramecc_pend" "0,1"
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bitfld.long 0x04 9. "UDMAP0_RPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcfg_ramecc_pend" "0,1"
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bitfld.long 0x04 8. "UDMAP0_RPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rpstate_ramecc_pend" "0,1"
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bitfld.long 0x04 7. "UDMAP0_TPCU_CNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x04 6. "UDMAP0_TPCU_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcu_ramecc_pend" "0,1"
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bitfld.long 0x04 5. "UDMAP0_TPBUF_PF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x04 4. "UDMAP0_TPBUF_DF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x04 3. "UDMAP0_TPBUF_CF_RAMECC_PEND,Interrupt Pending Status for udmap0_tpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x04 2. "UDMAP0_TPCFG_RAMECC_PEND,Interrupt Pending Status for udmap0_tpcfg_ramecc_pend" "0,1"
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bitfld.long 0x04 1. "UDMAP0_TPSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_tpstate_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
line.long 0x08 "MCU_NAVSS_DED_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 31. "UDMASS_INTA0_SR_ECC_PEND,Interrupt Pending Status for udmass_inta0_sr_ecc_pend" "0,1"
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bitfld.long 0x08 30. "UDMASS_INTA0_IM_ECC_PEND,Interrupt Pending Status for udmass_inta0_im_ecc_pend" "0,1"
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bitfld.long 0x08 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 28. "RINGACC0_ECC_PEND,Interrupt Pending Status for ringacc0_ecc_pend" "0,1"
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bitfld.long 0x08 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x08 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x08 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x08 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x08 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x08 22. "UDMAP0_RRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_rrngocc_ramecc_pend" "0,1"
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bitfld.long 0x08 21. "UDMAP0_TRNGOCC_RAMECC_PEND,Interrupt Pending Status for udmap0_trngocc_ramecc_pend" "0,1"
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bitfld.long 0x08 20. "UDMAP0_PSILTID_RAMECC_PEND,Interrupt Pending Status for udmap0_psiltid_ramecc_pend" "0,1"
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bitfld.long 0x08 19. "UDMAP0_PSILR_RAMECC_PEND,Interrupt Pending Status for udmap0_psilr_ramecc_pend" "0,1"
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bitfld.long 0x08 18. "UDMAP0_SDEC3_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec3_ramecc_pend" "0,1"
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bitfld.long 0x08 17. "UDMAP0_SDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_sdec0_ramecc_pend" "0,1"
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bitfld.long 0x08 16. "UDMAP0_RDEC2_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec2_ramecc_pend" "0,1"
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bitfld.long 0x08 15. "UDMAP0_RDEC1_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec1_ramecc_pend" "0,1"
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bitfld.long 0x08 14. "UDMAP0_RDEC0_RAMECC_PEND,Interrupt Pending Status for udmap0_rdec0_ramecc_pend" "0,1"
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bitfld.long 0x08 13. "UDMAP0_REVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_revtcntr_ramecc_pend" "0,1"
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bitfld.long 0x08 12. "UDMAP0_TEVTCNTR_RAMECC_PEND,Interrupt Pending Status for udmap0_tevtcntr_ramecc_pend" "0,1"
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bitfld.long 0x08 11. "UDMAP0_STS_RAMECC3_PEND,Interrupt Pending Status for udmap0_sts_ramecc3_pend" "0,1"
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bitfld.long 0x08 10. "UDMAP0_STS_RAMECC2_PEND,Interrupt Pending Status for udmap0_sts_ramecc2_pend" "0,1"
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bitfld.long 0x08 9. "UDMAP0_STS_RAMECC1_PEND,Interrupt Pending Status for udmap0_sts_ramecc1_pend" "0,1"
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bitfld.long 0x08 8. "UDMAP0_STS_RAMECC0_PEND,Interrupt Pending Status for udmap0_sts_ramecc0_pend" "0,1"
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bitfld.long 0x08 7. "UDMAP0_EH_RAMECC_PEND,Interrupt Pending Status for udmap0_eh_ramecc_pend" "0,1"
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bitfld.long 0x08 6. "UDMAP0_PROXY_RAMECC_PEND,Interrupt Pending Status for udmap0_proxy_ramecc_pend" "0,1"
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bitfld.long 0x08 5. "UDMAP0_RSTATE_RAMECC_PEND,Interrupt Pending Status for udmap0_rstate_ramecc_pend" "0,1"
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bitfld.long 0x08 4. "UDMAP0_RFLOW1_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow1_ramecc_pend" "0,1"
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bitfld.long 0x08 3. "UDMAP0_RFLOW0_RAMECC_PEND,Interrupt Pending Status for udmap0_rflow0_ramecc_pend" "0,1"
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bitfld.long 0x08 2. "UDMAP0_RPCF4_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf4_ramecc_pend" "0,1"
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bitfld.long 0x08 1. "UDMAP0_RPCF3_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf3_ramecc_pend" "0,1"
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bitfld.long 0x08 0. "UDMAP0_RPCF2_RAMECC_PEND,Interrupt Pending Status for udmap0_rpcf2_ramecc_pend" "0,1"
line.long 0x0C "MCU_NAVSS_DED_STATUS_REG2,Interrupt Status Register 2"
bitfld.long 0x0C 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_navss_mcu_udmass_psilss0_l2p_psilcfg0_cfgstrm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_navss_mcu_udmass_psilss0_l2p_udmap0_cfgstrm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_navss_mcu_udmass_psilss0_l2p_udmass_inta0_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu1_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_navss_mcu_udmass_psilss0_l2p_pdma_mcu0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x0C 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_navss_mcu_udmass_psilss0_udmap0_cfgstrm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu1_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_navss_mcu_udmass_psilss0_pdma_mcu0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for navss_mcu_udmass_psilss0_navss_psil_rt_bridge_navss_mcu_udmass_psilss0_navss_psil_rt_bridge_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x0C 2. "UDMASS_INTA0_GC_ECC_PEND,Interrupt Pending Status for udmass_inta0_gc_ecc_pend" "0,1"
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bitfld.long 0x0C 1. "UDMASS_INTA0_MC_ECC_PEND,Interrupt Pending Status for udmass_inta0_mc_ecc_pend" "0,1"
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bitfld.long 0x0C 0. "UDMASS_INTA0_LC_ECC_PEND,Interrupt Pending Status for udmass_inta0_lc_ecc_pend" "0,1"
line.long 0x10 "MCU_NAVSS_DED_STATUS_REG3,Interrupt Status Register 3"
bitfld.long 0x10 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_PEND,Interrupt Pending Status for.." "0,1"
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bitfld.long 0x10 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_PEND,Interrupt Pending Status for.." "0,1"
group.long 0x180++0x0F
line.long 0x00 "MCU_NAVSS_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "UDMAP0_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 30. "UDMAP0_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 29. "UDMAP0_RFFW_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rffw_ramecc_pend" "0,1"
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bitfld.long 0x00 28. "UDMAP0_TPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf4_ramecc_pend" "0,1"
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bitfld.long 0x00 27. "UDMAP0_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 26. "UDMAP0_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 25. "UDMAP0_TSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tstate_ramecc_pend" "0,1"
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bitfld.long 0x00 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb1_ramecc_pend" "0,1"
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bitfld.long 0x00 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcu_sb0_ramecc_pend" "0,1"
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bitfld.long 0x00 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 10. "UDMAP0_RPRQ_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rprq_ramecc_pend" "0,1"
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bitfld.long 0x00 9. "UDMAP0_RPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 6. "UDMAP0_TPCU_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcu_ramecc_pend" "0,1"
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bitfld.long 0x00 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 2. "UDMAP0_TPCFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
line.long 0x04 "MCU_NAVSS_DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 31. "UDMASS_INTA0_SR_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_sr_ecc_pend" "0,1"
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bitfld.long 0x04 30. "UDMASS_INTA0_IM_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_im_ecc_pend" "0,1"
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bitfld.long 0x04 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 28. "RINGACC0_ECC_ENABLE_SET,Interrupt Enable Set Register for ringacc0_ecc_pend" "0,1"
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bitfld.long 0x04 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x04 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rrngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_trngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 20. "UDMAP0_PSILTID_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psiltid_ramecc_pend" "0,1"
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bitfld.long 0x04 19. "UDMAP0_PSILR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_psilr_ramecc_pend" "0,1"
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bitfld.long 0x04 18. "UDMAP0_SDEC3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec3_ramecc_pend" "0,1"
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bitfld.long 0x04 17. "UDMAP0_SDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_sdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 16. "UDMAP0_RDEC2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec2_ramecc_pend" "0,1"
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bitfld.long 0x04 15. "UDMAP0_RDEC1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec1_ramecc_pend" "0,1"
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bitfld.long 0x04 14. "UDMAP0_RDEC0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_revtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_tevtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 11. "UDMAP0_STS_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc3_pend" "0,1"
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bitfld.long 0x04 10. "UDMAP0_STS_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc2_pend" "0,1"
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bitfld.long 0x04 9. "UDMAP0_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc1_pend" "0,1"
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bitfld.long 0x04 8. "UDMAP0_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for udmap0_sts_ramecc0_pend" "0,1"
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bitfld.long 0x04 7. "UDMAP0_EH_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_eh_ramecc_pend" "0,1"
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bitfld.long 0x04 6. "UDMAP0_PROXY_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_proxy_ramecc_pend" "0,1"
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bitfld.long 0x04 5. "UDMAP0_RSTATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rstate_ramecc_pend" "0,1"
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bitfld.long 0x04 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow1_ramecc_pend" "0,1"
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bitfld.long 0x04 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rflow0_ramecc_pend" "0,1"
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bitfld.long 0x04 2. "UDMAP0_RPCF4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf4_ramecc_pend" "0,1"
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bitfld.long 0x04 1. "UDMAP0_RPCF3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf3_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "UDMAP0_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for udmap0_rpcf2_ramecc_pend" "0,1"
line.long 0x08 "MCU_NAVSS_DED_ENABLE_SET_REG2,Interrupt Enable Set Register 2"
bitfld.long 0x08 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x08 2. "UDMASS_INTA0_GC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_gc_ecc_pend" "0,1"
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bitfld.long 0x08 1. "UDMASS_INTA0_MC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_mc_ecc_pend" "0,1"
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bitfld.long 0x08 0. "UDMASS_INTA0_LC_ECC_ENABLE_SET,Interrupt Enable Set Register for udmass_inta0_lc_ecc_pend" "0,1"
line.long 0x0C "MCU_NAVSS_DED_ENABLE_SET_REG3,Interrupt Enable Set Register 3"
bitfld.long 0x0C 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
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bitfld.long 0x0C 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_SET,Interrupt Enable Set Register for.." "0,1"
group.long 0x1C0++0x0F
line.long 0x00 "MCU_NAVSS_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "UDMAP0_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 30. "UDMAP0_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 29. "UDMAP0_RFFW_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rffw_ramecc_pend" "0,1"
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bitfld.long 0x00 28. "UDMAP0_TPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf4_ramecc_pend" "0,1"
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bitfld.long 0x00 27. "UDMAP0_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf1_ramecc_pend" "0,1"
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bitfld.long 0x00 26. "UDMAP0_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcf0_ramecc_pend" "0,1"
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bitfld.long 0x00 25. "UDMAP0_TSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tstate_ramecc_pend" "0,1"
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bitfld.long 0x00 24. "UDMAP0_RPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 23. "UDMAP0_RPCU_SB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb1_ramecc_pend" "0,1"
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bitfld.long 0x00 22. "UDMAP0_RPCU_SB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcu_sb0_ramecc_pend" "0,1"
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bitfld.long 0x00 21. "UDMAP0_RPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 20. "UDMAP0_RPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 19. "UDMAP0_RPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 18. "UDMAP0_RPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 17. "UDMAP0_TPTRCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 16. "UDMAP0_TPTRSB2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb2_ramecc_pend" "0,1"
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bitfld.long 0x00 15. "UDMAP0_TPTRSB1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb1_ramecc_pend" "0,1"
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bitfld.long 0x00 14. "UDMAP0_TPTRSB0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tptrsb0_ramecc_pend" "0,1"
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bitfld.long 0x00 13. "UDMAP0_RPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 12. "UDMAP0_RPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 11. "UDMAP0_RPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 10. "UDMAP0_RPRQ_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rprq_ramecc_pend" "0,1"
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bitfld.long 0x00 9. "UDMAP0_RPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 8. "UDMAP0_RPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 7. "UDMAP0_TPCU_CNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_cntr_ramecc_pend" "0,1"
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bitfld.long 0x00 6. "UDMAP0_TPCU_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcu_ramecc_pend" "0,1"
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bitfld.long 0x00 5. "UDMAP0_TPBUF_PF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_pf_ramecc_pend" "0,1"
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bitfld.long 0x00 4. "UDMAP0_TPBUF_DF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_df_ramecc_pend" "0,1"
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bitfld.long 0x00 3. "UDMAP0_TPBUF_CF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpbuf_cf_ramecc_pend" "0,1"
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bitfld.long 0x00 2. "UDMAP0_TPCFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpcfg_ramecc_pend" "0,1"
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bitfld.long 0x00 1. "UDMAP0_TPSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tpstate_ramecc_pend" "0,1"
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bitfld.long 0x00 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
line.long 0x04 "MCU_NAVSS_DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 31. "UDMASS_INTA0_SR_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_sr_ecc_pend" "0,1"
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bitfld.long 0x04 30. "UDMASS_INTA0_IM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_im_ecc_pend" "0,1"
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bitfld.long 0x04 29. "NAVSS_MCU_UDMASS_UDMASS_INTA0_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmass_inta0_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 28. "RINGACC0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc0_ecc_pend" "0,1"
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bitfld.long 0x04 27. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 26. "NAVSS_MCU_UDMASS_RINGACC0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_ringacc0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 25. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_2_pend" "0,1"
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bitfld.long 0x04 24. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_1_pend" "0,1"
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bitfld.long 0x04 23. "NAVSS_MCU_UDMASS_UDMAP0_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_udmap0_edc_ctrl_busecc_0_pend" "0,1"
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bitfld.long 0x04 22. "UDMAP0_RRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rrngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 21. "UDMAP0_TRNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_trngocc_ramecc_pend" "0,1"
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bitfld.long 0x04 20. "UDMAP0_PSILTID_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psiltid_ramecc_pend" "0,1"
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bitfld.long 0x04 19. "UDMAP0_PSILR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_psilr_ramecc_pend" "0,1"
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bitfld.long 0x04 18. "UDMAP0_SDEC3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec3_ramecc_pend" "0,1"
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bitfld.long 0x04 17. "UDMAP0_SDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 16. "UDMAP0_RDEC2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec2_ramecc_pend" "0,1"
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bitfld.long 0x04 15. "UDMAP0_RDEC1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec1_ramecc_pend" "0,1"
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bitfld.long 0x04 14. "UDMAP0_RDEC0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rdec0_ramecc_pend" "0,1"
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bitfld.long 0x04 13. "UDMAP0_REVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_revtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 12. "UDMAP0_TEVTCNTR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_tevtcntr_ramecc_pend" "0,1"
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bitfld.long 0x04 11. "UDMAP0_STS_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc3_pend" "0,1"
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bitfld.long 0x04 10. "UDMAP0_STS_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc2_pend" "0,1"
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bitfld.long 0x04 9. "UDMAP0_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc1_pend" "0,1"
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bitfld.long 0x04 8. "UDMAP0_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_sts_ramecc0_pend" "0,1"
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bitfld.long 0x04 7. "UDMAP0_EH_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_eh_ramecc_pend" "0,1"
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bitfld.long 0x04 6. "UDMAP0_PROXY_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_proxy_ramecc_pend" "0,1"
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bitfld.long 0x04 5. "UDMAP0_RSTATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rstate_ramecc_pend" "0,1"
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bitfld.long 0x04 4. "UDMAP0_RFLOW1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow1_ramecc_pend" "0,1"
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bitfld.long 0x04 3. "UDMAP0_RFLOW0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rflow0_ramecc_pend" "0,1"
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bitfld.long 0x04 2. "UDMAP0_RPCF4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf4_ramecc_pend" "0,1"
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bitfld.long 0x04 1. "UDMAP0_RPCF3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf3_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "UDMAP0_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for udmap0_rpcf2_ramecc_pend" "0,1"
line.long 0x08 "MCU_NAVSS_DED_ENABLE_CLR_REG2,Interrupt Enable Clear Register 2"
bitfld.long 0x08 31. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 30. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 29. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 28. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_D_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 27. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 26. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 25. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 24. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SAFEG_RT_CPSW0_PSIL_S_DATA_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_DATA_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 23. "NAVSS_MCU_UDMASS_PSILSS0_CFG_NAVSS_MCU_UDMASS_PSILSS0_CFG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cfg_navss_mcu_udmass_psilss0_cfg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 22. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 21. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 20. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 19. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 18. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 17. "NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_NAVSS_MCU_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_dmsc_evt_navss_mcu_udmass_psilss0_l2p_dmsc_evt_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 16. "NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_NAVSS_MCU_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_udmap0_strm_navss_mcu_udmass_psilss0_l2p_udmap0_strm_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 15. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 14. "NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 13. "NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_cpsw0_psil_navss_mcu_udmass_psilss0_l2p_cpsw0_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 12. "NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_NAVSS_MCU_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_l2p_navss_psil_navss_mcu_udmass_psilss0_l2p_navss_psil_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 11. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 10. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 9. "NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 8. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 7. "NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_udmap0_strm_safeg_navss_mcu_udmass_psilss0_udmap0_strm_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 6. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 5. "NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 4. "NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_NAVSS_MCU_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for navss_mcu_udmass_psilss0_cpsw0_psil_safeg_navss_mcu_udmass_psilss0_cpsw0_psil_safeg_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x08 3. "NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_NAVSS_MCU_UDMASS_PSILSS0_NAVSS_PSIL_RT_BRIDGE_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x08 2. "UDMASS_INTA0_GC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_gc_ecc_pend" "0,1"
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bitfld.long 0x08 1. "UDMASS_INTA0_MC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_mc_ecc_pend" "0,1"
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bitfld.long 0x08 0. "UDMASS_INTA0_LC_ECC_ENABLE_CLR,Interrupt Enable Clear Register for udmass_inta0_lc_ecc_pend" "0,1"
line.long 0x0C "MCU_NAVSS_DED_ENABLE_CLR_REG3,Interrupt Enable Clear Register 3"
bitfld.long 0x0C 23. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_4_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 22. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_3_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 21. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 20. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 19. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 18. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_D_DEF_EVT_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 17. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 16. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 15. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 14. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_NAVSS_MCU_UDMASS_PSILSS0_CBASS_ETL_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_ETL0_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 13. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 12. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 11. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 10. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 9. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 8. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 7. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_S_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_S_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 6. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 5. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_PDMA_MCU1_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 4. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_DST_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 3. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_NAVSS_MCU_UDMASS_PSILSS0_CBASS_RESP_SAFEG_RT_CPSW0_PSIL_D_RESP_P2P_BRIDGE_SAFEG_RT_CPSW0_PSIL_D_RESP_BRIDGE_SRC_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 2. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_2_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 1. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_1_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
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bitfld.long 0x0C 0. "NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_NAVSS_MCU_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_BUSECC_0_ENABLE_CLR,Interrupt Enable Clear Register for.." "0,1"
group.long 0x200++0x0F
line.long 0x00 "MCU_NAVSS_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
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bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MCU_NAVSS_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MCU_NAVSS_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MCU_NAVSS_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MCU_PLL0_CFG"
tree "MCU_PLL0_CFG"
base ad:0x40D00000
rgroup.long 0x00++0x03
line.long 0x00 "MCU_PLL0_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "MCU_PLL0_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x10++0x07
line.long 0x00 "MCU_PLL0_LOCKKEY0,- PLL0 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "MCU_PLL0_LOCKKEY1,- PLL0 Lock Key 1 RegisterAddr"
group.long 0x20++0x07
line.long 0x00 "MCU_PLL0_CTRL,- PLL0 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled,Delta-Sigma modulator is enabled"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "MCU_PLL0_STAT,- PLL0 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x30++0x0B
line.long 0x00 "MCU_PLL0_FREQ_CTRL0,- PLL0 Frequency Control 0 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "MCU_PLL0_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "MCU_PLL0_DIV_CTRL,- PLL0 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x40++0x07
line.long 0x00 "MCU_PLL0_SS_CTRL,PLL_SS_CTRL register for pll0"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "MCU_PLL0_SS_SPREAD,PLL_SS_SPREAD register for PLL0"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x07
line.long 0x00 "MCU_PLL0_HSDIV_CTRL0,HSDIV_CTRL0 register for pll0"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "MCU_PLL0_HSDIV_CTRL1,HSDIV_CTRL1 register for pll0"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x1000++0x03
line.long 0x00 "MCU_PLL1_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1008++0x03
line.long 0x00 "MCU_PLL1_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x1010++0x07
line.long 0x00 "MCU_PLL1_LOCKKEY0,- PLL1 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "MCU_PLL1_LOCKKEY1,- PLL1 Lock Key 1 RegisterAddr"
group.long 0x1020++0x07
line.long 0x00 "MCU_PLL1_CTRL,- PLL1 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "MCU_PLL1_STAT,- PLL1 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x1030++0x0B
line.long 0x00 "MCU_PLL1_FREQ_CTRL0,- PLL1 Frequency Control 1 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "MCU_PLL1_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "MCU_PLL1_DIV_CTRL,- PLL1 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x1040++0x07
line.long 0x00 "MCU_PLL1_SS_CTRL,PLL_SS_CTRL register for pll1"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "MCU_PLL1_SS_SPREAD,PLL_SS_SPREAD register for pll1"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1080++0x13
line.long 0x00 "MCU_PLL1_HSDIV_CTRL0,HSDIV_CTRL0 register for pll1"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "MCU_PLL1_HSDIV_CTRL1,HSDIV_CTRL1 register for pll1"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "MCU_PLL1_HSDIV_CTRL2,HSDIV_CTRL2 register for pll1"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "MCU_PLL1_HSDIV_CTRL3,HSDIV_CTRL3 register for pll1"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x10 "MCU_PLL1_HSDIV_CTRL4,HSDIV_CTRL4 register for pll1"
bitfld.long 0x10 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x2000++0x03
line.long 0x00 "MCU_PLL2_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2008++0x03
line.long 0x00 "MCU_PLL2_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x2010++0x07
line.long 0x00 "MCU_PLL2_LOCKKEY0,- PLL2 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "MCU_PLL2_LOCKKEY1,- PLL2 Lock Key 1 RegisterAddr"
group.long 0x2020++0x07
line.long 0x00 "MCU_PLL2_CTRL,- PLL2 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "MCU_PLL2_STAT,- PLL2 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x2030++0x0B
line.long 0x00 "MCU_PLL2_FREQ_CTRL0,- PLL2 Frequency Control 2 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "MCU_PLL2_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "MCU_PLL2_DIV_CTRL,- PLL2 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x2040++0x07
line.long 0x00 "MCU_PLL2_SS_CTRL,PLL_SS_CTRL register for pll2"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "MCU_PLL2_SS_SPREAD,PLL_SS_SPREAD register for pll2"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2080++0x13
line.long 0x00 "MCU_PLL2_HSDIV_CTRL0,HSDIV_CTRL0 register for pll2"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "MCU_PLL2_HSDIV_CTRL1,HSDIV_CTRL1 register for pll2"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "MCU_PLL2_HSDIV_CTRL2,HSDIV_CTRL2 register for pll2"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "MCU_PLL2_HSDIV_CTRL3,HSDIV_CTRL3 register for pll2"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x10 "MCU_PLL2_HSDIV_CTRL4,HSDIV_CTRL4 register for pll2"
bitfld.long 0x10 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
tree.end
tree.end
tree "MCU_SEC_MMR0_DBG_CTRL"
tree "MCU_SEC_MMR0_CFG0"
base ad:0x45A50000
rgroup.long 0x20++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_DEF,Defines the type of the processor cluster"
bitfld.long 0x00 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7"
abitfld.long 0x00 8.--15. "DSP_CORE_TYPE,DSP core type configuration" "0x00=C7x,0x01=C6x,0xFF=Not DSP"
abitfld.long 0x00 0.--7. "ARM_CORE_TYPE,ARM core type configuration" "0x00=A53,0x01=A57,0x10=R5,0xFF=Not ARM"
group.long 0x40++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CFG,Configures cluster level characteristics"
hexmask.long 0x00 4.--31. 1. "CLSTR_CFG_RSVD,Reserved for future use"
rbitfld.long 0x00 3. "LOCKSTEP_EN,Lockstep enable" "0,1"
bitfld.long 0x00 2. "DBG_NO_CLKSTOP,CPU clockstop behavior" "0,1"
bitfld.long 0x00 1. "TEINIT,Exception handling state at reset" "0,1"
newline
bitfld.long 0x00 0. "LOCKSTEP,When set Core0 and Core1 operate in lockstep mode" "0,1"
group.long 0x100++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE0_CFG,Configures the TCM and interrupt operation of R5 Core0"
bitfld.long 0x00 15. "NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts" "0,1"
bitfld.long 0x00 11. "TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator" "0,1"
bitfld.long 0x00 7. "BTCM_EN,Enable Core0 BTCM RAM at reset" "0,1"
bitfld.long 0x00 3. "ATCM_EN,Enable Core0 ATCM RAM at reset" "0,1"
group.long 0x110++0x07
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core0"
hexmask.long 0x00 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]"
line.long 0x04 "CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core0"
hexmask.long.word 0x04 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]"
group.long 0x120++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE0_PMCTRL,Configures Cluster Core0 power state"
bitfld.long 0x00 0. "CORE_HALT,Halt Core0.When 0 indicates that Core0 is in the Halt state" "0,1"
rgroup.long 0x130++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE0_PMSTAT,Shows Cluster Core0 power status"
bitfld.long 0x00 3. "CLK_GATE,Core0 Clocked stopped due to WFI or WFE state" "0,1"
bitfld.long 0x00 1. "WFE,Core0 WFE" "0,1"
bitfld.long 0x00 0. "WFI,Core0 WFI" "0,1"
group.long 0x180++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE1_CFG,Configures the TCM and interrupt operation of R5 Core1"
bitfld.long 0x00 15. "NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts" "0,1"
bitfld.long 0x00 11. "TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator" "0,1"
bitfld.long 0x00 7. "BTCM_EN,Enable Core1 BTCM RAM at reset" "0,1"
bitfld.long 0x00 3. "ATCM_EN,Enable Core1 ATCM RAM at reset" "0,1"
group.long 0x190++0x07
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core1"
hexmask.long 0x00 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]"
line.long 0x04 "CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core1"
hexmask.long.word 0x04 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]"
group.long 0x1A0++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE1_PMCTRL,Configures Cluster Core1 power state"
bitfld.long 0x00 0. "CORE_HALT,Halt Core1.When 0 indicates that Core1 is in the Halt state" "0,1"
rgroup.long 0x1B0++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE1_PMSTAT,Shows Cluster Core1 power status"
bitfld.long 0x00 3. "CLK_GATE,Core1 Clocked stopped due to WFI or WFE state" "0,1"
bitfld.long 0x00 1. "WFE,Core1 WFE" "0,1"
bitfld.long 0x00 0. "WFI,Core1 WFI" "0,1"
tree.end
tree "MCU_SEC_MMR0_DBG_CTRL"
base ad:0x45950000
group.long 0x00++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE0_DBG_CFG,Configures debug operation for Cluster Core0"
bitfld.long 0x00 12.--15. "DBGEN,Core0 Invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "NIDEN,Core0 Non-invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "CTRLMMR_MCUSEC_CLSTR0_CORE1_DBG_CFG,Configures debug operation for Cluster Core1"
bitfld.long 0x00 12.--15. "DBGEN,Core1 Invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "NIDEN,Core1 Non-invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "MLBSS"
tree "MLB0_MMR_MMRVBP"
base ad:0x2F80000
rgroup.long 0x00++0x03
line.long 0x00 "MLBSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x07
line.long 0x00 "MLBSS_STAT,The Status register provide general status bits for the mlbss"
bitfld.long 0x00 1. "MEM_INIT_DONE," "0,1"
line.long 0x04 "MLBSS_DMA_CTRL,The DMA Control register provide control bits for the DMA Vbusp"
bitfld.long 0x04 0.--2. "PRIORITY,DMA Vbusp priority" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "MLBSS_Configuration"
tree "MLB0_VBP2APB_WRAP_MLB_CFG_VBP_MLBDIM"
base ad:0x2F82000
group.long 0x00++0x03
line.long 0x00 "MLB_MLBC0,MediaLB Control 0 Register"
bitfld.long 0x00 15.--17. "FCNT,Number of frames per sub-buffer (synchronous channels)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14. "CTLRETRY,Control Tx packet retry" "0,1"
bitfld.long 0x00 12. "ASYRETRY,Asynchronous Tx packet retry" "0,1"
rbitfld.long 0x00 7. "MLBLK,MediaLB lock status" "0,1"
bitfld.long 0x00 5. "MLBPEN,MediaLB 6-pin enable" "0,1"
bitfld.long 0x00 2.--4. "MLBCLK,MediaLB clock speed select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "MLBEN,MediaLB enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "MLB_MS0,MediaLB Channel Status 0 Register"
group.long 0x14++0x03
line.long 0x00 "MLB_MS1,MediaLB Channel Status 1 Register"
group.long 0x20++0x07
line.long 0x00 "MLB_MSS,MediaLB System Status Register"
bitfld.long 0x00 5. "SERVREQ,Service request enabled" "0,1"
bitfld.long 0x00 4. "SWSYSCMD,Software system command detected (in the system quadlet)" "0,1"
bitfld.long 0x00 3. "CSSYSCMD,Channel scan system command detected (in the system quadlet)" "0,1"
bitfld.long 0x00 2. "ULKSYSCMD,Network unlock system command detected (in the system quadlet)" "0,1"
bitfld.long 0x00 1. "LKSYSCMD,Network lock system command detected (in the system quadlet)" "0,1"
bitfld.long 0x00 0. "RSTSYSCMD,Reset system command detected (in the system quadlet)" "0,1"
line.long 0x04 "MLB_MSD,MediaLB System Data Register"
hexmask.long.byte 0x04 24.--31. 1. "SD3,System data (byte 3)"
hexmask.long.byte 0x04 16.--23. 1. "SD2,System data (byte 2)"
hexmask.long.byte 0x04 8.--15. 1. "SD1,System data (byte 1)"
hexmask.long.byte 0x04 0.--7. 1. "SD0,System data (byte 0)"
group.long 0x2C++0x03
line.long 0x00 "MLB_MIEN,MediaLB Interrupt Enable Register"
bitfld.long 0x00 29. "CTX_BREAK,Control Tx break enable" "0,1"
bitfld.long 0x00 28. "CTX_PE,Control Tx protocol error enable" "0,1"
bitfld.long 0x00 27. "CTX_DONE,Control Tx packet done enable" "0,1"
bitfld.long 0x00 26. "CRX_BREAK,Control Rx break enable" "0,1"
bitfld.long 0x00 25. "CRX_PE,Control Rx protocol error enable" "0,1"
bitfld.long 0x00 24. "CRX_DONE,Control Rx packet done enable" "0,1"
bitfld.long 0x00 22. "ATX_BREAK,Asynchronous Tx break enable" "0,1"
bitfld.long 0x00 21. "ATX_PE,Asynchronous Tx protocol error enable" "0,1"
newline
bitfld.long 0x00 20. "ATX_DONE,Asynchronous Tx packet done enable" "0,1"
bitfld.long 0x00 19. "ARX_BREAK,Asynchronous Rx break enable" "0,1"
bitfld.long 0x00 18. "ARX_PE,Asynchronous Rx protocol error enable" "0,1"
bitfld.long 0x00 17. "ARX_DONE,Asynchronous Rx done enable" "0,1"
bitfld.long 0x00 16. "SYNC_PE,Synchronous protocol error enable" "0,1"
bitfld.long 0x00 1. "ISOC_BUFO,Isochronous Rx buffer overflow enable" "0,1"
bitfld.long 0x00 0. "ISOC_PE,Isochronous Rx protocol error enable" "0,1"
group.long 0x3C++0x03
line.long 0x00 "MLB_MLBC1,MediaLB Control 1 Register"
hexmask.long.byte 0x00 8.--15. 1. "NDA,Node device address"
bitfld.long 0x00 7. "CLKM,MediaLB clock missing status" "0,1"
bitfld.long 0x00 6. "LOCK,MediaLB lock error status" "0,1"
group.long 0x80++0x03
line.long 0x00 "MLB_HCTL,HBI Control Register"
bitfld.long 0x00 15. "EN,HBI enable" "0,1"
group.long 0x88++0x17
line.long 0x00 "MLB_HCMR0,HBI Channel Mask 0 Register"
line.long 0x04 "MLB_HCMR1,HBI Channel Mask 1 Register"
line.long 0x08 "MLB_HCER0,HBI Channel Error 0 Register"
line.long 0x0C "MLB_HCER1,HBI Channel Error 1 Register"
line.long 0x10 "MLB_HCBR0,HBI Channel Busy 0 Register"
line.long 0x14 "MLB_HCBR1,HBI Channel Busy 1 Register"
group.long 0xC0++0x27
line.long 0x00 "MLB_MDAT0,Memory Interface Data 0 Register"
line.long 0x04 "MLB_MDAT1,Memory Interface Data 1 Register"
line.long 0x08 "MLB_MDAT2,Memory Interface Data 2 Register"
line.long 0x0C "MLB_MDAT3,Memory Interface Data 3 Register"
line.long 0x10 "MLB_MDWE0,Memory Interface Data Write Enable 0 Register"
line.long 0x14 "MLB_MDWE1,Memory Interface Data Write Enable 1 Register"
line.long 0x18 "MLB_MDWE2,Memory Interface Data Write Enable 2 Register"
line.long 0x1C "MLB_MDWE3,Memory Interface Data Write Enable 3 Register"
line.long 0x20 "MLB_MCTL,Memory Interface Control Register"
bitfld.long 0x20 0. "XCMP,Transfer complete (write 0 to clear)" "0,1"
line.long 0x24 "MLB_MADR,Memory Interface Address Register"
bitfld.long 0x24 31. "WNR,Write-Not-Read selection (0 = read 1 = write)" "0,1"
bitfld.long 0x24 30. "TB,Target location bit (0 = selects CTR 1 = selects DBR)" "0,1"
bitfld.long 0x24 8.--13. "ADDR_13_8,DBR address of 8-bit entry - bits[13-8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x24 0.--7. 1. "ADDR_7_0,CTR address of 128-bit entry or DBR address of 8-bit entry - bits[7-0]"
rgroup.long 0xFC++0x03
line.long 0x00 "MLB_PID,MediaLB Core Revision Register"
hexmask.long.byte 0x00 8.--15. 1. "MAJOR,Major revision"
hexmask.long.byte 0x00 0.--7. 1. "MINOR,Minor revision"
group.long 0x3C0++0x03
line.long 0x00 "MLB_ACTL,AHB Control Register"
bitfld.long 0x00 4. "MPB,Packet buffering mode" "0,1"
bitfld.long 0x00 2. "DMA_MODE,DMA Mode" "0,1"
bitfld.long 0x00 1. "SMX,AHB interrupt mux enable" "0,1"
bitfld.long 0x00 0. "SCE,Software clear enable" "0,1"
group.long 0x3D0++0x0F
line.long 0x00 "MLB_ACSR0,AHB Channel Status 0 Register"
line.long 0x04 "MLB_ACSR1,AHB Channel Status 1 Register"
line.long 0x08 "MLB_ACMR0,AHB Channel Mask 0 Register"
line.long 0x0C "MLB_ACMR1,AHB Channel Mask 1 Register"
tree.end
tree.end
tree "MLBSS_ECC_Aggregator"
tree "MLB0_MLBDIM_WRAP_ECC_AGGR_VBP"
base ad:0x2F81000
rgroup.long 0x00++0x03
line.long 0x00 "MLB_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "MLB_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MLB_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MLB_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "MLB_ECC_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MLB_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "DBMEM_PEND,Interrupt Pending Status for dbmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MLB_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "DBMEM_ENABLE_SET,Interrupt Enable Set Register for dbmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MLB_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "DBMEM_ENABLE_CLR,Interrupt Enable Clear Register for dbmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MLB_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MLB_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "DBMEM_PEND,Interrupt Pending Status for dbmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MLB_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "DBMEM_ENABLE_SET,Interrupt Enable Set Register for dbmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MLB_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "DBMEM_ENABLE_CLR,Interrupt Enable Clear Register for dbmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MLB_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MLB_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MLB_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MLB_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MLBSS_RAT"
tree "MLB0_RAT_WRAP_RAT_CFG_VBP_MMRS"
base ad:0x2F83000
rgroup.long 0x00++0x07
line.long 0x00 "MLB_RAT_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MLB_RAT_CONFIG,The Configuration Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "MLB_RAT_CTRL_j,The Control for Region a Offset = 20h + (j * 10h); where j = 0h to 3Fh"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MLB_RAT_BASE_j,The Base Address for Region a"
line.long 0x08 "MLB_RAT_TRANS_l_j,The Translated Lower Address Bits for Region a Offset = 28h + (j * 10h); where j = 0h to 3Fh"
line.long 0x0C "MLB_RAT_TRANS_U_j,The Translated Upper Address Bits for Region a Offset = 2Ch + (j * 10h); where j = 0h to 3Fh"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
group.long 0x804++0x03
line.long 0x00 "MLB_RAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "MLB_RAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "MLB_RAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "MLB_RAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "MLB_RAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "MLB_RAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "MLB_RAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
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bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "MLB_RAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "MLB_RAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "MLB_RAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "MLB_RAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "MLB_RAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "MLB_RAT_EOI_REG,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree.end
tree "MMCSD0_Host_Controller"
tree "MMCSD0_CTL_CFG"
base ad:0x4F80000
group.word 0x00++0x0F
line.word 0x00 "MMCSD0_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10"
line.word 0x02 "MMCSD0_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10"
line.word 0x04 "MMCSD0_BLOCK_SIZE,This register is used to configure the number of bytes in a data block"
bitfld.word 0x04 12.--14. "SDMA_BUF_SIZE,Host SDMA Buffer Size To perform long DMA transfer System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry.." "4KB (Detects A11 Carry out),8KB (Detects A12 Carry out),16KB (Detects A13 Carry out),32KB (Detects A14 Carry out),64KB (Detects A15 Carry out),128KB (Detects A16 Carry out),256KB (Detects A17 Carry out),512KB (Detects A18 Carry out)"
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abitfld.word 0x04 0.--11. "XFER_BLK_SIZE,Transfer Block Size This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53" "0x000=No Data Transfer,0x001=1 Byte,0x002=2 Bytes,0x003=3 Bytes,0x004=4 Bytes,0x1FF=511 Bytes,0x200=512 Bytes,0x800=2048 Bytes"
line.word 0x06 "MMCSD0_BLOCK_COUNT,This register is used to configure the number of data blocks"
line.word 0x08 "MMCSD0_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument"
line.word 0x0A "MMCSD0_ARGUMENT1_HI,This register contains higher bits of SD Command Argument"
line.word 0x0C "MMCSD0_TRANSFER_MODE,"
bitfld.word 0x0C 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Interrupt is enabled,Response Interrupt is disabled"
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bitfld.word 0x0C 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Error Check is disabled,Response Error Check is enabled"
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bitfld.word 0x0C 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "R1 (Memory),R5 (SDIO)"
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bitfld.word 0x0C 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit enables multiple block data transfers" "Single Block,Multiple Block"
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bitfld.word 0x0C 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of data transfers" "Write (Host to Card),Read (Card to Host)"
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bitfld.word 0x0C 2.--3. "AUTO_CMD_ENA,Auto CMD Enable This field determines use of auto command functions" "Auto Command Disabled,Auto CMD12 Enable,Auto CMD23 Enable,Reserved"
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bitfld.word 0x0C 1. "BLK_CNT_ENA,Block Count Enable This bit is used to enable" "Disable,Enable"
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bitfld.word 0x0C 0. "DMA_ENA,DMA Enable DMA can be enabled only if" "Disable,Enable"
line.word 0x0E "MMCSD0_COMMAND,This register is used to program the Command for host controller"
bitfld.word 0x0E 8.--13. "CMD_INDEX,Command Index This bit shall be set to the command number (CMD0-63 ACMD0-63)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x0E 6.--7. "CMD_TYPE,Command Type There are three types of special commands" "Normal,Suspend,Resume,Abort"
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bitfld.word 0x0E 5. "DATA_PRESENT,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line" "No Data Present,Data Present"
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bitfld.word 0x0E 4. "CMD_INDEX_CHK_ENA,Command Index Check Enable If this bit is set to 1h the HC shall check the index field in the response to see if it has the same value as the command index" "Disable,Enable"
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bitfld.word 0x0E 3. "CMD_CRC_CHK_ENA,Command CRC Check Enable If this bit is set to 1h the HC shall check the CRC field in the response" "Disable,Enable"
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bitfld.word 0x0E 2. "SUB_CMD,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command" "Sub Command,Main Command"
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bitfld.word 0x0E 0.--1. "RESP_TYPE_SEL,Response Type Select" "No Response,Response length 136,Response length 48,Response length 48 check Busy after response"
group.long 0x20++0x07
line.long 0x00 "MMCSD0_DATA_PORT,This register is used to access internal buffer"
line.long 0x04 "MMCSD0_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x04 31. "UHS2_IF_DETECTION,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF" "UHS-II IF is not detected,UHS-II IF is detected"
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bitfld.long 0x04 30. "UHS2_IF_LANE_SYNC,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode" "UHS-II PHY is not initialized,UHS-II PHY is initialized"
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bitfld.long 0x04 29. "UHS2_DORMANT,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state" "Not in DORMANT state,In DORMANT state"
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bitfld.long 0x04 28. "SUB_COMMAND_STS,Sub Command Status" "Main Command Status,Sub Command Status"
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bitfld.long 0x04 27. "CMD_NOT_ISS_BY_ERR,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in.." "No error for issuing a command,Command cannot be issued"
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bitfld.long 0x04 24. "SDIF_CMDIN,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 23. "SDIF_DAT3IN,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 22. "SDIF_DAT2IN,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 21. "SDIF_DAT1IN,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 20. "SDIF_DAT0IN,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 19. "WRITE_PROTECT,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin" "Write protected (SDWP# = 1),Write enabled (SDWP# = 0)"
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bitfld.long 0x04 18. "CARD_DETECT,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin" "No Card present (SDCD# = 1),Card present (SDCD# = 0)"
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bitfld.long 0x04 17. "CARD_STATE_STABLE,Card State Stable This bit is used for testing" "Reset of Debouncing,No Card or Inserted"
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bitfld.long 0x04 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted" "Reset or Debouncing or No Card,Card Inserted"
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bitfld.long 0x04 11. "BUF_RD_ENA,Buffer Read Enable This status is used for non-DMA read transfers" "Read Disable,Read Enable"
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bitfld.long 0x04 10. "BUF_WR_ENA,Buffer Write Enable This status is used for non-DMA write transfers" "Write Disable,Write Enable"
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bitfld.long 0x04 9. "RD_XFER_ACTIVE,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer" "No valid data,Transferring data"
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bitfld.long 0x04 8. "WR_XFER_ACTIVE,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active" "No valid data,Transferring data"
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bitfld.long 0x04 7. "SDIF_DAT7IN,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 6. "SDIF_DAT6IN,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 5. "SDIF_DAT5IN,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 4. "SDIF_DAT4IN,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 3. "RETUNING_REQ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive.." "Fixed or well tuned sampling clock,Sampling clock needs re-tuning"
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bitfld.long 0x04 2. "DATA_LINE_ACTIVE,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use" "DAT line inactive,DAT line active"
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bitfld.long 0x04 1. "INHIBIT_DAT,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h" "Can issue command which uses the DAT line,Cannot issue command which uses the DAT line"
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bitfld.long 0x04 0. "INHIBIT_CMD,Command Inhibit (CMD)" "Host Controller is ready to issue a command..,Host Controller is not ready to issue a command"
group.byte 0x28++0x03
line.byte 0x00 "MMCSD0_HOST_CONTROL1,This register is used to program DMA modes. LED control. data transfer width. High Speed enable. card detect test level and signal selection"
bitfld.byte 0x00 7. "CD_SIG_SEL,Card Detect Signal Detection This bit selects source for card detection" "SDCD# is selected (for normal use),The card detect test level is selected"
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bitfld.byte 0x00 6. "CD_TEST_LEVEL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not" "No Card,Card Inserted"
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bitfld.byte 0x00 5. "EXT_DATA_WIDTH,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device" "Bus Width is Selected by Data Transfer Width,8-bit Bus Width"
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bitfld.byte 0x00 3.--4. "DMA_SELECT,DMA Select This field is used to select DMA type" "0,1,2,3"
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bitfld.byte 0x00 2. "HIGH_SPEED_ENA,High Speed Enable (SD Mode Only) This bit is optional" "Normal Speed Mode,High Speed Mode"
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bitfld.byte 0x00 1. "DATA_WIDTH,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC" "1 bit mode,4 bit mode"
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bitfld.byte 0x00 0. "LED_CONTROL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed" "LED off,LED on"
line.byte 0x01 "MMCSD0_POWER_CONTROL,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x01 5.--7. "UHS2_VOLTAGE,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2" "VDD2 Not Supported,Reserved,?,?,Reserved for 1.2 V,1.8 V,Not used,Not used"
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bitfld.byte 0x01 4. "UHS2_POWER,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2" "Power off,Power on"
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bitfld.byte 0x01 1.--3. "SD_BUS_VOLTAGE,SD Bus Voltage Select for VDD1 By setting these bits the HD selects the voltage level for the SD card" "Reserved,?,?,?,?,1.8 V (Typ.) for Embedded,3.0 V (Typ.),3.3 V (Flattop.)"
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bitfld.byte 0x01 0. "SD_BUS_POWER,SD Bus Power for VDD1 Before setting this bit the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state) and drive SDCLK to low level. If card.." "Power off,Power on"
line.byte 0x02 "MMCSD0_BLOCK_GAP_CONTROL,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x02 7. "BOOT_ACK_ENA,Boot Acknowledge Check To check for the boot acknowledge in boot operation" "Will not wait for boot ack from eMMC card,Wait for boot ack from eMMC card"
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bitfld.byte 0x02 6. "ALT_BOOT_MODE,Alternative Boot Mode To start boot code access in alternative mode" "To stop alternate boot mode access,To start alternate boot mode access"
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bitfld.byte 0x02 5. "BOOT_ENABLE,Boot Enable To start boot code access" "To stop boot code access,To start boot code access"
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bitfld.byte 0x02 3. "INTRPT_AT_BLK_GAP,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle" "0,1"
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bitfld.byte 0x02 2. "RDWAIT_CTRL,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards" "Disable Read Wait Control,Enable Read Wait Control"
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bitfld.byte 0x02 1. "CONTINUE,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request" "Ignored,Restart"
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bitfld.byte 0x02 0. "STOP_AT_BLK_GAP,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA SDMA and ADMA transfers" "Transfer,Stop"
line.byte 0x03 "MMCSD0_WAKEUP_CONTROL,This register is used to program the wakeup functionality"
bitfld.byte 0x03 2. "CARD_REMOVAL,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit" "Disable,Enable"
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bitfld.byte 0x03 1. "CARD_INSERTION,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit" "Disable,Enable"
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bitfld.byte 0x03 0. "CARD_INTERRUPT,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h" "Disable,Enable"
group.word 0x2C++0x01
line.word 0x00 "MMCSD0_CLOCK_CONTROL,This register is used to program the Clock frequency select. Clock generator select. Clock enable. Internal clock state fields"
hexmask.word.byte 0x00 8.--15. 1. "SDCLK_FRQSEL,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin"
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bitfld.word 0x00 6.--7. "SDCLK_FRQSEL_UPBITS,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to" "0,1,2,3"
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bitfld.word 0x00 5. "CLKGEN_SEL,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h:.." "Divided Clock Mode,Programmable Clock Mode"
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bitfld.word 0x00 3. "PLL_ENA,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL" "PLL is in low power mode,PLL is enabled"
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bitfld.word 0x00 2. "SD_CLK_ENA,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h" "Disable providing SDCLK or RCLK,Enable providing SDCLK or RCLK"
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bitfld.word 0x00 1. "INT_CLK_STABLE,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller.." "Not Ready,Ready"
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bitfld.word 0x00 0. "INT_CLK_ENA,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event" "Stop,Oscillate"
group.byte 0x2E++0x01
line.byte 0x00 "MMCSD0_TIMEOUT_CONTROL,The register sets the data timeout counter value"
bitfld.byte 0x00 0.--3. "COUNTER_VALUE,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x,Reserved"
line.byte 0x01 "MMCSD0_SOFTWARE_RESET,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x01 2. "SWRST_FOR_DAT,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset" "Work,Reset"
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bitfld.byte 0x01 1. "SWRST_FOR_CMD,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command" "Work,Reset"
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bitfld.byte 0x01 0. "SWRST_FOR_ALL,Software Reset for All This reset affects the entire HC except for the card detection circuit" "Work,Reset"
group.word 0x30++0x0F
line.word 0x00 "MMCSD0_NORMAL_INTR_STS,This register gives the status of all the interrupts"
bitfld.word 0x00 15. "ERROR_INTR,Error Interrupt If any of the bits in the In UHS-II mode is enabled if any of the bits in" "No Error,Error"
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bitfld.word 0x00 14. "BOOT_COMPLETE,Boot Terminate Interrupt This status is set if the boot operation gets terminated" "Boot operation is not terminated,Boot operation is terminated"
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bitfld.word 0x00 13. "RCV_BOOT_ACK,Boot Acknowledge Receive This status is set if the boot acknowledge is received from device" "Boot acknowledge is not received,Boot acknowledge is received"
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bitfld.word 0x00 12. "RETUNING_EVENT,Re-Tuning Event (UHS-I Only) This status is set if the Host Controller requests Host Driver to perform re-tuning for next data transfer" "Re-Tuning is not required,Re-Tuning should be performed"
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rbitfld.word 0x00 11. "INTC,int_c (Embedded) This status is set if INT_C is enabled and INT_C# pin is in low level" "0,1"
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rbitfld.word 0x00 10. "INTB,int_b (Embedded) This status is set if INT_B is enabled and INT_B# pin is in low level" "0,1"
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rbitfld.word 0x00 9. "INTA,int_a (Embedded) This status is set if INT_A is enabled and INT_A# pin is in low level" "0,1"
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bitfld.word 0x00 8. "CARD_INTR,Card Interrupt When this status has been set and the Host Driver needs to start this interrupt service the Writing this bit to 1h does not clear this bit" "No Card Interrupt,Generate Card Interrupt"
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bitfld.word 0x00 7. "CARD_REM,Card Removal This status is set if" "Card State Stable or Debouncing,Card Removed"
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bitfld.word 0x00 6. "CARD_INS,Card Insertion This status is set if" "Card State Stable or Debouncing,Card Inserted"
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bitfld.word 0x00 5. "BUF_RD_READY,Buffer Read Ready This status is set if the The In UHS-II mode this bit is set at FC (Flow Control) unit basis" "Not Ready to read Buffer,Ready to read Buffer"
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bitfld.word 0x00 4. "BUF_WR_READY,Buffer Write Ready This status is set if the In UHS-II mode this bit is set at FC (Flow Control) unit basis" "Not Ready to Write Buffer,Ready to Write Buffer"
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bitfld.word 0x00 3. "DMA_INTERRUPT,DMA Interrupt This status is set if the HC detects the Host DMA Buffer Boundary in" "No DMA Interrupt,DMA Interrupt is Generated"
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bitfld.word 0x00 2. "BLK_GAP_EVENT,Block Gap Event If the Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (see Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (see 0h: No Block Gap Event 1h:.." "No Block Gap Event,Transaction stopped at Block Gap"
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bitfld.word 0x00 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transaction is completed" "Not complete,Command execution is completed"
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bitfld.word 0x00 0. "CMD_COMPLETE,Command Complete This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23)" "No Command Complete,Command Complete"
line.word 0x02 "MMCSD0_ERROR_INTR_STS,This register gives the status of the error interrupts"
bitfld.word 0x02 12. "HOST,Target Response Error Occurs when detecting ERROR in m_hresp (DMA transaction)" "No error,Error"
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bitfld.word 0x02 11. "RESP,Response Error (SD Mode Only) Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "No error,Error"
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bitfld.word 0x02 9. "ADMA,ADMA Error This bit is set when the Host Controller detects errors during ADMA based data transfer" "No error,Error"
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bitfld.word 0x02 8. "AUTO_CMD,Auto CMD Error (SD Mode Only) Auto CMD12 and Auto CMD23 use this error status" "No error,Error"
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bitfld.word 0x02 7. "CURR_LIMIT,Current Limit Error By setting" "No error,Power Fail"
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bitfld.word 0x02 6. "DATA_ENDBIT,Data End Bit Error (SD Mode Only) Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status" "No error,Error"
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bitfld.word 0x02 5. "DATA_CRC,Data CRC Error (SD Mode Only) Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h" "No error,Error"
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bitfld.word 0x02 4. "DATA_TIMEOUT,Data Timeout Error (SD Mode Only) Occurs when detecting one of following timeout conditions" "No error,Timeout"
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bitfld.word 0x02 3. "CMD_INDEX,Command Index Error (SD Mode Only) Occurs if a Command Index error occurs in the Command Response ( 0h: No error 1h: Error" "No error,Error"
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bitfld.word 0x02 2. "CMD_ENDBIT,Command End Bit Error (SD Mode Only) Occurs when detecting that the end bit of a command response is 0h" "No error,End Bit Error Generated"
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bitfld.word 0x02 1. "CMD_CRC,Command CRC Error (SD Mode Only) Command CRC Error is generated in two cases" "No error,CRC Error Generated"
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bitfld.word 0x02 0. "CMD_TIMEOUT,Command Timeout Error (SD Mode Only) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command" "No error,Timeout"
line.word 0x04 "MMCSD0_NORMAL_INTR_STS_ENA,This register is used to enable the register fields"
rbitfld.word 0x04 15. "BIT15_FIXED0,Fixed to 0 The HC shall control error Interrupts using" "0,1"
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bitfld.word 0x04 14. "BOOT_COMPLETE,Boot Terminate Interrupt Enable" "Masked,Enabled"
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bitfld.word 0x04 13. "RCV_BOOT_ACK,Boot Acknowledge Enable" "Masked,Enabled"
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bitfld.word 0x04 12. "RETUNING_EVENT,Re-Tuning Event Status Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x04 11. "INTC,INT_C Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 10. "INTB,INT_B Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 9. "INTA,INT_A Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 8. "CARD_INTERRUPT,Card Interrupt Status Enable If this bit is set to 0h the HC shall clear Interrupt request to the System" "Masked,Enabled"
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bitfld.word 0x04 7. "CARD_REMOVAL,Card Removal Status Enable" "Masked,Enabled"
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bitfld.word 0x04 6. "CARD_INSERTION,Card Insertion Status Enable" "Masked,Enabled"
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bitfld.word 0x04 5. "BUF_RD_READY,Buffer Read Ready Status Enable" "Masked,Enabled"
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bitfld.word 0x04 4. "BUF_WR_READY,Buffer Write Ready Status Enable" "Masked,Enabled"
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bitfld.word 0x04 3. "DMA_INTERRUPT,DMA Interrupt Status Enable" "Masked,Enabled"
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bitfld.word 0x04 2. "BLK_GAP_EVENT,Block Gap Event Status Enable" "Masked,Enabled"
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bitfld.word 0x04 1. "XFER_COMPLETE,Transfer Complete Status Enable" "Masked,Enabled"
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bitfld.word 0x04 0. "CMD_COMPLETE,Command Complete Status Enable" "Masked,Enabled"
line.word 0x06 "MMCSD0_ERROR_INTR_STS_ENA,This register is used to enable the register fields"
bitfld.word 0x06 12.--15. "VENDOR_SPECIFIC,Vendor Specific Error Status Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x06 11. "RESP,Response Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 10. "TUNING,Tuning Error Status Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x06 9. "ADMA,ADMA Error Status Enable" "Masked,Enabled"
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bitfld.word 0x06 8. "AUTO_CMD,Auto CMD Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 7. "CURR_LIMIT,Current Limit Error Status Enable" "Masked,Enabled"
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bitfld.word 0x06 6. "DATA_ENDBIT,Data End Bit Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 5. "DATA_CRC,Data CRC Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 4. "DATA_TIMEOUT,Data Timeout Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 3. "CMD_INDEX,Command Index Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 2. "CMD_ENDBIT,Command End Bit Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 1. "CMD_CRC,Command CRC Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 0. "CMD_TIMEOUT,Command Timeout Error Status Enable (SD Mode Only)" "Masked,Enabled"
line.word 0x08 "MMCSD0_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt"
rbitfld.word 0x08 15. "BIT15_FIXED0,Fixed to 0 The HD shall control error Interrupts using" "0,1"
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bitfld.word 0x08 14. "BOOT_COMPLETE,Boot Terminate Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 13. "RCV_BOOT_ACK,Boot Acknowledge Receive Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 12. "RETUNING_EVENT,Re-Tuning Event Signal Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x08 11. "INTC,INT_C Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 10. "INTB,INT_B Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 9. "INTA,INT_A Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 8. "CARD_INTERRUPT,Card Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 7. "CARD_REMOVAL,Card Removal Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 6. "CARD_INSERTION,Card Insertion Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 5. "BUF_RD_READY,Buffer Read Ready Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 4. "BUF_WR_READY,Buffer Write Ready Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 3. "DMA_INTERRUPT,DMA Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 2. "BLK_GAP_EVENT,Block Gap Event Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 1. "XFER_COMPLETE,Transfer Complete Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 0. "CMD_COMPLETE,Command Complete Signal Enable" "Masked,Enabled"
line.word 0x0A "MMCSD0_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt"
bitfld.word 0x0A 12.--15. "VENDOR_SPECIFIC,Vendor Specific Error Signal Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x0A 11. "RESP,Response Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 10. "TUNING,Tuning Error Signal Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x0A 9. "ADMA,ADMA Error Signal Enable" "Masked,Enabled"
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bitfld.word 0x0A 8. "AUTO_CMD,Auto CMD Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 7. "CURR_LIMIT,Current Limit Error Signal Enable" "Masked,Enabled"
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bitfld.word 0x0A 6. "DATA_ENDBIT,Data End Bit Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 5. "DATA_CRC,Data CRC Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 4. "DATA_TIMEOUT,Data Timeout Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 3. "CMD_INDEX,Command Index Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 2. "CMD_ENDBIT,Command End Bit Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 1. "CMD_CRC,Command CRC Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 0. "CMD_TIMEOUT,Command Timeout Error Signal Enable (SD Mode Only)" "Masked,Enabled"
line.word 0x0C "MMCSD0_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23"
bitfld.word 0x0C 7. "CMD_NOT_ISSUED,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register" "No Error,Not Issued"
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bitfld.word 0x0C 4. "INDEX,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command" "No Error,Error"
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bitfld.word 0x0C 3. "ENDBIT,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h" "No Error,End Bit Error Generated"
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bitfld.word 0x0C 2. "CRC,Auto CMD CRC Error Occurs when detecting a CRC error in the command response" "No Error,CRC Error Generated"
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bitfld.word 0x0C 1. "TIMEOUT,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command" "No Error,Timeout"
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bitfld.word 0x0C 0. "ACMD12_NOT_EXEC,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "Executed,Not Executed"
line.word 0x0E "MMCSD0_HOST_CONTROL2,This register is used to program UHS Mode Select. Driver Strength Select. Execute Tuning. Sampling Clock Select. Asynchronous Interrupt Enable and Preset Value Enable"
bitfld.word 0x0E 15. "PRESET_VALUE_ENA,Preset Value Enable Host Controller Version 3.00 supports this bit" "SDCLK and Driver Strength are controlled by Host..,Automatic Selection by Preset Value are Enabled"
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bitfld.word 0x0E 14. "ASYNCH_INTR_ENA,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and" "Disabled,Enabled"
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bitfld.word 0x0E 13. "BIT64_ADDRESSING,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory" "32-bits Addressing,64-bits Addressing"
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bitfld.word 0x0E 12. "HOST_VER40_ENA,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode" "Version 3.00 Compatible Mode,Version 4.Mode"
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bitfld.word 0x0E 11. "CMD23_ENA,CMD23 Enable In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]" "0,1"
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bitfld.word 0x0E 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit" "16-bit Data Length Mode,26-bit Data Length Mode"
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bitfld.word 0x0E 9. "DRIVER_STRENGTH2,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value" "0,1"
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bitfld.word 0x0E 8. "UHS2_INTF_ENABLE,UHS-II Interface Enable This bit is used to enable UHS-II Interface" "4-bit SD Interface Enabled,UHS-II Interface Enabled"
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bitfld.word 0x0E 7. "SAMPLING_CLK_SELECT,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when" "Fixed clock is used to sample data,Tuned clock is used to sample data"
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bitfld.word 0x0E 6. "EXECUTE_TUNING,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed" "Not Tuned or Tuning Completed,Execute Tuning"
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bitfld.word 0x0E 4.--5. "DRIVER_STRENGTH1,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit" "Driver Type B is Selected (Default),Driver Type A is Selected,Driver Type C is Selected,Driver Type D is Selected"
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bitfld.word 0x0E 3. "V1P8_SIGNAL_ENA,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell" "3.3 V Signaling,1.8 V Signaling"
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bitfld.word 0x0E 0.--2. "UHS_MODE_SELECT,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode" "SDR12,SDR25,SDR50,SDR104,DDR50,HS400,Reserved,UHS-II When.."
rgroup.quad 0x40++0x0F
line.quad 0x00 "MMCSD0_CAPABILITIES,This register provides the HD with information specific to the HC implementation"
bitfld.quad 0x00 63. "HS400_SUPPORT,HS400 Support" "HS400 is Not Supported,HS400 is Supported"
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bitfld.quad 0x00 60. "VDD2_1P8_SUPPORT,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system" "1.8 V VDD2 is not supported,1.8 V VDD2 is supported"
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bitfld.quad 0x00 59. "ADMA3_SUPPORT,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller" "ADMA3 is not supported,ADMA3 is supported"
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bitfld.quad 0x00 57. "SPI_BLK_MODE,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not" "Not Supported,Supported"
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bitfld.quad 0x00 56. "SPI_SUPPORT,SPI Mode This bit indicates whether SPI Mode is supported or not" "Not Supported,Supported"
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abitfld.quad 0x00 48.--55. "CLOCK_MULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" "0x00=Clock Multiplier is Not Supported,0x01=Clock Multiplier M = 2,0x02=Clock Multiplier M = 3,0xFF=Clock Multiplier M ="
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bitfld.quad 0x00 46.--47. "RETUNING_MODES,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver" "Mode 1,Mode 2,Mode 3,Reserved There.."
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bitfld.quad 0x00 45. "TUNING_FOR_SDR50,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104)" "SDR50 does not require tuning,SDR50 requires tuning"
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bitfld.quad 0x00 40.--43. "RETUNING_TIMER_CNT,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "Get information via other source,1 seconds,2 seconds,4 seconds,8 seconds ---- n =,?,?,?,?,?,?,1024 seconds,?,?,?,Ch = Reserved"
newline
bitfld.quad 0x00 38. "DRIVERD_SUPPORT,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling" "Driver Type D is Not Supported,Driver Type D is Supported"
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bitfld.quad 0x00 37. "DRIVERC_SUPPORT,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling" "Driver Type C is Not Supported,Driver Type C is Supported"
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bitfld.quad 0x00 36. "DRIVERA_SUPPORT,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling" "Driver Type A is Not Supported,Driver Type A is Supported"
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bitfld.quad 0x00 35. "UHS2_SUPPORT,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II" "UHS-II is Not Supported,UHS-II is Supported"
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bitfld.quad 0x00 34. "DDR50_SUPPORT,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not" "DDR50 is Not Supported,DDR50 is Supported"
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bitfld.quad 0x00 33. "SDR104_SUPPORT,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not" "SDR104 is Not Supported,SDR104 is Supported"
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bitfld.quad 0x00 32. "SDR50_SUPPORT,SDR50 Support (UHS-I Only) If SDR104 is supported this bit shall be set to 1h" "SDR50 is Not Supported,SDR50 is Supported"
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bitfld.quad 0x00 30.--31. "SLOT_TYPE,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot)" "Removable Card Slot,Embedded Slot for One Device,Shared Bus Slot (SD Mode),UHS-II Multiple Embedded Devices"
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bitfld.quad 0x00 29. "ASYNCH_INTR_SUPPORT,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "Asynchronous Interrupt Not Supported,Asynchronous Interrupt Supported"
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bitfld.quad 0x00 28. "ADDR_64BIT_SUPPORT_V3,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions" "64-bit System Address for V3 is not Supported,64-bit System Address for V3 is Supported"
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bitfld.quad 0x00 27. "ADDR_64BIT_SUPPORT_V4,64-bit System Address Support for V4 This bit is added from Version 4.10" "64-bit System Address for V4 is not Supported,64-bit System Address for V4 is Supported"
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bitfld.quad 0x00 26. "VOLT_1P8_SUPPORT,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V" "1.8 V Not Supported,1.8 V Supported"
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bitfld.quad 0x00 25. "VOLT_3P0_SUPPORT,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V" "3.0 V Not Supported,3.0 V Supported"
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bitfld.quad 0x00 24. "VOLT_3P3_SUPPORT,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V" "3.3 V Not Supported,3.3 V Supported"
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bitfld.quad 0x00 23. "SUSP_RES_SUPPORT,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality" "Not Supported,Supported"
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bitfld.quad 0x00 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly" "SDMA Not Supported,SDMA Supported"
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bitfld.quad 0x00 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC)" "High Speed Not Supported,High Speed Supported"
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bitfld.quad 0x00 19. "ADMA2_SUPPORT,ADMA2 Support" "ADMA2 Not support,ADMA2 support"
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bitfld.quad 0x00 18. "BUS_8BIT_SUPPORT,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode" "8-bit Bus Width Not Supported,8-bit Bus Width Supported"
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bitfld.quad 0x00 16.--17. "MAX_BLK_LENGTH,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC" "512 byte,1024 byte,2048 byte,4096 byte"
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abitfld.quad 0x00 8.--15. "BASE_CLK_FREQ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00" "0x00=Get Information via..,0x01=1 MHz,0x02=2 MHz,0x0F=63 MHz 0000,0xFF=255 MHz"
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bitfld.quad 0x00 7. "TIMEOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "KHz,MHz"
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bitfld.quad 0x00 0.--5. "TIMEOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "MMCSD0_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x08 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8 V VDD2"
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hexmask.quad.byte 0x08 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8 V VDD1"
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hexmask.quad.byte 0x08 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0 V VDD1"
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hexmask.quad.byte 0x08 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3 V VDD1"
group.word 0x50++0x03
line.word 0x00 "MMCSD0_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.word 0x00 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error" "Not Affected,Command Not Issued By Auto CMD12.."
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bitfld.word 0x00 5. "RESP,Force Event for AUTO CMD Response Error" "Not Affected,Auto CMD Response Error Status is.."
newline
bitfld.word 0x00 4. "INDEX,Force Event for AUTO CMD Index Error" "Not Affected,Auto CMD Index Error Status is set"
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bitfld.word 0x00 3. "ENDBIT,Force Event for AUTO CMD End Bit Error" "Not Affected,Auto CMD End bit Error Status is set"
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bitfld.word 0x00 2. "CRC,Force Event for AUTO CMD Timeout Error" "Not Affected,Auto CMD CRC Error Status is set"
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bitfld.word 0x00 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error" "Not Affected,Auto CMD Timeout Error Status is set"
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bitfld.word 0x00 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed" "Not Affected,Auto CMD12 Not Executed Status is.."
line.word 0x02 "MMCSD0_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.word 0x02 12.--15. "VEND_SPEC,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x02 11. "RESP,Force Event for Response Error" "Not Affected,Response Error Status is set"
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bitfld.word 0x02 10. "TUNING,Force Event for Tuning Error" "Not Affected,Tuning Error Status is set"
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bitfld.word 0x02 9. "ADMA,Force Event for ADMA Error" "Not Affected,ADMA Error Status is set"
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bitfld.word 0x02 8. "AUTO_CMD,Force Event for Auto CMD Error" "Not Affected,Auto CMD Error Status is set"
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bitfld.word 0x02 7. "CURR_LIM,Force Event for Current Limit Error" "Not Affected,Current Limit Error Status is set"
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bitfld.word 0x02 6. "DAT_ENDBIT,Force Event for Data End Bit Error" "Not Affected,Data End Bit Error Status is set"
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bitfld.word 0x02 5. "DAT_CRC,Force Event for Data CRC Error" "Not Affected,CRC Error Status is set"
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bitfld.word 0x02 4. "DAT_TIMEOUT,Force Event for Data Timeout Error" "Not Affected,Timeout Error Status is set"
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bitfld.word 0x02 3. "CMD_INDEX,Force Event for Command Index Error" "Not Affected,Command Index Error Status is set"
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bitfld.word 0x02 2. "CMD_ENDBIT,Force Event for Command End Bit Error" "Not Affected,Command End Bit Error Status is set"
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bitfld.word 0x02 1. "CMD_CRC,Force Event for Command CRC Error" "Not Affected,Command CRC Error Status is set"
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bitfld.word 0x02 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error" "Not Affected,Command Timeout Error Status is set"
rgroup.byte 0x54++0x00
line.byte 0x00 "MMCSD0_ADMA_ERR_STATUS,When the ADMA Error interrupt occur. this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor"
bitfld.byte 0x00 2. "ADMA_LENGTH_ERR,ADMA Length Mismatch Error This error occurs in the following 2 cases" "No Error,Error"
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bitfld.byte 0x00 0.--1. "ADMA_ERR_STATE,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer" "ST_STOP (Stop DMA) Points to next of the error..,ST_FDS (Fetch Descriptor) Points to the error..,Never set this state (Not used),ST_TFR (Transfer Data) Points to the next of the.."
group.quad 0x58++0x07
line.quad 0x00 "MMCSD0_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer"
rgroup.word 0x60++0x01
line.word 0x00 "MMCSD0_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value"
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes" "Driver Type D is Selected,Driver Type C is Selected,Driver Type A is Selected,Driver Type B is Selected"
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bitfld.word 0x00 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "Host Controller Version 2.00 Compatible Clock..,Programmable Clock Generator"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set"
group.quad 0x78++0x07
line.quad 0x00 "MMCSD0_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register"
group.word 0x80++0x01
line.word 0x00 "MMCSD0_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BOUNDARY,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging SDMA data transfer is performed in unit of paging" "4K bytes (Detects A11 carry out),8K bytes (Detects A12 carry out),16K Bytes (Detects A13 carry out),32K Bytes (Detects A14 carry out),64K bytes (Detects A15 carry out),128K Bytes (Detects A16 carry out),256K Bytes (Detects A17 carry out),512K Bytes (Detects A18 carry out)"
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hexmask.word 0x00 0.--11. 1. "XFER_BLK_SIZE,UHS-II Block Size This bit field specifies the block size of data packet"
group.long 0x84++0x03
line.long 0x00 "MMCSD0_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks"
group.word 0x9C++0x03
line.word 0x00 "MMCSD0_UHS2_XFER_MODE,This register is used to control the operations of data transfers"
bitfld.word 0x00 15. "DUPLEX_SELECT,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver" "Full Duplex Mode,2 Lane Half Duplex Mode"
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bitfld.word 0x00 14. "EBSY_WAIT,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution" "Issue a command without..,Wait EBSY"
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bitfld.word 0x00 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Interrupt is enabled,Response Interrupt is disabled"
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bitfld.word 0x00 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Error Check is disabled,Response Error Check is enabled"
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bitfld.word 0x00 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled this bit selects either R1 or R5 response types" "R1 (Memory),R5 (SDIO)"
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bitfld.word 0x00 5. "BYTE_MODE,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when" "Block Mode,Byte Mode"
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bitfld.word 0x00 4. "DATA_XFER_DIR,Data Transfer Direction This bit specifies direction of data transfer when" "Read (Card to Host),Write (Host to Card)"
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bitfld.word 0x00 1. "BLK_CNT_ENA,Block Count Enable This bit specifies whether data transfer uses" "Block Count Disabled,Block Count Enabled"
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bitfld.word 0x00 0. "DMA_ENA,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer" "DMA is disabled,DMA is enabled"
line.word 0x02 "MMCSD0_UHS2_COMMAND,This register is used to program the Command for host controller"
bitfld.word 0x02 8.--12. "PKT_LENGTH,UHS-II Command Packet Length A command packet length which is set in the UHS-II Command Packet register ( 00011b - 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b - 10101b" "3-0 Bytes (Not used),?,?,?,4 Bytes,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20 Bytes 11111b - 10101b,?..."
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bitfld.word 0x02 6.--7. "CMD_TYPE,Command Type This field is used to distinguish a specific command like abort command" "Normal Command,TRANS_ABORT CCMD,?,CMD12 or SDIO Abort command"
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bitfld.word 0x02 5. "DATA_PRESENT,Data Present This bit specifies whether the command is accompanied by data packet" "No Data Present,Data Present"
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bitfld.word 0x02 2. "SUB_COMMAND,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command" "Sub Command,Main Command"
rgroup.byte 0xA0++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_0,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xA4++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_1,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xA8++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_2,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xAC++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_3,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xB0++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_4,This register is used to store received UHS-II RES Packet image"
group.byte 0xB4++0x00
line.byte 0x00 "MMCSD0_UHS2_MESSAGE_SELECT,This register is used to access internal buffer"
bitfld.byte 0x00 0.--1. "MSG_SEL,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer" "The latest MSG,One MSG before,Two MSGs before,Three MSGs before"
rgroup.byte 0xB4++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_5,This register is used to store received UHS-II RES Packet image"
rgroup.long 0xB8++0x03
line.long 0x00 "MMCSD0_UHS2_MESSAGE,This register is used to access internal buffer"
hexmask.long.byte 0x00 24.--31. 1. "MSG_BYTE3,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 16.--23. 1. "MSG_BYTE2,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 8.--15. 1. "MSG_BYTE1,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 0.--7. 1. "MSG_BYTE0,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
rgroup.byte 0xB8++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_6,This register is used to store received UHS-II RES Packet image"
group.word 0xBC++0x01
line.word 0x00 "MMCSD0_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device"
rgroup.byte 0xBC++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_7,This register is used to store received UHS-II RES Packet image"
group.byte 0xBE++0x02
line.byte 0x00 "MMCSD0_UHS2_DEVICE_SELECT,UHS-II Device Select Register"
bitfld.byte 0x00 7. "INT_MSG_ENA,INT MSG Enable (Optional) This bit enables receipt of INT MSG" "Disabled,Enabled"
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bitfld.byte 0x00 0.--3. "DEV_SEL,UHS-II Device Select Host Controller holds an INT MSG packet per device" "Unselected (Default),INT MSG of Device ID 1 is selected,INT MSG of Device ID 2 is selected,?,?,?,?,?,?,?,?,?,?,?,?,INT MSG of Device ID 15 is selected"
line.byte 0x01 "MMCSD0_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h"
line.byte 0x02 "MMCSD0_UHS2_RESPONSE_8,This register is used to store received UHS-II RES Packet image"
group.word 0xC0++0x03
line.word 0x00 "MMCSD0_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register"
bitfld.word 0x00 1. "HOST_SDTRAN_RESET,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs" "Not Affected,Reset SD-TRAN"
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bitfld.word 0x00 0. "HOST_FULL_RESET,Host Full Reset On issuing FULL_RESET CCMD Host Driver set this bit to 1h to reset Host Controller" "Not Affected,Reset Host Controller"
line.word 0x02 "MMCSD0_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register"
bitfld.word 0x02 4.--7. "DEADLOCK_TIMEOUT_CTR,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second)" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x 2,Reserved"
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bitfld.word 0x02 0.--3. "CMDRESP_TIMEOUT_CTR,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms)" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x 2,Reserved"
group.long 0xC4++0x03
line.long 0x00 "MMCSD0_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC_ERR,Vendor Specific Error Vendor may use this field for vendor specific error status" "Interrupt is not generated,Vendor Specific Error,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting of this bit means that deadlock timeout occurs" "Interrupt is not generated,Deadlock Error"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting of this bit means that RES Packet timeout occurs" "Interrupt is not generated,RES Packet Timeout Error"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode" "Interrupt is not generated,ADMA2/3 Error"
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bitfld.long 0x00 8. "EBSY,EBSY Error On receiving EBSY packet if the packet indicates an error this bit is set to 1h" "Interrupt is not generated,EBSY Error (Backend Error)"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting of this bit means that Unrecoverable Error is set in a packet from a device" "Interrupt is not generated,Device Unrecoverable Error"
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bitfld.long 0x00 5. "TID,TID Error Setting of this bit means that TID Error occurs" "Interrupt is not generated,TID Error"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting of this bit means that Framing Error occurs during a packet receiving" "Interrupt is not generated,Framing Error"
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bitfld.long 0x00 3. "CRC,CRC Error Setting of this bit means that CRC Error occurs during a packet receiving" "Interrupt is not generated,CRC Error"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Retry Expired Setting of this bit means that Retry Counter Expired Error occurs during data transfer" "Interrupt is not generated,Retry Expired Error"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "Interrupt is not generated,RES Packet Error"
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bitfld.long 0x00 0. "HEADER,Header Error Setting of this bit means that Header Error occurs in a received packet" "Interrupt is not generated,Header Error"
rgroup.byte 0xC4++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_9,This register is used to store received UHS-II RES Packet image"
group.byte 0xC8++0x00
line.byte 0x00 "MMCSD0_UHS2_COMMAND_PKT_16,UHS-II Command Packet image is set to this register"
group.long 0xC8++0x03
line.long 0x00 "MMCSD0_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in" "Status is Disabled,Status is Enabled,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 8. "EBSY,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 5. "TID,TID Error Setting this bit to 1h enables setting of TID Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting this bit to 1h enables setting of Framing Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 3. "CRC,CRC Error Setting this bit to 1h enables setting of CRC Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 0. "HEADER,Header Error Setting this bit to 1h enables setting of Header Error bit in" "Status is Disabled,Status is Enabled"
rgroup.byte 0xC8++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_10,This register is used to store received UHS-II RES Packet image"
group.byte 0xCC++0x00
line.byte 0x00 "MMCSD0_UHS2_COMMAND_PKT_17,UHS-II Command Packet image is set to this register"
group.long 0xCC++0x03
line.long 0x00 "MMCSD0_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 8. "EBSY,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 5. "TID,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 3. "CRC,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 2. "RETRY_EXPIRED_SIG_ENA,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 0. "HEADER,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
rgroup.byte 0xCC++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_11,This register is used to store received UHS-II RES Packet image"
group.byte 0xD0++0x00
line.byte 0x00 "MMCSD0_UHS2_COMMAND_PKT_18,UHS-II Command Packet image is set to this register"
rgroup.word 0xE0++0x09
line.word 0x00 "MMCSD0_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings"
line.word 0x02 "MMCSD0_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register"
line.word 0x04 "MMCSD0_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register"
line.word 0x06 "MMCSD0_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register"
line.word 0x08 "MMCSD0_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register"
group.long 0xF4++0x07
line.long 0x00 "MMCSD0_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter"
line.long 0x04 "MMCSD0_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK. CMD11 Power Down Timer. Enhanced Strobe and eMMC Hardware Reset"
bitfld.long 0x04 16. "AUTOGATE_SDCLK,Auto Gate SD CLK If this bit is set SD CLK will be gated automatically when there is no transfer" "Disable,Enable"
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hexmask.long.word 0x04 2.--15. 1. "CMD11_PD_TIMER,CMD11 Power Down Timer Value"
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bitfld.long 0x04 1. "EMMC_HW_RESET,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set" "De-sassert hardware reset pin,Drives the hardware reset pin as ZERO (Active.."
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bitfld.long 0x04 0. "ENHANCED_STROBE,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x03
line.word 0x00 "MMCSD0_SLOT_INT_STS,This register is used to read the interrupt signal for each slot"
hexmask.word.byte 0x00 0.--7. 1. "INTR_SIG,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot"
line.word 0x02 "MMCSD0_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number"
hexmask.word.byte 0x02 8.--15. 1. "VEN_VER_NUM,Vendor Version Number The Vendor Version Number is set to 10h (1.0)"
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abitfld.word 0x02 0.--7. "SPEC_VER_NUM,Specification Version Number This status indicates the Host Controller Specification Version" "0x00=SD Host Controller Specification Version 1.00,0x01=SD Host Controller Specification Version..,0x02=SD Host Controller Specification Version 3.00,0x03=SD Host Controller Specification Version 4.00,0x04=SD Host Controller Specification Version.."
group.long 0x100++0x07
line.long 0x00 "MMCSD0_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register"
bitfld.long 0x00 8.--13. "NUMLANES,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices" "2 Lanes FD or 2L-HD,Not Used,3 Lanes 2D1U-FD (Embedded),3 Lanes 1D2U-FD (Embedded),4 Lanes 2D2U-FD (Embedded) Others: Reserved,?..."
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bitfld.long 0x00 0. "POWER_MODE,Power Mode This field determines either Fast mode or Low Power mode" "Fast Mode,Low Power Mode"
line.long 0x04 "MMCSD0_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register"
bitfld.long 0x04 20.--23. "N_LSS_DIR,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field" "8 x 16 LSS,8 x 1 LSS,8 x 2 LSS,8 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,8 x 15 LSS"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS 3h - 4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 15. "HIBERNATE_ENA,Hibernate Enable After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set" "Hibernate Disabled,Hibernate Enabled"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,Speed Range PLL multiplier is selected by this field" "Range A (Defalt),Range B,Reserved,Reserved"
group.quad 0x108++0x07
line.quad 0x00 "MMCSD0_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register"
abitfld.quad 0x00 32.--39. "N_DATA_GAP,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field" "0x00=No Gap,0x01=1 LSS,0x02=2 LSS,0x03=3 LSS,0xFF=255 LSS"
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bitfld.quad 0x00 16.--17. "RETRY_COUNT,Retry Count Data Burst retry count is set to this field" "Retry Disabled,1 time,2 times,3 times"
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abitfld.quad 0x00 8.--15. "HOST_NFCU,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field" "0x00=256 Blocks,0x01=1 Block,0x02=2 Blocks,0x03=3 Blocks,0xFF=255 Blocks"
rgroup.long 0x110++0x07
line.long 0x00 "MMCSD0_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register"
bitfld.long 0x00 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,Bus Topology This field indicates one of bus topologies configured by a Host system" "P2P Connection,Ring Connection,HUB Connection,HUB is Connected in Ring"
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bitfld.long 0x00 18.--21. "CORECFG_UHS2_MAX_DEVICES,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller" "Not used,1 Devices,2 Devices,?,?,?,?,?,?,?,?,?,?,?,?,15 Devices"
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bitfld.long 0x00 16.--17. "DEVICE_TYPE,Removable/Embedded This field indicates device type configured by a Host system" "Removable Card (P2P),Embedded Devices,Embedded Devices + Removable Card,Reserved"
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bitfld.long 0x00 14. "CFG_64BIT_ADDRESSING,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller" "32-bit Addressing is supported,32-bit and 64-bit Addressing is supported"
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bitfld.long 0x00 8.--13. "NUM_LANES,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--7. "GAP,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system" "Not used,360 mW,720 mW,?,?,?,?,?,?,?,?,?,?,?,?,360 x 15 mW"
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bitfld.long 0x00 0.--3. "DAP,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system" "360 mW (Default),360 mW,720 mW,?,?,?,?,?,?,?,?,?,?,?,?,360 x 15 mW"
line.long 0x04 "MMCSD0_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register"
bitfld.long 0x04 20.--23. "N_LSS_DIR,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS,4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS,4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,Speed Range This field indicates supported Speed Range by the Host Controller" "Range A (Default),Range A and Range B,Reserved,Reserved"
rgroup.quad 0x118++0x07
line.quad 0x00 "MMCSD0_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register"
abitfld.quad 0x00 32.--39. "N_DATA_GAP,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller" "0x00=No Gap,0x01=1 LSS,0x02=2 LSS,0x03=3 LSS,0xFF=255 LSS"
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abitfld.quad 0x00 20.--31. "MAX_BLK_LENGTH,Host Maximum Block Length This field indicates maximum block length by the Host Controller" "0x000=Not Used,0x001=1 byte,0x002=2 bytes,0x200=512 bytes,0x800=2048 bytes,0x801=FFFh"
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abitfld.quad 0x00 8.--15. "N_FCU,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller" "0x00=256 Blocks,0x01=1 Block,0x02=2 Block,0x03=3 Block,0xFF=255 Blocks"
group.long 0x120++0x03
line.long 0x00 "MMCSD0_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.long 0x00 27.--31. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error" "Not Affected,Vendor Specific Error Status is set,?..."
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bitfld.long 0x00 17. "TIMEOUT_DEADLOCK,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in" "Not affected,Timeout for Deadlock Error status.."
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bitfld.long 0x00 16. "TIMEOUT_CMD_RES,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in" "Not affected,Timout for CMD_RES Status is set"
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bitfld.long 0x00 15. "ADMA,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in" "Not affected,ADMA Error Status is set"
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bitfld.long 0x00 8. "EBSY,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in" "Not affected,EBSY Error Status is set"
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bitfld.long 0x00 7. "UNRECOVERABLE,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in" "Not affected,Unrecoverable Error Status is set"
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bitfld.long 0x00 5. "TID,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in" "Not affected,TID Error Status is set"
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bitfld.long 0x00 4. "FRAMING,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in" "Not affected,Framing Error Status is set"
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bitfld.long 0x00 3. "CRC,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in" "Not affected,CRC Error Status is set"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in" "Not affected,Retry expired error status is set"
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bitfld.long 0x00 1. "RES_PKT,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in" "Not affected,RES packet error status is set"
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bitfld.long 0x00 0. "HEADER,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in" "Not affected,Header error status is set"
rgroup.long 0x200++0x3B
line.long 0x00 "MMCSD0_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE. in BCD format"
bitfld.long 0x00 8.--11. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number (digit left of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number (digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VERSION_SUFFIX,eMMC Version Suffix (2nd digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MMCSD0_CQ_CAPABILITIES,This register is reserved for capability indication"
bitfld.long 0x04 12.--15. "CF_MUL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period" "0.001 MHz,0.01 MHz,0.1 MHz,1 MHz,10 MHz Other values..,?..."
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hexmask.long.word 0x04 0.--9. 1. "CF_VAL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling"
line.long 0x08 "MMCSD0_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time"
bitfld.long 0x08 12. "DCMD_ENA,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor" "Task descriptor in slot #31 is a Data Transfer..,Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x08 8. "TASK_DESC_SIZE,This bit indicates whether the task descriptor size is 128 bits or 64 bits" "Task descriptor size is 64 bits,Task descriptor size is 128 bits"
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bitfld.long 0x08 0. "CQ_ENABLE,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE)" "0,1"
line.long 0x0C "MMCSD0_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time"
bitfld.long 0x0C 8. "CLEAR_ALL_TASKS,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device" "0,1"
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bitfld.long 0x0C 0. "HALT_BIT,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus" "0,1"
line.long 0x10 "MMCSD0_CQ_INTR_STS,This register indicates pending interrupts that require service"
bitfld.long 0x10 4. "TASK_ERROR,This bit is asserted when task error is detected due to invalid task descriptor" "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED,This status bit is asserted (if" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET,This status bit is asserted (if Software uses" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,This status bit is asserted (if (1) A task is completed and the INT bit is set in its Task Descriptor (2) Interrupt caused by Interrupt Coalescing logic" "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE,This status bit is asserted (if" "0,1"
line.long 0x14 "MMCSD0_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register"
bitfld.long 0x14 4. "TASK_ERROR," "0,1"
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bitfld.long 0x14 3. "TASK_CLEARED," "0,1"
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bitfld.long 0x14 2. "RESP_ERR_DET," "0,1"
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bitfld.long 0x14 1. "TASK_COMPLETE," "0,1"
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bitfld.long 0x14 0. "HALT_COMPLETE," "0,1"
line.long 0x18 "MMCSD0_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software"
bitfld.long 0x18 4. "TASK_ERROR,When set and" "0,1"
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bitfld.long 0x18 3. "TASK_CLEARED,When set and" "0,1"
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bitfld.long 0x18 2. "RESP_ERR_DET,When set and" "0,1"
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bitfld.long 0x18 1. "TASK_COMPLETE,When set and" "0,1"
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bitfld.long 0x18 0. "HALT_COMPLETE,When set and" "0,1"
line.long 0x1C "MMCSD0_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature"
bitfld.long 0x1C 31. "CQINTCOALESC_ENABLE,When set to 0h by software command responses are neither counted nor timed" "0,1"
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bitfld.long 0x1C 20. "IC_STATUS,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0)" "No task completions have occurred since last..,At least one task completion has been counted.."
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bitfld.long 0x1C 8.--12. "CTR_THRESHOLD,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x1C 0.--6. 1. "TIMEOUT_VAL,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt"
line.long 0x20 "MMCSD0_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory"
line.long 0x24 "MMCSD0_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory"
line.long 0x28 "MMCSD0_CQ_TASK_DOOR_BELL,Using this register. software triggers CQE to process a new task"
line.long 0x2C "MMCSD0_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks"
line.long 0x30 "MMCSD0_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status"
line.long 0x34 "MMCSD0_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device. awaiting execution"
line.long 0x38 "MMCSD0_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327"
group.long 0x240++0x0B
line.long 0x00 "MMCSD0_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent"
bitfld.long 0x00 16.--19. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling"
line.long 0x04 "MMCSD0_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument"
hexmask.long.word 0x04 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument"
line.long 0x08 "MMCSD0_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software"
rgroup.long 0x250++0x13
line.long 0x00 "MMCSD0_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt"
line.long 0x04 "MMCSD0_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity"
bitfld.long 0x04 31. "DATERR_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 24.--28. "DATERR_TASK_ID,This field indicates the ID of the task which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--21. "DATERR_CMD_INDEX,This field indicates the index of the command which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "RESP_MODE_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 8.--12. "RESP_MODE_TASK_ID,This field indicates the ID of the task which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "RESP_MODE_CMD_INDEX,This field indicates the index of the command which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MMCSD0_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response"
bitfld.long 0x08 0.--5. "LAST_CRI,This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MMCSD0_CQ_CMD_RESP_ARG,This register stores the index of the last received command response"
line.long 0x10 "MMCSD0_CQ_ERROR_TASK_ID,CQ Error Task ID Register"
bitfld.long 0x10 0.--4. "TERR_ID,Task Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 7. (list 12. 13. 14. 15. 16. 17. 18. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
rgroup.byte ($2+0xD0)++0x00
line.byte 0x00 "MMCSD0_UHS2_RESPONSE_$1,This register is used to store received UHS-II RES Packet image"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.byte ($2+0x88)++0x00
line.byte 0x00 "MMCSD0_UHS2_COMMAND_PKT_$1,UHS-II Command Packet image is set to this register"
repeat.end
repeat 9. (list 1. 2. 3. 4. 5. 6. 7. 8. 10. )(list 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x10 0x12 )
rgroup.word ($2+0x62)++0x01
line.word 0x00 "MMCSD0_PRESET_VALUE$1,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value"
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes" "Driver Type D is Selected,Driver Type C is Selected,Driver Type A is Selected,Driver Type B is Selected"
bitfld.word 0x00 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "Host Controller Version 2.00 Compatible Clock..,Programmable Clock Generator"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set"
repeat.end
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
rgroup.word ($2+0x10)++0x01
line.word 0x00 "MMCSD0_RESPONSE_$1,This registers is used to store responses from SD Cards"
repeat.end
tree.end
tree.end
tree "MMCSD0_RX_RAM_ECC_Aggregator"
tree "MMCSD0_ECC_AGGR_RXMEM"
base ad:0x2A24000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD0_RXECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MMCSD0_RXECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MMCSD0_RXECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "MMCSD0_RXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,SEC EOI" "0,1"
line.long 0x04 "MMCSD0_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MMCSD0_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MMCSD0_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MMCSD0_RXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,DED EOI" "0,1"
line.long 0x04 "MMCSD0_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MMCSD0_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MMCSD0_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MMCSD0_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MMCSD0_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MMCSD0_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MMCSD0_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MMCSD0_Subsystem"
tree "MMCSD0_SS_CFG"
base ad:0x4F88000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD0_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MIN_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x37
line.long 0x00 "MMCSD0_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x00 24.--29. "TUNINGCOUNT,Configures the number of Taps (Phases) of the RX clock that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode" "0,1"
bitfld.long 0x00 12.--15. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x04 "MMCSD0_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x04 30.--31. "SLOTTYPE,Slot Type Should be set based on the final product usage" "0,1,2,3"
bitfld.long 0x04 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt)" "0,1"
bitfld.long 0x04 26. "SUPPORT1P8VOLT,1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by Core)" "0,1"
bitfld.long 0x04 25. "SUPPORT3P0VOLT,3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface" "0,1"
bitfld.long 0x04 24. "SUPPORT3P3VOLT,3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface" "0,1"
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bitfld.long 0x04 23. "SUSPRESSUPPORT,Suspend/Resume Support Suggested Value is 1h (The Suspend/Resume is supported by Core)" "0,1"
bitfld.long 0x04 22. "SDMASUPPORT,SDMA Support Suggested Value is 1h (The SDMA is supported by Core)" "0,1"
bitfld.long 0x04 21. "HIGHSPEEDSUPPORT,High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core)" "0,1"
bitfld.long 0x04 19. "ADMA2SUPPORT,ADMA2 Support Suggested Value is 1h (The ADMA2 is supported by Core)" "0,1"
bitfld.long 0x04 18. "SUPPORT8BIT,8-bit Support for Embedded Device Suggested Value is 1h (The Core supports 8-bit Interface)" "0,1"
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bitfld.long 0x04 16.--17. "MAXBLKLENGTH,Max Block Length Maximum Block Length supported by the Core/Device" "0,1,2,3"
hexmask.long.byte 0x04 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock This is the frequency of the xin_clk"
bitfld.long 0x04 7. "TIMEOUTCLKUNIT,Timeout Clock Unit Suggested Value is 0h (KHz)" "0,1"
bitfld.long 0x04 0.--5. "TIMEOUTCLKFREQ,Timeout Clock Frequency Suggested Value is 1 KHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MMCSD0_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x08 31. "HS400SUPPORT,HS400 Support Suggested Value is 1h (The Core supports HS400 Mode)" "0,1"
bitfld.long 0x08 28. "SUPPORT1P8VDD2,1.8 V VDD2 Support" "0,1"
bitfld.long 0x08 27. "ADMA3SUPPORT,ADMA3 Support" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator"
bitfld.long 0x08 14.--15. "RETUNINGMODES,Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning" "0,1,2,3"
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bitfld.long 0x08 13. "TUNINGFORSDR50,Use Tuning for SDR50 This bit should be set if the application wants Tuning be used for SDR50 Modes" "0,1"
bitfld.long 0x08 8.--11. "RETUNINGTIMERCNT,Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 7. "TYPE4SUPPORT,Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 6. "DDRIVERSUPPORT,Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 5. "CDRIVERSUPPORT,Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not" "0,1"
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bitfld.long 0x08 4. "ADRIVERSUPPORT,Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 2. "DDR50SUPPORT,DDR50 Support Suggested Value is 1h (The Core supports DDR50 mode of operation)" "0,1"
bitfld.long 0x08 1. "SDR104SUPPORT,SDR104 Support" "0,1"
bitfld.long 0x08 0. "SDR50SUPPORT,SDR50 Support" "0,1"
line.long 0x0C "MMCSD0_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.byte 0x0C 16.--23. 1. "MAXCURRENT1P8V,Maximum Current For 1.8 V"
hexmask.long.byte 0x0C 8.--15. 1. "MAXCURRENT3P0V,Maximum Current For 3.0 V"
hexmask.long.byte 0x0C 0.--7. 1. "MAXCURRENT3P3V,Maximum Current For 3.3 V"
line.long 0x10 "MMCSD0_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current For 1.8 V (VDD2)"
line.long 0x14 "MMCSD0_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value For Initialization"
line.long 0x18 "MMCSD0_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value For Default Speed"
line.long 0x1C "MMCSD0_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value For High Speed"
line.long 0x20 "MMCSD0_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value For SDR12"
line.long 0x24 "MMCSD0_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value For SDR25"
line.long 0x28 "MMCSD0_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value For SDR50"
line.long 0x2C "MMCSD0_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value For SDR104"
line.long 0x30 "MMCSD0_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value For DDR50"
line.long 0x34 "MMCSD0_SS_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x34 0.--12. 1. "HS400PRESETVAL,Preset Value For HS400"
rgroup.long 0x60++0x17
line.long 0x00 "MMCSD0_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller"
bitfld.long 0x00 31. "SDHC_CMDIDLE,Idle signal to enable software to gate off the clocks" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus"
line.long 0x04 "MMCSD0_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x04 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus"
line.long 0x08 "MMCSD0_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x08 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus"
line.long 0x0C "MMCSD0_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x0C 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)"
line.long 0x10 "MMCSD0_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)"
line.long 0x14 "MMCSD0_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus"
group.long 0x100++0x17
line.long 0x00 "MMCSD0_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x00 20.--22. "DR_TY,Drive Source/Sink Impedance Programming" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 17. "RETRIM,Start CALIO Calibration Cycle At positive edge initiates CALIO calibration cycle" "0,1"
bitfld.long 0x00 16. "EN_RTRIM,CALIO Enable Enables CALIO If enabled CALIO will start calibration cycle at phyctrl_pdb positive edge" "0,1"
bitfld.long 0x00 4.--7. "DLL_TRM_ICP,Analog DLL's Charge Pump Current Trim Programs the analog DLL loop gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "ENDLL,Enable DLL Enables the analog DLL circuits" "0,1"
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bitfld.long 0x00 0. "PDB,CALIO S/M Power Down Bar SoC asserts after power up sequence is completed" "0,1"
line.long 0x04 "MMCSD0_SS_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x04 29. "OD_RELEASE_STRB,Disable an internal 4.7 K pull up resistor on STRB line in open drain mode" "0,1"
bitfld.long 0x04 28. "OD_RELEASE_CMD,Disable an internal 4.7 K pull up resistor on CMD line in open drain mode" "0,1"
hexmask.long.byte 0x04 16.--23. 1. "OD_RELEASE_DAT,Disable an internal 4.7 K pull up resistor on data lines in open drain mode"
bitfld.long 0x04 13. "ODEN_STRB,Open Drain Enable On STRB Lline" "0,1"
bitfld.long 0x04 12. "ODEN_CMD,Open Drain Enable On CMD Line" "0,1"
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hexmask.long.byte 0x04 0.--7. 1. "ODEN_DAT,Open Drain Enable On DAT Lines"
line.long 0x08 "MMCSD0_SS_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x08 29. "PU_STRB,Enable Pull Up On STRB Line If ren_strb is high week pull up is enabled on STRB line" "0,1"
bitfld.long 0x08 28. "PU_CMD,Enable Pull Up On CMD Line If ren_cmd is high week pull up is enabled on CMD line" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "PU_DAT,Enable Pull Up On DAT Lines If ren_dat is high week pull up is enabled on DATA lines"
bitfld.long 0x08 13. "REN_STRB,Enable Pull Up/Down On The STRB Line If pu_strb is high a week pull up is enabled on STRB line if low week pull down is enabled on STRB line" "0,1"
bitfld.long 0x08 12. "REN_CMD,Enable Pull Up/Down On The CMD Line If pu_cmd is high a week pull up is enabled on CMD line if low week pull down is enabled on CMD line" "0,1"
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hexmask.long.byte 0x08 0.--7. 1. "REN_DAT,Enable Pull Up/Down On The DAT Lines If pu_dat is high a week pull up is enabled on DATA lines if low week pull down is enabled on DATA lines"
line.long 0x0C "MMCSD0_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY"
hexmask.long.byte 0x0C 24.--31. 1. "STRBSEL,Select the Four Taps for each of STRB_90 and STRB_180 Outputs"
bitfld.long 0x0C 20. "OTAPDLYENA,Output Tap Delay Enable Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface" "0,1"
bitfld.long 0x0C 12.--15. "OTAPDLYSEL,Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 9. "ITAPCHGWIN,Input Tap Change Window It gets asserted by the controller while changing the itapdlysel" "0,1"
bitfld.long 0x0C 8. "ITAPDLYENA,Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes" "0,1"
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bitfld.long 0x0C 0.--4. "ITAPDLYSEL,Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "MMCSD0_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x10 17. "SELDLYTXCLK,Select the Delay chain based txclk" "0,1"
bitfld.long 0x10 16. "SELDLYRXCLK,Select the Delay chain based rxclk" "0,1"
bitfld.long 0x10 8.--10. "FRQSEL,Select the frequency range of DLL operation" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select" "0,1,2,3,4,5,6,7"
line.long 0x14 "MMCSD0_SS_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x14 31. "BISTENABLE,Internal BIST Operation Enable Enables the embedded BIST" "0,1"
bitfld.long 0x14 30. "BISTSTART,Internal BIST Start Starts the embedded BIST operation" "0,1"
bitfld.long 0x14 24.--27. "BISTMODE,Internal BIST Mode Select Select the embedded BIST mode of operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x14 0.--7. 1. "TESTCTRL,PHY Test Control"
rgroup.long 0x130++0x07
line.long 0x00 "MMCSD0_SS_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Host Controller PHY ports"
bitfld.long 0x00 4.--7. "RTRIM,CALIO Calibration Result Holds the content of CALIO Impedance Calibration Result" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "BISTDONE,Internal BIST Completed Test Cycle Indicates that the embedded BIST has completed the test cycle" "0,1"
bitfld.long 0x00 2. "EXR_NINST,External Resistor On CALIO Absent Indicates trim cycle started and external resistor is absent" "0,1"
bitfld.long 0x00 1. "CALDONE,STATUS indicate that CALIO Calibration is completed successfully" "0,1"
bitfld.long 0x00 0. "DLLRDY,DLL Ready Indicates that DLL loop is locked" "0,1"
line.long 0x04 "MMCSD0_SS_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Host Controller PHY ports"
tree.end
tree.end
tree "MMCSD0_TX_RAM_ECC_Aggregator"
tree "MMCSD0_ECC_AGGR_TXMEM"
base ad:0x2A25000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD0_TXECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MMCSD0_TXECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MMCSD0_TXECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "MMCSD0_TXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,SEC EOI" "0,1"
line.long 0x04 "MMCSD0_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MMCSD0_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MMCSD0_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MMCSD0_TXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,DED EOI" "0,1"
line.long 0x04 "MMCSD0_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MMCSD0_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MMCSD0_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MMCSD0_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MMCSD0_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MMCSD0_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MMCSD0_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MMCSD1___MMCSD2_Host_Controller"
tree "MMCSD1_CTL_CFG"
base ad:0x4FB0000
group.word 0x00++0x0F
line.word 0x00 "MMCSD12_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10"
line.word 0x02 "MMCSD12_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10"
line.word 0x04 "MMCSD12_BLOCK_SIZE,This register is used to configure the number of bytes in a data block"
bitfld.word 0x04 12.--14. "SDMA_BUF_SIZE,Host SDMA Buffer Size To perform long DMA transfer System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry.." "4KB (Detects A11 Carry out),8KB (Detects A12 Carry out),16KB (Detects A13 Carry out),32KB (Detects A14 Carry out),64KB (Detects A15 Carry out),128KB (Detects A16 Carry out),256KB (Detects A17 Carry out),512KB (Detects A18 Carry out)"
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abitfld.word 0x04 0.--11. "XFER_BLK_SIZE,Transfer Block Size This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53" "0x000=No Data Transfer,0x001=1 Byte,0x002=2 Bytes,0x003=3 Bytes,0x004=4 Bytes,0x1FF=511 Bytes,0x200=512 Bytes,0x800=2048 Bytes"
line.word 0x06 "MMCSD12_BLOCK_COUNT,This register is used to configure the number of data blocks"
line.word 0x08 "MMCSD12_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument"
line.word 0x0A "MMCSD12_ARGUMENT1_HI,This register contains higher bits of SD Command Argument"
line.word 0x0C "MMCSD12_TRANSFER_MODE,"
bitfld.word 0x0C 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Interrupt is enabled,Response Interrupt is disabled"
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bitfld.word 0x0C 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Error Check is disabled,Response Error Check is enabled"
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bitfld.word 0x0C 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "R1 (Memory),R5 (SDIO)"
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bitfld.word 0x0C 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit enables multiple block data transfers" "Single Block,Multiple Block"
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bitfld.word 0x0C 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of data transfers" "Write (Host to Card),Read (Card to Host)"
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bitfld.word 0x0C 2.--3. "AUTO_CMD_ENA,Auto CMD Enable This field determines use of auto command functions" "Auto Command Disabled,Auto CMD12 Enable,Auto CMD23 Enable,Reserved"
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bitfld.word 0x0C 1. "BLK_CNT_ENA,Block Count Enable This bit is used to enable" "Disable,Enable"
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bitfld.word 0x0C 0. "DMA_ENA,DMA Enable DMA can be enabled only if" "Disable,Enable"
line.word 0x0E "MMCSD12_COMMAND,This register is used to program the Command for host controller"
bitfld.word 0x0E 8.--13. "CMD_INDEX,Command Index This bit shall be set to the command number (CMD0-63 ACMD0-63)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x0E 6.--7. "CMD_TYPE,Command Type There are three types of special commands" "Normal,Suspend,Resume,Abort"
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bitfld.word 0x0E 5. "DATA_PRESENT,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line" "No Data Present,Data Present"
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bitfld.word 0x0E 4. "CMD_INDEX_CHK_ENA,Command Index Check Enable If this bit is set to 1h the HC shall check the index field in the response to see if it has the same value as the command index" "Disable,Enable"
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bitfld.word 0x0E 3. "CMD_CRC_CHK_ENA,Command CRC Check Enable If this bit is set to 1h the HC shall check the CRC field in the response" "Disable,Enable"
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bitfld.word 0x0E 2. "SUB_CMD,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command" "Sub Command,Main Command"
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bitfld.word 0x0E 0.--1. "RESP_TYPE_SEL,Response Type Select" "No Response,Response length 136,Response length 48,Response length 48 check Busy after response"
group.long 0x20++0x07
line.long 0x00 "MMCSD12_DATA_PORT,This register is used to access internal buffer"
line.long 0x04 "MMCSD12_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x04 31. "UHS2_IF_DETECTION,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF" "UHS-II IF is not detected,UHS-II IF is detected"
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bitfld.long 0x04 30. "UHS2_IF_LANE_SYNC,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode" "UHS-II PHY is not initialized,UHS-II PHY is initialized"
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bitfld.long 0x04 29. "UHS2_DORMANT,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state" "Not in DORMANT state,In DORMANT state"
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bitfld.long 0x04 28. "SUB_COMMAND_STS,Sub Command Status" "Main Command Status,Sub Command Status"
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bitfld.long 0x04 27. "CMD_NOT_ISS_BY_ERR,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in.." "No error for issuing a command,Command cannot be issued"
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bitfld.long 0x04 24. "SDIF_CMDIN,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 23. "SDIF_DAT3IN,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 22. "SDIF_DAT2IN,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 21. "SDIF_DAT1IN,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 20. "SDIF_DAT0IN,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 19. "WRITE_PROTECT,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin" "Write protected (SDWP# = 1),Write enabled (SDWP# = 0)"
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bitfld.long 0x04 18. "CARD_DETECT,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin" "No Card present (SDCD# = 1),Card present (SDCD# = 0)"
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bitfld.long 0x04 17. "CARD_STATE_STABLE,Card State Stable This bit is used for testing" "Reset of Debouncing,No Card or Inserted"
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bitfld.long 0x04 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted" "Reset or Debouncing or No Card,Card Inserted"
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bitfld.long 0x04 11. "BUF_RD_ENA,Buffer Read Enable This status is used for non-DMA read transfers" "Read Disable,Read Enable"
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bitfld.long 0x04 10. "BUF_WR_ENA,Buffer Write Enable This status is used for non-DMA write transfers" "Write Disable,Write Enable"
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bitfld.long 0x04 9. "RD_XFER_ACTIVE,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer" "No valid data,Transferring data"
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bitfld.long 0x04 8. "WR_XFER_ACTIVE,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active" "No valid data,Transferring data"
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bitfld.long 0x04 7. "SDIF_DAT7IN,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 6. "SDIF_DAT6IN,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 5. "SDIF_DAT5IN,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 4. "SDIF_DAT4IN,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 3. "RETUNING_REQ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive.." "Fixed or well tuned sampling clock,Sampling clock needs re-tuning"
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bitfld.long 0x04 2. "DATA_LINE_ACTIVE,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use" "DAT line inactive,DAT line active"
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bitfld.long 0x04 1. "INHIBIT_DAT,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h" "Can issue command which uses the DAT line,Cannot issue command which uses the DAT line"
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bitfld.long 0x04 0. "INHIBIT_CMD,Command Inhibit (CMD)" "Host Controller is ready to issue a command..,Host Controller is not ready to issue a command"
group.byte 0x28++0x03
line.byte 0x00 "MMCSD12_HOST_CONTROL1,This register is used to program DMA modes. LED control. data transfer width. High Speed enable. card detect test level and signal selection"
bitfld.byte 0x00 7. "CD_SIG_SEL,Card Detect Signal Detection This bit selects source for card detection" "SDCD# is selected (for normal use),The card detect test level is selected"
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bitfld.byte 0x00 6. "CD_TEST_LEVEL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not" "No Card,Card Inserted"
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bitfld.byte 0x00 5. "EXT_DATA_WIDTH,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device" "Bus Width is Selected by Data Transfer Width,8-bit Bus Width"
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bitfld.byte 0x00 3.--4. "DMA_SELECT,DMA Select This field is used to select DMA type" "0,1,2,3"
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bitfld.byte 0x00 2. "HIGH_SPEED_ENA,High Speed Enable (SD Mode Only) This bit is optional" "Normal Speed Mode,High Speed Mode"
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bitfld.byte 0x00 1. "DATA_WIDTH,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC" "1 bit mode,4 bit mode"
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bitfld.byte 0x00 0. "LED_CONTROL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed" "LED off,LED on"
line.byte 0x01 "MMCSD12_POWER_CONTROL,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x01 5.--7. "UHS2_VOLTAGE,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2" "VDD2 Not Supported,Reserved,?,?,Reserved for 1.2 V,1.8 V,Not used,Not used"
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bitfld.byte 0x01 4. "UHS2_POWER,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2" "Power off,Power on"
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bitfld.byte 0x01 1.--3. "SD_BUS_VOLTAGE,SD Bus Voltage Select for VDD1 By setting these bits the HD selects the voltage level for the SD card" "Reserved,?,?,?,?,1.8 V (Typ.) for Embedded,3.0 V (Typ.),3.3 V (Flattop.)"
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bitfld.byte 0x01 0. "SD_BUS_POWER,SD Bus Power for VDD1 Before setting this bit the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state) and drive SDCLK to low level. If card.." "Power off,Power on"
line.byte 0x02 "MMCSD12_BLOCK_GAP_CONTROL,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x02 7. "BOOT_ACK_ENA,Boot Acknowledge Check To check for the boot acknowledge in boot operation" "Will not wait for boot ack from eMMC card,Wait for boot ack from eMMC card"
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bitfld.byte 0x02 6. "ALT_BOOT_MODE,Alternative Boot Mode To start boot code access in alternative mode" "To stop alternate boot mode access,To start alternate boot mode access"
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bitfld.byte 0x02 5. "BOOT_ENABLE,Boot Enable To start boot code access" "To stop boot code access,To start boot code access"
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bitfld.byte 0x02 3. "INTRPT_AT_BLK_GAP,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle" "0,1"
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bitfld.byte 0x02 2. "RDWAIT_CTRL,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards" "Disable Read Wait Control,Enable Read Wait Control"
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bitfld.byte 0x02 1. "CONTINUE,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request" "Ignored,Restart"
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bitfld.byte 0x02 0. "STOP_AT_BLK_GAP,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA SDMA and ADMA transfers" "Transfer,Stop"
line.byte 0x03 "MMCSD12_WAKEUP_CONTROL,This register is used to program the wakeup functionality"
bitfld.byte 0x03 2. "CARD_REMOVAL,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit" "Disable,Enable"
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bitfld.byte 0x03 1. "CARD_INSERTION,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit" "Disable,Enable"
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bitfld.byte 0x03 0. "CARD_INTERRUPT,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h" "Disable,Enable"
group.word 0x2C++0x01
line.word 0x00 "MMCSD12_CLOCK_CONTROL,This register is used to program the Clock frequency select. Clock generator select. Clock enable. Internal clock state fields"
hexmask.word.byte 0x00 8.--15. 1. "SDCLK_FRQSEL,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin"
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bitfld.word 0x00 6.--7. "SDCLK_FRQSEL_UPBITS,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to" "0,1,2,3"
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bitfld.word 0x00 5. "CLKGEN_SEL,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h:.." "Divided Clock Mode,Programmable Clock Mode"
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bitfld.word 0x00 3. "PLL_ENA,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL" "PLL is in low power mode,PLL is enabled"
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bitfld.word 0x00 2. "SD_CLK_ENA,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h" "Disable providing SDCLK or RCLK,Enable providing SDCLK or RCLK"
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bitfld.word 0x00 1. "INT_CLK_STABLE,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller.." "Not Ready,Ready"
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bitfld.word 0x00 0. "INT_CLK_ENA,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event" "Stop,Oscillate"
group.byte 0x2E++0x01
line.byte 0x00 "MMCSD12_TIMEOUT_CONTROL,The register sets the data timeout counter value"
bitfld.byte 0x00 0.--3. "COUNTER_VALUE,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x,Reserved"
line.byte 0x01 "MMCSD12_SOFTWARE_RESET,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x01 2. "SWRST_FOR_DAT,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset" "Work,Reset"
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bitfld.byte 0x01 1. "SWRST_FOR_CMD,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command" "Work,Reset"
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bitfld.byte 0x01 0. "SWRST_FOR_ALL,Software Reset for All This reset affects the entire HC except for the card detection circuit" "Work,Reset"
group.word 0x30++0x0F
line.word 0x00 "MMCSD12_NORMAL_INTR_STS,This register gives the status of all the interrupts"
bitfld.word 0x00 15. "ERROR_INTR,Error Interrupt If any of the bits in the In UHS-II mode is enabled if any of the bits in" "No Error,Error"
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bitfld.word 0x00 14. "BOOT_COMPLETE,Boot Terminate Interrupt This status is set if the boot operation gets terminated" "Boot operation is not terminated,Boot operation is terminated"
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bitfld.word 0x00 13. "RCV_BOOT_ACK,Boot Acknowledge Receive This status is set if the boot acknowledge is received from device" "Boot acknowledge is not received,Boot acknowledge is received"
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bitfld.word 0x00 12. "RETUNING_EVENT,Re-Tuning Event (UHS-I Only) This status is set if the Host Controller requests Host Driver to perform re-tuning for next data transfer" "Re-Tuning is not required,Re-Tuning should be performed"
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rbitfld.word 0x00 11. "INTC,int_c (Embedded) This status is set if INT_C is enabled and INT_C# pin is in low level" "0,1"
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rbitfld.word 0x00 10. "INTB,int_b (Embedded) This status is set if INT_B is enabled and INT_B# pin is in low level" "0,1"
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rbitfld.word 0x00 9. "INTA,int_a (Embedded) This status is set if INT_A is enabled and INT_A# pin is in low level" "0,1"
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bitfld.word 0x00 8. "CARD_INTR,Card Interrupt When this status has been set and the Host Driver needs to start this interrupt service the Writing this bit to 1h does not clear this bit" "No Card Interrupt,Generate Card Interrupt"
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bitfld.word 0x00 7. "CARD_REM,Card Removal This status is set if" "Card State Stable or Debouncing,Card Removed"
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bitfld.word 0x00 6. "CARD_INS,Card Insertion This status is set if" "Card State Stable or Debouncing,Card Inserted"
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bitfld.word 0x00 5. "BUF_RD_READY,Buffer Read Ready This status is set if the The In UHS-II mode this bit is set at FC (Flow Control) unit basis" "Not Ready to read Buffer,Ready to read Buffer"
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bitfld.word 0x00 4. "BUF_WR_READY,Buffer Write Ready This status is set if the In UHS-II mode this bit is set at FC (Flow Control) unit basis" "Not Ready to Write Buffer,Ready to Write Buffer"
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bitfld.word 0x00 3. "DMA_INTERRUPT,DMA Interrupt This status is set if the HC detects the Host DMA Buffer Boundary in" "No DMA Interrupt,DMA Interrupt is Generated"
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bitfld.word 0x00 2. "BLK_GAP_EVENT,Block Gap Event If the Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (see Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (see 0h: No Block Gap Event 1h:.." "No Block Gap Event,Transaction stopped at Block Gap"
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bitfld.word 0x00 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transaction is completed" "Not complete,Command execution is completed"
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bitfld.word 0x00 0. "CMD_COMPLETE,Command Complete This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23)" "No Command Complete,Command Complete"
line.word 0x02 "MMCSD12_ERROR_INTR_STS,This register gives the status of the error interrupts"
bitfld.word 0x02 12. "HOST,Target Response Error Occurs when detecting ERROR in m_hresp (DMA transaction)" "No error,Error"
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bitfld.word 0x02 11. "RESP,Response Error (SD Mode Only) Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "No error,Error"
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bitfld.word 0x02 9. "ADMA,ADMA Error This bit is set when the Host Controller detects errors during ADMA based data transfer" "No error,Error"
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bitfld.word 0x02 8. "AUTO_CMD,Auto CMD Error (SD Mode Only) Auto CMD12 and Auto CMD23 use this error status" "No error,Error"
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bitfld.word 0x02 7. "CURR_LIMIT,Current Limit Error By setting" "No error,Power Fail"
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bitfld.word 0x02 6. "DATA_ENDBIT,Data End Bit Error (SD Mode Only) Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status" "No error,Error"
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bitfld.word 0x02 5. "DATA_CRC,Data CRC Error (SD Mode Only) Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h" "No error,Error"
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bitfld.word 0x02 4. "DATA_TIMEOUT,Data Timeout Error (SD Mode Only) Occurs when detecting one of following timeout conditions" "No error,Timeout"
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bitfld.word 0x02 3. "CMD_INDEX,Command Index Error (SD Mode Only) Occurs if a Command Index error occurs in the Command Response ( 0h: No error 1h: Error" "No error,Error"
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bitfld.word 0x02 2. "CMD_ENDBIT,Command End Bit Error (SD Mode Only) Occurs when detecting that the end bit of a command response is 0h" "No error,End Bit Error Generated"
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bitfld.word 0x02 1. "CMD_CRC,Command CRC Error (SD Mode Only) Command CRC Error is generated in two cases" "No error,CRC Error Generated"
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bitfld.word 0x02 0. "CMD_TIMEOUT,Command Timeout Error (SD Mode Only) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command" "No error,Timeout"
line.word 0x04 "MMCSD12_NORMAL_INTR_STS_ENA,This register is used to enable the register fields"
rbitfld.word 0x04 15. "BIT15_FIXED0,Fixed to 0 The HC shall control error Interrupts using" "0,1"
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bitfld.word 0x04 14. "BOOT_COMPLETE,Boot Terminate Interrupt Enable" "Masked,Enabled"
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bitfld.word 0x04 13. "RCV_BOOT_ACK,Boot Acknowledge Enable" "Masked,Enabled"
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bitfld.word 0x04 12. "RETUNING_EVENT,Re-Tuning Event Status Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x04 11. "INTC,INT_C Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 10. "INTB,INT_B Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 9. "INTA,INT_A Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 8. "CARD_INTERRUPT,Card Interrupt Status Enable If this bit is set to 0h the HC shall clear Interrupt request to the System" "Masked,Enabled"
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bitfld.word 0x04 7. "CARD_REMOVAL,Card Removal Status Enable" "Masked,Enabled"
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bitfld.word 0x04 6. "CARD_INSERTION,Card Insertion Status Enable" "Masked,Enabled"
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bitfld.word 0x04 5. "BUF_RD_READY,Buffer Read Ready Status Enable" "Masked,Enabled"
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bitfld.word 0x04 4. "BUF_WR_READY,Buffer Write Ready Status Enable" "Masked,Enabled"
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bitfld.word 0x04 3. "DMA_INTERRUPT,DMA Interrupt Status Enable" "Masked,Enabled"
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bitfld.word 0x04 2. "BLK_GAP_EVENT,Block Gap Event Status Enable" "Masked,Enabled"
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bitfld.word 0x04 1. "XFER_COMPLETE,Transfer Complete Status Enable" "Masked,Enabled"
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bitfld.word 0x04 0. "CMD_COMPLETE,Command Complete Status Enable" "Masked,Enabled"
line.word 0x06 "MMCSD12_ERROR_INTR_STS_ENA,This register is used to enable the register fields"
bitfld.word 0x06 12.--15. "VENDOR_SPECIFIC,Vendor Specific Error Status Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x06 11. "RESP,Response Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 10. "TUNING,Tuning Error Status Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x06 9. "ADMA,ADMA Error Status Enable" "Masked,Enabled"
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bitfld.word 0x06 8. "AUTO_CMD,Auto CMD Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 7. "CURR_LIMIT,Current Limit Error Status Enable" "Masked,Enabled"
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bitfld.word 0x06 6. "DATA_ENDBIT,Data End Bit Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 5. "DATA_CRC,Data CRC Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 4. "DATA_TIMEOUT,Data Timeout Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 3. "CMD_INDEX,Command Index Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 2. "CMD_ENDBIT,Command End Bit Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 1. "CMD_CRC,Command CRC Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 0. "CMD_TIMEOUT,Command Timeout Error Status Enable (SD Mode Only)" "Masked,Enabled"
line.word 0x08 "MMCSD12_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt"
rbitfld.word 0x08 15. "BIT15_FIXED0,Fixed to 0 The HD shall control error Interrupts using" "0,1"
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bitfld.word 0x08 14. "BOOT_COMPLETE,Boot Terminate Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 13. "RCV_BOOT_ACK,Boot Acknowledge Receive Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 12. "RETUNING_EVENT,Re-Tuning Event Signal Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x08 11. "INTC,INT_C Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 10. "INTB,INT_B Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 9. "INTA,INT_A Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 8. "CARD_INTERRUPT,Card Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 7. "CARD_REMOVAL,Card Removal Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 6. "CARD_INSERTION,Card Insertion Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 5. "BUF_RD_READY,Buffer Read Ready Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 4. "BUF_WR_READY,Buffer Write Ready Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 3. "DMA_INTERRUPT,DMA Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 2. "BLK_GAP_EVENT,Block Gap Event Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 1. "XFER_COMPLETE,Transfer Complete Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 0. "CMD_COMPLETE,Command Complete Signal Enable" "Masked,Enabled"
line.word 0x0A "MMCSD12_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt"
bitfld.word 0x0A 12.--15. "VENDOR_SPECIFIC,Vendor Specific Error Signal Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x0A 11. "RESP,Response Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 10. "TUNING,Tuning Error Signal Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x0A 9. "ADMA,ADMA Error Signal Enable" "Masked,Enabled"
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bitfld.word 0x0A 8. "AUTO_CMD,Auto CMD Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 7. "CURR_LIMIT,Current Limit Error Signal Enable" "Masked,Enabled"
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bitfld.word 0x0A 6. "DATA_ENDBIT,Data End Bit Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 5. "DATA_CRC,Data CRC Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 4. "DATA_TIMEOUT,Data Timeout Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 3. "CMD_INDEX,Command Index Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 2. "CMD_ENDBIT,Command End Bit Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 1. "CMD_CRC,Command CRC Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 0. "CMD_TIMEOUT,Command Timeout Error Signal Enable (SD Mode Only)" "Masked,Enabled"
line.word 0x0C "MMCSD12_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23"
bitfld.word 0x0C 7. "CMD_NOT_ISSUED,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register" "No Error,Not Issued"
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bitfld.word 0x0C 4. "INDEX,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command" "No Error,Error"
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bitfld.word 0x0C 3. "ENDBIT,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h" "No Error,End Bit Error Generated"
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bitfld.word 0x0C 2. "CRC,Auto CMD CRC Error Occurs when detecting a CRC error in the command response" "No Error,CRC Error Generated"
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bitfld.word 0x0C 1. "TIMEOUT,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command" "No Error,Timeout"
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bitfld.word 0x0C 0. "ACMD12_NOT_EXEC,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "Executed,Not Executed"
line.word 0x0E "MMCSD12_HOST_CONTROL2,This register is used to program UHS Mode Select. Driver Strength Select. Execute Tuning. Sampling Clock Select. Asynchronous Interrupt Enable and Preset Value Enable"
bitfld.word 0x0E 15. "PRESET_VALUE_ENA,Preset Value Enable Host Controller Version 3.00 supports this bit" "SDCLK and Driver Strength are controlled by Host..,Automatic Selection by Preset Value are Enabled"
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bitfld.word 0x0E 14. "ASYNCH_INTR_ENA,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and" "Disabled,Enabled"
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bitfld.word 0x0E 13. "BIT64_ADDRESSING,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory" "32-bits Addressing,64-bits Addressing"
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bitfld.word 0x0E 12. "HOST_VER40_ENA,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode" "Version 3.00 Compatible Mode,Version 4.Mode"
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bitfld.word 0x0E 11. "CMD23_ENA,CMD23 Enable In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]" "0,1"
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bitfld.word 0x0E 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit" "16-bit Data Length Mode,26-bit Data Length Mode"
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bitfld.word 0x0E 9. "DRIVER_STRENGTH2,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value" "0,1"
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bitfld.word 0x0E 8. "UHS2_INTF_ENABLE,UHS-II Interface Enable This bit is used to enable UHS-II Interface" "4-bit SD Interface Enabled,UHS-II Interface Enabled"
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bitfld.word 0x0E 7. "SAMPLING_CLK_SELECT,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when" "Fixed clock is used to sample data,Tuned clock is used to sample data"
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bitfld.word 0x0E 6. "EXECUTE_TUNING,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed" "Not Tuned or Tuning Completed,Execute Tuning"
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bitfld.word 0x0E 4.--5. "DRIVER_STRENGTH1,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit" "Driver Type B is Selected (Default),Driver Type A is Selected,Driver Type C is Selected,Driver Type D is Selected"
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bitfld.word 0x0E 3. "V1P8_SIGNAL_ENA,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell" "3.3 V Signaling,1.8 V Signaling"
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bitfld.word 0x0E 0.--2. "UHS_MODE_SELECT,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode" "SDR12,SDR25,SDR50,SDR104,DDR50,HS400,Reserved,UHS-II When.."
rgroup.quad 0x40++0x0F
line.quad 0x00 "MMCSD12_CAPABILITIES,This register provides the HD with information specific to the HC implementation"
bitfld.quad 0x00 63. "HS400_SUPPORT,HS400 Support" "HS400 is Not Supported,HS400 is Supported"
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bitfld.quad 0x00 60. "VDD2_1P8_SUPPORT,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system" "1.8 V VDD2 is not supported,1.8 V VDD2 is supported"
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bitfld.quad 0x00 59. "ADMA3_SUPPORT,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller" "ADMA3 is not supported,ADMA3 is supported"
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bitfld.quad 0x00 57. "SPI_BLK_MODE,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not" "Not Supported,Supported"
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bitfld.quad 0x00 56. "SPI_SUPPORT,SPI Mode This bit indicates whether SPI Mode is supported or not" "Not Supported,Supported"
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abitfld.quad 0x00 48.--55. "CLOCK_MULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" "0x00=Clock Multiplier is Not Supported,0x01=Clock Multiplier M = 2,0x02=Clock Multiplier M = 3,0xFF=Clock Multiplier M ="
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bitfld.quad 0x00 46.--47. "RETUNING_MODES,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver" "Mode 1,Mode 2,Mode 3,Reserved There.."
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bitfld.quad 0x00 45. "TUNING_FOR_SDR50,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104)" "SDR50 does not require tuning,SDR50 requires tuning"
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bitfld.quad 0x00 40.--43. "RETUNING_TIMER_CNT,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "Get information via other source,1 seconds,2 seconds,4 seconds,8 seconds ---- n =,?,?,?,?,?,?,1024 seconds,?,?,?,Ch = Reserved"
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bitfld.quad 0x00 38. "DRIVERD_SUPPORT,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling" "Driver Type D is Not Supported,Driver Type D is Supported"
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bitfld.quad 0x00 37. "DRIVERC_SUPPORT,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling" "Driver Type C is Not Supported,Driver Type C is Supported"
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bitfld.quad 0x00 36. "DRIVERA_SUPPORT,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling" "Driver Type A is Not Supported,Driver Type A is Supported"
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bitfld.quad 0x00 35. "UHS2_SUPPORT,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II" "UHS-II is Not Supported,UHS-II is Supported"
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bitfld.quad 0x00 34. "DDR50_SUPPORT,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not" "DDR50 is Not Supported,DDR50 is Supported"
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bitfld.quad 0x00 33. "SDR104_SUPPORT,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not" "SDR104 is Not Supported,SDR104 is Supported"
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bitfld.quad 0x00 32. "SDR50_SUPPORT,SDR50 Support (UHS-I Only) If SDR104 is supported this bit shall be set to 1h" "SDR50 is Not Supported,SDR50 is Supported"
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bitfld.quad 0x00 30.--31. "SLOT_TYPE,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot)" "Removable Card Slot,Embedded Slot for One Device,Shared Bus Slot (SD Mode),UHS-II Multiple Embedded Devices"
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bitfld.quad 0x00 29. "ASYNCH_INTR_SUPPORT,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "Asynchronous Interrupt Not Supported,Asynchronous Interrupt Supported"
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bitfld.quad 0x00 28. "ADDR_64BIT_SUPPORT_V3,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions" "64-bit System Address for V3 is not Supported,64-bit System Address for V3 is Supported"
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bitfld.quad 0x00 27. "ADDR_64BIT_SUPPORT_V4,64-bit System Address Support for V4 This bit is added from Version 4.10" "64-bit System Address for V4 is not Supported,64-bit System Address for V4 is Supported"
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bitfld.quad 0x00 26. "VOLT_1P8_SUPPORT,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V" "1.8 V Not Supported,1.8 V Supported"
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bitfld.quad 0x00 25. "VOLT_3P0_SUPPORT,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V" "3.0 V Not Supported,3.0 V Supported"
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bitfld.quad 0x00 24. "VOLT_3P3_SUPPORT,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V" "3.3 V Not Supported,3.3 V Supported"
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bitfld.quad 0x00 23. "SUSP_RES_SUPPORT,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality" "Not Supported,Supported"
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bitfld.quad 0x00 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly" "SDMA Not Supported,SDMA Supported"
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bitfld.quad 0x00 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC)" "High Speed Not Supported,High Speed Supported"
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bitfld.quad 0x00 19. "ADMA2_SUPPORT,ADMA2 Support" "ADMA2 Not support,ADMA2 support"
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bitfld.quad 0x00 18. "BUS_8BIT_SUPPORT,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode" "8-bit Bus Width Not Supported,8-bit Bus Width Supported"
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bitfld.quad 0x00 16.--17. "MAX_BLK_LENGTH,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC" "512 byte,1024 byte,2048 byte,4096 byte"
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abitfld.quad 0x00 8.--15. "BASE_CLK_FREQ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00" "0x00=Get Information via..,0x01=1 MHz,0x02=2 MHz,0x0F=63 MHz 0000,0xFF=255 MHz"
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bitfld.quad 0x00 7. "TIMEOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "KHz,MHz"
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bitfld.quad 0x00 0.--5. "TIMEOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "MMCSD12_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x08 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8 V VDD2"
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hexmask.quad.byte 0x08 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8 V VDD1"
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hexmask.quad.byte 0x08 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0 V VDD1"
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hexmask.quad.byte 0x08 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3 V VDD1"
group.word 0x50++0x03
line.word 0x00 "MMCSD12_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.word 0x00 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error" "Not Affected,Command Not Issued By Auto CMD12.."
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bitfld.word 0x00 5. "RESP,Force Event for AUTO CMD Response Error" "Not Affected,Auto CMD Response Error Status is.."
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bitfld.word 0x00 4. "INDEX,Force Event for AUTO CMD Index Error" "Not Affected,Auto CMD Index Error Status is set"
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bitfld.word 0x00 3. "ENDBIT,Force Event for AUTO CMD End Bit Error" "Not Affected,Auto CMD End bit Error Status is set"
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bitfld.word 0x00 2. "CRC,Force Event for AUTO CMD Timeout Error" "Not Affected,Auto CMD CRC Error Status is set"
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bitfld.word 0x00 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error" "Not Affected,Auto CMD Timeout Error Status is set"
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bitfld.word 0x00 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed" "Not Affected,Auto CMD12 Not Executed Status is.."
line.word 0x02 "MMCSD12_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.word 0x02 12.--15. "VEND_SPEC,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x02 11. "RESP,Force Event for Response Error" "Not Affected,Response Error Status is set"
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bitfld.word 0x02 10. "TUNING,Force Event for Tuning Error" "Not Affected,Tuning Error Status is set"
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bitfld.word 0x02 9. "ADMA,Force Event for ADMA Error" "Not Affected,ADMA Error Status is set"
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bitfld.word 0x02 8. "AUTO_CMD,Force Event for Auto CMD Error" "Not Affected,Auto CMD Error Status is set"
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bitfld.word 0x02 7. "CURR_LIM,Force Event for Current Limit Error" "Not Affected,Current Limit Error Status is set"
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bitfld.word 0x02 6. "DAT_ENDBIT,Force Event for Data End Bit Error" "Not Affected,Data End Bit Error Status is set"
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bitfld.word 0x02 5. "DAT_CRC,Force Event for Data CRC Error" "Not Affected,CRC Error Status is set"
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bitfld.word 0x02 4. "DAT_TIMEOUT,Force Event for Data Timeout Error" "Not Affected,Timeout Error Status is set"
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bitfld.word 0x02 3. "CMD_INDEX,Force Event for Command Index Error" "Not Affected,Command Index Error Status is set"
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bitfld.word 0x02 2. "CMD_ENDBIT,Force Event for Command End Bit Error" "Not Affected,Command End Bit Error Status is set"
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bitfld.word 0x02 1. "CMD_CRC,Force Event for Command CRC Error" "Not Affected,Command CRC Error Status is set"
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bitfld.word 0x02 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error" "Not Affected,Command Timeout Error Status is set"
rgroup.byte 0x54++0x00
line.byte 0x00 "MMCSD12_ADMA_ERR_STATUS,When the ADMA Error interrupt occur. this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor"
bitfld.byte 0x00 2. "ADMA_LENGTH_ERR,ADMA Length Mismatch Error This error occurs in the following 2 cases" "No Error,Error"
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bitfld.byte 0x00 0.--1. "ADMA_ERR_STATE,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer" "ST_STOP (Stop DMA) Points to next of the error..,ST_FDS (Fetch Descriptor) Points to the error..,Never set this state (Not used),ST_TFR (Transfer Data) Points to the next of the.."
group.quad 0x58++0x07
line.quad 0x00 "MMCSD12_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer"
rgroup.word 0x60++0x01
line.word 0x00 "MMCSD12_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value"
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes" "Driver Type D is Selected,Driver Type C is Selected,Driver Type A is Selected,Driver Type B is Selected"
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bitfld.word 0x00 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "Host Controller Version 2.00 Compatible Clock..,Programmable Clock Generator"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set"
group.quad 0x78++0x07
line.quad 0x00 "MMCSD12_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register"
group.word 0x80++0x01
line.word 0x00 "MMCSD12_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BOUNDARY,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging SDMA data transfer is performed in unit of paging" "4K bytes (Detects A11 carry out),8K bytes (Detects A12 carry out),16K Bytes (Detects A13 carry out),32K Bytes (Detects A14 carry out),64K bytes (Detects A15 carry out),128K Bytes (Detects A16 carry out),256K Bytes (Detects A17 carry out),512K Bytes (Detects A18 carry out)"
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hexmask.word 0x00 0.--11. 1. "XFER_BLK_SIZE,UHS-II Block Size This bit field specifies the block size of data packet"
group.long 0x84++0x03
line.long 0x00 "MMCSD12_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks"
group.word 0x9C++0x03
line.word 0x00 "MMCSD12_UHS2_XFER_MODE,This register is used to control the operations of data transfers"
bitfld.word 0x00 15. "DUPLEX_SELECT,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver" "Full Duplex Mode,2 Lane Half Duplex Mode"
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bitfld.word 0x00 14. "EBSY_WAIT,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution" "Issue a command without..,Wait EBSY"
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bitfld.word 0x00 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Interrupt is enabled,Response Interrupt is disabled"
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bitfld.word 0x00 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Error Check is disabled,Response Error Check is enabled"
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bitfld.word 0x00 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled this bit selects either R1 or R5 response types" "R1 (Memory),R5 (SDIO)"
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bitfld.word 0x00 5. "BYTE_MODE,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when" "Block Mode,Byte Mode"
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bitfld.word 0x00 4. "DATA_XFER_DIR,Data Transfer Direction This bit specifies direction of data transfer when" "Read (Card to Host),Write (Host to Card)"
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bitfld.word 0x00 1. "BLK_CNT_ENA,Block Count Enable This bit specifies whether data transfer uses" "Block Count Disabled,Block Count Enabled"
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bitfld.word 0x00 0. "DMA_ENA,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer" "DMA is disabled,DMA is enabled"
line.word 0x02 "MMCSD12_UHS2_COMMAND,This register is used to program the Command for host controller"
bitfld.word 0x02 8.--12. "PKT_LENGTH,UHS-II Command Packet Length A command packet length which is set in the UHS-II Command Packet register ( 00011b - 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b - 10101b" "3-0 Bytes (Not used),?,?,?,4 Bytes,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20 Bytes 11111b - 10101b,?..."
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bitfld.word 0x02 6.--7. "CMD_TYPE,Command Type This field is used to distinguish a specific command like abort command" "Normal Command,TRANS_ABORT CCMD,CMD12 or SDIO Abort command,Go Dormant Command"
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bitfld.word 0x02 5. "DATA_PRESENT,Data Present This bit specifies whether the command is accompanied by data packet" "No Data Present,Data Present"
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bitfld.word 0x02 2. "SUB_COMMAND,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command" "Sub Command,Main Command"
rgroup.byte 0xA0++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_0,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xA4++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_1,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xA8++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_2,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xAC++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_3,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xB0++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_4,This register is used to store received UHS-II RES Packet image"
group.byte 0xB4++0x00
line.byte 0x00 "MMCSD12_UHS2_MESSAGE_SELECT,This register is used to access internal buffer"
bitfld.byte 0x00 0.--1. "MSG_SEL,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer" "The latest MSG,One MSG before,Two MSGs before,Three MSGs before"
rgroup.byte 0xB4++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_5,This register is used to store received UHS-II RES Packet image"
rgroup.long 0xB8++0x03
line.long 0x00 "MMCSD12_UHS2_MESSAGE,This register is used to access internal buffer"
hexmask.long.byte 0x00 24.--31. 1. "MSG_BYTE3,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 16.--23. 1. "MSG_BYTE2,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 8.--15. 1. "MSG_BYTE1,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 0.--7. 1. "MSG_BYTE0,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
rgroup.byte 0xB8++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_6,This register is used to store received UHS-II RES Packet image"
group.word 0xBC++0x01
line.word 0x00 "MMCSD12_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device"
rgroup.byte 0xBC++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_7,This register is used to store received UHS-II RES Packet image"
group.byte 0xBE++0x02
line.byte 0x00 "MMCSD12_UHS2_DEVICE_SELECT,UHS-II Device Select Register"
bitfld.byte 0x00 7. "INT_MSG_ENA,INT MSG Enable (Optional) This bit enables receipt of INT MSG" "Disabled,Enabled"
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bitfld.byte 0x00 0.--3. "DEV_SEL,UHS-II Device Select Host Controller holds an INT MSG packet per device" "Unselected (Default),INT MSG of Device ID 1 is selected,INT MSG of Device ID 2 is selected,?,?,?,?,?,?,?,?,?,?,?,?,INT MSG of Device ID 15 is selected"
line.byte 0x01 "MMCSD12_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h"
line.byte 0x02 "MMCSD12_UHS2_RESPONSE_8,This register is used to store received UHS-II RES Packet image"
group.word 0xC0++0x03
line.word 0x00 "MMCSD12_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register"
bitfld.word 0x00 1. "HOST_SDTRAN_RESET,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs" "Not Affected,Reset SD-TRAN"
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bitfld.word 0x00 0. "HOST_FULL_RESET,Host Full Reset On issuing FULL_RESET CCMD Host Driver set this bit to 1h to reset Host Controller" "Not Affected,Reset Host Controller"
line.word 0x02 "MMCSD12_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register"
bitfld.word 0x02 4.--7. "DEADLOCK_TIMEOUT_CTR,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second)" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x 2,Reserved"
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bitfld.word 0x02 0.--3. "CMDRESP_TIMEOUT_CTR,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms)" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x 2,Reserved"
group.long 0xC4++0x03
line.long 0x00 "MMCSD12_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC_ERR,Vendor Specific Error Vendor may use this field for vendor specific error status" "Interrupt is not generated,Vendor Specific Error,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting of this bit means that deadlock timeout occurs" "Interrupt is not generated,Deadlock Error"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting of this bit means that RES Packet timeout occurs" "Interrupt is not generated,RES Packet Timeout Error"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode" "Interrupt is not generated,ADMA2/3 Error"
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bitfld.long 0x00 8. "EBSY,EBSY Error On receiving EBSY packet if the packet indicates an error this bit is set to 1h" "Interrupt is not generated,EBSY Error (Backend Error)"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting of this bit means that Unrecoverable Error is set in a packet from a device" "Interrupt is not generated,Device Unrecoverable Error"
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bitfld.long 0x00 5. "TID,TID Error Setting of this bit means that TID Error occurs" "Interrupt is not generated,TID Error"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting of this bit means that Framing Error occurs during a packet receiving" "Interrupt is not generated,Framing Error"
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bitfld.long 0x00 3. "CRC,CRC Error Setting of this bit means that CRC Error occurs during a packet receiving" "Interrupt is not generated,CRC Error"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Retry Expired Setting of this bit means that Retry Counter Expired Error occurs during data transfer" "Interrupt is not generated,Retry Expired Error"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "Interrupt is not generated,RES Packet Error"
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bitfld.long 0x00 0. "HEADER,Header Error Setting of this bit means that Header Error occurs in a received packet" "Interrupt is not generated,Header Error"
rgroup.byte 0xC4++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_9,This register is used to store received UHS-II RES Packet image"
group.byte 0xC8++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_16,UHS-II Command Packet image is set to this register"
group.long 0xC8++0x03
line.long 0x00 "MMCSD12_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in" "Status is Disabled,Status is Enabled,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 8. "EBSY,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 5. "TID,TID Error Setting this bit to 1h enables setting of TID Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting this bit to 1h enables setting of Framing Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 3. "CRC,CRC Error Setting this bit to 1h enables setting of CRC Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 0. "HEADER,Header Error Setting this bit to 1h enables setting of Header Error bit in" "Status is Disabled,Status is Enabled"
rgroup.byte 0xC8++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_10,This register is used to store received UHS-II RES Packet image"
group.byte 0xCC++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_17,UHS-II Command Packet image is set to this register"
group.long 0xCC++0x03
line.long 0x00 "MMCSD12_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 8. "EBSY,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 5. "TID,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 3. "CRC,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 2. "RETRY_EXPIRED_SIG_ENA,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 0. "HEADER,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
rgroup.byte 0xCC++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_11,This register is used to store received UHS-II RES Packet image"
group.byte 0xD0++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_18,UHS-II Command Packet image is set to this register"
rgroup.word 0xE0++0x09
line.word 0x00 "MMCSD12_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings"
line.word 0x02 "MMCSD12_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register"
line.word 0x04 "MMCSD12_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register"
line.word 0x06 "MMCSD12_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register"
line.word 0x08 "MMCSD12_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register"
group.long 0xF4++0x07
line.long 0x00 "MMCSD12_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter"
line.long 0x04 "MMCSD12_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK. CMD11 Power Down Timer. Enhanced Strobe and eMMC Hardware Reset"
bitfld.long 0x04 16. "AUTOGATE_SDCLK,Auto Gate SD CLK If this bit is set SD CLK will be gated automatically when there is no transfer" "Disable,Enable"
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hexmask.long.word 0x04 2.--15. 1. "CMD11_PD_TIMER,CMD11 Power Down Timer Value"
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bitfld.long 0x04 1. "EMMC_HW_RESET,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set" "De-sassert hardware reset pin,Drives the hardware reset pin as ZERO (Active.."
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bitfld.long 0x04 0. "ENHANCED_STROBE,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x03
line.word 0x00 "MMCSD12_SLOT_INT_STS,This register is used to read the interrupt signal for each slot"
hexmask.word.byte 0x00 0.--7. 1. "INTR_SIG,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot"
line.word 0x02 "MMCSD12_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number"
hexmask.word.byte 0x02 8.--15. 1. "VEN_VER_NUM,Vendor Version Number The Vendor Version Number is set to 10h (1.0)"
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abitfld.word 0x02 0.--7. "SPEC_VER_NUM,Specification Version Number This status indicates the Host Controller Specification Version" "0x00=SD Host Controller Specification Version 1.00,0x01=SD Host Controller Specification Version..,0x02=SD Host Controller Specification Version 3.00,0x03=SD Host Controller Specification Version 4.00,0x04=SD Host Controller Specification Version.."
group.long 0x100++0x07
line.long 0x00 "MMCSD12_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register"
bitfld.long 0x00 8.--13. "NUMLANES,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices" "2 Lanes FD or 2L-HD,Not Used,3 Lanes 2D1U-FD (Embedded),3 Lanes 1D2U-FD (Embedded),4 Lanes 2D2U-FD (Embedded) Others: Reserved,?..."
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bitfld.long 0x00 0. "POWER_MODE,Power Mode This field determines either Fast mode or Low Power mode" "Fast Mode,Low Power Mode"
line.long 0x04 "MMCSD12_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register"
bitfld.long 0x04 20.--23. "N_LSS_DIR,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field" "8 x 16 LSS,8 x 1 LSS,8 x 2 LSS,8 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,8 x 15 LSS"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS 3h - 4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 15. "HIBERNATE_ENA,Hibernate Enable After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set" "Hibernate Disabled,Hibernate Enabled"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,Speed Range PLL multiplier is selected by this field" "Range A (Defalt),Range B,Reserved,Reserved"
group.quad 0x108++0x07
line.quad 0x00 "MMCSD12_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register"
abitfld.quad 0x00 32.--39. "N_DATA_GAP,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field" "0x00=No Gap,0x01=1 LSS,0x02=2 LSS,0x03=3 LSS,0xFF=255 LSS"
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bitfld.quad 0x00 16.--17. "RETRY_COUNT,Retry Count Data Burst retry count is set to this field" "Retry Disabled,1 time,2 times,3 times"
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abitfld.quad 0x00 8.--15. "HOST_NFCU,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field" "0x00=256 Blocks,0x01=1 Block,0x02=2 Blocks,0x03=3 Blocks,0xFF=255 Blocks"
rgroup.long 0x110++0x07
line.long 0x00 "MMCSD12_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register"
bitfld.long 0x00 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,Bus Topology This field indicates one of bus topologies configured by a Host system" "P2P Connection,Ring Connection,HUB Connection,HUB is Connected in Ring"
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bitfld.long 0x00 18.--21. "CORECFG_UHS2_MAX_DEVICES,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller" "Not used,1 Devices,2 Devices,?,?,?,?,?,?,?,?,?,?,?,?,15 Devices"
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bitfld.long 0x00 16.--17. "DEVICE_TYPE,Removable/Embedded This field indicates device type configured by a Host system" "Removable Card (P2P),Embedded Devices,Embedded Devices + Removable Card,Reserved"
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bitfld.long 0x00 14. "CFG_64BIT_ADDRESSING,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller" "32-bit Addressing is supported,32-bit and 64-bit Addressing is supported"
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bitfld.long 0x00 8.--13. "NUM_LANES,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--7. "GAP,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system" "Not used,360 mW,720 mW,?,?,?,?,?,?,?,?,?,?,?,?,360 x 15 mW"
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bitfld.long 0x00 0.--3. "DAP,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system" "360 mW (Default),360 mW,720 mW,?,?,?,?,?,?,?,?,?,?,?,?,360 x 15 mW"
line.long 0x04 "MMCSD12_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register"
bitfld.long 0x04 20.--23. "N_LSS_DIR,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS,4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS,4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,Speed Range This field indicates supported Speed Range by the Host Controller" "Range A (Default),Range A and Range B,Reserved,Reserved"
rgroup.quad 0x118++0x07
line.quad 0x00 "MMCSD12_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register"
abitfld.quad 0x00 32.--39. "N_DATA_GAP,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller" "0x00=No Gap,0x01=1 LSS,0x02=2 LSS,0x03=3 LSS,0xFF=255 LSS"
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abitfld.quad 0x00 20.--31. "MAX_BLK_LENGTH,Host Maximum Block Length This field indicates maximum block length by the Host Controller" "0x000=Not Used,0x001=1 byte,0x002=2 bytes,0x200=512 bytes,0x800=2048 bytes,0x801=FFFh"
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abitfld.quad 0x00 8.--15. "N_FCU,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller" "0x00=256 Blocks,0x01=1 Block,0x02=2 Block,0x03=3 Block,0xFF=255 Blocks"
group.long 0x120++0x03
line.long 0x00 "MMCSD12_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.long 0x00 27.--31. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error" "Not Affected,Vendor Specific Error Status is set,?..."
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bitfld.long 0x00 17. "TIMEOUT_DEADLOCK,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in" "Not affected,Timeout for Deadlock Error status.."
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bitfld.long 0x00 16. "TIMEOUT_CMD_RES,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in" "Not affected,Timout for CMD_RES Status is set"
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bitfld.long 0x00 15. "ADMA,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in" "Not affected,ADMA Error Status is set"
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bitfld.long 0x00 8. "EBSY,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in" "Not affected,EBSY Error Status is set"
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bitfld.long 0x00 7. "UNRECOVERABLE,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in" "Not affected,Unrecoverable Error Status is set"
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bitfld.long 0x00 5. "TID,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in" "Not affected,TID Error Status is set"
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bitfld.long 0x00 4. "FRAMING,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in" "Not affected,Framing Error Status is set"
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bitfld.long 0x00 3. "CRC,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in" "Not affected,CRC Error Status is set"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in" "Not affected,Retry expired error status is set"
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bitfld.long 0x00 1. "RES_PKT,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in" "Not affected,RES packet error status is set"
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bitfld.long 0x00 0. "HEADER,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in" "Not affected,Header error status is set"
rgroup.long 0x200++0x3B
line.long 0x00 "MMCSD12_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE. in BCD format"
bitfld.long 0x00 8.--11. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number (digit left of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number (digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VERSION_SUFFIX,eMMC Version Suffix (2nd digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MMCSD12_CQ_CAPABILITIES,This register is reserved for capability indication"
bitfld.long 0x04 12.--15. "CF_MUL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period" "0.001 MHz,0.01 MHz,0.1 MHz,1 MHz,10 MHz Other values..,?..."
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hexmask.long.word 0x04 0.--9. 1. "CF_VAL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling"
line.long 0x08 "MMCSD12_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time"
bitfld.long 0x08 12. "DCMD_ENA,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor" "Task descriptor in slot #31 is a Data Transfer..,Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x08 8. "TASK_DESC_SIZE,This bit indicates whether the task descriptor size is 128 bits or 64 bits" "Task descriptor size is 64 bits,Task descriptor size is 128 bits"
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bitfld.long 0x08 0. "CQ_ENABLE,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE)" "0,1"
line.long 0x0C "MMCSD12_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time"
bitfld.long 0x0C 8. "CLEAR_ALL_TASKS,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device" "0,1"
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bitfld.long 0x0C 0. "HALT_BIT,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus" "0,1"
line.long 0x10 "MMCSD12_CQ_INTR_STS,This register indicates pending interrupts that require service"
bitfld.long 0x10 4. "TASK_ERROR,This bit is asserted when task error is detected due to invalid task descriptor" "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED,This status bit is asserted (if" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET,This status bit is asserted (if Software uses" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,This status bit is asserted (if (1) A task is completed and the INT bit is set in its Task Descriptor (2) Interrupt caused by Interrupt Coalescing logic" "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE,This status bit is asserted (if" "0,1"
line.long 0x14 "MMCSD12_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register"
bitfld.long 0x14 4. "TASK_ERROR," "0,1"
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bitfld.long 0x14 3. "TASK_CLEARED," "0,1"
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bitfld.long 0x14 2. "RESP_ERR_DET," "0,1"
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bitfld.long 0x14 1. "TASK_COMPLETE," "0,1"
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bitfld.long 0x14 0. "HALT_COMPLETE," "0,1"
line.long 0x18 "MMCSD12_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software"
bitfld.long 0x18 4. "TASK_ERROR,When set and" "0,1"
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bitfld.long 0x18 3. "TASK_CLEARED,When set and" "0,1"
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bitfld.long 0x18 2. "RESP_ERR_DET,When set and" "0,1"
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bitfld.long 0x18 1. "TASK_COMPLETE,When set and" "0,1"
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bitfld.long 0x18 0. "HALT_COMPLETE,When set and" "0,1"
line.long 0x1C "MMCSD12_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature"
bitfld.long 0x1C 31. "CQINTCOALESC_ENABLE,When set to 0h by software command responses are neither counted nor timed" "0,1"
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bitfld.long 0x1C 20. "IC_STATUS,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0)" "No task completions have occurred since last..,At least one task completion has been counted.."
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bitfld.long 0x1C 8.--12. "CTR_THRESHOLD,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x1C 0.--6. 1. "TIMEOUT_VAL,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt"
line.long 0x20 "MMCSD12_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory"
line.long 0x24 "MMCSD12_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory"
line.long 0x28 "MMCSD12_CQ_TASK_DOOR_BELL,Using this register. software triggers CQE to process a new task"
line.long 0x2C "MMCSD12_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks"
line.long 0x30 "MMCSD12_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status"
line.long 0x34 "MMCSD12_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device. awaiting execution"
line.long 0x38 "MMCSD12_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327"
group.long 0x240++0x0B
line.long 0x00 "MMCSD12_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent"
bitfld.long 0x00 16.--19. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling"
line.long 0x04 "MMCSD12_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument"
hexmask.long.word 0x04 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument"
line.long 0x08 "MMCSD12_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software"
rgroup.long 0x250++0x13
line.long 0x00 "MMCSD12_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt"
line.long 0x04 "MMCSD12_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity"
bitfld.long 0x04 31. "DATERR_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 24.--28. "DATERR_TASK_ID,This field indicates the ID of the task which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--21. "DATERR_CMD_INDEX,This field indicates the index of the command which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "RESP_MODE_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 8.--12. "RESP_MODE_TASK_ID,This field indicates the ID of the task which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "RESP_MODE_CMD_INDEX,This field indicates the index of the command which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MMCSD12_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response"
bitfld.long 0x08 0.--5. "LAST_CRI,This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MMCSD12_CQ_CMD_RESP_ARG,This register stores the index of the last received command response"
line.long 0x10 "MMCSD12_CQ_ERROR_TASK_ID,CQ Error Task ID Register"
bitfld.long 0x10 0.--4. "TERR_ID,Task Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 7. (list 12. 13. 14. 15. 16. 17. 18. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
rgroup.byte ($2+0xD0)++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_$1,This register is used to store received UHS-II RES Packet image"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.byte ($2+0x88)++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_$1,UHS-II Command Packet image is set to this register"
repeat.end
repeat 9. (list 1. 2. 3. 4. 5. 6. 7. 8. 10. )(list 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x10 0x12 )
rgroup.word ($2+0x62)++0x01
line.word 0x00 "MMCSD12_PRESET_VALUE$1,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value"
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes" "Driver Type D is Selected,Driver Type C is Selected,Driver Type A is Selected,Driver Type B is Selected"
bitfld.word 0x00 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "Host Controller Version 2.00 Compatible Clock..,Programmable Clock Generator"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set"
repeat.end
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
rgroup.word ($2+0x10)++0x01
line.word 0x00 "MMCSD12_RESPONSE_$1,This registers is used to store responses from SD Cards"
repeat.end
tree.end
tree "MMCSD2_CTL_CFG"
base ad:0x4F98000
group.word 0x00++0x0F
line.word 0x00 "MMCSD12_SDMA_SYS_ADDR_LO,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10"
line.word 0x02 "MMCSD12_SDMA_SYS_ADDR_HI,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10"
line.word 0x04 "MMCSD12_BLOCK_SIZE,This register is used to configure the number of bytes in a data block"
bitfld.word 0x04 12.--14. "SDMA_BUF_SIZE,Host SDMA Buffer Size To perform long DMA transfer System Address register ( These bits shall support when the 0h: 4KB (Detects A11 Carry out) 1h: 8KB (Detects A12 Carry out) 2h: 16KB (Detects A13 Carry out) 3h: 32KB (Detects A14 Carry.." "4KB (Detects A11 Carry out),8KB (Detects A12 Carry out),16KB (Detects A13 Carry out),32KB (Detects A14 Carry out),64KB (Detects A15 Carry out),128KB (Detects A16 Carry out),256KB (Detects A17 Carry out),512KB (Detects A18 Carry out)"
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abitfld.word 0x04 0.--11. "XFER_BLK_SIZE,Transfer Block Size This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53" "0x000=No Data Transfer,0x001=1 Byte,0x002=2 Bytes,0x003=3 Bytes,0x004=4 Bytes,0x1FF=511 Bytes,0x200=512 Bytes,0x800=2048 Bytes"
line.word 0x06 "MMCSD12_BLOCK_COUNT,This register is used to configure the number of data blocks"
line.word 0x08 "MMCSD12_ARGUMENT1_LO,This register contains Lower bits of SD Command Argument"
line.word 0x0A "MMCSD12_ARGUMENT1_HI,This register contains higher bits of SD Command Argument"
line.word 0x0C "MMCSD12_TRANSFER_MODE,"
bitfld.word 0x0C 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Interrupt is enabled,Response Interrupt is disabled"
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bitfld.word 0x0C 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Error Check is disabled,Response Error Check is enabled"
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bitfld.word 0x0C 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled ( Error Statuses Checked in R1: Response Flags Checked in R5: 0h: R1 (Memory) 1h: R5 (SDIO)" "R1 (Memory),R5 (SDIO)"
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bitfld.word 0x0C 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit enables multiple block data transfers" "Single Block,Multiple Block"
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bitfld.word 0x0C 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of data transfers" "Write (Host to Card),Read (Card to Host)"
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bitfld.word 0x0C 2.--3. "AUTO_CMD_ENA,Auto CMD Enable This field determines use of auto command functions" "Auto Command Disabled,Auto CMD12 Enable,Auto CMD23 Enable,Reserved"
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bitfld.word 0x0C 1. "BLK_CNT_ENA,Block Count Enable This bit is used to enable" "Disable,Enable"
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bitfld.word 0x0C 0. "DMA_ENA,DMA Enable DMA can be enabled only if" "Disable,Enable"
line.word 0x0E "MMCSD12_COMMAND,This register is used to program the Command for host controller"
bitfld.word 0x0E 8.--13. "CMD_INDEX,Command Index This bit shall be set to the command number (CMD0-63 ACMD0-63)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x0E 6.--7. "CMD_TYPE,Command Type There are three types of special commands" "Normal,Suspend,Resume,Abort"
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bitfld.word 0x0E 5. "DATA_PRESENT,Data Present Select This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line" "No Data Present,Data Present"
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bitfld.word 0x0E 4. "CMD_INDEX_CHK_ENA,Command Index Check Enable If this bit is set to 1h the HC shall check the index field in the response to see if it has the same value as the command index" "Disable,Enable"
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bitfld.word 0x0E 3. "CMD_CRC_CHK_ENA,Command CRC Check Enable If this bit is set to 1h the HC shall check the CRC field in the response" "Disable,Enable"
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bitfld.word 0x0E 2. "SUB_CMD,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command" "Sub Command,Main Command"
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bitfld.word 0x0E 0.--1. "RESP_TYPE_SEL,Response Type Select" "No Response,Response length 136,Response length 48,Response length 48 check Busy after response"
group.long 0x20++0x07
line.long 0x00 "MMCSD12_DATA_PORT,This register is used to access internal buffer"
line.long 0x04 "MMCSD12_PRESENTSTATE,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x04 31. "UHS2_IF_DETECTION,UHS-II IF Detection (UHS-II Only) This status indicates whether a card supports UHS-II IF" "UHS-II IF is not detected,UHS-II IF is detected"
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bitfld.long 0x04 30. "UHS2_IF_LANE_SYNC,Lane Synchronization (UHS-II Only) This status indicates whether lane is synchronized in UHS-II mode" "UHS-II PHY is not initialized,UHS-II PHY is initialized"
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bitfld.long 0x04 29. "UHS2_DORMANT,In Dormant State (UHS-II Only) This status indicates whether UHS-II lanes enter Dormant state" "Not in DORMANT state,In DORMANT state"
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bitfld.long 0x04 28. "SUB_COMMAND_STS,Sub Command Status" "Main Command Status,Sub Command Status"
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bitfld.long 0x04 27. "CMD_NOT_ISS_BY_ERR,Command Not Issued by Error Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in.." "No error for issuing a command,Command cannot be issued"
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bitfld.long 0x04 24. "SDIF_CMDIN,CMD Line Signal Level (SD Mode Only) This status is used to check CMD line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 23. "SDIF_DAT3IN,DAT[3] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 22. "SDIF_DAT2IN,DAT[2] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 21. "SDIF_DAT1IN,DAT[1] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 20. "SDIF_DAT0IN,DAT[0] Line Signal Level (SD Mode Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 19. "WRITE_PROTECT,Write Protect Switch Pin Level The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin" "Write protected (SDWP# = 1),Write enabled (SDWP# = 0)"
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bitfld.long 0x04 18. "CARD_DETECT,Card Detect Pin Level This bit reflects the inverse value of the SDCD# pin" "No Card present (SDCD# = 1),Card present (SDCD# = 0)"
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bitfld.long 0x04 17. "CARD_STATE_STABLE,Card State Stable This bit is used for testing" "Reset of Debouncing,No Card or Inserted"
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bitfld.long 0x04 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted" "Reset or Debouncing or No Card,Card Inserted"
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bitfld.long 0x04 11. "BUF_RD_ENA,Buffer Read Enable This status is used for non-DMA read transfers" "Read Disable,Read Enable"
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bitfld.long 0x04 10. "BUF_WR_ENA,Buffer Write Enable This status is used for non-DMA write transfers" "Write Disable,Write Enable"
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bitfld.long 0x04 9. "RD_XFER_ACTIVE,Read Transfer Active (SD Mode Only) This status is used for detecting completion of a read transfer" "No valid data,Transferring data"
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bitfld.long 0x04 8. "WR_XFER_ACTIVE,Write Transfer Active (SD Mode Only) This status indicates a write transfer is active" "No valid data,Transferring data"
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bitfld.long 0x04 7. "SDIF_DAT7IN,DAT[7] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 6. "SDIF_DAT6IN,DAT[6] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 5. "SDIF_DAT5IN,DAT[5] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 4. "SDIF_DAT4IN,DAT[4] Line Signal Level (Embedded Only) This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 3. "RETUNING_REQ,Re-Tuning Request (UHS-I Only) Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive.." "Fixed or well tuned sampling clock,Sampling clock needs re-tuning"
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bitfld.long 0x04 2. "DATA_LINE_ACTIVE,DAT Line Active (SD Mode Only) This bit indicates whether one of the DAT line on SD bus is in use" "DAT line inactive,DAT line active"
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bitfld.long 0x04 1. "INHIBIT_DAT,Command Inhibit (DAT) (SD Mode Only) This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h" "Can issue command which uses the DAT line,Cannot issue command which uses the DAT line"
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bitfld.long 0x04 0. "INHIBIT_CMD,Command Inhibit (CMD)" "Host Controller is ready to issue a command..,Host Controller is not ready to issue a command"
group.byte 0x28++0x03
line.byte 0x00 "MMCSD12_HOST_CONTROL1,This register is used to program DMA modes. LED control. data transfer width. High Speed enable. card detect test level and signal selection"
bitfld.byte 0x00 7. "CD_SIG_SEL,Card Detect Signal Detection This bit selects source for card detection" "SDCD# is selected (for normal use),The card detect test level is selected"
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bitfld.byte 0x00 6. "CD_TEST_LEVEL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not" "No Card,Card Inserted"
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bitfld.byte 0x00 5. "EXT_DATA_WIDTH,Extended Data Transfer Width (Embedded and SD Mode Only) This bit controls 8-bit bus width mode for embedded device" "Bus Width is Selected by Data Transfer Width,8-bit Bus Width"
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bitfld.byte 0x00 3.--4. "DMA_SELECT,DMA Select This field is used to select DMA type" "0,1,2,3"
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bitfld.byte 0x00 2. "HIGH_SPEED_ENA,High Speed Enable (SD Mode Only) This bit is optional" "Normal Speed Mode,High Speed Mode"
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bitfld.byte 0x00 1. "DATA_WIDTH,Data Transfer Width (SD Mode Only) This bit selects the data width of the HC" "1 bit mode,4 bit mode"
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bitfld.byte 0x00 0. "LED_CONTROL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed" "LED off,LED on"
line.byte 0x01 "MMCSD12_POWER_CONTROL,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x01 5.--7. "UHS2_VOLTAGE,SD Bus Voltage Select for VDD2 (UHS-II Only) This field determines supply voltage range to VDD2" "VDD2 Not Supported,Reserved,?,?,Reserved for 1.2 V,1.8 V,Not used,Not used"
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bitfld.byte 0x01 4. "UHS2_POWER,SD Bus Power for VDD2 (UHS-II Only) Setting this bit enables providing VDD2" "Power off,Power on"
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bitfld.byte 0x01 1.--3. "SD_BUS_VOLTAGE,SD Bus Voltage Select for VDD1 By setting these bits the HD selects the voltage level for the SD card" "Reserved,?,?,?,?,1.8 V (Typ.) for Embedded,3.0 V (Typ.),3.3 V (Flattop.)"
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bitfld.byte 0x01 0. "SD_BUS_POWER,SD Bus Power for VDD1 Before setting this bit the SD host driver shall set SD Bus Voltage Select ( If this bit is cleared the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state) and drive SDCLK to low level. If card.." "Power off,Power on"
line.byte 0x02 "MMCSD12_BLOCK_GAP_CONTROL,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x02 7. "BOOT_ACK_ENA,Boot Acknowledge Check To check for the boot acknowledge in boot operation" "Will not wait for boot ack from eMMC card,Wait for boot ack from eMMC card"
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bitfld.byte 0x02 6. "ALT_BOOT_MODE,Alternative Boot Mode To start boot code access in alternative mode" "To stop alternate boot mode access,To start alternate boot mode access"
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bitfld.byte 0x02 5. "BOOT_ENABLE,Boot Enable To start boot code access" "To stop boot code access,To start boot code access"
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bitfld.byte 0x02 3. "INTRPT_AT_BLK_GAP,Interrupt At Block Gap (SD Mode Only) This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle" "0,1"
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bitfld.byte 0x02 2. "RDWAIT_CTRL,Read Wait Control (SD Mode Only) The read wait function is optional for SDIO cards" "Disable Read Wait Control,Enable Read Wait Control"
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bitfld.byte 0x02 1. "CONTINUE,Continue Request This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request" "Ignored,Restart"
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bitfld.byte 0x02 0. "STOP_AT_BLK_GAP,Stop At Block Gap Request This bit is used to stop executing a transaction at the next block gap for non-DMA SDMA and ADMA transfers" "Transfer,Stop"
line.byte 0x03 "MMCSD12_WAKEUP_CONTROL,This register is used to program the wakeup functionality"
bitfld.byte 0x03 2. "CARD_REMOVAL,Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card removal assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit" "Disable,Enable"
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bitfld.byte 0x03 1. "CARD_INSERTION,Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the FN_WUS (Wake up Support) in CIS does not affect this bit" "Disable,Enable"
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bitfld.byte 0x03 0. "CARD_INTERRUPT,Wakeup Event Enable On Card Interrupt This bit enables wakeup event via Card Interrupt assertion in the This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h" "Disable,Enable"
group.word 0x2C++0x01
line.word 0x00 "MMCSD12_CLOCK_CONTROL,This register is used to program the Clock frequency select. Clock generator select. Clock enable. Internal clock state fields"
hexmask.word.byte 0x00 8.--15. 1. "SDCLK_FRQSEL,SDCLK/RCLK Frequency Select This register is used to select the frequency of the SDCLK pin"
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bitfld.word 0x00 6.--7. "SDCLK_FRQSEL_UPBITS,Upper Bits of SDCLK/RCLK Frequency Select This bit field is assigned to" "0,1,2,3"
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bitfld.word 0x00 5. "CLKGEN_SEL,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select ( If the Programmable Clock Mode is supported (non-zero value is set to the This bit depends on the setting of the If If 1h:.." "Divided Clock Mode,Programmable Clock Mode"
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bitfld.word 0x00 3. "PLL_ENA,PLL Enable This bit is added from Version 4.10 for Host Controller using PLL" "PLL is in low power mode,PLL is enabled"
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bitfld.word 0x00 2. "SD_CLK_ENA,SD Clock Enable The HC shall stop SDCLK when writing this bit to 0h" "Disable providing SDCLK or RCLK,Enable providing SDCLK or RCLK"
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bitfld.word 0x00 1. "INT_CLK_STABLE,Internal Clock Stable This bit is set to 1h when SD clock is stable after writing 1h to (1) Internal Clock Stable (when This bit is set to 1h when internal clock is stable after writing 1h to (2) PLL Clock Stable (when Host Controller.." "Not Ready,Ready"
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bitfld.word 0x00 0. "INT_CLK_ENA,Internal Clock Enable This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event" "Stop,Oscillate"
group.byte 0x2E++0x01
line.byte 0x00 "MMCSD12_TIMEOUT_CONTROL,The register sets the data timeout counter value"
bitfld.byte 0x00 0.--3. "COUNTER_VALUE,Data Timeout Counter Value This value determines the interval by which DAT line time-outs are detected" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x,Reserved"
line.byte 0x01 "MMCSD12_SOFTWARE_RESET,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x01 2. "SWRST_FOR_DAT,Software Reset for DAT Line (SD Mode Only) Only part of data circuit is reset" "Work,Reset"
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bitfld.byte 0x01 1. "SWRST_FOR_CMD,Software Reset for CMD Line (SD Mode Only) Only part of command circuit is reset to be able to issue a command" "Work,Reset"
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bitfld.byte 0x01 0. "SWRST_FOR_ALL,Software Reset for All This reset affects the entire HC except for the card detection circuit" "Work,Reset"
group.word 0x30++0x0F
line.word 0x00 "MMCSD12_NORMAL_INTR_STS,This register gives the status of all the interrupts"
bitfld.word 0x00 15. "ERROR_INTR,Error Interrupt If any of the bits in the In UHS-II mode is enabled if any of the bits in" "No Error,Error"
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bitfld.word 0x00 14. "BOOT_COMPLETE,Boot Terminate Interrupt This status is set if the boot operation gets terminated" "Boot operation is not terminated,Boot operation is terminated"
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bitfld.word 0x00 13. "RCV_BOOT_ACK,Boot Acknowledge Receive This status is set if the boot acknowledge is received from device" "Boot acknowledge is not received,Boot acknowledge is received"
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bitfld.word 0x00 12. "RETUNING_EVENT,Re-Tuning Event (UHS-I Only) This status is set if the Host Controller requests Host Driver to perform re-tuning for next data transfer" "Re-Tuning is not required,Re-Tuning should be performed"
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rbitfld.word 0x00 11. "INTC,int_c (Embedded) This status is set if INT_C is enabled and INT_C# pin is in low level" "0,1"
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rbitfld.word 0x00 10. "INTB,int_b (Embedded) This status is set if INT_B is enabled and INT_B# pin is in low level" "0,1"
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rbitfld.word 0x00 9. "INTA,int_a (Embedded) This status is set if INT_A is enabled and INT_A# pin is in low level" "0,1"
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bitfld.word 0x00 8. "CARD_INTR,Card Interrupt When this status has been set and the Host Driver needs to start this interrupt service the Writing this bit to 1h does not clear this bit" "No Card Interrupt,Generate Card Interrupt"
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bitfld.word 0x00 7. "CARD_REM,Card Removal This status is set if" "Card State Stable or Debouncing,Card Removed"
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bitfld.word 0x00 6. "CARD_INS,Card Insertion This status is set if" "Card State Stable or Debouncing,Card Inserted"
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bitfld.word 0x00 5. "BUF_RD_READY,Buffer Read Ready This status is set if the The In UHS-II mode this bit is set at FC (Flow Control) unit basis" "Not Ready to read Buffer,Ready to read Buffer"
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bitfld.word 0x00 4. "BUF_WR_READY,Buffer Write Ready This status is set if the In UHS-II mode this bit is set at FC (Flow Control) unit basis" "Not Ready to Write Buffer,Ready to Write Buffer"
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bitfld.word 0x00 3. "DMA_INTERRUPT,DMA Interrupt This status is set if the HC detects the Host DMA Buffer Boundary in" "No DMA Interrupt,DMA Interrupt is Generated"
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bitfld.word 0x00 2. "BLK_GAP_EVENT,Block Gap Event If the Read Transaction: This bit is set at the falling edge of the DAT Line Active Status (see Write Transaction: This bit is set at the falling edge of Write Transfer Active Status (see 0h: No Block Gap Event 1h:.." "No Block Gap Event,Transaction stopped at Block Gap"
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bitfld.word 0x00 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transaction is completed" "Not complete,Command execution is completed"
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bitfld.word 0x00 0. "CMD_COMPLETE,Command Complete This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23)" "No Command Complete,Command Complete"
line.word 0x02 "MMCSD12_ERROR_INTR_STS,This register gives the status of the error interrupts"
bitfld.word 0x02 12. "HOST,Target Response Error Occurs when detecting ERROR in m_hresp (DMA transaction)" "No error,Error"
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bitfld.word 0x02 11. "RESP,Response Error (SD Mode Only) Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "No error,Error"
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bitfld.word 0x02 9. "ADMA,ADMA Error This bit is set when the Host Controller detects errors during ADMA based data transfer" "No error,Error"
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bitfld.word 0x02 8. "AUTO_CMD,Auto CMD Error (SD Mode Only) Auto CMD12 and Auto CMD23 use this error status" "No error,Error"
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bitfld.word 0x02 7. "CURR_LIMIT,Current Limit Error By setting" "No error,Power Fail"
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bitfld.word 0x02 6. "DATA_ENDBIT,Data End Bit Error (SD Mode Only) Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status" "No error,Error"
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bitfld.word 0x02 5. "DATA_CRC,Data CRC Error (SD Mode Only) Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h" "No error,Error"
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bitfld.word 0x02 4. "DATA_TIMEOUT,Data Timeout Error (SD Mode Only) Occurs when detecting one of following timeout conditions" "No error,Timeout"
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bitfld.word 0x02 3. "CMD_INDEX,Command Index Error (SD Mode Only) Occurs if a Command Index error occurs in the Command Response ( 0h: No error 1h: Error" "No error,Error"
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bitfld.word 0x02 2. "CMD_ENDBIT,Command End Bit Error (SD Mode Only) Occurs when detecting that the end bit of a command response is 0h" "No error,End Bit Error Generated"
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bitfld.word 0x02 1. "CMD_CRC,Command CRC Error (SD Mode Only) Command CRC Error is generated in two cases" "No error,CRC Error Generated"
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bitfld.word 0x02 0. "CMD_TIMEOUT,Command Timeout Error (SD Mode Only) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command" "No error,Timeout"
line.word 0x04 "MMCSD12_NORMAL_INTR_STS_ENA,This register is used to enable the register fields"
rbitfld.word 0x04 15. "BIT15_FIXED0,Fixed to 0 The HC shall control error Interrupts using" "0,1"
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bitfld.word 0x04 14. "BOOT_COMPLETE,Boot Terminate Interrupt Enable" "Masked,Enabled"
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bitfld.word 0x04 13. "RCV_BOOT_ACK,Boot Acknowledge Enable" "Masked,Enabled"
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bitfld.word 0x04 12. "RETUNING_EVENT,Re-Tuning Event Status Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x04 11. "INTC,INT_C Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 10. "INTB,INT_B Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 9. "INTA,INT_A Status Enable (Embedded) If this bit is set to 0h the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 8. "CARD_INTERRUPT,Card Interrupt Status Enable If this bit is set to 0h the HC shall clear Interrupt request to the System" "Masked,Enabled"
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bitfld.word 0x04 7. "CARD_REMOVAL,Card Removal Status Enable" "Masked,Enabled"
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bitfld.word 0x04 6. "CARD_INSERTION,Card Insertion Status Enable" "Masked,Enabled"
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bitfld.word 0x04 5. "BUF_RD_READY,Buffer Read Ready Status Enable" "Masked,Enabled"
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bitfld.word 0x04 4. "BUF_WR_READY,Buffer Write Ready Status Enable" "Masked,Enabled"
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bitfld.word 0x04 3. "DMA_INTERRUPT,DMA Interrupt Status Enable" "Masked,Enabled"
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bitfld.word 0x04 2. "BLK_GAP_EVENT,Block Gap Event Status Enable" "Masked,Enabled"
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bitfld.word 0x04 1. "XFER_COMPLETE,Transfer Complete Status Enable" "Masked,Enabled"
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bitfld.word 0x04 0. "CMD_COMPLETE,Command Complete Status Enable" "Masked,Enabled"
line.word 0x06 "MMCSD12_ERROR_INTR_STS_ENA,This register is used to enable the register fields"
bitfld.word 0x06 12.--15. "VENDOR_SPECIFIC,Vendor Specific Error Status Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x06 11. "RESP,Response Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 10. "TUNING,Tuning Error Status Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x06 9. "ADMA,ADMA Error Status Enable" "Masked,Enabled"
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bitfld.word 0x06 8. "AUTO_CMD,Auto CMD Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 7. "CURR_LIMIT,Current Limit Error Status Enable" "Masked,Enabled"
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bitfld.word 0x06 6. "DATA_ENDBIT,Data End Bit Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 5. "DATA_CRC,Data CRC Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 4. "DATA_TIMEOUT,Data Timeout Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 3. "CMD_INDEX,Command Index Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 2. "CMD_ENDBIT,Command End Bit Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 1. "CMD_CRC,Command CRC Error Status Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x06 0. "CMD_TIMEOUT,Command Timeout Error Status Enable (SD Mode Only)" "Masked,Enabled"
line.word 0x08 "MMCSD12_NORMAL_INTR_SIG_ENA,Normal Interrupt Signal Enable Register This register is used to select which interrupt status is indicated to the Host System as the Interrupt"
rbitfld.word 0x08 15. "BIT15_FIXED0,Fixed to 0 The HD shall control error Interrupts using" "0,1"
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bitfld.word 0x08 14. "BOOT_COMPLETE,Boot Terminate Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 13. "RCV_BOOT_ACK,Boot Acknowledge Receive Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 12. "RETUNING_EVENT,Re-Tuning Event Signal Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x08 11. "INTC,INT_C Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 10. "INTB,INT_B Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 9. "INTA,INT_A Signal Enable (Embedded)" "Masked,Enabled"
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bitfld.word 0x08 8. "CARD_INTERRUPT,Card Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 7. "CARD_REMOVAL,Card Removal Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 6. "CARD_INSERTION,Card Insertion Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 5. "BUF_RD_READY,Buffer Read Ready Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 4. "BUF_WR_READY,Buffer Write Ready Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 3. "DMA_INTERRUPT,DMA Interrupt Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 2. "BLK_GAP_EVENT,Block Gap Event Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 1. "XFER_COMPLETE,Transfer Complete Signal Enable" "Masked,Enabled"
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bitfld.word 0x08 0. "CMD_COMPLETE,Command Complete Signal Enable" "Masked,Enabled"
line.word 0x0A "MMCSD12_ERROR_INTR_SIG_ENA,Error Interrupt Signal Enable Register This register is used to select which interrupt status is notified to the Host System as the Interrupt"
bitfld.word 0x0A 12.--15. "VENDOR_SPECIFIC,Vendor Specific Error Signal Enable N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x0A 11. "RESP,Response Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 10. "TUNING,Tuning Error Signal Enable (UHS-I Only)" "Masked,Enabled"
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bitfld.word 0x0A 9. "ADMA,ADMA Error Signal Enable" "Masked,Enabled"
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bitfld.word 0x0A 8. "AUTO_CMD,Auto CMD Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 7. "CURR_LIMIT,Current Limit Error Signal Enable" "Masked,Enabled"
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bitfld.word 0x0A 6. "DATA_ENDBIT,Data End Bit Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 5. "DATA_CRC,Data CRC Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 4. "DATA_TIMEOUT,Data Timeout Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 3. "CMD_INDEX,Command Index Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 2. "CMD_ENDBIT,Command End Bit Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 1. "CMD_CRC,Command CRC Error Signal Enable (SD Mode Only)" "Masked,Enabled"
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bitfld.word 0x0A 0. "CMD_TIMEOUT,Command Timeout Error Signal Enable (SD Mode Only)" "Masked,Enabled"
line.word 0x0C "MMCSD12_AUTOCMD_ERR_STS,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23"
bitfld.word 0x0C 7. "CMD_NOT_ISSUED,Command Not Issued By Auto CMD12 Error Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register" "No Error,Not Issued"
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bitfld.word 0x0C 4. "INDEX,Auto CMD Index Error Occurs if the Command Index error occurs in response to a command" "No Error,Error"
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bitfld.word 0x0C 3. "ENDBIT,Auto CMD End Bit Error Occurs when detecting that the end bit of command response is 0h" "No Error,End Bit Error Generated"
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bitfld.word 0x0C 2. "CRC,Auto CMD CRC Error Occurs when detecting a CRC error in the command response" "No Error,CRC Error Generated"
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bitfld.word 0x0C 1. "TIMEOUT,Auto CMD Timeout Error Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command" "No Error,Timeout"
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bitfld.word 0x0C 0. "ACMD12_NOT_EXEC,Auto CMD12 not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "Executed,Not Executed"
line.word 0x0E "MMCSD12_HOST_CONTROL2,This register is used to program UHS Mode Select. Driver Strength Select. Execute Tuning. Sampling Clock Select. Asynchronous Interrupt Enable and Preset Value Enable"
bitfld.word 0x0E 15. "PRESET_VALUE_ENA,Preset Value Enable Host Controller Version 3.00 supports this bit" "SDCLK and Driver Strength are controlled by Host..,Automatic Selection by Preset Value are Enabled"
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bitfld.word 0x0E 14. "ASYNCH_INTR_ENA,Asynchronous Interrupt Enable This bit can be set to 1h if a card support asynchronous interrupt and" "Disabled,Enabled"
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bitfld.word 0x0E 13. "BIT64_ADDRESSING,64-bit Addressing This field is effective when the Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory" "32-bits Addressing,64-bits Addressing"
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bitfld.word 0x0E 12. "HOST_VER40_ENA,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4.00 mode" "Version 3.00 Compatible Mode,Version 4.Mode"
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bitfld.word 0x0E 11. "CMD23_ENA,CMD23 Enable In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]" "0,1"
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bitfld.word 0x0E 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit" "16-bit Data Length Mode,26-bit Data Length Mode"
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bitfld.word 0x0E 9. "DRIVER_STRENGTH2,Driver Strength Select This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value" "0,1"
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bitfld.word 0x0E 8. "UHS2_INTF_ENABLE,UHS-II Interface Enable This bit is used to enable UHS-II Interface" "4-bit SD Interface Enabled,UHS-II Interface Enabled"
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bitfld.word 0x0E 7. "SAMPLING_CLK_SELECT,Sampling Clock Select (UHS-I Only) This bit is set by tuning procedure when" "Fixed clock is used to sample data,Tuned clock is used to sample data"
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bitfld.word 0x0E 6. "EXECUTE_TUNING,Execute Tuning (UHS-I Only) This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed" "Not Tuned or Tuning Completed,Execute Tuning"
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bitfld.word 0x0E 4.--5. "DRIVER_STRENGTH1,Driver Strength Select (UHS-I Only) Host Controller output driver in 1.8 V signaling is selected by this bit" "Driver Type B is Selected (Default),Driver Type A is Selected,Driver Type C is Selected,Driver Type D is Selected"
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bitfld.word 0x0E 3. "V1P8_SIGNAL_ENA,1.8 V Signaling Enable (UHS-I Only) This bit controls voltage regulator for I/O cell" "3.3 V Signaling,1.8 V Signaling"
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bitfld.word 0x0E 0.--2. "UHS_MODE_SELECT,UHS Mode Select (UHS-I Only) This field is used to select one of UHS-I modes or UHS-II mode" "SDR12,SDR25,SDR50,SDR104,DDR50,HS400,Reserved,UHS-II When.."
rgroup.quad 0x40++0x0F
line.quad 0x00 "MMCSD12_CAPABILITIES,This register provides the HD with information specific to the HC implementation"
bitfld.quad 0x00 63. "HS400_SUPPORT,HS400 Support" "HS400 is Not Supported,HS400 is Supported"
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bitfld.quad 0x00 60. "VDD2_1P8_SUPPORT,1.8 V VDD2 Support This bit indicates that support of VDD2 on Host system" "1.8 V VDD2 is not supported,1.8 V VDD2 is supported"
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bitfld.quad 0x00 59. "ADMA3_SUPPORT,ADMA3 Support This bit indicates that support of ADMA3 on Host Controller" "ADMA3 is not supported,ADMA3 is supported"
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bitfld.quad 0x00 57. "SPI_BLK_MODE,SPI Block Mode This bit indicates whether SPI Block Mode is supported or not" "Not Supported,Supported"
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bitfld.quad 0x00 56. "SPI_SUPPORT,SPI Mode This bit indicates whether SPI Mode is supported or not" "Not Supported,Supported"
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abitfld.quad 0x00 48.--55. "CLOCK_MULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" "0x00=Clock Multiplier is Not Supported,0x01=Clock Multiplier M = 2,0x02=Clock Multiplier M = 3,0xFF=Clock Multiplier M ="
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bitfld.quad 0x00 46.--47. "RETUNING_MODES,Re-tuning Modes (UHS-I Only) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver" "Mode 1,Mode 2,Mode 3,Reserved There.."
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bitfld.quad 0x00 45. "TUNING_FOR_SDR50,Use Tuning for SDR50 (UHS-I Only) If this bit is set to 1h this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104)" "SDR50 does not require tuning,SDR50 requires tuning"
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bitfld.quad 0x00 40.--43. "RETUNING_TIMER_CNT,Timer Count for Re-Tuning (UHS-I Only) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "Get information via other source,1 seconds,2 seconds,4 seconds,8 seconds ---- n =,?,?,?,?,?,?,1024 seconds,?,?,?,Ch = Reserved"
newline
bitfld.quad 0x00 38. "DRIVERD_SUPPORT,Driver Type D Support (UHS-I Only) This bit indicates support of Driver Type D for 1.8 Signaling" "Driver Type D is Not Supported,Driver Type D is Supported"
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bitfld.quad 0x00 37. "DRIVERC_SUPPORT,Driver Type C Support (UHS-I Only) This bit indicates support of Driver Type C for 1.8 Signaling" "Driver Type C is Not Supported,Driver Type C is Supported"
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bitfld.quad 0x00 36. "DRIVERA_SUPPORT,Driver Type A Support (UHS-I Only) This bit indicates support of Driver Type A for 1.8 Signaling" "Driver Type A is Not Supported,Driver Type A is Supported"
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bitfld.quad 0x00 35. "UHS2_SUPPORT,UHS-II Support (UHS-II Only) This bit indicates whether Host Controller supports UHS-II" "UHS-II is Not Supported,UHS-II is Supported"
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bitfld.quad 0x00 34. "DDR50_SUPPORT,DDR50 Support (UHS-I Only) This bit indicates whether DDR50 is supported or not" "DDR50 is Not Supported,DDR50 is Supported"
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bitfld.quad 0x00 33. "SDR104_SUPPORT,SDR104 Support (UHS-I Only) This bit indicates whether SDR104 is supported or not" "SDR104 is Not Supported,SDR104 is Supported"
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bitfld.quad 0x00 32. "SDR50_SUPPORT,SDR50 Support (UHS-I Only) If SDR104 is supported this bit shall be set to 1h" "SDR50 is Not Supported,SDR50 is Supported"
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bitfld.quad 0x00 30.--31. "SLOT_TYPE,Slot Type This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot)" "Removable Card Slot,Embedded Slot for One Device,Shared Bus Slot (SD Mode),UHS-II Multiple Embedded Devices"
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bitfld.quad 0x00 29. "ASYNCH_INTR_SUPPORT,Asynchronous Interrupt Support (SD Mode Only) Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "Asynchronous Interrupt Not Supported,Asynchronous Interrupt Supported"
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bitfld.quad 0x00 28. "ADDR_64BIT_SUPPORT_V3,64-bit System Address Support for V3 Meaning of this bit is different depends on Versions" "64-bit System Address for V3 is not Supported,64-bit System Address for V3 is Supported"
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bitfld.quad 0x00 27. "ADDR_64BIT_SUPPORT_V4,64-bit System Address Support for V4 This bit is added from Version 4.10" "64-bit System Address for V4 is not Supported,64-bit System Address for V4 is Supported"
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bitfld.quad 0x00 26. "VOLT_1P8_SUPPORT,Voltage Support 1.8 V This bit indicates whether the HC supports 1.8 V" "1.8 V Not Supported,1.8 V Supported"
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bitfld.quad 0x00 25. "VOLT_3P0_SUPPORT,Voltage Support 3.0 V This bit indicates whether the HC supports 3.0 V" "3.0 V Not Supported,3.0 V Supported"
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bitfld.quad 0x00 24. "VOLT_3P3_SUPPORT,Voltage Support 3.3 V This bit indicates whether the HC supports 3.3 V" "3.3 V Not Supported,3.3 V Supported"
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bitfld.quad 0x00 23. "SUSP_RES_SUPPORT,Suspend/Resume Support This bit indicates whether the HC supports Suspend/Resume functionality" "Not Supported,Supported"
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bitfld.quad 0x00 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly" "SDMA Not Supported,SDMA Supported"
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bitfld.quad 0x00 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC)" "High Speed Not Supported,High Speed Supported"
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bitfld.quad 0x00 19. "ADMA2_SUPPORT,ADMA2 Support" "ADMA2 Not support,ADMA2 support"
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bitfld.quad 0x00 18. "BUS_8BIT_SUPPORT,8-bit Support for Embedded Device (Embedded) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode" "8-bit Bus Width Not Supported,8-bit Bus Width Supported"
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bitfld.quad 0x00 16.--17. "MAX_BLK_LENGTH,Max Block Length This value indicates the maximum block size that the HD can read and write to the buffer in the HC" "512 byte,1024 byte,2048 byte,4096 byte"
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abitfld.quad 0x00 8.--15. "BASE_CLK_FREQ,Base Clock Frequency for SD Clock (1) 6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00" "0x00=Get Information via..,0x01=1 MHz,0x02=2 MHz,0x0F=63 MHz 0000,0xFF=255 MHz"
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bitfld.quad 0x00 7. "TIMEOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data Timeout Error ( 0h: KHz 1h: MHz" "KHz,MHz"
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bitfld.quad 0x00 0.--5. "TIMEOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error ( 0h: Get Information via another method Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "MMCSD12_MAX_CURRENT_CAP,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x08 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8 V VDD2"
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hexmask.quad.byte 0x08 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8 V VDD1"
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hexmask.quad.byte 0x08 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0 V VDD1"
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hexmask.quad.byte 0x08 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3 V VDD1"
group.word 0x50++0x03
line.word 0x00 "MMCSD12_FORCE_EVNT_ACMD_ERR_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.word 0x00 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error" "Not Affected,Command Not Issued By Auto CMD12.."
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bitfld.word 0x00 5. "RESP,Force Event for AUTO CMD Response Error" "Not Affected,Auto CMD Response Error Status is.."
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bitfld.word 0x00 4. "INDEX,Force Event for AUTO CMD Index Error" "Not Affected,Auto CMD Index Error Status is set"
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bitfld.word 0x00 3. "ENDBIT,Force Event for AUTO CMD End Bit Error" "Not Affected,Auto CMD End bit Error Status is set"
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bitfld.word 0x00 2. "CRC,Force Event for AUTO CMD Timeout Error" "Not Affected,Auto CMD CRC Error Status is set"
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bitfld.word 0x00 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error" "Not Affected,Auto CMD Timeout Error Status is set"
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bitfld.word 0x00 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed" "Not Affected,Auto CMD12 Not Executed Status is.."
line.word 0x02 "MMCSD12_FORCE_EVNT_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.word 0x02 12.--15. "VEND_SPEC,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x02 11. "RESP,Force Event for Response Error" "Not Affected,Response Error Status is set"
newline
bitfld.word 0x02 10. "TUNING,Force Event for Tuning Error" "Not Affected,Tuning Error Status is set"
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bitfld.word 0x02 9. "ADMA,Force Event for ADMA Error" "Not Affected,ADMA Error Status is set"
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bitfld.word 0x02 8. "AUTO_CMD,Force Event for Auto CMD Error" "Not Affected,Auto CMD Error Status is set"
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bitfld.word 0x02 7. "CURR_LIM,Force Event for Current Limit Error" "Not Affected,Current Limit Error Status is set"
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bitfld.word 0x02 6. "DAT_ENDBIT,Force Event for Data End Bit Error" "Not Affected,Data End Bit Error Status is set"
newline
bitfld.word 0x02 5. "DAT_CRC,Force Event for Data CRC Error" "Not Affected,CRC Error Status is set"
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bitfld.word 0x02 4. "DAT_TIMEOUT,Force Event for Data Timeout Error" "Not Affected,Timeout Error Status is set"
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bitfld.word 0x02 3. "CMD_INDEX,Force Event for Command Index Error" "Not Affected,Command Index Error Status is set"
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bitfld.word 0x02 2. "CMD_ENDBIT,Force Event for Command End Bit Error" "Not Affected,Command End Bit Error Status is set"
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bitfld.word 0x02 1. "CMD_CRC,Force Event for Command CRC Error" "Not Affected,Command CRC Error Status is set"
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bitfld.word 0x02 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error" "Not Affected,Command Timeout Error Status is set"
rgroup.byte 0x54++0x00
line.byte 0x00 "MMCSD12_ADMA_ERR_STATUS,When the ADMA Error interrupt occur. this register holds the ADMA State ([1-0] ADMA_ERR_STATE) and the register holds address around the error descriptor"
bitfld.byte 0x00 2. "ADMA_LENGTH_ERR,ADMA Length Mismatch Error This error occurs in the following 2 cases" "No Error,Error"
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bitfld.byte 0x00 0.--1. "ADMA_ERR_STATE,ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer" "ST_STOP (Stop DMA) Points to next of the error..,ST_FDS (Fetch Descriptor) Points to the error..,Never set this state (Not used),ST_TFR (Transfer Data) Points to the next of the.."
group.quad 0x58++0x07
line.quad 0x00 "MMCSD12_ADMA_SYS_ADDRESS,This register contains the physical address used for ADMA data transfer"
rgroup.word 0x60++0x01
line.word 0x00 "MMCSD12_PRESET_VALUE0,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value"
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes" "Driver Type D is Selected,Driver Type C is Selected,Driver Type A is Selected,Driver Type B is Selected"
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bitfld.word 0x00 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "Host Controller Version 2.00 Compatible Clock..,Programmable Clock Generator"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set"
group.quad 0x78++0x07
line.quad 0x00 "MMCSD12_ADMA3_DESC_ADDRESS,The start address of Integrated DMA Descriptor is set to this register"
group.word 0x80++0x01
line.word 0x00 "MMCSD12_UHS2_BLOCK_SIZE,This register is used to configure the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BOUNDARY,UHS-II SDMA Buffer Boundary (SDMA only) When system memory is managed by paging SDMA data transfer is performed in unit of paging" "4K bytes (Detects A11 carry out),8K bytes (Detects A12 carry out),16K Bytes (Detects A13 carry out),32K Bytes (Detects A14 carry out),64K bytes (Detects A15 carry out),128K Bytes (Detects A16 carry out),256K Bytes (Detects A17 carry out),512K Bytes (Detects A18 carry out)"
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hexmask.word 0x00 0.--11. 1. "XFER_BLK_SIZE,UHS-II Block Size This bit field specifies the block size of data packet"
group.long 0x84++0x03
line.long 0x00 "MMCSD12_UHS2_BLOCK_COUNT,This register is used to configure the number of data blocks"
group.word 0x9C++0x03
line.word 0x00 "MMCSD12_UHS2_XFER_MODE,This register is used to control the operations of data transfers"
bitfld.word 0x00 15. "DUPLEX_SELECT,Half/Full Select Use of 2 lane half duplex mode is determined by Host Driver" "Full Duplex Mode,2 Lane Half Duplex Mode"
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bitfld.word 0x00 14. "EBSY_WAIT,EBSY Wait This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution" "Issue a command without..,Wait EBSY"
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bitfld.word 0x00 8. "RESP_INTR_DIS,Response Interrupt Disable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Interrupt is enabled,Response Interrupt is disabled"
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bitfld.word 0x00 7. "RESP_ERR_CHK_ENA,Response Error Check Enable Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "Response Error Check is disabled,Response Error Check is enabled"
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bitfld.word 0x00 6. "RESP_TYPE,Response Type R1/R5 When response error check is enabled this bit selects either R1 or R5 response types" "R1 (Memory),R5 (SDIO)"
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bitfld.word 0x00 5. "BYTE_MODE,Block/Byte Mode This bit specifies whether data transfer is in byte mode or block mode when" "Block Mode,Byte Mode"
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bitfld.word 0x00 4. "DATA_XFER_DIR,Data Transfer Direction This bit specifies direction of data transfer when" "Read (Card to Host),Write (Host to Card)"
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bitfld.word 0x00 1. "BLK_CNT_ENA,Block Count Enable This bit specifies whether data transfer uses" "Block Count Disabled,Block Count Enabled"
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bitfld.word 0x00 0. "DMA_ENA,DMA Enable This bit selects whether DMA is used or not and is effective to a command with data transfer" "DMA is disabled,DMA is enabled"
line.word 0x02 "MMCSD12_UHS2_COMMAND,This register is used to program the Command for host controller"
bitfld.word 0x02 8.--12. "PKT_LENGTH,UHS-II Command Packet Length A command packet length which is set in the UHS-II Command Packet register ( 00011b - 00000b: 3-0 Bytes (Not used) 00100b: 4 Bytes .... .... 10100b: 20 Bytes 11111b - 10101b" "3-0 Bytes (Not used),?,?,?,4 Bytes,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20 Bytes 11111b - 10101b,?..."
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bitfld.word 0x02 6.--7. "CMD_TYPE,Command Type This field is used to distinguish a specific command like abort command" "Normal Command,TRANS_ABORT CCMD,CMD12 or SDIO Abort command,Go Dormant Command"
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bitfld.word 0x02 5. "DATA_PRESENT,Data Present This bit specifies whether the command is accompanied by data packet" "No Data Present,Data Present"
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bitfld.word 0x02 2. "SUB_COMMAND,Sub Command Flag This bit is added from Version 4.10 to distinguish a main command or sub command" "Sub Command,Main Command"
rgroup.byte 0xA0++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_0,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xA4++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_1,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xA8++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_2,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xAC++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_3,This register is used to store received UHS-II RES Packet image"
rgroup.byte 0xB0++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_4,This register is used to store received UHS-II RES Packet image"
group.byte 0xB4++0x00
line.byte 0x00 "MMCSD12_UHS2_MESSAGE_SELECT,This register is used to access internal buffer"
bitfld.byte 0x00 0.--1. "MSG_SEL,UHS-II MSG Select Host Controller holds 4 MSG packets in FIFO buffer" "The latest MSG,One MSG before,Two MSGs before,Three MSGs before"
rgroup.byte 0xB4++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_5,This register is used to store received UHS-II RES Packet image"
rgroup.long 0xB8++0x03
line.long 0x00 "MMCSD12_UHS2_MESSAGE,This register is used to access internal buffer"
hexmask.long.byte 0x00 24.--31. 1. "MSG_BYTE3,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 16.--23. 1. "MSG_BYTE2,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 8.--15. 1. "MSG_BYTE1,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 0.--7. 1. "MSG_BYTE0,UHS II MSG Host Controller holds 4 MSG packets in FIFO buffer"
rgroup.byte 0xB8++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_6,This register is used to store received UHS-II RES Packet image"
group.word 0xBC++0x01
line.word 0x00 "MMCSD12_UHS2_DEVICE_INTR_STATUS,This register shows receipt of INT MSG from which device"
rgroup.byte 0xBC++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_7,This register is used to store received UHS-II RES Packet image"
group.byte 0xBE++0x02
line.byte 0x00 "MMCSD12_UHS2_DEVICE_SELECT,UHS-II Device Select Register"
bitfld.byte 0x00 7. "INT_MSG_ENA,INT MSG Enable (Optional) This bit enables receipt of INT MSG" "Disabled,Enabled"
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bitfld.byte 0x00 0.--3. "DEV_SEL,UHS-II Device Select Host Controller holds an INT MSG packet per device" "Unselected (Default),INT MSG of Device ID 1 is selected,INT MSG of Device ID 2 is selected,?,?,?,?,?,?,?,?,?,?,?,?,INT MSG of Device ID 15 is selected"
line.byte 0x01 "MMCSD12_UHS2_DEVICE_INT_CODE,This register is effective when the [7] INT_MSG_ENA bit is set to 1h"
line.byte 0x02 "MMCSD12_UHS2_RESPONSE_8,This register is used to store received UHS-II RES Packet image"
group.word 0xC0++0x03
line.word 0x00 "MMCSD12_UHS2_SOFTWARE_RESET,UHS-II Software Reset Register"
bitfld.word 0x00 1. "HOST_SDTRAN_RESET,Host SD-TRAN Reset Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs" "Not Affected,Reset SD-TRAN"
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bitfld.word 0x00 0. "HOST_FULL_RESET,Host Full Reset On issuing FULL_RESET CCMD Host Driver set this bit to 1h to reset Host Controller" "Not Affected,Reset Host Controller"
line.word 0x02 "MMCSD12_UHS2_TIMER_CONTROL,UHS-II Timeout Control Register"
bitfld.word 0x02 4.--7. "DEADLOCK_TIMEOUT_CTR,Timeout Counter Value for Deadlock This value determines the deadlock period while host expecting to receive a packet (1 second)" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x 2,Reserved"
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bitfld.word 0x02 0.--3. "CMDRESP_TIMEOUT_CTR,Timeout Counter Value for CMD_RES This value determines the interval between command packet and response packet (5 ms)" "TMCLK x 2,TMCLK x 2,?,?,?,?,?,?,?,?,?,?,?,?,TMCLK x 2,Reserved"
group.long 0xC4++0x03
line.long 0x00 "MMCSD12_UHS2_ERR_INTR_STS,This register gives the status of all UHS-II interrupts"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC_ERR,Vendor Specific Error Vendor may use this field for vendor specific error status" "Interrupt is not generated,Vendor Specific Error,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting of this bit means that deadlock timeout occurs" "Interrupt is not generated,Deadlock Error"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting of this bit means that RES Packet timeout occurs" "Interrupt is not generated,RES Packet Timeout Error"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode" "Interrupt is not generated,ADMA2/3 Error"
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bitfld.long 0x00 8. "EBSY,EBSY Error On receiving EBSY packet if the packet indicates an error this bit is set to 1h" "Interrupt is not generated,EBSY Error (Backend Error)"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting of this bit means that Unrecoverable Error is set in a packet from a device" "Interrupt is not generated,Device Unrecoverable Error"
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bitfld.long 0x00 5. "TID,TID Error Setting of this bit means that TID Error occurs" "Interrupt is not generated,TID Error"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting of this bit means that Framing Error occurs during a packet receiving" "Interrupt is not generated,Framing Error"
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bitfld.long 0x00 3. "CRC,CRC Error Setting of this bit means that CRC Error occurs during a packet receiving" "Interrupt is not generated,CRC Error"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Retry Expired Setting of this bit means that Retry Counter Expired Error occurs during data transfer" "Interrupt is not generated,Retry Expired Error"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "Interrupt is not generated,RES Packet Error"
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bitfld.long 0x00 0. "HEADER,Header Error Setting of this bit means that Header Error occurs in a received packet" "Interrupt is not generated,Header Error"
rgroup.byte 0xC4++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_9,This register is used to store received UHS-II RES Packet image"
group.byte 0xC8++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_16,UHS-II Command Packet image is set to this register"
group.long 0xC8++0x03
line.long 0x00 "MMCSD12_UHS2_ERR_INTR_STS_ENA,This register is used to enable the register fields"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC,Vendor Specific Error Setting this bit to 1h enables setting of Vendor Specific Error bit in" "Status is Disabled,Status is Enabled,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables setting of Timeout for Dead lock bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables setting of Timeout for CMD_RES bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables setting of ADMA2/3 Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 8. "EBSY,EBSY Error Setting this bit to 1h enables setting of EBSY Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables setting of Unrecoverable Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 5. "TID,TID Error Setting this bit to 1h enables setting of TID Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting this bit to 1h enables setting of Framing Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 3. "CRC,CRC Error Setting this bit to 1h enables setting of CRC Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Retry Expired Setting this bit to 1h enables setting of Retry Expired bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables setting of RES Packet Error bit in" "Status is Disabled,Status is Enabled"
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bitfld.long 0x00 0. "HEADER,Header Error Setting this bit to 1h enables setting of Header Error bit in" "Status is Disabled,Status is Enabled"
rgroup.byte 0xC8++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_10,This register is used to store received UHS-II RES Packet image"
group.byte 0xCC++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_17,UHS-II Command Packet image is set to this register"
group.long 0xCC++0x03
line.long 0x00 "MMCSD12_UHS2_ERR_INTR_SIG_ENA,This register is used to generate UHS-II Interrupt signals"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC,Vendor Specific Error Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled,?..."
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT,Timeout for Deadlock Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT,Timeout for CMD_RES Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 15. "ADMA2_ADMA3,ADMA2/3 Error Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 8. "EBSY,EBSY Error Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 7. "UNRECOVERABLE,Unrecoverable Error Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 5. "TID,TID Error Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 4. "FRAMING,Framing Error Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 3. "CRC,CRC Error Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 2. "RETRY_EXPIRED_SIG_ENA,Retry Expired Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 1. "RESP_PKT,RES Packet Error Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
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bitfld.long 0x00 0. "HEADER,Header Error Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in" "Interrupt Signal is Disabled,Interrupt Signal is Enabled"
rgroup.byte 0xCC++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_11,This register is used to store received UHS-II RES Packet image"
group.byte 0xD0++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_18,UHS-II Command Packet image is set to this register"
rgroup.word 0xE0++0x09
line.word 0x00 "MMCSD12_UHS2_SETTINGS_PTR,This register is pointer for UHS-II settings"
line.word 0x02 "MMCSD12_UHS2_CAPABILITIES_PTR,This register is pointer for UHS-II Capabilities Register"
line.word 0x04 "MMCSD12_UHS2_TEST_PTR,This register is pointer for UHS-II Test Register"
line.word 0x06 "MMCSD12_SHARED_BUS_CTRL_PTR,This register is pointer for UHS-II Shared Bus Control Register"
line.word 0x08 "MMCSD12_VENDOR_SPECFIC_PTR,This register is pointer for UHS-II Vendor Specific Register"
group.long 0xF4++0x07
line.long 0x00 "MMCSD12_BOOT_TIMEOUT_CONTROL,This is used to program the boot timeout value counter"
line.long 0x04 "MMCSD12_VENDOR_REGISTER,Vendor register added for Auto Gate SD CLK. CMD11 Power Down Timer. Enhanced Strobe and eMMC Hardware Reset"
bitfld.long 0x04 16. "AUTOGATE_SDCLK,Auto Gate SD CLK If this bit is set SD CLK will be gated automatically when there is no transfer" "Disable,Enable"
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hexmask.long.word 0x04 2.--15. 1. "CMD11_PD_TIMER,CMD11 Power Down Timer Value"
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bitfld.long 0x04 1. "EMMC_HW_RESET,eMMC Hardware Reset Hardware reset signal is generared for eMMC card when this bit is set" "De-sassert hardware reset pin,Drives the hardware reset pin as ZERO (Active.."
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bitfld.long 0x04 0. "ENHANCED_STROBE,Enhanced Strobe This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x03
line.word 0x00 "MMCSD12_SLOT_INT_STS,This register is used to read the interrupt signal for each slot"
hexmask.word.byte 0x00 0.--7. 1. "INTR_SIG,Interrupt Signal for Slot#0 These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot"
line.word 0x02 "MMCSD12_HOST_CONTROLLER_VER,This register is used to read the vendor version number and specification version number"
hexmask.word.byte 0x02 8.--15. 1. "VEN_VER_NUM,Vendor Version Number The Vendor Version Number is set to 10h (1.0)"
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abitfld.word 0x02 0.--7. "SPEC_VER_NUM,Specification Version Number This status indicates the Host Controller Specification Version" "0x00=SD Host Controller Specification Version 1.00,0x01=SD Host Controller Specification Version..,0x02=SD Host Controller Specification Version 3.00,0x03=SD Host Controller Specification Version 4.00,0x04=SD Host Controller Specification Version.."
group.long 0x100++0x07
line.long 0x00 "MMCSD12_UHS2_GEN_SETTINGS,Start Address of General settings is pointed by the Register"
bitfld.long 0x00 8.--13. "NUMLANES,Number of Lanes and Functionalities The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices" "2 Lanes FD or 2L-HD,Not Used,3 Lanes 2D1U-FD (Embedded),3 Lanes 1D2U-FD (Embedded),4 Lanes 2D2U-FD (Embedded) Others: Reserved,?..."
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bitfld.long 0x00 0. "POWER_MODE,Power Mode This field determines either Fast mode or Low Power mode" "Fast Mode,Low Power Mode"
line.long 0x04 "MMCSD12_UHS2_PHY_SETTINGS,Start Address of PHY settings is pointed by the Register"
bitfld.long 0x04 20.--23. "N_LSS_DIR,Host N_LSS_DIR The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field" "8 x 16 LSS,8 x 1 LSS,8 x 2 LSS,8 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,8 x 15 LSS"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,Host N_LSS_SYN The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS 3h - 4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 15. "HIBERNATE_ENA,Hibernate Enable After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set" "Hibernate Disabled,Hibernate Enabled"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,Speed Range PLL multiplier is selected by this field" "Range A (Defalt),Range B,Reserved,Reserved"
group.quad 0x108++0x07
line.quad 0x00 "MMCSD12_UHS2_LNK_TRN_SETTINGS,Start Address of LINK/TRAN settings is pointed by the Register"
abitfld.quad 0x00 32.--39. "N_DATA_GAP,Host N_DATA_GAP The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field" "0x00=No Gap,0x01=1 LSS,0x02=2 LSS,0x03=3 LSS,0xFF=255 LSS"
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bitfld.quad 0x00 16.--17. "RETRY_COUNT,Retry Count Data Burst retry count is set to this field" "Retry Disabled,1 time,2 times,3 times"
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abitfld.quad 0x00 8.--15. "HOST_NFCU,Host N_FCU Host Driver sets the number of blocks in Data Burst (Flow Control) to this field" "0x00=256 Blocks,0x01=1 Block,0x02=2 Blocks,0x03=3 Blocks,0xFF=255 Blocks"
rgroup.long 0x110++0x07
line.long 0x00 "MMCSD12_UHS2_GEN_CAP,Start Address of General Capabilities is pointed by the Register"
bitfld.long 0x00 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,Bus Topology This field indicates one of bus topologies configured by a Host system" "P2P Connection,Ring Connection,HUB Connection,HUB is Connected in Ring"
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bitfld.long 0x00 18.--21. "CORECFG_UHS2_MAX_DEVICES,Number of Devices Supported This field indicates the maximum number of devices supported by the Host Controller" "Not used,1 Devices,2 Devices,?,?,?,?,?,?,?,?,?,?,?,?,15 Devices"
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bitfld.long 0x00 16.--17. "DEVICE_TYPE,Removable/Embedded This field indicates device type configured by a Host system" "Removable Card (P2P),Embedded Devices,Embedded Devices + Removable Card,Reserved"
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bitfld.long 0x00 14. "CFG_64BIT_ADDRESSING,64-bit Addressing This field indicates support of 64-bit addressing by the Host Controller" "32-bit Addressing is supported,32-bit and 64-bit Addressing is supported"
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bitfld.long 0x00 8.--13. "NUM_LANES,Number of Lanes and Functionalities This field indicates support of lanes by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--7. "GAP,GAP (Group Allocation Power) This field indicates the maximum capability of host power supply for a group configured by a Host system" "Not used,360 mW,720 mW,?,?,?,?,?,?,?,?,?,?,?,?,360 x 15 mW"
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bitfld.long 0x00 0.--3. "DAP,DAP (Device Allocation Power) This field indicates the maximum capability of host power supply for a device configured by a Host system" "360 mW (Default),360 mW,720 mW,?,?,?,?,?,?,?,?,?,?,?,?,360 x 15 mW"
line.long 0x04 "MMCSD12_UHS2_PHY_CAP,Start Address of PHY Capabilities is pointed by the Register"
bitfld.long 0x04 20.--23. "N_LSS_DIR,Host N_LSS_DIR This field indicates the minimum N_LSS_DIR required by the Host Controller" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS,4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,Host N_LSS_SYN This field indicates the minimum N_LSS_SYN required by the Host Controller" "4 x 16 LSS,4 x 1 LSS,4 x 2 LSS,4 x 3 LSS,?,?,?,?,?,?,?,?,?,?,?,4 x 15 LSS"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,Speed Range This field indicates supported Speed Range by the Host Controller" "Range A (Default),Range A and Range B,Reserved,Reserved"
rgroup.quad 0x118++0x07
line.quad 0x00 "MMCSD12_UHS2_LNK_TRN_CAP,Start Address of LINK/TRAN settings is pointed by the Register"
abitfld.quad 0x00 32.--39. "N_DATA_GAP,Host N_DATA_GAP This field indicates the minimum number of data gap (DIDL) supported by the Host Controller" "0x00=No Gap,0x01=1 LSS,0x02=2 LSS,0x03=3 LSS,0xFF=255 LSS"
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abitfld.quad 0x00 20.--31. "MAX_BLK_LENGTH,Host Maximum Block Length This field indicates maximum block length by the Host Controller" "0x000=Not Used,0x001=1 byte,0x002=2 bytes,0x200=512 bytes,0x800=2048 bytes,0x801=FFFh"
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abitfld.quad 0x00 8.--15. "N_FCU,Host N_FCU This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller" "0x00=256 Blocks,0x01=1 Block,0x02=2 Block,0x03=3 Block,0xFF=255 Blocks"
group.long 0x120++0x03
line.long 0x00 "MMCSD12_FORCE_UHSII_ERR_INT_STS,This register is not physically implemented. rather it is an address where the register can be written"
bitfld.long 0x00 27.--31. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error" "Not Affected,Vendor Specific Error Status is set,?..."
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bitfld.long 0x00 17. "TIMEOUT_DEADLOCK,Force Event for Timeout for Deadlock Setting this bit forces the Host Controller to set Timeout for Deadlock in" "Not affected,Timeout for Deadlock Error status.."
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bitfld.long 0x00 16. "TIMEOUT_CMD_RES,Force Event for Timeout for CMD_RES Setting this bit forces the Host Controller to set Timeout for CMD_RES in" "Not affected,Timout for CMD_RES Status is set"
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bitfld.long 0x00 15. "ADMA,Force Event for ADMA Error Setting this bit forces the Host Controller to set ADMA Error in" "Not affected,ADMA Error Status is set"
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bitfld.long 0x00 8. "EBSY,Force Event for EBSY Error Setting this bit forces the Host Controller to set EBSY Error in" "Not affected,EBSY Error Status is set"
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bitfld.long 0x00 7. "UNRECOVERABLE,Force Event for Unrecoverable Error Setting this bit forces the Host Controller to set Unrecoverable Error in" "Not affected,Unrecoverable Error Status is set"
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bitfld.long 0x00 5. "TID,Force Event for TID Error Setting this bit forces the Host Controller to set TID Error in" "Not affected,TID Error Status is set"
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bitfld.long 0x00 4. "FRAMING,Force Event for Framing Error Setting this bit forces the Host Controller to set Framing Error in" "Not affected,Framing Error Status is set"
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bitfld.long 0x00 3. "CRC,Force Event for CRC Error Setting this bit forces the Host Controller to set CRC Error in" "Not affected,CRC Error Status is set"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Force Event for Retry Expired Setting this bit forces the Host Controller to set Retry Expired in" "Not affected,Retry expired error status is set"
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bitfld.long 0x00 1. "RES_PKT,Force Event for RES Packet Error Setting this bit forces the Host Controller to set RES Packet Error in" "Not affected,RES packet error status is set"
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bitfld.long 0x00 0. "HEADER,Force Event for Header Error Setting this bit forces the Host Controller to set Header Error in" "Not affected,Header error status is set"
rgroup.long 0x200++0x3B
line.long 0x00 "MMCSD12_CQ_VERSION,This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE. in BCD format"
bitfld.long 0x00 8.--11. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number (digit left of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number (digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VERSION_SUFFIX,eMMC Version Suffix (2nd digit right of decimal point) in BCD format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MMCSD12_CQ_CAPABILITIES,This register is reserved for capability indication"
bitfld.long 0x04 12.--15. "CF_MUL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period" "0.001 MHz,0.01 MHz,0.1 MHz,1 MHz,10 MHz Other values..,?..."
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hexmask.long.word 0x04 0.--9. 1. "CF_VAL,ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling"
line.long 0x08 "MMCSD12_CQ_CONFIG,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time"
bitfld.long 0x08 12. "DCMD_ENA,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor" "Task descriptor in slot #31 is a Data Transfer..,Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x08 8. "TASK_DESC_SIZE,This bit indicates whether the task descriptor size is 128 bits or 64 bits" "Task descriptor size is 64 bits,Task descriptor size is 128 bits"
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bitfld.long 0x08 0. "CQ_ENABLE,Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE)" "0,1"
line.long 0x0C "MMCSD12_CQ_CONTROL,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time"
bitfld.long 0x0C 8. "CLEAR_ALL_TASKS,Software shall write 1h to this bit when it wants to clear all the tasks sent to the device" "0,1"
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bitfld.long 0x0C 0. "HALT_BIT,Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus" "0,1"
line.long 0x10 "MMCSD12_CQ_INTR_STS,This register indicates pending interrupts that require service"
bitfld.long 0x10 4. "TASK_ERROR,This bit is asserted when task error is detected due to invalid task descriptor" "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED,This status bit is asserted (if" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET,This status bit is asserted (if Software uses" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,This status bit is asserted (if (1) A task is completed and the INT bit is set in its Task Descriptor (2) Interrupt caused by Interrupt Coalescing logic" "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE,This status bit is asserted (if" "0,1"
line.long 0x14 "MMCSD12_CQ_INTR_STS_ENA,This register enables and disables the reporting of the corresponding interrupt to host software in 299 register"
bitfld.long 0x14 4. "TASK_ERROR," "0,1"
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bitfld.long 0x14 3. "TASK_CLEARED," "0,1"
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bitfld.long 0x14 2. "RESP_ERR_DET," "0,1"
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bitfld.long 0x14 1. "TASK_COMPLETE," "0,1"
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bitfld.long 0x14 0. "HALT_COMPLETE," "0,1"
line.long 0x18 "MMCSD12_CQ_INTR_SIG_ENA,This register enables and disables the generation of interrupts to host software"
bitfld.long 0x18 4. "TASK_ERROR,When set and" "0,1"
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bitfld.long 0x18 3. "TASK_CLEARED,When set and" "0,1"
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bitfld.long 0x18 2. "RESP_ERR_DET,When set and" "0,1"
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bitfld.long 0x18 1. "TASK_COMPLETE,When set and" "0,1"
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bitfld.long 0x18 0. "HALT_COMPLETE,When set and" "0,1"
line.long 0x1C "MMCSD12_CQ_INTR_COALESCING,This register controls the interrupt coalescing feature"
bitfld.long 0x1C 31. "CQINTCOALESC_ENABLE,When set to 0h by software command responses are neither counted nor timed" "0,1"
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bitfld.long 0x1C 20. "IC_STATUS,This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0)" "No task completions have occurred since last..,At least one task completion has been counted.."
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bitfld.long 0x1C 8.--12. "CTR_THRESHOLD,Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x1C 0.--6. 1. "TIMEOUT_VAL,Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt"
line.long 0x20 "MMCSD12_CQ_TDL_BASE_ADDR,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory"
line.long 0x24 "MMCSD12_CQ_TDL_BASE_ADDR_UPBITS,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory"
line.long 0x28 "MMCSD12_CQ_TASK_DOOR_BELL,Using this register. software triggers CQE to process a new task"
line.long 0x2C "MMCSD12_CQ_TASK_COMP_NOTIF,This register is used by CQE to notify software about completed tasks"
line.long 0x30 "MMCSD12_CQ_DEV_QUEUE_STATUS,This register stores the most recent value of the device's queue status"
line.long 0x34 "MMCSD12_CQ_DEV_PENDING_TASKS,This register indicates to software which tasks are queued in the device. awaiting execution"
line.long 0x38 "MMCSD12_CQ_TASK_CLEAR,This register is used for removing an outstanding task in the CQE 327"
group.long 0x240++0x0B
line.long 0x00 "MMCSD12_CQ_SEND_STS_CONFIG1,The register controls when the SEND_QUEUE_STATUS commands are sent"
bitfld.long 0x00 16.--19. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling"
line.long 0x04 "MMCSD12_CQ_SEND_STS_CONFIG2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument"
hexmask.long.word 0x04 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument"
line.long 0x08 "MMCSD12_CQ_DCMD_RESPONSE,This register is used for passing the response of a DCMD task to software"
rgroup.long 0x250++0x13
line.long 0x00 "MMCSD12_CQ_RESP_ERR_MASK,This register controls the generation of Response Error Detection (RED) interrupt"
line.long 0x04 "MMCSD12_CQ_TASK_ERR_INFO,This register is updated by CQE when an error occurs on data or command related to a task activity"
bitfld.long 0x04 31. "DATERR_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 24.--28. "DATERR_TASK_ID,This field indicates the ID of the task which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--21. "DATERR_CMD_INDEX,This field indicates the index of the command which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "RESP_MODE_VALID,This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 8.--12. "RESP_MODE_TASK_ID,This field indicates the ID of the task which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "RESP_MODE_CMD_INDEX,This field indicates the index of the command which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MMCSD12_CQ_CMD_RESP_INDEX,This register stores the index of the last received command response"
bitfld.long 0x08 0.--5. "LAST_CRI,This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MMCSD12_CQ_CMD_RESP_ARG,This register stores the index of the last received command response"
line.long 0x10 "MMCSD12_CQ_ERROR_TASK_ID,CQ Error Task ID Register"
bitfld.long 0x10 0.--4. "TERR_ID,Task Error ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 7. (list 12. 13. 14. 15. 16. 17. 18. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
rgroup.byte ($2+0xD0)++0x00
line.byte 0x00 "MMCSD12_UHS2_RESPONSE_$1,This register is used to store received UHS-II RES Packet image"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.byte ($2+0x88)++0x00
line.byte 0x00 "MMCSD12_UHS2_COMMAND_PKT_$1,UHS-II Command Packet image is set to this register"
repeat.end
repeat 9. (list 1. 2. 3. 4. 5. 6. 7. 8. 10. )(list 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x10 0x12 )
rgroup.word ($2+0x62)++0x01
line.word 0x00 "MMCSD12_PRESET_VALUE$1,This register is used to read the SDCLK Frequency Select Value. Clock Generator Select Value. Driver Strength Select Value"
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength Select Value (UHS-I Only) Driver Strength is supported by 1.8 V signaling bus speed modes" "Driver Type D is Selected,Driver Type C is Selected,Driver Type A is Selected,Driver Type B is Selected"
bitfld.word 0x00 10. "CLOCK_GENSEL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator" "Host Controller Version 2.00 Compatible Clock..,Programmable Clock Generator"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL,SDCLK Frequency Select Value 10-bit preset value to set"
repeat.end
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
rgroup.word ($2+0x10)++0x01
line.word 0x00 "MMCSD12_RESPONSE_$1,This registers is used to store responses from SD Cards"
repeat.end
tree.end
tree.end
tree "MMCSD1___MMCSD2_RX_RAM_ECC_Aggregator"
tree "MMCSD1_ECC_AGGR_RXMEM"
base ad:0x2A26000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD12_RXECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MMCSD12_RXECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MMCSD12_RXECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "MMCSD12_RXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,SEC EOI" "0,1"
line.long 0x04 "MMCSD12_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MMCSD12_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MMCSD12_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MMCSD12_RXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,DED EOI" "0,1"
line.long 0x04 "MMCSD12_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MMCSD12_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MMCSD12_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MMCSD12_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MMCSD12_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MMCSD12_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MMCSD12_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD2_ECC_AGGR_RXMEM"
base ad:0x2A71000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD12_RXECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MMCSD12_RXECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MMCSD12_RXECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "MMCSD12_RXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,SEC EOI" "0,1"
line.long 0x04 "MMCSD12_RXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MMCSD12_RXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MMCSD12_RXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MMCSD12_RXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,DED EOI" "0,1"
line.long 0x04 "MMCSD12_RXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MMCSD12_RXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set for rxmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MMCSD12_RXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear for rxmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MMCSD12_RXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MMCSD12_RXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MMCSD12_RXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MMCSD12_RXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MMCSD1___MMCSD2_Subsystem"
tree "MMCSD1_SS_CFG"
base ad:0x4FB8000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD12_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MIN_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x33
line.long 0x00 "MMCSD12_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x00 24.--29. "TUNINGCOUNT,Configures the number of Taps (Phases) of the RX clock that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode" "0,1"
bitfld.long 0x00 12.--15. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x04 "MMCSD12_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x04 30.--31. "SLOTTYPE,Slot Type Should be set based on the final product usage" "0,1,2,3"
bitfld.long 0x04 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt)" "0,1"
bitfld.long 0x04 26. "SUPPORT1P8VOLT,1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by Core)" "0,1"
bitfld.long 0x04 25. "SUPPORT3P0VOLT,3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface" "0,1"
bitfld.long 0x04 24. "SUPPORT3P3VOLT,3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface" "0,1"
newline
bitfld.long 0x04 23. "SUSPRESSUPPORT,Suspend/Resume Support Suggested Value is 1h (The Suspend/Resume is supported by Core)" "0,1"
bitfld.long 0x04 22. "SDMASUPPORT,SDMA Support Suggested Value is 1h (The SDMA is supported by Core)" "0,1"
bitfld.long 0x04 21. "HIGHSPEEDSUPPORT,High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core)" "0,1"
bitfld.long 0x04 19. "ADMA2SUPPORT,ADMA2 Support Suggested Value is 1h (The ADMA2 is supported by Core)" "0,1"
bitfld.long 0x04 18. "SUPPORT8BIT,8-bit Support for Embedded Device Suggested Value is 1h (The Core supports 8-bit Interface)" "0,1"
newline
bitfld.long 0x04 16.--17. "MAXBLKLENGTH,Max Block Length Maximum Block Length supported by the Core/Device" "0,1,2,3"
hexmask.long.byte 0x04 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock This is the frequency of the xin_clk"
bitfld.long 0x04 7. "TIMEOUTCLKUNIT,Timeout Clock Unit Suggested Value is 0h (KHz)" "0,1"
bitfld.long 0x04 0.--5. "TIMEOUTCLKFREQ,Timeout Clock Frequency Suggested Value is 1 KHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MMCSD12_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x08 28. "SUPPORT1P8VDD2,1.8 V VDD2 Support" "0,1"
bitfld.long 0x08 27. "ADMA3SUPPORT,ADMA3 Support" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator"
bitfld.long 0x08 14.--15. "RETUNINGMODES,Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning" "0,1,2,3"
bitfld.long 0x08 13. "TUNINGFORSDR50,Use Tuning for SDR50 This bit should be set if the application wants Tuning be used for SDR50 Modes" "0,1"
newline
bitfld.long 0x08 8.--11. "RETUNINGTIMERCNT,Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 7. "TYPE4SUPPORT,Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 6. "DDRIVERSUPPORT,Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 5. "CDRIVERSUPPORT,Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 4. "ADRIVERSUPPORT,Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not" "0,1"
newline
bitfld.long 0x08 2. "DDR50SUPPORT,DDR50 Support Suggested Value is 1h (The Core supports DDR50 mode of operation)" "0,1"
bitfld.long 0x08 1. "SDR104SUPPORT,SDR104 Support" "0,1"
bitfld.long 0x08 0. "SDR50SUPPORT,SDR50 Support" "0,1"
line.long 0x0C "MMCSD12_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.byte 0x0C 16.--23. 1. "MAXCURRENT1P8V,Maximum Current For 1.8 V"
hexmask.long.byte 0x0C 8.--15. 1. "MAXCURRENT3P0V,Maximum Current For 3.0 V"
hexmask.long.byte 0x0C 0.--7. 1. "MAXCURRENT3P3V,Maximum Current For 3.3 V"
line.long 0x10 "MMCSD12_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current For 1.8 V (VDD2)"
line.long 0x14 "MMCSD12_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value For Initialization"
line.long 0x18 "MMCSD12_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value For Default Speed"
line.long 0x1C "MMCSD12_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value For High Speed"
line.long 0x20 "MMCSD12_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value For SDR12"
line.long 0x24 "MMCSD12_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value For SDR25"
line.long 0x28 "MMCSD12_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value For SDR50"
line.long 0x2C "MMCSD12_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value For SDR104"
line.long 0x30 "MMCSD12_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value For DDR50"
rgroup.long 0x60++0x17
line.long 0x00 "MMCSD12_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller"
bitfld.long 0x00 31. "SDHC_CMDIDLE,Idle signal to enable software to gate off the clocks" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus"
line.long 0x04 "MMCSD12_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x04 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus"
line.long 0x08 "MMCSD12_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x08 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus"
line.long 0x0C "MMCSD12_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x0C 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)"
line.long 0x10 "MMCSD12_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)"
line.long 0x14 "MMCSD12_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus"
group.long 0x100++0x03
line.long 0x00 "MMCSD12_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x00 31. "IOMUX_ENABLE,IO Mux Enable Set 1h for GPIO" "0,1"
group.long 0x10C++0x07
line.long 0x00 "MMCSD12_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x00 20. "OTAPDLYENA,Output Tap Delay Enable Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface" "0,1"
bitfld.long 0x00 12.--15. "OTAPDLYSEL,Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "ITAPCHGWIN,Input Tap Change Window It gets asserted by the controller while changing the itapdlysel" "0,1"
bitfld.long 0x00 8. "ITAPDLYENA,Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes" "0,1"
bitfld.long 0x00 0.--4. "ITAPDLYSEL,Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MMCSD12_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x04 0.--2. "CLKBUFSEL,Clock Delay Buffer Select" "0,1,2,3,4,5,6,7"
tree.end
tree "MMCSD2_SS_CFG"
base ad:0x4F90000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD12_SS_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MIN_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x33
line.long 0x00 "MMCSD12_SS_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x00 24.--29. "TUNINGCOUNT,Configures the number of Taps (Phases) of the RX clock that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode" "0,1"
bitfld.long 0x00 12.--15. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x04 "MMCSD12_SS_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x04 30.--31. "SLOTTYPE,Slot Type Should be set based on the final product usage" "0,1,2,3"
bitfld.long 0x04 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt)" "0,1"
bitfld.long 0x04 26. "SUPPORT1P8VOLT,1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by Core)" "0,1"
bitfld.long 0x04 25. "SUPPORT3P0VOLT,3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface" "0,1"
bitfld.long 0x04 24. "SUPPORT3P3VOLT,3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface" "0,1"
newline
bitfld.long 0x04 23. "SUSPRESSUPPORT,Suspend/Resume Support Suggested Value is 1h (The Suspend/Resume is supported by Core)" "0,1"
bitfld.long 0x04 22. "SDMASUPPORT,SDMA Support Suggested Value is 1h (The SDMA is supported by Core)" "0,1"
bitfld.long 0x04 21. "HIGHSPEEDSUPPORT,High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core)" "0,1"
bitfld.long 0x04 19. "ADMA2SUPPORT,ADMA2 Support Suggested Value is 1h (The ADMA2 is supported by Core)" "0,1"
bitfld.long 0x04 18. "SUPPORT8BIT,8-bit Support for Embedded Device Suggested Value is 1h (The Core supports 8-bit Interface)" "0,1"
newline
bitfld.long 0x04 16.--17. "MAXBLKLENGTH,Max Block Length Maximum Block Length supported by the Core/Device" "0,1,2,3"
hexmask.long.byte 0x04 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock This is the frequency of the xin_clk"
bitfld.long 0x04 7. "TIMEOUTCLKUNIT,Timeout Clock Unit Suggested Value is 0h (KHz)" "0,1"
bitfld.long 0x04 0.--5. "TIMEOUTCLKFREQ,Timeout Clock Frequency Suggested Value is 1 KHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MMCSD12_SS_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller"
bitfld.long 0x08 28. "SUPPORT1P8VDD2,1.8 V VDD2 Support" "0,1"
bitfld.long 0x08 27. "ADMA3SUPPORT,ADMA3 Support" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier This field indicates clock multiplier value of programmable clock generator"
bitfld.long 0x08 14.--15. "RETUNINGMODES,Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning" "0,1,2,3"
bitfld.long 0x08 13. "TUNINGFORSDR50,Use Tuning for SDR50 This bit should be set if the application wants Tuning be used for SDR50 Modes" "0,1"
newline
bitfld.long 0x08 8.--11. "RETUNINGTIMERCNT,Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 7. "TYPE4SUPPORT,Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 6. "DDRIVERSUPPORT,Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 5. "CDRIVERSUPPORT,Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not" "0,1"
bitfld.long 0x08 4. "ADRIVERSUPPORT,Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not" "0,1"
newline
bitfld.long 0x08 2. "DDR50SUPPORT,DDR50 Support Suggested Value is 1h (The Core supports DDR50 mode of operation)" "0,1"
bitfld.long 0x08 1. "SDR104SUPPORT,SDR104 Support" "0,1"
bitfld.long 0x08 0. "SDR50SUPPORT,SDR50 Support" "0,1"
line.long 0x0C "MMCSD12_SS_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.byte 0x0C 16.--23. 1. "MAXCURRENT1P8V,Maximum Current For 1.8 V"
hexmask.long.byte 0x0C 8.--15. 1. "MAXCURRENT3P0V,Maximum Current For 3.0 V"
hexmask.long.byte 0x0C 0.--7. 1. "MAXCURRENT3P3V,Maximum Current For 3.3 V"
line.long 0x10 "MMCSD12_SS_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current For 1.8 V (VDD2)"
line.long 0x14 "MMCSD12_SS_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value For Initialization"
line.long 0x18 "MMCSD12_SS_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value For Default Speed"
line.long 0x1C "MMCSD12_SS_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value For High Speed"
line.long 0x20 "MMCSD12_SS_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value For SDR12"
line.long 0x24 "MMCSD12_SS_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value For SDR25"
line.long 0x28 "MMCSD12_SS_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value For SDR50"
line.long 0x2C "MMCSD12_SS_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value For SDR104"
line.long 0x30 "MMCSD12_SS_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller"
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value For DDR50"
rgroup.long 0x60++0x17
line.long 0x00 "MMCSD12_SS_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller"
bitfld.long 0x00 31. "SDHC_CMDIDLE,Idle signal to enable software to gate off the clocks" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus"
line.long 0x04 "MMCSD12_SS_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x04 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus"
line.long 0x08 "MMCSD12_SS_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x08 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus"
line.long 0x0C "MMCSD12_SS_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x0C 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)"
line.long 0x10 "MMCSD12_SS_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)"
line.long 0x14 "MMCSD12_SS_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller"
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus"
group.long 0x100++0x03
line.long 0x00 "MMCSD12_SS_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x00 31. "IOMUX_ENABLE,IO Mux Enable Set 1h for GPIO" "0,1"
group.long 0x10C++0x07
line.long 0x00 "MMCSD12_SS_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x00 20. "OTAPDLYENA,Output Tap Delay Enable Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface" "0,1"
bitfld.long 0x00 12.--15. "OTAPDLYSEL,Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "ITAPCHGWIN,Input Tap Change Window It gets asserted by the controller while changing the itapdlysel" "0,1"
bitfld.long 0x00 8. "ITAPDLYENA,Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes" "0,1"
bitfld.long 0x00 0.--4. "ITAPDLYSEL,Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MMCSD12_SS_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY"
bitfld.long 0x04 0.--2. "CLKBUFSEL,Clock Delay Buffer Select" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "MMCSD1___MMCSD2_TX_RAM_ECC_Aggregator"
tree "MMCSD1_ECC_AGGR_TXMEM"
base ad:0x2A27000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD12_TXECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MMCSD12_TXECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MMCSD12_TXECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "MMCSD12_TXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,SEC EOI" "0,1"
line.long 0x04 "MMCSD12_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MMCSD12_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MMCSD12_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MMCSD12_TXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,DED EOI" "0,1"
line.long 0x04 "MMCSD12_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MMCSD12_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MMCSD12_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MMCSD12_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MMCSD12_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MMCSD12_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MMCSD12_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD2_ECC_AGGR_TXMEM"
base ad:0x2A70000
rgroup.long 0x00++0x03
line.long 0x00 "MMCSD12_TXECC_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "MMCSD12_TXECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial ECC interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial ECC interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MMCSD12_TXECC_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "MMCSD12_TXECC_SEC_EOI_REG,SEC EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,SEC EOI" "0,1"
line.long 0x04 "MMCSD12_TXECC_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MMCSD12_TXECC_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MMCSD12_TXECC_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MMCSD12_TXECC_DED_EOI_REG,DED EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,DED EOI" "0,1"
line.long 0x04 "MMCSD12_TXECC_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MMCSD12_TXECC_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set for txmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MMCSD12_TXECC_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear for txmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MMCSD12_TXECC_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial ECC interface timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "MMCSD12_TXECC_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial ECC interface timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MMCSD12_TXECC_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MMCSD12_TXECC_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial ECC interface timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "MODSS_INTA_CFG"
tree "NAVSS0_MODSS_INTA0_CFG"
base ad:0x30800000
rgroup.quad 0x00++0x17
line.quad 0x00 "INTA_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.quad.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.quad 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.quad 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "INTA_INTCAP,The IntCap Register contains information on virtual interrupts"
hexmask.quad.word 0x08 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count"
hexmask.quad.word 0x08 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers"
line.quad 0x10 "INTA_AUXCAP,The AuxCap Register contains information on additional capabilities"
hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers"
hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation"
hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers"
tree.end
tree "NAVSS0_MODSS_INTA1_CFG"
base ad:0x30801000
rgroup.quad 0x00++0x17
line.quad 0x00 "INTA_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.quad.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.quad 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--10. "REVMAJ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.quad 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "INTA_INTCAP,The IntCap Register contains information on virtual interrupts"
hexmask.quad.word 0x08 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count"
hexmask.quad.word 0x08 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers"
line.quad 0x10 "INTA_AUXCAP,The AuxCap Register contains information on additional capabilities"
hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers"
hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation"
hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers"
tree.end
tree.end
tree "MODSS_INTA_CFG_IMAP"
tree "NAVSS0_MODSS_INTA0_CFG_IMAP"
base ad:0x30900000
group.quad 0x00++0x07
line.quad 0x00 "INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto"
hexmask.quad.word 0x00 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in"
bitfld.quad 0x00 0.--5. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "NAVSS0_MODSS_INTA1_CFG_IMAP"
base ad:0x30908000
group.quad 0x00++0x07
line.quad 0x00 "INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto"
hexmask.quad.word 0x00 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in"
bitfld.quad 0x00 0.--5. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "MODSS_INTA_CFG_INTR"
tree "NAVSS0_MODSS_INTA0_CFG_INTR"
base ad:0x33C00000
group.quad 0x00++0x27
line.quad 0x00 "INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x08 "INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x10 "INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x18 "INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x20 "INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt"
tree.end
tree "NAVSS0_MODSS_INTA1_CFG_INTR"
base ad:0x33C40000
group.quad 0x00++0x27
line.quad 0x00 "INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x08 "INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x10 "INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x18 "INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x20 "INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt"
tree.end
tree.end
tree "MSMC"
tree "COMPUTE_CLUSTER0_MSMC_CFGS0"
base ad:0x6E000000
rgroup.quad 0x00++0x07
line.quad 0x00 "MSMC_PID,Peripheral ID Register"
hexmask.quad 0x00 0.--31. 1. "REVISION,PID Revision"
group.quad 0x1000++0x07
line.quad 0x00 "MSMC_CACHE_CTRL,Cache Control Register"
bitfld.quad 0x00 10. "ALLOCATION_POLICY,Allocation Policy" "0,1"
bitfld.quad 0x00 8. "REPLACEMENT_POLICY,Replacement Policy" "0,1"
rbitfld.quad 0x00 4. "SZ_TRANSITION,Cache Size Change in Progress" "0,1"
bitfld.quad 0x00 0.--3. "CACHE_SIZE,Cache Size Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad 0x1010++0x0F
line.quad 0x00 "MSMC_RT_WAY_SELECT,Real Time Way Select"
bitfld.quad 0x00 5.--6. "OR_MASK,OR mask for way-select" "0,1,2,3"
bitfld.quad 0x00 0.--1. "AND_MASK,AND mask for way-select" "0,1,2,3"
line.quad 0x08 "MSMC_NRT_WAY_SELECT,Non Real Time Way Select"
bitfld.quad 0x08 5.--6. "OR_MASK,OR mask for way-select" "0,1,2,3"
bitfld.quad 0x08 0.--1. "AND_MASK,AND mask for way-select" "0,1,2,3"
group.quad 0x2048++0x07
line.quad 0x00 "MSMC_COHCTRL,Coherence Control Register"
bitfld.quad 0x00 0. "BCM,Broadcast Mode" "0,1"
group.quad 0x3080++0x07
line.quad 0x00 "MSMC_SMEDCC,Scrub Rate Register"
bitfld.quad 0x00 31. "SEN,Scrub Engine Enable" "0,1"
hexmask.quad.byte 0x00 0.--7. 1. "REFDEL,Number of Clock Cycles Between Scrubs"
rgroup.quad 0x5000++0x0F
line.quad 0x00 "MSMC_SMESTAT,Interrupt Enabled Status register"
bitfld.quad 0x00 0. "NULL_SLV,Null slave error is enabled and pending" "0,1"
line.quad 0x08 "MSMC_SMIRSTAT,Interrupt raw status register"
bitfld.quad 0x08 0. "NULL_SLV,Null slave error flagged" "0,1"
group.quad 0x5008++0x17
line.quad 0x00 "MSMC_SMIRWS,Set interrupt raw status register"
bitfld.quad 0x00 0. "NULL_SLV,Set software null slave error" "0,1"
line.quad 0x08 "MSMC_SMIRC,Interrupt clear register"
bitfld.quad 0x08 0. "NULL_SLV,Clear null slave error flag" "0,1"
line.quad 0x10 "MSMC_SMIESTAT,Interrupt raw status register"
bitfld.quad 0x10 0. "NULL_SLV,Null slave error interrupt is enabled" "0,1"
group.quad 0x5018++0x0F
line.quad 0x00 "MSMC_SMIEWS,Set interrupt raw status register"
bitfld.quad 0x00 0. "NULL_SLV,Enable null slave error" "0,1"
line.quad 0x08 "MSMC_SMIEC,Interrupt clear register"
bitfld.quad 0x08 0. "NULL_SLV,clear null slave error interrupt enable" "0,1"
group.quad 0x6000++0x57
line.quad 0x00 "MSMC_SBNDCOH0,Starvation Bound for Coherent Port 0"
hexmask.quad.byte 0x00 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x00 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x08 "MSMC_SBNDCOH1,Starvation Bound for Coherent Port 1"
hexmask.quad.byte 0x08 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x08 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x08 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x08 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x10 "MSMC_SBNDCOH2,Starvation Bound for Coherent Port 2"
hexmask.quad.byte 0x10 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x10 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x10 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x10 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x18 "MSMC_SBNDCOH3,Starvation Bound for Coherent Port 3"
hexmask.quad.byte 0x18 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x18 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x18 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x18 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x20 "MSMC_SBNDCOH4,Starvation Bound for Coherent Port 4"
hexmask.quad.byte 0x20 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x20 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x20 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x20 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x28 "MSMC_SBNDCOH5,Starvation Bound for Coherent Port 5"
hexmask.quad.byte 0x28 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x28 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x28 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x28 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x30 "MSMC_SBNDCOH6,Starvation Bound for Coherent Port 6"
hexmask.quad.byte 0x30 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x30 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x30 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x30 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x38 "MSMC_SBNDCOH7,Starvation Bound for Coherent Port 7"
hexmask.quad.byte 0x38 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x38 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x38 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x38 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x40 "MSMC_SBNDCOH8,Starvation Bound for Coherent Port 8"
hexmask.quad.byte 0x40 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x40 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x40 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x40 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x48 "MSMC_SBNDCOH9,Starvation Bound for Coherent Port 9"
hexmask.quad.byte 0x48 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x48 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x48 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x48 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
line.quad 0x50 "MSMC_SBNDCOH10,Starvation Bound for Coherent Port 10"
hexmask.quad.byte 0x50 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x50 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x50 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x50 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6100++0x07
line.quad 0x00 "MSMC_SBNDDRU,Starvation Bound for Data Routing Unit"
hexmask.quad.byte 0x00 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x00 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x6200++0x07
line.quad 0x00 "MSMC_SBNDRESP,Starvation Bound for Read Response"
hexmask.quad.byte 0x00 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
hexmask.quad.byte 0x00 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
group.quad 0x7000++0x07
line.quad 0x00 "MSMC_DBGTAGCTL,Debug Tag View Control"
bitfld.quad 0x00 40. "L3CACHE,Level 3 Cache Tag Select" "0,1"
bitfld.quad 0x00 32.--33. "BANK,Physical Bank Select" "0,1,2,3"
hexmask.quad.word 0x00 16.--29. 1. "INDEX,Index Select"
bitfld.quad 0x00 0.--4. "WAY,Way Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.quad 0x7080++0x07
line.quad 0x00 "MSMC_DBGTAGVIEW,Debug Tag View"
bitfld.quad 0x00 54.--58. "SF,Snoop Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 52. "DIRTY,Dirty" "0,1"
bitfld.quad 0x00 50. "DATA_VALID,Data Valid" "0,1"
bitfld.quad 0x00 48. "ADDR_VALID,Address Valid" "0,1"
hexmask.quad 0x00 0.--47. 1. "ADDRESS,Tag Address"
rgroup.quad 0xA000++0x0F
line.quad 0x00 "MSMC_NULL_SLV_STAT0,Null Slave Status 0"
line.quad 0x08 "MSMC_NULL_SLV_STAT1,Null Slave Status 1"
bitfld.quad 0x08 52.--53. "PRIV,Privilege" "0,1,2,3"
bitfld.quad 0x08 48. "SECURE,Secure" "0,1"
bitfld.quad 0x08 44. "EMU,Emulation" "0,1"
bitfld.quad 0x08 40.--41. "MEMTYPE,Memory Type" "0,1,2,3"
bitfld.quad 0x08 32.--37. "OPCODE,Opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.quad.byte 0x08 24.--31. 1. "PRIVID,Priv ID"
hexmask.quad.word 0x08 12.--23. 1. "ROUTEID,Route ID"
hexmask.quad.word 0x08 0.--9. 1. "BYTECNT,Byte Count"
group.quad 0xA018++0x07
line.quad 0x00 "MSMC_NULL_SLV_CNT,Null Slave Error Count"
hexmask.quad.byte 0x00 0.--7. 1. "COUNT,Count"
repeat 2. (list 11. 12. )(list 0x00 0x08 )
group.quad ($2+0x6058)++0x07
line.quad 0x00 "MSMC_SBNDCOH$1,Starvation Bound for Coherent Port 11"
hexmask.quad.byte 0x00 48.--55. 1. "SBNDE_RT,Starvation Bound for Real-Time External Memory"
hexmask.quad.byte 0x00 32.--39. 1. "SBNDM_RT,Starvation Bound for Real-Time On-Chip Memory"
newline
hexmask.quad.byte 0x00 16.--23. 1. "SBNDE_NRT,Starvation Bound for Non-Real-Time External Memory"
hexmask.quad.byte 0x00 0.--7. 1. "SBNDM_NRT,Starvation Bound for Non-Real-Time On-Chip Memory"
repeat.end
tree.end
tree.end
tree "NAVSS0_CFG"
tree "NAVSS0_CFG"
base ad:0x310C0000
rgroup.long 0x00++0x03
line.long 0x00 "NAVSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "NAVSS0_CPTS"
tree "NAVSS0_CPTS"
base ad:0x310D0000
rgroup.long 0x00++0x5B
line.long 0x00 "CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select0000 - TS_SYNC disabled 0001" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 16. "TS_RX_NO_EVENT,Timestamp Ethernet Receive produces no events 0 - Ethernet receive timesync events enabled 1 - Ethernet receive timesync events disabled" "0,1"
bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
newline
bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
newline
bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
bitfld.long 0x04 7. "TS_PPM_DIR,Timestamp PPM Direction0 - Increase the time_stamp[63:0] value by the PPM value 1 - Decrease the time_stamp[63:0] value by the PPM value" "0,1"
bitfld.long 0x04 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "TS_COMP is in non-toggle mode,TS_COMP is in toggle mode"
newline
bitfld.long 0x04 5. "MODE,Timestamp mode 0 - The timestamp is 32-bits with the upper 32-bits forced to zero" "0,1"
bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable0 - The timestamp value increments with the selected RFTCLK" "0,1"
bitfld.long 0x04 3. "TSTAMP_EN,Host Receive Timestamp Enable0 - Timestamps are disabled on received packets to host 1 - Timestamps enabled on received packets to host (cpts_en must be set)" "0,1"
bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP polarity0 - TS_COMP is asserted low 1 - TS_COMP is asserted high" "0,1"
newline
bitfld.long 0x04 1. "INT_TEST,Interrupt testWhen set this bit allows the raw interrupt to be written to facilitate interrupt test" "0,1"
bitfld.long 0x04 0. "CPTS_EN,Time sync enableWhen disabled (cleared to zero) the RCLK domain is held in reset" "0,1"
line.long 0x08 "CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event pushWhen a logic high is written to this bit a time stamp event is pushed onto the event FIFO" "0,1"
line.long 0x10 "CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x14 "CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x14 0. "TS_LOAD_EN,Time stamp load enableWriting a one to this bit enables the time stamp value to be written with the value in ts_load[63:0]" "0,1"
line.long 0x18 "CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x1C "CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x20 "CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)Writable when int_test = 1" "0,1"
line.long 0x24 "CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x28 "CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x2C "CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x2C 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amountOnly a single high or low time is adjusted and the ts_comp_nudge value is cleared to zero when the nudge has occurred"
line.long 0x30 "CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x30 0. "EVENT_POP,Event popWhen a logic high is written to this bit an event is popped off the event FIFO" "0,1"
line.long 0x34 "CPTS_EVENT_0_REG,Event 0 Register"
line.long 0x38 "CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x38 29. "PREMPT_QUEUE,Prempt QUEUE0 - The packet was received/transmitted on the express queue" "0,1"
bitfld.long 0x38 24.--28. "PORT_NUMBER,Port numberindicates the port number (encoded) of an Ethernet event or the encoded hardware timestamp number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 20.--23. "EVENT_TYPE,Event type0000 - Time Stamp Push Event 0001 - Time Stamp Rollover Event 0010 - Time Stamp Half Rollover Event 0011 - Hardware Time Stamp Push Event 0100 - Ethernet Receive Event 0101 - Ethernet Transmit Event 0110 - Time Stamp Compare Event.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message typeThe message type value that was contained in an Ethernet transmit or receive time sync packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence IDThe 16-bit sequence id is the value that was contained in an Ethernet transmit or receive time sync packet"
line.long 0x3C "CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,DomainThe 8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet"
line.long 0x40 "CPTS_EVENT_3_REG,Event 3 Register"
line.long 0x44 "CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x48 "CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x4C "CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x4C 0.--2. "ADD_VAL,Add ValueAdd Value is added to 1 to comprise the timestamp increment value" "0,1,2,3,4,5,6,7"
line.long 0x50 "CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x54 "CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x54 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High valueThis value should be written first (before the low value is written)"
line.long 0x58 "CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x58 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge valueThis two's complement number is added to the time_stamp[63:0] value to increase or decrease the timestamp value by the ts_nudge amount"
group.long 0xE0++0x1B
line.long 0x00 "CPTS_TS_GENF_COMP_LOW_REG_j,Time Stamp Generate Function Comparison Low Value Offset = E0h + (j * 20h); where j = 0h to 5h"
line.long 0x04 "CPTS_TS_GENF_COMP_HIGH_REG_j,Time Stamp Generate Function Comparison high Value Offset = E4h + (j * 20h); where j = 0h to 5h"
line.long 0x08 "CPTS_TS_GENF_CONTROL_REG_j,Time Stamp Generate Function Control Offset = E8h + (j * 20h); where j = 0h to 5h"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert0 - The output TS_GENFn signal asserts high 1 - The output TS_GENFn signal asserts low" "0,1"
bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function PPM Direction0 - A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount" "0,1"
line.long 0x0C "CPTS_TS_GENF_LENGTH_REG_j,Time Stamp Generate Function Length Value Offset = ECh + (j * 20h); where j = 0h to 5h"
line.long 0x10 "CPTS_TS_GENF_PPM_LOW_REG_j,Time Stamp Generate Function PPM Low Value Offset = F0h + (j * 20h); where j = 0h to 5h"
line.long 0x14 "CPTS_TS_GENF_PPM_HIGH_REG_j,Time Stamp Generate Function PPM High Value Offset = F4h + (j * 20h); where j = 0h to 5h"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High ValueThis value should be written first (before the low value is written)"
line.long 0x18 "CPTS_TS_GENF_NUDGE_REG_j,Time Stamp Generate Function Nudge Value Offset = F8h + (j * 20h); where j = 0h to 5h"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge ValueThis two's complement number is added to the generate counter value to increase or decrease the length by the ts_genfN_nudge amount"
group.long 0x200++0x1B
line.long 0x00 "CPTS_TS_ESTF_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
line.long 0x04 "CPTS_TS_ESTF_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
line.long 0x08 "CPTS_TS_ESTF_CONTROL_REG,Time Stamp ESTF Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert 0 - The output TS_ESTFn signal asserts low 1 - The output TS_ESTFn signal asserts high" "0,1"
bitfld.long 0x08 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction 0 - A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount" "0,1"
line.long 0x0C "CPTS_TS_ESTF_LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
line.long 0x10 "CPTS_TS_ESTF_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
line.long 0x14 "CPTS_TS_ESTF_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High ValueThis value should be written first (before the low value is written)"
line.long 0x18 "CPTS_TS_ESTF_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge ValueThis two's complement number is added to the generate counter value to increase or decrease the length by the ts_estfN_nudge amount"
tree.end
tree.end
tree "NAVSS0_MCRC"
tree "MCU_NAVSS0_MCRC"
base ad:0x2A264000
group.long 0x00++0x03
line.long 0x00 "MCRC_CRC_CTRL0,CRC Global Control Register 0"
bitfld.long 0x00 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "MCRC_CRC_CTRL1,CRC Global Control Register 1"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "MCRC_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1"
bitfld.long 0x00 24.--25. "CH4_MODE,Channel 4 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode For all four channels the seed.."
newline
bitfld.long 0x00 16.--17. "CH3_MODE,Channel 3 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode"
newline
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode"
newline
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode" "Data Trace disable,Data Trace enable"
newline
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode"
group.long 0x18++0x03
line.long 0x00 "MCRC_CRC_INTS,CRC Interrupt Enable Set Register"
bitfld.long 0x00 28. "CH4_TIME_OUT_ENS,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 12. "CH2_TIME_OUT_ENS,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 4. "CH1_TIME_OUT_ENS,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
group.long 0x20++0x03
line.long 0x00 "MCRC_CRC_INTR,CRC Interrupt Enable Reset Register"
bitfld.long 0x00 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 20. "CH3_TIME_OUT_ENR,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 12. "CH2_TIME_OUT_ENR,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 4. "CH1_TIME_OUT_ENR,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
group.long 0x28++0x03
line.long 0x00 "MCRC_CRC_STATUS,CRC Interrupt Status Register"
bitfld.long 0x00 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
rgroup.long 0x30++0x03
line.long 0x00 "MCRC_CRC_INT_OFFSET_REG,CRC Interrupt Offset"
hexmask.long.byte 0x00 0.--7. 1. "CRC,Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "MCRC_CRC_BUSY,CRC Busy Register"
bitfld.long 0x00 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
group.long 0x40++0x13
line.long 0x00 "MCRC_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "MCRC_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "MCRC_CRC_CURSEC_REG1,CRC Current Sector Register 1"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "MCRC_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "MCRC_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register"
group.long 0x60++0x33
line.long 0x00 "MCRC_PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL1,Channel 1 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH1,Channel 1 Raw Data High Register"
line.long 0x20 "MCRC_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed"
line.long 0x24 "MCRC_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "MCRC_CRC_CURSEC_REG2,CRC Current Sector Register 2"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "MCRC_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "MCRC_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register"
group.long 0xA0++0x33
line.long 0x00 "MCRC_PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL2,Channel 2 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH2,Channel 2 Raw Data High Register"
line.long 0x20 "MCRC_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register"
line.long 0x24 "MCRC_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register"
line.long 0x28 "MCRC_CRC_CURSEC_REG3,CRC Current Sector Register 3"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register"
line.long 0x2C "MCRC_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register"
line.long 0x30 "MCRC_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register"
group.long 0xE0++0x33
line.long 0x00 "MCRC_PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL3,Channel 3 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH3,Channel 3 Raw Data High Register"
line.long 0x20 "MCRC_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register"
line.long 0x24 "MCRC_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register"
line.long 0x28 "MCRC_CRC_CURSEC_REG4,CRC Current Sector Register 4"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails"
line.long 0x2C "MCRC_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns"
line.long 0x30 "MCRC_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated"
group.long 0x120++0x23
line.long 0x00 "MCRC_PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL4,Channel 4 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH4,Channel 4 Raw Data High Register"
line.long 0x20 "MCRC_BUS_SEL,Data bus tracing selection"
bitfld.long 0x20 2. "MEN,Enable/disables the tracing of VBUSM" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTC_MEN,Enable/disables the tracing of data TCM" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
newline
bitfld.long 0x20 0. "ITC_MEN,Enable/disables the tracing of instruction TCM" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled Please.."
group.long 0x200++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG1_CPY_Y,Channel 1 PSA signature block region Offset = 200h + (y * 4h); where y = 0h to 1Fh"
group.long 0x280++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG2_CPY_Y,Channel 2 PSA signature block region Offset = 280h + (y * 4h); where y = 0h to 1Fh"
group.long 0x300++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG3_CPY_Y,Channel 3 PSA signature block region Offset = 300h + (y * 4h); where y = 0h to 1Fh"
group.long 0x380++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG4_CPY_Y,Channel 4 PSA signature block region Offset = 380h + (y * 4h); where y = 0h to 1Fh"
tree.end
tree "NAVSS0_MCRC"
base ad:0x31F70000
group.long 0x00++0x03
line.long 0x00 "MCRC_CRC_CTRL0,CRC Global Control Register 0"
bitfld.long 0x00 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "MCRC_CRC_CTRL1,CRC Global Control Register 1"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "MCRC_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1"
bitfld.long 0x00 24.--25. "CH4_MODE,Channel 4 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode For all four channels the seed.."
newline
bitfld.long 0x00 16.--17. "CH3_MODE,Channel 3 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode"
newline
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode"
newline
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode" "Data Trace disable,Data Trace enable"
newline
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode" "Data Capture mode,AUTO mode,?,Full-CPU mode"
group.long 0x18++0x03
line.long 0x00 "MCRC_CRC_INTS,CRC Interrupt Enable Set Register"
bitfld.long 0x00 28. "CH4_TIME_OUT_ENS,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 12. "CH2_TIME_OUT_ENS,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 4. "CH1_TIME_OUT_ENS,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
group.long 0x20++0x03
line.long 0x00 "MCRC_CRC_INTR,CRC Interrupt Enable Reset Register"
bitfld.long 0x00 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 20. "CH3_TIME_OUT_ENR,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 12. "CH2_TIME_OUT_ENR,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 4. "CH1_TIME_OUT_ENR,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
group.long 0x28++0x03
line.long 0x00 "MCRC_CRC_STATUS,CRC Interrupt Status Register"
bitfld.long 0x00 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
rgroup.long 0x30++0x03
line.long 0x00 "MCRC_CRC_INT_OFFSET_REG,CRC Interrupt Offset"
hexmask.long.byte 0x00 0.--7. 1. "CRC,Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "MCRC_CRC_BUSY,CRC Busy Register"
bitfld.long 0x00 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
group.long 0x40++0x13
line.long 0x00 "MCRC_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "MCRC_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "MCRC_CRC_CURSEC_REG1,CRC Current Sector Register 1"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "MCRC_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "MCRC_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register"
group.long 0x60++0x33
line.long 0x00 "MCRC_PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL1,Channel 1 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH1,Channel 1 Raw Data High Register"
line.long 0x20 "MCRC_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed"
line.long 0x24 "MCRC_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "MCRC_CRC_CURSEC_REG2,CRC Current Sector Register 2"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "MCRC_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "MCRC_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register"
group.long 0xA0++0x33
line.long 0x00 "MCRC_PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL2,Channel 2 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH2,Channel 2 Raw Data High Register"
line.long 0x20 "MCRC_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register"
line.long 0x24 "MCRC_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register"
line.long 0x28 "MCRC_CRC_CURSEC_REG3,CRC Current Sector Register 3"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register"
line.long 0x2C "MCRC_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register"
line.long 0x30 "MCRC_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register"
group.long 0xE0++0x33
line.long 0x00 "MCRC_PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL3,Channel 3 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH3,Channel 3 Raw Data High Register"
line.long 0x20 "MCRC_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register"
line.long 0x24 "MCRC_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register"
line.long 0x28 "MCRC_CRC_CURSEC_REG4,CRC Current Sector Register 4"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails"
line.long 0x2C "MCRC_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns"
line.long 0x30 "MCRC_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated"
group.long 0x120++0x23
line.long 0x00 "MCRC_PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "MCRC_PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "MCRC_CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "MCRC_CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "MCRC_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register"
line.long 0x14 "MCRC_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register"
line.long 0x18 "MCRC_RAW_DATAREGL4,Channel 4 Raw Data Low Register"
line.long 0x1C "MCRC_RAW_DATAREGH4,Channel 4 Raw Data High Register"
line.long 0x20 "MCRC_BUS_SEL,Data bus tracing selection"
bitfld.long 0x20 2. "MEN,Enable/disables the tracing of VBUSM" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTC_MEN,Enable/disables the tracing of data TCM" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
newline
bitfld.long 0x20 0. "ITC_MEN,Enable/disables the tracing of instruction TCM" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled Please.."
group.long 0x200++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG1_CPY_Y,Channel 1 PSA signature block region Offset = 200h + (y * 4h); where y = 0h to 1Fh"
group.long 0x280++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG2_CPY_Y,Channel 2 PSA signature block region Offset = 280h + (y * 4h); where y = 0h to 1Fh"
group.long 0x300++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG3_CPY_Y,Channel 3 PSA signature block region Offset = 300h + (y * 4h); where y = 0h to 1Fh"
group.long 0x380++0x03
line.long 0x00 "MCRC_I0_PSA_SIGREG4_CPY_Y,Channel 4 PSA signature block region Offset = 380h + (y * 4h); where y = 0h to 1Fh"
tree.end
tree.end
tree "NAVSS0_NBSS_CFG_REGS0_MMRS"
tree "NAVSS0_NBSS_CFG_REGS0_MMRS"
base ad:0x3800000
rgroup.long 0x00++0x03
line.long 0x00 "NBSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG"
tree "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG"
base ad:0x3820000
group.long 0x00++0x03
line.long 0x00 "NB_MEMATTR64K_Y,The Memory Attribute register contains the attributes for all the 64K mapped regions"
bitfld.long 0x00 6.--7. "MEMTYPE,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "SDOMAIN,Defines the shareability domain of the memory" "0,1,2,3"
bitfld.long 0x00 2.--3. "OUTER,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "INNER,Defines the inner allocatability of the memory" "0,1,2,3"
tree.end
tree.end
tree "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG"
tree "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG"
base ad:0x3828000
group.long 0x00++0x03
line.long 0x00 "NB_MEMATTR64K_Y,The Memory Attribute register contains the attributes for all the 64K mapped regions"
bitfld.long 0x00 6.--7. "MEMTYPE,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "SDOMAIN,Defines the shareability domain of the memory" "0,1,2,3"
bitfld.long 0x00 2.--3. "OUTER,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "INNER,Defines the inner allocatability of the memory" "0,1,2,3"
tree.end
tree.end
tree "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG"
tree "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG"
base ad:0x3840000
group.long 0x00++0x03
line.long 0x00 "NB_MEMATTR16M0_Y,The Memory Attribute register contains the attributes for all the first 16M mapped regions"
bitfld.long 0x00 6.--7. "MEMTYPE,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "SDOMAIN,Defines the shareability domain of the memory" "0,1,2,3"
bitfld.long 0x00 2.--3. "OUTER,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "INNER,Defines the inner allocatability of the memory" "0,1,2,3"
group.long 0x200++0x03
line.long 0x00 "NB_MEMATTR16M1_Y,The Memory Attribute register contains the attributes for all the second 16M mapped regions"
bitfld.long 0x00 6.--7. "MEMTYPE,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "SDOMAIN,Defines the shareability domain of the memory" "0,1,2,3"
bitfld.long 0x00 2.--3. "OUTER,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "INNER,Defines the inner allocatability of the memory" "0,1,2,3"
tree.end
tree.end
tree "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG"
tree "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG"
base ad:0x3850000
group.long 0x00++0x03
line.long 0x00 "NB_MEMATTR16M0_Y,The Memory Attribute register contains the attributes for all the first 16M mapped regions"
bitfld.long 0x00 6.--7. "MEMTYPE,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "SDOMAIN,Defines the shareability domain of the memory" "0,1,2,3"
bitfld.long 0x00 2.--3. "OUTER,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "INNER,Defines the inner allocatability of the memory" "0,1,2,3"
group.long 0x200++0x03
line.long 0x00 "NB_MEMATTR16M1_Y,The Memory Attribute register contains the attributes for all the second 16M mapped regions"
bitfld.long 0x00 6.--7. "MEMTYPE,Defines the type of the memory" "0,1,2,3"
bitfld.long 0x00 4.--5. "SDOMAIN,Defines the shareability domain of the memory" "0,1,2,3"
bitfld.long 0x00 2.--3. "OUTER,Defines the outer allocatability of the memory" "0,1,2,3"
bitfld.long 0x00 0.--1. "INNER,Defines the inner allocatability of the memory" "0,1,2,3"
tree.end
tree.end
tree "NAVSS0_NBSS_NB_CFG_MMRS"
tree "NAVSS0_NBSS_NB0_CFG_MMRS"
base ad:0x3802000
rgroup.long 0x00++0x03
line.long 0x00 "NB_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "NB_THREADMAP,The Thread Map Register defines the VBUSM.C thread for each VBUSM source"
bitfld.long 0x00 0.--1. "THREADMAP,Thread map each bit is for each VBUSM source" "VBUSM.C thread 0 (non-real time traffic),VBUSM.C thread 2 (real-time traffic),?..."
tree.end
tree "NAVSS0_NBSS_NB1_CFG_MMRS"
base ad:0x3803000
rgroup.long 0x00++0x03
line.long 0x00 "NB_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "NB_THREADMAP,The Thread Map Register defines the VBUSM.C thread for each VBUSM source"
bitfld.long 0x00 0.--1. "THREADMAP,Thread map each bit is for each VBUSM source" "VBUSM.C thread 0 (non-real time traffic),VBUSM.C thread 2 (real-time traffic),?..."
tree.end
tree.end
tree "NAVSS0_PROXY0_BUF_CFG"
tree "MCU_NAVSS0_PROXY0_BUF_CFG"
base ad:0x2A580000
group.long 0x00++0x03
line.long 0x00 "PROXY_EVT_REG_j,The Proxy Event for the proxy Offset = 0h + (j * 1000h); where j = 0h to 3Fh"
hexmask.long.word 0x00 0.--15. 1. "ERR_EVENT,Proxy Error Event"
tree.end
tree "NAVSS0_PROXY0_BUF_CFG"
base ad:0x33400000
group.long 0x00++0x03
line.long 0x00 "PROXY_EVT_REG_j,The Proxy Event for the proxy Offset = 0h + (j * 1000h); where j = 0h to 3Fh"
hexmask.long.word 0x00 0.--15. 1. "ERR_EVENT,Proxy Error Event"
tree.end
tree.end
tree "NAVSS0_PROXY0_CFG_BUF_CFG"
tree "MCU_NAVSS0_PROXY_CFG_GCFG"
base ad:0x28590000
rgroup.long 0x00++0x07
line.long 0x00 "PROXY_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PROXY_CONFIG,The Config Register shows configured params"
hexmask.long.word 0x04 0.--15. 1. "THREADS,Number of proxy threads supported"
tree.end
tree "NAVSS0_PROXY0_CFG_BUF_CFG"
base ad:0x31120000
rgroup.long 0x00++0x07
line.long 0x00 "PROXY_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PROXY_CONFIG,The Config Register shows configured params"
hexmask.long.word 0x04 0.--15. 1. "THREADS,Number of proxy threads supported"
tree.end
tree.end
tree "NAVSS0_PROXY_BUF"
tree "MCU_NAVSS0_PROXY_CFG_BUF"
base ad:0x285A0000
group.long 0x00++0x03
line.long 0x00 "PROXY_DATA_y,The Proxy Buffer for the proxy Offset = 0h + (y * 4h); where y = 0h to FFFh"
tree.end
tree "NAVSS0_PROXY_BUF"
base ad:0x31130000
group.long 0x00++0x03
line.long 0x00 "PROXY_DATA_y,The Proxy Buffer for the proxy Offset = 0h + (y * 4h); where y = 0h to FFFh"
tree.end
tree.end
tree "NAVSS0_PROXY_TARGET0_DATA"
tree "MCU_NAVSS0_PROXY0_TARGET0_DATA"
base ad:0x2A500000
group.long 0x00++0x07
line.long 0x00 "PROXY_CTL_j,The Proxy Control for the proxy"
bitfld.long 0x00 24.--26. "ELSIZE,Queue element size" "4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes"
bitfld.long 0x00 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue" "access the head of the queue,access the tail of the queue,peek access the head of the queue,peek access the tail of the queue"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Proxy Queue"
line.long 0x04 "PROXY_STATUS_j,The Proxy Status for the proxy"
bitfld.long 0x04 31. "ERROR,Proxy Error status" "0,1"
group.long 0x200++0x03
line.long 0x00 "PROXY_DATA_j_y,The Proxy Data for the proxy. target and channel Offset = 200h + (j * 1000h) + (y * 4h); where j = 0h to 3Fh. y = 0h to 7Fh"
tree.end
tree "NAVSS0_PROXY_TARGET0_DATA"
base ad:0x33000000
group.long 0x00++0x07
line.long 0x00 "PROXY_CTL_j,The Proxy Control for the proxy"
bitfld.long 0x00 24.--26. "ELSIZE,Queue element size" "4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes"
bitfld.long 0x00 16.--17. "MODE,Proxy Queue Mode that determines how to access the queue" "access the head of the queue,access the tail of the queue,peek access the head of the queue,peek access the tail of the queue"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Proxy Queue"
line.long 0x04 "PROXY_STATUS_j,The Proxy Status for the proxy"
bitfld.long 0x04 31. "ERROR,Proxy Error status" "0,1"
group.long 0x200++0x03
line.long 0x00 "PROXY_DATA_j_y,The Proxy Data for the proxy. target and channel Offset = 200h + (j * 1000h) + (y * 4h); where j = 0h to 3Fh. y = 0h to 7Fh"
tree.end
tree.end
tree "NAVSS0_PVU_CFG_TLBIF"
tree "NAVSS0_DMA_PVU1_CFG_TLBIF"
base ad:0x360C0000
group.long 0x00++0x03
line.long 0x00 "PVU_CHAIN_j,The TLB chain points to another TLB"
bitfld.long 0x00 31. "EN,Enable for the TLB" "disable TLB,enable TLB"
bitfld.long 0x00 30. "LOG_DIS,Disable Fault Logging for the TLB" "enable fault logging,disable fault logging"
newline
bitfld.long 0x00 29. "FAULT,A fault has been detected from this TLB that could not be logged" "0,1"
hexmask.long.word 0x00 0.--11. 1. "CHAIN,Chain to another TLB"
group.long 0x20++0x0B
line.long 0x00 "PVU_ENTRY0_j_k,The TLB Entry"
line.long 0x04 "PVU_ENTRY1_j_k,The TLB Entry"
hexmask.long.word 0x04 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32.The address must be aligned to the page size"
line.long 0x08 "PVU_ENTRY2_j_k,The TLB Entry"
bitfld.long 0x08 30.--31. "MODE,Entry mode" "invalid,reserved - do..,valid,reserved - do.."
bitfld.long 0x08 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU0 is in secure mode" "Secure Transactions are not affected,Secure Transactions that match the entry is.."
newline
bitfld.long 0x08 21. "PSECURE,LPAE Field for Secure Page" "0,1"
bitfld.long 0x08 16.--19. "PSIZE,LPAE Field for Page Size" "4K,16K,64K,2M,32M,512M,1G,16G,?..."
newline
bitfld.long 0x08 10.--15. "PPERM,LPAE Field for Page Permissions" "enable user read access UR,enable user write access UW,enable user execute access UX,enable supervisor read access SR,enable supervisor write access SW,enable supervisor execute access SX,?..."
bitfld.long 0x08 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type" "device,write back,write through,?..."
newline
bitfld.long 0x08 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1"
bitfld.long 0x08 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1"
newline
bitfld.long 0x08 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1"
bitfld.long 0x08 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy" "no allocate,write allocate,read allocate,read and write allocate"
newline
bitfld.long 0x08 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy" "no allocate,write allocate,read allocate,read and write allocate"
group.long 0x30++0x0B
line.long 0x00 "PVU_ENTRY4_j_k,The TLB Entry"
line.long 0x04 "PVU_ENTRY5_j_k,The TLB Entry"
hexmask.long.word 0x04 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32.The address must be aligned to the page size"
line.long 0x08 "PVU_ENTRY6_j_k,The TLB Entry"
bitfld.long 0x08 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the ORDERID field" "bypass and use the orderid from the source..,use the ORDERID field value for the destination.."
bitfld.long 0x08 0.--3. "ORDERID,Defines the bus orderid value for this entry if hit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "NAVSS0_IO_PVU0_CFG_TLBIF"
base ad:0x36000000
group.long 0x00++0x03
line.long 0x00 "PVU_CHAIN_j,The TLB chain points to another TLB"
bitfld.long 0x00 31. "EN,Enable for the TLB" "disable TLB,enable TLB"
bitfld.long 0x00 30. "LOG_DIS,Disable Fault Logging for the TLB" "enable fault logging,disable fault logging"
newline
bitfld.long 0x00 29. "FAULT,A fault has been detected from this TLB that could not be logged" "0,1"
hexmask.long.word 0x00 0.--11. 1. "CHAIN,Chain to another TLB"
group.long 0x20++0x0B
line.long 0x00 "PVU_ENTRY0_j_k,The TLB Entry"
line.long 0x04 "PVU_ENTRY1_j_k,The TLB Entry"
hexmask.long.word 0x04 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32.The address must be aligned to the page size"
line.long 0x08 "PVU_ENTRY2_j_k,The TLB Entry"
bitfld.long 0x08 30.--31. "MODE,Entry mode" "invalid,reserved - do..,valid,reserved - do.."
bitfld.long 0x08 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU0 is in secure mode" "Secure Transactions are not affected,Secure Transactions that match the entry is.."
newline
bitfld.long 0x08 21. "PSECURE,LPAE Field for Secure Page" "0,1"
bitfld.long 0x08 16.--19. "PSIZE,LPAE Field for Page Size" "4K,16K,64K,2M,32M,512M,1G,16G,?..."
newline
bitfld.long 0x08 10.--15. "PPERM,LPAE Field for Page Permissions" "enable user read access UR,enable user write access UW,enable user execute access UX,enable supervisor read access SR,enable supervisor write access SW,enable supervisor execute access SX,?..."
bitfld.long 0x08 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type" "device,write back,write through,?..."
newline
bitfld.long 0x08 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1"
bitfld.long 0x08 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1"
newline
bitfld.long 0x08 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1"
bitfld.long 0x08 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy" "no allocate,write allocate,read allocate,read and write allocate"
newline
bitfld.long 0x08 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy" "no allocate,write allocate,read allocate,read and write allocate"
group.long 0x30++0x0B
line.long 0x00 "PVU_ENTRY4_j_k,The TLB Entry"
line.long 0x04 "PVU_ENTRY5_j_k,The TLB Entry"
hexmask.long.word 0x04 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32.The address must be aligned to the page size"
line.long 0x08 "PVU_ENTRY6_j_k,The TLB Entry"
bitfld.long 0x08 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the ORDERID field" "bypass and use the orderid from the source..,use the ORDERID field value for the destination.."
bitfld.long 0x08 0.--3. "ORDERID,Defines the bus orderid value for this entry if hit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "NAVSS0_IO_PVU1_CFG_TLBIF"
base ad:0x36040000
group.long 0x00++0x03
line.long 0x00 "PVU_CHAIN_j,The TLB chain points to another TLB"
bitfld.long 0x00 31. "EN,Enable for the TLB" "disable TLB,enable TLB"
bitfld.long 0x00 30. "LOG_DIS,Disable Fault Logging for the TLB" "enable fault logging,disable fault logging"
newline
bitfld.long 0x00 29. "FAULT,A fault has been detected from this TLB that could not be logged" "0,1"
hexmask.long.word 0x00 0.--11. 1. "CHAIN,Chain to another TLB"
group.long 0x20++0x0B
line.long 0x00 "PVU_ENTRY0_j_k,The TLB Entry"
line.long 0x04 "PVU_ENTRY1_j_k,The TLB Entry"
hexmask.long.word 0x04 0.--15. 1. "VBASE_H,Virtual Base Address bits 47 to 32.The address must be aligned to the page size"
line.long 0x08 "PVU_ENTRY2_j_k,The TLB Entry"
bitfld.long 0x08 30.--31. "MODE,Entry mode" "invalid,reserved - do..,valid,reserved - do.."
bitfld.long 0x08 29. "SEC_DEM,Enable Secure Transaction Demotion for the entry if the PVU0 is in secure mode" "Secure Transactions are not affected,Secure Transactions that match the entry is.."
newline
bitfld.long 0x08 21. "PSECURE,LPAE Field for Secure Page" "0,1"
bitfld.long 0x08 16.--19. "PSIZE,LPAE Field for Page Size" "4K,16K,64K,2M,32M,512M,1G,16G,?..."
newline
bitfld.long 0x08 10.--15. "PPERM,LPAE Field for Page Permissions" "enable user read access UR,enable user write access UW,enable user execute access UX,enable supervisor read access SR,enable supervisor write access SW,enable supervisor execute access SX,?..."
bitfld.long 0x08 8.--9. "PMEMTYPE,LPAE Field for Page Memory Type" "device,write back,write through,?..."
newline
bitfld.long 0x08 6. "PPREFETCH,LPAE Field for Page Prefetch allowed" "0,1"
bitfld.long 0x08 5. "PISABLE,LPAE Field for Page Inner Shareable allowed" "0,1"
newline
bitfld.long 0x08 4. "POSABLE,LPAE Field for Page Outer Shareable allowed" "0,1"
bitfld.long 0x08 2.--3. "PIALLOCPOL,LPAE Field for Page Inner Allocation Policy" "no allocate,write allocate,read allocate,read and write allocate"
newline
bitfld.long 0x08 0.--1. "POALLOCPOL,LPAE Field for Page Outer Allocation Policy" "no allocate,write allocate,read allocate,read and write allocate"
group.long 0x30++0x0B
line.long 0x00 "PVU_ENTRY4_j_k,The TLB Entry"
line.long 0x04 "PVU_ENTRY5_j_k,The TLB Entry"
hexmask.long.word 0x04 0.--15. 1. "PBASE_H,Physical Base Address bits 47 to 32.The address must be aligned to the page size"
line.long 0x08 "PVU_ENTRY6_j_k,The TLB Entry"
bitfld.long 0x08 4. "REPLACE,Indicates to replace the bus orderid value when matching this entry with the ORDERID field" "bypass and use the orderid from the source..,use the ORDERID field value for the destination.."
bitfld.long 0x08 0.--3. "ORDERID,Defines the bus orderid value for this entry if hit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "NAVSS0_SEC_PROXY0_CFG_MMRS"
tree "MCU_NAVSS0_SEC_PROXY0_CFG"
base ad:0x285B0000
rgroup.long 0x00++0x07
line.long 0x00 "SEC_PROXY_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SEC_PROXY_CONFIG,The Config Register shows configured params"
hexmask.long.word 0x04 16.--31. 1. "MSG_SIZE,Supported message size in bytes"
hexmask.long.word 0x04 0.--15. 1. "THREADS,Number of proxy threads supported"
tree.end
tree "NAVSS0_SEC_PROXY0_CFG_MMRS"
base ad:0x31140000
rgroup.long 0x00++0x07
line.long 0x00 "SEC_PROXY_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SEC_PROXY_CONFIG,The Config Register shows configured params"
hexmask.long.word 0x04 16.--31. 1. "MSG_SIZE,Supported message size in bytes"
hexmask.long.word 0x04 0.--15. 1. "THREADS,Number of proxy threads supported"
tree.end
tree.end
tree "NAVSS0_SEC_PROXY0_CFG_RT"
tree "MCU_NAVSS0_SEC_PROXY0_CFG_RT"
base ad:0x2A380000
group.long 0x00++0x07
line.long 0x00 "SEC_PROXY_STATUS_j,The Status Register gives status for proxy thread j"
bitfld.long 0x00 31. "ERROR,Error detected on proxy thread" "0,1"
rbitfld.long 0x00 30. "DIR,Direction for the proxy thread" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread"
hexmask.long.byte 0x00 0.--7. 1. "CUR_CNT,Current message count for the proxy thread"
line.long 0x04 "SEC_PROXY_THR_j,The Threshold Register controls the threshold for proxy thread j events"
hexmask.long.byte 0x04 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events"
tree.end
tree "NAVSS0_SEC_PROXY0_CFG_RT"
base ad:0x32400000
group.long 0x00++0x07
line.long 0x00 "SEC_PROXY_STATUS_j,The Status Register gives status for proxy thread j"
bitfld.long 0x00 31. "ERROR,Error detected on proxy thread" "0,1"
rbitfld.long 0x00 30. "DIR,Direction for the proxy thread" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread"
hexmask.long.byte 0x00 0.--7. 1. "CUR_CNT,Current message count for the proxy thread"
line.long 0x04 "SEC_PROXY_THR_j,The Threshold Register controls the threshold for proxy thread j events"
hexmask.long.byte 0x04 0.--7. 1. "THR_CNT,Threshold count that causes proxy thread events"
tree.end
tree.end
tree "NAVSS0_SEC_PROXY0_CFG_SCFG"
tree "MCU_NAVSS0_SEC_PROXY0_CFG_SCFG"
base ad:0x2A400000
group.long 0x00++0x13
line.long 0x00 "SEC_PROXY_BUFFER_L,The Buffer Register defines the pointer for the external buffer"
line.long 0x04 "SEC_PROXY_BUFFER_H,The Buffer Register defines the pointer for the external buffer"
hexmask.long.word 0x04 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits"
line.long 0x08 "SEC_PROXY_TARGET_L,The Target Register defines the pointer for the external target"
line.long 0x0C "SEC_PROXY_TARGET_H,The Target Register defines the pointer for the external target"
hexmask.long.word 0x0C 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits"
line.long 0x10 "SEC_PROXY_ORDERID,The Buffer OrderID Register contains the bus value for the buffer memory access"
bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus OrderID value for the buffer access with the ORDERID register field" "bypass and use the OrderID from the source..,use the ORDERID register field value for the.."
bitfld.long 0x10 0.--3. "ORDERID,Defines the bus OrderID value for the buffer access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1000++0x0B
line.long 0x00 "SEC_PROXY_CTL_j,The Control Register defines controls for proxy thread a"
bitfld.long 0x00 31. "DIR,Direction for the proxy thread" "outbound write only,inbound read only"
hexmask.long.byte 0x00 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread"
line.long 0x04 "SEC_PROXY_EVT_MAP_j,The Event Map Register defines the event numbers for proxy thread a"
hexmask.long.word 0x04 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread"
hexmask.long.word 0x04 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread"
line.long 0x08 "SEC_PROXY_DST_j,The Destination Register defines the destination proxy thread for outbound proxy thread a"
hexmask.long.word 0x08 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers"
tree.end
tree "NAVSS0_SEC_PROXY0_CFG_SCFG"
base ad:0x32800000
group.long 0x00++0x13
line.long 0x00 "SEC_PROXY_BUFFER_L,The Buffer Register defines the pointer for the external buffer"
line.long 0x04 "SEC_PROXY_BUFFER_H,The Buffer Register defines the pointer for the external buffer"
hexmask.long.word 0x04 0.--15. 1. "BASE_H,The base address for the external buffer upper 16 bits"
line.long 0x08 "SEC_PROXY_TARGET_L,The Target Register defines the pointer for the external target"
line.long 0x0C "SEC_PROXY_TARGET_H,The Target Register defines the pointer for the external target"
hexmask.long.word 0x0C 0.--15. 1. "BASE_H,The base address for the external target upper 16 bits"
line.long 0x10 "SEC_PROXY_ORDERID,The Buffer OrderID Register contains the bus value for the buffer memory access"
bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus OrderID value for the buffer access with the ORDERID register field" "bypass and use the OrderID from the source..,use the ORDERID register field value for the.."
bitfld.long 0x10 0.--3. "ORDERID,Defines the bus OrderID value for the buffer access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1000++0x0B
line.long 0x00 "SEC_PROXY_CTL_j,The Control Register defines controls for proxy thread a"
bitfld.long 0x00 31. "DIR,Direction for the proxy thread" "outbound write only,inbound read only"
hexmask.long.byte 0x00 16.--23. 1. "MAX_CNT,Max message count allowed for an outbound proxy thread"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue number in the target to use for the proxy thread"
line.long 0x04 "SEC_PROXY_EVT_MAP_j,The Event Map Register defines the event numbers for proxy thread a"
hexmask.long.word 0x04 16.--31. 1. "ERR_EVT,Event number for an error from the proxy thread"
hexmask.long.word 0x04 0.--15. 1. "THR_EVT,Event number for a threshold event from the proxy thread"
line.long 0x08 "SEC_PROXY_DST_j,The Destination Register defines the destination proxy thread for outbound proxy thread a"
hexmask.long.word 0x08 0.--15. 1. "THREAD,The proxy thread that is the destination of messages from this outbound proxy thread based on the queue numbers"
tree.end
tree.end
tree "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA"
tree "MCU_NAVSS0_SEC_PROXY0_TARGET_DATA"
base ad:0x2A480000
rgroup.long 0x00++0x07
line.long 0x00 "SEC_PROXY_DATA_j,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored"
hexmask.long.word 0x00 0.--9. 1. "SRC_THR,Proxy source thread of message"
line.long 0x04 "SEC_PROXY_MESSAGE_j_y,The Message Data for proxy thread a"
tree.end
tree "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA"
base ad:0x32C00000
rgroup.long 0x00++0x07
line.long 0x00 "SEC_PROXY_DATA_j,The Proxy Private register contains private information for the proxy thread a and should not be written. writes are ignored"
hexmask.long.word 0x00 0.--9. 1. "SRC_THR,Proxy source thread of message"
line.long 0x04 "SEC_PROXY_MESSAGE_j_y,The Message Data for proxy thread a"
tree.end
tree.end
tree "NAVSS0_UDMASS_RINGACC0_CFG"
tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG"
base ad:0x28440000
group.long 0x40++0x13
line.long 0x00 "RINGACC_BA_LO_J,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
line.long 0x04 "RINGACC_BA_HI_j,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
hexmask.long.word 0x04 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)"
line.long 0x08 "RINGACC_SIZE_j,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x08 30.--31. "QMODE,Defines the mode for this ring or queue" "exposed ring mode for SW direct access,messaging mode when all operations are through..,credentials mode is message mode plus stores..,QM mode where the elements include additional.."
bitfld.long 0x08 24.--26. "ELSIZE,Ring element size" "4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,RESERVED"
hexmask.long.tbyte 0x08 0.--19. 1. "ELCNT,Tx Ring element count"
line.long 0x0C "RINGACC_EVENT_j,The Ring Event Register contains the event number for the ring for when it is active or empty"
hexmask.long.word 0x0C 0.--15. 1. "EVENT,Defines the event for this ring or queue"
line.long 0x10 "RINGACC_ORDERID_j,The Ring OrderID Register contains the bus orderid value for the ring memory access"
bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field" "bypass and use the orderid from the source..,use the orderid MMR field value for the.."
bitfld.long 0x10 0.--3. "ORDERID,Defines the bus orderid value for this ring or queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "NAVSS0_UDMASS_RINGACC0_CFG"
base ad:0x31080000
group.long 0x40++0x13
line.long 0x00 "RINGACC_BA_LO_J,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
line.long 0x04 "RINGACC_BA_HI_j,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
hexmask.long.word 0x04 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)"
line.long 0x08 "RINGACC_SIZE_j,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x08 30.--31. "QMODE,Defines the mode for this ring or queue" "exposed ring mode for SW direct access,messaging mode when all operations are through..,credentials mode is message mode plus stores..,QM mode where the elements include additional.."
bitfld.long 0x08 24.--26. "ELSIZE,Ring element size" "4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,RESERVED"
hexmask.long.tbyte 0x08 0.--19. 1. "ELCNT,Tx Ring element count"
line.long 0x0C "RINGACC_EVENT_j,The Ring Event Register contains the event number for the ring for when it is active or empty"
hexmask.long.word 0x0C 0.--15. 1. "EVENT,Defines the event for this ring or queue"
line.long 0x10 "RINGACC_ORDERID_j,The Ring OrderID Register contains the bus orderid value for the ring memory access"
bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field" "bypass and use the orderid from the source..,use the orderid MMR field value for the.."
bitfld.long 0x10 0.--3. "ORDERID,Defines the bus orderid value for this ring or queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "NAVSS0_UDMASS_RINGACC0_CFG_MON"
tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON"
base ad:0x2A280000
group.long 0x00++0x0F
line.long 0x00 "RINGACC_CONTROL_j,Monitor Control Register Offset = 0h + (j * 1000h); where j = 0h to 1Fh"
hexmask.long.word 0x00 16.--31. 1. "EVT,Event to produce"
bitfld.long 0x00 8.--11. "SOURCE,Monitor source selection" "element count,head packet size (illegal for rings not in QM..,accumulated queue size (illegal for rings not in..,?..."
bitfld.long 0x00 0.--2. "MODE,Monitor Mode" "disabled,push/pop statistics capture,low/high threshold checks,low/high watermarking,starvation counting,?..."
line.long 0x04 "RINGACC_QUEUE_j,Monitor Queue Register Offset = 4h + (j * 1000h); where j = 0h to 1Fh"
hexmask.long.word 0x04 0.--15. 1. "VAL,Queue to monitor"
line.long 0x08 "RINGACC_DATA0_j,Monitor Data Register Offset = 8h + (j * 1000h); where j = 0h to 1Fh"
line.long 0x0C "RINGACC_DATA1_j,Monitor Data Register Offset = Ch + (j * 1000h); where j = 0h to 1Fh"
tree.end
tree "NAVSS0_UDMASS_RINGACC0_CFG_MON"
base ad:0x32000000
group.long 0x00++0x0F
line.long 0x00 "RINGACC_CONTROL_j,Monitor Control Register Offset = 0h + (j * 1000h); where j = 0h to 1Fh"
hexmask.long.word 0x00 16.--31. 1. "EVT,Event to produce"
bitfld.long 0x00 8.--11. "SOURCE,Monitor source selection" "element count,head packet size (illegal for rings not in QM..,accumulated queue size (illegal for rings not in..,?..."
bitfld.long 0x00 0.--2. "MODE,Monitor Mode" "disabled,push/pop statistics capture,low/high threshold checks,low/high watermarking,starvation counting,?..."
line.long 0x04 "RINGACC_QUEUE_j,Monitor Queue Register Offset = 4h + (j * 1000h); where j = 0h to 1Fh"
hexmask.long.word 0x04 0.--15. 1. "VAL,Queue to monitor"
line.long 0x08 "RINGACC_DATA0_j,Monitor Data Register Offset = 8h + (j * 1000h); where j = 0h to 1Fh"
line.long 0x0C "RINGACC_DATA1_j,Monitor Data Register Offset = Ch + (j * 1000h); where j = 0h to 1Fh"
tree.end
tree.end
tree "NAVSS0_UDMASS_RINGACC0_CFG_RT"
tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT"
base ad:0x2B800000
group.long 0x10++0x03
line.long 0x00 "RINGACC_DB_j,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
hexmask.long.byte 0x00 0.--7. 1. "CNT,Signed number of entries by which to increment the ring occupancy"
rgroup.long 0x18++0x0F
line.long 0x00 "RINGACC_OCC_j,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
hexmask.long.tbyte 0x00 0.--20. 1. "CNT,Total number of valid entries on the ring"
line.long 0x04 "RINGACC_INDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel"
hexmask.long.tbyte 0x04 0.--19. 1. "IDX,Current SW owned read index for the ring"
line.long 0x08 "RINGACC_HWOCC_j,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring"
hexmask.long.tbyte 0x08 0.--20. 1. "CNT,Total number of valid entries on the ring"
line.long 0x0C "RINGACC_HWINDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel"
hexmask.long.tbyte 0x0C 0.--19. 1. "IDX,Current HW owned read index for the ring"
tree.end
tree "NAVSS0_UDMASS_RINGACC0_CFG_RT"
base ad:0x3C000000
group.long 0x10++0x03
line.long 0x00 "RINGACC_DB_j,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
hexmask.long.byte 0x00 0.--7. 1. "CNT,Signed number of entries by which to increment the ring occupancy"
rgroup.long 0x18++0x0F
line.long 0x00 "RINGACC_OCC_j,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
hexmask.long.tbyte 0x00 0.--20. 1. "CNT,Total number of valid entries on the ring"
line.long 0x04 "RINGACC_INDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel"
hexmask.long.tbyte 0x04 0.--19. 1. "IDX,Current SW owned read index for the ring"
line.long 0x08 "RINGACC_HWOCC_j,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring"
hexmask.long.tbyte 0x08 0.--20. 1. "CNT,Total number of valid entries on the ring"
line.long 0x0C "RINGACC_HWINDX_j,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel"
hexmask.long.tbyte 0x0C 0.--19. 1. "IDX,Current HW owned read index for the ring"
tree.end
tree.end
tree "NAVSS0_UDMASS_RINGACC0_GCFG"
tree "MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG"
base ad:0x285D0000
rgroup.long 0x00++0x03
line.long 0x00 "RINGACC_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "RINGACC_TRACE_CTL,Trace Control Register"
bitfld.long 0x00 31. "EN,Trace enable" "disable,enable"
bitfld.long 0x00 30. "ALL_QUEUES,Trace everything" "only the selected queue,every queue"
bitfld.long 0x00 29. "MSG,Trace message data" "include only the operation,include message data"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue number when tracing a single queue"
group.long 0x20++0x03
line.long 0x00 "RINGACC_OVRFLOW,Overflow Queue Register"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue to send overflow messages.A value of 0xFFFF will disable the overflow function"
group.long 0x40++0x07
line.long 0x00 "RINGACC_ERROR_EVT,Error Event Register"
hexmask.long.word 0x00 0.--15. 1. "EVT,Event to send when detecting a bus error"
line.long 0x04 "RINGACC_ERROR_LOG,Error Log Register"
bitfld.long 0x04 31. "PUSH,Bus error was caused by a push" "pop,push"
hexmask.long.word 0x04 0.--15. 1. "QUEUE,Queue that received the bus error"
tree.end
tree "NAVSS0_UDMASS_RINGACC0_GCFG"
base ad:0x31160000
rgroup.long 0x00++0x03
line.long 0x00 "RINGACC_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "RINGACC_TRACE_CTL,Trace Control Register"
bitfld.long 0x00 31. "EN,Trace enable" "disable,enable"
bitfld.long 0x00 30. "ALL_QUEUES,Trace everything" "only the selected queue,every queue"
bitfld.long 0x00 29. "MSG,Trace message data" "include only the operation,include message data"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue number when tracing a single queue"
group.long 0x20++0x03
line.long 0x00 "RINGACC_OVRFLOW,Overflow Queue Register"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue to send overflow messages.A value of 0xFFFF will disable the overflow function"
group.long 0x40++0x07
line.long 0x00 "RINGACC_ERROR_EVT,Error Event Register"
hexmask.long.word 0x00 0.--15. 1. "EVT,Event to send when detecting a bus error"
line.long 0x04 "RINGACC_ERROR_LOG,Error Log Register"
bitfld.long 0x04 31. "PUSH,Bus error was caused by a push" "pop,push"
hexmask.long.word 0x04 0.--15. 1. "QUEUE,Queue that received the bus error"
tree.end
tree.end
tree "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS"
tree "MCU_NAVSS0_UDMASS_RINGACC0_FIFOS"
base ad:0x2B000000
group.long 0x00++0x03
line.long 0x00 "RINGACC_RINGHEADDATA_j_y,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head"
group.long 0x200++0x03
line.long 0x00 "RINGACC_RINGTAILDATA_j_y,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail"
group.long 0x400++0x03
line.long 0x00 "RINGACC_PEEKHEADDATA_j_y,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element"
group.long 0x600++0x03
line.long 0x00 "RINGACC_PEEKTAILDATA_j_y,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element"
tree.end
tree "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS"
base ad:0x38000000
group.long 0x00++0x03
line.long 0x00 "RINGACC_RINGHEADDATA_j_y,The Ring Head Entry Data Registers contain the data which is to be written or which was read from the ring head"
group.long 0x200++0x03
line.long 0x00 "RINGACC_RINGTAILDATA_j_y,The Ring Tail Entry Data Registers contain the data which is to be written or which was read from the ring tail"
group.long 0x400++0x03
line.long 0x00 "RINGACC_PEEKHEADDATA_j_y,The Ring Peek Head Entry Data Registers contain the data which is to be read from the ring head without removing the element"
group.long 0x600++0x03
line.long 0x00 "RINGACC_PEEKTAILDATA_j_y,The Ring Peek Tail Entry Data Registers contain the data which is to be read from the ring tail without removing the element"
tree.end
tree.end
tree "NAVSS_PVU_CFG"
tree "NAVSS0_DMA_PVU1_CFG"
base ad:0x30F83000
rgroup.long 0x00++0x07
line.long 0x00 "PVU_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PVU_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel"
hexmask.long.word 0x04 0.--15. 1. "TLBS,Number of TLBs"
group.long 0x10++0x0B
line.long 0x00 "PVU_ENABLE,The Enable Register enables the PVU0"
bitfld.long 0x00 0. "EN,PVU0 Enable bit" "disabled,enabled"
line.long 0x04 "PVU_VIRTID_MAP1,The Map Register 1 defines the virtid mapping for the PVU0"
bitfld.long 0x04 22.--23. "DMA_CL3,Map for DMA sub-class 3" "0,1,2,3"
bitfld.long 0x04 20.--21. "DMA_CL2,Map for DMA sub-class 2" "0,1,2,3"
newline
bitfld.long 0x04 18.--19. "DMA_CL1,Map for DMA sub-class 1" "0,1,2,3"
bitfld.long 0x04 16.--17. "DMA_CL0,Map for DMA sub-class 0" "0,1,2,3"
newline
hexmask.long.word 0x04 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes"
line.long 0x08 "PVU_VIRTID_MAP2,The Map Register 2 defines the virtid mapping for the PVU0"
hexmask.long.word 0x08 0.--11. 1. "MAX_CNT,VirtID maximum for PVU0"
group.long 0x30++0x03
line.long 0x00 "PVU_EXCEPTION_LOGGING_DISABLE,The Exception Logging Disable Register defines which types of faults are disabled for logging"
bitfld.long 0x00 6. "MISS_DIS,Disable for PVU0 miss fault logging" "enable miss fault logging,disable miss fault logging"
bitfld.long 0x00 5. "PREF_DIS,Disable for prefetch permissions fault logging" "enable prefetch fault logging,disable prefetch fault logging"
newline
bitfld.long 0x00 4. "EXEC_DIS,Disable for execute permissions fault logging" "enable execute fault logging,disable execute fault logging"
bitfld.long 0x00 3. "WRITE_DIS,Disable for write permissions fault logging" "enable write fault logging,disable write fault logging"
newline
bitfld.long 0x00 2. "READ_DIS,Disable for read permissions fault logging" "enable read fault logging,disable read fault logging"
bitfld.long 0x00 0. "VIRTID_DIS,Disable for virtID permission fault logging" "enable virtID fault logging,disable virtID fault logging"
group.long 0x104++0x03
line.long 0x00 "PVU_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x120++0x1B
line.long 0x00 "PVU_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PVU_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
newline
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PVU_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x00=PVU0 miss,0x01=Max virtid violation,0x02=reserved,0x03=read permission violation,0x04=write permission violation,0x05=execute permission violation,0x06=prefetch permission violation"
line.long 0x0C "PVU_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PVU_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits"
line.long 0x14 "PVU_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
newline
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
newline
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PVU_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x140++0x13
line.long 0x00 "PVU_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PVU_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PVU_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PVU_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PVU_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "NAVSS0_IO_PVU0_CFG"
base ad:0x30F80000
rgroup.long 0x00++0x07
line.long 0x00 "PVU_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PVU_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel"
hexmask.long.word 0x04 0.--15. 1. "TLBS,Number of TLBs"
group.long 0x10++0x0B
line.long 0x00 "PVU_ENABLE,The Enable Register enables the PVU0"
bitfld.long 0x00 0. "EN,PVU0 Enable bit" "disabled,enabled"
line.long 0x04 "PVU_VIRTID_MAP1,The Map Register 1 defines the virtid mapping for the PVU0"
bitfld.long 0x04 22.--23. "DMA_CL3,Map for DMA sub-class 3" "0,1,2,3"
bitfld.long 0x04 20.--21. "DMA_CL2,Map for DMA sub-class 2" "0,1,2,3"
newline
bitfld.long 0x04 18.--19. "DMA_CL1,Map for DMA sub-class 1" "0,1,2,3"
bitfld.long 0x04 16.--17. "DMA_CL0,Map for DMA sub-class 0" "0,1,2,3"
newline
hexmask.long.word 0x04 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes"
line.long 0x08 "PVU_VIRTID_MAP2,The Map Register 2 defines the virtid mapping for the PVU0"
hexmask.long.word 0x08 0.--11. 1. "MAX_CNT,VirtID maximum for PVU0"
group.long 0x30++0x03
line.long 0x00 "PVU_EXCEPTION_LOGGING_DISABLE,The Exception Logging Disable Register defines which types of faults are disabled for logging"
bitfld.long 0x00 6. "MISS_DIS,Disable for PVU0 miss fault logging" "enable miss fault logging,disable miss fault logging"
bitfld.long 0x00 5. "PREF_DIS,Disable for prefetch permissions fault logging" "enable prefetch fault logging,disable prefetch fault logging"
newline
bitfld.long 0x00 4. "EXEC_DIS,Disable for execute permissions fault logging" "enable execute fault logging,disable execute fault logging"
bitfld.long 0x00 3. "WRITE_DIS,Disable for write permissions fault logging" "enable write fault logging,disable write fault logging"
newline
bitfld.long 0x00 2. "READ_DIS,Disable for read permissions fault logging" "enable read fault logging,disable read fault logging"
bitfld.long 0x00 0. "VIRTID_DIS,Disable for virtID permission fault logging" "enable virtID fault logging,disable virtID fault logging"
group.long 0x104++0x03
line.long 0x00 "PVU_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x120++0x1B
line.long 0x00 "PVU_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PVU_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
newline
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PVU_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x00=PVU0 miss,0x01=Max virtid violation,0x02=reserved,0x03=read permission violation,0x04=write permission violation,0x05=execute permission violation,0x06=prefetch permission violation"
line.long 0x0C "PVU_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PVU_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits"
line.long 0x14 "PVU_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
newline
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
newline
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PVU_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x140++0x13
line.long 0x00 "PVU_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PVU_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PVU_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PVU_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PVU_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "NAVSS0_IO_PVU1_CFG"
base ad:0x30F81000
rgroup.long 0x00++0x07
line.long 0x00 "PVU_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PVU_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "TLB_ENTRIES,Number of TLB entries per channel"
hexmask.long.word 0x04 0.--15. 1. "TLBS,Number of TLBs"
group.long 0x10++0x0B
line.long 0x00 "PVU_ENABLE,The Enable Register enables the PVU0"
bitfld.long 0x00 0. "EN,PVU0 Enable bit" "disabled,enabled"
line.long 0x04 "PVU_VIRTID_MAP1,The Map Register 1 defines the virtid mapping for the PVU0"
bitfld.long 0x04 22.--23. "DMA_CL3,Map for DMA sub-class 3" "0,1,2,3"
bitfld.long 0x04 20.--21. "DMA_CL2,Map for DMA sub-class 2" "0,1,2,3"
newline
bitfld.long 0x04 18.--19. "DMA_CL1,Map for DMA sub-class 1" "0,1,2,3"
bitfld.long 0x04 16.--17. "DMA_CL0,Map for DMA sub-class 0" "0,1,2,3"
newline
hexmask.long.word 0x04 0.--11. 1. "DMA_CNT,VirtID count for DMA class that use sub-classes"
line.long 0x08 "PVU_VIRTID_MAP2,The Map Register 2 defines the virtid mapping for the PVU0"
hexmask.long.word 0x08 0.--11. 1. "MAX_CNT,VirtID maximum for PVU0"
group.long 0x30++0x03
line.long 0x00 "PVU_EXCEPTION_LOGGING_DISABLE,The Exception Logging Disable Register defines which types of faults are disabled for logging"
bitfld.long 0x00 6. "MISS_DIS,Disable for PVU0 miss fault logging" "enable miss fault logging,disable miss fault logging"
bitfld.long 0x00 5. "PREF_DIS,Disable for prefetch permissions fault logging" "enable prefetch fault logging,disable prefetch fault logging"
newline
bitfld.long 0x00 4. "EXEC_DIS,Disable for execute permissions fault logging" "enable execute fault logging,disable execute fault logging"
bitfld.long 0x00 3. "WRITE_DIS,Disable for write permissions fault logging" "enable write fault logging,disable write fault logging"
newline
bitfld.long 0x00 2. "READ_DIS,Disable for read permissions fault logging" "enable read fault logging,disable read fault logging"
bitfld.long 0x00 0. "VIRTID_DIS,Disable for virtID permission fault logging" "enable virtID fault logging,disable virtID fault logging"
group.long 0x104++0x03
line.long 0x00 "PVU_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x120++0x1B
line.long 0x00 "PVU_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PVU_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
newline
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PVU_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x00=PVU0 miss,0x01=Max virtid violation,0x02=reserved,0x03=read permission violation,0x04=write permission violation,0x05=execute permission violation,0x06=prefetch permission violation"
line.long 0x0C "PVU_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PVU_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Input virtual address upper 12 bits"
line.long 0x14 "PVU_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
newline
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
newline
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PVU_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x140++0x13
line.long 0x00 "PVU_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PVU_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PVU_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PVU_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PVU_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree.end
tree "Null_Error_Reporting"
tree "CBASS_AASRC0_ERR"
base ad:0x2A8E000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_AC0_ERR"
base ad:0x2A85000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_CSI0_ERR"
base ad:0x2A88000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_DATADEBUG0_ERR"
base ad:0x2A86000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_FW0_ERR"
base ad:0xB08000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_HC0_ERR"
base ad:0x2A87000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_HC2_0_ERR"
base ad:0x2A83000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_HC_CFG0_ERR"
base ad:0x2A89000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_INFRA0_ERR"
base ad:0xB00000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_IPPHY0_ERR"
base ad:0x2A8F000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_MCASP_G0_0_ERR"
base ad:0x2A8A000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_MCASP_G1_0_ERR"
base ad:0x2A8B000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_RC0_ERR"
base ad:0x2A8C000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "CBASS_RC_CFG0_ERR"
base ad:0x2A8D000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "MCU_CBASS_FW0_ERR"
base ad:0x47108000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree "WKUP_CBASS_FW0_ERR"
base ad:0x42404000
rgroup.long 0x00++0x07
line.long 0x00 "CBASS_PID,The Revision Register contains the major and minor revisions for the module"
line.long 0x04 "CBASS_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "CBASS_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "CBASS_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "CBASS_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "CBASS_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "CBASS_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "CBASS_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "CBASS_ERR_INTR_RAW_STAT,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "CBASS_ERR_INTR_ENABLED_STAT,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "CBASS_ERR_INTR_ENABLE_SET,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "CBASS_ERR_INTR_ENABLE_CLR,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "CBASS_EOI,End of Interrupt Register"
hexmask.long.word 0x10 0.--15. 1. "WR,End of Interrupt Register"
tree.end
tree.end
tree "OSPI"
tree "MCU_FSS0_OSPI0_CTRL"
base ad:0x47040000
group.long 0x00++0x47
line.long 0x00 "OSPI_CONFIG_REG,OSPI Configuration Register This register contains basic configuration fields of the controller"
rbitfld.long 0x00 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE" "0,1"
newline
bitfld.long 0x00 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit" "0,1"
newline
bitfld.long 0x00 29. "CRC_ENABLE_FLD,CRC enable bit" "0,1"
newline
rbitfld.long 0x00 26.--28. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable" "0,1"
newline
bitfld.long 0x00 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder" "Active slave is selected based on the..,Active slave is selected based on actual data.."
newline
bitfld.long 0x00 19.--22. "MSTR_BAUD_DIV_FLD,Master mode baud rate divisor (2 to 32) " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately.0h = If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value=1h = Operate the device in XIP mode immediately" "0,1"
newline
bitfld.long 0x00 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ.0h = If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction.1h = If XIP is disabled then setting to 1 will inform the controller that the device is ready.." "0,1"
newline
bitfld.long 0x00 16. "ENB_AHB_ADDR_REMAP_FLD,Enable Data Interface Address Remapping [Direct Access Mode Only]" "0,1"
newline
bitfld.long 0x00 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface" "0,1"
newline
bitfld.long 0x00 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin" "0,1"
newline
bitfld.long 0x00 10.--13. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines.If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0 ss[3:0] are output thus:else ss[3-0] directly drives N_SS_OUT[3-0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9. "PERIPH_SEL_DEC_FLD,Peripheral select" "0,1"
newline
bitfld.long 0x00 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode" "0,1"
newline
bitfld.long 0x00 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access" "0,1"
newline
bitfld.long 0x00 6. "RESET_CFG_FLD,RESET pin" "0,1"
newline
bitfld.long 0x00 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1"
newline
bitfld.long 0x00 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1"
newline
bitfld.long 0x00 3. "PHY_MODE_ENABLE_FLD,PHY mode enable" "0,1"
newline
bitfld.long 0x00 2. "SEL_CLK_PHASE_FLD,Select Clock Phase.Selects whether the clock is in an active or inactive phase outside the SPI word" "The SPI clock is active outside the word,The SPI clock is inactive outside the word"
newline
bitfld.long 0x00 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word.0h = The SPI clock is quiescent low" "0,1"
newline
bitfld.long 0x00 0. "ENB_SPI_FLD,OSPI" "0,1"
line.long 0x04 "OSPI_DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register"
rbitfld.long 0x04 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 24.--28. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x04 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable" "0,1"
newline
rbitfld.long 0x04 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3"
newline
bitfld.long 0x04 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only" "?,Used for Dual Input/Output instructions For data..,Used for Quad Input/Output instructions For data..,Used for Octal Input/Output instructions For.."
newline
rbitfld.long 0x04 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3"
newline
bitfld.long 0x04 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only" "?,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ[7:0]"
newline
rbitfld.long 0x04 11. "RD_INSTR_RESV1_FLD,Reserved" "0,1"
newline
bitfld.long 0x04 10. "DDR_EN_FLD,DDR Enable" "0,1"
newline
bitfld.long 0x04 8.--9. "INSTR_TYPE_FLD,Instruction Type.0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only]" "?,Use DIO-SPI mode [Instructions Address and Data..,Use QIO-SPI mode [Instructions Address and Data..,Use Octal-IO-SPI mode [Instructions Address and.."
newline
hexmask.long.byte 0x04 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode"
line.long 0x08 "OSPI_DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register"
rbitfld.long 0x08 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--28. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x08 18.--23. "WR_INSTR_RESV3_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only" "?,Used for Dual Input/Output instructions For data..,Used for Quad Input/Output instructions For data..,Used for Octal Input/Output instructions For.."
newline
rbitfld.long 0x08 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3"
newline
bitfld.long 0x08 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only" "?,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ[7:0]"
newline
rbitfld.long 0x08 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8. "WEL_DIS_FLD,WEL Disable" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "WR_OPCODE_FLD,Write Opcode"
line.long 0x0C "OSPI_DEV_DELAY_REG,OSPI Device Delay Register"
hexmask.long.byte 0x0C 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert"
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hexmask.long.byte 0x0C 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation"
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hexmask.long.byte 0x0C 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit"
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hexmask.long.byte 0x0C 0.--7. 1. "D_INIT_FLD,Clock Delay with N_SS_OUT"
line.long 0x10 "OSPI_RD_DATA_CAPTURE_REG,Read Data Capture Register"
hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved"
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bitfld.long 0x10 16.--19. "DDR_READ_DELAY_FLD,DDR read delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved"
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bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit" "0,1"
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rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection" "0,1"
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bitfld.long 0x10 1.--4. "DELAY_FLD,Read Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0. "BYPASS_FLD,Bypass" "0,1"
line.long 0x14 "OSPI_DEV_SIZE_CONFIG_REG,Device Size Configuration Register"
rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin:0h = size of 512Mb" "?,size of 1Gb2h = size of 2Gb,?,size of 4Gb"
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bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin:0h = size of" "?,?,size of 2Gb,size of 4Gb"
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bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin:0h = size of" "?,?,size of 2Gb,size of 4Gb"
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bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin:0h = size of" "?,?,size of 2Gb,size of 4Gb"
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bitfld.long 0x14 16.--20. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page"
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bitfld.long 0x14 0.--3. "NUM_ADDR_BYTES_FLD,Number of address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "OSPI_SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register"
hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved"
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hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size"
line.long 0x1C "OSPI_IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register"
line.long 0x20 "OSPI_DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register"
hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved"
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bitfld.long 0x20 8.--11. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 4.--7. "DMA_PERIPH_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "OSPI_REMAP_ADDR_REG,Remap Address Register"
line.long 0x28 "OSPI_MODE_BIT_CONFIG_REG,Mode Bit Configuration Register"
hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower]"
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hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper]"
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bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit" "0,1"
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rbitfld.long 0x28 11.--14. "MODE_BIT_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled"
line.long 0x2C "OSPI_SRAM_FILL_REG,SRAM Fill Register"
hexmask.long.word 0x2C 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]"
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hexmask.long.word 0x2C 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]"
line.long 0x30 "OSPI_TX_THRESH_REG,TX Threshold Register"
hexmask.long 0x30 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved"
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bitfld.long 0x30 0.--4. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "OSPI_RX_THRESH_REG,RX Threshold Register"
hexmask.long 0x34 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved"
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bitfld.long 0x34 0.--4. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "OSPI_WRITE_COMPLETION_CTRL_REG,Write Completion Control Register"
hexmask.long.byte 0x38 24.--31. 1. "POLL_REP_DELAY_FLD,Polling repetition delay"
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hexmask.long.byte 0x38 16.--23. 1. "POLL_COUNT_FLD,Polling count"
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bitfld.long 0x38 15. "ENABLE_POLLING_EXP_FLD,Enable polling expiration" "0,1"
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bitfld.long 0x38 14. "DISABLE_POLLING_FLD,Disable polling" "0,1"
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bitfld.long 0x38 13. "POLLING_POLARITY_FLD,Polling polarity" "0,1"
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rbitfld.long 0x38 11.--12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x38 8.--10. "POLLING_BIT_INDEX_FLD,Polling bit index" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x38 0.--7. 1. "OPCODE_FLD,Polling opcode"
line.long 0x3C "OSPI_NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register"
line.long 0x40 "OSPI_IRQ_STATUS_REG,Interrupt Status Register"
hexmask.long.word 0x40 20.--31. 1. "IRQ_STAT_RESV_FLD,Reserved"
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bitfld.long 0x40 19. "ECC_FAIL_FLD,ECC failure" "0,1"
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bitfld.long 0x40 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken" "0,1"
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bitfld.long 0x40 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid" "0,1"
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bitfld.long 0x40 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error" "0,1"
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rbitfld.long 0x40 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1"
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bitfld.long 0x40 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request" "0,1"
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bitfld.long 0x40 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1"
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bitfld.long 0x40 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow" "0,1"
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bitfld.long 0x40 11. "RX_FIFO_FULL_FLD,Small RX FIFO full.Current FIFO status can be ignored in non-SPI legacy mode.0h = FIFO is not full" "0,1"
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bitfld.long 0x40 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries"
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bitfld.long 0x40 9. "TX_FIFO_FULL_FLD,Small TX FIFO full" "FIFO is not full,FIFO is full"
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bitfld.long 0x40 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full.Current FIFO status can be ignored in non-SPI legacy mode" "0,1"
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bitfld.long 0x40 7. "RECV_OVERFLOW_FLD,Receive Overflow" "0,1"
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bitfld.long 0x40 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1"
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bitfld.long 0x40 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger" "0,1"
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bitfld.long 0x40 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected" "0,1"
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bitfld.long 0x40 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted" "0,1"
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bitfld.long 0x40 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1"
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bitfld.long 0x40 1. "UNDERFLOW_DET_FLD,Underflow" "0,1"
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bitfld.long 0x40 0. "MODE_M_FAIL_FLD,Mode M Failure" "no mode fault has been detected.Read,a mode fault has occurred"
line.long 0x44 "OSPI_IRQ_MASK_REG,Interrupt Mask Register"
hexmask.long.word 0x44 20.--31. 1. "IRQ_MASK_RESV_FLD,Reserved"
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bitfld.long 0x44 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1"
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bitfld.long 0x44 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1"
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bitfld.long 0x44 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1"
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bitfld.long 0x44 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1"
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rbitfld.long 0x44 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1"
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bitfld.long 0x44 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1"
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bitfld.long 0x44 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1"
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bitfld.long 0x44 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1"
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bitfld.long 0x44 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1"
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bitfld.long 0x44 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1"
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bitfld.long 0x44 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1"
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bitfld.long 0x44 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1"
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bitfld.long 0x44 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1"
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bitfld.long 0x44 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1"
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bitfld.long 0x44 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1"
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bitfld.long 0x44 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1"
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bitfld.long 0x44 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1"
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bitfld.long 0x44 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1"
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bitfld.long 0x44 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1"
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bitfld.long 0x44 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1"
group.long 0x50++0x0B
line.long 0x00 "OSPI_LOWER_WR_PROT_REG,Lower Write Protection Register"
line.long 0x04 "OSPI_UPPER_WR_PROT_REG,Upper Write Protection Register"
line.long 0x08 "OSPI_WR_PROT_CTRL_REG,Write Protection Control Register"
hexmask.long 0x08 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved"
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bitfld.long 0x08 1. "ENB_FLD,Write Protection Enable Bit" "0,1"
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bitfld.long 0x08 0. "INV_FLD,Write Protection Inversion Bit" "0,1"
group.long 0x60++0x23
line.long 0x00 "OSPI_INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved"
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rbitfld.long 0x00 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed" "0,1,2,3"
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bitfld.long 0x00 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status" "0,1"
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rbitfld.long 0x00 4. "RD_QUEUED_FLD,Queued Indirect Read Operations" "0,1"
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bitfld.long 0x00 3. "SRAM_FULL_FLD,SRAM Full" "0,1"
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rbitfld.long 0x00 2. "RD_STATUS_FLD,Indirect Read Status" "0,1"
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bitfld.long 0x00 1. "CANCEL_FLD,Cancel Indirect" "0,1"
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bitfld.long 0x00 0. "START_FLD,Start Indirect" "0,1"
line.long 0x04 "OSPI_INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register"
line.long 0x08 "OSPI_INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register"
line.long 0x0C "OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register"
line.long 0x10 "OSPI_INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register"
hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved"
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rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed" "0,1,2,3"
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bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status" "0,1"
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rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1"
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rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1"
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rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status" "0,1"
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bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect" "0,1"
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bitfld.long 0x10 0. "START_FLD,Start Indirect" "0,1"
line.long 0x14 "OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register"
line.long 0x18 "OSPI_INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register"
line.long 0x1C "OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register"
line.long 0x20 "OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register"
hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved"
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bitfld.long 0x20 0.--3. "IND_RANGE_WIDTH_FLD,Indirect Range Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C++0x0B
line.long 0x00 "OSPI_FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register"
rbitfld.long 0x00 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 20.--28. 1. "MEM_BANK_ADDR_FLD,Memory Bank Address"
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rbitfld.long 0x00 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1"
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bitfld.long 0x00 16.--18. "NB_OF_STIG_READ_BYTES_FLD,Number of STIG Memory Bank Read Bytes" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Memory Bank Read Data"
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rbitfld.long 0x00 2.--7. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress" "0,1"
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bitfld.long 0x00 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request" "0,1"
line.long 0x04 "OSPI_FLASH_CMD_CTRL_REG,Flash Command Control Register"
hexmask.long.byte 0x04 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode"
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bitfld.long 0x04 23. "ENB_READ_DATA_FLD,Read Data Enable" "0,1"
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bitfld.long 0x04 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 19. "ENB_COMD_ADDR_FLD,Command Address Enable.Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field" "0,1"
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bitfld.long 0x04 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1"
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bitfld.long 0x04 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes" "?,2 address bytes,3 address bytes,4 address bytes"
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bitfld.long 0x04 15. "ENB_WRITE_DATA_FLD,Write Data Enable" "0,1"
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bitfld.long 0x04 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7.--11. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x04 3.--6. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit" "0,1"
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rbitfld.long 0x04 1. "CMD_EXEC_STATUS_FLD,Command execution in progress" "0,1"
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bitfld.long 0x04 0. "CMD_EXEC_FLD,Execute the command" "0,1"
line.long 0x08 "OSPI_FLASH_CMD_ADDR_REG,Flash Command Address Register"
rgroup.long 0xA0++0x23
line.long 0x00 "OSPI_FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower)"
line.long 0x04 "OSPI_FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper)"
line.long 0x08 "OSPI_FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower)"
line.long 0x0C "OSPI_FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper)"
line.long 0x10 "OSPI_POLLING_FLASH_STATUS_REG,Polling Flash Status Register"
hexmask.long.word 0x10 20.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved"
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bitfld.long 0x10 16.--19. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved"
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rbitfld.long 0x10 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid" "0,1"
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hexmask.long.byte 0x10 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device"
line.long 0x14 "OSPI_PHY_CONFIGURATION_REG,PHY Configuration Register"
bitfld.long 0x14 31. "PHY_CONFIG_RESYNC_FLD,Re-synchronisation DLL" "0,1"
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bitfld.long 0x14 30. "PHY_CONFIG_RESET_FLD,DLL Reset" "0,1"
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bitfld.long 0x14 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass" "0,1"
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rbitfld.long 0x14 23.--28. "PHY_CONFIG_RESV2_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay"
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hexmask.long.word 0x14 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved"
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hexmask.long.byte 0x14 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay"
line.long 0x18 "OSPI_PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register"
hexmask.long.byte 0x18 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved"
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bitfld.long 0x18 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay" "0,1"
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bitfld.long 0x18 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs.Master DLL is disabled with only 1 delay element in its delay line" "0,1"
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bitfld.long 0x18 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x18 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1"
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bitfld.long 0x18 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x18 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved"
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hexmask.long.byte 0x18 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the Master DLL"
line.long 0x1C "OSPI_DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower"
hexmask.long.byte 0x1C 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative lock incremental steps when"
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hexmask.long.byte 0x1C 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative lock decremental steps when"
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bitfld.long 0x1C 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done" "0,1"
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hexmask.long.byte 0x1C 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,DLL Lock Value"
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bitfld.long 0x1C 3.--7. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,DLL Unlock Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,DLL Locked Mode" "0,1,2,3"
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bitfld.long 0x1C 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,DLL Lock" "0,1"
line.long 0x20 "OSPI_DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper"
hexmask.long.word 0x20 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved"
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hexmask.long.byte 0x20 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,TX DLL decoder output"
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hexmask.long.word 0x20 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved"
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hexmask.long.byte 0x20 0.--6. 1. "DLL_OBSERVABLE_UPPER_RX_DECODER_OUTPUT_FLD,RX DLL decoder output"
group.long 0xE0++0x07
line.long 0x00 "OSPI_OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower)"
hexmask.long.byte 0x00 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcoded defined in"
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hexmask.long.byte 0x00 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode defined in"
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hexmask.long.byte 0x00 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode defined in"
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hexmask.long.byte 0x00 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode defined in"
line.long 0x04 "OSPI_OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper)"
hexmask.long.byte 0x04 24.--31. 1. "WEL_OPCODE_FLD,WEL Opcode byte 1"
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hexmask.long.byte 0x04 16.--23. 1. "EXT_WEL_OPCODE_FLD,WEL Opcode byte 2 (Optional)"
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hexmask.long.word 0x04 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved"
rgroup.long 0xFC++0x03
line.long 0x00 "OSPI_MODULE_ID_REG,Module ID Register"
hexmask.long.byte 0x00 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register"
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hexmask.long.word 0x00 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number"
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bitfld.long 0x00 2.--7. "MODULE_ID_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--1. "CONF_FLD,Configuration ID number:0h = OCTAL + PHY Configuration" "?,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration"
tree.end
tree "MCU_FSS0_OSPI1_CTRL"
base ad:0x47050000
group.long 0x00++0x47
line.long 0x00 "OSPI_CONFIG_REG,OSPI Configuration Register This register contains basic configuration fields of the controller"
rbitfld.long 0x00 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE" "0,1"
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bitfld.long 0x00 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit" "0,1"
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bitfld.long 0x00 29. "CRC_ENABLE_FLD,CRC enable bit" "0,1"
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rbitfld.long 0x00 26.--28. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable" "0,1"
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bitfld.long 0x00 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol" "0,1"
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bitfld.long 0x00 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder" "Active slave is selected based on the..,Active slave is selected based on actual data.."
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bitfld.long 0x00 19.--22. "MSTR_BAUD_DIV_FLD,Master mode baud rate divisor (2 to 32) " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately.0h = If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value=1h = Operate the device in XIP mode immediately" "0,1"
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bitfld.long 0x00 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ.0h = If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction.1h = If XIP is disabled then setting to 1 will inform the controller that the device is ready.." "0,1"
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bitfld.long 0x00 16. "ENB_AHB_ADDR_REMAP_FLD,Enable Data Interface Address Remapping [Direct Access Mode Only]" "0,1"
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bitfld.long 0x00 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface" "0,1"
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bitfld.long 0x00 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin" "0,1"
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bitfld.long 0x00 10.--13. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines.If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0 ss[3:0] are output thus:else ss[3-0] directly drives N_SS_OUT[3-0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 9. "PERIPH_SEL_DEC_FLD,Peripheral select" "0,1"
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bitfld.long 0x00 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode" "0,1"
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bitfld.long 0x00 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access" "0,1"
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bitfld.long 0x00 6. "RESET_CFG_FLD,RESET pin" "0,1"
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bitfld.long 0x00 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1"
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bitfld.long 0x00 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1"
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bitfld.long 0x00 3. "PHY_MODE_ENABLE_FLD,PHY mode enable" "0,1"
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bitfld.long 0x00 2. "SEL_CLK_PHASE_FLD,Select Clock Phase.Selects whether the clock is in an active or inactive phase outside the SPI word" "The SPI clock is active outside the word,The SPI clock is inactive outside the word"
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bitfld.long 0x00 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word.0h = The SPI clock is quiescent low" "0,1"
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bitfld.long 0x00 0. "ENB_SPI_FLD,OSPI" "0,1"
line.long 0x04 "OSPI_DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register"
rbitfld.long 0x04 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 24.--28. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x04 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable" "0,1"
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rbitfld.long 0x04 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x04 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only" "?,Used for Dual Input/Output instructions For data..,Used for Quad Input/Output instructions For data..,Used for Octal Input/Output instructions For.."
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rbitfld.long 0x04 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x04 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only" "?,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ[7:0]"
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rbitfld.long 0x04 11. "RD_INSTR_RESV1_FLD,Reserved" "0,1"
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bitfld.long 0x04 10. "DDR_EN_FLD,DDR Enable" "0,1"
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bitfld.long 0x04 8.--9. "INSTR_TYPE_FLD,Instruction Type.0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only]" "?,Use DIO-SPI mode [Instructions Address and Data..,Use QIO-SPI mode [Instructions Address and Data..,Use Octal-IO-SPI mode [Instructions Address and.."
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hexmask.long.byte 0x04 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode"
line.long 0x08 "OSPI_DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register"
rbitfld.long 0x08 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 24.--28. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x08 18.--23. "WR_INSTR_RESV3_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes.0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only" "?,Used for Dual Input/Output instructions For data..,Used for Quad Input/Output instructions For data..,Used for Octal Input/Output instructions For.."
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rbitfld.long 0x08 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x08 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes.0h = Addresses can be shifted to the device on DQ0 only" "?,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ[7:0]"
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rbitfld.long 0x08 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 8. "WEL_DIS_FLD,WEL Disable" "0,1"
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hexmask.long.byte 0x08 0.--7. 1. "WR_OPCODE_FLD,Write Opcode"
line.long 0x0C "OSPI_DEV_DELAY_REG,OSPI Device Delay Register"
hexmask.long.byte 0x0C 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert"
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hexmask.long.byte 0x0C 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation"
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hexmask.long.byte 0x0C 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit"
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hexmask.long.byte 0x0C 0.--7. 1. "D_INIT_FLD,Clock Delay with N_SS_OUT"
line.long 0x10 "OSPI_RD_DATA_CAPTURE_REG,Read Data Capture Register"
hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved"
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bitfld.long 0x10 16.--19. "DDR_READ_DELAY_FLD,DDR read delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved"
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bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit" "0,1"
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rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection" "0,1"
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bitfld.long 0x10 1.--4. "DELAY_FLD,Read Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 0. "BYPASS_FLD,Bypass" "0,1"
line.long 0x14 "OSPI_DEV_SIZE_CONFIG_REG,Device Size Configuration Register"
rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin:0h = size of 512Mb" "?,size of 1Gb2h = size of 2Gb,?,size of 4Gb"
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bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin:0h = size of" "?,?,size of 2Gb,size of 4Gb"
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bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin:0h = size of" "?,?,size of 2Gb,size of 4Gb"
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bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin:0h = size of" "?,?,size of 2Gb,size of 4Gb"
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bitfld.long 0x14 16.--20. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page"
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bitfld.long 0x14 0.--3. "NUM_ADDR_BYTES_FLD,Number of address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "OSPI_SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register"
hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved"
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hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size"
line.long 0x1C "OSPI_IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register"
line.long 0x20 "OSPI_DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register"
hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved"
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bitfld.long 0x20 8.--11. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x20 4.--7. "DMA_PERIPH_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "OSPI_REMAP_ADDR_REG,Remap Address Register"
line.long 0x28 "OSPI_MODE_BIT_CONFIG_REG,Mode Bit Configuration Register"
hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower]"
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hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper]"
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bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit" "0,1"
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rbitfld.long 0x28 11.--14. "MODE_BIT_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled"
line.long 0x2C "OSPI_SRAM_FILL_REG,SRAM Fill Register"
hexmask.long.word 0x2C 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]"
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hexmask.long.word 0x2C 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]"
line.long 0x30 "OSPI_TX_THRESH_REG,TX Threshold Register"
hexmask.long 0x30 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved"
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bitfld.long 0x30 0.--4. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "OSPI_RX_THRESH_REG,RX Threshold Register"
hexmask.long 0x34 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved"
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bitfld.long 0x34 0.--4. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "OSPI_WRITE_COMPLETION_CTRL_REG,Write Completion Control Register"
hexmask.long.byte 0x38 24.--31. 1. "POLL_REP_DELAY_FLD,Polling repetition delay"
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hexmask.long.byte 0x38 16.--23. 1. "POLL_COUNT_FLD,Polling count"
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bitfld.long 0x38 15. "ENABLE_POLLING_EXP_FLD,Enable polling expiration" "0,1"
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bitfld.long 0x38 14. "DISABLE_POLLING_FLD,Disable polling" "0,1"
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bitfld.long 0x38 13. "POLLING_POLARITY_FLD,Polling polarity" "0,1"
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rbitfld.long 0x38 11.--12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1,2,3"
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bitfld.long 0x38 8.--10. "POLLING_BIT_INDEX_FLD,Polling bit index" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x38 0.--7. 1. "OPCODE_FLD,Polling opcode"
line.long 0x3C "OSPI_NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register"
line.long 0x40 "OSPI_IRQ_STATUS_REG,Interrupt Status Register"
hexmask.long.word 0x40 20.--31. 1. "IRQ_STAT_RESV_FLD,Reserved"
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bitfld.long 0x40 19. "ECC_FAIL_FLD,ECC failure" "0,1"
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bitfld.long 0x40 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken" "0,1"
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bitfld.long 0x40 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid" "0,1"
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bitfld.long 0x40 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error" "0,1"
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rbitfld.long 0x40 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1"
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bitfld.long 0x40 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request" "0,1"
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bitfld.long 0x40 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1"
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bitfld.long 0x40 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow" "0,1"
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bitfld.long 0x40 11. "RX_FIFO_FULL_FLD,Small RX FIFO full.Current FIFO status can be ignored in non-SPI legacy mode.0h = FIFO is not full" "0,1"
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bitfld.long 0x40 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries"
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bitfld.long 0x40 9. "TX_FIFO_FULL_FLD,Small TX FIFO full" "FIFO is not full,FIFO is full"
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bitfld.long 0x40 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full.Current FIFO status can be ignored in non-SPI legacy mode" "0,1"
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bitfld.long 0x40 7. "RECV_OVERFLOW_FLD,Receive Overflow" "0,1"
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bitfld.long 0x40 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1"
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bitfld.long 0x40 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger" "0,1"
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bitfld.long 0x40 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected" "0,1"
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bitfld.long 0x40 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted" "0,1"
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bitfld.long 0x40 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1"
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bitfld.long 0x40 1. "UNDERFLOW_DET_FLD,Underflow" "0,1"
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bitfld.long 0x40 0. "MODE_M_FAIL_FLD,Mode M Failure" "no mode fault has been detected.Read,a mode fault has occurred"
line.long 0x44 "OSPI_IRQ_MASK_REG,Interrupt Mask Register"
hexmask.long.word 0x44 20.--31. 1. "IRQ_MASK_RESV_FLD,Reserved"
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bitfld.long 0x44 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1"
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bitfld.long 0x44 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1"
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bitfld.long 0x44 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1"
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bitfld.long 0x44 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1"
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rbitfld.long 0x44 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1"
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bitfld.long 0x44 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1"
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bitfld.long 0x44 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1"
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bitfld.long 0x44 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1"
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bitfld.long 0x44 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1"
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bitfld.long 0x44 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1"
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bitfld.long 0x44 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1"
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bitfld.long 0x44 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1"
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bitfld.long 0x44 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1"
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bitfld.long 0x44 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1"
newline
bitfld.long 0x44 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1"
newline
bitfld.long 0x44 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1"
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bitfld.long 0x44 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1"
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bitfld.long 0x44 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1"
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bitfld.long 0x44 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1"
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bitfld.long 0x44 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1"
group.long 0x50++0x0B
line.long 0x00 "OSPI_LOWER_WR_PROT_REG,Lower Write Protection Register"
line.long 0x04 "OSPI_UPPER_WR_PROT_REG,Upper Write Protection Register"
line.long 0x08 "OSPI_WR_PROT_CTRL_REG,Write Protection Control Register"
hexmask.long 0x08 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved"
newline
bitfld.long 0x08 1. "ENB_FLD,Write Protection Enable Bit" "0,1"
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bitfld.long 0x08 0. "INV_FLD,Write Protection Inversion Bit" "0,1"
group.long 0x60++0x23
line.long 0x00 "OSPI_INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved"
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rbitfld.long 0x00 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed" "0,1,2,3"
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bitfld.long 0x00 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status" "0,1"
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rbitfld.long 0x00 4. "RD_QUEUED_FLD,Queued Indirect Read Operations" "0,1"
newline
bitfld.long 0x00 3. "SRAM_FULL_FLD,SRAM Full" "0,1"
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rbitfld.long 0x00 2. "RD_STATUS_FLD,Indirect Read Status" "0,1"
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bitfld.long 0x00 1. "CANCEL_FLD,Cancel Indirect" "0,1"
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bitfld.long 0x00 0. "START_FLD,Start Indirect" "0,1"
line.long 0x04 "OSPI_INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register"
line.long 0x08 "OSPI_INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register"
line.long 0x0C "OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register"
line.long 0x10 "OSPI_INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register"
hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved"
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rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed" "0,1,2,3"
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bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status" "0,1"
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rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1"
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rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1"
newline
rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status" "0,1"
newline
bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect" "0,1"
newline
bitfld.long 0x10 0. "START_FLD,Start Indirect" "0,1"
line.long 0x14 "OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register"
line.long 0x18 "OSPI_INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register"
line.long 0x1C "OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register"
line.long 0x20 "OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register"
hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved"
newline
bitfld.long 0x20 0.--3. "IND_RANGE_WIDTH_FLD,Indirect Range Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C++0x0B
line.long 0x00 "OSPI_FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register"
rbitfld.long 0x00 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 20.--28. 1. "MEM_BANK_ADDR_FLD,Memory Bank Address"
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rbitfld.long 0x00 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1"
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bitfld.long 0x00 16.--18. "NB_OF_STIG_READ_BYTES_FLD,Number of STIG Memory Bank Read Bytes" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Memory Bank Read Data"
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rbitfld.long 0x00 2.--7. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress" "0,1"
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bitfld.long 0x00 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request" "0,1"
line.long 0x04 "OSPI_FLASH_CMD_CTRL_REG,Flash Command Control Register"
hexmask.long.byte 0x04 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode"
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bitfld.long 0x04 23. "ENB_READ_DATA_FLD,Read Data Enable" "0,1"
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bitfld.long 0x04 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 19. "ENB_COMD_ADDR_FLD,Command Address Enable.Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field" "0,1"
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bitfld.long 0x04 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1"
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bitfld.long 0x04 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes" "?,2 address bytes,3 address bytes,4 address bytes"
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bitfld.long 0x04 15. "ENB_WRITE_DATA_FLD,Write Data Enable" "0,1"
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bitfld.long 0x04 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7.--11. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x04 3.--6. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit" "0,1"
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rbitfld.long 0x04 1. "CMD_EXEC_STATUS_FLD,Command execution in progress" "0,1"
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bitfld.long 0x04 0. "CMD_EXEC_FLD,Execute the command" "0,1"
line.long 0x08 "OSPI_FLASH_CMD_ADDR_REG,Flash Command Address Register"
rgroup.long 0xA0++0x23
line.long 0x00 "OSPI_FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower)"
line.long 0x04 "OSPI_FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper)"
line.long 0x08 "OSPI_FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower)"
line.long 0x0C "OSPI_FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper)"
line.long 0x10 "OSPI_POLLING_FLASH_STATUS_REG,Polling Flash Status Register"
hexmask.long.word 0x10 20.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved"
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bitfld.long 0x10 16.--19. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved"
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rbitfld.long 0x10 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid" "0,1"
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hexmask.long.byte 0x10 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device"
line.long 0x14 "OSPI_PHY_CONFIGURATION_REG,PHY Configuration Register"
bitfld.long 0x14 31. "PHY_CONFIG_RESYNC_FLD,Re-synchronisation DLL" "0,1"
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bitfld.long 0x14 30. "PHY_CONFIG_RESET_FLD,DLL Reset" "0,1"
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bitfld.long 0x14 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass" "0,1"
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rbitfld.long 0x14 23.--28. "PHY_CONFIG_RESV2_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x14 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay"
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hexmask.long.word 0x14 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved"
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hexmask.long.byte 0x14 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay"
line.long 0x18 "OSPI_PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register"
hexmask.long.byte 0x18 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved"
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bitfld.long 0x18 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay" "0,1"
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bitfld.long 0x18 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs.Master DLL is disabled with only 1 delay element in its delay line" "0,1"
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bitfld.long 0x18 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x18 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1"
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bitfld.long 0x18 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x18 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved"
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hexmask.long.byte 0x18 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the Master DLL"
line.long 0x1C "OSPI_DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower"
hexmask.long.byte 0x1C 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative lock incremental steps when"
newline
hexmask.long.byte 0x1C 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative lock decremental steps when"
newline
bitfld.long 0x1C 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done" "0,1"
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hexmask.long.byte 0x1C 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,DLL Lock Value"
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bitfld.long 0x1C 3.--7. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,DLL Unlock Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,DLL Locked Mode" "0,1,2,3"
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bitfld.long 0x1C 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,DLL Lock" "0,1"
line.long 0x20 "OSPI_DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper"
hexmask.long.word 0x20 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved"
newline
hexmask.long.byte 0x20 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,TX DLL decoder output"
newline
hexmask.long.word 0x20 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved"
newline
hexmask.long.byte 0x20 0.--6. 1. "DLL_OBSERVABLE_UPPER_RX_DECODER_OUTPUT_FLD,RX DLL decoder output"
group.long 0xE0++0x07
line.long 0x00 "OSPI_OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower)"
hexmask.long.byte 0x00 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcoded defined in"
newline
hexmask.long.byte 0x00 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode defined in"
newline
hexmask.long.byte 0x00 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode defined in"
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hexmask.long.byte 0x00 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode defined in"
line.long 0x04 "OSPI_OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper)"
hexmask.long.byte 0x04 24.--31. 1. "WEL_OPCODE_FLD,WEL Opcode byte 1"
newline
hexmask.long.byte 0x04 16.--23. 1. "EXT_WEL_OPCODE_FLD,WEL Opcode byte 2 (Optional)"
newline
hexmask.long.word 0x04 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved"
rgroup.long 0xFC++0x03
line.long 0x00 "OSPI_MODULE_ID_REG,Module ID Register"
hexmask.long.byte 0x00 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register"
newline
hexmask.long.word 0x00 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number"
newline
bitfld.long 0x00 2.--7. "MODULE_ID_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--1. "CONF_FLD,Configuration ID number:0h = OCTAL + PHY Configuration" "?,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration"
tree.end
tree "MCU_FSS0_OSPI0_SS_CFG"
base ad:0x47044000
rgroup.long 0x00++0x0B
line.long 0x00 "OSPI_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "OSPI_CTRL,The Control Register contains general control bits for the OSPI"
bitfld.long 0x04 3. "PIPELINE_MODE_FLUSH," "0,1"
line.long 0x08 "OSPI_STAT,The Status register provide general status bits for the OSPI"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
group.long 0x20++0x03
line.long 0x00 "OSPI_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI,Write with bit position of targetted interrupt.(that is Ext TS is bit 0)"
tree.end
tree "MCU_FSS0_OSPI1_SS_CFG"
base ad:0x47054000
rgroup.long 0x00++0x0B
line.long 0x00 "OSPI_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "OSPI_CTRL,The Control Register contains general control bits for the OSPI"
bitfld.long 0x04 3. "PIPELINE_MODE_FLUSH," "0,1"
line.long 0x08 "OSPI_STAT,The Status register provide general status bits for the OSPI"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
group.long 0x20++0x03
line.long 0x00 "OSPI_EOI,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI,Write with bit position of targetted interrupt.(that is Ext TS is bit 0)"
tree.end
tree "MCU_FSS0_OSPI0_ECC_AGGR"
base ad:0x47068000
rgroup.long 0x00++0x03
line.long 0x00 "OSPI_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "OSPI_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "OSPI_ECC_STAT,Miscellaneous status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
line.long 0x08 "OSPI_RESERVED_SVBUS_Y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "OSPI_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "OSPI_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "OSPI_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "OSPI_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "OSPI_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "OSPI_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "OSPI_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "OSPI_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "OSPI_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "OSPI_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "OSPI_ECC_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "OSPI_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_FSS0_OSPI1_ECC_AGGR"
base ad:0x47064000
rgroup.long 0x00++0x03
line.long 0x00 "OSPI_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "OSPI_ECC_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "OSPI_ECC_STAT,Miscellaneous status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
line.long 0x08 "OSPI_RESERVED_SVBUS_Y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "OSPI_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "OSPI_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "OSPI_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "OSPI_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "OSPI_ECC_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "OSPI_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "OSPI_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "OSPI_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "OSPI_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "OSPI_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "OSPI_ECC_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "OSPI_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "PAT_CFG_MMRS"
tree "PAT0_CFG_MMRS"
base ad:0x31010000
rgroup.long 0x00++0x07
line.long 0x00 "PAT_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
newline
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PAT_CONFIG,The Config Register contains the configuration values for the module"
group.long 0x10++0x03
line.long 0x00 "PAT_CONTROL,The Control Register contains controls for the PAT"
bitfld.long 0x00 6.--7. "ARB_MODE,Arbitration mode" "updates first,reserved,round robin,reserved"
bitfld.long 0x00 4.--5. "PAGE_SIZE,Page Size" "4KB,16KB,64KB,1MB"
bitfld.long 0x00 1. "REPLACE_ORDERID_ENABLE,Globally enable the replace orderid feature allowing a hypervisor or OS to globally disable the feature if applications or VMs should not be able to modify orderid values" "disabled,enabled"
newline
bitfld.long 0x00 0. "ENABLE,Enable bit" "disabled,enabled"
group.long 0x84++0x03
line.long 0x00 "PAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0xA0++0x1B
line.long 0x00 "PAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x01=Boundary crossing error,0x02=Page not enabled error"
line.long 0x0C "PAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "PAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
newline
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0xC0++0x13
line.long 0x00 "PAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PAT_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PAT1_CFG_MMRS"
base ad:0x31011000
rgroup.long 0x00++0x07
line.long 0x00 "PAT_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
newline
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PAT_CONFIG,The Config Register contains the configuration values for the module"
group.long 0x10++0x03
line.long 0x00 "PAT_CONTROL,The Control Register contains controls for the PAT"
bitfld.long 0x00 6.--7. "ARB_MODE,Arbitration mode" "updates first,reserved,round robin,reserved"
bitfld.long 0x00 4.--5. "PAGE_SIZE,Page Size" "4KB,16KB,64KB,1MB"
bitfld.long 0x00 1. "REPLACE_ORDERID_ENABLE,Globally enable the replace orderid feature allowing a hypervisor or OS to globally disable the feature if applications or VMs should not be able to modify orderid values" "disabled,enabled"
newline
bitfld.long 0x00 0. "ENABLE,Enable bit" "disabled,enabled"
group.long 0x84++0x03
line.long 0x00 "PAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0xA0++0x1B
line.long 0x00 "PAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x01=Boundary crossing error,0x02=Page not enabled error"
line.long 0x0C "PAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "PAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
newline
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0xC0++0x13
line.long 0x00 "PAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PAT_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PAT2_CFG_MMRS"
base ad:0x31012000
rgroup.long 0x00++0x07
line.long 0x00 "PAT_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
newline
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PAT_CONFIG,The Config Register contains the configuration values for the module"
group.long 0x10++0x03
line.long 0x00 "PAT_CONTROL,The Control Register contains controls for the PAT"
bitfld.long 0x00 6.--7. "ARB_MODE,Arbitration mode" "updates first,reserved,round robin,reserved"
bitfld.long 0x00 4.--5. "PAGE_SIZE,Page Size" "4KB,16KB,64KB,1MB"
bitfld.long 0x00 1. "REPLACE_ORDERID_ENABLE,Globally enable the replace orderid feature allowing a hypervisor or OS to globally disable the feature if applications or VMs should not be able to modify orderid values" "disabled,enabled"
newline
bitfld.long 0x00 0. "ENABLE,Enable bit" "disabled,enabled"
group.long 0x84++0x03
line.long 0x00 "PAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0xA0++0x1B
line.long 0x00 "PAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x01=Boundary crossing error,0x02=Page not enabled error"
line.long 0x0C "PAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "PAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
newline
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0xC0++0x13
line.long 0x00 "PAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PAT_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PAT3_CFG_MMRS"
base ad:0x31013000
rgroup.long 0x00++0x07
line.long 0x00 "PAT_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
newline
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PAT_CONFIG,The Config Register contains the configuration values for the module"
group.long 0x10++0x03
line.long 0x00 "PAT_CONTROL,The Control Register contains controls for the PAT"
bitfld.long 0x00 6.--7. "ARB_MODE,Arbitration mode" "updates first,reserved,round robin,reserved"
bitfld.long 0x00 4.--5. "PAGE_SIZE,Page Size" "4KB,16KB,64KB,1MB"
bitfld.long 0x00 1. "REPLACE_ORDERID_ENABLE,Globally enable the replace orderid feature allowing a hypervisor or OS to globally disable the feature if applications or VMs should not be able to modify orderid values" "disabled,enabled"
newline
bitfld.long 0x00 0. "ENABLE,Enable bit" "disabled,enabled"
group.long 0x84++0x03
line.long 0x00 "PAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0xA0++0x1B
line.long 0x00 "PAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x01=Boundary crossing error,0x02=Page not enabled error"
line.long 0x0C "PAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "PAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
newline
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0xC0++0x13
line.long 0x00 "PAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PAT_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PAT4_CFG_MMRS"
base ad:0x31014000
rgroup.long 0x00++0x07
line.long 0x00 "PAT_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
newline
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PAT_CONFIG,The Config Register contains the configuration values for the module"
group.long 0x10++0x03
line.long 0x00 "PAT_CONTROL,The Control Register contains controls for the PAT"
bitfld.long 0x00 6.--7. "ARB_MODE,Arbitration mode" "updates first,reserved,round robin,reserved"
bitfld.long 0x00 4.--5. "PAGE_SIZE,Page Size" "4KB,16KB,64KB,1MB"
bitfld.long 0x00 1. "REPLACE_ORDERID_ENABLE,Globally enable the replace orderid feature allowing a hypervisor or OS to globally disable the feature if applications or VMs should not be able to modify orderid values" "disabled,enabled"
newline
bitfld.long 0x00 0. "ENABLE,Enable bit" "disabled,enabled"
group.long 0x84++0x03
line.long 0x00 "PAT_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0xA0++0x1B
line.long 0x00 "PAT_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PAT_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PAT_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
abitfld.long 0x08 16.--23. "CODE,Code" "0x01=Boundary crossing error,0x02=Page not enabled error"
line.long 0x0C "PAT_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PAT_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "PAT_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
newline
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PAT_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the third word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0xC0++0x13
line.long 0x00 "PAT_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PAT_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PAT_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PAT_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PAT_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PAT0_CFG_SCRATCH"
base ad:0x36200000
group.long 0x00++0x03
line.long 0x00 "PAT_MEM_y,The Scratch Memory Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
tree.end
tree "PAT1_CFG_SCRATCH"
base ad:0x36210000
group.long 0x00++0x03
line.long 0x00 "PAT_MEM_y,The Scratch Memory Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
tree.end
tree "PAT2_CFG_SCRATCH"
base ad:0x36220000
group.long 0x00++0x03
line.long 0x00 "PAT_MEM_y,The Scratch Memory Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
tree.end
tree "PAT3_CFG_SCRATCH"
base ad:0x36230000
group.long 0x00++0x03
line.long 0x00 "PAT_MEM_y,The Scratch Memory Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
tree.end
tree "PAT4_CFG_SCRATCH"
base ad:0x36240000
group.long 0x00++0x03
line.long 0x00 "PAT_MEM_y,The Scratch Memory Offset = 0h + (y * 4h); where y = 0h to 3FFFh"
tree.end
tree "PAT0_CFG_TABLE"
base ad:0x36400000
group.long 0x00++0x07
line.long 0x00 "PAT_BASE_REG_L_j_k,The Base Low Address bits 43 to 12 for Page"
line.long 0x04 "PAT_BASE_REG_H_j_k,The Base High Address bits 47 to 44 for Page"
bitfld.long 0x04 31. "ENABLE,Translation Enable for Page" "disabled,enabled"
bitfld.long 0x04 30. "REPLACE_OID,OrderID replacement Enable for Page" "use input orderid,force replacement to orderid in page"
rbitfld.long 0x04 24.--27. "ORDERID,Translated orderid to use with translation address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "BASE_H,Translated Base Address bits 47 to 44 for Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "PAT1_CFG_TABLE"
base ad:0x36440000
group.long 0x00++0x07
line.long 0x00 "PAT_BASE_REG_L_j_k,The Base Low Address bits 43 to 12 for Page"
line.long 0x04 "PAT_BASE_REG_H_j_k,The Base High Address bits 47 to 44 for Page"
bitfld.long 0x04 31. "ENABLE,Translation Enable for Page" "disabled,enabled"
bitfld.long 0x04 30. "REPLACE_OID,OrderID replacement Enable for Page" "use input orderid,force replacement to orderid in page"
rbitfld.long 0x04 24.--27. "ORDERID,Translated orderid to use with translation address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "BASE_H,Translated Base Address bits 47 to 44 for Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "PAT2_CFG_TABLE"
base ad:0x36480000
group.long 0x00++0x07
line.long 0x00 "PAT_BASE_REG_L_j_k,The Base Low Address bits 43 to 12 for Page"
line.long 0x04 "PAT_BASE_REG_H_j_k,The Base High Address bits 47 to 44 for Page"
bitfld.long 0x04 31. "ENABLE,Translation Enable for Page" "disabled,enabled"
bitfld.long 0x04 30. "REPLACE_OID,OrderID replacement Enable for Page" "use input orderid,force replacement to orderid in page"
rbitfld.long 0x04 24.--27. "ORDERID,Translated orderid to use with translation address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "BASE_H,Translated Base Address bits 47 to 44 for Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "PAT3_CFG_TABLE"
base ad:0x364C0000
group.long 0x00++0x07
line.long 0x00 "PAT_BASE_REG_L_j_k,The Base Low Address bits 43 to 12 for Page"
line.long 0x04 "PAT_BASE_REG_H_j_k,The Base High Address bits 47 to 44 for Page"
bitfld.long 0x04 31. "ENABLE,Translation Enable for Page" "disabled,enabled"
bitfld.long 0x04 30. "REPLACE_OID,OrderID replacement Enable for Page" "use input orderid,force replacement to orderid in page"
rbitfld.long 0x04 24.--27. "ORDERID,Translated orderid to use with translation address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "BASE_H,Translated Base Address bits 47 to 44 for Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "PAT4_CFG_TABLE"
base ad:0x36500000
group.long 0x00++0x07
line.long 0x00 "PAT_BASE_REG_L_j_k,The Base Low Address bits 43 to 12 for Page"
line.long 0x04 "PAT_BASE_REG_H_j_k,The Base High Address bits 47 to 44 for Page"
bitfld.long 0x04 31. "ENABLE,Translation Enable for Page" "disabled,enabled"
bitfld.long 0x04 30. "REPLACE_OID,OrderID replacement Enable for Page" "use input orderid,force replacement to orderid in page"
rbitfld.long 0x04 24.--27. "ORDERID,Translated orderid to use with translation address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "BASE_H,Translated Base Address bits 47 to 44 for Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "PCIE_CORE_AXI"
tree "PCIE0_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE1_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE2_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE3_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree.end
tree "PCIE_CORE_EP"
tree "PCIE0_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE1_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE2_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE3_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree.end
tree "PCIE_CORE_EP_PF"
tree "PCIE0_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE1_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE2_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE3_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree.end
tree "PCIE_CORE_EP_VF"
tree "PCIE0_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE1_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE2_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE3_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree.end
tree "PCIE_CORE_LM"
tree "PCIE0_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE1_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE2_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE3_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree.end
tree "PCIE0_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE1_CORE_DBN_CFG_PCIE_CORE"
base ad:0xD800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE2_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE000000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE3_CORE_DBN_CFG_PCIE_CORE"
base ad:0xE800000
group.long 0x400000++0x0F
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400014++0x0B
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400400++0x0F
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of PCIe Address Register for region N"
rbitfld.long 0x00 6.--7. "RSVD,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,Number_bits + 1 bits are passed through from AXI address to the PCIe address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_ADDR1,Return to"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC0,Return to"
line.long 0x0C "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC1,Return to"
group.long 0x400414++0x0B
line.long 0x00 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_DESC3,Return to"
hexmask.long.word 0x00 23.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--22. 1. "DATA,{Execute Permission Supported Privileged Mode Supported PASID Value PASID present bit}"
line.long 0x04 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR0,Return to"
hexmask.long.tbyte 0x04 8.--31. 1. "DATA,Bits[31:8] of Outbound AXI Region Base Address Register used to decode the region"
bitfld.long 0x04 6.--7. "RSVD,These needs to be forced to 0" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REGION_SIZE,the value programmed in this field + 1 gives the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "PCIE_CORE_ATU_HP_WRAPPER_OB_i_AXI_ADDR1,Return to"
group.long 0x400800++0x07
line.long 0x00 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR0,Return to"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA,Bits[31:8] of AXI Address Register for BAR N"
rbitfld.long 0x00 6.--7. "RSVD0,Bits 7 and 6 are reserved" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "NUM_BITS,The value programmed in this register +1 bits are passed through from PCIe to AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_CORE_ATU_WRAPPER_IB_k_ADDR1,Return to"
group.long 0x400820++0x07
line.long 0x00 "PCIE_CORE_ATU_CREDIT_THRESHOLD_C0,Return to"
hexmask.long.byte 0x00 12.--19. 1. "HEADER,This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper"
hexmask.long.word 0x00 0.--11. 1. "DATA,This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper"
line.long 0x04 "PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0,Return to"
bitfld.long 0x04 0. "CLEAR_LINK_DOWN_BIT_TO_PROCEED,This bit will be set when link down reset comes.client should clear this bit before issueing new traffic to the core" "0,1"
group.long 0x400840++0x07
line.long 0x00 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR0,Return to"
line.long 0x04 "PCIE_CORE_ATU_FUNCm_WRAPPER_IB_EP_n_ADDR1,Return to"
tree.end
tree "PCIE_CPTS"
tree "PCIE0_CORE_CPTS_CFG_CPTS_VBUSP"
base ad:0x2906000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x08++0x53
line.long 0x00 "PCIE_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x00 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x04 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x08 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x0C "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x0C 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x10 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x14 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x18 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x18 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x1C "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x1C 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x20 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x20 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x24 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x24 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x28 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x28 0. "EVENT_POP,Event pop" "0,1"
line.long 0x2C "PCIE_CPTS_EVENT_0_REG,Event 0 Register"
line.long 0x30 "PCIE_CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x30 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
bitfld.long 0x30 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x34 "PCIE_CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x34 0.--7. 1. "DOMAIN,Domain"
line.long 0x38 "PCIE_CPTS_EVENT_3_REG,Event 3 Register"
line.long 0x3C "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x40 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x44 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x44 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x48 "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x4C "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x4C 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x50 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x50 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x200++0x1B
line.long 0x00 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x08 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
bitfld.long 0x08 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
bitfld.long 0x08 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
bitfld.long 0x08 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
newline
bitfld.long 0x08 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
bitfld.long 0x08 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
bitfld.long 0x08 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
bitfld.long 0x08 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
bitfld.long 0x08 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
newline
bitfld.long 0x08 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
bitfld.long 0x08 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "0,1"
bitfld.long 0x08 5. "MODE,Timestamp mode" "0,1"
bitfld.long 0x08 4. "SEQUENCE_EN,Sequence Enable" "0,1"
bitfld.long 0x08 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
newline
bitfld.long 0x08 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
bitfld.long 0x08 1. "INT_TEST,Interrupt test" "0,1"
bitfld.long 0x08 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x0C "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
tree.end
tree "PCIE1_CORE_CPTS_CFG_CPTS_VBUSP"
base ad:0x2916000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x08++0x53
line.long 0x00 "PCIE_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x00 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x04 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x08 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x0C "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x0C 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x10 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x14 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x18 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x18 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x1C "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x1C 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x20 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x20 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x24 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x24 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x28 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x28 0. "EVENT_POP,Event pop" "0,1"
line.long 0x2C "PCIE_CPTS_EVENT_0_REG,Event 0 Register"
line.long 0x30 "PCIE_CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x30 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
bitfld.long 0x30 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x34 "PCIE_CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x34 0.--7. 1. "DOMAIN,Domain"
line.long 0x38 "PCIE_CPTS_EVENT_3_REG,Event 3 Register"
line.long 0x3C "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x40 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x44 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x44 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x48 "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x4C "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x4C 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x50 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x50 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x200++0x1B
line.long 0x00 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x08 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
bitfld.long 0x08 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
bitfld.long 0x08 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
bitfld.long 0x08 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
newline
bitfld.long 0x08 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
bitfld.long 0x08 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
bitfld.long 0x08 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
bitfld.long 0x08 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
bitfld.long 0x08 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
newline
bitfld.long 0x08 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
bitfld.long 0x08 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "0,1"
bitfld.long 0x08 5. "MODE,Timestamp mode" "0,1"
bitfld.long 0x08 4. "SEQUENCE_EN,Sequence Enable" "0,1"
bitfld.long 0x08 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
newline
bitfld.long 0x08 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
bitfld.long 0x08 1. "INT_TEST,Interrupt test" "0,1"
bitfld.long 0x08 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x0C "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
tree.end
tree "PCIE2_CORE_CPTS_CFG_CPTS_VBUSP"
base ad:0x2926000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x08++0x53
line.long 0x00 "PCIE_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x00 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x04 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x08 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x0C "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x0C 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x10 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x14 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x18 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x18 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x1C "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x1C 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x20 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x20 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x24 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x24 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x28 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x28 0. "EVENT_POP,Event pop" "0,1"
line.long 0x2C "PCIE_CPTS_EVENT_0_REG,Event 0 Register"
line.long 0x30 "PCIE_CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x30 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
bitfld.long 0x30 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x34 "PCIE_CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x34 0.--7. 1. "DOMAIN,Domain"
line.long 0x38 "PCIE_CPTS_EVENT_3_REG,Event 3 Register"
line.long 0x3C "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x40 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x44 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x44 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x48 "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x4C "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x4C 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x50 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x50 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x200++0x1B
line.long 0x00 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x08 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
bitfld.long 0x08 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
bitfld.long 0x08 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
bitfld.long 0x08 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
newline
bitfld.long 0x08 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
bitfld.long 0x08 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
bitfld.long 0x08 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
bitfld.long 0x08 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
bitfld.long 0x08 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
newline
bitfld.long 0x08 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
bitfld.long 0x08 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "0,1"
bitfld.long 0x08 5. "MODE,Timestamp mode" "0,1"
bitfld.long 0x08 4. "SEQUENCE_EN,Sequence Enable" "0,1"
bitfld.long 0x08 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
newline
bitfld.long 0x08 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
bitfld.long 0x08 1. "INT_TEST,Interrupt test" "0,1"
bitfld.long 0x08 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x0C "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
tree.end
tree "PCIE3_CORE_CPTS_CFG_CPTS_VBUSP"
base ad:0x2936000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_CPTS_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
group.long 0x08++0x53
line.long 0x00 "PCIE_CPTS_RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x00 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PCIE_CPTS_TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x04 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x08 "PCIE_CPTS_TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x0C "PCIE_CPTS_TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x0C 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x10 "PCIE_CPTS_TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x14 "PCIE_CPTS_TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x18 "PCIE_CPTS_INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x18 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x1C "PCIE_CPTS_INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x1C 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x20 "PCIE_CPTS_INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x20 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x24 "PCIE_CPTS_TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x24 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x28 "PCIE_CPTS_EVENT_POP_REG,Event Pop Register"
bitfld.long 0x28 0. "EVENT_POP,Event pop" "0,1"
line.long 0x2C "PCIE_CPTS_EVENT_0_REG,Event 0 Register"
line.long 0x30 "PCIE_CPTS_EVENT_1_REG,Event 1 Register"
bitfld.long 0x30 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
bitfld.long 0x30 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x34 "PCIE_CPTS_EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x34 0.--7. 1. "DOMAIN,Domain"
line.long 0x38 "PCIE_CPTS_EVENT_3_REG,Event 3 Register"
line.long 0x3C "PCIE_CPTS_TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x40 "PCIE_CPTS_TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x44 "PCIE_CPTS_TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x44 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x48 "PCIE_CPTS_TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x4C "PCIE_CPTS_TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x4C 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x50 "PCIE_CPTS_TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x50 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x200++0x1B
line.long 0x00 "PCIE_CPTS_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "PCIE_CPTS_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "PCIE_CPTS_CONTROL_REG,Time Sync Control Register"
bitfld.long 0x08 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
bitfld.long 0x08 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
bitfld.long 0x08 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
bitfld.long 0x08 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
newline
bitfld.long 0x08 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
bitfld.long 0x08 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
bitfld.long 0x08 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
bitfld.long 0x08 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
bitfld.long 0x08 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
newline
bitfld.long 0x08 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
bitfld.long 0x08 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "0,1"
bitfld.long 0x08 5. "MODE,Timestamp mode" "0,1"
bitfld.long 0x08 4. "SEQUENCE_EN,Sequence Enable" "0,1"
bitfld.long 0x08 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
newline
bitfld.long 0x08 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
bitfld.long 0x08 1. "INT_TEST,Interrupt test" "0,1"
bitfld.long 0x08 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x0C "PCIE_CPTS_LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PCIE_CPTS_PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PCIE_CPTS_PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "PCIE_CPTS_NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
tree.end
tree.end
tree "PCIE_ECC_AGGR0"
tree "PCIE0_CORE_ECC_AGGR0"
base ad:0x2A00000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC0_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC0_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC0_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC0_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PCIE1_CORE_ECC_AGGR0"
base ad:0x2A02000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC0_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC0_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC0_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC0_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PCIE2_CORE_ECC_AGGR0"
base ad:0x2A04000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC0_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC0_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC0_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC0_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PCIE3_CORE_ECC_AGGR0"
base ad:0x2A06000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC0_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC0_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC0_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC0_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC0_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC0_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC0_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC0_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "AXI2VBUSM_MST_LP_PEND,Interrupt Pending Status for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x04 7. "AXI2VBUSM_MST_HP_PEND,Interrupt Pending Status for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x04 6. "HP_DIBRAM_RAMECC_PEND,Interrupt Pending Status for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 5. "HP_AXISFIFO_RAMECC_PEND,Interrupt Pending Status for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 4. "HP_AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 3. "DIBRAM_RAMECC_PEND,Interrupt Pending Status for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "AXISFIFO_RAMECC_PEND,Interrupt Pending Status for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "AXIMFIFO_RAMECC_PEND,Interrupt Pending Status for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "EDC_CTRL_PEND,Interrupt Pending Status for edc_ctrl_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_SET,Interrupt Enable Set Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_SET,Interrupt Enable Set Register for edc_ctrl_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC0_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "AXI2VBUSM_MST_LP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_lp_pend" "0,1"
bitfld.long 0x00 7. "AXI2VBUSM_MST_HP_ENABLE_CLR,Interrupt Enable Clear Register for axi2vbusm_mst_hp_pend" "0,1"
bitfld.long 0x00 6. "HP_DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 5. "HP_AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 4. "HP_AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 3. "DIBRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dibram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 2. "AXISFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "AXIMFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for aximfifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "EDC_CTRL_ENABLE_CLR,Interrupt Enable Clear Register for edc_ctrl_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC0_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC0_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC0_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC0_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "PCIE_ECC_AGGR1"
tree "PCIE0_CORE_ECC_AGGR1"
base ad:0x2A01000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC1_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC1_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC1_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC1_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC1_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC1_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PCIE1_CORE_ECC_AGGR1"
base ad:0x2A03000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC1_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC1_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC1_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC1_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC1_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC1_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PCIE2_CORE_ECC_AGGR1"
base ad:0x2A05000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC1_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC1_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC1_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC1_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC1_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC1_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PCIE3_CORE_ECC_AGGR1"
base ad:0x2A07000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_ECC1_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "PCIE_ECC1_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PCIE_ECC1_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "PCIE_ECC1_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "PCIE_ECC1_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PCIE_ECC1_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PCIE_ECC1_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "PCIE_ECC1_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 6. "HP_AXISRODR_RAMECC_PEND,Interrupt Pending Status for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 5. "AXISRODR_RAMECC_PEND,Interrupt Pending Status for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x04 4. "RPLYBUF_RAMECC_PEND,Interrupt Pending Status for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "HP_RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RXCPLFIFO_RAMECC_PEND,Interrupt Pending Status for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x04 1. "HP_PNPFIFO_RAMECC_PEND,Interrupt Pending Status for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PNPFIFO_RAMECC_PEND,Interrupt Pending Status for pnpfifo_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PCIE_ECC1_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 6. "HP_AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 5. "AXISRODR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for axisrodr_ramecc_pend" "0,1"
bitfld.long 0x00 4. "RPLYBUF_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rplybuf_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "HP_RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RXCPLFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rxcplfifo_ramecc_pend" "0,1"
bitfld.long 0x00 1. "HP_PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hp_pnpfifo_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PNPFIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pnpfifo_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PCIE_ECC1_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "PCIE_ECC1_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PCIE_ECC1_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PCIE_ECC1_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "PCIE_HP_DAT0"
tree "PCIE0_DAT0"
base ad:0x10000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE1_DAT0"
base ad:0x18000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE2_DAT0"
base ad:0x4400000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE3_DAT0"
base ad:0x4410000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree.end
tree "PCIE_HP_DAT1"
tree "PCIE0_DAT1"
base ad:0x4000000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE1_DAT1"
base ad:0x4100000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE2_DAT1"
base ad:0x4200000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE3_DAT1"
base ad:0x4300000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree.end
tree "PCIE_INTD"
tree "PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG"
base ad:0x2900000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_INTD_REVISION,Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "PCIE_INTD_EOI_REG,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "PCIE_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_REG_SYS_0,Enable Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8,Enable Set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7,Enable Set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6,Enable Set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5,Enable Set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4,Enable Set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3,Enable Set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2,Enable Set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1,Enable Set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0,Enable Set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2,Enable Set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1,Enable Set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0,Enable Set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3,Enable Set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2,Enable Set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1,Enable Set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0,Enable Set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_REG_SYS_1,Enable Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5,Enable Set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4,Enable Set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3,Enable Set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2,Enable Set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1,Enable Set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0,Enable Set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21,Enable Set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20,Enable Set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19,Enable Set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18,Enable Set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17,Enable Set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16,Enable Set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15,Enable Set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14,Enable Set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13,Enable Set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12,Enable Set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11,Enable Set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10,Enable Set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9,Enable Set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8,Enable Set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7,Enable Set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6,Enable Set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5,Enable Set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4,Enable Set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3,Enable Set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2,Enable Set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1,Enable Set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0,Enable Set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_REG_SYS_2,Enable Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM,Enable Set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6,Enable Set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5,Enable Set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4,Enable Set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3,Enable Set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2,Enable Set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1,Enable Set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0,Enable Set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE,Enable Set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET,Enable Set for sys_en_pcie_hot_reset" "0,1"
group.long 0x300++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_CLR_REG_SYS_0,Enable Clear Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8_CLR,Enable Clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7_CLR,Enable Clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6_CLR,Enable Clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5_CLR,Enable Clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4_CLR,Enable Clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3_CLR,Enable Clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2_CLR,Enable Clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1_CLR,Enable Clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0_CLR,Enable Clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2_CLR,Enable Clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1_CLR,Enable Clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0_CLR,Enable Clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3_CLR,Enable Clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2_CLR,Enable Clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1_CLR,Enable Clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0_CLR,Enable Clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_CLR_REG_SYS_1,Enable Clear Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR,Enable Clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR,Enable Clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR,Enable Clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR,Enable Clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR,Enable Clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR,Enable Clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21_CLR,Enable Clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20_CLR,Enable Clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19_CLR,Enable Clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18_CLR,Enable Clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17_CLR,Enable Clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16_CLR,Enable Clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15_CLR,Enable Clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14_CLR,Enable Clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13_CLR,Enable Clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12_CLR,Enable Clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11_CLR,Enable Clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10_CLR,Enable Clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9_CLR,Enable Clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8_CLR,Enable Clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7_CLR,Enable Clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6_CLR,Enable Clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5_CLR,Enable Clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4_CLR,Enable Clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3_CLR,Enable Clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2_CLR,Enable Clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1_CLR,Enable Clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0_CLR,Enable Clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_CLR_REG_SYS_2,Enable Clear Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM_CLR,Enable Clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6_CLR,Enable Clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5_CLR,Enable Clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4_CLR,Enable Clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3_CLR,Enable Clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2_CLR,Enable Clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1_CLR,Enable Clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0_CLR,Enable Clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE_CLR,Enable Clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET_CLR,Enable Clear for sys_en_pcie_hot_reset" "0,1"
group.long 0x500++0x0B
line.long 0x00 "PCIE_INTD_STATUS_REG_SYS_0,Status Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8,Status write 1 to set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7,Status write 1 to set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6,Status write 1 to set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5,Status write 1 to set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4,Status write 1 to set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3,Status write 1 to set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2,Status write 1 to set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1,Status write 1 to set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0,Status write 1 to set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2,Status write 1 to set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1,Status write 1 to set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0,Status write 1 to set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3,Status write 1 to set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2,Status write 1 to set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1,Status write 1 to set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0,Status write 1 to set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_REG_SYS_1,Status Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5,Status write 1 to set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4,Status write 1 to set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3,Status write 1 to set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2,Status write 1 to set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1,Status write 1 to set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0,Status write 1 to set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21,Status write 1 to set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20,Status write 1 to set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19,Status write 1 to set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18,Status write 1 to set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17,Status write 1 to set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16,Status write 1 to set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15,Status write 1 to set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14,Status write 1 to set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13,Status write 1 to set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12,Status write 1 to set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11,Status write 1 to set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10,Status write 1 to set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9,Status write 1 to set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8,Status write 1 to set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7,Status write 1 to set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6,Status write 1 to set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5,Status write 1 to set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4,Status write 1 to set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3,Status write 1 to set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2,Status write 1 to set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1,Status write 1 to set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0,Status write 1 to set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_REG_SYS_2,Status Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM,Status write 1 to set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6,Status write 1 to set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5,Status write 1 to set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4,Status write 1 to set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3,Status write 1 to set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2,Status write 1 to set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1,Status write 1 to set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0,Status write 1 to set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE,Status write 1 to set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET,Status write 1 to set for sys_en_pcie_hot_reset" "0,1"
group.long 0x700++0x0B
line.long 0x00 "PCIE_INTD_STATUS_CLR_REG_SYS_0,Status Clear Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8_CLR,Status write 1 to clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7_CLR,Status write 1 to clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6_CLR,Status write 1 to clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5_CLR,Status write 1 to clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4_CLR,Status write 1 to clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3_CLR,Status write 1 to clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2_CLR,Status write 1 to clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1_CLR,Status write 1 to clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0_CLR,Status write 1 to clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2_CLR,Status write 1 to clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1_CLR,Status write 1 to clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0_CLR,Status write 1 to clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3_CLR,Status write 1 to clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2_CLR,Status write 1 to clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1_CLR,Status write 1 to clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0_CLR,Status write 1 to clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_CLR_REG_SYS_1,Status Clear Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5_CLR,Status write 1 to clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4_CLR,Status write 1 to clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3_CLR,Status write 1 to clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2_CLR,Status write 1 to clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1_CLR,Status write 1 to clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0_CLR,Status write 1 to clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21_CLR,Status write 1 to clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20_CLR,Status write 1 to clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19_CLR,Status write 1 to clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18_CLR,Status write 1 to clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17_CLR,Status write 1 to clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16_CLR,Status write 1 to clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15_CLR,Status write 1 to clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14_CLR,Status write 1 to clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13_CLR,Status write 1 to clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12_CLR,Status write 1 to clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11_CLR,Status write 1 to clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10_CLR,Status write 1 to clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9_CLR,Status write 1 to clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8_CLR,Status write 1 to clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7_CLR,Status write 1 to clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6_CLR,Status write 1 to clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5_CLR,Status write 1 to clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4_CLR,Status write 1 to clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3_CLR,Status write 1 to clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2_CLR,Status write 1 to clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1_CLR,Status write 1 to clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0_CLR,Status write 1 to clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_CLR_REG_SYS_2,Status Clear Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM_CLR,Status write 1 to clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE_CLR,Status write 1 to clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET_CLR,Status write 1 to clear for sys_en_pcie_hot_reset" "0,1"
rgroup.long 0xA80++0x03
line.long 0x00 "PCIE_INTD_INTR_VECTOR_REG_SYS,Interrupt Vector for sys"
tree.end
tree "PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG"
base ad:0x2910000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_INTD_REVISION,Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "PCIE_INTD_EOI_REG,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "PCIE_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_REG_SYS_0,Enable Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8,Enable Set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7,Enable Set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6,Enable Set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5,Enable Set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4,Enable Set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3,Enable Set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2,Enable Set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1,Enable Set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0,Enable Set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2,Enable Set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1,Enable Set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0,Enable Set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3,Enable Set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2,Enable Set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1,Enable Set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0,Enable Set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_REG_SYS_1,Enable Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5,Enable Set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4,Enable Set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3,Enable Set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2,Enable Set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1,Enable Set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0,Enable Set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21,Enable Set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20,Enable Set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19,Enable Set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18,Enable Set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17,Enable Set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16,Enable Set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15,Enable Set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14,Enable Set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13,Enable Set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12,Enable Set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11,Enable Set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10,Enable Set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9,Enable Set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8,Enable Set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7,Enable Set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6,Enable Set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5,Enable Set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4,Enable Set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3,Enable Set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2,Enable Set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1,Enable Set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0,Enable Set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_REG_SYS_2,Enable Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM,Enable Set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6,Enable Set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5,Enable Set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4,Enable Set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3,Enable Set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2,Enable Set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1,Enable Set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0,Enable Set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE,Enable Set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET,Enable Set for sys_en_pcie_hot_reset" "0,1"
group.long 0x300++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_CLR_REG_SYS_0,Enable Clear Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8_CLR,Enable Clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7_CLR,Enable Clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6_CLR,Enable Clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5_CLR,Enable Clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4_CLR,Enable Clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3_CLR,Enable Clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2_CLR,Enable Clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1_CLR,Enable Clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0_CLR,Enable Clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2_CLR,Enable Clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1_CLR,Enable Clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0_CLR,Enable Clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3_CLR,Enable Clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2_CLR,Enable Clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1_CLR,Enable Clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0_CLR,Enable Clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_CLR_REG_SYS_1,Enable Clear Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR,Enable Clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR,Enable Clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR,Enable Clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR,Enable Clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR,Enable Clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR,Enable Clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21_CLR,Enable Clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20_CLR,Enable Clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19_CLR,Enable Clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18_CLR,Enable Clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17_CLR,Enable Clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16_CLR,Enable Clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15_CLR,Enable Clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14_CLR,Enable Clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13_CLR,Enable Clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12_CLR,Enable Clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11_CLR,Enable Clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10_CLR,Enable Clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9_CLR,Enable Clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8_CLR,Enable Clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7_CLR,Enable Clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6_CLR,Enable Clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5_CLR,Enable Clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4_CLR,Enable Clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3_CLR,Enable Clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2_CLR,Enable Clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1_CLR,Enable Clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0_CLR,Enable Clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_CLR_REG_SYS_2,Enable Clear Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM_CLR,Enable Clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6_CLR,Enable Clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5_CLR,Enable Clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4_CLR,Enable Clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3_CLR,Enable Clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2_CLR,Enable Clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1_CLR,Enable Clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0_CLR,Enable Clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE_CLR,Enable Clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET_CLR,Enable Clear for sys_en_pcie_hot_reset" "0,1"
group.long 0x500++0x0B
line.long 0x00 "PCIE_INTD_STATUS_REG_SYS_0,Status Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8,Status write 1 to set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7,Status write 1 to set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6,Status write 1 to set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5,Status write 1 to set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4,Status write 1 to set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3,Status write 1 to set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2,Status write 1 to set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1,Status write 1 to set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0,Status write 1 to set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2,Status write 1 to set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1,Status write 1 to set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0,Status write 1 to set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3,Status write 1 to set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2,Status write 1 to set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1,Status write 1 to set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0,Status write 1 to set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_REG_SYS_1,Status Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5,Status write 1 to set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4,Status write 1 to set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3,Status write 1 to set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2,Status write 1 to set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1,Status write 1 to set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0,Status write 1 to set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21,Status write 1 to set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20,Status write 1 to set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19,Status write 1 to set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18,Status write 1 to set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17,Status write 1 to set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16,Status write 1 to set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15,Status write 1 to set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14,Status write 1 to set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13,Status write 1 to set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12,Status write 1 to set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11,Status write 1 to set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10,Status write 1 to set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9,Status write 1 to set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8,Status write 1 to set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7,Status write 1 to set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6,Status write 1 to set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5,Status write 1 to set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4,Status write 1 to set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3,Status write 1 to set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2,Status write 1 to set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1,Status write 1 to set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0,Status write 1 to set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_REG_SYS_2,Status Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM,Status write 1 to set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6,Status write 1 to set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5,Status write 1 to set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4,Status write 1 to set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3,Status write 1 to set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2,Status write 1 to set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1,Status write 1 to set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0,Status write 1 to set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE,Status write 1 to set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET,Status write 1 to set for sys_en_pcie_hot_reset" "0,1"
group.long 0x700++0x0B
line.long 0x00 "PCIE_INTD_STATUS_CLR_REG_SYS_0,Status Clear Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8_CLR,Status write 1 to clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7_CLR,Status write 1 to clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6_CLR,Status write 1 to clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5_CLR,Status write 1 to clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4_CLR,Status write 1 to clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3_CLR,Status write 1 to clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2_CLR,Status write 1 to clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1_CLR,Status write 1 to clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0_CLR,Status write 1 to clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2_CLR,Status write 1 to clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1_CLR,Status write 1 to clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0_CLR,Status write 1 to clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3_CLR,Status write 1 to clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2_CLR,Status write 1 to clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1_CLR,Status write 1 to clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0_CLR,Status write 1 to clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_CLR_REG_SYS_1,Status Clear Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5_CLR,Status write 1 to clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4_CLR,Status write 1 to clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3_CLR,Status write 1 to clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2_CLR,Status write 1 to clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1_CLR,Status write 1 to clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0_CLR,Status write 1 to clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21_CLR,Status write 1 to clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20_CLR,Status write 1 to clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19_CLR,Status write 1 to clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18_CLR,Status write 1 to clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17_CLR,Status write 1 to clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16_CLR,Status write 1 to clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15_CLR,Status write 1 to clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14_CLR,Status write 1 to clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13_CLR,Status write 1 to clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12_CLR,Status write 1 to clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11_CLR,Status write 1 to clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10_CLR,Status write 1 to clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9_CLR,Status write 1 to clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8_CLR,Status write 1 to clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7_CLR,Status write 1 to clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6_CLR,Status write 1 to clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5_CLR,Status write 1 to clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4_CLR,Status write 1 to clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3_CLR,Status write 1 to clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2_CLR,Status write 1 to clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1_CLR,Status write 1 to clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0_CLR,Status write 1 to clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_CLR_REG_SYS_2,Status Clear Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM_CLR,Status write 1 to clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE_CLR,Status write 1 to clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET_CLR,Status write 1 to clear for sys_en_pcie_hot_reset" "0,1"
rgroup.long 0xA80++0x03
line.long 0x00 "PCIE_INTD_INTR_VECTOR_REG_SYS,Interrupt Vector for sys"
tree.end
tree "PCIE2_CORE_PCIE_INTD_CFG_INTD_CFG"
base ad:0x2920000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_INTD_REVISION,Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "PCIE_INTD_EOI_REG,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "PCIE_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_REG_SYS_0,Enable Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8,Enable Set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7,Enable Set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6,Enable Set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5,Enable Set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4,Enable Set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3,Enable Set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2,Enable Set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1,Enable Set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0,Enable Set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2,Enable Set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1,Enable Set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0,Enable Set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3,Enable Set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2,Enable Set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1,Enable Set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0,Enable Set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_REG_SYS_1,Enable Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5,Enable Set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4,Enable Set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3,Enable Set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2,Enable Set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1,Enable Set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0,Enable Set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21,Enable Set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20,Enable Set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19,Enable Set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18,Enable Set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17,Enable Set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16,Enable Set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15,Enable Set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14,Enable Set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13,Enable Set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12,Enable Set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11,Enable Set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10,Enable Set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9,Enable Set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8,Enable Set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7,Enable Set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6,Enable Set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5,Enable Set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4,Enable Set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3,Enable Set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2,Enable Set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1,Enable Set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0,Enable Set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_REG_SYS_2,Enable Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM,Enable Set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6,Enable Set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5,Enable Set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4,Enable Set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3,Enable Set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2,Enable Set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1,Enable Set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0,Enable Set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE,Enable Set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET,Enable Set for sys_en_pcie_hot_reset" "0,1"
group.long 0x300++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_CLR_REG_SYS_0,Enable Clear Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8_CLR,Enable Clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7_CLR,Enable Clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6_CLR,Enable Clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5_CLR,Enable Clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4_CLR,Enable Clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3_CLR,Enable Clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2_CLR,Enable Clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1_CLR,Enable Clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0_CLR,Enable Clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2_CLR,Enable Clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1_CLR,Enable Clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0_CLR,Enable Clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3_CLR,Enable Clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2_CLR,Enable Clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1_CLR,Enable Clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0_CLR,Enable Clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_CLR_REG_SYS_1,Enable Clear Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR,Enable Clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR,Enable Clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR,Enable Clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR,Enable Clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR,Enable Clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR,Enable Clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21_CLR,Enable Clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20_CLR,Enable Clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19_CLR,Enable Clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18_CLR,Enable Clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17_CLR,Enable Clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16_CLR,Enable Clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15_CLR,Enable Clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14_CLR,Enable Clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13_CLR,Enable Clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12_CLR,Enable Clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11_CLR,Enable Clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10_CLR,Enable Clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9_CLR,Enable Clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8_CLR,Enable Clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7_CLR,Enable Clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6_CLR,Enable Clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5_CLR,Enable Clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4_CLR,Enable Clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3_CLR,Enable Clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2_CLR,Enable Clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1_CLR,Enable Clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0_CLR,Enable Clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_CLR_REG_SYS_2,Enable Clear Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM_CLR,Enable Clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6_CLR,Enable Clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5_CLR,Enable Clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4_CLR,Enable Clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3_CLR,Enable Clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2_CLR,Enable Clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1_CLR,Enable Clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0_CLR,Enable Clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE_CLR,Enable Clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET_CLR,Enable Clear for sys_en_pcie_hot_reset" "0,1"
group.long 0x500++0x0B
line.long 0x00 "PCIE_INTD_STATUS_REG_SYS_0,Status Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8,Status write 1 to set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7,Status write 1 to set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6,Status write 1 to set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5,Status write 1 to set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4,Status write 1 to set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3,Status write 1 to set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2,Status write 1 to set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1,Status write 1 to set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0,Status write 1 to set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2,Status write 1 to set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1,Status write 1 to set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0,Status write 1 to set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3,Status write 1 to set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2,Status write 1 to set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1,Status write 1 to set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0,Status write 1 to set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_REG_SYS_1,Status Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5,Status write 1 to set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4,Status write 1 to set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3,Status write 1 to set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2,Status write 1 to set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1,Status write 1 to set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0,Status write 1 to set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21,Status write 1 to set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20,Status write 1 to set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19,Status write 1 to set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18,Status write 1 to set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17,Status write 1 to set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16,Status write 1 to set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15,Status write 1 to set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14,Status write 1 to set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13,Status write 1 to set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12,Status write 1 to set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11,Status write 1 to set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10,Status write 1 to set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9,Status write 1 to set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8,Status write 1 to set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7,Status write 1 to set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6,Status write 1 to set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5,Status write 1 to set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4,Status write 1 to set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3,Status write 1 to set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2,Status write 1 to set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1,Status write 1 to set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0,Status write 1 to set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_REG_SYS_2,Status Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM,Status write 1 to set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6,Status write 1 to set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5,Status write 1 to set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4,Status write 1 to set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3,Status write 1 to set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2,Status write 1 to set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1,Status write 1 to set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0,Status write 1 to set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE,Status write 1 to set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET,Status write 1 to set for sys_en_pcie_hot_reset" "0,1"
group.long 0x700++0x0B
line.long 0x00 "PCIE_INTD_STATUS_CLR_REG_SYS_0,Status Clear Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8_CLR,Status write 1 to clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7_CLR,Status write 1 to clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6_CLR,Status write 1 to clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5_CLR,Status write 1 to clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4_CLR,Status write 1 to clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3_CLR,Status write 1 to clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2_CLR,Status write 1 to clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1_CLR,Status write 1 to clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0_CLR,Status write 1 to clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2_CLR,Status write 1 to clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1_CLR,Status write 1 to clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0_CLR,Status write 1 to clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3_CLR,Status write 1 to clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2_CLR,Status write 1 to clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1_CLR,Status write 1 to clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0_CLR,Status write 1 to clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_CLR_REG_SYS_1,Status Clear Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5_CLR,Status write 1 to clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4_CLR,Status write 1 to clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3_CLR,Status write 1 to clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2_CLR,Status write 1 to clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1_CLR,Status write 1 to clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0_CLR,Status write 1 to clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21_CLR,Status write 1 to clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20_CLR,Status write 1 to clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19_CLR,Status write 1 to clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18_CLR,Status write 1 to clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17_CLR,Status write 1 to clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16_CLR,Status write 1 to clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15_CLR,Status write 1 to clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14_CLR,Status write 1 to clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13_CLR,Status write 1 to clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12_CLR,Status write 1 to clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11_CLR,Status write 1 to clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10_CLR,Status write 1 to clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9_CLR,Status write 1 to clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8_CLR,Status write 1 to clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7_CLR,Status write 1 to clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6_CLR,Status write 1 to clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5_CLR,Status write 1 to clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4_CLR,Status write 1 to clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3_CLR,Status write 1 to clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2_CLR,Status write 1 to clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1_CLR,Status write 1 to clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0_CLR,Status write 1 to clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_CLR_REG_SYS_2,Status Clear Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM_CLR,Status write 1 to clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE_CLR,Status write 1 to clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET_CLR,Status write 1 to clear for sys_en_pcie_hot_reset" "0,1"
rgroup.long 0xA80++0x03
line.long 0x00 "PCIE_INTD_INTR_VECTOR_REG_SYS,Interrupt Vector for sys"
tree.end
tree "PCIE3_CORE_PCIE_INTD_CFG_INTD_CFG"
base ad:0x2930000
rgroup.long 0x00++0x03
line.long 0x00 "PCIE_INTD_REVISION,Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "PCIE_INTD_EOI_REG,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "PCIE_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_REG_SYS_0,Enable Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8,Enable Set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7,Enable Set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6,Enable Set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5,Enable Set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4,Enable Set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3,Enable Set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2,Enable Set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1,Enable Set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0,Enable Set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2,Enable Set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1,Enable Set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0,Enable Set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3,Enable Set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2,Enable Set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1,Enable Set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0,Enable Set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_REG_SYS_1,Enable Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5,Enable Set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4,Enable Set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3,Enable Set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2,Enable Set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1,Enable Set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0,Enable Set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21,Enable Set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20,Enable Set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19,Enable Set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18,Enable Set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17,Enable Set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16,Enable Set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15,Enable Set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14,Enable Set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13,Enable Set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12,Enable Set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11,Enable Set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10,Enable Set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9,Enable Set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8,Enable Set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7,Enable Set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6,Enable Set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5,Enable Set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4,Enable Set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3,Enable Set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2,Enable Set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1,Enable Set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0,Enable Set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_REG_SYS_2,Enable Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM,Enable Set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6,Enable Set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5,Enable Set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4,Enable Set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3,Enable Set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2,Enable Set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1,Enable Set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0,Enable Set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE,Enable Set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET,Enable Set for sys_en_pcie_hot_reset" "0,1"
group.long 0x300++0x0B
line.long 0x00 "PCIE_INTD_ENABLE_CLR_REG_SYS_0,Enable Clear Register 0"
bitfld.long 0x00 24. "ENABLE_SYS_EN_PCIE_ASF_8_CLR,Enable Clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "ENABLE_SYS_EN_PCIE_ASF_7_CLR,Enable Clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "ENABLE_SYS_EN_PCIE_ASF_6_CLR,Enable Clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_SYS_EN_PCIE_ASF_5_CLR,Enable Clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "ENABLE_SYS_EN_PCIE_ASF_4_CLR,Enable Clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "ENABLE_SYS_EN_PCIE_ASF_3_CLR,Enable Clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_SYS_EN_PCIE_ASF_2_CLR,Enable Clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "ENABLE_SYS_EN_PCIE_ASF_1_CLR,Enable Clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "ENABLE_SYS_EN_PCIE_ASF_0_CLR,Enable Clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_SYS_EN_PCIE_ERROR_2_CLR,Enable Clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "ENABLE_SYS_EN_PCIE_ERROR_1_CLR,Enable Clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "ENABLE_SYS_EN_PCIE_ERROR_0_CLR,Enable Clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_SYS_EN_PCIE_LEGACY_3_CLR,Enable Clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "ENABLE_SYS_EN_PCIE_LEGACY_2_CLR,Enable Clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "ENABLE_SYS_EN_PCIE_LEGACY_1_CLR,Enable Clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_SYS_EN_PCIE_LEGACY_0_CLR,Enable Clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_ENABLE_CLR_REG_SYS_1,Enable Clear Register 1"
bitfld.long 0x04 29. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_5_CLR,Enable Clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_4_CLR,Enable Clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_3_CLR,Enable Clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_2_CLR,Enable Clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_1_CLR,Enable Clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "ENABLE_SYS_EN_PCIE_DOWNSTREAM_0_CLR,Enable Clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_SYS_EN_PCIE_FLR_21_CLR,Enable Clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "ENABLE_SYS_EN_PCIE_FLR_20_CLR,Enable Clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "ENABLE_SYS_EN_PCIE_FLR_19_CLR,Enable Clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_SYS_EN_PCIE_FLR_18_CLR,Enable Clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "ENABLE_SYS_EN_PCIE_FLR_17_CLR,Enable Clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "ENABLE_SYS_EN_PCIE_FLR_16_CLR,Enable Clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_SYS_EN_PCIE_FLR_15_CLR,Enable Clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "ENABLE_SYS_EN_PCIE_FLR_14_CLR,Enable Clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "ENABLE_SYS_EN_PCIE_FLR_13_CLR,Enable Clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_SYS_EN_PCIE_FLR_12_CLR,Enable Clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "ENABLE_SYS_EN_PCIE_FLR_11_CLR,Enable Clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "ENABLE_SYS_EN_PCIE_FLR_10_CLR,Enable Clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_SYS_EN_PCIE_FLR_9_CLR,Enable Clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "ENABLE_SYS_EN_PCIE_FLR_8_CLR,Enable Clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "ENABLE_SYS_EN_PCIE_FLR_7_CLR,Enable Clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_SYS_EN_PCIE_FLR_6_CLR,Enable Clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "ENABLE_SYS_EN_PCIE_FLR_5_CLR,Enable Clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "ENABLE_SYS_EN_PCIE_FLR_4_CLR,Enable Clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_SYS_EN_PCIE_FLR_3_CLR,Enable Clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "ENABLE_SYS_EN_PCIE_FLR_2_CLR,Enable Clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "ENABLE_SYS_EN_PCIE_FLR_1_CLR,Enable Clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_SYS_EN_PCIE_FLR_0_CLR,Enable Clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_ENABLE_CLR_REG_SYS_2,Enable Clear Register 2"
bitfld.long 0x08 24. "ENABLE_SYS_EN_PCIE_PTM_CLR,Enable Clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "ENABLE_SYS_EN_PCIE_PWR_STATE_6_CLR,Enable Clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "ENABLE_SYS_EN_PCIE_PWR_STATE_5_CLR,Enable Clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "ENABLE_SYS_EN_PCIE_PWR_STATE_4_CLR,Enable Clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "ENABLE_SYS_EN_PCIE_PWR_STATE_3_CLR,Enable Clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "ENABLE_SYS_EN_PCIE_PWR_STATE_2_CLR,Enable Clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_SYS_EN_PCIE_PWR_STATE_1_CLR,Enable Clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "ENABLE_SYS_EN_PCIE_PWR_STATE_0_CLR,Enable Clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "ENABLE_SYS_EN_PCIE_LINK_STATE_CLR,Enable Clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_SYS_EN_PCIE_HOT_RESET_CLR,Enable Clear for sys_en_pcie_hot_reset" "0,1"
group.long 0x500++0x0B
line.long 0x00 "PCIE_INTD_STATUS_REG_SYS_0,Status Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8,Status write 1 to set for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7,Status write 1 to set for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6,Status write 1 to set for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5,Status write 1 to set for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4,Status write 1 to set for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3,Status write 1 to set for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2,Status write 1 to set for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1,Status write 1 to set for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0,Status write 1 to set for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2,Status write 1 to set for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1,Status write 1 to set for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0,Status write 1 to set for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3,Status write 1 to set for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2,Status write 1 to set for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1,Status write 1 to set for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0,Status write 1 to set for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_REG_SYS_1,Status Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5,Status write 1 to set for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4,Status write 1 to set for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3,Status write 1 to set for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2,Status write 1 to set for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1,Status write 1 to set for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0,Status write 1 to set for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21,Status write 1 to set for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20,Status write 1 to set for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19,Status write 1 to set for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18,Status write 1 to set for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17,Status write 1 to set for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16,Status write 1 to set for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15,Status write 1 to set for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14,Status write 1 to set for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13,Status write 1 to set for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12,Status write 1 to set for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11,Status write 1 to set for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10,Status write 1 to set for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9,Status write 1 to set for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8,Status write 1 to set for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7,Status write 1 to set for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6,Status write 1 to set for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5,Status write 1 to set for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4,Status write 1 to set for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3,Status write 1 to set for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2,Status write 1 to set for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1,Status write 1 to set for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0,Status write 1 to set for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_REG_SYS_2,Status Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM,Status write 1 to set for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6,Status write 1 to set for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5,Status write 1 to set for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4,Status write 1 to set for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3,Status write 1 to set for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2,Status write 1 to set for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1,Status write 1 to set for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0,Status write 1 to set for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE,Status write 1 to set for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET,Status write 1 to set for sys_en_pcie_hot_reset" "0,1"
group.long 0x700++0x0B
line.long 0x00 "PCIE_INTD_STATUS_CLR_REG_SYS_0,Status Clear Register 0"
bitfld.long 0x00 24. "STATUS_SYS_PCIE_ASF_8_CLR,Status write 1 to clear for sys_en_pcie_asf_8" "0,1"
bitfld.long 0x00 23. "STATUS_SYS_PCIE_ASF_7_CLR,Status write 1 to clear for sys_en_pcie_asf_7" "0,1"
bitfld.long 0x00 22. "STATUS_SYS_PCIE_ASF_6_CLR,Status write 1 to clear for sys_en_pcie_asf_6" "0,1"
newline
bitfld.long 0x00 21. "STATUS_SYS_PCIE_ASF_5_CLR,Status write 1 to clear for sys_en_pcie_asf_5" "0,1"
bitfld.long 0x00 20. "STATUS_SYS_PCIE_ASF_4_CLR,Status write 1 to clear for sys_en_pcie_asf_4" "0,1"
bitfld.long 0x00 19. "STATUS_SYS_PCIE_ASF_3_CLR,Status write 1 to clear for sys_en_pcie_asf_3" "0,1"
newline
bitfld.long 0x00 18. "STATUS_SYS_PCIE_ASF_2_CLR,Status write 1 to clear for sys_en_pcie_asf_2" "0,1"
bitfld.long 0x00 17. "STATUS_SYS_PCIE_ASF_1_CLR,Status write 1 to clear for sys_en_pcie_asf_1" "0,1"
bitfld.long 0x00 16. "STATUS_SYS_PCIE_ASF_0_CLR,Status write 1 to clear for sys_en_pcie_asf_0" "0,1"
newline
bitfld.long 0x00 10. "STATUS_SYS_PCIE_ERROR_2_CLR,Status write 1 to clear for sys_en_pcie_error_2" "0,1"
bitfld.long 0x00 9. "STATUS_SYS_PCIE_ERROR_1_CLR,Status write 1 to clear for sys_en_pcie_error_1" "0,1"
bitfld.long 0x00 8. "STATUS_SYS_PCIE_ERROR_0_CLR,Status write 1 to clear for sys_en_pcie_error_0" "0,1"
newline
bitfld.long 0x00 3. "STATUS_SYS_PCIE_LEGACY_3_CLR,Status write 1 to clear for sys_en_pcie_legacy_3" "0,1"
bitfld.long 0x00 2. "STATUS_SYS_PCIE_LEGACY_2_CLR,Status write 1 to clear for sys_en_pcie_legacy_2" "0,1"
bitfld.long 0x00 1. "STATUS_SYS_PCIE_LEGACY_1_CLR,Status write 1 to clear for sys_en_pcie_legacy_1" "0,1"
newline
bitfld.long 0x00 0. "STATUS_SYS_PCIE_LEGACY_0_CLR,Status write 1 to clear for sys_en_pcie_legacy_0" "0,1"
line.long 0x04 "PCIE_INTD_STATUS_CLR_REG_SYS_1,Status Clear Register 1"
bitfld.long 0x04 29. "STATUS_SYS_PCIE_DOWNSTREAM_5_CLR,Status write 1 to clear for sys_en_pcie_downstream_5" "0,1"
bitfld.long 0x04 28. "STATUS_SYS_PCIE_DOWNSTREAM_4_CLR,Status write 1 to clear for sys_en_pcie_downstream_4" "0,1"
bitfld.long 0x04 27. "STATUS_SYS_PCIE_DOWNSTREAM_3_CLR,Status write 1 to clear for sys_en_pcie_downstream_3" "0,1"
newline
bitfld.long 0x04 26. "STATUS_SYS_PCIE_DOWNSTREAM_2_CLR,Status write 1 to clear for sys_en_pcie_downstream_2" "0,1"
bitfld.long 0x04 25. "STATUS_SYS_PCIE_DOWNSTREAM_1_CLR,Status write 1 to clear for sys_en_pcie_downstream_1" "0,1"
bitfld.long 0x04 24. "STATUS_SYS_PCIE_DOWNSTREAM_0_CLR,Status write 1 to clear for sys_en_pcie_downstream_0" "0,1"
newline
bitfld.long 0x04 21. "STATUS_SYS_PCIE_FLR_21_CLR,Status write 1 to clear for sys_en_pcie_flr_21" "0,1"
bitfld.long 0x04 20. "STATUS_SYS_PCIE_FLR_20_CLR,Status write 1 to clear for sys_en_pcie_flr_20" "0,1"
bitfld.long 0x04 19. "STATUS_SYS_PCIE_FLR_19_CLR,Status write 1 to clear for sys_en_pcie_flr_19" "0,1"
newline
bitfld.long 0x04 18. "STATUS_SYS_PCIE_FLR_18_CLR,Status write 1 to clear for sys_en_pcie_flr_18" "0,1"
bitfld.long 0x04 17. "STATUS_SYS_PCIE_FLR_17_CLR,Status write 1 to clear for sys_en_pcie_flr_17" "0,1"
bitfld.long 0x04 16. "STATUS_SYS_PCIE_FLR_16_CLR,Status write 1 to clear for sys_en_pcie_flr_16" "0,1"
newline
bitfld.long 0x04 15. "STATUS_SYS_PCIE_FLR_15_CLR,Status write 1 to clear for sys_en_pcie_flr_15" "0,1"
bitfld.long 0x04 14. "STATUS_SYS_PCIE_FLR_14_CLR,Status write 1 to clear for sys_en_pcie_flr_14" "0,1"
bitfld.long 0x04 13. "STATUS_SYS_PCIE_FLR_13_CLR,Status write 1 to clear for sys_en_pcie_flr_13" "0,1"
newline
bitfld.long 0x04 12. "STATUS_SYS_PCIE_FLR_12_CLR,Status write 1 to clear for sys_en_pcie_flr_12" "0,1"
bitfld.long 0x04 11. "STATUS_SYS_PCIE_FLR_11_CLR,Status write 1 to clear for sys_en_pcie_flr_11" "0,1"
bitfld.long 0x04 10. "STATUS_SYS_PCIE_FLR_10_CLR,Status write 1 to clear for sys_en_pcie_flr_10" "0,1"
newline
bitfld.long 0x04 9. "STATUS_SYS_PCIE_FLR_9_CLR,Status write 1 to clear for sys_en_pcie_flr_9" "0,1"
bitfld.long 0x04 8. "STATUS_SYS_PCIE_FLR_8_CLR,Status write 1 to clear for sys_en_pcie_flr_8" "0,1"
bitfld.long 0x04 7. "STATUS_SYS_PCIE_FLR_7_CLR,Status write 1 to clear for sys_en_pcie_flr_7" "0,1"
newline
bitfld.long 0x04 6. "STATUS_SYS_PCIE_FLR_6_CLR,Status write 1 to clear for sys_en_pcie_flr_6" "0,1"
bitfld.long 0x04 5. "STATUS_SYS_PCIE_FLR_5_CLR,Status write 1 to clear for sys_en_pcie_flr_5" "0,1"
bitfld.long 0x04 4. "STATUS_SYS_PCIE_FLR_4_CLR,Status write 1 to clear for sys_en_pcie_flr_4" "0,1"
newline
bitfld.long 0x04 3. "STATUS_SYS_PCIE_FLR_3_CLR,Status write 1 to clear for sys_en_pcie_flr_3" "0,1"
bitfld.long 0x04 2. "STATUS_SYS_PCIE_FLR_2_CLR,Status write 1 to clear for sys_en_pcie_flr_2" "0,1"
bitfld.long 0x04 1. "STATUS_SYS_PCIE_FLR_1_CLR,Status write 1 to clear for sys_en_pcie_flr_1" "0,1"
newline
bitfld.long 0x04 0. "STATUS_SYS_PCIE_FLR_0_CLR,Status write 1 to clear for sys_en_pcie_flr_0" "0,1"
line.long 0x08 "PCIE_INTD_STATUS_CLR_REG_SYS_2,Status Clear Register 2"
bitfld.long 0x08 24. "STATUS_SYS_PCIE_PTM_CLR,Status write 1 to clear for sys_en_pcie_ptm" "0,1"
bitfld.long 0x08 14. "STATUS_SYS_PCIE_PWR_STATE_6_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_6" "0,1"
bitfld.long 0x08 13. "STATUS_SYS_PCIE_PWR_STATE_5_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_5" "0,1"
newline
bitfld.long 0x08 12. "STATUS_SYS_PCIE_PWR_STATE_4_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_4" "0,1"
bitfld.long 0x08 11. "STATUS_SYS_PCIE_PWR_STATE_3_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_3" "0,1"
bitfld.long 0x08 10. "STATUS_SYS_PCIE_PWR_STATE_2_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_2" "0,1"
newline
bitfld.long 0x08 9. "STATUS_SYS_PCIE_PWR_STATE_1_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_1" "0,1"
bitfld.long 0x08 8. "STATUS_SYS_PCIE_PWR_STATE_0_CLR,Status write 1 to clear for sys_en_pcie_pwr_state_0" "0,1"
bitfld.long 0x08 1. "STATUS_SYS_PCIE_LINK_STATE_CLR,Status write 1 to clear for sys_en_pcie_link_state" "0,1"
newline
bitfld.long 0x08 0. "STATUS_SYS_PCIE_HOT_RESET_CLR,Status write 1 to clear for sys_en_pcie_hot_reset" "0,1"
rgroup.long 0xA80++0x03
line.long 0x00 "PCIE_INTD_INTR_VECTOR_REG_SYS,Interrupt Vector for sys"
tree.end
tree.end
tree "PCIE_LP_DAT0"
tree "PCIE0_DAT0"
base ad:0x10000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE1_DAT0"
base ad:0x18000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE2_DAT0"
base ad:0x4400000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE3_DAT0"
base ad:0x4410000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region0 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree.end
tree "PCIE_LP_DAT1"
tree "PCIE0_DAT1"
base ad:0x4000000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE1_DAT1"
base ad:0x4100000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE2_DAT1"
base ad:0x4200000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree "PCIE3_DAT1"
base ad:0x4300000000
group.long 0x00++0x03
line.long 0x00 "PCIE_LP_DATA_MEM_Y,PCIE data region1 Offset = 0h + (y * 4h); where y = 0h to 03FFFFFFh"
tree.end
tree.end
tree "PCIE_USER_CFG"
tree "PCIE0_CORE_USER_CFG_USER_CFG"
base ad:0x2907000
rgroup.long 0x00++0xC3
line.long 0x00 "PCIE_USER_REVID,Module ID register"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_USER_CMD_STATUS,Command Status register"
bitfld.long 0x04 0. "LINK_TRAINING_ENABLE,This bit must be set to 1 to enable the LTSSM to bring up the link" "0,1"
line.long 0x08 "PCIE_USER_RSTCMD,Reset Command and Status register"
bitfld.long 0x08 0. "INIT_HOT_RESET,When this bit is set to 1'b1 in the RP mode the core initiates a Hot Reset sequence on the PCIe link" "0,1"
line.long 0x0C "PCIE_USER_INITCFG,Initialization configuration register"
bitfld.long 0x0C 24. "CONFIG_ENABLE,When this bit is set to 0 in the EP mode the Controller will generate a CRS Completion in response to Configuration Requests" "0,1"
bitfld.long 0x0C 22.--23. "VC_COUNT,Number of VCs configured" "0,1,2,3"
hexmask.long.byte 0x0C 15.--21. 1. "MAX_EVAL_ITERATION,Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00"
newline
bitfld.long 0x0C 14. "BYPASS_PHASE23,This MMR should be programmed during system boot or initialization" "0,1"
bitfld.long 0x0C 13. "BYPASS_REMOTE_TX_EQUALIZATION,This MMR should be programmed during system boot or initialization" "0,1"
hexmask.long.word 0x0C 2.--12. 1. "SUPPORTED_PRESET,This MMR should be programmed during system boot or initialization"
newline
bitfld.long 0x0C 1. "DISABLE_GEN3_DC_BALANCE,This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed" "0,1"
bitfld.long 0x0C 0. "SRIS_ENABLE,Should be set as per the System Reference Clocking Implementation" "0,1"
line.long 0x10 "PCIE_USER_PMCMD,Power Management command register"
bitfld.long 0x10 2. "POWER_STATE_CHANGE_ACK,Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT when it is ready to transition to the low-power state requested by the configuration write request" "0,1"
bitfld.long 0x10 1. "CLIENT_REQ_EXIT_L1_SUBSTATE,Client logic can trigger an explicit L" "0,1"
bitfld.long 0x10 0. "CLIENT_REQ_EXIT_L1,Client logic can trigger an explicit L1 exit by setting this bit" "0,1"
line.long 0x14 "PCIE_USER_LINKSTATUS,Link Status register"
bitfld.long 0x14 24.--29. "LTSSM_STATE,Current state of the Link Training and Status State Machine within the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 16.--23. 1. "POWER_STATE_CHANGE_FUNCTION_NUM,Function number of the function for which a power state change occurred"
bitfld.long 0x14 12.--14. "L1_PM_SUBSTATE,This register provides the current state of the L1 PM substates state machine" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8.--11. "LINK_POWER_STATE,Current power state of the PCIe link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 3.--4. "NEGOTIATED_SPEED,Current operating speed of the link is as follows" "0,1,2,3"
bitfld.long 0x14 2. "NEGOTIATED_LINK_WIDTH,Current link width are as follows" "0,1"
newline
bitfld.long 0x14 0.--1. "LINK_STATUS,Status of the PCI Express link" "0,1,2,3"
line.long 0x18 "PCIE_USER_LEGACY_INTR_SET,Legacy interrupt set register"
bitfld.long 0x18 3. "INTD_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 2. "INTC_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 1. "INTB_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
newline
bitfld.long 0x18 0. "INTA_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
line.long 0x1C "PCIE_USER_LEGACY_INT_PENDING,Legacy interrupt pending set register"
bitfld.long 0x1C 0.--5. "INT_PENDING_STATUS,When using legacy interrupts this input is used to indicate the interrupt pending status of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "PCIE_USER_MSI_STAT,MSI status register"
bitfld.long 0x20 0.--5. "MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "PCIE_USER_MSI_VECTOR,MSI vector register"
hexmask.long.tbyte 0x24 0.--17. 1. "MSI_VECTOR_COUNT,When the core is configured in the EndPoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions"
line.long 0x28 "PCIE_USER_MSI_MASK_PF0,PF0 MSI mask register"
line.long 0x2C "PCIE_USER_MSI_MASK_PF1,PF1 MSI mask register"
line.long 0x30 "PCIE_USER_MSI_MASK_PF2,PF2 MSI mask register"
line.long 0x34 "PCIE_USER_MSI_MASK_PF3,PF3 MSI mask register"
line.long 0x38 "PCIE_USER_MSI_MASK_PF4,PF4 MSI mask register"
line.long 0x3C "PCIE_USER_MSI_MASK_PF5,PF5 MSI mask register"
line.long 0x40 "PCIE_USER_MSI_PENDING_STATUS_PF0,PF0 MSI pending status input register"
line.long 0x44 "PCIE_USER_MSI_PENDING_STATUS_PF1,PF1 MSI pending status input register"
line.long 0x48 "PCIE_USER_MSI_PENDING_STATUS_PF2,PF2 MSI pending status input register"
line.long 0x4C "PCIE_USER_MSI_PENDING_STATUS_PF3,PF3 MSI pending status input register"
line.long 0x50 "PCIE_USER_MSI_PENDING_STATUS_PF4,PF4 MSI pending status input register"
line.long 0x54 "PCIE_USER_MSI_PENDING_STATUS_PF5,PF5 MSI pending status input register"
line.long 0x58 "PCIE_USER_MSI_STAT_VF,MSI_VF status register"
hexmask.long.word 0x58 0.--15. 1. "VF_MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions"
line.long 0x5C "PCIE_USER_MSI_VECTOR0_VF,MSI_VF vector count register0"
hexmask.long.tbyte 0x5C 0.--23. 1. "VF_MSI_VECTOR_COUNT0,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7"
line.long 0x60 "PCIE_USER_MSI_VECTOR1_VF,MSI_VF vector count register1"
hexmask.long.tbyte 0x60 0.--23. 1. "VF_MSI_VECTOR_COUNT1,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15"
line.long 0x64 "PCIE_USER_MSI_MASK_VF0,VF0MSI mask register"
line.long 0x68 "PCIE_USER_MSI_MASK_VF1,VF1MSI mask register"
line.long 0x6C "PCIE_USER_MSI_MASK_VF2,VF2MSI mask register"
line.long 0x70 "PCIE_USER_MSI_MASK_VF3,VF3MSI mask register"
line.long 0x74 "PCIE_USER_MSI_MASK_VF4,VF4MSI mask register"
line.long 0x78 "PCIE_USER_MSI_MASK_VF5,VF5MSI mask register"
line.long 0x7C "PCIE_USER_MSI_MASK_VF6,VF6MSI mask register"
line.long 0x80 "PCIE_USER_MSI_MASK_VF7,VF7MSI mask register"
line.long 0x84 "PCIE_USER_MSI_MASK_VF8,VF8MSI mask register"
line.long 0x88 "PCIE_USER_MSI_MASK_VF9,VF9MSI mask register"
line.long 0x8C "PCIE_USER_MSI_MASK_VF10,VF10MSI mask register"
line.long 0x90 "PCIE_USER_MSI_MASK_VF11,VF11MSI mask register"
line.long 0x94 "PCIE_USER_MSI_MASK_VF12,VF12MSI mask register"
line.long 0x98 "PCIE_USER_MSI_MASK_VF13,VF13MSI mask register"
line.long 0x9C "PCIE_USER_MSI_MASK_VF14,VF14MSI mask register"
line.long 0xA0 "PCIE_USER_MSI_MASK_VF15,VF15MSI mask register"
line.long 0xA4 "PCIE_USER_MSIX_STAT,MSIX status register"
bitfld.long 0xA4 0.--5. "MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "PCIE_USER_MSIX_MASK,MSIX mask register"
bitfld.long 0xA8 0.--5. "MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xAC "PCIE_USER_MSIX_STAT_VF,Virtual Function MSIX status register"
hexmask.long.word 0xAC 0.--15. 1. "VF_MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0 Bit1 represents the MSIX Enable for Virtual Function 1 and so on"
line.long 0xB0 "PCIE_USER_MSIX_MASK_VF,Virtual Function MSIX mask register"
hexmask.long.word 0xB0 0.--15. 1. "VF_MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions"
line.long 0xB4 "PCIE_USER_FLR_DONE,Physical Function-Level Reset Done register"
bitfld.long 0xB4 0.--5. "FLR_DONE,These bits are connected to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xB8 "PCIE_USER_VF_FLR_DONE,Virtual Function-Level Reset Done register"
hexmask.long.word 0xB8 0.--15. 1. "VF_FLR_DONE,These bits are connected to"
line.long 0xBC "PCIE_USER_PTM_TIMER_LOW,PTM timer value lower 32-bits"
line.long 0xC0 "PCIE_USER_PTM_TIMER_HIGH,PTM timer value upper 32-bits"
tree.end
tree "PCIE1_CORE_USER_CFG_USER_CFG"
base ad:0x2917000
rgroup.long 0x00++0xC3
line.long 0x00 "PCIE_USER_REVID,Module ID register"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_USER_CMD_STATUS,Command Status register"
bitfld.long 0x04 0. "LINK_TRAINING_ENABLE,This bit must be set to 1 to enable the LTSSM to bring up the link" "0,1"
line.long 0x08 "PCIE_USER_RSTCMD,Reset Command and Status register"
bitfld.long 0x08 0. "INIT_HOT_RESET,When this bit is set to 1'b1 in the RP mode the core initiates a Hot Reset sequence on the PCIe link" "0,1"
line.long 0x0C "PCIE_USER_INITCFG,Initialization configuration register"
bitfld.long 0x0C 24. "CONFIG_ENABLE,When this bit is set to 0 in the EP mode the Controller will generate a CRS Completion in response to Configuration Requests" "0,1"
bitfld.long 0x0C 22.--23. "VC_COUNT,Number of VCs configured" "0,1,2,3"
hexmask.long.byte 0x0C 15.--21. 1. "MAX_EVAL_ITERATION,Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00"
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bitfld.long 0x0C 14. "BYPASS_PHASE23,This MMR should be programmed during system boot or initialization" "0,1"
bitfld.long 0x0C 13. "BYPASS_REMOTE_TX_EQUALIZATION,This MMR should be programmed during system boot or initialization" "0,1"
hexmask.long.word 0x0C 2.--12. 1. "SUPPORTED_PRESET,This MMR should be programmed during system boot or initialization"
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bitfld.long 0x0C 1. "DISABLE_GEN3_DC_BALANCE,This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed" "0,1"
bitfld.long 0x0C 0. "SRIS_ENABLE,Should be set as per the System Reference Clocking Implementation" "0,1"
line.long 0x10 "PCIE_USER_PMCMD,Power Management command register"
bitfld.long 0x10 2. "POWER_STATE_CHANGE_ACK,Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT when it is ready to transition to the low-power state requested by the configuration write request" "0,1"
bitfld.long 0x10 1. "CLIENT_REQ_EXIT_L1_SUBSTATE,Client logic can trigger an explicit L" "0,1"
bitfld.long 0x10 0. "CLIENT_REQ_EXIT_L1,Client logic can trigger an explicit L1 exit by setting this bit" "0,1"
line.long 0x14 "PCIE_USER_LINKSTATUS,Link Status register"
bitfld.long 0x14 24.--29. "LTSSM_STATE,Current state of the Link Training and Status State Machine within the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 16.--23. 1. "POWER_STATE_CHANGE_FUNCTION_NUM,Function number of the function for which a power state change occurred"
bitfld.long 0x14 12.--14. "L1_PM_SUBSTATE,This register provides the current state of the L1 PM substates state machine" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8.--11. "LINK_POWER_STATE,Current power state of the PCIe link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 3.--4. "NEGOTIATED_SPEED,Current operating speed of the link is as follows" "0,1,2,3"
bitfld.long 0x14 2. "NEGOTIATED_LINK_WIDTH,Current link width are as follows" "0,1"
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bitfld.long 0x14 0.--1. "LINK_STATUS,Status of the PCI Express link" "0,1,2,3"
line.long 0x18 "PCIE_USER_LEGACY_INTR_SET,Legacy interrupt set register"
bitfld.long 0x18 3. "INTD_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 2. "INTC_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 1. "INTB_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
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bitfld.long 0x18 0. "INTA_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
line.long 0x1C "PCIE_USER_LEGACY_INT_PENDING,Legacy interrupt pending set register"
bitfld.long 0x1C 0.--5. "INT_PENDING_STATUS,When using legacy interrupts this input is used to indicate the interrupt pending status of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "PCIE_USER_MSI_STAT,MSI status register"
bitfld.long 0x20 0.--5. "MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "PCIE_USER_MSI_VECTOR,MSI vector register"
hexmask.long.tbyte 0x24 0.--17. 1. "MSI_VECTOR_COUNT,When the core is configured in the EndPoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions"
line.long 0x28 "PCIE_USER_MSI_MASK_PF0,PF0 MSI mask register"
line.long 0x2C "PCIE_USER_MSI_MASK_PF1,PF1 MSI mask register"
line.long 0x30 "PCIE_USER_MSI_MASK_PF2,PF2 MSI mask register"
line.long 0x34 "PCIE_USER_MSI_MASK_PF3,PF3 MSI mask register"
line.long 0x38 "PCIE_USER_MSI_MASK_PF4,PF4 MSI mask register"
line.long 0x3C "PCIE_USER_MSI_MASK_PF5,PF5 MSI mask register"
line.long 0x40 "PCIE_USER_MSI_PENDING_STATUS_PF0,PF0 MSI pending status input register"
line.long 0x44 "PCIE_USER_MSI_PENDING_STATUS_PF1,PF1 MSI pending status input register"
line.long 0x48 "PCIE_USER_MSI_PENDING_STATUS_PF2,PF2 MSI pending status input register"
line.long 0x4C "PCIE_USER_MSI_PENDING_STATUS_PF3,PF3 MSI pending status input register"
line.long 0x50 "PCIE_USER_MSI_PENDING_STATUS_PF4,PF4 MSI pending status input register"
line.long 0x54 "PCIE_USER_MSI_PENDING_STATUS_PF5,PF5 MSI pending status input register"
line.long 0x58 "PCIE_USER_MSI_STAT_VF,MSI_VF status register"
hexmask.long.word 0x58 0.--15. 1. "VF_MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions"
line.long 0x5C "PCIE_USER_MSI_VECTOR0_VF,MSI_VF vector count register0"
hexmask.long.tbyte 0x5C 0.--23. 1. "VF_MSI_VECTOR_COUNT0,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7"
line.long 0x60 "PCIE_USER_MSI_VECTOR1_VF,MSI_VF vector count register1"
hexmask.long.tbyte 0x60 0.--23. 1. "VF_MSI_VECTOR_COUNT1,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15"
line.long 0x64 "PCIE_USER_MSI_MASK_VF0,VF0MSI mask register"
line.long 0x68 "PCIE_USER_MSI_MASK_VF1,VF1MSI mask register"
line.long 0x6C "PCIE_USER_MSI_MASK_VF2,VF2MSI mask register"
line.long 0x70 "PCIE_USER_MSI_MASK_VF3,VF3MSI mask register"
line.long 0x74 "PCIE_USER_MSI_MASK_VF4,VF4MSI mask register"
line.long 0x78 "PCIE_USER_MSI_MASK_VF5,VF5MSI mask register"
line.long 0x7C "PCIE_USER_MSI_MASK_VF6,VF6MSI mask register"
line.long 0x80 "PCIE_USER_MSI_MASK_VF7,VF7MSI mask register"
line.long 0x84 "PCIE_USER_MSI_MASK_VF8,VF8MSI mask register"
line.long 0x88 "PCIE_USER_MSI_MASK_VF9,VF9MSI mask register"
line.long 0x8C "PCIE_USER_MSI_MASK_VF10,VF10MSI mask register"
line.long 0x90 "PCIE_USER_MSI_MASK_VF11,VF11MSI mask register"
line.long 0x94 "PCIE_USER_MSI_MASK_VF12,VF12MSI mask register"
line.long 0x98 "PCIE_USER_MSI_MASK_VF13,VF13MSI mask register"
line.long 0x9C "PCIE_USER_MSI_MASK_VF14,VF14MSI mask register"
line.long 0xA0 "PCIE_USER_MSI_MASK_VF15,VF15MSI mask register"
line.long 0xA4 "PCIE_USER_MSIX_STAT,MSIX status register"
bitfld.long 0xA4 0.--5. "MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "PCIE_USER_MSIX_MASK,MSIX mask register"
bitfld.long 0xA8 0.--5. "MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xAC "PCIE_USER_MSIX_STAT_VF,Virtual Function MSIX status register"
hexmask.long.word 0xAC 0.--15. 1. "VF_MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0 Bit1 represents the MSIX Enable for Virtual Function 1 and so on"
line.long 0xB0 "PCIE_USER_MSIX_MASK_VF,Virtual Function MSIX mask register"
hexmask.long.word 0xB0 0.--15. 1. "VF_MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions"
line.long 0xB4 "PCIE_USER_FLR_DONE,Physical Function-Level Reset Done register"
bitfld.long 0xB4 0.--5. "FLR_DONE,These bits are connected to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xB8 "PCIE_USER_VF_FLR_DONE,Virtual Function-Level Reset Done register"
hexmask.long.word 0xB8 0.--15. 1. "VF_FLR_DONE,These bits are connected to"
line.long 0xBC "PCIE_USER_PTM_TIMER_LOW,PTM timer value lower 32-bits"
line.long 0xC0 "PCIE_USER_PTM_TIMER_HIGH,PTM timer value upper 32-bits"
tree.end
tree "PCIE2_CORE_USER_CFG_USER_CFG"
base ad:0x2927000
rgroup.long 0x00++0xC3
line.long 0x00 "PCIE_USER_REVID,Module ID register"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_USER_CMD_STATUS,Command Status register"
bitfld.long 0x04 0. "LINK_TRAINING_ENABLE,This bit must be set to 1 to enable the LTSSM to bring up the link" "0,1"
line.long 0x08 "PCIE_USER_RSTCMD,Reset Command and Status register"
bitfld.long 0x08 0. "INIT_HOT_RESET,When this bit is set to 1'b1 in the RP mode the core initiates a Hot Reset sequence on the PCIe link" "0,1"
line.long 0x0C "PCIE_USER_INITCFG,Initialization configuration register"
bitfld.long 0x0C 24. "CONFIG_ENABLE,When this bit is set to 0 in the EP mode the Controller will generate a CRS Completion in response to Configuration Requests" "0,1"
bitfld.long 0x0C 22.--23. "VC_COUNT,Number of VCs configured" "0,1,2,3"
hexmask.long.byte 0x0C 15.--21. 1. "MAX_EVAL_ITERATION,Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00"
newline
bitfld.long 0x0C 14. "BYPASS_PHASE23,This MMR should be programmed during system boot or initialization" "0,1"
bitfld.long 0x0C 13. "BYPASS_REMOTE_TX_EQUALIZATION,This MMR should be programmed during system boot or initialization" "0,1"
hexmask.long.word 0x0C 2.--12. 1. "SUPPORTED_PRESET,This MMR should be programmed during system boot or initialization"
newline
bitfld.long 0x0C 1. "DISABLE_GEN3_DC_BALANCE,This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed" "0,1"
bitfld.long 0x0C 0. "SRIS_ENABLE,Should be set as per the System Reference Clocking Implementation" "0,1"
line.long 0x10 "PCIE_USER_PMCMD,Power Management command register"
bitfld.long 0x10 2. "POWER_STATE_CHANGE_ACK,Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT when it is ready to transition to the low-power state requested by the configuration write request" "0,1"
bitfld.long 0x10 1. "CLIENT_REQ_EXIT_L1_SUBSTATE,Client logic can trigger an explicit L" "0,1"
bitfld.long 0x10 0. "CLIENT_REQ_EXIT_L1,Client logic can trigger an explicit L1 exit by setting this bit" "0,1"
line.long 0x14 "PCIE_USER_LINKSTATUS,Link Status register"
bitfld.long 0x14 24.--29. "LTSSM_STATE,Current state of the Link Training and Status State Machine within the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 16.--23. 1. "POWER_STATE_CHANGE_FUNCTION_NUM,Function number of the function for which a power state change occurred"
bitfld.long 0x14 12.--14. "L1_PM_SUBSTATE,This register provides the current state of the L1 PM substates state machine" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8.--11. "LINK_POWER_STATE,Current power state of the PCIe link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 3.--4. "NEGOTIATED_SPEED,Current operating speed of the link is as follows" "0,1,2,3"
bitfld.long 0x14 2. "NEGOTIATED_LINK_WIDTH,Current link width are as follows" "0,1"
newline
bitfld.long 0x14 0.--1. "LINK_STATUS,Status of the PCI Express link" "0,1,2,3"
line.long 0x18 "PCIE_USER_LEGACY_INTR_SET,Legacy interrupt set register"
bitfld.long 0x18 3. "INTD_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 2. "INTC_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 1. "INTB_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
newline
bitfld.long 0x18 0. "INTA_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
line.long 0x1C "PCIE_USER_LEGACY_INT_PENDING,Legacy interrupt pending set register"
bitfld.long 0x1C 0.--5. "INT_PENDING_STATUS,When using legacy interrupts this input is used to indicate the interrupt pending status of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "PCIE_USER_MSI_STAT,MSI status register"
bitfld.long 0x20 0.--5. "MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "PCIE_USER_MSI_VECTOR,MSI vector register"
hexmask.long.tbyte 0x24 0.--17. 1. "MSI_VECTOR_COUNT,When the core is configured in the EndPoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions"
line.long 0x28 "PCIE_USER_MSI_MASK_PF0,PF0 MSI mask register"
line.long 0x2C "PCIE_USER_MSI_MASK_PF1,PF1 MSI mask register"
line.long 0x30 "PCIE_USER_MSI_MASK_PF2,PF2 MSI mask register"
line.long 0x34 "PCIE_USER_MSI_MASK_PF3,PF3 MSI mask register"
line.long 0x38 "PCIE_USER_MSI_MASK_PF4,PF4 MSI mask register"
line.long 0x3C "PCIE_USER_MSI_MASK_PF5,PF5 MSI mask register"
line.long 0x40 "PCIE_USER_MSI_PENDING_STATUS_PF0,PF0 MSI pending status input register"
line.long 0x44 "PCIE_USER_MSI_PENDING_STATUS_PF1,PF1 MSI pending status input register"
line.long 0x48 "PCIE_USER_MSI_PENDING_STATUS_PF2,PF2 MSI pending status input register"
line.long 0x4C "PCIE_USER_MSI_PENDING_STATUS_PF3,PF3 MSI pending status input register"
line.long 0x50 "PCIE_USER_MSI_PENDING_STATUS_PF4,PF4 MSI pending status input register"
line.long 0x54 "PCIE_USER_MSI_PENDING_STATUS_PF5,PF5 MSI pending status input register"
line.long 0x58 "PCIE_USER_MSI_STAT_VF,MSI_VF status register"
hexmask.long.word 0x58 0.--15. 1. "VF_MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions"
line.long 0x5C "PCIE_USER_MSI_VECTOR0_VF,MSI_VF vector count register0"
hexmask.long.tbyte 0x5C 0.--23. 1. "VF_MSI_VECTOR_COUNT0,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7"
line.long 0x60 "PCIE_USER_MSI_VECTOR1_VF,MSI_VF vector count register1"
hexmask.long.tbyte 0x60 0.--23. 1. "VF_MSI_VECTOR_COUNT1,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15"
line.long 0x64 "PCIE_USER_MSI_MASK_VF0,VF0MSI mask register"
line.long 0x68 "PCIE_USER_MSI_MASK_VF1,VF1MSI mask register"
line.long 0x6C "PCIE_USER_MSI_MASK_VF2,VF2MSI mask register"
line.long 0x70 "PCIE_USER_MSI_MASK_VF3,VF3MSI mask register"
line.long 0x74 "PCIE_USER_MSI_MASK_VF4,VF4MSI mask register"
line.long 0x78 "PCIE_USER_MSI_MASK_VF5,VF5MSI mask register"
line.long 0x7C "PCIE_USER_MSI_MASK_VF6,VF6MSI mask register"
line.long 0x80 "PCIE_USER_MSI_MASK_VF7,VF7MSI mask register"
line.long 0x84 "PCIE_USER_MSI_MASK_VF8,VF8MSI mask register"
line.long 0x88 "PCIE_USER_MSI_MASK_VF9,VF9MSI mask register"
line.long 0x8C "PCIE_USER_MSI_MASK_VF10,VF10MSI mask register"
line.long 0x90 "PCIE_USER_MSI_MASK_VF11,VF11MSI mask register"
line.long 0x94 "PCIE_USER_MSI_MASK_VF12,VF12MSI mask register"
line.long 0x98 "PCIE_USER_MSI_MASK_VF13,VF13MSI mask register"
line.long 0x9C "PCIE_USER_MSI_MASK_VF14,VF14MSI mask register"
line.long 0xA0 "PCIE_USER_MSI_MASK_VF15,VF15MSI mask register"
line.long 0xA4 "PCIE_USER_MSIX_STAT,MSIX status register"
bitfld.long 0xA4 0.--5. "MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "PCIE_USER_MSIX_MASK,MSIX mask register"
bitfld.long 0xA8 0.--5. "MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xAC "PCIE_USER_MSIX_STAT_VF,Virtual Function MSIX status register"
hexmask.long.word 0xAC 0.--15. 1. "VF_MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0 Bit1 represents the MSIX Enable for Virtual Function 1 and so on"
line.long 0xB0 "PCIE_USER_MSIX_MASK_VF,Virtual Function MSIX mask register"
hexmask.long.word 0xB0 0.--15. 1. "VF_MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions"
line.long 0xB4 "PCIE_USER_FLR_DONE,Physical Function-Level Reset Done register"
bitfld.long 0xB4 0.--5. "FLR_DONE,These bits are connected to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xB8 "PCIE_USER_VF_FLR_DONE,Virtual Function-Level Reset Done register"
hexmask.long.word 0xB8 0.--15. 1. "VF_FLR_DONE,These bits are connected to"
line.long 0xBC "PCIE_USER_PTM_TIMER_LOW,PTM timer value lower 32-bits"
line.long 0xC0 "PCIE_USER_PTM_TIMER_HIGH,PTM timer value upper 32-bits"
tree.end
tree "PCIE3_CORE_USER_CFG_USER_CFG"
base ad:0x2937000
rgroup.long 0x00++0xC3
line.long 0x00 "PCIE_USER_REVID,Module ID register"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PCIE_USER_CMD_STATUS,Command Status register"
bitfld.long 0x04 0. "LINK_TRAINING_ENABLE,This bit must be set to 1 to enable the LTSSM to bring up the link" "0,1"
line.long 0x08 "PCIE_USER_RSTCMD,Reset Command and Status register"
bitfld.long 0x08 0. "INIT_HOT_RESET,When this bit is set to 1'b1 in the RP mode the core initiates a Hot Reset sequence on the PCIe link" "0,1"
line.long 0x0C "PCIE_USER_INITCFG,Initialization configuration register"
bitfld.long 0x0C 24. "CONFIG_ENABLE,When this bit is set to 0 in the EP mode the Controller will generate a CRS Completion in response to Configuration Requests" "0,1"
bitfld.long 0x0C 22.--23. "VC_COUNT,Number of VCs configured" "0,1,2,3"
hexmask.long.byte 0x0C 15.--21. 1. "MAX_EVAL_ITERATION,Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00"
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bitfld.long 0x0C 14. "BYPASS_PHASE23,This MMR should be programmed during system boot or initialization" "0,1"
bitfld.long 0x0C 13. "BYPASS_REMOTE_TX_EQUALIZATION,This MMR should be programmed during system boot or initialization" "0,1"
hexmask.long.word 0x0C 2.--12. 1. "SUPPORTED_PRESET,This MMR should be programmed during system boot or initialization"
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bitfld.long 0x0C 1. "DISABLE_GEN3_DC_BALANCE,This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed" "0,1"
bitfld.long 0x0C 0. "SRIS_ENABLE,Should be set as per the System Reference Clocking Implementation" "0,1"
line.long 0x10 "PCIE_USER_PMCMD,Power Management command register"
bitfld.long 0x10 2. "POWER_STATE_CHANGE_ACK,Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT when it is ready to transition to the low-power state requested by the configuration write request" "0,1"
bitfld.long 0x10 1. "CLIENT_REQ_EXIT_L1_SUBSTATE,Client logic can trigger an explicit L" "0,1"
bitfld.long 0x10 0. "CLIENT_REQ_EXIT_L1,Client logic can trigger an explicit L1 exit by setting this bit" "0,1"
line.long 0x14 "PCIE_USER_LINKSTATUS,Link Status register"
bitfld.long 0x14 24.--29. "LTSSM_STATE,Current state of the Link Training and Status State Machine within the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 16.--23. 1. "POWER_STATE_CHANGE_FUNCTION_NUM,Function number of the function for which a power state change occurred"
bitfld.long 0x14 12.--14. "L1_PM_SUBSTATE,This register provides the current state of the L1 PM substates state machine" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8.--11. "LINK_POWER_STATE,Current power state of the PCIe link" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 3.--4. "NEGOTIATED_SPEED,Current operating speed of the link is as follows" "0,1,2,3"
bitfld.long 0x14 2. "NEGOTIATED_LINK_WIDTH,Current link width are as follows" "0,1"
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bitfld.long 0x14 0.--1. "LINK_STATUS,Status of the PCI Express link" "0,1,2,3"
line.long 0x18 "PCIE_USER_LEGACY_INTR_SET,Legacy interrupt set register"
bitfld.long 0x18 3. "INTD_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 2. "INTC_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
bitfld.long 0x18 1. "INTB_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
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bitfld.long 0x18 0. "INTA_IN,When the core is configured as EP this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express" "0,1"
line.long 0x1C "PCIE_USER_LEGACY_INT_PENDING,Legacy interrupt pending set register"
bitfld.long 0x1C 0.--5. "INT_PENDING_STATUS,When using legacy interrupts this input is used to indicate the interrupt pending status of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "PCIE_USER_MSI_STAT,MSI status register"
bitfld.long 0x20 0.--5. "MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "PCIE_USER_MSI_VECTOR,MSI vector register"
hexmask.long.tbyte 0x24 0.--17. 1. "MSI_VECTOR_COUNT,When the core is configured in the EndPoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions"
line.long 0x28 "PCIE_USER_MSI_MASK_PF0,PF0 MSI mask register"
line.long 0x2C "PCIE_USER_MSI_MASK_PF1,PF1 MSI mask register"
line.long 0x30 "PCIE_USER_MSI_MASK_PF2,PF2 MSI mask register"
line.long 0x34 "PCIE_USER_MSI_MASK_PF3,PF3 MSI mask register"
line.long 0x38 "PCIE_USER_MSI_MASK_PF4,PF4 MSI mask register"
line.long 0x3C "PCIE_USER_MSI_MASK_PF5,PF5 MSI mask register"
line.long 0x40 "PCIE_USER_MSI_PENDING_STATUS_PF0,PF0 MSI pending status input register"
line.long 0x44 "PCIE_USER_MSI_PENDING_STATUS_PF1,PF1 MSI pending status input register"
line.long 0x48 "PCIE_USER_MSI_PENDING_STATUS_PF2,PF2 MSI pending status input register"
line.long 0x4C "PCIE_USER_MSI_PENDING_STATUS_PF3,PF3 MSI pending status input register"
line.long 0x50 "PCIE_USER_MSI_PENDING_STATUS_PF4,PF4 MSI pending status input register"
line.long 0x54 "PCIE_USER_MSI_PENDING_STATUS_PF5,PF5 MSI pending status input register"
line.long 0x58 "PCIE_USER_MSI_STAT_VF,MSI_VF status register"
hexmask.long.word 0x58 0.--15. 1. "VF_MSI_ENABLE,When the core is configured in the EndPoint mode to support MSI interrupts this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions"
line.long 0x5C "PCIE_USER_MSI_VECTOR0_VF,MSI_VF vector count register0"
hexmask.long.tbyte 0x5C 0.--23. 1. "VF_MSI_VECTOR_COUNT0,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7"
line.long 0x60 "PCIE_USER_MSI_VECTOR1_VF,MSI_VF vector count register1"
hexmask.long.tbyte 0x60 0.--23. 1. "VF_MSI_VECTOR_COUNT1,When the core is configured in the Endpoint mode to support MSI interrupts these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15"
line.long 0x64 "PCIE_USER_MSI_MASK_VF0,VF0MSI mask register"
line.long 0x68 "PCIE_USER_MSI_MASK_VF1,VF1MSI mask register"
line.long 0x6C "PCIE_USER_MSI_MASK_VF2,VF2MSI mask register"
line.long 0x70 "PCIE_USER_MSI_MASK_VF3,VF3MSI mask register"
line.long 0x74 "PCIE_USER_MSI_MASK_VF4,VF4MSI mask register"
line.long 0x78 "PCIE_USER_MSI_MASK_VF5,VF5MSI mask register"
line.long 0x7C "PCIE_USER_MSI_MASK_VF6,VF6MSI mask register"
line.long 0x80 "PCIE_USER_MSI_MASK_VF7,VF7MSI mask register"
line.long 0x84 "PCIE_USER_MSI_MASK_VF8,VF8MSI mask register"
line.long 0x88 "PCIE_USER_MSI_MASK_VF9,VF9MSI mask register"
line.long 0x8C "PCIE_USER_MSI_MASK_VF10,VF10MSI mask register"
line.long 0x90 "PCIE_USER_MSI_MASK_VF11,VF11MSI mask register"
line.long 0x94 "PCIE_USER_MSI_MASK_VF12,VF12MSI mask register"
line.long 0x98 "PCIE_USER_MSI_MASK_VF13,VF13MSI mask register"
line.long 0x9C "PCIE_USER_MSI_MASK_VF14,VF14MSI mask register"
line.long 0xA0 "PCIE_USER_MSI_MASK_VF15,VF15MSI mask register"
line.long 0xA4 "PCIE_USER_MSIX_STAT,MSIX status register"
bitfld.long 0xA4 0.--5. "MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "PCIE_USER_MSIX_MASK,MSIX mask register"
bitfld.long 0xA8 0.--5. "MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xAC "PCIE_USER_MSIX_STAT_VF,Virtual Function MSIX status register"
hexmask.long.word 0xAC 0.--15. 1. "VF_MSIX_ENABLE,These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0 Bit1 represents the MSIX Enable for Virtual Function 1 and so on"
line.long 0xB0 "PCIE_USER_MSIX_MASK_VF,Virtual Function MSIX mask register"
hexmask.long.word 0xB0 0.--15. 1. "VF_MSIX_MASK,These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions"
line.long 0xB4 "PCIE_USER_FLR_DONE,Physical Function-Level Reset Done register"
bitfld.long 0xB4 0.--5. "FLR_DONE,These bits are connected to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xB8 "PCIE_USER_VF_FLR_DONE,Virtual Function-Level Reset Done register"
hexmask.long.word 0xB8 0.--15. 1. "VF_FLR_DONE,These bits are connected to"
line.long 0xBC "PCIE_USER_PTM_TIMER_LOW,PTM timer value lower 32-bits"
line.long 0xC0 "PCIE_USER_PTM_TIMER_HIGH,PTM timer value upper 32-bits"
tree.end
tree.end
tree "PCIE_VMAP_HP"
tree "PCIE0_CORE_VMAP_HP_MMRS"
base ad:0x2904000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_HP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_HP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_HP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_HP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree "PCIE1_CORE_VMAP_HP_MMRS"
base ad:0x2914000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_HP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_HP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_HP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_HP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree "PCIE2_CORE_VMAP_HP_MMRS"
base ad:0x2924000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_HP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_HP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_HP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_HP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree "PCIE3_CORE_VMAP_HP_MMRS"
base ad:0x2934000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_HP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_HP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_HP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_HP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree.end
tree "PCIE_VMAP_LP"
tree "PCIE0_CORE_VMAP_LP_MMRS"
base ad:0x2905000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_LP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_LP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_LP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_LP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree "PCIE1_CORE_VMAP_LP_MMRS"
base ad:0x2915000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_LP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_LP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_LP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_LP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree "PCIE2_CORE_VMAP_LP_MMRS"
base ad:0x2925000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_LP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_LP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_LP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_LP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree "PCIE3_CORE_VMAP_LP_MMRS"
base ad:0x2935000
group.long 0x00++0x0B
line.long 0x00 "PCIE_VMAP_LP_CTRL_j,Control register Offset = 0h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x00 0. "EN,ID enable" "0,1"
line.long 0x04 "PCIE_VMAP_LP_REQID_j,Requester ID mask and value register Offset = 4h + (j * Ch); where j = 0h to 1Fh"
hexmask.long.word 0x04 16.--31. 1. "MASK,RequesterID mask"
hexmask.long.word 0x04 0.--15. 1. "RID,RequesterID"
line.long 0x08 "PCIE_VMAP_LP_VIRTID_j,Virt ID and Atype register Offset = 8h + (j * Ch); where j = 0h to 1Fh"
bitfld.long 0x08 16.--17. "ATYPE,Address type attribute" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "VID,Match ID"
group.long 0x200++0x03
line.long 0x00 "PCIE_VMAP_LP_DEFMAP,virtID default value register"
bitfld.long 0x00 20. "ATS_DIS,ATS mode" "0,1"
bitfld.long 0x00 19. "BDF_MODE,Bus default mode" "0,1"
bitfld.long 0x00 16.--17. "DEF_ATYPE,Default address type attribute" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. "DEF_VID,Default match ID"
tree.end
tree.end
tree "PDMA5_ECC"
tree "PDMA5_REGS"
base ad:0x27E0000
rgroup.long 0x00++0x03
line.long 0x00 "PDMA5_ECC_REV,IP revision register"
group.long 0x08++0x07
line.long 0x00 "PDMA5_ECC_VECTOR,ECC vector register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "PDMA5_ECC_STAT,Misc status register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMs serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "PDMA5_ECC_SEC_EOI_REG,SEC EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "PDMA5_ECC_SEC_STATUS_REG0,SEC interrupt status register 0"
bitfld.long 0x04 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "PDMA5_ECC_SEC_ENABLE_SET_REG0,SEC interrupt enable set register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "PDMA5_ECC_SEC_ENABLE_CLR_REG0,SEC interrupt enable clear register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "PDMA5_ECC_DED_EOI_REG,DED EOI register"
bitfld.long 0x00 0. "EOI_WR,EOI value" "0,1"
line.long 0x04 "PDMA5_ECC_DED_STATUS_REG0,DED interrupt status register 0"
bitfld.long 0x04 3. "RPCF1_RAMECC_PEND,Interrupt pending status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RPCF0_RAMECC_PEND,Interrupt pending status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "TPCF1_RAMECC_PEND,Interrupt pending status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "TPCF0_RAMECC_PEND,Interrupt pending status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "PDMA5_ECC_DED_ENABLE_SET_REG0,DED interrupt enable set register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt enable set register for tpcf0_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "PDMA5_ECC_DED_ENABLE_CLR_REG0,DED interrupt enable clear register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt enable clear register for tpcf0_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "PDMA5_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "PDMA5_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "PDMA5_ECC_AGGR_STATUS_SET,AGGR interrupt status set register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "PDMA5_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "PI"
tree "COMPUTE_CLUSTER0_CTL_CFG_PI"
base ad:0x2990000
group.long 0x2000++0x03
line.long 0x00 "DDRSS_PI_0,"
bitfld.long 0x00 8.--11. "PI_DRAM_CLASS,Defines the memory class for the PI.Bh - LPDDR4All other values reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "PI_START,Initiate command processing in the PI" "0,1"
rgroup.long 0x200C++0x47
line.long 0x00 "DDRSS_PI_3,"
hexmask.long.word 0x00 0.--15. 1. "PI_ID,Holds the PI ID number"
line.long 0x04 "DDRSS_PI_4,"
line.long 0x08 "DDRSS_PI_5,"
bitfld.long 0x08 16. "PI_NOTCARE_PHYUPD,Allow the PI to issue a master request to the controller if a phyupd_req from the PHY has been detected" "0,1"
bitfld.long 0x08 8. "PI_INIT_LVL_EN,Enables the initial leveling sequence after PI initialization procedure" "0,1"
bitfld.long 0x08 0. "PI_NORMAL_LVL_SEQ,Enable the PI to finish all the pending leveling before releasing the DFI bus" "0,1"
line.long 0x0C "DDRSS_PI_6,"
bitfld.long 0x0C 24. "PI_TRAIN_ALL_FREQ_REQ,Triggers training for all supported frequencies in PI_FREQ_MAP" "0,1"
hexmask.long.word 0x0C 0.--15. 1. "PI_TCMD_GAP,Specifies the minimum gap in DFI clocks between two commands"
line.long 0x10 "DDRSS_PI_7,"
bitfld.long 0x10 24. "PI_DFI_PHYMSTR_STATE_SEL_R,DFI PHY Master State Select: Indication from the PHY to the MC whether the requested memory state is IDLE or Self refresh" "0,1"
bitfld.long 0x10 16. "PI_DFI_PHYMSTR_CS_STATE_R,This signal indicates the state of the DRAM when the PHY becomes the master" "0,1"
bitfld.long 0x10 8.--9. "PI_DFI_PHYMSTR_TYPE,DFI Master Request Type used for dfi 4.1 verision: This signal indicates the required state of DRAM when PHY becomes the master" "0,1,2,3"
newline
bitfld.long 0x10 0. "PI_DFI_VERSION,Define the DFI master version set 1 for DFI4.1 set 0 for DFI4.0" "0,1"
line.long 0x14 "DDRSS_PI_8,"
line.long 0x18 "DDRSS_PI_9,"
hexmask.long.tbyte 0x18 0.--19. 1. "PI_TDFI_PHYMSTR_RESP,Indicates the maximum number of DFI clock cycles registered between a dfi_phymstr_req signal assertion and a dfi_phymstr_ack signal assertion"
line.long 0x1C "DDRSS_PI_10,"
hexmask.long.tbyte 0x1C 0.--19. 1. "PI_TDFI_PHYUPD_RESP,Indicates the maximum number of DFI clock cycles registered between a dfi_phyupd_req signal assertion and a dfi_phyupd_ack signal assertion"
line.long 0x20 "DDRSS_PI_11,"
line.long 0x24 "DDRSS_PI_12,"
line.long 0x28 "DDRSS_PI_13,"
bitfld.long 0x28 16. "PI_SW_RST_N,User request to reset the whole PI except the parameter modules" "0,1"
bitfld.long 0x28 8. "PI_INIT_DFS_CALVL_ONLY,Enables frequency training for CA leveling only" "0,1"
bitfld.long 0x28 0.--4. "PI_INIT_WORK_FREQ,Indicates the initial work frequency after initialization and initial leveling sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "DDRSS_PI_14,"
bitfld.long 0x2C 24.--27. "PI_TMRR,DRAM tMRR value in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 16. "PI_SRX_LVL_TARGET_CS_EN,Defines self refresh exit trigger target rank/ranks training or all ranks training" "0,1"
bitfld.long 0x2C 8.--12. "PI_RANK_NUM_PER_CKE,Defines the number of chip selects share one cke" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x2C 0.--3. "PI_CS_MAP,Defines which chip selects are active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "DDRSS_PI_15,"
bitfld.long 0x30 8. "PI_MCAREF_FORWARD_ONLY,Controls the generation of AREF from the PI module or forward the MC received value" "0,1"
bitfld.long 0x30 0.--1. "PI_PREAMBLE_SUPPORT,Defines the read and write preamble length" "0,1,2,3"
line.long 0x34 "DDRSS_PI_16,"
rbitfld.long 0x34 24. "PI_ON_DFIBUS,Monitors the state of the PI controlling the DFI bus" "0,1"
hexmask.long.tbyte 0x34 0.--19. 1. "PI_TREF_INTERVAL,Defines the cycles between refreshes to different chip selects"
line.long 0x38 "DDRSS_PI_17,"
rbitfld.long 0x38 24. "PI_SW_WRLVL_RESP_0,Write leveling response for data slice 0" "0,1"
rbitfld.long 0x38 16. "PI_SWLVL_OP_DONE,Reports the status of the software leveling operation" "0,1"
bitfld.long 0x38 8. "PI_SWLVL_LOAD,User request to load delays and execute software leveling" "0,1"
newline
rbitfld.long 0x38 0. "PI_DATA_RETENTION,Monitors the readiness for the PHY to be put into data retention mode after pi_sref_entry req parameter has been written" "0,1"
line.long 0x3C "DDRSS_PI_18,"
bitfld.long 0x3C 24.--25. "PI_SW_RDLVL_RESP_0,Read leveling response for data slice 0" "0,1,2,3"
bitfld.long 0x3C 16. "PI_SW_WRLVL_RESP_3,Write leveling response for data slice 3" "0,1"
bitfld.long 0x3C 8. "PI_SW_WRLVL_RESP_2,Write leveling response for data slice 2" "0,1"
newline
bitfld.long 0x3C 0. "PI_SW_WRLVL_RESP_1,Write leveling response for data slice 1" "0,1"
line.long 0x40 "DDRSS_PI_19,"
bitfld.long 0x40 24.--25. "PI_SW_CALVL_RESP_0,CA leveling response for address slice 0" "0,1,2,3"
bitfld.long 0x40 16.--17. "PI_SW_RDLVL_RESP_3,Read leveling response for data slice 3" "0,1,2,3"
bitfld.long 0x40 8.--9. "PI_SW_RDLVL_RESP_2,Read leveling response for data slice 2" "0,1,2,3"
newline
bitfld.long 0x40 0.--1. "PI_SW_RDLVL_RESP_1,Read leveling response for data slice 1" "0,1,2,3"
line.long 0x44 "DDRSS_PI_20,"
bitfld.long 0x44 24. "PI_SWLVL_WR_SLICE_0,SW leveling write command in WDQ training" "0,1"
bitfld.long 0x44 16. "PI_SWLVL_EXIT,User request to exit software leveling" "0,1"
bitfld.long 0x44 8. "PI_SWLVL_START,User request to initiate software leveling of type in the SW_LEVELING_MODE parameter" "0,1"
newline
bitfld.long 0x44 0.--2. "PI_SW_LEVELING_MODE,Defines the leveling operation for software leveling" "0,1,2,3,4,5,6,7"
group.long 0x2060++0xC7
line.long 0x00 "DDRSS_PI_24,"
bitfld.long 0x00 24. "PI_SWLVL_SM2_START,SW leveling start command for stage 2" "0,1"
rbitfld.long 0x00 16.--17. "PI_SW_WDQLVL_RESP_3,Leveling response for data slice 3" "0,1,2,3"
bitfld.long 0x00 8. "PI_SWLVL_VREF_UPDATE_SLICE_3,SW leveling vref update command in WDQ training" "0,1"
newline
bitfld.long 0x00 0. "PI_SWLVL_RD_SLICE_3,SW leveling read command in WDQ training" "0,1"
line.long 0x04 "DDRSS_PI_25,"
bitfld.long 0x04 24. "PI_DFS_PERIOD_EN,Enable the DFS triggered periodic leveling" "0,1"
bitfld.long 0x04 16. "PI_SEQUENTIAL_LVL_REQ,User request to initiate all possible leveling sequences" "0,1"
bitfld.long 0x04 8. "PI_SWLVL_SM2_RD,SW leveling read command for stage 2" "0,1"
newline
bitfld.long 0x04 0. "PI_SWLVL_SM2_WR,SW leveling write command for stage 2" "0,1"
line.long 0x08 "DDRSS_PI_26,"
bitfld.long 0x08 24. "PI_WRLVL_REQ,User request to initiate write leveling" "0,1"
bitfld.long 0x08 16. "PI_16BIT_DRAM_CONNECT,Enable 16/32 bit DRAM configuration" "0,1"
bitfld.long 0x08 8. "PI_DFI40_POLARITY,Defines the polarity of the dfi_wrdata_cs_n/dfi_rddata_cs_n signals" "0,1"
newline
bitfld.long 0x08 0. "PI_SRE_PERIOD_EN,Enable the self refresh exit triggered periodic leveling" "0,1"
line.long 0x0C "DDRSS_PI_27,"
bitfld.long 0x0C 16.--21. "PI_WLMRD,Delay from issuing MRS to first write leveling strobe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 8.--13. "PI_WLDQSEN,Delay from issuing MRS to first DQS strobe for write leveling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--1. "PI_WRLVL_CS,Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter" "0,1,2,3"
line.long 0x10 "DDRSS_PI_28,"
bitfld.long 0x10 24. "PI_WRLVL_ON_SREF_EXIT,Enables automatic write leveling on a self-refresh exit" "0,1"
bitfld.long 0x10 16. "PI_WRLVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during write leveling" "0,1"
hexmask.long.word 0x10 0.--15. 1. "PI_WRLVL_INTERVAL,Number of long count sequences counted between automatic write leveling commands"
line.long 0x14 "DDRSS_PI_29,"
bitfld.long 0x14 24.--27. "PI_WRLVL_CS_MAP,Defines the chip select map for write leveling operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 16. "PI_WRLVL_ROTATE,Enables rotational CS for counter triggered automatic write leveling" "0,1"
bitfld.long 0x14 8.--11. "PI_WRLVL_RESP_MASK,Mask for the dfi_wrlvl_resp signal during write leveling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0. "PI_WRLVL_DISABLE_DFS,Disable automatic write leveling on freq change" "0,1"
line.long 0x18 "DDRSS_PI_30,"
hexmask.long.byte 0x18 8.--15. 1. "PI_TDFI_WRLVL_EN,Defines the DFI tWRLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion"
rbitfld.long 0x18 0. "PI_WRLVL_ERROR_STATUS,Holds the error associated with the write level error interrupt" "0,1"
line.long 0x1C "DDRSS_PI_31,"
line.long 0x20 "DDRSS_PI_32,"
line.long 0x24 "DDRSS_PI_33,"
bitfld.long 0x24 24.--27. "PI_ODT_VALUE,When using LPDDR4 this value will be driven out on the dfi_odt signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 16.--19. "PI_TODTH_RD,Defines the minimum DRAM cycles of ODT high time for a read command in memory clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 8.--11. "PI_TODTH_WR,Defines the minimum DRAM cycles of ODT high time for a write command in memory clocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--4. "PI_WRLVL_STROBE_NUM,Defines the number of write leveling strobes generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "DDRSS_PI_34,"
bitfld.long 0x28 16.--17. "PI_RDLVL_CS,Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter" "0,1,2,3"
bitfld.long 0x28 8. "PI_RDLVL_GATE_REQ,User request to initiate gate training" "0,1"
bitfld.long 0x28 0. "PI_RDLVL_REQ,User request to initiate data eye training" "0,1"
line.long 0x2C "DDRSS_PI_35,"
line.long 0x30 "DDRSS_PI_36,"
line.long 0x34 "DDRSS_PI_37,"
line.long 0x38 "DDRSS_PI_38,"
line.long 0x3C "DDRSS_PI_39,"
line.long 0x40 "DDRSS_PI_40,"
line.long 0x44 "DDRSS_PI_41,"
line.long 0x48 "DDRSS_PI_42,"
line.long 0x4C "DDRSS_PI_43,"
bitfld.long 0x4C 24. "PI_RDLVL_DISABLE_DFS,Disables automatic data eye training on freq change" "0,1"
bitfld.long 0x4C 16. "PI_RDLVL_ON_SREF_EXIT,Enables automatic data eye training on a self-refresh exit" "0,1"
bitfld.long 0x4C 8. "PI_RDLVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during data eye training" "0,1"
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bitfld.long 0x4C 0.--3. "PI_RDLVL_SEQ_EN,Specifies the pattern format and MPR for data eye training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "DDRSS_PI_44,"
bitfld.long 0x50 24. "PI_RDLVL_ROTATE,Enables rotational CS for interval data eye training" "0,1"
bitfld.long 0x50 16. "PI_RDLVL_GATE_DISABLE_DFS,Disables automatic gate training on freq change" "0,1"
bitfld.long 0x50 8. "PI_RDLVL_GATE_ON_SREF_EXIT,Enables automatic gate training on a self-refresh exit" "0,1"
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bitfld.long 0x50 0. "PI_RDLVL_GATE_PERIODIC,Enables the use of the dfi_lvl_periodic signal during gate training" "0,1"
line.long 0x54 "DDRSS_PI_45,"
bitfld.long 0x54 16.--19. "PI_RDLVL_GATE_CS_MAP,Defines the chip select map for gate training operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x54 8.--11. "PI_RDLVL_CS_MAP,Defines the chip select map for data eye training operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x54 0. "PI_RDLVL_GATE_ROTATE,Enables rotational CS for interval gate training" "0,1"
line.long 0x58 "DDRSS_PI_46,"
hexmask.long.word 0x58 0.--9. 1. "PI_TDFI_RDLVL_RR,Defines the DFI tRDLVL_RR timing parameter (in DFI clocks) the minimum cycles between read commands"
line.long 0x5C "DDRSS_PI_47,"
line.long 0x60 "DDRSS_PI_48,"
hexmask.long.byte 0x60 8.--15. 1. "PI_TDFI_RDLVL_EN,Defines the DFI tRDLVL_EN timing parameter (in DFI clocks) the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR"
bitfld.long 0x60 0.--3. "PI_RDLVL_RESP_MASK,Mask for the dfi_rdlvl_resp signal during data eye training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DDRSS_PI_49,"
line.long 0x68 "DDRSS_PI_50,"
hexmask.long.word 0x68 8.--23. 1. "PI_RDLVL_INTERVAL,Number of long count sequences counted between automatic data eye training commands"
rbitfld.long 0x68 0. "PI_RDLVL_ERROR_STATUS,Holds the error associated with the data eye training error or gate training error interrupt" "0,1"
line.long 0x6C "DDRSS_PI_51,"
bitfld.long 0x6C 24.--27. "PI_RDLVL_PATTERN_NUM,Defines the number of pattern supported in read leveling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x6C 16.--19. "PI_RDLVL_PATTERN_START,Defines the start pattern in read leveling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x6C 0.--15. 1. "PI_RDLVL_GATE_INTERVAL,Number of long count sequences counted between automatic gate training commands"
line.long 0x70 "DDRSS_PI_52,"
bitfld.long 0x70 24. "PI_REG_DIMM_ENABLE,Enable registered DIMM operation" "0,1"
bitfld.long 0x70 16. "PI_RD_PREAMBLE_TRAINING_EN,Enable read preamble training during gate training" "0,1"
bitfld.long 0x70 8.--12. "PI_RDLVL_GATE_STROBE_NUM,Defines the number of back to back MPC command in one read process in read gate training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x70 0.--4. "PI_RDLVL_STROBE_NUM,Defines the number of back to back MPC command in one read process in read eye training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "DDRSS_PI_53,"
bitfld.long 0x74 24.--25. "PI_CALVL_CS,Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter" "0,1,2,3"
bitfld.long 0x74 16. "PI_CALVL_REQ,User request to initiate CA training" "0,1"
hexmask.long.byte 0x74 8.--14. 1. "PI_TDFI_PHY_WRLAT,Holds the calculated DFI tPHY_WRLAT timing parameter (in DFI PHY clocks) the maximum cycles between a write command and a dfi_wrdata_en assertion"
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hexmask.long.byte 0x74 0.--6. 1. "PI_TDFI_RDDATA_EN,Holds the calculated DFI tRDDATA_EN timing parameter (in DFI PHY clocks) the maximum cycles between a read command and a dfi_rddata_en assertion"
line.long 0x78 "DDRSS_PI_54,"
bitfld.long 0x78 24. "PI_CALVL_PERIODIC,Enables the use of the dfi_lvl_periodic signal during CA training" "0,1"
bitfld.long 0x78 16.--17. "PI_CALVL_SEQ_EN,Specifies which CA training patterns will be used" "0,1,2,3"
line.long 0x7C "DDRSS_PI_55,"
bitfld.long 0x7C 24.--27. "PI_CALVL_CS_MAP,Defines the chip select map for CA training operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x7C 16. "PI_CALVL_ROTATE,Enables rotational CS for interval CA training" "0,1"
bitfld.long 0x7C 8. "PI_CALVL_DISABLE_DFS,Disables automatic CA training on freq change" "0,1"
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bitfld.long 0x7C 0. "PI_CALVL_ON_SREF_EXIT,Enables automatic CA training on a self-refresh exit" "0,1"
line.long 0x80 "DDRSS_PI_56,"
hexmask.long.byte 0x80 0.--7. 1. "PI_TDFI_CALVL_EN,Defines the DFI tCALVL_EN timing parameter (in DFI clocks) the minimum cycles between a dfi_calvl_en assertion and a dfi_cke de-assertion"
line.long 0x84 "DDRSS_PI_57,"
line.long 0x88 "DDRSS_PI_58,"
line.long 0x8C "DDRSS_PI_59,"
hexmask.long.word 0x8C 16.--31. 1. "PI_CALVL_INTERVAL,Number of long count sequences counted between automatic CA training commands"
rbitfld.long 0x8C 8.--9. "PI_CALVL_ERROR_STATUS,Holds the error associated with the CA training error interrupt" "0,1,2,3"
bitfld.long 0x8C 0. "PI_CALVL_RESP_MASK,Mask for the dfi_calvl_resp signal during CA training" "0,1"
line.long 0x90 "DDRSS_PI_60,"
bitfld.long 0x90 24.--28. "PI_TCAEXT,DRAM tCAEXT value in memory cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 16.--20. "PI_TCACKEH,DRAM tCACKEH value in memory cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 8.--13. "PI_TCAMRD,DRAM tCAMRD value in memory cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x90 0.--4. "PI_TCACKEL,DRAM tCACKEL value in memory cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x94 "DDRSS_PI_61,"
hexmask.long.byte 0x94 24.--31. 1. "PI_TDFI_INIT_START_MIN,Minimum number of DFI clocks before dfi_init_start can be driven after a previous command/training event"
bitfld.long 0x94 16.--19. "PI_CALVL_VREF_NORMAL_STEPSIZE,The adjust step for the post-initial Vref(ca) training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x94 8.--11. "PI_CALVL_VREF_INITIAL_STEPSIZE,The adjust step for the initial Vref(ca) training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x94 0. "PI_CA_TRAIN_VREF_EN,Control for VREF training during CA training post power-on initialization" "0,1"
line.long 0x98 "DDRSS_PI_62,"
hexmask.long.byte 0x98 24.--30. 1. "PI_SW_CA_TRAIN_VREF,The Vref value which is set for SW step by step CA training"
bitfld.long 0x98 16.--20. "PI_CALVL_STROBE_NUM,The consecutive dfi_calvl_strobe number when updating the CA vref data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 8.--11. "PI_TCKCKEH,DRAM tCKELCK Clock and command valid before CKE HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x98 0.--7. 1. "PI_TDFI_INIT_COMPLETE_MIN,Minimum number of DFI clocks from dfi_init_complete to a command/training event"
line.long 0x9C "DDRSS_PI_63,"
bitfld.long 0x9C 24. "PI_REFRESH_BETWEEN_SEGMENT_DISABLE,Disable the refresh between CA first and second segment training" "0,1"
bitfld.long 0x9C 16. "PI_DRAM_CLK_DISABLE_DEASSERT_SEL,Indicate dfi_dram_clk_disable deassert following dfi_init_start deassert or dfi_init_complete assert" "0,1"
hexmask.long.byte 0x9C 8.--15. 1. "PI_INIT_STARTORCOMPLETE_2_CLKDISABLE,Defines the delay from deasserting of dfi_init_start or asserting of dfi_init_complete to deasserting of dfi_dram_clk_disable in DFI clock"
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hexmask.long.byte 0x9C 0.--7. 1. "PI_CLKDISABLE_2_INIT_START,Defines the delay from the asserting of dfi_dram_clk_disable to the asserting of dfi_init_start in DFI clock"
line.long 0xA0 "DDRSS_PI_64,"
hexmask.long.word 0xA0 8.--23. 1. "PI_FSM_ERROR_INFO_MASK,PI FSM Error Info MASK"
bitfld.long 0xA0 0. "PI_MC_DFS_PI_SET_VREF_ENABLE,Enable the PI to set VREF value after DFS issued by MC" "0,1"
line.long 0xA4 "DDRSS_PI_65,"
hexmask.long.word 0xA4 16.--31. 1. "PI_FSM_ERROR_INFO,Gather each fsm error bit"
hexmask.long.word 0xA4 0.--15. 1. "PI_SC_FSM_ERROR_INFO_WOCLR,PI FSM Error Info"
line.long 0xA8 "DDRSS_PI_66,"
bitfld.long 0xA8 24. "PI_WDQLVL_ROTATE,Enables write DQ training rotate for interval training" "0,1"
bitfld.long 0xA8 16.--19. "PI_WDQLVL_RESP_MASK,Write DQ training response mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xA8 8.--10. "PI_WDQLVL_BST_NUM,Defines the number of write/read bursts issued at each step in write DQ training" "0,1,2,3,4,5,6,7"
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bitfld.long 0xA8 0. "PI_WDQLVL_VREF_EN,Control for VREF training as part of non-initialization write DQ training" "0,1"
line.long 0xAC "DDRSS_PI_67,"
bitfld.long 0xAC 24. "PI_WDQLVL_PERIODIC,Enables periodic write DQ training" "0,1"
bitfld.long 0xAC 16.--20. "PI_WDQLVL_VREF_NORMAL_STEPSIZE,Write DQ training vref step size for post_initial training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0xAC 8.--12. "PI_WDQLVL_VREF_INITIAL_STEPSIZE,Write DQ training vref step size for initial training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xAC 0.--3. "PI_WDQLVL_CS_MAP,Map of CS's included in write DQ training sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "DDRSS_PI_68,"
hexmask.long.byte 0xB0 16.--23. 1. "PI_TDFI_WDQLVL_EN,DFI timing param tWDQLVL_EN"
bitfld.long 0xB0 8.--9. "PI_WDQLVL_CS,Write DQ training target chip select" "0,1,2,3"
bitfld.long 0xB0 0. "PI_WDQLVL_REQ,SW write to initiate Write DQ training request" "0,1"
line.long 0xB4 "DDRSS_PI_69,"
line.long 0xB8 "DDRSS_PI_70,"
line.long 0xBC "DDRSS_PI_71,"
bitfld.long 0xBC 24. "PI_WDQLVL_DISABLE_DFS,Disable automatic write DQ training on freq change" "0,1"
bitfld.long 0xBC 16. "PI_WDQLVL_ON_SREF_EXIT,Issue a write DQ training command on self-refresh exit" "0,1"
hexmask.long.word 0xBC 0.--15. 1. "PI_WDQLVL_INTERVAL,Sets the maximum number of long count sequences allowed between automatic write DQ training operations"
line.long 0xC0 "DDRSS_PI_72,"
bitfld.long 0xC0 24. "PI_PARALLEL_WDQLVL_EN,Enable per rank parallel Write DQ training for LPDDR4 " "0,1"
bitfld.long 0xC0 16. "PI_DQS_OSC_PERIOD_EN,Enable for DQS oscillator triggered periodic write DQ training " "0,1"
bitfld.long 0xC0 8. "PI_WDQLVL_OSC_EN,Enable for DQS oscillator triggered write DQ training " "0,1"
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rbitfld.long 0xC0 0.--1. "PI_WDQLVL_ERROR_STATUS,Holds the error associated with the write dq level error interrupt" "0,1,2,3"
line.long 0xC4 "DDRSS_PI_73,"
bitfld.long 0xC4 16.--20. "PI_TCCD,DRAM CAS-to-CAS value in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0xC4 8.--10. "PI_ROW_DIFF,Difference between number of address pins available and number being used" "0,1,2,3,4,5,6,7"
bitfld.long 0xC4 0.--1. "PI_BANK_DIFF,Difference between number of bank pins available and number being used" "0,1,2,3"
rgroup.long 0x213C++0x0B
line.long 0x00 "DDRSS_PI_79,"
hexmask.long 0x00 0.--27. 1. "PI_INT_STATUS,Status of interrupt features in the PI"
line.long 0x04 "DDRSS_PI_80,"
hexmask.long 0x04 0.--26. 1. "PI_INT_ACK,Clear the corresponding interrupt bit of the PI_INT_STATUS parameter"
line.long 0x08 "DDRSS_PI_81,"
hexmask.long 0x08 0.--27. 1. "PI_INT_MASK,Mask for PI_int signals from the PI_INT_STATUS parameter"
rgroup.long 0x2168++0x1F
line.long 0x00 "DDRSS_PI_90,"
line.long 0x04 "DDRSS_PI_91,"
bitfld.long 0x04 24. "PI_CMD_SWAP_EN,Command pin swap function enable" "0,1"
bitfld.long 0x04 16.--20. "PI_LONG_COUNT_MASK,Reduces the length of the long counter from 1024 cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "PI_BSTLEN,Encoded burst length sent to DRAMs during initialization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x04 0.--2. "PI_BIST_FAIL_ADDR_1,The burst aligned address of BIST error" "0,1,2,3,4,5,6,7"
line.long 0x08 "DDRSS_PI_92,"
bitfld.long 0x08 24.--25. "PI_DATA_BYTE_SWAP_SLICE2,DATA pin 2 mux selector" "0,1,2,3"
bitfld.long 0x08 16.--17. "PI_DATA_BYTE_SWAP_SLICE1,DATA pin 1 mux selector" "0,1,2,3"
bitfld.long 0x08 8.--9. "PI_DATA_BYTE_SWAP_SLICE0,DATA pin 0 mux selector" "0,1,2,3"
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bitfld.long 0x08 0. "PI_DATA_BYTE_SWAP_EN,DATA pin swap function enable" "0,1"
line.long 0x0C "DDRSS_PI_93,"
rbitfld.long 0x0C 24.--25. "PI_UPDATE_ERROR_STATUS,Identifies the source of any DFI PI-initiated update errors" "0,1,2,3"
hexmask.long.byte 0x0C 16.--23. 1. "PI_TDFI_CTRLUPD_MIN,Reports the DFI tCTRLUPD_MIN timing parameter (in DFI clocks) the minimum cycles that dfi_ctrlupd_req must be asserted"
bitfld.long 0x0C 8. "PI_CTRLUPD_REQ_PER_AREF_EN,Enable an automatic PI initiated update (dfi_ctrlupd_req) after every refresh" "0,1"
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bitfld.long 0x0C 0.--1. "PI_DATA_BYTE_SWAP_SLICE3,DATA pin 3 mux selector" "0,1,2,3"
line.long 0x10 "DDRSS_PI_94,"
bitfld.long 0x10 24. "PI_BIST_DATA_CHECK,Enable data checking with BIST operation" "0,1"
bitfld.long 0x10 16.--21. "PI_ADDR_SPACE,Sets the number of address bits to check during BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x10 8.--9. "PI_BIST_RESULT,BIST operation status (pass/fail)" "0,1,2,3"
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bitfld.long 0x10 0. "PI_BIST_GO,Initiate a BIST operation" "0,1"
line.long 0x14 "DDRSS_PI_95,"
bitfld.long 0x14 0. "PI_BIST_ADDR_CHECK,Enable address checking with BIST operation" "0,1"
line.long 0x18 "DDRSS_PI_96,"
line.long 0x1C "DDRSS_PI_97,"
hexmask.long.byte 0x1C 8.--15. 1. "PI_MBIST_INIT_PATTERN,PI mbist data check random lfsr pattern mode init pattern seed"
bitfld.long 0x1C 0.--2. "PI_BIST_START_ADDRESS_1,Start BIST checking at this address" "0,1,2,3,4,5,6,7"
group.long 0x2190++0x53
line.long 0x00 "DDRSS_PI_100,"
hexmask.long.word 0x00 16.--27. 1. "PI_BIST_ERR_STOP,Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is set to 1 2 or 3"
hexmask.long.word 0x00 0.--11. 1. "PI_BIST_ERR_COUNT,Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is set to 1 2 or 3"
line.long 0x04 "DDRSS_PI_101,"
line.long 0x08 "DDRSS_PI_102,"
bitfld.long 0x08 0.--3. "PI_BIST_ADDR_MASK_0_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DDRSS_PI_103,"
line.long 0x10 "DDRSS_PI_104,"
bitfld.long 0x10 0.--3. "PI_BIST_ADDR_MASK_1_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "DDRSS_PI_105,"
line.long 0x18 "DDRSS_PI_106,"
bitfld.long 0x18 0.--3. "PI_BIST_ADDR_MASK_2_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DDRSS_PI_107,"
line.long 0x20 "DDRSS_PI_108,"
bitfld.long 0x20 0.--3. "PI_BIST_ADDR_MASK_3_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDRSS_PI_109,"
line.long 0x28 "DDRSS_PI_110,"
bitfld.long 0x28 0.--3. "PI_BIST_ADDR_MASK_4_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DDRSS_PI_111,"
line.long 0x30 "DDRSS_PI_112,"
bitfld.long 0x30 0.--3. "PI_BIST_ADDR_MASK_5_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DDRSS_PI_113,"
line.long 0x38 "DDRSS_PI_114,"
bitfld.long 0x38 0.--3. "PI_BIST_ADDR_MASK_6_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DDRSS_PI_115,"
line.long 0x40 "DDRSS_PI_116,"
bitfld.long 0x40 0.--3. "PI_BIST_ADDR_MASK_7_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DDRSS_PI_117,"
line.long 0x48 "DDRSS_PI_118,"
bitfld.long 0x48 0.--3. "PI_BIST_ADDR_MASK_8_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DDRSS_PI_119,"
line.long 0x50 "DDRSS_PI_120,"
bitfld.long 0x50 24.--25. "PI_BIST_PAT_MODE,Sets the pattern mode of BIST" "0,1,2,3"
bitfld.long 0x50 16.--17. "PI_BIST_ADDR_MODE,Sets the address traversing order of BIST" "0,1,2,3"
bitfld.long 0x50 8.--10. "PI_BIST_MODE,Sets the BIST data checking mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x50 0.--3. "PI_BIST_ADDR_MASK_9_1,Defines an address to be masked during the BIST operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21F4++0x03
line.long 0x00 "DDRSS_PI_125,"
bitfld.long 0x00 0.--3. "PI_BIST_PAT_NUM,Sets the max used pattern number of BIST from a total of 8 built-in patterns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2218++0x53
line.long 0x00 "DDRSS_PI_134,"
bitfld.long 0x00 24. "PI_SREFRESH_EXIT_NO_REFRESH,Disables the automatic refresh request associated with self-refresh exit" "0,1"
bitfld.long 0x00 16. "PI_PWRUP_SREFRESH_EXIT,Allow powerup via self-refresh instead of full memory initialization" "0,1"
bitfld.long 0x00 8. "PI_SELF_REFRESH_EN,Control for PI to enable self refresh mode" "0,1"
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bitfld.long 0x00 0.--3. "PI_COL_DIFF,Difference between number of column pins available and number being used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DDRSS_PI_135,"
bitfld.long 0x04 24. "PI_NO_PHY_IND_TRAIN_INIT,Disable PHY Independent Training during initialization" "0,1"
bitfld.long 0x04 16. "PI_NO_MRW_INIT,Disable MRW commands after training during initialization" "0,1"
bitfld.long 0x04 8. "PI_NO_MRW_BT_INIT,Disable MRW commands before training during initialization" "0,1"
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bitfld.long 0x04 0. "PI_SREF_ENTRY_REQ,In PI power up data retention PI can issued sref entry command" "0,1"
line.long 0x08 "DDRSS_PI_136,"
bitfld.long 0x08 0. "PI_NO_AUTO_MRR_INIT,Disable MRR commands during initialization" "0,1"
line.long 0x0C "DDRSS_PI_137,"
line.long 0x10 "DDRSS_PI_138,"
line.long 0x14 "DDRSS_PI_139,"
hexmask.long.word 0x14 16.--31. 1. "PI_DLL_RST_DELAY,Minimum cycles required for DLL reset signal dll_rst_n to be held"
bitfld.long 0x14 8. "PI_DRAM_INIT_EN,Control for the initialization of DRAM by the PI" "0,1"
bitfld.long 0x14 0. "PI_DLL_RST,Enables use of the DLL reset (dll_rst_n)" "0,1"
line.long 0x18 "DDRSS_PI_140,"
hexmask.long.byte 0x18 0.--7. 1. "PI_DLL_RST_ADJ_DLY,Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted"
line.long 0x1C "DDRSS_PI_141,"
hexmask.long 0x1C 0.--25. 1. "PI_WRITE_MODEREG,Write memory mode register data to the DRAMs"
line.long 0x20 "DDRSS_PI_142,"
hexmask.long.tbyte 0x20 8.--24. 1. "PI_READ_MODEREG,Read the specified memory mode register from specified chip when start bit set"
hexmask.long.byte 0x20 0.--7. 1. "PI_MRW_STATUS,Write memory mode register status"
line.long 0x24 "DDRSS_PI_143,"
bitfld.long 0x24 24. "PI_NO_ZQ_INIT,Disable ZQ operations during initialization" "0,1"
hexmask.long.tbyte 0x24 0.--23. 1. "PI_PERIPHERAL_MRR_DATA_0,Data and chip returned from memory mode register read requested by the READ_MODEREG parameter Bits ("
line.long 0x28 "DDRSS_PI_144,"
bitfld.long 0x28 16. "PI_ZQ_REQ_PENDING,Indicates that a ZQ command is currently in progress or waiting to run" "0,1"
line.long 0x2C "DDRSS_PI_145,"
hexmask.long.byte 0x2C 24.--31. 1. "PI_MONITOR_0,Monitor register 0"
bitfld.long 0x2C 16. "PI_MONITOR_CAP_SEL_0,Selection of captures for pi_monitor_0" "0,1"
bitfld.long 0x2C 8.--11. "PI_MONITOR_SRC_SEL_0,Selection of sources for pi_monitor_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "DDRSS_PI_146,"
bitfld.long 0x30 24.--27. "PI_MONITOR_SRC_SEL_2,Selection of sources for pi_monitor_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x30 16.--23. 1. "PI_MONITOR_1,Monitor register 1"
bitfld.long 0x30 8. "PI_MONITOR_CAP_SEL_1,Selection of captures for pi_monitor_1" "0,1"
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bitfld.long 0x30 0.--3. "PI_MONITOR_SRC_SEL_1,Selection of sources for pi_monitor_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DDRSS_PI_147,"
bitfld.long 0x34 24. "PI_MONITOR_CAP_SEL_3,Selection of captures for pi_monitor_3" "0,1"
bitfld.long 0x34 16.--19. "PI_MONITOR_SRC_SEL_3,Selection of sources for pi_monitor_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x34 8.--15. 1. "PI_MONITOR_2,Monitor register 2"
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bitfld.long 0x34 0. "PI_MONITOR_CAP_SEL_2,Selection of captures for pi_monitor_2" "0,1"
line.long 0x38 "DDRSS_PI_148,"
hexmask.long.byte 0x38 24.--31. 1. "PI_MONITOR_4,Monitor register 4"
bitfld.long 0x38 16. "PI_MONITOR_CAP_SEL_4,Selection of captures for pi_monitor_4" "0,1"
bitfld.long 0x38 8.--11. "PI_MONITOR_SRC_SEL_4,Selection of sources for pi_monitor_4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x38 0.--7. 1. "PI_MONITOR_3,Monitor register 3"
line.long 0x3C "DDRSS_PI_149,"
bitfld.long 0x3C 24.--27. "PI_MONITOR_SRC_SEL_6,Selection of sources for pi_monitor_6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x3C 16.--23. 1. "PI_MONITOR_5,Monitor register 5"
bitfld.long 0x3C 8. "PI_MONITOR_CAP_SEL_5,Selection of captures for pi_monitor_5" "0,1"
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bitfld.long 0x3C 0.--3. "PI_MONITOR_SRC_SEL_5,Selection of sources for pi_monitor_5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "DDRSS_PI_150,"
bitfld.long 0x40 24. "PI_MONITOR_CAP_SEL_7,Selection of captures for pi_monitor_7" "0,1"
bitfld.long 0x40 16.--19. "PI_MONITOR_SRC_SEL_7,Selection of sources for pi_monitor_7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x40 8.--15. 1. "PI_MONITOR_6,Monitor register 6"
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bitfld.long 0x40 0. "PI_MONITOR_CAP_SEL_6,Selection of captures for pi_monitor_6" "0,1"
line.long 0x44 "DDRSS_PI_151,"
hexmask.long.byte 0x44 0.--7. 1. "PI_MONITOR_7,Monitor register 7"
line.long 0x48 "DDRSS_PI_152,"
hexmask.long.byte 0x48 0.--7. 1. "PI_MONITOR_STROBE,Strobe the pi_monitor once"
line.long 0x4C "DDRSS_PI_153,"
bitfld.long 0x4C 16.--20. "PI_FREQ_RETENTION_NUM,Monitor active freq number in PI for data_retention" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x4C 8.--12. "PI_FREQ_NUMBER_STATUS,Monitor active freq number in PI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x4C 0. "PI_DLL_LOCK,Monitor dfi_init_complete from PHY" "0,1"
line.long 0x50 "DDRSS_PI_154,"
bitfld.long 0x50 16. "PI_POWER_REDUC_EN,PI Power reduction enable " "0,1"
bitfld.long 0x50 0.--1. "PI_PHYMSTR_TYPE,Defines how the controller should set the state of DRAM before turning control of the DFI bus over to the PI" "0,1,2,3"
group.long 0x227C++0x13
line.long 0x00 "DDRSS_PI_159,"
hexmask.long.word 0x00 8.--16. 1. "PI_TREFBW_THR,Threshold value to control the AREF command interval"
hexmask.long.byte 0x00 0.--7. 1. "PI_WRLVL_MAX_STROBE_PEND,Defines the maximum number of wrlvl_strobes that be accumulated before an AREF is prevented from being generated"
line.long 0x04 "DDRSS_PI_160,"
bitfld.long 0x04 0.--4. "PI_FREQ_CHANGE_REG_COPY,In non-DFI 4.0 mode contains the frequency copy value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DDRSS_PI_161,"
bitfld.long 0x08 24.--27. "PI_CATR,It indicates LP4 DRAM CA terminition ON/OFF state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16. "PI_PARALLEL_CALVL_EN,Enable parallel channel CA training for LPDDR4" "0,1"
bitfld.long 0x08 0. "PI_FREQ_SEL_FROM_REGIF,In non-DFI 4.0 mode user select the frequency copies from pi_freq_change_reg_copy" "0,1"
line.long 0x0C "DDRSS_PI_162,"
bitfld.long 0x0C 24. "PI_NOTCARE_MC_INIT_START,Defines whether PI waits for the controller to initiate dfi_init_start before PI memory initialization " "0,1"
bitfld.long 0x0C 16. "PI_DISCONNECT_MC,PI disconnects the controller from the PHY " "0,1"
bitfld.long 0x0C 8. "PI_MASK_INIT_COMPLETE,Enable the masking of the dfi_init_complete signal back to the controller " "0,1"
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bitfld.long 0x0C 0. "PI_NO_CATR_READ,Defines how the LPDDR4 termination status is determined" "0,1"
line.long 0x10 "DDRSS_PI_163,"
hexmask.long.byte 0x10 24.--31. 1. "PI_TSDO_F2,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 2 in PI clocks"
hexmask.long.byte 0x10 16.--23. 1. "PI_TSDO_F1,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 1 in PI clocks"
hexmask.long.byte 0x10 8.--15. 1. "PI_TSDO_F0,The delay from the read preamble training MRS command to the data strobe drive out for frequency set 0 in PI clocks"
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bitfld.long 0x10 0. "PI_TRACE_MC_MR13,Defines whether PI monitors controller mr13 mrw or not" "0,1"
group.long 0x2298++0x43
line.long 0x00 "DDRSS_PI_166,"
hexmask.long.word 0x00 8.--19. 1. "PI_ZQINIT_F0,Number of cycles needed for a ZQINIT command for frequency set 0"
hexmask.long.byte 0x00 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F2,The delay from read or write to bus idle for frequency set 2"
line.long 0x04 "DDRSS_PI_167,"
hexmask.long.word 0x04 16.--27. 1. "PI_ZQINIT_F2,Number of cycles needed for a ZQINIT command for frequency set 2"
hexmask.long.word 0x04 0.--11. 1. "PI_ZQINIT_F1,Number of cycles needed for a ZQINIT command for frequency set 1"
line.long 0x08 "DDRSS_PI_168,"
hexmask.long.byte 0x08 24.--30. 1. "PI_CASLAT_LIN_F1,Sets latency from read command sent to data received from/to controller for frequency set 1"
hexmask.long.byte 0x08 16.--22. 1. "PI_WRLAT_F1,DRAM WRLAT value in cycles for frequency set 1"
hexmask.long.byte 0x08 8.--14. 1. "PI_CASLAT_LIN_F0,Sets latency from read command sent to data received from/to controller for frequency set 0"
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hexmask.long.byte 0x08 0.--6. 1. "PI_WRLAT_F0,DRAM WRLAT value in cycles for frequency set 0"
line.long 0x0C "DDRSS_PI_169,"
hexmask.long.word 0x0C 16.--25. 1. "PI_TRFC_F0,DRAM tRFC value in memory clocks for frequency set 0"
hexmask.long.byte 0x0C 8.--14. 1. "PI_CASLAT_LIN_F2,Sets latency from read command sent to data received from/to controller for frequency set 2"
hexmask.long.byte 0x0C 0.--6. 1. "PI_WRLAT_F2,DRAM WRLAT value in cycles for frequency set 2"
line.long 0x10 "DDRSS_PI_170,"
hexmask.long.tbyte 0x10 0.--19. 1. "PI_TREF_F0,DRAM tREF value in memory clocks for frequency set 0"
line.long 0x14 "DDRSS_PI_171,"
hexmask.long.word 0x14 0.--9. 1. "PI_TRFC_F1,DRAM tRFC value in memory clocks for frequency set 1"
line.long 0x18 "DDRSS_PI_172,"
hexmask.long.tbyte 0x18 0.--19. 1. "PI_TREF_F1,DRAM tREF value in memory clocks for frequency set 1"
line.long 0x1C "DDRSS_PI_173,"
hexmask.long.word 0x1C 0.--9. 1. "PI_TRFC_F2,DRAM tRFC value in memory clocks for frequency set 2"
line.long 0x20 "DDRSS_PI_174,"
bitfld.long 0x20 24.--27. "PI_TDFI_CTRL_DELAY_F0,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 0 the delay between a DFI command change and a memory command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x20 0.--19. 1. "PI_TREF_F2,DRAM tREF value in memory clocks for frequency set 2"
line.long 0x24 "DDRSS_PI_175,"
bitfld.long 0x24 24.--25. "PI_WRLVL_EN_F1,Enable the PI write leveling module for frequency set 1" "0,1,2,3"
bitfld.long 0x24 16.--17. "PI_WRLVL_EN_F0,Enable the PI write leveling module for frequency set 0" "0,1,2,3"
bitfld.long 0x24 8.--11. "PI_TDFI_CTRL_DELAY_F2,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 2 the delay between a DFI command change and a memory command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0.--3. "PI_TDFI_CTRL_DELAY_F1,Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 1 the delay between a DFI command change and a memory command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "DDRSS_PI_176,"
hexmask.long.word 0x28 8.--17. 1. "PI_TDFI_WRLVL_WW_F0,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 0 the minimum cycles between dfi_wrlvl_strobe assertions"
bitfld.long 0x28 0.--1. "PI_WRLVL_EN_F2,Enable the PI write leveling module for frequency set 2" "0,1,2,3"
line.long 0x2C "DDRSS_PI_177,"
hexmask.long.word 0x2C 16.--25. 1. "PI_TDFI_WRLVL_WW_F2,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 2 the minimum cycles between dfi_wrlvl_strobe assertions"
hexmask.long.word 0x2C 0.--9. 1. "PI_TDFI_WRLVL_WW_F1,Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 1 the minimum cycles between dfi_wrlvl_strobe assertions"
line.long 0x30 "DDRSS_PI_178,"
bitfld.long 0x30 24. "PI_ODT_EN_F1,Enable support of DRAM ODT" "0,1"
hexmask.long.byte 0x30 16.--23. 1. "PI_TODTL_2CMD_F1,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command for frequency set 1"
bitfld.long 0x30 8. "PI_ODT_EN_F0,Enable support of DRAM ODT" "0,1"
newline
hexmask.long.byte 0x30 0.--7. 1. "PI_TODTL_2CMD_F0,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command for frequency set 0"
line.long 0x34 "DDRSS_PI_179,"
bitfld.long 0x34 24.--27. "PI_TODTON_MIN_F0,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 16.--19. "PI_ODTLON_F0,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 8. "PI_ODT_EN_F2,Enable support of DRAM ODT" "0,1"
newline
hexmask.long.byte 0x34 0.--7. 1. "PI_TODTL_2CMD_F2,Defines the DRAM delay from an ODT de-assertion to the next non-write non-read command for frequency set 2"
line.long 0x38 "DDRSS_PI_180,"
bitfld.long 0x38 24.--27. "PI_TODTON_MIN_F2,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 16.--19. "PI_ODTLON_F2,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 8.--11. "PI_TODTON_MIN_F1,Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 0.--3. "PI_ODTLON_F1,Defines the latency from a CAS-2 command to the tODTon reference for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DDRSS_PI_181,"
bitfld.long 0x3C 24.--25. "PI_RDLVL_GATE_EN_F1,Enable the PI gate training module for frequency set 1" "0,1,2,3"
bitfld.long 0x3C 16.--17. "PI_RDLVL_EN_F1,Enable the PI data eye training module for frequency set 1" "0,1,2,3"
bitfld.long 0x3C 8.--9. "PI_RDLVL_GATE_EN_F0,Enable the PI gate training module for frequency set 0" "0,1,2,3"
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bitfld.long 0x3C 0.--1. "PI_RDLVL_EN_F0,Enable the PI data eye training module for frequency set 0" "0,1,2,3"
line.long 0x40 "DDRSS_PI_182,"
bitfld.long 0x40 24.--25. "PI_RDLVL_RXCAL_EN_F0,Enable RX Offset calibration (PATTERN 14 15) for read training for frequency set 0" "0,1,2,3"
bitfld.long 0x40 16.--17. "PI_RDLVL_PAT0_EN_F0,Enable PATTERN-0 for read training for frequency set 0" "0,1,2,3"
bitfld.long 0x40 8.--9. "PI_RDLVL_GATE_EN_F2,Enable the PI gate training module for frequency set 2" "0,1,2,3"
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bitfld.long 0x40 0.--1. "PI_RDLVL_EN_F2,Enable the PI data eye training module for frequency set 2" "0,1,2,3"
group.long 0x22E4++0x1B
line.long 0x00 "DDRSS_PI_185,"
hexmask.long.byte 0x00 24.--30. 1. "PI_RDLAT_ADJ_F1,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 1"
hexmask.long.byte 0x00 16.--22. 1. "PI_RDLAT_ADJ_F0,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 0"
bitfld.long 0x00 8.--9. "PI_RDLVL_MULTI_EN_F2,Enable Multi-pattern (from PI_RDLVL_PATTERN_START total PI_RDLVL_PATTERN_NUM) for read training for frequency set 2" "0,1,2,3"
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bitfld.long 0x00 0.--1. "PI_RDLVL_DFE_EN_F2,Enable DFE (PATTERN 8 9) for read training for frequency set 2" "0,1,2,3"
line.long 0x04 "DDRSS_PI_186,"
hexmask.long.byte 0x04 24.--30. 1. "PI_WRLAT_ADJ_F2,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 2"
hexmask.long.byte 0x04 16.--22. 1. "PI_WRLAT_ADJ_F1,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 1"
hexmask.long.byte 0x04 8.--14. 1. "PI_WRLAT_ADJ_F0,Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 0"
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hexmask.long.byte 0x04 0.--6. 1. "PI_RDLAT_ADJ_F2,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 2"
line.long 0x08 "DDRSS_PI_187,"
bitfld.long 0x08 16.--18. "PI_TDFI_PHY_WRDATA_F2,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 2 the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--10. "PI_TDFI_PHY_WRDATA_F1,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 1 the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "PI_TDFI_PHY_WRDATA_F0,Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 0 the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal" "0,1,2,3,4,5,6,7"
line.long 0x0C "DDRSS_PI_188,"
hexmask.long.word 0x0C 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F0,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 0 the minimum cycles between a calibration command and a dfi_calvl_capture pulse"
hexmask.long.word 0x0C 0.--9. 1. "PI_TDFI_CALVL_CC_F0,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 0 the minimum cycles between calibration commands"
line.long 0x10 "DDRSS_PI_189,"
hexmask.long.word 0x10 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F1,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 1 the minimum cycles between a calibration command and a dfi_calvl_capture pulse"
hexmask.long.word 0x10 0.--9. 1. "PI_TDFI_CALVL_CC_F1,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 1 the minimum cycles between calibration commands"
line.long 0x14 "DDRSS_PI_190,"
hexmask.long.word 0x14 16.--25. 1. "PI_TDFI_CALVL_CAPTURE_F2,Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 2 the minimum cycles between a calibration command and a dfi_calvl_capture pulse"
hexmask.long.word 0x14 0.--9. 1. "PI_TDFI_CALVL_CC_F2,Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 2 the minimum cycles between calibration commands"
line.long 0x18 "DDRSS_PI_191,"
bitfld.long 0x18 24.--28. "PI_TMRZ_F0,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--17. "PI_CALVL_EN_F2,Enable the PI CA training module" "0,1,2,3"
bitfld.long 0x18 8.--9. "PI_CALVL_EN_F1,Enable the PI CA training module" "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "PI_CALVL_EN_F0,Enable the PI CA training module" "0,1,2,3"
group.long 0x2308++0x1F
line.long 0x00 "DDRSS_PI_194,"
bitfld.long 0x00 24.--28. "PI_TDFI_CASEL_F0,Defines the DFI tcalvl_ca_sel timing parameter the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PI_TDFI_CACSCA_F0,Defines the DFI tcalvl_cs_ca timing parameter the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "PI_TCAENT_F2,Defines the DRAM tCAENT term in memory clocks for frequency set 2"
line.long 0x04 "DDRSS_PI_195,"
hexmask.long.word 0x04 16.--25. 1. "PI_TVREF_LONG_F0,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 0"
hexmask.long.word 0x04 0.--9. 1. "PI_TVREF_SHORT_F0,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 0"
line.long 0x08 "DDRSS_PI_196,"
hexmask.long.word 0x08 16.--25. 1. "PI_TVREF_SHORT_F1,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 1"
bitfld.long 0x08 8.--12. "PI_TDFI_CASEL_F1,Defines the DFI tcalvl_ca_sel timing parameter the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "PI_TDFI_CACSCA_F1,Defines the DFI tcalvl_cs_ca timing parameter the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "DDRSS_PI_197,"
bitfld.long 0x0C 24.--28. "PI_TDFI_CASEL_F2,Defines the DFI tcalvl_ca_sel timing parameter the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "PI_TDFI_CACSCA_F2,Defines the DFI tcalvl_cs_ca timing parameter the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 0.--9. 1. "PI_TVREF_LONG_F1,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 1"
line.long 0x10 "DDRSS_PI_198,"
hexmask.long.word 0x10 16.--25. 1. "PI_TVREF_LONG_F2,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 2"
hexmask.long.word 0x10 0.--9. 1. "PI_TVREF_SHORT_F2,Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 2"
line.long 0x14 "DDRSS_PI_199,"
hexmask.long.byte 0x14 24.--30. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F1,The end point of initial training for the Vref(ca) training for frequency set 1 { vrefca_range vref_ca_setting"
hexmask.long.byte 0x14 16.--22. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F1,The start point of initial training for the Vref(ca) training for frequency set 1 { vrefca_range vref_ca_setting"
hexmask.long.byte 0x14 8.--14. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F0,The end point of initial training for the Vref(ca) training for frequency set 0 { vrefca_range vref_ca_setting"
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hexmask.long.byte 0x14 0.--6. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F0,The start point of initial training for the Vref(ca) training for frequency set 0 { vrefca_range vref_ca_setting"
line.long 0x18 "DDRSS_PI_200,"
bitfld.long 0x18 24.--27. "PI_CALVL_VREF_DELTA_F1,The delta fro the current CA vref for non-initial CA training for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "PI_CALVL_VREF_DELTA_F0,The delta fro the current CA vref for non-initial CA training for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x18 8.--14. 1. "PI_CALVL_VREF_INITIAL_STOP_POINT_F2,The end point of initial training for the Vref(ca) training for frequency set 2 { vrefca_range vref_ca_setting"
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hexmask.long.byte 0x18 0.--6. 1. "PI_CALVL_VREF_INITIAL_START_POINT_F2,The start point of initial training for the Vref(ca) training for frequency set 2 { vrefca_range vref_ca_setting"
line.long 0x1C "DDRSS_PI_201,"
hexmask.long.byte 0x1C 24.--31. 1. "PI_TMRWCKEL_F0,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 0"
bitfld.long 0x1C 16.--20. "PI_TXP_F0,CKE assert to next valid command delay for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--11. "PI_TDFI_CALVL_STROBE_F0,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 0.--3. "PI_CALVL_VREF_DELTA_F2,The delta fro the current CA vref for non-initial CA training for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2330++0x0F
line.long 0x00 "DDRSS_PI_204,"
hexmask.long.word 0x00 8.--17. 1. "PI_TDFI_INIT_START_F0,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 0 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY"
bitfld.long 0x00 0.--4. "PI_TCKELCK_F2,Valid Clock Requirement after CKE deassert for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRSS_PI_205,"
hexmask.long.word 0x04 16.--25. 1. "PI_TDFI_INIT_START_F1,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 1 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY"
hexmask.long.word 0x04 0.--15. 1. "PI_TDFI_INIT_COMPLETE_F0,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 0 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY"
line.long 0x08 "DDRSS_PI_206,"
hexmask.long.word 0x08 16.--25. 1. "PI_TDFI_INIT_START_F2,Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 2 the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY"
hexmask.long.word 0x08 0.--15. 1. "PI_TDFI_INIT_COMPLETE_F1,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 1 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY"
line.long 0x0C "DDRSS_PI_207,"
bitfld.long 0x0C 16.--21. "PI_TCKEHDQS_F0,The DRAM timing tCKEHDQS minimum delay from CKE high to strobe high impedance for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--15. 1. "PI_TDFI_INIT_COMPLETE_F2,Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 2 the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY"
group.long 0x2348++0xBF
line.long 0x00 "DDRSS_PI_210,"
hexmask.long.word 0x00 16.--25. 1. "PI_TDFI_WDQLVL_WR_F0,Switch time from write to read for frequency set 0"
hexmask.long.word 0x00 0.--9. 1. "PI_TFC_F2,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 2"
line.long 0x04 "DDRSS_PI_211,"
hexmask.long.byte 0x04 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0,Write DQ training vref initial training stop value for frequency set 0"
hexmask.long.byte 0x04 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F0,Write DQ training vref initial training start value for frequency set 0"
hexmask.long.word 0x04 0.--9. 1. "PI_TDFI_WDQLVL_RW_F0,Switch time from read to write for frequency set 0"
line.long 0x08 "DDRSS_PI_212,"
bitfld.long 0x08 16.--17. "PI_NTP_TRAIN_EN_F0,Indicates whether the no topology WDQ training is enabled" "0,1,2,3"
bitfld.long 0x08 8.--9. "PI_WDQLVL_EN_F0,Indicates if Write DQ leveling is enabled for frequency set 0" "0,1,2,3"
bitfld.long 0x08 0.--3. "PI_WDQLVL_VREF_DELTA_F0,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DDRSS_PI_213,"
hexmask.long.word 0x0C 16.--25. 1. "PI_TDFI_WDQLVL_RW_F1,Switch time from read to write for frequency set 1"
hexmask.long.word 0x0C 0.--9. 1. "PI_TDFI_WDQLVL_WR_F1,Switch time from write to read for frequency set 1"
line.long 0x10 "DDRSS_PI_214,"
bitfld.long 0x10 24.--25. "PI_WDQLVL_EN_F1,Indicates if Write DQ leveling is enabled for frequency set 1" "0,1,2,3"
bitfld.long 0x10 16.--19. "PI_WDQLVL_VREF_DELTA_F1,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--14. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1,Write DQ training vref initial training stop value for frequency set 1"
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hexmask.long.byte 0x10 0.--6. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F1,Write DQ training vref initial training start value for frequency set 1"
line.long 0x14 "DDRSS_PI_215,"
hexmask.long.word 0x14 8.--17. 1. "PI_TDFI_WDQLVL_WR_F2,Switch time from write to read for frequency set 2"
bitfld.long 0x14 0.--1. "PI_NTP_TRAIN_EN_F1,Indicates whether the no topology WDQ training is enabled" "0,1,2,3"
line.long 0x18 "DDRSS_PI_216,"
hexmask.long.byte 0x18 24.--30. 1. "PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2,Write DQ training vref initial training stop value for frequency set 2"
hexmask.long.byte 0x18 16.--22. 1. "PI_WDQLVL_VREF_INITIAL_START_POINT_F2,Write DQ training vref initial training start value for frequency set 2"
hexmask.long.word 0x18 0.--9. 1. "PI_TDFI_WDQLVL_RW_F2,Switch time from read to write for frequency set 2"
line.long 0x1C "DDRSS_PI_217,"
hexmask.long.byte 0x1C 24.--31. 1. "PI_TRTP_F0,DRAM tRTP value in cycles for frequency set 0"
bitfld.long 0x1C 16.--17. "PI_NTP_TRAIN_EN_F2,Indicates whether the no topology WDQ training is enabled" "0,1,2,3"
bitfld.long 0x1C 8.--9. "PI_WDQLVL_EN_F2,Indicates if Write DQ leveling is enabled for frequency set 2" "0,1,2,3"
newline
bitfld.long 0x1C 0.--3. "PI_WDQLVL_VREF_DELTA_F2,The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "DDRSS_PI_218,"
hexmask.long.byte 0x20 24.--31. 1. "PI_TWR_F0,DRAM tWR value in cycles for frequency set 0"
bitfld.long 0x20 16.--21. "PI_TWTR_F0,DRAM tWTR value in cycles for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 8.--15. 1. "PI_TRCD_F0,DRAM tRCD value in cycles for frequency set 0"
newline
hexmask.long.byte 0x20 0.--7. 1. "PI_TRP_F0,DRAM tRP value in cycles for frequency set 0"
line.long 0x24 "DDRSS_PI_219,"
hexmask.long.byte 0x24 24.--31. 1. "PI_TRAS_MIN_F0,DRAM tRAS_MIN value in cycles for frequency set 0"
hexmask.long.tbyte 0x24 0.--16. 1. "PI_TRAS_MAX_F0,DRAM tRAS_MAX value in cycles for frequency set 0"
line.long 0x28 "DDRSS_PI_220,"
hexmask.long.byte 0x28 24.--31. 1. "PI_TMRD_F0,DRAM tMRD value in cycles for frequency set 0"
hexmask.long.byte 0x28 16.--23. 1. "PI_TSR_F0,Min cycles from sref entry to sref exit for frequency set 0"
bitfld.long 0x28 8.--13. "PI_TCCDMW_F0,LPDDR4 DRAM tCCDMW in cycles for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 0.--3. "PI_TDQSCK_MAX_F0,Additional delay needed for tDQSCK for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DDRSS_PI_221,"
hexmask.long.byte 0x2C 24.--31. 1. "PI_TRCD_F1,DRAM tRCD value in cycles for frequency set 1"
hexmask.long.byte 0x2C 16.--23. 1. "PI_TRP_F1,DRAM tRP value in cycles for frequency set 1"
hexmask.long.byte 0x2C 8.--15. 1. "PI_TRTP_F1,DRAM tRTP value in cycles for frequency set 1"
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hexmask.long.byte 0x2C 0.--7. 1. "PI_TMRW_F0,DRAM tMRW value in cycles for frequency set 0"
line.long 0x30 "DDRSS_PI_222,"
hexmask.long.byte 0x30 8.--15. 1. "PI_TWR_F1,DRAM tWR value in cycles for frequency set 1"
bitfld.long 0x30 0.--5. "PI_TWTR_F1,DRAM tWTR value in cycles for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x34 "DDRSS_PI_223,"
hexmask.long.byte 0x34 24.--31. 1. "PI_TRAS_MIN_F1,DRAM tRAS_MIN value in cycles for frequency set 1"
hexmask.long.tbyte 0x34 0.--16. 1. "PI_TRAS_MAX_F1,DRAM tRAS_MAX value in cycles for frequency set 1"
line.long 0x38 "DDRSS_PI_224,"
hexmask.long.byte 0x38 24.--31. 1. "PI_TMRD_F1,DRAM tMRD value in cycles for frequency set 1"
hexmask.long.byte 0x38 16.--23. 1. "PI_TSR_F1,Min cycles from sref entry to sref exit for frequency set 1"
bitfld.long 0x38 8.--13. "PI_TCCDMW_F1,LPDDR4 DRAM tCCDMW in cycles for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 0.--3. "PI_TDQSCK_MAX_F1,Additional delay needed for tDQSCK for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DDRSS_PI_225,"
hexmask.long.byte 0x3C 24.--31. 1. "PI_TRCD_F2,DRAM tRCD value in cycles for frequency set 2"
hexmask.long.byte 0x3C 16.--23. 1. "PI_TRP_F2,DRAM tRP value in cycles for frequency set 2"
hexmask.long.byte 0x3C 8.--15. 1. "PI_TRTP_F2,DRAM tRTP value in cycles for frequency set 2"
newline
hexmask.long.byte 0x3C 0.--7. 1. "PI_TMRW_F1,DRAM tMRW value in cycles for frequency set 1"
line.long 0x40 "DDRSS_PI_226,"
hexmask.long.byte 0x40 8.--15. 1. "PI_TWR_F2,DRAM tWR value in cycles for frequency set 2"
bitfld.long 0x40 0.--5. "PI_TWTR_F2,DRAM tWTR value in cycles for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "DDRSS_PI_227,"
hexmask.long.byte 0x44 24.--31. 1. "PI_TRAS_MIN_F2,DRAM tRAS_MIN value in cycles for frequency set 2"
hexmask.long.tbyte 0x44 0.--16. 1. "PI_TRAS_MAX_F2,DRAM tRAS_MAX value in cycles for frequency set 2"
line.long 0x48 "DDRSS_PI_228,"
hexmask.long.byte 0x48 24.--31. 1. "PI_TMRD_F2,DRAM tMRD value in cycles for frequency set 2"
hexmask.long.byte 0x48 16.--23. 1. "PI_TSR_F2,Min cycles from sref entry to sref exit for frequency set 2"
bitfld.long 0x48 8.--13. "PI_TCCDMW_F2,LPDDR4 DRAM tCCDMW in cycles for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x48 0.--3. "PI_TDQSCK_MAX_F2,Additional delay needed for tDQSCK for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DDRSS_PI_229,"
hexmask.long.tbyte 0x4C 8.--28. 1. "PI_TDFI_CTRLUPD_MAX_F0,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 0 the maximum cycles that dfi_ctrlupd_req can be asserted"
hexmask.long.byte 0x4C 0.--7. 1. "PI_TMRW_F2,DRAM tMRW value in cycles for frequency set 2"
line.long 0x50 "DDRSS_PI_230,"
line.long 0x54 "DDRSS_PI_231,"
hexmask.long.tbyte 0x54 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F1,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 1 the maximum cycles that dfi_ctrlupd_req can be asserted"
line.long 0x58 "DDRSS_PI_232,"
line.long 0x5C "DDRSS_PI_233,"
hexmask.long.tbyte 0x5C 0.--20. 1. "PI_TDFI_CTRLUPD_MAX_F2,Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 2 the maximum cycles that dfi_ctrlupd_req can be asserted"
line.long 0x60 "DDRSS_PI_234,"
line.long 0x64 "DDRSS_PI_235,"
hexmask.long.word 0x64 16.--31. 1. "PI_TXSR_F1,DRAM TXSR value for frequency set 1 in cycles"
hexmask.long.word 0x64 0.--15. 1. "PI_TXSR_F0,DRAM TXSR value for frequency set 0 in cycles"
line.long 0x68 "DDRSS_PI_236,"
bitfld.long 0x68 24.--29. "PI_TEXCKE_F1,DRAM CKE low after SREF command timing for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x68 16.--21. "PI_TEXCKE_F0,DRAM CKE low after SREF command timing for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x68 0.--15. 1. "PI_TXSR_F2,DRAM TXSR value for frequency set 2 in cycles"
line.long 0x6C "DDRSS_PI_237,"
hexmask.long.tbyte 0x6C 8.--31. 1. "PI_TINIT_F0,DRAM tINIT value for frequency set 0 in cycles"
bitfld.long 0x6C 0.--5. "PI_TEXCKE_F2,DRAM CKE low after SREF command timing for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x70 "DDRSS_PI_238,"
hexmask.long.tbyte 0x70 0.--23. 1. "PI_TINIT3_F0,DRAM tINIT3 value for frequency set 0 in cycles"
line.long 0x74 "DDRSS_PI_239,"
hexmask.long.tbyte 0x74 0.--23. 1. "PI_TINIT4_F0,DRAM tINIT4 value for frequency set 0 in cycles"
line.long 0x78 "DDRSS_PI_240,"
hexmask.long.tbyte 0x78 0.--23. 1. "PI_TINIT5_F0,DRAM tINIT5 value for frequency set 0 in cycles"
line.long 0x7C "DDRSS_PI_241,"
hexmask.long.word 0x7C 0.--15. 1. "PI_TXSNR_F0,DRAM tXSNR value for frequency set 0 in cycles"
line.long 0x80 "DDRSS_PI_242,"
hexmask.long.tbyte 0x80 0.--23. 1. "PI_TINIT_F1,DRAM tINIT value for frequency set 1 in cycles"
line.long 0x84 "DDRSS_PI_243,"
hexmask.long.tbyte 0x84 0.--23. 1. "PI_TINIT3_F1,DRAM tINIT3 value for frequency set 1 in cycles"
line.long 0x88 "DDRSS_PI_244,"
hexmask.long.tbyte 0x88 0.--23. 1. "PI_TINIT4_F1,DRAM tINIT4 value for frequency set 1 in cycles"
line.long 0x8C "DDRSS_PI_245,"
hexmask.long.tbyte 0x8C 0.--23. 1. "PI_TINIT5_F1,DRAM tINIT5 value for frequency set 1 in cycles"
line.long 0x90 "DDRSS_PI_246,"
hexmask.long.word 0x90 0.--15. 1. "PI_TXSNR_F1,DRAM tXSNR value for frequency set 1 in cycles"
line.long 0x94 "DDRSS_PI_247,"
hexmask.long.tbyte 0x94 0.--23. 1. "PI_TINIT_F2,DRAM tINIT value for frequency set 2 in cycles"
line.long 0x98 "DDRSS_PI_248,"
hexmask.long.tbyte 0x98 0.--23. 1. "PI_TINIT3_F2,DRAM tINIT3 value for frequency set 2 in cycles"
line.long 0x9C "DDRSS_PI_249,"
hexmask.long.tbyte 0x9C 0.--23. 1. "PI_TINIT4_F2,DRAM tINIT4 value for frequency set 2 in cycles"
line.long 0xA0 "DDRSS_PI_250,"
hexmask.long.tbyte 0xA0 0.--23. 1. "PI_TINIT5_F2,DRAM tINIT5 value for frequency set 2 in cycles"
line.long 0xA4 "DDRSS_PI_251,"
hexmask.long.word 0xA4 0.--15. 1. "PI_TXSNR_F2,DRAM tXSNR value for frequency set 2 in cycles"
line.long 0xA8 "DDRSS_PI_252,"
hexmask.long.word 0xA8 16.--27. 1. "PI_TZQCAL_F0,Holds the DRAM ZQCAL value for frequency set 0 in cycles"
line.long 0xAC "DDRSS_PI_253,"
hexmask.long.byte 0xAC 0.--6. 1. "PI_TZQLAT_F0,Holds the DRAM ZQLAT value for frequency set 0 in cycles"
line.long 0xB0 "DDRSS_PI_254,"
hexmask.long.word 0xB0 16.--27. 1. "PI_TZQCAL_F1,Holds the DRAM ZQCAL value for frequency set 1 in cycles"
line.long 0xB4 "DDRSS_PI_255,"
hexmask.long.byte 0xB4 0.--6. 1. "PI_TZQLAT_F1,Holds the DRAM ZQLAT value for frequency set 1 in cycles"
line.long 0xB8 "DDRSS_PI_256,"
hexmask.long.word 0xB8 16.--27. 1. "PI_TZQCAL_F2,Holds the DRAM ZQCAL value for frequency set 2 in cycles"
line.long 0xBC "DDRSS_PI_257,"
hexmask.long.byte 0xBC 0.--6. 1. "PI_TZQLAT_F2,Holds the DRAM ZQLAT value for frequency set 2 in cycles"
group.long 0x240C++0x37
line.long 0x00 "DDRSS_PI_259,"
hexmask.long.byte 0x00 24.--31. 1. "PI_MR13_DATA_0,Data to program into memory mode register 13 for chip select 0"
bitfld.long 0x00 16.--19. "PI_WDQ_OSC_DELTA_INDEX_F2,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PI_WDQ_OSC_DELTA_INDEX_F1,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "PI_WDQ_OSC_DELTA_INDEX_F0,WDQ DQS delay delta index for OSC triggered periodic training for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DDRSS_PI_260,"
hexmask.long.byte 0x04 24.--31. 1. "PI_MR20_DATA_0,Data to program into memory mode register 20 for chip select 0"
hexmask.long.byte 0x04 16.--23. 1. "PI_MR17_DATA_0,Data to program into memory mode register 17 for chip select 0"
hexmask.long.byte 0x04 8.--15. 1. "PI_MR16_DATA_0,Data to program into memory mode register 16 for chip select 0"
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hexmask.long.byte 0x04 0.--7. 1. "PI_MR15_DATA_0,Data to program into memory mode register 15 for chip select 0"
line.long 0x08 "DDRSS_PI_261,"
hexmask.long.byte 0x08 24.--31. 1. "PI_MR15_DATA_1,Data to program into memory mode register 15 for chip select 1"
hexmask.long.byte 0x08 16.--23. 1. "PI_MR13_DATA_1,Data to program into memory mode register 13 for chip select 1"
hexmask.long.byte 0x08 8.--15. 1. "PI_MR40_DATA_0,Data to program into memory mode register 40 for chip select 0"
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hexmask.long.byte 0x08 0.--7. 1. "PI_MR32_DATA_0,Data to program into memory mode register 32 for chip select 0"
line.long 0x0C "DDRSS_PI_262,"
hexmask.long.byte 0x0C 24.--31. 1. "PI_MR32_DATA_1,Data to program into memory mode register 32 for chip select 1"
hexmask.long.byte 0x0C 16.--23. 1. "PI_MR20_DATA_1,Data to program into memory mode register 20 for chip select 1"
hexmask.long.byte 0x0C 8.--15. 1. "PI_MR17_DATA_1,Data to program into memory mode register 17 for chip select 1"
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hexmask.long.byte 0x0C 0.--7. 1. "PI_MR16_DATA_1,Data to program into memory mode register 16 for chip select 1"
line.long 0x10 "DDRSS_PI_263,"
hexmask.long.byte 0x10 24.--31. 1. "PI_MR16_DATA_2,Data to program into memory mode register 16 for chip select 2"
hexmask.long.byte 0x10 16.--23. 1. "PI_MR15_DATA_2,Data to program into memory mode register 15 for chip select 2"
hexmask.long.byte 0x10 8.--15. 1. "PI_MR13_DATA_2,Data to program into memory mode register 13 for chip select 2"
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hexmask.long.byte 0x10 0.--7. 1. "PI_MR40_DATA_1,Data to program into memory mode register 40 for chip select 1"
line.long 0x14 "DDRSS_PI_264,"
hexmask.long.byte 0x14 24.--31. 1. "PI_MR40_DATA_2,Data to program into memory mode register 40 for chip select 2"
hexmask.long.byte 0x14 16.--23. 1. "PI_MR32_DATA_2,Data to program into memory mode register 32 for chip select 2"
hexmask.long.byte 0x14 8.--15. 1. "PI_MR20_DATA_2,Data to program into memory mode register 20 for chip select 2"
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hexmask.long.byte 0x14 0.--7. 1. "PI_MR17_DATA_2,Data to program into memory mode register 17 for chip select 2"
line.long 0x18 "DDRSS_PI_265,"
hexmask.long.byte 0x18 24.--31. 1. "PI_MR17_DATA_3,Data to program into memory mode register 17 for chip select 3"
hexmask.long.byte 0x18 16.--23. 1. "PI_MR16_DATA_3,Data to program into memory mode register 16 for chip select 3"
hexmask.long.byte 0x18 8.--15. 1. "PI_MR15_DATA_3,Data to program into memory mode register 15 for chip select 3"
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hexmask.long.byte 0x18 0.--7. 1. "PI_MR13_DATA_3,Data to program into memory mode register 13 for chip select 3"
line.long 0x1C "DDRSS_PI_266,"
bitfld.long 0x1C 24.--27. "PI_CKE_MUX_0,Command pin CKE_0 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1C 16.--23. 1. "PI_MR40_DATA_3,Data to program into memory mode register 40 for chip select 3"
hexmask.long.byte 0x1C 8.--15. 1. "PI_MR32_DATA_3,Data to program into memory mode register 32 for chip select 3"
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hexmask.long.byte 0x1C 0.--7. 1. "PI_MR20_DATA_3,Data to program into memory mode register 20 for chip select 3"
line.long 0x20 "DDRSS_PI_267,"
bitfld.long 0x20 24.--27. "PI_CS_MUX_0,Command pin CS_0 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 16.--19. "PI_CKE_MUX_3,Command pin CKE_3 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 8.--11. "PI_CKE_MUX_2,Command pin CKE_2 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--3. "PI_CKE_MUX_1,Command pin CKE_1 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDRSS_PI_268,"
bitfld.long 0x24 24.--27. "PI_RESET_N_MUX_0,Command pin RESET_N_0 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 16.--19. "PI_CS_MUX_3,Command pin CS_3 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 8.--11. "PI_CS_MUX_2,Command pin CS_2 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0.--3. "PI_CS_MUX_1,Command pin CS_1 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "DDRSS_PI_269,"
hexmask.long.byte 0x28 24.--31. 1. "PI_MRSINGLE_DATA_0,Data to program into memory mode register single write to chip select 0"
bitfld.long 0x28 16.--19. "PI_RESET_N_MUX_3,Command pin RESET_N_3 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 8.--11. "PI_RESET_N_MUX_2,Command pin RESET_N_2 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "PI_RESET_N_MUX_1,Command pin RESET_N_1 mux selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "DDRSS_PI_270,"
bitfld.long 0x2C 24.--27. "PI_ZQ_CAL_START_MAP_0,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x2C 16.--23. 1. "PI_MRSINGLE_DATA_3,Data to program into memory mode register single write to chip select 3"
hexmask.long.byte 0x2C 8.--15. 1. "PI_MRSINGLE_DATA_2,Data to program into memory mode register single write to chip select 2"
newline
hexmask.long.byte 0x2C 0.--7. 1. "PI_MRSINGLE_DATA_1,Data to program into memory mode register single write to chip select 1"
line.long 0x30 "DDRSS_PI_271,"
bitfld.long 0x30 24.--27. "PI_ZQ_CAL_START_MAP_2,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 2 of the ZQ START initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 16.--19. "PI_ZQ_CAL_LATCH_MAP_1,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 8.--11. "PI_ZQ_CAL_START_MAP_1,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x30 0.--3. "PI_ZQ_CAL_LATCH_MAP_0,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DDRSS_PI_272,"
bitfld.long 0x34 16.--19. "PI_ZQ_CAL_LATCH_MAP_3,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 3 of the ZQ LATCH initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 8.--11. "PI_ZQ_CAL_START_MAP_3,Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 3 of the ZQ START initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 0.--3. "PI_ZQ_CAL_LATCH_MAP_2,Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 2 of the ZQ LATCH initialization and periodic command sequences" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x244C++0x63
line.long 0x00 "DDRSS_PI_275,"
hexmask.long.byte 0x00 24.--31. 1. "PI_MR11_DATA_F0_0,Data to program into memory mode register 11 for chip select 0 for frequency set 0"
hexmask.long.byte 0x00 16.--23. 1. "PI_MR3_DATA_F0_0,Data to program into memory mode register 3 for chip select 0 for frequency set 0"
hexmask.long.byte 0x00 8.--15. 1. "PI_MR2_DATA_F0_0,Data to program into memory mode register 2 for chip select 0 for frequency set 0"
newline
hexmask.long.byte 0x00 0.--7. 1. "PI_MR1_DATA_F0_0,Data to program into memory mode register 1 for chip select 0 for frequency set 0"
line.long 0x04 "DDRSS_PI_276,"
hexmask.long.byte 0x04 24.--31. 1. "PI_MR23_DATA_F0_0,Data to program into memory mode register 23 for chip select 0 for frequency set 0"
hexmask.long.byte 0x04 16.--23. 1. "PI_MR22_DATA_F0_0,Data to program into memory mode register 22 for chip select 0 for frequency set 0"
hexmask.long.byte 0x04 8.--15. 1. "PI_MR14_DATA_F0_0,Data to program into memory mode register 14 for chip select 0 for frequency set 0"
newline
hexmask.long.byte 0x04 0.--7. 1. "PI_MR12_DATA_F0_0,Data to program into memory mode register 12 for chip select 0 for frequency set 0"
line.long 0x08 "DDRSS_PI_277,"
hexmask.long.byte 0x08 24.--31. 1. "PI_MR11_DATA_F1_0,Data to program into memory mode register 11 for chip select 0 for frequency set 1"
hexmask.long.byte 0x08 16.--23. 1. "PI_MR3_DATA_F1_0,Data to program into memory mode register 3 for chip select 0 for frequency set 1"
hexmask.long.byte 0x08 8.--15. 1. "PI_MR2_DATA_F1_0,Data to program into memory mode register 2 for chip select 0 for frequency set 1"
newline
hexmask.long.byte 0x08 0.--7. 1. "PI_MR1_DATA_F1_0,Data to program into memory mode register 1 for chip select 0 for frequency set 1"
line.long 0x0C "DDRSS_PI_278,"
hexmask.long.byte 0x0C 24.--31. 1. "PI_MR23_DATA_F1_0,Data to program into memory mode register 23 for chip select 0 for frequency set 1"
hexmask.long.byte 0x0C 16.--23. 1. "PI_MR22_DATA_F1_0,Data to program into memory mode register 22 for chip select 0 for frequency set 1"
hexmask.long.byte 0x0C 8.--15. 1. "PI_MR14_DATA_F1_0,Data to program into memory mode register 14 for chip select 0 for frequency set 1"
newline
hexmask.long.byte 0x0C 0.--7. 1. "PI_MR12_DATA_F1_0,Data to program into memory mode register 12 for chip select 0 for frequency set 1"
line.long 0x10 "DDRSS_PI_279,"
hexmask.long.byte 0x10 24.--31. 1. "PI_MR11_DATA_F2_0,Data to program into memory mode register 11 for chip select 0 for frequency set 2"
hexmask.long.byte 0x10 16.--23. 1. "PI_MR3_DATA_F2_0,Data to program into memory mode register 3 for chip select 0 for frequency set 2"
hexmask.long.byte 0x10 8.--15. 1. "PI_MR2_DATA_F2_0,Data to program into memory mode register 2 for chip select 0 for frequency set 2"
newline
hexmask.long.byte 0x10 0.--7. 1. "PI_MR1_DATA_F2_0,Data to program into memory mode register 1 for chip select 0 for frequency set 2"
line.long 0x14 "DDRSS_PI_280,"
hexmask.long.byte 0x14 24.--31. 1. "PI_MR23_DATA_F2_0,Data to program into memory mode register 23 for chip select 0 for frequency set 2"
hexmask.long.byte 0x14 16.--23. 1. "PI_MR22_DATA_F2_0,Data to program into memory mode register 22 for chip select 0 for frequency set 2"
hexmask.long.byte 0x14 8.--15. 1. "PI_MR14_DATA_F2_0,Data to program into memory mode register 14 for chip select 0 for frequency set 2"
newline
hexmask.long.byte 0x14 0.--7. 1. "PI_MR12_DATA_F2_0,Data to program into memory mode register 12 for chip select 0 for frequency set 2"
line.long 0x18 "DDRSS_PI_281,"
hexmask.long.byte 0x18 24.--31. 1. "PI_MR11_DATA_F0_1,Data to program into memory mode register 11 for chip select 1 for frequency set 0"
hexmask.long.byte 0x18 16.--23. 1. "PI_MR3_DATA_F0_1,Data to program into memory mode register 3 for chip select 1 for frequency set 0"
hexmask.long.byte 0x18 8.--15. 1. "PI_MR2_DATA_F0_1,Data to program into memory mode register 2 for chip select 1 for frequency set 0"
newline
hexmask.long.byte 0x18 0.--7. 1. "PI_MR1_DATA_F0_1,Data to program into memory mode register 1 for chip select 1 for frequency set 0"
line.long 0x1C "DDRSS_PI_282,"
hexmask.long.byte 0x1C 24.--31. 1. "PI_MR23_DATA_F0_1,Data to program into memory mode register 23 for chip select 1 for frequency set 0"
hexmask.long.byte 0x1C 16.--23. 1. "PI_MR22_DATA_F0_1,Data to program into memory mode register 22 for chip select 1 for frequency set 0"
hexmask.long.byte 0x1C 8.--15. 1. "PI_MR14_DATA_F0_1,Data to program into memory mode register 14 for chip select 1 for frequency set 0"
newline
hexmask.long.byte 0x1C 0.--7. 1. "PI_MR12_DATA_F0_1,Data to program into memory mode register 12 for chip select 1 for frequency set 0"
line.long 0x20 "DDRSS_PI_283,"
hexmask.long.byte 0x20 24.--31. 1. "PI_MR11_DATA_F1_1,Data to program into memory mode register 11 for chip select 1 for frequency set 1"
hexmask.long.byte 0x20 16.--23. 1. "PI_MR3_DATA_F1_1,Data to program into memory mode register 3 for chip select 1 for frequency set 1"
hexmask.long.byte 0x20 8.--15. 1. "PI_MR2_DATA_F1_1,Data to program into memory mode register 2 for chip select 1 for frequency set 1"
newline
hexmask.long.byte 0x20 0.--7. 1. "PI_MR1_DATA_F1_1,Data to program into memory mode register 1 for chip select 1 for frequency set 1"
line.long 0x24 "DDRSS_PI_284,"
hexmask.long.byte 0x24 24.--31. 1. "PI_MR23_DATA_F1_1,Data to program into memory mode register 23 for chip select 1 for frequency set 1"
hexmask.long.byte 0x24 16.--23. 1. "PI_MR22_DATA_F1_1,Data to program into memory mode register 22 for chip select 1 for frequency set 1"
hexmask.long.byte 0x24 8.--15. 1. "PI_MR14_DATA_F1_1,Data to program into memory mode register 14 for chip select 1 for frequency set 1"
newline
hexmask.long.byte 0x24 0.--7. 1. "PI_MR12_DATA_F1_1,Data to program into memory mode register 12 for chip select 1 for frequency set 1"
line.long 0x28 "DDRSS_PI_285,"
hexmask.long.byte 0x28 24.--31. 1. "PI_MR11_DATA_F2_1,Data to program into memory mode register 11 for chip select 1 for frequency set 2"
hexmask.long.byte 0x28 16.--23. 1. "PI_MR3_DATA_F2_1,Data to program into memory mode register 3 for chip select 1 for frequency set 2"
hexmask.long.byte 0x28 8.--15. 1. "PI_MR2_DATA_F2_1,Data to program into memory mode register 2 for chip select 1 for frequency set 2"
newline
hexmask.long.byte 0x28 0.--7. 1. "PI_MR1_DATA_F2_1,Data to program into memory mode register 1 for chip select 1 for frequency set 2"
line.long 0x2C "DDRSS_PI_286,"
hexmask.long.byte 0x2C 24.--31. 1. "PI_MR23_DATA_F2_1,Data to program into memory mode register 23 for chip select 1 for frequency set 2"
hexmask.long.byte 0x2C 16.--23. 1. "PI_MR22_DATA_F2_1,Data to program into memory mode register 22 for chip select 1 for frequency set 2"
hexmask.long.byte 0x2C 8.--15. 1. "PI_MR14_DATA_F2_1,Data to program into memory mode register 14 for chip select 1 for frequency set 2"
newline
hexmask.long.byte 0x2C 0.--7. 1. "PI_MR12_DATA_F2_1,Data to program into memory mode register 12 for chip select 1 for frequency set 2"
line.long 0x30 "DDRSS_PI_287,"
hexmask.long.byte 0x30 24.--31. 1. "PI_MR11_DATA_F0_2,Data to program into memory mode register 11 for chip select 2 for frequency set 0"
hexmask.long.byte 0x30 16.--23. 1. "PI_MR3_DATA_F0_2,Data to program into memory mode register 3 for chip select 2 for frequency set 0"
hexmask.long.byte 0x30 8.--15. 1. "PI_MR2_DATA_F0_2,Data to program into memory mode register 2 for chip select 2 for frequency set 0"
newline
hexmask.long.byte 0x30 0.--7. 1. "PI_MR1_DATA_F0_2,Data to program into memory mode register 1 for chip select 2 for frequency set 0"
line.long 0x34 "DDRSS_PI_288,"
hexmask.long.byte 0x34 24.--31. 1. "PI_MR23_DATA_F0_2,Data to program into memory mode register 23 for chip select 2 for frequency set 0"
hexmask.long.byte 0x34 16.--23. 1. "PI_MR22_DATA_F0_2,Data to program into memory mode register 22 for chip select 2 for frequency set 0"
hexmask.long.byte 0x34 8.--15. 1. "PI_MR14_DATA_F0_2,Data to program into memory mode register 14 for chip select 2 for frequency set 0"
newline
hexmask.long.byte 0x34 0.--7. 1. "PI_MR12_DATA_F0_2,Data to program into memory mode register 12 for chip select 2 for frequency set 0"
line.long 0x38 "DDRSS_PI_289,"
hexmask.long.byte 0x38 24.--31. 1. "PI_MR11_DATA_F1_2,Data to program into memory mode register 11 for chip select 2 for frequency set 1"
hexmask.long.byte 0x38 16.--23. 1. "PI_MR3_DATA_F1_2,Data to program into memory mode register 3 for chip select 2 for frequency set 1"
hexmask.long.byte 0x38 8.--15. 1. "PI_MR2_DATA_F1_2,Data to program into memory mode register 2 for chip select 2 for frequency set 1"
newline
hexmask.long.byte 0x38 0.--7. 1. "PI_MR1_DATA_F1_2,Data to program into memory mode register 1 for chip select 2 for frequency set 1"
line.long 0x3C "DDRSS_PI_290,"
hexmask.long.byte 0x3C 24.--31. 1. "PI_MR23_DATA_F1_2,Data to program into memory mode register 23 for chip select 2 for frequency set 1"
hexmask.long.byte 0x3C 16.--23. 1. "PI_MR22_DATA_F1_2,Data to program into memory mode register 22 for chip select 2 for frequency set 1"
hexmask.long.byte 0x3C 8.--15. 1. "PI_MR14_DATA_F1_2,Data to program into memory mode register 14 for chip select 2 for frequency set 1"
newline
hexmask.long.byte 0x3C 0.--7. 1. "PI_MR12_DATA_F1_2,Data to program into memory mode register 12 for chip select 2 for frequency set 1"
line.long 0x40 "DDRSS_PI_291,"
hexmask.long.byte 0x40 24.--31. 1. "PI_MR11_DATA_F2_2,Data to program into memory mode register 11 for chip select 2 for frequency set 2"
hexmask.long.byte 0x40 16.--23. 1. "PI_MR3_DATA_F2_2,Data to program into memory mode register 3 for chip select 2 for frequency set 2"
hexmask.long.byte 0x40 8.--15. 1. "PI_MR2_DATA_F2_2,Data to program into memory mode register 2 for chip select 2 for frequency set 2"
newline
hexmask.long.byte 0x40 0.--7. 1. "PI_MR1_DATA_F2_2,Data to program into memory mode register 1 for chip select 2 for frequency set 2"
line.long 0x44 "DDRSS_PI_292,"
hexmask.long.byte 0x44 24.--31. 1. "PI_MR23_DATA_F2_2,Data to program into memory mode register 23 for chip select 2 for frequency set 2"
hexmask.long.byte 0x44 16.--23. 1. "PI_MR22_DATA_F2_2,Data to program into memory mode register 22 for chip select 2 for frequency set 2"
hexmask.long.byte 0x44 8.--15. 1. "PI_MR14_DATA_F2_2,Data to program into memory mode register 14 for chip select 2 for frequency set 2"
newline
hexmask.long.byte 0x44 0.--7. 1. "PI_MR12_DATA_F2_2,Data to program into memory mode register 12 for chip select 2 for frequency set 2"
line.long 0x48 "DDRSS_PI_293,"
hexmask.long.byte 0x48 24.--31. 1. "PI_MR11_DATA_F0_3,Data to program into memory mode register 11 for chip select 3 for frequency set 0"
hexmask.long.byte 0x48 16.--23. 1. "PI_MR3_DATA_F0_3,Data to program into memory mode register 3 for chip select 3 for frequency set 0"
hexmask.long.byte 0x48 8.--15. 1. "PI_MR2_DATA_F0_3,Data to program into memory mode register 2 for chip select 3 for frequency set 0"
newline
hexmask.long.byte 0x48 0.--7. 1. "PI_MR1_DATA_F0_3,Data to program into memory mode register 1 for chip select 3 for frequency set 0"
line.long 0x4C "DDRSS_PI_294,"
hexmask.long.byte 0x4C 24.--31. 1. "PI_MR23_DATA_F0_3,Data to program into memory mode register 23 for chip select 3 for frequency set 0"
hexmask.long.byte 0x4C 16.--23. 1. "PI_MR22_DATA_F0_3,Data to program into memory mode register 22 for chip select 3 for frequency set 0"
hexmask.long.byte 0x4C 8.--15. 1. "PI_MR14_DATA_F0_3,Data to program into memory mode register 14 for chip select 3 for frequency set 0"
newline
hexmask.long.byte 0x4C 0.--7. 1. "PI_MR12_DATA_F0_3,Data to program into memory mode register 12 for chip select 3 for frequency set 0"
line.long 0x50 "DDRSS_PI_295,"
hexmask.long.byte 0x50 24.--31. 1. "PI_MR11_DATA_F1_3,Data to program into memory mode register 11 for chip select 3 for frequency set 1"
hexmask.long.byte 0x50 16.--23. 1. "PI_MR3_DATA_F1_3,Data to program into memory mode register 3 for chip select 3 for frequency set 1"
hexmask.long.byte 0x50 8.--15. 1. "PI_MR2_DATA_F1_3,Data to program into memory mode register 2 for chip select 3 for frequency set 1"
newline
hexmask.long.byte 0x50 0.--7. 1. "PI_MR1_DATA_F1_3,Data to program into memory mode register 1 for chip select 3 for frequency set 1"
line.long 0x54 "DDRSS_PI_296,"
hexmask.long.byte 0x54 24.--31. 1. "PI_MR23_DATA_F1_3,Data to program into memory mode register 23 for chip select 3 for frequency set 1"
hexmask.long.byte 0x54 16.--23. 1. "PI_MR22_DATA_F1_3,Data to program into memory mode register 22 for chip select 3 for frequency set 1"
hexmask.long.byte 0x54 8.--15. 1. "PI_MR14_DATA_F1_3,Data to program into memory mode register 14 for chip select 3 for frequency set 1"
newline
hexmask.long.byte 0x54 0.--7. 1. "PI_MR12_DATA_F1_3,Data to program into memory mode register 12 for chip select 3 for frequency set 1"
line.long 0x58 "DDRSS_PI_297,"
hexmask.long.byte 0x58 24.--31. 1. "PI_MR11_DATA_F2_3,Data to program into memory mode register 11 for chip select 3 for frequency set 2"
hexmask.long.byte 0x58 16.--23. 1. "PI_MR3_DATA_F2_3,Data to program into memory mode register 3 for chip select 3 for frequency set 2"
hexmask.long.byte 0x58 8.--15. 1. "PI_MR2_DATA_F2_3,Data to program into memory mode register 2 for chip select 3 for frequency set 2"
newline
hexmask.long.byte 0x58 0.--7. 1. "PI_MR1_DATA_F2_3,Data to program into memory mode register 1 for chip select 3 for frequency set 2"
line.long 0x5C "DDRSS_PI_298,"
hexmask.long.byte 0x5C 24.--31. 1. "PI_MR23_DATA_F2_3,Data to program into memory mode register 23 for chip select 3 for frequency set 2"
hexmask.long.byte 0x5C 16.--23. 1. "PI_MR22_DATA_F2_3,Data to program into memory mode register 22 for chip select 3 for frequency set 2"
hexmask.long.byte 0x5C 8.--15. 1. "PI_MR14_DATA_F2_3,Data to program into memory mode register 14 for chip select 3 for frequency set 2"
newline
hexmask.long.byte 0x5C 0.--7. 1. "PI_MR12_DATA_F2_3,Data to program into memory mode register 12 for chip select 3 for frequency set 2"
line.long 0x60 "DDRSS_PI_299,"
hexmask.long.word 0x60 0.--10. 1. "PI_PARITY_ERROR_REGIF,Inject parity error to regisster interface signals for PI"
repeat 2. (list 273. 274. )(list 0x00 0x04 )
group.long ($2+0x2444)++0x03
line.long 0x00 "DDRSS_PI_$1,"
hexmask.long.word 0x00 16.--31. 1. "PI_DQS_OSC_BASE_VALUE_1_0,Base value for comparison of oscillator measurement for device 1 of rank 0"
hexmask.long.word 0x00 0.--15. 1. "PI_DQS_OSC_BASE_VALUE_0_0,Base value for comparison of oscillator measurement for device 0 of rank 0"
repeat.end
repeat 2. (list 208. 209. )(list 0x00 0x04 )
group.long ($2+0x2340)++0x03
line.long 0x00 "DDRSS_PI_$1,"
bitfld.long 0x00 16.--21. "PI_TCKEHDQS_F1,The DRAM timing tCKEHDQS minimum delay from CKE high to strobe high impedance for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--9. 1. "PI_TFC_F0,The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 0"
repeat.end
repeat 2. (list 202. 203. )(list 0x00 0x04 )
group.long ($2+0x2328)++0x03
line.long 0x00 "DDRSS_PI_$1,"
hexmask.long.byte 0x00 24.--31. 1. "PI_TMRWCKEL_F1,Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 1"
bitfld.long 0x00 16.--20. "PI_TXP_F1,CKE assert to next valid command delay for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--11. "PI_TDFI_CALVL_STROBE_F1,Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--4. "PI_TCKELCK_F0,Valid Clock Requirement after CKE deassert for frequency set 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (list 192. 193. )(list 0x00 0x04 )
group.long ($2+0x2300)++0x03
line.long 0x00 "DDRSS_PI_$1,"
bitfld.long 0x00 16.--20. "PI_TMRZ_F1,Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--13. 1. "PI_TCAENT_F0,Defines the DRAM tCAENT term in memory clocks for frequency set 0"
repeat.end
repeat 2. (list 183. 184. )(list 0x00 0x04 )
group.long ($2+0x22DC)++0x03
line.long 0x00 "DDRSS_PI_$1,"
bitfld.long 0x00 24.--25. "PI_RDLVL_RXCAL_EN_F1,Enable RX Offset calibration (PATTERN 14 15) for read training for frequency set 1" "0,1,2,3"
bitfld.long 0x00 16.--17. "PI_RDLVL_PAT0_EN_F1,Enable PATTERN-0 for read training for frequency set 1" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "PI_RDLVL_MULTI_EN_F0,Enable Multi-pattern (from PI_RDLVL_PATTERN_START total PI_RDLVL_PATTERN_NUM) for read training for frequency set 0" "0,1,2,3"
bitfld.long 0x00 0.--1. "PI_RDLVL_DFE_EN_F0,Enable DFE (PATTERN 8 9) for read training for frequency set 0" "0,1,2,3"
repeat.end
repeat 2. (list 164. 165. )(list 0x00 0x04 )
group.long ($2+0x2290)++0x03
line.long 0x00 "DDRSS_PI_$1,"
hexmask.long.byte 0x00 0.--7. 1. "PI_TDELAY_RDWR_2_BUS_IDLE_F0,The delay from read or write to bus idle for frequency set 0"
repeat.end
repeat 8. (list 126. 127. 128. 129. 130. 131. 132. 133. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x21F8)++0x03
line.long 0x00 "DDRSS_PI_$1,"
hexmask.long 0x00 0.--29. 1. "PI_BIST_STAGE_0,Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4"
repeat.end
repeat 4. (list 121. 122. 123. 124. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x21E4)++0x03
line.long 0x00 "DDRSS_PI_$1,"
repeat.end
repeat 2. (list 98. 99. )(list 0x00 0x04 )
group.long ($2+0x2188)++0x03
line.long 0x00 "DDRSS_PI_$1,"
repeat.end
repeat 4. (list 86. 87. 88. 89. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x2158)++0x03
line.long 0x00 "DDRSS_PI_$1,"
repeat.end
repeat 4. (list 82. 83. 84. 85. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x2148)++0x03
line.long 0x00 "DDRSS_PI_$1,"
repeat.end
repeat 10. (list 74. 75. 76. 77. 78. 155. 156. 157. 158. 258. )(list 0x00 0x04 0x08 0x0C 0x10 0x144 0x148 0x14C 0x150 0x2E0 )
hgroup.long ($2+0x2128)++0x03
hide.long 0x00 "DDRSS_PI_$1,"
repeat.end
repeat 3. (list 21. 22. 23. )(list 0x00 0x04 0x08 )
group.long ($2+0x2054)++0x03
line.long 0x00 "DDRSS_PI_$1,"
bitfld.long 0x00 24. "PI_SWLVL_WR_SLICE_1,SW leveling write command in WDQ training" "0,1"
rbitfld.long 0x00 16.--17. "PI_SW_WDQLVL_RESP_0,Leveling response for data slice 0" "0,1,2,3"
newline
bitfld.long 0x00 8. "PI_SWLVL_VREF_UPDATE_SLICE_0,SW leveling vref update command in WDQ training" "0,1"
bitfld.long 0x00 0. "PI_SWLVL_RD_SLICE_0,SW leveling read command in WDQ training" "0,1"
repeat.end
repeat 2. (list 1. 2. )(list 0x00 0x04 )
rgroup.long ($2+0x2004)++0x03
line.long 0x00 "DDRSS_PI_$1,"
repeat.end
tree.end
tree.end
tree "PLL0_CFG"
tree "PLL0_CFG"
base ad:0x680000
rgroup.long 0x00++0x03
line.long 0x00 "PLL0_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "PLL0_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x10++0x07
line.long 0x00 "PLL0_LOCKKEY0,- PLL0 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL0_LOCKKEY1,- PLL0 Lock Key 1 RegisterAddr"
group.long 0x20++0x07
line.long 0x00 "PLL0_CTRL,- PLL0 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL0_STAT,- PLL0 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x30++0x0B
line.long 0x00 "PLL0_FREQ_CTRL0,- PLL0 Frequency Control 0 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL0_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL0_DIV_CTRL,- PLL0 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x40++0x07
line.long 0x00 "PLL0_SS_CTRL,PLL_SS_CTRL register for pll0"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL0_SS_SPREAD,PLL_SS_SPREAD register for pll0"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x80++0x23
line.long 0x00 "PLL0_HSDIV_CTRL0,HSDIV_CTRL0 register for pll0"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL0_HSDIV_CTRL1,HSDIV_CTRL1 register for pll0"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL0_HSDIV_CTRL2,HSDIV_CTRL2 register for pll0"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL0_HSDIV_CTRL3,HSDIV_CTRL3 register for pll0"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x10 "PLL0_HSDIV_CTRL4,HSDIV_CTRL4 register for pll0"
bitfld.long 0x10 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x14 "PLL0_HSDIV_CTRL5,HSDIV_CTRL5 register for pll0"
bitfld.long 0x14 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x18 "PLL0_HSDIV_CTRL6,HSDIV_CTRL6 register for pll0"
bitfld.long 0x18 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x1C "PLL0_HSDIV_CTRL7,HSDIV_CTRL7 register for pll0"
bitfld.long 0x1C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x20 "PLL0_HSDIV_CTRL8,HSDIV_CTRL8 register for pll0"
bitfld.long 0x20 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x1000++0x03
line.long 0x00 "PLL1_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1008++0x03
line.long 0x00 "PLL1_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x1010++0x07
line.long 0x00 "PLL1_LOCKKEY0,- PLL1 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL1_LOCKKEY1,- PLL1 Lock Key 1 RegisterAddr"
group.long 0x1020++0x07
line.long 0x00 "PLL1_CTRL,- PLL1 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL1_STAT,- PLL1 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x1030++0x0B
line.long 0x00 "PLL1_FREQ_CTRL0,- PLL1 Frequency Control 1 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL1_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL1_DIV_CTRL,- PLL1 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x1040++0x07
line.long 0x00 "PLL1_SS_CTRL,PLL_SS_CTRL register for pll1"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL1_SS_SPREAD,PLL_SS_SPREAD register for pll1"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1080++0x23
line.long 0x00 "PLL1_HSDIV_CTRL0,HSDIV_CTRL0 register for pll1"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL1_HSDIV_CTRL1,HSDIV_CTRL1 register for pll1"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL1_HSDIV_CTRL2,HSDIV_CTRL2 register for pll1"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL1_HSDIV_CTRL3,HSDIV_CTRL3 register for pll1"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x10 "PLL1_HSDIV_CTRL4,HSDIV_CTRL4 register for pll1"
bitfld.long 0x10 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x14 "PLL1_HSDIV_CTRL5,HSDIV_CTRL5 register for pll1"
bitfld.long 0x14 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x18 "PLL1_HSDIV_CTRL6,HSDIV_CTRL6 register for pll1"
bitfld.long 0x18 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x1C "PLL1_HSDIV_CTRL7,HSDIV_CTRL7 register for pll1"
bitfld.long 0x1C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x20 "PLL1_HSDIV_CTRL8,HSDIV_CTRL8 register for pll1"
bitfld.long 0x20 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x2000++0x03
line.long 0x00 "PLL2_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x2008++0x03
line.long 0x00 "PLL2_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x2010++0x07
line.long 0x00 "PLL2_LOCKKEY0,- PLL2 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL2_LOCKKEY1,- PLL2 Lock Key 1 RegisterAddr"
group.long 0x2020++0x07
line.long 0x00 "PLL2_CTRL,- PLL2 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL2_STAT,- PLL2 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x2030++0x0B
line.long 0x00 "PLL2_FREQ_CTRL0,- PLL2 Frequency Control 2 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL2_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL2_DIV_CTRL,- PLL2 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x2040++0x07
line.long 0x00 "PLL2_SS_CTRL,PLL_SS_CTRL register for pll2"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL2_SS_SPREAD,PLL_SS_SPREAD register for pll2"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2080++0x1F
line.long 0x00 "PLL2_HSDIV_CTRL0,HSDIV_CTRL0 register for pll2"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL2_HSDIV_CTRL1,HSDIV_CTRL1 register for pll2"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL2_HSDIV_CTRL2,HSDIV_CTRL2 register for pll2"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL2_HSDIV_CTRL3,HSDIV_CTRL3 register for pll2"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x10 "PLL2_HSDIV_CTRL4,HSDIV_CTRL4 register for pll2"
bitfld.long 0x10 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x14 "PLL2_HSDIV_CTRL5,HSDIV_CTRL5 register for pll2"
bitfld.long 0x14 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x18 "PLL2_HSDIV_CTRL6,HSDIV_CTRL6 register for pll2"
bitfld.long 0x18 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x1C "PLL2_HSDIV_CTRL7,HSDIV_CTRL7 register for pll2"
bitfld.long 0x1C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x3000++0x03
line.long 0x00 "PLL3_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3008++0x03
line.long 0x00 "PLL3_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x3010++0x07
line.long 0x00 "PLL3_LOCKKEY0,- PLL3 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL3_LOCKKEY1,- PLL3 Lock Key 1 RegisterAddr"
group.long 0x3020++0x07
line.long 0x00 "PLL3_CTRL,- PLL3 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL3_STAT,- PLL3 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x3030++0x0B
line.long 0x00 "PLL3_FREQ_CTRL0,- PLL3 Frequency Control 3 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL3_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL3_DIV_CTRL,- PLL3 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x3040++0x07
line.long 0x00 "PLL3_SS_CTRL,PLL_SS_CTRL register for pll3"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL3_SS_SPREAD,PLL_SS_SPREAD register for pll3"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3080++0x13
line.long 0x00 "PLL3_HSDIV_CTRL0,HSDIV_CTRL0 register for pll3"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL3_HSDIV_CTRL1,HSDIV_CTRL1 register for pll3"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL3_HSDIV_CTRL2,HSDIV_CTRL2 register for pll3"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL3_HSDIV_CTRL3,HSDIV_CTRL3 register for pll3"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x10 "PLL3_HSDIV_CTRL4,HSDIV_CTRL4 register for pll3"
bitfld.long 0x10 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x4000++0x03
line.long 0x00 "PLL4_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x4008++0x03
line.long 0x00 "PLL4_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x4010++0x07
line.long 0x00 "PLL4_LOCKKEY0,- PLL4 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL4_LOCKKEY1,- PLL4 Lock Key 1 RegisterAddr"
group.long 0x4020++0x07
line.long 0x00 "PLL4_CTRL,- PLL4 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL4_STAT,- PLL4 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x4030++0x0B
line.long 0x00 "PLL4_FREQ_CTRL0,- PLL4 Frequency Control 4 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL4_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL4_DIV_CTRL,- PLL4 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x4040++0x07
line.long 0x00 "PLL4_SS_CTRL,PLL_SS_CTRL register for pll4"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL4_SS_SPREAD,PLL_SS_SPREAD register for pll4"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4080++0x0F
line.long 0x00 "PLL4_HSDIV_CTRL0,HSDIV_CTRL0 register for pll4"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL4_HSDIV_CTRL1,HSDIV_CTRL1 register for pll4"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL4_HSDIV_CTRL2,HSDIV_CTRL2 register for pll4"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL4_HSDIV_CTRL3,HSDIV_CTRL3 register for pll4"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x5000++0x03
line.long 0x00 "PLL5_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5008++0x03
line.long 0x00 "PLL5_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x5010++0x07
line.long 0x00 "PLL5_LOCKKEY0,- PLL5 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL5_LOCKKEY1,- PLL5 Lock Key 1 RegisterAddr"
group.long 0x5020++0x07
line.long 0x00 "PLL5_CTRL,- PLL5 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL5_STAT,- PLL5 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x5030++0x0B
line.long 0x00 "PLL5_FREQ_CTRL0,- PLL5 Frequency Control 5 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL5_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL5_DIV_CTRL,- PLL5 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x5040++0x07
line.long 0x00 "PLL5_SS_CTRL,PLL_SS_CTRL register for pll5"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL5_SS_SPREAD,PLL_SS_SPREAD register for pll5"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x5080++0x0F
line.long 0x00 "PLL5_HSDIV_CTRL0,HSDIV_CTRL0 register for pll5"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL5_HSDIV_CTRL1,HSDIV_CTRL1 register for pll5"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL5_HSDIV_CTRL2,HSDIV_CTRL2 register for pll5"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL5_HSDIV_CTRL3,HSDIV_CTRL3 register for pll5"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x6000++0x03
line.long 0x00 "PLL6_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x6008++0x03
line.long 0x00 "PLL6_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x6010++0x07
line.long 0x00 "PLL6_LOCKKEY0,- PLL6 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL6_LOCKKEY1,- PLL6 Lock Key 1 RegisterAddr"
group.long 0x6020++0x07
line.long 0x00 "PLL6_CTRL,- PLL6 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL6_STAT,- PLL6 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x6030++0x0B
line.long 0x00 "PLL6_FREQ_CTRL0,- PLL6 Frequency Control 6 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL6_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL6_DIV_CTRL,- PLL6 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x6040++0x07
line.long 0x00 "PLL6_SS_CTRL,PLL_SS_CTRL register for pll6"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL6_SS_SPREAD,PLL_SS_SPREAD register for pll6"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6080++0x03
line.long 0x00 "PLL6_HSDIV_CTRL0,HSDIV_CTRL0 register for pll6"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x7000++0x03
line.long 0x00 "PLL7_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x7008++0x03
line.long 0x00 "PLL7_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x7010++0x07
line.long 0x00 "PLL7_LOCKKEY0,- PLL7 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL7_LOCKKEY1,- PLL7 Lock Key 1 RegisterAddr"
group.long 0x7020++0x07
line.long 0x00 "PLL7_CTRL,- PLL7 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL7_STAT,- PLL7 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x7030++0x0B
line.long 0x00 "PLL7_FREQ_CTRL0,- PLL7 Frequency Control 7 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL7_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL7_DIV_CTRL,- PLL7 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x7040++0x07
line.long 0x00 "PLL7_SS_CTRL,PLL_SS_CTRL register for pll7"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL7_SS_SPREAD,PLL_SS_SPREAD register for pll7"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x7080++0x03
line.long 0x00 "PLL7_HSDIV_CTRL0,HSDIV_CTRL0 register for pll7"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x8000++0x03
line.long 0x00 "PLL8_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x8008++0x03
line.long 0x00 "PLL8_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x8010++0x07
line.long 0x00 "PLL8_LOCKKEY0,- PLL8 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL8_LOCKKEY1,- PLL8 Lock Key 1 RegisterAddr"
group.long 0x8020++0x07
line.long 0x00 "PLL8_CTRL,- PLL8 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL8_STAT,- PLL8 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x8030++0x0B
line.long 0x00 "PLL8_FREQ_CTRL0,- PLL8 Frequency Control 8 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL8_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL8_DIV_CTRL,- PLL8 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x8040++0x07
line.long 0x00 "PLL8_SS_CTRL,PLL_SS_CTRL register for pll8"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL8_SS_SPREAD,PLL_SS_SPREAD register for pll8"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8080++0x03
line.long 0x00 "PLL8_HSDIV_CTRL0,HSDIV_CTRL0 register for pll8"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x9000++0x03
line.long 0x00 "PLL9_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x9008++0x03
line.long 0x00 "PLL9_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x9010++0x07
line.long 0x00 "PLL9_LOCKKEY0,- PLL9 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition9 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL9_LOCKKEY1,- PLL9 Lock Key 1 RegisterAddr"
group.long 0x9020++0x07
line.long 0x00 "PLL9_CTRL,- PLL9 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
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bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL9_STAT,- PLL9 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x9030++0x0B
line.long 0x00 "PLL9_FREQ_CTRL0,- PLL9 Frequency Control 9 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported,0x010=Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by..,0xFFF=Not supported"
line.long 0x04 "PLL9_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL9_DIV_CTRL,- PLL9 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
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bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x9040++0x07
line.long 0x00 "PLL9_SS_CTRL,PLL_SS_CTRL register for pll9"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
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bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
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bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL9_SS_SPREAD,PLL_SS_SPREAD register for pll9"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x9080++0x03
line.long 0x00 "PLL9_HSDIV_CTRL0,HSDIV_CTRL0 register for pll9"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
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bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0xC000++0x03
line.long 0x00 "PLL12_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC008++0x03
line.long 0x00 "PLL12_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
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bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0xC010++0x07
line.long 0x00 "PLL12_LOCKKEY0,- PLL12 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL12_LOCKKEY1,- PLL12 Lock Key 1 RegisterAddr"
group.long 0xC020++0x07
line.long 0x00 "PLL12_CTRL,- PLL12 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
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bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
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bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
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bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL12_STAT,- PLL12 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0xC030++0x0B
line.long 0x00 "PLL12_FREQ_CTRL0,- PLL12 Frequency Control 12 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL12_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL12_DIV_CTRL,- PLL12 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0xC040++0x07
line.long 0x00 "PLL12_SS_CTRL,PLL_SS_CTRL register for pll12"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
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bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL12_SS_SPREAD,PLL_SS_SPREAD register for pll12"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC060++0x07
line.long 0x00 "PLL12_CAL_CTRL,- PLL12 Calibration Control Register"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input" "0,1"
bitfld.long 0x00 20. "FAST_CAL,Fast calibration" "0,1"
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bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter.Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "CAL_BYP,Calibration" "0,1"
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hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration.When cal_byp is 1'b1 this is the override value for calibration"
line.long 0x04 "PLL12_CAL_STAT,- PLL12 Calibration Status Register"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0.If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]"
group.long 0xC080++0x03
line.long 0x00 "PLL12_HSDIV_CTRL0,HSDIV_CTRL0 register for pll12"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
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bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0xD000++0x03
line.long 0x00 "PLL13_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD008++0x03
line.long 0x00 "PLL13_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0xD010++0x07
line.long 0x00 "PLL13_LOCKKEY0,- PLL13 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition13 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL13_LOCKKEY1,- PLL13 Lock Key 1 RegisterAddr"
group.long 0xD020++0x07
line.long 0x00 "PLL13_CTRL,- PLL13 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL13_STAT,- PLL13 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0xD030++0x0B
line.long 0x00 "PLL13_FREQ_CTRL0,- PLL13 Frequency Control 13 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported,0x010=Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by..,0xFFF=Not supported"
line.long 0x04 "PLL13_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL13_DIV_CTRL,- PLL13 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0xD040++0x07
line.long 0x00 "PLL13_SS_CTRL,PLL_SS_CTRL register for pll13"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL13_SS_SPREAD,PLL_SS_SPREAD register for pll13"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xD080++0x0F
line.long 0x00 "PLL13_HSDIV_CTRL0,HSDIV_CTRL0 register for pll13"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL13_HSDIV_CTRL1,HSDIV_CTRL1 register for pll13"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL13_HSDIV_CTRL2,HSDIV_CTRL2 register for pll13"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL13_HSDIV_CTRL3,HSDIV_CTRL3 register for pll13"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0xE000++0x03
line.long 0x00 "PLL14_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE008++0x03
line.long 0x00 "PLL14_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0xE010++0x07
line.long 0x00 "PLL14_LOCKKEY0,- PLL14 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition14 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL14_LOCKKEY1,- PLL14 Lock Key 1 RegisterAddr"
group.long 0xE020++0x07
line.long 0x00 "PLL14_CTRL,- PLL14 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL14_STAT,- PLL14 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0xE030++0x0B
line.long 0x00 "PLL14_FREQ_CTRL0,- PLL14 Frequency Control 14 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL14_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL14_DIV_CTRL,- PLL14 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0xE040++0x07
line.long 0x00 "PLL14_SS_CTRL,PLL_SS_CTRL register for pll14"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL14_SS_SPREAD,PLL_SS_SPREAD register for pll14"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xE080++0x07
line.long 0x00 "PLL14_HSDIV_CTRL0,HSDIV_CTRL0 register for pll14"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL14_HSDIV_CTRL1,HSDIV_CTRL1 register for pll14"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0xF000++0x03
line.long 0x00 "PLL15_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF008++0x03
line.long 0x00 "PLL15_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0xF010++0x07
line.long 0x00 "PLL15_LOCKKEY0,- PLL15 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition15 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL15_LOCKKEY1,- PLL15 Lock Key 1 RegisterAddr"
group.long 0xF020++0x07
line.long 0x00 "PLL15_CTRL,- PLL15 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL15_STAT,- PLL15 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0xF030++0x0B
line.long 0x00 "PLL15_FREQ_CTRL0,- PLL15 Frequency Control 15 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL15_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL15_DIV_CTRL,- PLL15 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0xF040++0x07
line.long 0x00 "PLL15_SS_CTRL,PLL_SS_CTRL register for pll15"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL15_SS_SPREAD,PLL_SS_SPREAD register for pll15"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF080++0x0F
line.long 0x00 "PLL15_HSDIV_CTRL0,HSDIV_CTRL0 register for pll15"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL15_HSDIV_CTRL1,HSDIV_CTRL1 register for pll15"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x08 "PLL15_HSDIV_CTRL2,HSDIV_CTRL2 register for pll15"
bitfld.long 0x08 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x08 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x08 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x0C "PLL15_HSDIV_CTRL3,HSDIV_CTRL3 register for pll15"
bitfld.long 0x0C 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x0C 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x0C 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x0C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x10000++0x03
line.long 0x00 "PLL16_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10008++0x03
line.long 0x00 "PLL16_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x10010++0x07
line.long 0x00 "PLL16_LOCKKEY0,- PLL16 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition16 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL16_LOCKKEY1,- PLL16 Lock Key 1 RegisterAddr"
group.long 0x10020++0x07
line.long 0x00 "PLL16_CTRL,- PLL16 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL16_STAT,- PLL16 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x10030++0x0B
line.long 0x00 "PLL16_FREQ_CTRL0,- PLL16 Frequency Control 16 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL16_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL16_DIV_CTRL,- PLL16 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x10040++0x07
line.long 0x00 "PLL16_SS_CTRL,PLL_SS_CTRL register for pll16"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL16_SS_SPREAD,PLL_SS_SPREAD register for pll16"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10080++0x07
line.long 0x00 "PLL16_HSDIV_CTRL0,HSDIV_CTRL0 register for pll16"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL16_HSDIV_CTRL1,HSDIV_CTRL1 register for pll16"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x11000++0x03
line.long 0x00 "PLL17_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x11008++0x03
line.long 0x00 "PLL17_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x11010++0x07
line.long 0x00 "PLL17_LOCKKEY0,- PLL17 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition17 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL17_LOCKKEY1,- PLL17 Lock Key 1 RegisterAddr"
group.long 0x11020++0x07
line.long 0x00 "PLL17_CTRL,- PLL17 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL17_STAT,- PLL17 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x11030++0x0B
line.long 0x00 "PLL17_FREQ_CTRL0,- PLL17 Frequency Control 17 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL17_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL17_DIV_CTRL,- PLL17 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x11040++0x07
line.long 0x00 "PLL17_SS_CTRL,PLL_SS_CTRL register for pll17"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL17_SS_SPREAD,PLL_SS_SPREAD register for pll17"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x11080++0x07
line.long 0x00 "PLL17_HSDIV_CTRL0,HSDIV_CTRL0 register for pll17"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL17_HSDIV_CTRL1,HSDIV_CTRL1 register for pll17"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x12000++0x03
line.long 0x00 "PLL18_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x12008++0x03
line.long 0x00 "PLL18_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x12010++0x07
line.long 0x00 "PLL18_LOCKKEY0,- PLL18 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition18 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL18_LOCKKEY1,- PLL18 Lock Key 1 RegisterAddr"
group.long 0x12020++0x07
line.long 0x00 "PLL18_CTRL,- PLL18 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
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bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
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bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL18_STAT,- PLL18 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x12030++0x0B
line.long 0x00 "PLL18_FREQ_CTRL0,- PLL18 Frequency Control 18 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL18_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL18_DIV_CTRL,- PLL18 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x12040++0x07
line.long 0x00 "PLL18_SS_CTRL,PLL_SS_CTRL register for pll18"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL18_SS_SPREAD,PLL_SS_SPREAD register for pll18"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x12080++0x07
line.long 0x00 "PLL18_HSDIV_CTRL0,HSDIV_CTRL0 register for pll18"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL18_HSDIV_CTRL1,HSDIV_CTRL1 register for pll18"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x13000++0x03
line.long 0x00 "PLL19_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x13008++0x03
line.long 0x00 "PLL19_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x13010++0x07
line.long 0x00 "PLL19_LOCKKEY0,- PLL19 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition19 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL19_LOCKKEY1,- PLL19 Lock Key 1 RegisterAddr"
group.long 0x13020++0x07
line.long 0x00 "PLL19_CTRL,- PLL19 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL19_STAT,- PLL19 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x13030++0x0B
line.long 0x00 "PLL19_FREQ_CTRL0,- PLL19 Frequency Control 19 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL19_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL19_DIV_CTRL,- PLL19 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x13040++0x07
line.long 0x00 "PLL19_SS_CTRL,PLL_SS_CTRL register for pll19"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL19_SS_SPREAD,PLL_SS_SPREAD register for pll19"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x13080++0x07
line.long 0x00 "PLL19_HSDIV_CTRL0,HSDIV_CTRL0 register for pll19"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL19_HSDIV_CTRL1,HSDIV_CTRL1 register for pll19"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x14000++0x03
line.long 0x00 "PLL20_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14008++0x03
line.long 0x00 "PLL20_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x14010++0x07
line.long 0x00 "PLL20_LOCKKEY0,- PLL20 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition20 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL20_LOCKKEY1,- PLL20 Lock Key 1 RegisterAddr"
group.long 0x14020++0x07
line.long 0x00 "PLL20_CTRL,- PLL20 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL20_STAT,- PLL20 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x14030++0x0B
line.long 0x00 "PLL20_FREQ_CTRL0,- PLL20 Frequency Control 20 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL20_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL20_DIV_CTRL,- PLL20 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x14040++0x07
line.long 0x00 "PLL20_SS_CTRL,PLL_SS_CTRL register for pll20"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL20_SS_SPREAD,PLL_SS_SPREAD register for pll20"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14080++0x07
line.long 0x00 "PLL20_HSDIV_CTRL0,HSDIV_CTRL0 register for pll20"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL20_HSDIV_CTRL1,HSDIV_CTRL1 register for pll20"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x15000++0x03
line.long 0x00 "PLL21_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x15008++0x03
line.long 0x00 "PLL21_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x15010++0x07
line.long 0x00 "PLL21_LOCKKEY0,- PLL21 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition21 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL21_LOCKKEY1,- PLL21 Lock Key 1 RegisterAddr"
group.long 0x15020++0x07
line.long 0x00 "PLL21_CTRL,- PLL21 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL21_STAT,- PLL21 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x15030++0x0B
line.long 0x00 "PLL21_FREQ_CTRL0,- PLL21 Frequency Control 21 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL21_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL21_DIV_CTRL,- PLL21 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x15040++0x07
line.long 0x00 "PLL21_SS_CTRL,PLL_SS_CTRL register for pll21"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL21_SS_SPREAD,PLL_SS_SPREAD register for pll21"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x15080++0x07
line.long 0x00 "PLL21_HSDIV_CTRL0,HSDIV_CTRL0 register for pll21"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL21_HSDIV_CTRL1,HSDIV_CTRL1 register for pll21"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x16000++0x03
line.long 0x00 "PLL22_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x16008++0x03
line.long 0x00 "PLL22_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x16010++0x07
line.long 0x00 "PLL22_LOCKKEY0,- PLL22 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition22 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL22_LOCKKEY1,- PLL22 Lock Key 1 RegisterAddr"
group.long 0x16020++0x07
line.long 0x00 "PLL22_CTRL,- PLL22 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL22_STAT,- PLL22 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x16030++0x0B
line.long 0x00 "PLL22_FREQ_CTRL0,- PLL22 Frequency Control 22 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL22_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL22_DIV_CTRL,- PLL22 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x16040++0x07
line.long 0x00 "PLL22_SS_CTRL,PLL_SS_CTRL register for pll22"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL22_SS_SPREAD,PLL_SS_SPREAD register for pll22"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x16080++0x07
line.long 0x00 "PLL22_HSDIV_CTRL0,HSDIV_CTRL0 register for pll22"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL22_HSDIV_CTRL1,HSDIV_CTRL1 register for pll22"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x17000++0x03
line.long 0x00 "PLL23_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x17008++0x03
line.long 0x00 "PLL23_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x17010++0x07
line.long 0x00 "PLL23_LOCKKEY0,- PLL23 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition23 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL23_LOCKKEY1,- PLL23 Lock Key 1 RegisterAddr"
group.long 0x17020++0x07
line.long 0x00 "PLL23_CTRL,- PLL23 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL23_STAT,- PLL23 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x17030++0x0B
line.long 0x00 "PLL23_FREQ_CTRL0,- PLL23 Frequency Control 23 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL23_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL23_DIV_CTRL,- PLL23 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x17040++0x07
line.long 0x00 "PLL23_SS_CTRL,PLL_SS_CTRL register for pll23"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL23_SS_SPREAD,PLL_SS_SPREAD register for pll23"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x17080++0x07
line.long 0x00 "PLL23_HSDIV_CTRL0,HSDIV_CTRL0 register for pll23"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL23_HSDIV_CTRL1,HSDIV_CTRL1 register for pll23"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x18000++0x03
line.long 0x00 "PLL24_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18008++0x03
line.long 0x00 "PLL24_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x18010++0x07
line.long 0x00 "PLL24_LOCKKEY0,- PLL24 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition24 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL24_LOCKKEY1,LOCK register - LOCKKEY1 component"
group.long 0x18020++0x07
line.long 0x00 "PLL24_PLL_CTRL,PLL_CTRL register for pll24"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL clock outputs,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
bitfld.long 0x00 4. "PD_EN,Power down.When set to 1 deskew PLL is powered down" "0,1"
newline
bitfld.long 0x00 0. "VCO_SEL,Select clock source for post" "0,1"
line.long 0x04 "PLL24_DSPLL_STAT,DSPLL_STAT register for pll24"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x18038++0x03
line.long 0x00 "PLL24_PLL_DIV_CTRL,PLL_DIV_CTRL register for pll24"
bitfld.long 0x00 12.--13. "FB_DIV,Feedback divide value:2'b00 - Divide by 4 2'b01 - Divide by 2 2'b10 - Divide by 1 2'b11 - Divide by 1" "0,1,2,3"
bitfld.long 0x00 8.--10. "POST_DIV,Post divide value:3'b000 - Divided by 1 3'b001 - Divided by 2 3'b010 - Divided by 4 3'b011- Divided by 8 3'b100 - Divided by 16 3'b101 - Divided by 32 3'b110 - Divided by 64 3'b111 - Divided by 128" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "REF_DIV,Reference divide value:2'b00 - Divide by 4 2'b01 - Divide by 2 2'b10 - Divide by 1 2'b11 - Divide by 1" "0,1,2,3"
group.long 0x18050++0x03
line.long 0x00 "PLL24_PLL_TEST_CTRL,PLL_TEST_CTRL register for pll24"
bitfld.long 0x00 7. "TEST_EN,Enable test mux" "0,1"
bitfld.long 0x00 4. "PD_CAL,Skew calibration power down" "0,1"
newline
bitfld.long 0x00 0. "TEST_SEL,Selects TESTOUT clock" "0,1"
group.long 0x18060++0x07
line.long 0x00 "PLL24_DSCAL_CTRL,DSCAL_CTRL register for pll24"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input" "0,1"
bitfld.long 0x00 27. "SPO_CAL_EN,Enable the SPO_CAL_CLKOUT when set" "0,1"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration" "0,1"
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter.Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration" "0,1"
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration.When cal_byp is 1'b1 this is the override value for calibration"
line.long 0x04 "PLL24_DSCAL_STAT,DSCAL_STAT register for pll24"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0.If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]"
group.long 0x18080++0x03
line.long 0x00 "PLL24_HSDIV_CTRL0,HSDIV_CTRL0 register for pll24"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
rgroup.long 0x19000++0x03
line.long 0x00 "PLL25_PID,Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x19008++0x03
line.long 0x00 "PLL25_CFG,PLL Configuration"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15.By definition HSDIV [4:0] are connected the PLL FOUTVCO output clock and HSDIV [15:5] are connected to the PLL FOUTPOSTDIV output clock"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are" "?,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table" "0,1"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are" "?,FractionalF PLL,De-Skew PLL,?..."
group.long 0x19010++0x07
line.long 0x00 "PLL25_LOCKKEY0,- PLL25 Lock Key 0 Register"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition25 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status.When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing" "0,1"
line.long 0x04 "PLL25_LOCKKEY1,- PLL25 Lock Key 1 RegisterAddr"
group.long 0x19020++0x07
line.long 0x00 "PLL25_CTRL,- PLL25 Control"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable.This controls the glitch-free bypass mux" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock.This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL" "0,1"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable.This is an asynchronous mux which can produce glitches on the output clocks during switching" "0,1"
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator.NOTE: Always program this bit to 0" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK" "0,1"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator" "0,1"
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function when DSM_EN =" "Fractional NC DAC is disabled,Fractional NC DAC is enabled"
line.long 0x04 "PLL25_STAT,- PLL25 Status"
bitfld.long 0x04 0. "LOCK,PLL lock status.Software should wait for lock to be asserted before clearing the PLL_CTRL[31] BYPASS_EN bit" "PLL is not locked,PLL is locked"
group.long 0x19030++0x0B
line.long 0x00 "PLL25_FREQ_CTRL0,- PLL25 Frequency Control 25 Register"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL multiplier (integer portion) In Integer mode values of16 - 3200 (dec) are supported" "0x00F=Not supported12'h010 - Divide by 16,0x011=Divide by 17 ...12'h140 - Divide by 320..,0xFFF=Not supported"
line.long 0x04 "PLL25_FREQ_CTRL1,- PLL0 Frequency Control 1 Register"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL multiplier (fractional portion)" "0x000001=.000000059605 (1/(2)),0x000002=.000000119209 (2/(2)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2))"
line.long 0x08 "PLL25_DIV_CTRL,- PLL25 Output Clock Divider Register"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider.Supports values of 1-7" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider.To ensure correct operation POST_DIV1 must always be programmed to a value equal to or greater that POST_DIV2" "Reserved,Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider.Supports values of 1-63" "Reserved,Divide by 1,Divide by 2...6'b111111 -..,?..."
group.long 0x19040++0x07
line.long 0x00 "PLL25_SS_CTRL,PLL_SS_CTRL register for pll25"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS" "0,1"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address.Indicates the maximum number of address bits used to access the external wave table"
newline
bitfld.long 0x00 15. "RESET,HSDIV reset.When set to 1 the SSM modulator is in reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock" "0,1"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLLn_CFG[8] SSM_WVTBL = 1 Field values (Others are" "0,1"
line.long 0x04 "PLL25_SS_SPREAD,PLL_SS_SPREAD register for pll25"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider.This divider sets the modulation frequency" "?,Divide by 1,Divide by 2,?..."
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth.The depth is spread*0.1%" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x19080++0x07
line.long 0x00 "PLL25_HSDIV_CTRL0,HSDIV_CTRL0 register for pll25"
bitfld.long 0x00 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
line.long 0x04 "PLL25_HSDIV_CTRL1,HSDIV_CTRL1 register for pll25"
bitfld.long 0x04 31. "RESET,HSDIV reset.When set to 1 HSDIV is in reset" "0,1"
bitfld.long 0x04 15. "CLKOUT_EN,CLKOUT1" "0,1"
newline
bitfld.long 0x04 8. "SYNC_DIS,Disable divider synchronization" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are0-127"
tree.end
tree.end
tree "PLLCTRL0"
tree "PLLCTRL0"
base ad:0x40D00000
rgroup.long 0x00++0x03
line.long 0x00 "PID,register"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "PLLCTL,PLL control register"
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD2,Reserved"
bitfld.long 0x00 9. "EXCLKSRC,Selects between using bypass clock or an external clock source" "0,1"
bitfld.long 0x00 8. "CLKMODE,Reference Clock Selection" "0,1"
bitfld.long 0x00 7. "PLLSELB,Selects PLL A versus PLL B" "0,1"
bitfld.long 0x00 6. "RSVD1,Reserved" "0,1"
bitfld.long 0x00 5. "PLLENSRC,PLLEN Mux Control Source" "0,1"
bitfld.long 0x00 4. "PLLDIS,Asserts DISABLE to PLL if Supported" "0,1"
bitfld.long 0x00 3. "PLLRST,Asserts RESET to PLL if Supported" "0,1"
bitfld.long 0x00 2. "RSVD,Reserved" "0,1"
newline
bitfld.long 0x00 1. "PLLPWRDN,Selects PLL Power Down for the PLL selected by PLLSELB" "0,1"
bitfld.long 0x00 0. "PLLEN,PLL Mode Enable" "0,1"
group.long 0x118++0x07
line.long 0x00 "PLLDIV1,PLL controller divider1 control register"
hexmask.long.word 0x00 16.--31. 1. "RSVD1,Reserved"
rbitfld.long 0x00 15. "DN,Divider Dn Enable" "0,1"
bitfld.long 0x00 14. "HALF_RATIO,Ratio is in half steps" "0,1"
bitfld.long 0x00 8.--13. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider)"
line.long 0x04 "PLLDIV2,PLL controller divider2 control register"
hexmask.long.word 0x04 16.--31. 1. "RSVD1,Reserved"
rbitfld.long 0x04 15. "DN,Divider Dn Enable" "0,1"
bitfld.long 0x04 14. "HALF_RATIO,Ratio is in half steps" "0,1"
bitfld.long 0x04 8.--13. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider)"
group.long 0x138++0x0F
line.long 0x00 "PLLCMD,PLL Controller command register"
hexmask.long 0x00 2.--31. 1. "RSVD,Reserved"
bitfld.long 0x00 1. "OSCPWRDN,iOscillator Power Down Command" "0,1"
bitfld.long 0x00 0. "GOSET,GO bit for SYSCLKx phase alignment" "0,1"
line.long 0x04 "PLLSTAT,PLL Controller status register"
hexmask.long 0x04 3.--31. 1. "RSVD,Reserved"
rbitfld.long 0x04 2. "STABLE,OSCIN Stable" "0,1"
rbitfld.long 0x04 1. "LOCK,PLL Core STATUS" "0,1"
rbitfld.long 0x04 0. "GOSTAT,Reflects the status of GO transition" "0,1"
line.long 0x08 "ALNCTL,PLL Controller clock align control register"
hexmask.long.word 0x08 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x08 1.--15. 1. "ALN,SYSCLKx needs to be aligned with other clocks selected in this register"
bitfld.long 0x08 0. "ALN1,SYSCLK1 needs to be aligned with other clocks selected in this register" "0,1"
line.long 0x0C "DCHANGE,PLLDIV ratio change register"
hexmask.long.word 0x0C 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x0C 1.--15. 1. "SYS,SYSCLKx divide ratio has been modified"
rbitfld.long 0x0C 0. "SYS1,SYSCLK1 divide ratio has been modified" "0,1"
tree.end
tree "WKUP_PLLCTRL0"
base ad:0x42010000
rgroup.long 0x00++0x03
line.long 0x00 "PID,register"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "PLLCTL,PLL control register"
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD2,Reserved"
bitfld.long 0x00 9. "EXCLKSRC,Selects between using bypass clock or an external clock source" "0,1"
bitfld.long 0x00 8. "CLKMODE,Reference Clock Selection" "0,1"
bitfld.long 0x00 7. "PLLSELB,Selects PLL A versus PLL B" "0,1"
bitfld.long 0x00 6. "RSVD1,Reserved" "0,1"
bitfld.long 0x00 5. "PLLENSRC,PLLEN Mux Control Source" "0,1"
bitfld.long 0x00 4. "PLLDIS,Asserts DISABLE to PLL if Supported" "0,1"
bitfld.long 0x00 3. "PLLRST,Asserts RESET to PLL if Supported" "0,1"
bitfld.long 0x00 2. "RSVD,Reserved" "0,1"
newline
bitfld.long 0x00 1. "PLLPWRDN,Selects PLL Power Down for the PLL selected by PLLSELB" "0,1"
bitfld.long 0x00 0. "PLLEN,PLL Mode Enable" "0,1"
group.long 0x118++0x07
line.long 0x00 "PLLDIV1,PLL controller divider1 control register"
hexmask.long.word 0x00 16.--31. 1. "RSVD1,Reserved"
rbitfld.long 0x00 15. "DN,Divider Dn Enable" "0,1"
bitfld.long 0x00 14. "HALF_RATIO,Ratio is in half steps" "0,1"
bitfld.long 0x00 8.--13. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider)"
line.long 0x04 "PLLDIV2,PLL controller divider2 control register"
hexmask.long.word 0x04 16.--31. 1. "RSVD1,Reserved"
rbitfld.long 0x04 15. "DN,Divider Dn Enable" "0,1"
bitfld.long 0x04 14. "HALF_RATIO,Ratio is in half steps" "0,1"
bitfld.long 0x04 8.--13. "RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 0.--7. 1. "RATIO,Divider Dn Ratio (SYSCLKn divider)"
group.long 0x138++0x0F
line.long 0x00 "PLLCMD,PLL Controller command register"
hexmask.long 0x00 2.--31. 1. "RSVD,Reserved"
bitfld.long 0x00 1. "OSCPWRDN,iOscillator Power Down Command" "0,1"
bitfld.long 0x00 0. "GOSET,GO bit for SYSCLKx phase alignment" "0,1"
line.long 0x04 "PLLSTAT,PLL Controller status register"
hexmask.long 0x04 3.--31. 1. "RSVD,Reserved"
rbitfld.long 0x04 2. "STABLE,OSCIN Stable" "0,1"
rbitfld.long 0x04 1. "LOCK,PLL Core STATUS" "0,1"
rbitfld.long 0x04 0. "GOSTAT,Reflects the status of GO transition" "0,1"
line.long 0x08 "ALNCTL,PLL Controller clock align control register"
hexmask.long.word 0x08 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x08 1.--15. 1. "ALN,SYSCLKx needs to be aligned with other clocks selected in this register"
bitfld.long 0x08 0. "ALN1,SYSCLK1 needs to be aligned with other clocks selected in this register" "0,1"
line.long 0x0C "DCHANGE,PLLDIV ratio change register"
hexmask.long.word 0x0C 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x0C 1.--15. 1. "SYS,SYSCLKx divide ratio has been modified"
rbitfld.long 0x0C 0. "SYS1,SYSCLK1 divide ratio has been modified" "0,1"
tree.end
tree.end
tree "PSC"
tree "PSC0"
base ad:0x400000
rgroup.long 0x00++0x03
line.long 0x00 "PSC0_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module"
bitfld.long 0x00 30.--31. "SCHEME,PSC0_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x0B
line.long 0x00 "PSC0_GBLCTL,This register contains global control to PSC"
hexmask.long.byte 0x00 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control"
line.long 0x04 "PSC0_GBLSTAT,This register shows the PSC global status"
hexmask.long.word 0x04 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits"
bitfld.long 0x04 0. "OVRIDE,PSC Override Status" "0,1"
line.long 0x08 "PSC0_INTEVAL,This register has no storage"
bitfld.long 0x08 19. "GOSET,GOSTAT Interrupt Set" "0,1"
bitfld.long 0x08 18. "EPCSET,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 17. "ERRSET,Combined Interrupt Set" "0,1"
bitfld.long 0x08 2. "EPCEV,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 1. "ERREV,Re_evaluate Error Interrupt" "0,1"
bitfld.long 0x08 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "PSC0_MERRPR_y,This register records pending error conditions for all modules"
group.long 0x50++0x03
line.long 0x00 "PSC0_MERRCR_y,This register has no storage"
rgroup.long 0x60++0x03
line.long 0x00 "PSC0_PERRPR,This register records pending error conditions for each power domain"
group.long 0x68++0x03
line.long 0x00 "PSC0_PERRCR,This register has no storage"
rgroup.long 0x70++0x03
line.long 0x00 "PSC0_EPCPR,This register records pending external power control conditions"
group.long 0x78++0x03
line.long 0x00 "PSC0_EPCCR,This register has no storage"
rgroup.long 0x100++0x0B
line.long 0x00 "PSC0_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor"
bitfld.long 0x00 24.--28. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "RAILCNT,Indicates the current rail counter value"
line.long 0x04 "PSC0_RAILCTL,This register is user programmable"
hexmask.long.byte 0x04 8.--15. 1. "RAILCTR1,Rail Counter Value 1"
hexmask.long.byte 0x04 0.--7. 1. "RAILCTR0,Rail Counter Value 0"
line.long 0x08 "PSC0_RAILSEL,User can use this register to select the counter value (PSC0_RAILCTL) for each power domain"
group.long 0x120++0x03
line.long 0x00 "PSC0_PTCMD,This is a pseudo-command register with no actual storage"
rgroup.long 0x128++0x03
line.long 0x00 "PSC0_PTSTAT,This is a status register"
rgroup.long 0x200++0x03
line.long 0x00 "PSC0_PDSTAT_y,This is a status register"
bitfld.long 0x00 11. "EMUIHB,Emulation Alters Domain State" "0,1"
bitfld.long 0x00 10. "PWRBAD,Power Bad error" "0,1"
bitfld.long 0x00 9. "PORDONE,POR Done Input Status" "0,1"
bitfld.long 0x00 8. "PORZ,PORz output actual status" "0,1"
bitfld.long 0x00 0.--4. "STATE,Current Power Domain State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300++0x03
line.long 0x00 "PSC0_PDCTL_y,This is a control register"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 29. "PWRSW,Power shorting Switch Control" "0,1"
bitfld.long 0x00 28. "ISO,Isolation Cell control" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "WAKECNT,RAM wake count delay value"
bitfld.long 0x00 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "EMUIHBIE,Emulation alters domain state" "0,1"
bitfld.long 0x00 8. "EPCGOOD,External Power Control Power Good Indication" "0,1"
bitfld.long 0x00 0. "NEXT,User_Desired Next Power Domain State" "0,1"
rgroup.long 0x400++0x03
line.long 0x00 "PSC0_PDCFG_y,This is a status register"
bitfld.long 0x00 3. "ICEPICK,Icepick support" "0,1"
bitfld.long 0x00 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1"
bitfld.long 0x00 0. "ALWAYSON,Always on power domain" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "PSC0_MDCFG_y,This is a constant register showing some PSC settings for easy debug"
bitfld.long 0x00 16.--20. "PWRDOM,Indicates which power domain this module belongs to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "AUTOONLY," "0,1"
bitfld.long 0x00 14. "RESETISO," "0,1"
bitfld.long 0x00 13. "NEXTLOCK," "0,1"
bitfld.long 0x00 12. "ASYNC,Async Lpsc" "0,1"
bitfld.long 0x00 11. "ICEPICK,IcePick support" "0,1"
bitfld.long 0x00 10. "PERMDIS,Permanently disable" "0,1"
bitfld.long 0x00 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1"
newline
bitfld.long 0x00 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7"
rgroup.long 0x800++0x03
line.long 0x00 "PSC0_MDSTAT_y,This register shows the status of each module"
bitfld.long 0x00 17. "EMUIHB,Emulation Alters Module State" "0,1"
bitfld.long 0x00 16. "EMURST,Emulation Alters Reset" "0,1"
bitfld.long 0x00 12. "MCKOUT,Actual modclk output to module" "0,1"
bitfld.long 0x00 11. "MRSTDONE,Module reset initialization done status" "0,1"
bitfld.long 0x00 10. "MRSTZ,Module reset actual status" "0,1"
bitfld.long 0x00 9. "LRSTDONE,Module local reset initialization done status" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset actual status" "0,1"
bitfld.long 0x00 0.--5. "STATE,These bits indicate the current module state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA00++0x03
line.long 0x00 "PSC0_MDCTL_y,This register provides specific control for the individual module"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 12. "RESETISO,Reset Isolation" "0,1"
bitfld.long 0x00 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1"
bitfld.long 0x00 10. "EMUIHBIE,Emulation Alters Module State" "0,1"
bitfld.long 0x00 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset control" "0,1"
bitfld.long 0x00 0.--4. "NEXT,Module Next State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "WKUP_PSC0"
base ad:0x42000000
rgroup.long 0x00++0x03
line.long 0x00 "WKUP_PSC0_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module"
bitfld.long 0x00 30.--31. "SCHEME,WKUP_PSC0_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x0B
line.long 0x00 "WKUP_PSC0_GBLCTL,This register contains global control to PSC"
hexmask.long.byte 0x00 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control"
line.long 0x04 "WKUP_PSC0_GBLSTAT,This register shows the PSC global status"
hexmask.long.word 0x04 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits"
bitfld.long 0x04 0. "OVRIDE,PSC Override Status" "0,1"
line.long 0x08 "WKUP_PSC0_INTEVAL,This register has no storage"
bitfld.long 0x08 19. "GOSET,GOSTAT Interrupt Set" "0,1"
bitfld.long 0x08 18. "EPCSET,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 17. "ERRSET,Combined Interrupt Set" "0,1"
bitfld.long 0x08 2. "EPCEV,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 1. "ERREV,Re_evaluate Error Interrupt" "0,1"
bitfld.long 0x08 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "WKUP_PSC0_MERRPR,This register records pending error conditions for all modules"
group.long 0x50++0x03
line.long 0x00 "WKUP_PSC0_MERRCR,This register has no storage"
rgroup.long 0x60++0x03
line.long 0x00 "WKUP_PSC0_PERRPR,This register records pending error conditions for each power domain"
group.long 0x68++0x03
line.long 0x00 "WKUP_PSC0_PERRCR,This register has no storage"
rgroup.long 0x70++0x03
line.long 0x00 "WKUP_PSC0_EPCPR,This register records pending external power control conditions"
group.long 0x78++0x03
line.long 0x00 "WKUP_PSC0_EPCCR,This register has no storage"
rgroup.long 0x100++0x0B
line.long 0x00 "WKUP_PSC0_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor"
bitfld.long 0x00 24.--28. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "RAILCNT,Indicates the current rail counter value"
line.long 0x04 "WKUP_PSC0_RAILCTL,This register is user programmable"
hexmask.long.byte 0x04 8.--15. 1. "RAILCTR1,Rail Counter Value 1"
hexmask.long.byte 0x04 0.--7. 1. "RAILCTR0,Rail Counter Value 0"
line.long 0x08 "WKUP_PSC0_RAILSEL,User can use this register to select the counter value (WKUP_PSC0_RAILCTL) for each power domain"
group.long 0x120++0x03
line.long 0x00 "WKUP_PSC0_PTCMD,This is a pseudo-command register with no actual storage"
rgroup.long 0x128++0x03
line.long 0x00 "WKUP_PSC0_PTSTAT,This is a status register"
rgroup.long 0x200++0x03
line.long 0x00 "WKUP_PSC0_PDSTAT_y,This is a status register"
bitfld.long 0x00 11. "EMUIHB,Emulation Alters Domain State" "0,1"
bitfld.long 0x00 10. "PWRBAD,Power Bad error" "0,1"
bitfld.long 0x00 9. "PORDONE,POR Done Input Status" "0,1"
bitfld.long 0x00 8. "PORZ,PORz output actual status" "0,1"
bitfld.long 0x00 0.--4. "STATE,Current Power Domain State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300++0x03
line.long 0x00 "WKUP_PSC0_PDCTL_y,This is a control register"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 29. "PWRSW,Power shorting Switch Control" "0,1"
bitfld.long 0x00 28. "ISO,Isolation Cell control" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "WAKECNT,RAM wake count delay value"
bitfld.long 0x00 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "EMUIHBIE,Emulation alters domain state" "0,1"
bitfld.long 0x00 8. "EPCGOOD,External Power Control Power Good Indication" "0,1"
newline
bitfld.long 0x00 0. "NEXT,User_Desired Next Power Domain State" "0,1"
rgroup.long 0x400++0x03
line.long 0x00 "WKUP_PSC0_PDCFG_y,This is a status register"
bitfld.long 0x00 3. "ICEPICK,Icepick support" "0,1"
bitfld.long 0x00 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1"
bitfld.long 0x00 0. "ALWAYSON,Always on power domain" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "WKUP_PSC0_MDCFG_y,This is a constant register showing some PSC settings for easy debug"
bitfld.long 0x00 16.--20. "PWRDOM,Indicates which power domain this module belongs to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "AUTOONLY," "0,1"
bitfld.long 0x00 14. "RESETISO," "0,1"
bitfld.long 0x00 13. "NEXTLOCK," "0,1"
bitfld.long 0x00 12. "ASYNC,Async Lpsc" "0,1"
bitfld.long 0x00 11. "ICEPICK,IcePick support" "0,1"
bitfld.long 0x00 10. "PERMDIS,Permanently disable" "0,1"
newline
bitfld.long 0x00 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1"
bitfld.long 0x00 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7"
rgroup.long 0x800++0x03
line.long 0x00 "WKUP_PSC0_MDSTAT_y,This register shows the status of each module"
bitfld.long 0x00 17. "EMUIHB,Emulation Alters Module State" "0,1"
bitfld.long 0x00 16. "EMURST,Emulation Alters Reset" "0,1"
bitfld.long 0x00 12. "MCKOUT,Actual modclk output to module" "0,1"
bitfld.long 0x00 11. "MRSTDONE,Module reset initialization done status" "0,1"
bitfld.long 0x00 10. "MRSTZ,Module reset actual status" "0,1"
bitfld.long 0x00 9. "LRSTDONE,Module local reset initialization done status" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset actual status" "0,1"
newline
bitfld.long 0x00 0.--5. "STATE,These bits indicate the current module state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA00++0x03
line.long 0x00 "WKUP_PSC0_MDCTL_y,This register provides specific control for the individual module"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 12. "RESETISO,Reset Isolation" "0,1"
bitfld.long 0x00 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1"
bitfld.long 0x00 10. "EMUIHBIE,Emulation Alters Module State" "0,1"
bitfld.long 0x00 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset control" "0,1"
bitfld.long 0x00 0.--4. "NEXT,Module Next State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "PSI_L_CFG_PROXY"
tree "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY"
base ad:0x2A268000
rgroup.long 0x00++0x03
line.long 0x00 "PSIL_CFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module"
group.long 0x10++0x03
line.long 0x00 "PSIL_CFG_PROXY_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
group.long 0x100++0x0B
line.long 0x00 "PSIL_CFG_PROXY_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction"
bitfld.long 0x00 31. "BUSY,Indication that a configuration read or write is in progress" "No transaction is in progress,Transaction is in progress"
bitfld.long 0x00 30. "DIR,Direction of configuration transaction" "Write transaction,Read transaction"
bitfld.long 0x00 29. "TO,Indication that a timeout occurred" "Transaction completed normally,Timeout occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "THREAD_ID,Thread ID to which configuration read or write is being sent"
line.long 0x04 "PSIL_CFG_PROXY_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction"
bitfld.long 0x04 28.--31. "BYTEN,Byte enables to use for configuration read or write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
abitfld.long 0x04 0.--15. "ADDRESS,Word (32-bit) address within thread configuration space for transaction" "0x0000=Peer thread ID register (,0x0001=Peer credit register (,0x0002=Enable register (,0x0040=Capabilities register (,0x0400=Static TR register"
line.long 0x08 "PSIL_CFG_PROXY_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction"
group.long 0x140++0x03
line.long 0x00 "PSIL_CFG_PROXY_RDATA,The Read Data Register contains the data which was read back during the configuration transaction"
tree.end
tree "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY"
base ad:0x31F78000
rgroup.long 0x00++0x03
line.long 0x00 "PSIL_CFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module"
group.long 0x10++0x03
line.long 0x00 "PSIL_CFG_PROXY_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
group.long 0x100++0x0B
line.long 0x00 "PSIL_CFG_PROXY_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction"
bitfld.long 0x00 31. "BUSY,Indication that a configuration read or write is in progress" "No transaction is in progress,Transaction is in progress"
bitfld.long 0x00 30. "DIR,Direction of configuration transaction" "Write transaction,Read transaction"
bitfld.long 0x00 29. "TO,Indication that a timeout occurred" "Transaction completed normally,Timeout occurred"
newline
hexmask.long.word 0x00 0.--15. 1. "THREAD_ID,Thread ID to which configuration read or write is being sent"
line.long 0x04 "PSIL_CFG_PROXY_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction"
bitfld.long 0x04 28.--31. "BYTEN,Byte enables to use for configuration read or write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
abitfld.long 0x04 0.--15. "ADDRESS,Word (32-bit) address within thread configuration space for transaction" "0x0000=Peer thread ID register (,0x0001=Peer credit register (,0x0002=Enable register (,0x0040=Capabilities register (,0x0400=Static TR register"
line.long 0x08 "PSIL_CFG_PROXY_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction"
group.long 0x140++0x03
line.long 0x00 "PSIL_CFG_PROXY_RDATA,The Read Data Register contains the data which was read back during the configuration transaction"
tree.end
tree.end
tree "RAT"
tree "ARMSS_RAT_CFG"
base ad:0xFF90000
rgroup.long 0x00++0x07
line.long 0x00 "RAT_PID,This register contains the major and minor revisions for the module"
line.long 0x04 "RAT_CONFIG,This register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "RAT_CTRL_j,This region controls the size and the enable for a region"
bitfld.long 0x00 31. "EN,Enable for the region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the region in address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "RAT_BASE_j,This register is used for the base address for a region"
line.long 0x08 "RAT_TRANS_L_j,This register contains the translated lower address bits for a region"
line.long 0x0C "RAT_TRANS_U_j,This register contains the translated upper address bits for a region"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated upper address bits for the region"
group.long 0x804++0x03
line.long 0x00 "RAT_DESTINATION_ID,This register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
group.long 0x820++0x1B
line.long 0x00 "RAT_EXCEPTION_LOGGING_CONTROL,This register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "RAT_EXCEPTION_LOGGING_HEADER0,This register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "RAT_EXCEPTION_LOGGING_HEADER1,This register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "RAT_EXCEPTION_LOGGING_DATA0,This register contains the first word of the data"
line.long 0x10 "RAT_EXCEPTION_LOGGING_DATA1,This register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "RAT_EXCEPTION_LOGGING_DATA2,This register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "RAT_EXCEPTION_LOGGING_DATA3,This register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "RAT_EXCEPTION_PEND_SET,This register allows to set the exception pending signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pending signal" "0,1"
line.long 0x04 "RAT_EXCEPTION_PEND_CLEAR,This register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pending signal" "0,1"
line.long 0x08 "RAT_EXCEPTION_ENABLE_SET,This register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "RAT_EXCEPTION_ENABLE_CLEAR,This register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "RAT_EOI_REG,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI value"
tree.end
tree "MCU_ARMSS_RAT_CFG"
base ad:0x40F90000
rgroup.long 0x00++0x07
line.long 0x00 "RAT_PID,This register contains the major and minor revisions for the module"
line.long 0x04 "RAT_CONFIG,This register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "RAT_CTRL_j,This region controls the size and the enable for a region"
bitfld.long 0x00 31. "EN,Enable for the region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the region in address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "RAT_BASE_j,This register is used for the base address for a region"
line.long 0x08 "RAT_TRANS_L_j,This register contains the translated lower address bits for a region"
line.long 0x0C "RAT_TRANS_U_j,This register contains the translated upper address bits for a region"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated upper address bits for the region"
group.long 0x804++0x03
line.long 0x00 "RAT_DESTINATION_ID,This register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
group.long 0x820++0x1B
line.long 0x00 "RAT_EXCEPTION_LOGGING_CONTROL,This register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "RAT_EXCEPTION_LOGGING_HEADER0,This register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "RAT_EXCEPTION_LOGGING_HEADER1,This register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "RAT_EXCEPTION_LOGGING_DATA0,This register contains the first word of the data"
line.long 0x10 "RAT_EXCEPTION_LOGGING_DATA1,This register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "RAT_EXCEPTION_LOGGING_DATA2,This register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "RAT_EXCEPTION_LOGGING_DATA3,This register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "RAT_EXCEPTION_PEND_SET,This register allows to set the exception pending signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pending signal" "0,1"
line.long 0x04 "RAT_EXCEPTION_PEND_CLEAR,This register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pending signal" "0,1"
line.long 0x08 "RAT_EXCEPTION_ENABLE_SET,This register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "RAT_EXCEPTION_ENABLE_CLEAR,This register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "RAT_EOI_REG,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI value"
tree.end
tree.end
tree "RTI"
tree "MCU_RTI0_CFG"
base ad:0x40600000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "MCU_RTI1_CFG"
base ad:0x40610000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI0_CFG"
base ad:0x2200000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI15_CFG"
base ad:0x22F0000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI16_CFG"
base ad:0x2300000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI1_CFG"
base ad:0x2210000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI24_CFG"
base ad:0x2380000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI25_CFG"
base ad:0x2390000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI28_CFG"
base ad:0x23C0000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI29_CFG"
base ad:0x23D0000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI30_CFG"
base ad:0x23E0000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree "RTI31_CFG"
base ad:0x23F0000
group.long 0x00++0x1B
line.long 0x00 "RTI_GCTRL,"
bitfld.long 0x00 15. "COS,Continue On Suspend" "0,1"
bitfld.long 0x00 1. "CNT1EN,Counter 1 Enable" "0,1"
bitfld.long 0x00 0. "CNT0EN,Counter 0 Enable" "0,1"
line.long 0x04 "RTI_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines whether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "0,1"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "0,1"
line.long 0x08 "RTI_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,Capture Counter 1" "0,1"
bitfld.long 0x08 0. "CAPCNTR0,Capture Counter 0" "0,1"
line.long 0x0C "RTI_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,Compare Select 3" "0,1"
bitfld.long 0x0C 8. "COMPSEL2,Compare Select 2" "0,1"
bitfld.long 0x0C 4. "COMPSEL1,Compare Select 1" "0,1"
bitfld.long 0x0C 0. "COMPSEL0,Compare Select 0" "0,1"
line.long 0x10 "RTI_FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously"
line.long 0x14 "RTI_UC0,"
line.long 0x18 "RTI_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "RTI_CAFRC0,"
line.long 0x04 "RTI_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "RTI_FRC1,"
line.long 0x04 "RTI_UC1,"
line.long 0x08 "RTI_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "RTI_CAFRC1,"
line.long 0x04 "RTI_CAUC1,"
group.long 0x50++0x27
line.long 0x00 "RTI_COMP0,"
line.long 0x04 "RTI_UDCP0,"
line.long 0x08 "RTI_COMP1,"
line.long 0x0C "RTI_UDCP1,"
line.long 0x10 "RTI_COMP2,"
line.long 0x14 "RTI_UDCP2,This registers holds a value. which is added to the value in the compare 2 register each time a compare matches"
line.long 0x18 "RTI_COMP3,"
line.long 0x1C "RTI_UDCP3,"
line.long 0x20 "RTI_TBLCOMP,"
line.long 0x24 "RTI_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "RTI_SETINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be enabled"
bitfld.long 0x00 18. "SETOVL1INT,Set Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x00 17. "SETOVL0INT,Set Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "0,1"
bitfld.long 0x00 11. "SETDMA3,Set Compare DMA Request 3" "0,1"
bitfld.long 0x00 10. "SETDMA2,Set Compare DMA Request 2" "0,1"
bitfld.long 0x00 9. "SETDMA1,Set Compare DMA Request 1" "0,1"
bitfld.long 0x00 8. "SETDMA0,Set Compare DMA Request 0" "0,1"
newline
bitfld.long 0x00 3. "SETINT3,Set Compare Interrupt 3" "0,1"
bitfld.long 0x00 2. "SETINT2,Set Compare Interrupt 2" "0,1"
bitfld.long 0x00 1. "SETINT1,Set Compare Interrupt 1" "0,1"
bitfld.long 0x00 0. "SETINT0,Set Compare Interrupt 0" "0,1"
line.long 0x04 "RTI_CLEARINT,This register prevents the necessity of a read-modify-write operation if a particular interrupt should be disabled"
bitfld.long 0x04 18. "CLEAROVL1INT,Clear Free Running Counter 1 Overflow Interrupt" "0,1"
bitfld.long 0x04 17. "CLEAROVL0INT,Clear Free Running Counter 0 Overflow Interrupt" "0,1"
bitfld.long 0x04 16. "CLEARTBINT," "0,1"
bitfld.long 0x04 11. "CLEARDMA3,Clear Compare DMA Request 3" "0,1"
bitfld.long 0x04 10. "CLEARDMA2,Clear Compare DMA Request 2" "0,1"
bitfld.long 0x04 9. "CLEARDMA1,Clear Compare DMA Request 1" "0,1"
bitfld.long 0x04 8. "CLEARDMA0,Clear Compare DMA Request 0" "0,1"
newline
bitfld.long 0x04 3. "CLEARINT3,Clear Compare Interrupt 3" "0,1"
bitfld.long 0x04 2. "CLEARINT2,Clear Compare Interrupt 2" "0,1"
bitfld.long 0x04 1. "CLEARINT1,Clear Compare Interrupt 1" "0,1"
bitfld.long 0x04 0. "CLEARINT0,Clear Compare Interrupt 0" "0,1"
line.long 0x08 "RTI_INTFLAG,The corresponding flags are set at every compare match of Free Running Counterx and RTICOMPx value. regardless if the interrupt is enabled or not"
bitfld.long 0x08 18. "OVL1INT,Free Running Counter 1 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 17. "OVL0INT,Free Running Counter 0 Overflow Interrupt Flag" "0,1"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "0,1"
bitfld.long 0x08 3. "INT3,Interrupt Flag 3" "0,1"
bitfld.long 0x08 2. "INT2,Interrupt Flag 2" "0,1"
bitfld.long 0x08 1. "INT1,Interrupt Flag 1" "0,1"
bitfld.long 0x08 0. "INT0,Interrupt Flag 0" "0,1"
group.long 0x90++0x2F
line.long 0x00 "RTI_DWDCTRL,Some of the RTI features described in this section may not be supported on this family of devices"
line.long 0x04 "RTI_DWDPRLD,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,Digital Watchdog Preload Value"
line.long 0x08 "RTI_WDSTATUS,Some of the RTI features described in this section may not be supported on this family of devices"
bitfld.long 0x08 5. "DWWD_ST,Windowed Watchdog Status" "0,1"
bitfld.long 0x08 4. "END,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 3. "START,Windowed Watchdog End Time Violation Status" "0,1"
bitfld.long 0x08 2. "KEYST,Watchdog KeyStatus" "0,1"
bitfld.long 0x08 1. "DWDST,Digital Watchdog Status" "0,1"
bitfld.long 0x08 0. "AWDST,Analog Watchdog Status" "0,1"
line.long 0x0C "RTI_WDKEY,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,Watchdog Key.Example of a WDKEY sequenceStep -> Value written to WDKEY -> Result1 -> 0x0A35C -> No Action2 -> 0x0A35C -> No Action3 -> 0x0E51A -> WDKEY is enabled for reset by next 0x0A35C4.."
line.long 0x10 "RTI_DWDCNTR,Some of the RTI features described in this section may not be supported on this family of devices"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,Digital Watchdog Down Counter"
line.long 0x14 "RTI_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,Digital Windowed Watchdog Reaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "RTI_WWDSIZECTRL,"
line.long 0x1C "RTI_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTI_COMP0CLR,"
line.long 0x24 "RTI_COMP1CLR,"
line.long 0x28 "RTI_COMP2CLR,"
line.long 0x2C "RTI_COMP3CLR,"
tree.end
tree.end
tree "SEC_MMR0_DBG_CTRL"
tree "SEC_MMR0_BOOT_CTRL"
base ad:0x45A40000
rgroup.long 0x20++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_DEF,Defines the type of the processor cluster"
bitfld.long 0x00 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7"
abitfld.long 0x00 8.--15. "DSP_CORE_TYPE,DSP core type configuration" "0x00=C7x,0x01=C6x,0xFF=Not DSP"
abitfld.long 0x00 0.--7. "ARM_CORE_TYPE,ARM core type configuration" "0x00=A53,0x01=A57,0x10=R5,0xFF=Not ARM"
group.long 0x40++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CFG,Configures cluster level characteristics"
hexmask.long 0x00 4.--31. 1. "CLSTR_CFG_RSVD,Reserved for future use"
rbitfld.long 0x00 3. "LOCKSTEP_EN,Lockstep enable" "0,1"
bitfld.long 0x00 2. "DBG_NO_CLKSTOP,CPU clockstop behavior" "0,1"
newline
bitfld.long 0x00 1. "TEINIT,Exception handling state at reset" "0,1"
bitfld.long 0x00 0. "LOCKSTEP,When set Core0 and Core1 operate in lockstep mode" "0,1"
group.long 0x100++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE0_CFG,Configures the TCM and interrupt operation of R5 Core0"
bitfld.long 0x00 15. "NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts when set" "0,1"
bitfld.long 0x00 11. "TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator" "0,1"
bitfld.long 0x00 7. "BTCM_EN,Enable Core0 BTCM RAM at reset when set" "0,1"
newline
bitfld.long 0x00 3. "ATCM_EN,Enable Core0 ATCM RAM at reset when set" "0,1"
group.long 0x110++0x07
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core0"
hexmask.long 0x00 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]"
line.long 0x04 "CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core0"
hexmask.long.word 0x04 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]"
group.long 0x120++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE0_PMCTRL,Configures Cluster Core0 power state"
bitfld.long 0x00 0. "CORE_HALT,Halt Core0.When 0 indicates that Core0 is in the Halt state" "0,1"
rgroup.long 0x130++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE0_PMSTAT,Shows Cluster Core0 power status"
bitfld.long 0x00 3. "CLK_GATE,Core0 Clock StoppedWhen 0 indicates clock stopped due to WFI or WFE state" "0,1"
bitfld.long 0x00 1. "WFE,Core0 WFE" "0,1"
bitfld.long 0x00 0. "WFI,Core0 WFI" "0,1"
group.long 0x180++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE1_CFG,Configures the TCM and interrupt operation of R5 Core1"
bitfld.long 0x00 15. "NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts when set" "0,1"
bitfld.long 0x00 11. "TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator" "0,1"
bitfld.long 0x00 7. "BTCM_EN,Enable Core1 BTCM RAM at reset when set" "0,1"
newline
bitfld.long 0x00 3. "ATCM_EN,Enable Core1 ATCM RAM at reset when set" "0,1"
group.long 0x190++0x07
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core1"
hexmask.long 0x00 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]"
line.long 0x04 "CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core1"
hexmask.long.word 0x04 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]"
group.long 0x1A0++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE1_PMCTRL,Configures Cluster Core1 power state"
bitfld.long 0x00 0. "CORE_HALT,Halt Core1.When 0 indicates that Core1 is in the Halt state" "0,1"
rgroup.long 0x1B0++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE1_PMSTAT,Shows Cluster Core1 power status"
bitfld.long 0x00 3. "CLK_GATE,Core1 Clock StoppedWhen 0 indicates clock stopped due to WFI or WFE state" "0,1"
bitfld.long 0x00 1. "WFE,Core1 WFE" "0,1"
bitfld.long 0x00 0. "WFI,Core1 WFI" "0,1"
rgroup.long 0x1020++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_DEF,Defines the type of the processor cluster"
bitfld.long 0x00 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7"
abitfld.long 0x00 8.--15. "DSP_CORE_TYPE,DSP core type configuration" "0x00=C7x,0x01=C6x,0xFF=Not DSP"
abitfld.long 0x00 0.--7. "ARM_CORE_TYPE,ARM core type configuration" "0x00=A53,0x01=A57,0x10=R5,0xFF=Not ARM"
group.long 0x1040++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CFG,Configures cluster level characteristics"
hexmask.long 0x00 4.--31. 1. "CLSTR_CFG_RSVD,Reserved for future use"
rbitfld.long 0x00 3. "LOCKSTEP_EN,Lockstep enable" "0,1"
bitfld.long 0x00 2. "DBG_NO_CLKSTOP,CPU clockstop behavior" "0,1"
newline
bitfld.long 0x00 1. "TEINIT,Exception handling state at reset" "0,1"
bitfld.long 0x00 0. "LOCKSTEP,When set Core0 and Core1 operate in lockstep mode" "0,1"
group.long 0x1100++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE0_CFG,Configures the TCM and interrupt operation of R5 Core0"
bitfld.long 0x00 15. "NMFI_EN,Enable Core0 Non-Maskable Fast Interrupts when set" "0,1"
bitfld.long 0x00 11. "TCM_RSTBASE,Core0 A/BTCM Reset Base Address Indicator" "0,1"
bitfld.long 0x00 7. "BTCM_EN,Enable Core0 BTCM RAM at reset when set" "0,1"
newline
bitfld.long 0x00 3. "ATCM_EN,Enable Core0 ATCM RAM at reset when set" "0,1"
group.long 0x1110++0x07
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE0_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core0"
hexmask.long 0x00 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]"
line.long 0x04 "CTRLMMR_SEC_CLSTR1_CORE0_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core0"
hexmask.long.word 0x04 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]"
group.long 0x1120++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE0_PMCTRL,Configures Cluster Core0 power state"
bitfld.long 0x00 0. "CORE_HALT,Halt Core0.When 0 indicates that Core0 is in the Halt state" "0,1"
rgroup.long 0x1130++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE0_PMSTAT,Shows Cluster Core0 power status"
bitfld.long 0x00 3. "CLK_GATE,Core0 Clock StoppedWhen 0 indicates clock stopped due to WFI or WFE state" "0,1"
bitfld.long 0x00 1. "WFE,Core0 WFE" "0,1"
bitfld.long 0x00 0. "WFI,Core0 WFI" "0,1"
group.long 0x1180++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE1_CFG,Configures the TCM and interrupt operation of R5 Core1"
bitfld.long 0x00 15. "NMFI_EN,Enable Core1 Non-Maskable Fast Interrupts when set" "0,1"
bitfld.long 0x00 11. "TCM_RSTBASE,Core1 A/BTCM Reset Base Address Indicator" "0,1"
bitfld.long 0x00 7. "BTCM_EN,Enable Core1 BTCM RAM at reset when set" "0,1"
newline
bitfld.long 0x00 3. "ATCM_EN,Enable Core1 ATCM RAM at reset when set" "0,1"
group.long 0x1190++0x07
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE1_BOOTVECT_LO,Contains the lower 32 bits of the boot vector location for R5 Core1"
hexmask.long 0x00 7.--31. 1. "VECT_ADDR,Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]"
line.long 0x04 "CTRLMMR_SEC_CLSTR1_CORE1_BOOTVECT_HI,Contains the lower 16 bits of the boot vector location for R5 Core1"
hexmask.long.word 0x04 0.--15. 1. "VECT_ADDR,Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]"
group.long 0x11A0++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE1_PMCTRL,Configures Cluster Core1 power state"
bitfld.long 0x00 0. "CORE_HALT,Halt Core1.When 0 indicates that Core1 is in the Halt state" "0,1"
rgroup.long 0x11B0++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE1_PMSTAT,Shows Cluster Core1 power status"
bitfld.long 0x00 3. "CLK_GATE,Core1 Clock StoppedWhen 0 indicates clock stopped due to WFI or WFE state" "0,1"
bitfld.long 0x00 1. "WFE,Core1 WFE" "0,1"
bitfld.long 0x00 0. "WFI,Core1 WFI" "0,1"
rgroup.long 0x2020++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR2_DEF,Defines the type of the processor cluster"
bitfld.long 0x00 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7"
abitfld.long 0x00 8.--15. "DSP_CORE_TYPE,DSP core type configuration" "0x00=C7x,0x01=C6x,0xFF=Not DSP"
abitfld.long 0x00 0.--7. "ARM_CORE_TYPE,ARM core type configuration" "0x00=A53,0x01=A57,0x10=R5,0xFF=Not ARM"
group.long 0x2040++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR2_CFG,Configures cluster level characteristics"
bitfld.long 0x00 0.--1. "SSCLK_MODE,Controls the C66 clock rate for cluster logic and bus interfaces" "Div2 clock mode,Div3 clock mode,Div4 clock mode3h - Reserved,?..."
group.long 0x2100++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR2_CORE0_CFG,Configures the C66 operation"
bitfld.long 0x00 16. "BIG_ENDIAN,When big endian operation is selected C66 core operates in big endian and corepac bridges will swzzle the data in from and out to the SoC (which is always little endian)" "0,1"
group.long 0x2110++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR2_CORE0_BOOTVECT_LO,Contains the boot vector for the C66 core"
hexmask.long.tbyte 0x00 0.--21. 1. "GEM_ISTP_RST_VAL,C66 interrupt service table pointer"
rgroup.long 0x3020++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR3_DEF,Defines the type of the processor cluster"
bitfld.long 0x00 16.--18. "CORE_NUM,Number of cores in cluster" "0,1,2,3,4,5,6,7"
abitfld.long 0x00 8.--15. "DSP_CORE_TYPE,DSP core type configuration" "0x00=C7x,0x01=C6x,0xFF=Not DSP"
abitfld.long 0x00 0.--7. "ARM_CORE_TYPE,ARM core type configuration" "0x00=A53,0x01=A57,0x10=R5,0xFF=Not ARM"
group.long 0x3040++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR3_CFG,Configures cluster level characteristics"
bitfld.long 0x00 0.--1. "SSCLK_MODE,Controls the C66 clock rate for cluster logic and bus interfaces" "Div2 clock mode,Div3 clock mode,Div4 clock mode3h - Reserved,?..."
group.long 0x3100++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR3_CORE0_CFG,Configures the C66 operation"
bitfld.long 0x00 16. "BIG_ENDIAN,When big endian operation is selected C66 core operates in big endian and corepac bridges will swzzle the data in from and out to the SoC (which is always little endian)" "0,1"
group.long 0x3110++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR3_CORE0_BOOTVECT_LO,Contains the boot vector for the C66 core"
hexmask.long.tbyte 0x00 0.--21. 1. "GEM_ISTP_RST_VAL,C66 interrupt service table pointer"
tree.end
tree "SEC_MMR0_DBG_CTRL"
base ad:0x45944000
group.long 0x00++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE0_DBG_CFG,Configures debug operation for Cluster Core0"
bitfld.long 0x00 12.--15. "DBGEN,Core0 Invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "NIDEN,Core0 Non-invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR0_CORE1_DBG_CFG,Configures debug operation for Cluster Core1"
bitfld.long 0x00 12.--15. "DBGEN,Core1 Invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "NIDEN,Core1 Non-invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1000++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE0_DBG_CFG,Configures debug operation for Cluster Core0"
bitfld.long 0x00 12.--15. "DBGEN,Core0 Invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "NIDEN,Core0 Non-invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1040++0x03
line.long 0x00 "CTRLMMR_SEC_CLSTR1_CORE1_DBG_CFG,Configures debug operation for Cluster Core1"
bitfld.long 0x00 12.--15. "DBGEN,Core1 Invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "NIDEN,Core1 Non-invasive debug enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
tree "Spinlock"
tree "SPINLOCK"
base ad:0x30E00000
rgroup.long 0x00++0x03
line.long 0x00 "SPINLOCK_REVISION,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU identifier" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module family"
bitfld.long 0x00 11.--15. "R_RTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Special version number" "0,1,2,3"
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bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "SPINLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock"
bitfld.long 0x00 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware" "0,1"
line.long 0x04 "SPINLOCK_SYSTATUS,Provides information about the Spinlock module"
hexmask.long.byte 0x04 24.--31. 1. "NUMLOCKS,Module configuration parameter n the total number of spinlocks divided by 32"
bitfld.long 0x04 7. "IU7,In-Use flag 7 covering lock registers" "All lock registers 224 - 255 are in the Not..,At least one of the lock registers 224 - 255 are.."
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bitfld.long 0x04 6. "IU6,In-Use flag 6 covering lock registers" "All lock registers 192 - 223 are in the Not..,At least one of the lock registers 192 - 223 are.."
bitfld.long 0x04 5. "IU5,In-Use flag 5 covering lock registers" "All lock registers 160 - 191 are in the Not..,At least one of the lock registers 160 - 191 are.."
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bitfld.long 0x04 4. "IU4,In-Use flag 4 covering lock registers" "All lock registers 128 - 159 are in the Not..,At least one of the lock registers 128 - 159 are.."
bitfld.long 0x04 3. "IU3,In-Use flag 3 covering lock registers" "All lock registers 96 - 127 are in the Not Taken..,At least one of the lock registers 96 - 127 are.."
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bitfld.long 0x04 2. "IU2,In-Use flag 2 covering lock registers" "All lock registers 64 - 95 are in the Not Taken..,At least one of the lock registers 64 - 95 are.."
bitfld.long 0x04 1. "IU1,In-Use flag 1 covering lock registers" "All lock registers 32 - 63 are in the Not Taken..,At least one of the lock registers 32 - 63 are.."
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bitfld.long 0x04 0. "IU0,In-Use flag 0 covering lock registers" "All lock registers 0 - 31 are in the Not Taken..,At least one of the lock registers 0 - 31 are in.."
group.long 0x800++0x03
line.long 0x00 "SPINLOCK_LOCK_REG_y,The LOCK_REG_y register is read and written to perform lock and unlock operations on lock 'y' Offset = 30E00800h + (y * 4h); where y = 0h to FFh"
bitfld.long 0x00 0. "TAKEN,Lock Status" "Free the lock by setting..,No effect"
tree.end
tree.end
tree "Time_Sync_Routers"
tree "CMPEVENT_INTRTR0_INTR_ROUTER_CFG"
base ad:0xA30000
rgroup.long 0x00++0x07
line.long 0x00 "CMPEVT_INTRTR0_PID,Description: Peripheral identification register"
line.long 0x04 "CMPEVT_INTRTR0_MUXCNTL_y,Description: Event mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for event output N" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "ENABLE,Mux control for event output N"
tree.end
tree "TIMESYNC_INTRTR0_INTR_ROUTER_CFG"
base ad:0xA40000
rgroup.long 0x00++0x07
line.long 0x00 "TIMESYNC_INTRTR0_PID,Description: Peripheral identification register"
line.long 0x04 "TIMESYNC_INTRTR0_MUXCNTL_y,Description: Event mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for event output N" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "ENABLE,Mux control for event output N"
tree.end
tree.end
tree "TIMERMGR_CFG_CFG"
tree "NAVSS0_TIMERMGR0_CFG"
base ad:0x30E80000
rgroup.long 0x00++0x0B
line.long 0x00 "TIMERMGR_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function identifier"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TIMERMGR_CNTL,This register controls the overall behavior of the timer manager module"
bitfld.long 0x04 12. "MASS_ENABLE,Always reads zero" "0,1"
hexmask.long.word 0x04 1.--10. 1. "MAX_TIMER,The maximum timer that will be"
bitfld.long 0x04 0. "ENABLE,Enables the timer manager" "Timer Manager is disabled,Timer Manager is enabled"
line.long 0x08 "TIMERMGR_COUNTER,This register contains the current value"
rgroup.long 0xA0++0x0B
line.long 0x00 "TIMERMGR_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires"
bitfld.long 0x00 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer" "0,1"
hexmask.long.word 0x00 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire"
hexmask.long.word 0x00 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers"
line.long 0x04 "TIMERMGR_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire"
bitfld.long 0x04 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1"
hexmask.long.word 0x04 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire"
bitfld.long 0x04 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1"
hexmask.long.word 0x04 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire"
line.long 0x08 "TIMERMGR_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0"
rgroup.long 0x100++0x03
line.long 0x00 "TIMERMGR_STATUS_y,Each bit is the timeout status for an individual timer"
tree.end
tree "NAVSS0_TIMERMGR1_CFG"
base ad:0x30E81000
rgroup.long 0x00++0x0B
line.long 0x00 "TIMERMGR_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function identifier"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TIMERMGR_CNTL,This register controls the overall behavior of the timer manager module"
bitfld.long 0x04 12. "MASS_ENABLE,Always reads zero" "0,1"
hexmask.long.word 0x04 1.--10. 1. "MAX_TIMER,The maximum timer that will be"
bitfld.long 0x04 0. "ENABLE,Enables the timer manager" "Timer Manager is disabled,Timer Manager is enabled"
line.long 0x08 "TIMERMGR_COUNTER,This register contains the current value"
rgroup.long 0xA0++0x0B
line.long 0x00 "TIMERMGR_TIMEOUT_STATUS0,This register should be read whenever the timer interrupt fires"
bitfld.long 0x00 23. "VALID0,1 indicates that expired_timer0 is a valid expired timer" "0,1"
hexmask.long.word 0x00 12.--22. 1. "EXPIRED_TIMER0,The ID of the first timer to expire"
hexmask.long.word 0x00 0.--11. 1. "NUM_EXPIRED_TIMERS,The total number of expired timers"
line.long 0x04 "TIMERMGR_TIMEOUT_STATUS1,This register contains the IDs of the second and third timers to expire"
bitfld.long 0x04 23. "VALID2,1 indicates that expired_timer2 is valid" "0,1"
hexmask.long.word 0x04 12.--22. 1. "EXPIRED_TIMER2,The ID of the third timer to expire"
bitfld.long 0x04 11. "VALID1,1 indicates that expired_timer1 is valid" "0,1"
hexmask.long.word 0x04 0.--10. 1. "EXPIRED_TIMER1,The ID of the second timer to expire"
line.long 0x08 "TIMERMGR_TIMEOUT_STATUS_BANK0,This register contains the status of each timer bank for banks 31:0"
rgroup.long 0x100++0x03
line.long 0x00 "TIMERMGR_STATUS_y,Each bit is the timeout status for an individual timer"
tree.end
tree.end
tree "TIMERMGR_CFG_OES"
tree "NAVSS0_TIMERMGR0_CFG_OES"
base ad:0x30F00000
group.long 0x00++0x03
line.long 0x00 "TIMERMGR_EVENTIDX_y,This programs the event index for a given timer Offset = 0h + (y * 4h); where y = 0h to 3FFh"
hexmask.long.word 0x00 0.--15. 1. "VAL,The event index for a given timer to be used on the output event interface"
tree.end
tree "NAVSS0_TIMERMGR1_CFG_OES"
base ad:0x30F01000
group.long 0x00++0x03
line.long 0x00 "TIMERMGR_EVENTIDX_y,This programs the event index for a given timer Offset = 0h + (y * 4h); where y = 0h to 3FFh"
hexmask.long.word 0x00 0.--15. 1. "VAL,The event index for a given timer to be used on the output event interface"
tree.end
tree.end
tree "TIMERMGR_CFG_TIMERS"
tree "NAVSS0_TIMERMGR0_CFG_TIMERS"
base ad:0x32200000
group.long 0x00++0x07
line.long 0x00 "TIMERMGR_SETUP_j_k,This reprograms timer N with the written value"
line.long 0x04 "TIMERMGR_CONTROL_j_k,Modifies the behavior of timer N with control signals below Offset = 4h + (j * 1000h) + (k * 100h); where j = 0h to 3Fh. k = 0h to Fh"
bitfld.long 0x04 8. "AUTORESET,Automatically reset the timer when it expires" "0,1"
rbitfld.long 0x04 2. "EXPIRED,The status of the current timer" "0,1"
bitfld.long 0x04 1. "SET,This may be used to touch/set a timer" "0,1"
bitfld.long 0x04 0. "ENABLE,Write 1 to enable 0 to disable the timer" "0,1"
tree.end
tree "NAVSS0_TIMERMGR1_CFG_TIMERS"
base ad:0x32240000
group.long 0x00++0x07
line.long 0x00 "TIMERMGR_SETUP_j_k,This reprograms timer N with the written value"
line.long 0x04 "TIMERMGR_CONTROL_j_k,Modifies the behavior of timer N with control signals below Offset = 4h + (j * 1000h) + (k * 100h); where j = 0h to 3Fh. k = 0h to Fh"
bitfld.long 0x04 8. "AUTORESET,Automatically reset the timer when it expires" "0,1"
rbitfld.long 0x04 2. "EXPIRED,The status of the current timer" "0,1"
bitfld.long 0x04 1. "SET,This may be used to touch/set a timer" "0,1"
bitfld.long 0x04 0. "ENABLE,Write 1 to enable 0 to disable the timer" "0,1"
tree.end
tree.end
tree "Timers"
tree "MCU_TIMER0_CFG"
base ad:0x40400000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER1_CFG"
base ad:0x40410000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER2_CFG"
base ad:0x40420000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER3_CFG"
base ad:0x40430000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER4_CFG"
base ad:0x40440000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER5_CFG"
base ad:0x40450000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER6_CFG"
base ad:0x40460000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER7_CFG"
base ad:0x40470000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER8_CFG"
base ad:0x40480000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "MCU_TIMER9_CFG"
base ad:0x40490000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER0_CFG"
base ad:0x2400000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER10_CFG"
base ad:0x24A0000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER11_CFG"
base ad:0x24B0000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER12_CFG"
base ad:0x24C0000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER13_CFG"
base ad:0x24D0000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER14_CFG"
base ad:0x24E0000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER15_CFG"
base ad:0x24F0000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER16_CFG"
base ad:0x2500000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER17_CFG"
base ad:0x2510000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER18_CFG"
base ad:0x2520000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER19_CFG"
base ad:0x2530000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER1_CFG"
base ad:0x2410000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER2_CFG"
base ad:0x2420000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER3_CFG"
base ad:0x2430000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER4_CFG"
base ad:0x2440000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER5_CFG"
base ad:0x2450000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER6_CFG"
base ad:0x2460000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER7_CFG"
base ad:0x2470000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER8_CFG"
base ad:0x2480000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree "TIMER9_CFG"
base ad:0x2490000
rgroup.long 0x00++0x03
line.long 0x00 "TIMER_TIDR,This read-only register contains the revision number of the module"
group.long 0x10++0x03
line.long 0x00 "TIMER_TIOCP_CFG,This register controls the various parameters of the CBASS0/MCU_CBASS0 interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode"
newline
bitfld.long 0x00 1. "EMUFREE,Emulation mode" "The timer is frozen in emulation mode..,The timer runs free regardless of PINSUSPENDN.."
newline
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "TIMER_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1"
line.long 0x04 "TIMER_IRQSTATUS_RAW,Component interrupt-request status"
bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x08 "TIMER_IRQSTATUS,Component interrupt-request status"
bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1"
newline
bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1"
newline
bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1"
line.long 0x0C "TIMER_IRQSTATUS_SET,Component interrupt-request enable"
bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x10 "TIMER_IRQSTATUS_CLR,Component interrupt-request enable"
bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare" "0,1"
newline
bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1"
newline
bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1"
line.long 0x14 "TIMER_IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up"
bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow" "Wake-up disabled,Wake-up enabled"
newline
bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match" "Wake-up disabled,Wake-up enabled"
line.long 0x18 "TIMER_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this bit is used to as an output enable for the TIMER IO pin" "TIMER IO pin functions as PWM output,TIMER IO pin functions as TRIGGER input"
newline
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second)" "Single capture,Capture on second event"
newline
bitfld.long 0x18 12. "PT,Pulse or toggle mode on POTIMERPWM output pin" "Pulse modulation,Toggle modulation"
newline
bitfld.long 0x18 10.--11. "TRG,Trigger output mode on POTIMERPWM output pin" "No trigger,Trigger on overflow,Trigger on overflow and match,Reserved"
newline
bitfld.long 0x18 8.--9. "TCM,Transition capture mode on EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.)" "No capture,Capture on rising edges of EVENT_CAPTURE pin,Capture on falling edges of EVENT_CAPTURE pin,Capture on both edges of EVENT_CAPTURE pin"
newline
bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting" "Clear the POTIMERPWM output pin and select..,Set the POTIMERPWM output pin and select.."
newline
bitfld.long 0x18 6. "CE,Compare enable" "Compare mode is disable,Compare mode is enable"
newline
bitfld.long 0x18 5. "PRE,Prescaler enable" "The timer clock input pin clocks the counter,The divided input pin clocks the counter"
newline
bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 1. "AR,Autoreload mode" "One shot timer,Autoreload timer"
newline
bitfld.long 0x18 0. "ST,Start/stop timer control" "Stop timer,Start timer"
line.long 0x1C "TIMER_TCRR,This register holds the value of the internal counter"
line.long 0x20 "TIMER_TLDR,This register holds the timer load value"
line.long 0x24 "TIMER_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "TIMER_TWPS,This register contains the write posting bits for all writable functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for the" "No write pending,Write pending"
newline
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for the" "No negative increment register write pending,Negative increment register write pending"
newline
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for the" "No positive increment register write pending,Positive increment register write pending"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for theRead" "No write pending,Write pending"
newline
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for theRead" "No write pending,Write pending"
line.long 0x2C "TIMER_TMAR,The register holds the match value to be compared with the counter's value"
line.long 0x30 "TIMER_TCAR1,This register holds the first captured value of the counter register"
line.long 0x34 "TIMER_TSICR,Timer synchronous interface control register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for firstTIMER_TCRR read operation after idle state is active.Field values" "0,1"
newline
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation: NOTE: When the module is configured in posted mode (POSTED = '1') this bit is not used" "When the module is configured in non-posted mode..,When the module is configured in non-posted mode.."
newline
bitfld.long 0x34 2. "POSTED,Posted mode selection" "Posted mode inactive,Posted mode active"
newline
bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "Software reset is disabled,Software reset is enabled"
line.long 0x38 "TIMER_TCAR2,This register holds the second captured value of the counter register"
line.long 0x3C "TIMER_TPIR,This register is used for 1-ms tick generation"
line.long 0x40 "TIMER_TNIR,This register is used for 1-ms tick generation"
line.long 0x44 "TIMER_TCVR,This register is used for 1-ms tick generation"
line.long 0x48 "TIMER_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events"
line.long 0x4C "TIMER_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts"
tree.end
tree.end
tree "UART"
tree "MCU_UART0"
base ad:0x40A00000
group.long 0x00++0x03
line.long 0x00 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register"
hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register"
line.long 0x04 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator"
bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually"
bitfld.long 0x00 6.--7. "NOT_USED," "0,1,2,3"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually"
bitfld.long 0x00 7. "EOF_IT," "0,1"
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "CTS_IT," "0,1"
bitfld.long 0x00 6. "RTS_IT," "0,1"
newline
bitfld.long 0x00 5. "XOFF_IT," "0,1"
bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "UART_EFR,Enhanced feature register This register enables or disables enhanced features"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1"
bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1"
bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1"
newline
bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "SW_FLOW_CONTROL_0,SW_FLOW_CONTROL_1,SW_FLOW_CONTROL_2,SW_FLOW_CONTROL_3,SW_FLOW_CONTROL_4,SW_FLOW_CONTROL_5,SW_FLOW_CONTROL_6,SW_FLOW_CONTROL_7,SW_FLOW_CONTROL_8,SW_FLOW_CONTROL_9,SW_FLOW_CONTROL_10,SW_FLOW_CONTROL_11,SW_FLOW_CONTROL_12,SW_FLOW_CONTROL_13,SW_FLOW_CONTROL_14,SW_FLOW_CONTROL_15"
group.long 0x08++0x03
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1"
bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "RX_FIFO_TRIG_0,RX_FIFO_TRIG_1,RX_FIFO_TRIG_2,RX_FIFO_TRIG_3"
bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "TX_FIFO_TRIG_0,TX_FIFO_TRIG_1,TX_FIFO_TRIG_2,TX_FIFO_TRIG_3"
newline
bitfld.long 0x00 3. "DMA_MODE,This register is considered if" "DMA_MODE_0,DMA_MODE_1"
bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0,TX_FIFO_CLEAR_1"
newline
bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0,RX_FIFO_CLEAR_1"
bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0,FIFO_EN_1"
rgroup.long 0x08++0x03
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active"
bitfld.long 0x00 7. "EOF_IT," "0,1"
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "UART_IIR_UART,Interrupt identification register"
bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "UART_LCR,Line control register [6:0] define transmission and reception parameters"
bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1"
bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1"
newline
bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (if" "PARITY_TYPE2_0,PARITY_TYPE2_1"
bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x04 3. "PARITY_EN," "0,1"
bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1"
newline
bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3"
line.long 0x08 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem"
bitfld.long 0x08 6. "TCR_TLR," "TCR_TLR_0,TCR_TLR_1"
bitfld.long 0x08 5. "XON_EN," "XON_EN_0,XON_EN_1"
newline
bitfld.long 0x08 4. "LOOPBACK_EN," "LOOPBACK_EN_0,LOOPBACK_EN_1"
bitfld.long 0x08 3. "CD_STS_CH," "CD_STS_CH_0,CD_STS_CH_1"
newline
bitfld.long 0x08 2. "RI_STS_CH," "RI_STS_CH_0,RI_STS_CH_1"
bitfld.long 0x08 1. "RTS,In loopback controls" "RTS_0,RTS_1"
newline
bitfld.long 0x08 0. "DTR," "DTR_0,DTR_1"
group.long 0x10++0x07
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
newline
bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x00 3. "ABORT," "0,1"
bitfld.long 0x00 2. "CRC," "0,1"
newline
bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
bitfld.long 0x00 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
bitfld.long 0x00 4. "RX_BI," "0,1"
newline
bitfld.long 0x00 3. "RX_FE," "0,1"
bitfld.long 0x00 2. "RX_PE," "0,1"
newline
bitfld.long 0x00 1. "RX_OE," "0,1"
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "UART_MSR,Modem status register"
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
newline
bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
newline
bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (or" "0,1"
bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (or" "0,1"
newline
bitfld.long 0x04 1. "DSR_STS," "0,1"
bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "RX_FIFO_TRIG_START_0,RX_FIFO_TRIG_START_1,RX_FIFO_TRIG_START_2,RX_FIFO_TRIG_START_3,RX_FIFO_TRIG_START_4,RX_FIFO_TRIG_START_5,RX_FIFO_TRIG_START_6,RX_FIFO_TRIG_START_7,RX_FIFO_TRIG_START_8,RX_FIFO_TRIG_START_9,RX_FIFO_TRIG_START_10,RX_FIFO_TRIG_START_11,RX_FIFO_TRIG_START_12,RX_FIFO_TRIG_START_13,RX_FIFO_TRIG_START_14,RX_FIFO_TRIG_START_15"
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "RX_FIFO_TRIG_HALT_0,RX_FIFO_TRIG_HALT_1,RX_FIFO_TRIG_HALT_2,RX_FIFO_TRIG_HALT_3,RX_FIFO_TRIG_HALT_4,RX_FIFO_TRIG_HALT_5,RX_FIFO_TRIG_HALT_6,RX_FIFO_TRIG_HALT_7,RX_FIFO_TRIG_HALT_8,RX_FIFO_TRIG_HALT_9,RX_FIFO_TRIG_HALT_10,RX_FIFO_TRIG_HALT_11,RX_FIFO_TRIG_HALT_12,RX_FIFO_TRIG_HALT_13,RX_FIFO_TRIG_HALT_14,RX_FIFO_TRIG_HALT_15"
group.long 0x18++0x07
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes"
line.long 0x04 "UART_SPR,Scratchpad register This read/write register does not control the module"
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "RX_FIFO_TRIG_DMA_0,RX_FIFO_TRIG_DMA_1,RX_FIFO_TRIG_DMA_2,RX_FIFO_TRIG_DMA_3,RX_FIFO_TRIG_DMA_4,RX_FIFO_TRIG_DMA_5,RX_FIFO_TRIG_DMA_6,RX_FIFO_TRIG_DMA_7,RX_FIFO_TRIG_DMA_8,RX_FIFO_TRIG_DMA_9,RX_FIFO_TRIG_DMA_10,RX_FIFO_TRIG_DMA_11,RX_FIFO_TRIG_DMA_12,RX_FIFO_TRIG_DMA_13,RX_FIFO_TRIG_DMA_14,RX_FIFO_TRIG_DMA_15"
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "TX_FIFO_TRIG_DMA_0,TX_FIFO_TRIG_DMA_1,TX_FIFO_TRIG_DMA_2,TX_FIFO_TRIG_DMA_3,TX_FIFO_TRIG_DMA_4,TX_FIFO_TRIG_DMA_5,TX_FIFO_TRIG_DMA_6,TX_FIFO_TRIG_DMA_7,TX_FIFO_TRIG_DMA_8,TX_FIFO_TRIG_DMA_9,TX_FIFO_TRIG_DMA_10,TX_FIFO_TRIG_DMA_11,TX_FIFO_TRIG_DMA_12,TX_FIFO_TRIG_DMA_13,TX_FIFO_TRIG_DMA_14,TX_FIFO_TRIG_DMA_15"
group.long 0x1C++0x0F
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes"
line.long 0x04 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and )"
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "FRAME_END_MODE_0,FRAME_END_MODE_1"
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "SIP_MODE_0,SIP_MODE_1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "SCT_0,SCT_1"
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "SET_TXIR_0,SET_TXIR_1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "IR_SLEEP_0,IR_SLEEP_1"
bitfld.long 0x04 0.--2. "MODE_SELECT," "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7"
line.long 0x08 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only"
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate function for" "SET_TXIR_ALT_0,SET_TXIR_ALT_1"
bitfld.long 0x08 6. "IRRXINVERT,IR mode only (IrDA and CIR)" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition" "0,1,2,3"
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only" "0,1,2,3"
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IrDA transmission status interrupt" "0,1"
line.long 0x0C "UART_SFLSR,Status FIFO line status register IrDA modes only"
bitfld.long 0x0C 4. "OE_ERROR," "OE_ERROR_0,OE_ERROR_1"
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "FRAME_TOO_LONG_ERROR_0,FRAME_TOO_LONG_ERROR_1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "ABORT_DETECT_0,ABORT_DETECT_1"
bitfld.long 0x0C 1. "CRC_ERROR," "CRC_ERROR_0,CRC_ERROR_1"
group.long 0x28++0x07
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only"
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "UART_RESUME,IR-IrDA and IR-CIR modes only"
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only"
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "TXFLH_0,TXFLH_1,TXFLH_2,TXFLH_3,TXFLH_4,TXFLH_5,TXFLH_6,TXFLH_7,TXFLH_8,TXFLH_9,TXFLH_10,TXFLH_11,TXFLH_12,TXFLH_13,TXFLH_14,TXFLH_15,TXFLH_16,TXFLH_17,TXFLH_18,TXFLH_19,TXFLH_20,TXFLH_21,TXFLH_22,TXFLH_23,TXFLH_24,TXFLH_25,TXFLH_26,TXFLH_27,TXFLH_28,TXFLH_29,TXFLH_30,TXFLH_31"
line.long 0x04 "UART_RXFLL,Received frame length register low IrDA modes only"
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only"
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "UART_RXFLH,Received frame length register high IrDA modes only"
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "RXFLH_0,RXFLH_1,RXFLH_2,RXFLH_3,RXFLH_4,RXFLH_5,RXFLH_6,RXFLH_7,RXFLH_8,RXFLH_9,RXFLH_10,RXFLH_11,RXFLH_12,RXFLH_13,RXFLH_14,RXFLH_15"
rgroup.long 0x34++0x07
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only"
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "SFREGH_0,SFREGH_1,SFREGH_2,SFREGH_3,SFREGH_4,SFREGH_5,SFREGH_6,SFREGH_7,SFREGH_8,SFREGH_9,SFREGH_10,SFREGH_11,SFREGH_12,SFREGH_13,SFREGH_14,SFREGH_15"
line.long 0x04 "UART_BLR,BOF control register IrDA modes only"
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "STS_FIFO_RESET_0,STS_FIFO_RESET_1"
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "XBOF_TYPE_0,XBOF_TYPE_1"
rgroup.long 0x38++0x13
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "PARITY_TYPE_0,PARITY_TYPE_1,PARITY_TYPE_2,PARITY_TYPE_3"
bitfld.long 0x00 5. "BIT_BY_CHAR," "BIT_BY_CHAR_0,BIT_BY_CHAR_1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0,SPEED_1,SPEED_2,SPEED_3,SPEED_4,SPEED_5,SPEED_6,SPEED_7,SPEED_8,SPEED_9,SPEED_10,SPEED_11,SPEED_12,SPEED_13,SPEED_14,SPEED_15,SPEED_16,SPEED_17,SPEED_18,SPEED_19,SPEED_20,SPEED_21,SPEED_22,SPEED_23,SPEED_24,SPEED_25,SPEED_26,SPEED_27,SPEED_28,SPEED_29,SPEED_30,SPEED_31"
line.long 0x04 "UART_ACREG,Auxiliary control register"
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "PULSE_TYPE_0,PULSE_TYPE_1"
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "SD_MOD_0,SD_MOD_1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "DIS_IR_RX_0,DIS_IR_RX_1"
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "DIS_TX_UNDERRUN_0,DIS_TX_UNDERRUN_1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR modes only" "SEND_SIP_0,SEND_SIP_1"
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "SCTX_EN_0,SCTX_EN_1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame abort" "ABORT_EN_0,ABORT_EN_1"
bitfld.long 0x04 0. "EOT_EN,EOT (end of transmission) bit" "EOT_EN_0,EOT_EN_1"
line.long 0x08 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register"
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "RX_TRIG_GRANU1_0,RX_TRIG_GRANU1_1"
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "TX_TRIG_GRANU1_0,TX_TRIG_GRANU1_1"
newline
bitfld.long 0x08 5. "DSR_IT," "DSR_IT_0,DSR_IT_1"
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "RX_CTS_DSR_WAKE_UP_ENABLE_0,RX_CTS_DSR_WAKE_UP_ENABLE_1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "TX_EMPTY_CTL_IT_0,TX_EMPTY_CTL_IT_1"
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "DMA_MODE_CTL_0,DMA_MODE_CTL_1"
line.long 0x0C "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0"
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "DMA_COUNTER_RST_0,DMA_COUNTER_RST_1"
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "RX_CTS_DSR_WAKE_UP_STS_0,RX_CTS_DSR_WAKE_UP_STS_1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "TX_FIFO_FULL_0,TX_FIFO_FULL_1"
line.long 0x10 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only"
hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification"
rgroup.long 0x50++0x27
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface"
bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1"
line.long 0x08 "UART_SYSS,System status register"
bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0,RESETDONE_1"
line.long 0x0C "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system"
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic"
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple)"
line.long 0x14 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO"
line.long 0x18 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO"
line.long 0x1C "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1"
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1"
line.long 0x20 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1"
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1"
line.long 0x24 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used"
hgroup.long 0x78++0x07
hide.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
hide.long 0x04 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x27
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "0,1"
line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level"
bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "UART_MDR4,Mode definition register 4"
bitfld.long 0x08 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x08 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7"
line.long 0x0C "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x0C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x0C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0x0C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x0C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0x0C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x0C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1"
newline
bitfld.long 0x0C 1. "RHR_OVERRUN," "0,1"
bitfld.long 0x0C 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "UART_ECR,Enhanced Control register"
bitfld.long 0x10 5. "CLEAR_TX_PE," "0,1"
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
bitfld.long 0x10 2. "TX_RST,Writing" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing" "0,1"
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1"
line.long 0x14 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x18 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]"
line.long 0x1C "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]"
line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
line.long 0x24 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x24 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit"
group.long 0xA4++0x0F
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit"
line.long 0x04 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list ad:0x2800000 ad:0x2810000 ad:0x2820000 ad:0x2830000 ad:0x2840000 ad:0x2850000 ad:0x2860000 ad:0x2870000 ad:0x2880000 ad:0x2890000 )
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register"
hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register"
line.long 0x04 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator"
bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually"
bitfld.long 0x00 6.--7. "NOT_USED," "0,1,2,3"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually"
bitfld.long 0x00 7. "EOF_IT," "0,1"
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "CTS_IT," "0,1"
bitfld.long 0x00 6. "RTS_IT," "0,1"
newline
bitfld.long 0x00 5. "XOFF_IT," "0,1"
bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "UART_EFR,Enhanced feature register This register enables or disables enhanced features"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1"
bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1"
bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1"
newline
bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "SW_FLOW_CONTROL_0,SW_FLOW_CONTROL_1,SW_FLOW_CONTROL_2,SW_FLOW_CONTROL_3,SW_FLOW_CONTROL_4,SW_FLOW_CONTROL_5,SW_FLOW_CONTROL_6,SW_FLOW_CONTROL_7,SW_FLOW_CONTROL_8,SW_FLOW_CONTROL_9,SW_FLOW_CONTROL_10,SW_FLOW_CONTROL_11,SW_FLOW_CONTROL_12,SW_FLOW_CONTROL_13,SW_FLOW_CONTROL_14,SW_FLOW_CONTROL_15"
group.long 0x08++0x03
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1"
bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "RX_FIFO_TRIG_0,RX_FIFO_TRIG_1,RX_FIFO_TRIG_2,RX_FIFO_TRIG_3"
bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "TX_FIFO_TRIG_0,TX_FIFO_TRIG_1,TX_FIFO_TRIG_2,TX_FIFO_TRIG_3"
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bitfld.long 0x00 3. "DMA_MODE,This register is considered if" "DMA_MODE_0,DMA_MODE_1"
bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0,TX_FIFO_CLEAR_1"
newline
bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0,RX_FIFO_CLEAR_1"
bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0,FIFO_EN_1"
rgroup.long 0x08++0x03
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active"
bitfld.long 0x00 7. "EOF_IT," "0,1"
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "UART_IIR_UART,Interrupt identification register"
bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "UART_LCR,Line control register [6:0] define transmission and reception parameters"
bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1"
bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1"
newline
bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (if" "PARITY_TYPE2_0,PARITY_TYPE2_1"
bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
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bitfld.long 0x04 3. "PARITY_EN," "0,1"
bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1"
newline
bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3"
line.long 0x08 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem"
bitfld.long 0x08 6. "TCR_TLR," "TCR_TLR_0,TCR_TLR_1"
bitfld.long 0x08 5. "XON_EN," "XON_EN_0,XON_EN_1"
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bitfld.long 0x08 4. "LOOPBACK_EN," "LOOPBACK_EN_0,LOOPBACK_EN_1"
bitfld.long 0x08 3. "CD_STS_CH," "CD_STS_CH_0,CD_STS_CH_1"
newline
bitfld.long 0x08 2. "RI_STS_CH," "RI_STS_CH_0,RI_STS_CH_1"
bitfld.long 0x08 1. "RTS,In loopback controls" "RTS_0,RTS_1"
newline
bitfld.long 0x08 0. "DTR," "DTR_0,DTR_1"
group.long 0x10++0x07
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
newline
bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x00 3. "ABORT," "0,1"
bitfld.long 0x00 2. "CRC," "0,1"
newline
bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
bitfld.long 0x00 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
bitfld.long 0x00 4. "RX_BI," "0,1"
newline
bitfld.long 0x00 3. "RX_FE," "0,1"
bitfld.long 0x00 2. "RX_PE," "0,1"
newline
bitfld.long 0x00 1. "RX_OE," "0,1"
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "UART_MSR,Modem status register"
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
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bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
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bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (or" "0,1"
bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (or" "0,1"
newline
bitfld.long 0x04 1. "DSR_STS," "0,1"
bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "RX_FIFO_TRIG_START_0,RX_FIFO_TRIG_START_1,RX_FIFO_TRIG_START_2,RX_FIFO_TRIG_START_3,RX_FIFO_TRIG_START_4,RX_FIFO_TRIG_START_5,RX_FIFO_TRIG_START_6,RX_FIFO_TRIG_START_7,RX_FIFO_TRIG_START_8,RX_FIFO_TRIG_START_9,RX_FIFO_TRIG_START_10,RX_FIFO_TRIG_START_11,RX_FIFO_TRIG_START_12,RX_FIFO_TRIG_START_13,RX_FIFO_TRIG_START_14,RX_FIFO_TRIG_START_15"
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "RX_FIFO_TRIG_HALT_0,RX_FIFO_TRIG_HALT_1,RX_FIFO_TRIG_HALT_2,RX_FIFO_TRIG_HALT_3,RX_FIFO_TRIG_HALT_4,RX_FIFO_TRIG_HALT_5,RX_FIFO_TRIG_HALT_6,RX_FIFO_TRIG_HALT_7,RX_FIFO_TRIG_HALT_8,RX_FIFO_TRIG_HALT_9,RX_FIFO_TRIG_HALT_10,RX_FIFO_TRIG_HALT_11,RX_FIFO_TRIG_HALT_12,RX_FIFO_TRIG_HALT_13,RX_FIFO_TRIG_HALT_14,RX_FIFO_TRIG_HALT_15"
group.long 0x18++0x07
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes"
line.long 0x04 "UART_SPR,Scratchpad register This read/write register does not control the module"
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "RX_FIFO_TRIG_DMA_0,RX_FIFO_TRIG_DMA_1,RX_FIFO_TRIG_DMA_2,RX_FIFO_TRIG_DMA_3,RX_FIFO_TRIG_DMA_4,RX_FIFO_TRIG_DMA_5,RX_FIFO_TRIG_DMA_6,RX_FIFO_TRIG_DMA_7,RX_FIFO_TRIG_DMA_8,RX_FIFO_TRIG_DMA_9,RX_FIFO_TRIG_DMA_10,RX_FIFO_TRIG_DMA_11,RX_FIFO_TRIG_DMA_12,RX_FIFO_TRIG_DMA_13,RX_FIFO_TRIG_DMA_14,RX_FIFO_TRIG_DMA_15"
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "TX_FIFO_TRIG_DMA_0,TX_FIFO_TRIG_DMA_1,TX_FIFO_TRIG_DMA_2,TX_FIFO_TRIG_DMA_3,TX_FIFO_TRIG_DMA_4,TX_FIFO_TRIG_DMA_5,TX_FIFO_TRIG_DMA_6,TX_FIFO_TRIG_DMA_7,TX_FIFO_TRIG_DMA_8,TX_FIFO_TRIG_DMA_9,TX_FIFO_TRIG_DMA_10,TX_FIFO_TRIG_DMA_11,TX_FIFO_TRIG_DMA_12,TX_FIFO_TRIG_DMA_13,TX_FIFO_TRIG_DMA_14,TX_FIFO_TRIG_DMA_15"
group.long 0x1C++0x0F
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes"
line.long 0x04 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and )"
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "FRAME_END_MODE_0,FRAME_END_MODE_1"
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "SIP_MODE_0,SIP_MODE_1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "SCT_0,SCT_1"
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "SET_TXIR_0,SET_TXIR_1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "IR_SLEEP_0,IR_SLEEP_1"
bitfld.long 0x04 0.--2. "MODE_SELECT," "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7"
line.long 0x08 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only"
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate function for" "SET_TXIR_ALT_0,SET_TXIR_ALT_1"
bitfld.long 0x08 6. "IRRXINVERT,IR mode only (IrDA and CIR)" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition" "0,1,2,3"
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only" "0,1,2,3"
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IrDA transmission status interrupt" "0,1"
line.long 0x0C "UART_SFLSR,Status FIFO line status register IrDA modes only"
bitfld.long 0x0C 4. "OE_ERROR," "OE_ERROR_0,OE_ERROR_1"
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "FRAME_TOO_LONG_ERROR_0,FRAME_TOO_LONG_ERROR_1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "ABORT_DETECT_0,ABORT_DETECT_1"
bitfld.long 0x0C 1. "CRC_ERROR," "CRC_ERROR_0,CRC_ERROR_1"
group.long 0x28++0x07
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only"
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "UART_RESUME,IR-IrDA and IR-CIR modes only"
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only"
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "TXFLH_0,TXFLH_1,TXFLH_2,TXFLH_3,TXFLH_4,TXFLH_5,TXFLH_6,TXFLH_7,TXFLH_8,TXFLH_9,TXFLH_10,TXFLH_11,TXFLH_12,TXFLH_13,TXFLH_14,TXFLH_15,TXFLH_16,TXFLH_17,TXFLH_18,TXFLH_19,TXFLH_20,TXFLH_21,TXFLH_22,TXFLH_23,TXFLH_24,TXFLH_25,TXFLH_26,TXFLH_27,TXFLH_28,TXFLH_29,TXFLH_30,TXFLH_31"
line.long 0x04 "UART_RXFLL,Received frame length register low IrDA modes only"
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only"
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "UART_RXFLH,Received frame length register high IrDA modes only"
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "RXFLH_0,RXFLH_1,RXFLH_2,RXFLH_3,RXFLH_4,RXFLH_5,RXFLH_6,RXFLH_7,RXFLH_8,RXFLH_9,RXFLH_10,RXFLH_11,RXFLH_12,RXFLH_13,RXFLH_14,RXFLH_15"
rgroup.long 0x34++0x07
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only"
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "SFREGH_0,SFREGH_1,SFREGH_2,SFREGH_3,SFREGH_4,SFREGH_5,SFREGH_6,SFREGH_7,SFREGH_8,SFREGH_9,SFREGH_10,SFREGH_11,SFREGH_12,SFREGH_13,SFREGH_14,SFREGH_15"
line.long 0x04 "UART_BLR,BOF control register IrDA modes only"
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "STS_FIFO_RESET_0,STS_FIFO_RESET_1"
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "XBOF_TYPE_0,XBOF_TYPE_1"
rgroup.long 0x38++0x13
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "PARITY_TYPE_0,PARITY_TYPE_1,PARITY_TYPE_2,PARITY_TYPE_3"
bitfld.long 0x00 5. "BIT_BY_CHAR," "BIT_BY_CHAR_0,BIT_BY_CHAR_1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0,SPEED_1,SPEED_2,SPEED_3,SPEED_4,SPEED_5,SPEED_6,SPEED_7,SPEED_8,SPEED_9,SPEED_10,SPEED_11,SPEED_12,SPEED_13,SPEED_14,SPEED_15,SPEED_16,SPEED_17,SPEED_18,SPEED_19,SPEED_20,SPEED_21,SPEED_22,SPEED_23,SPEED_24,SPEED_25,SPEED_26,SPEED_27,SPEED_28,SPEED_29,SPEED_30,SPEED_31"
line.long 0x04 "UART_ACREG,Auxiliary control register"
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "PULSE_TYPE_0,PULSE_TYPE_1"
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "SD_MOD_0,SD_MOD_1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "DIS_IR_RX_0,DIS_IR_RX_1"
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "DIS_TX_UNDERRUN_0,DIS_TX_UNDERRUN_1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR modes only" "SEND_SIP_0,SEND_SIP_1"
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "SCTX_EN_0,SCTX_EN_1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame abort" "ABORT_EN_0,ABORT_EN_1"
bitfld.long 0x04 0. "EOT_EN,EOT (end of transmission) bit" "EOT_EN_0,EOT_EN_1"
line.long 0x08 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register"
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "RX_TRIG_GRANU1_0,RX_TRIG_GRANU1_1"
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "TX_TRIG_GRANU1_0,TX_TRIG_GRANU1_1"
newline
bitfld.long 0x08 5. "DSR_IT," "DSR_IT_0,DSR_IT_1"
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "RX_CTS_DSR_WAKE_UP_ENABLE_0,RX_CTS_DSR_WAKE_UP_ENABLE_1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "TX_EMPTY_CTL_IT_0,TX_EMPTY_CTL_IT_1"
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "DMA_MODE_CTL_0,DMA_MODE_CTL_1"
line.long 0x0C "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0"
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "DMA_COUNTER_RST_0,DMA_COUNTER_RST_1"
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "RX_CTS_DSR_WAKE_UP_STS_0,RX_CTS_DSR_WAKE_UP_STS_1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "TX_FIFO_FULL_0,TX_FIFO_FULL_1"
line.long 0x10 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only"
hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification"
rgroup.long 0x50++0x27
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface"
bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1"
line.long 0x08 "UART_SYSS,System status register"
bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0,RESETDONE_1"
line.long 0x0C "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system"
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic"
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple)"
line.long 0x14 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO"
line.long 0x18 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO"
line.long 0x1C "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1"
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1"
line.long 0x20 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1"
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1"
line.long 0x24 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used"
hgroup.long 0x78++0x07
hide.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
hide.long 0x04 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x27
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "0,1"
line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level"
bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "UART_MDR4,Mode definition register 4"
bitfld.long 0x08 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x08 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7"
line.long 0x0C "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x0C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x0C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0x0C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x0C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0x0C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x0C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1"
newline
bitfld.long 0x0C 1. "RHR_OVERRUN," "0,1"
bitfld.long 0x0C 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "UART_ECR,Enhanced Control register"
bitfld.long 0x10 5. "CLEAR_TX_PE," "0,1"
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
bitfld.long 0x10 2. "TX_RST,Writing" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing" "0,1"
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1"
line.long 0x14 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x18 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]"
line.long 0x1C "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]"
line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
line.long 0x24 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x24 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit"
group.long 0xA4++0x0F
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit"
line.long 0x04 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
repeat.end
tree "WKUP_UART0"
base ad:0x42300000
group.long 0x00++0x03
line.long 0x00 "UART_DLL,This register. with . stores the 14-bit divisor for generation of the baud clock in the baud rate generator"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register () and the receiver shift register"
hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register () and the transmit shift register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register"
line.long 0x04 "UART_DLH,This register. with . stores the 14-bit divisor for generating the baud clock in the baud rate generator"
bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x03
line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually"
bitfld.long 0x00 6.--7. "NOT_USED," "0,1,2,3"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually"
bitfld.long 0x00 7. "EOF_IT," "0,1"
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "UART_IER_UART,Interrupt enable register The interrupt enable register () can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "CTS_IT," "0,1"
bitfld.long 0x00 6. "RTS_IT," "0,1"
newline
bitfld.long 0x00 5. "XOFF_IT," "0,1"
bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "UART_EFR,Enhanced feature register This register enables or disables enhanced features"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1"
bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1"
bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1"
newline
bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "SW_FLOW_CONTROL_0,SW_FLOW_CONTROL_1,SW_FLOW_CONTROL_2,SW_FLOW_CONTROL_3,SW_FLOW_CONTROL_4,SW_FLOW_CONTROL_5,SW_FLOW_CONTROL_6,SW_FLOW_CONTROL_7,SW_FLOW_CONTROL_8,SW_FLOW_CONTROL_9,SW_FLOW_CONTROL_10,SW_FLOW_CONTROL_11,SW_FLOW_CONTROL_12,SW_FLOW_CONTROL_13,SW_FLOW_CONTROL_14,SW_FLOW_CONTROL_15"
group.long 0x08++0x03
line.long 0x00 "UART_FCR,FIFO control register Notes: Bits 4 and 5 can only be written to when [4] = 1"
bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If" "RX_FIFO_TRIG_0,RX_FIFO_TRIG_1,RX_FIFO_TRIG_2,RX_FIFO_TRIG_3"
bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If" "TX_FIFO_TRIG_0,TX_FIFO_TRIG_1,TX_FIFO_TRIG_2,TX_FIFO_TRIG_3"
newline
bitfld.long 0x00 3. "DMA_MODE,This register is considered if" "DMA_MODE_0,DMA_MODE_1"
bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0,TX_FIFO_CLEAR_1"
newline
bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0,RX_FIFO_CLEAR_1"
bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0,FIFO_EN_1"
rgroup.long 0x08++0x03
line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active"
bitfld.long 0x00 7. "EOF_IT," "0,1"
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "UART_IIR_UART,Interrupt identification register"
bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of" "0,1,2,3"
bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "UART_LCR,Line control register [6:0] define transmission and reception parameters"
bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1"
bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1"
newline
bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (if" "PARITY_TYPE2_0,PARITY_TYPE2_1"
bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x04 3. "PARITY_EN," "0,1"
bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1"
newline
bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3"
line.long 0x08 "UART_MCR,Modem control register [3:0] controls the interface with the modem. data set. or peripheral device that emulates the modem"
bitfld.long 0x08 6. "TCR_TLR," "TCR_TLR_0,TCR_TLR_1"
bitfld.long 0x08 5. "XON_EN," "XON_EN_0,XON_EN_1"
newline
bitfld.long 0x08 4. "LOOPBACK_EN," "LOOPBACK_EN_0,LOOPBACK_EN_1"
bitfld.long 0x08 3. "CD_STS_CH," "CD_STS_CH_0,CD_STS_CH_1"
newline
bitfld.long 0x08 2. "RI_STS_CH," "RI_STS_CH_0,RI_STS_CH_1"
bitfld.long 0x08 1. "RTS,In loopback controls" "RTS_0,RTS_1"
newline
bitfld.long 0x08 0. "DTR," "DTR_0,DTR_1"
group.long 0x10++0x07
line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "UART_LSR_CIR,Line status register in CIR mode"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (" "0,1"
newline
bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x00 3. "ABORT," "0,1"
bitfld.long 0x00 2. "CRC," "0,1"
newline
bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "UART_LSR_UART,Line status register"
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
bitfld.long 0x00 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
bitfld.long 0x00 4. "RX_BI," "0,1"
newline
bitfld.long 0x00 3. "RX_FE," "0,1"
bitfld.long 0x00 2. "RX_PE," "0,1"
newline
bitfld.long 0x00 1. "RX_OE," "0,1"
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "UART_MSR,Modem status register"
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
newline
bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
newline
bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (or" "0,1"
bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (or" "0,1"
newline
bitfld.long 0x04 1. "DSR_STS," "0,1"
bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "UART_TCR,Transmission control register This register stores the RX FIFO threshold levels to start/stop transmission during hardware/software flow control"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "RX_FIFO_TRIG_START_0,RX_FIFO_TRIG_START_1,RX_FIFO_TRIG_START_2,RX_FIFO_TRIG_START_3,RX_FIFO_TRIG_START_4,RX_FIFO_TRIG_START_5,RX_FIFO_TRIG_START_6,RX_FIFO_TRIG_START_7,RX_FIFO_TRIG_START_8,RX_FIFO_TRIG_START_9,RX_FIFO_TRIG_START_10,RX_FIFO_TRIG_START_11,RX_FIFO_TRIG_START_12,RX_FIFO_TRIG_START_13,RX_FIFO_TRIG_START_14,RX_FIFO_TRIG_START_15"
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "RX_FIFO_TRIG_HALT_0,RX_FIFO_TRIG_HALT_1,RX_FIFO_TRIG_HALT_2,RX_FIFO_TRIG_HALT_3,RX_FIFO_TRIG_HALT_4,RX_FIFO_TRIG_HALT_5,RX_FIFO_TRIG_HALT_6,RX_FIFO_TRIG_HALT_7,RX_FIFO_TRIG_HALT_8,RX_FIFO_TRIG_HALT_9,RX_FIFO_TRIG_HALT_10,RX_FIFO_TRIG_HALT_11,RX_FIFO_TRIG_HALT_12,RX_FIFO_TRIG_HALT_13,RX_FIFO_TRIG_HALT_14,RX_FIFO_TRIG_HALT_15"
group.long 0x18++0x07
line.long 0x00 "UART_XOFF1,UART mode XOFF1 character"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes"
line.long 0x04 "UART_SPR,Scratchpad register This read/write register does not control the module"
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "UART_TLR,Trigger level register This register stores the programmable transmit and RX FIFO trigger levels for DMA and IRQ generation"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "RX_FIFO_TRIG_DMA_0,RX_FIFO_TRIG_DMA_1,RX_FIFO_TRIG_DMA_2,RX_FIFO_TRIG_DMA_3,RX_FIFO_TRIG_DMA_4,RX_FIFO_TRIG_DMA_5,RX_FIFO_TRIG_DMA_6,RX_FIFO_TRIG_DMA_7,RX_FIFO_TRIG_DMA_8,RX_FIFO_TRIG_DMA_9,RX_FIFO_TRIG_DMA_10,RX_FIFO_TRIG_DMA_11,RX_FIFO_TRIG_DMA_12,RX_FIFO_TRIG_DMA_13,RX_FIFO_TRIG_DMA_14,RX_FIFO_TRIG_DMA_15"
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "TX_FIFO_TRIG_DMA_0,TX_FIFO_TRIG_DMA_1,TX_FIFO_TRIG_DMA_2,TX_FIFO_TRIG_DMA_3,TX_FIFO_TRIG_DMA_4,TX_FIFO_TRIG_DMA_5,TX_FIFO_TRIG_DMA_6,TX_FIFO_TRIG_DMA_7,TX_FIFO_TRIG_DMA_8,TX_FIFO_TRIG_DMA_9,TX_FIFO_TRIG_DMA_10,TX_FIFO_TRIG_DMA_11,TX_FIFO_TRIG_DMA_12,TX_FIFO_TRIG_DMA_13,TX_FIFO_TRIG_DMA_14,TX_FIFO_TRIG_DMA_15"
group.long 0x1C++0x0F
line.long 0x00 "UART_XOFF2,UART mode XOFF2 character"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes"
line.long 0x04 "UART_MDR1,Mode definition register 1 The mode of operation can be programmed by writing to MDR1[2:0] and therefore the must be programmed on startup after configuration of the configuration registers (. . and )"
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "FRAME_END_MODE_0,FRAME_END_MODE_1"
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "SIP_MODE_0,SIP_MODE_1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "SCT_0,SCT_1"
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "SET_TXIR_0,SET_TXIR_1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "IR_SLEEP_0,IR_SLEEP_1"
bitfld.long 0x04 0.--2. "MODE_SELECT," "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7"
line.long 0x08 "UART_MDR2,Mode definition register 2 IR-IrDA and IR-CIR modes only"
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate function for" "SET_TXIR_ALT_0,SET_TXIR_ALT_1"
bitfld.long 0x08 6. "IRRXINVERT,IR mode only (IrDA and CIR)" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition" "0,1,2,3"
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only" "0,1,2,3"
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IrDA transmission status interrupt" "0,1"
line.long 0x0C "UART_SFLSR,Status FIFO line status register IrDA modes only"
bitfld.long 0x0C 4. "OE_ERROR," "OE_ERROR_0,OE_ERROR_1"
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "FRAME_TOO_LONG_ERROR_0,FRAME_TOO_LONG_ERROR_1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "ABORT_DETECT_0,ABORT_DETECT_1"
bitfld.long 0x0C 1. "CRC_ERROR," "CRC_ERROR_0,CRC_ERROR_1"
group.long 0x28++0x07
line.long 0x00 "UART_TXFLL,Transmit frame length register low IrDA modes only"
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "UART_RESUME,IR-IrDA and IR-CIR modes only"
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "UART_TXFLH,Transmit frame length register high IrDA modes only"
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "TXFLH_0,TXFLH_1,TXFLH_2,TXFLH_3,TXFLH_4,TXFLH_5,TXFLH_6,TXFLH_7,TXFLH_8,TXFLH_9,TXFLH_10,TXFLH_11,TXFLH_12,TXFLH_13,TXFLH_14,TXFLH_15,TXFLH_16,TXFLH_17,TXFLH_18,TXFLH_19,TXFLH_20,TXFLH_21,TXFLH_22,TXFLH_23,TXFLH_24,TXFLH_25,TXFLH_26,TXFLH_27,TXFLH_28,TXFLH_29,TXFLH_30,TXFLH_31"
line.long 0x04 "UART_RXFLL,Received frame length register low IrDA modes only"
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "UART_SFREGL,Status FIFO register low IrDA modes only"
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "UART_RXFLH,Received frame length register high IrDA modes only"
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "RXFLH_0,RXFLH_1,RXFLH_2,RXFLH_3,RXFLH_4,RXFLH_5,RXFLH_6,RXFLH_7,RXFLH_8,RXFLH_9,RXFLH_10,RXFLH_11,RXFLH_12,RXFLH_13,RXFLH_14,RXFLH_15"
rgroup.long 0x34++0x07
line.long 0x00 "UART_SFREGH,Status FIFO register high IrDA modes only"
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "SFREGH_0,SFREGH_1,SFREGH_2,SFREGH_3,SFREGH_4,SFREGH_5,SFREGH_6,SFREGH_7,SFREGH_8,SFREGH_9,SFREGH_10,SFREGH_11,SFREGH_12,SFREGH_13,SFREGH_14,SFREGH_15"
line.long 0x04 "UART_BLR,BOF control register IrDA modes only"
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "STS_FIFO_RESET_0,STS_FIFO_RESET_1"
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "XBOF_TYPE_0,XBOF_TYPE_1"
rgroup.long 0x38++0x13
line.long 0x00 "UART_UASR,UART autobauding status register UART autobauding mode only"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "PARITY_TYPE_0,PARITY_TYPE_1,PARITY_TYPE_2,PARITY_TYPE_3"
bitfld.long 0x00 5. "BIT_BY_CHAR," "BIT_BY_CHAR_0,BIT_BY_CHAR_1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0,SPEED_1,SPEED_2,SPEED_3,SPEED_4,SPEED_5,SPEED_6,SPEED_7,SPEED_8,SPEED_9,SPEED_10,SPEED_11,SPEED_12,SPEED_13,SPEED_14,SPEED_15,SPEED_16,SPEED_17,SPEED_18,SPEED_19,SPEED_20,SPEED_21,SPEED_22,SPEED_23,SPEED_24,SPEED_25,SPEED_26,SPEED_27,SPEED_28,SPEED_29,SPEED_30,SPEED_31"
line.long 0x04 "UART_ACREG,Auxiliary control register"
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "PULSE_TYPE_0,PULSE_TYPE_1"
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "SD_MOD_0,SD_MOD_1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "DIS_IR_RX_0,DIS_IR_RX_1"
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "DIS_TX_UNDERRUN_0,DIS_TX_UNDERRUN_1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR modes only" "SEND_SIP_0,SEND_SIP_1"
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "SCTX_EN_0,SCTX_EN_1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame abort" "ABORT_EN_0,ABORT_EN_1"
bitfld.long 0x04 0. "EOT_EN,EOT (end of transmission) bit" "EOT_EN_0,EOT_EN_1"
line.long 0x08 "UART_SCR,Supplementary control register Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the UART_IIR register"
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "RX_TRIG_GRANU1_0,RX_TRIG_GRANU1_1"
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "TX_TRIG_GRANU1_0,TX_TRIG_GRANU1_1"
newline
bitfld.long 0x08 5. "DSR_IT," "DSR_IT_0,DSR_IT_1"
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "RX_CTS_DSR_WAKE_UP_ENABLE_0,RX_CTS_DSR_WAKE_UP_ENABLE_1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "TX_EMPTY_CTL_IT_0,TX_EMPTY_CTL_IT_1"
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "DMA_MODE_CTL_0,DMA_MODE_CTL_1"
line.long 0x0C "UART_SSR,Supplementary status register Note: Bit 1 is reset only when [4] is reset to 0"
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "DMA_COUNTER_RST_0,DMA_COUNTER_RST_1"
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "RX_CTS_DSR_WAKE_UP_STS_0,RX_CTS_DSR_WAKE_UP_STS_1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "TX_FIFO_FULL_0,TX_FIFO_FULL_1"
line.long 0x10 "UART_EBLR,BOF length register IR-IrDA and IR-CIR modes only"
hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification"
rgroup.long 0x50++0x27
line.long 0x00 "UART_MVR,Module version register The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UART_SYSC,System configuration register The AUTOIDLE bit controls a power-saving technique to reduce the logic power consumption of the open-core protocol (OCP) interface"
bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3"
bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1"
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1"
line.long 0x08 "UART_SYSS,System status register"
bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0,RESETDONE_1"
line.long 0x0C "UART_WER,Wake-up enable register The UART wake-up enable register is used to mask and unmask a UART event that would subsequently notify the system"
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "UART_CFPS,Carrier frequency prescaler Because the consumer IR works at modulation rates of 30 to 56.8 kHz. the 48-MHz clock must be prescaled before the clock can drive the IR logic"
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple)"
line.long 0x14 "UART_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO"
line.long 0x18 "UART_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO"
line.long 0x1C "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1"
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1"
line.long 0x20 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1"
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1"
line.long 0x24 "UART_FREQ_SEL,Sample per bit selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used"
hgroup.long 0x78++0x07
hide.long 0x00 "UART_ABAUD_1ST_CHAR,Unused"
hide.long 0x04 "UART_BAUD_2ND_CHAR,Unused"
group.long 0x80++0x27
line.long 0x00 "UART_MDR3,Mode definition register 3"
bitfld.long 0x00 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
bitfld.long 0x00 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold in" "0,1"
bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "0,1"
line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level"
bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "UART_MDR4,Mode definition register 4"
bitfld.long 0x08 6. "MODE9,9-bit character length When '1' overrides character length setting in UART_LCR" "0,1"
bitfld.long 0x08 3.--5. "FREQ_SEL_H,Upper 3 bits of" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "MODE,New modes [when set overrides" "0,1,2,3,4,5,6,7"
line.long 0x0C "UART_EFR2,Enhanced Features Register 2"
bitfld.long 0x0C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
bitfld.long 0x0C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0x0C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
bitfld.long 0x0C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0x0C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
bitfld.long 0x0C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides" "0,1"
newline
bitfld.long 0x0C 1. "RHR_OVERRUN," "0,1"
bitfld.long 0x0C 0. "ENDIAN,Endianness" "0,1"
line.long 0x10 "UART_ECR,Enhanced Control register"
bitfld.long 0x10 5. "CLEAR_TX_PE," "0,1"
bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1"
bitfld.long 0x10 2. "TX_RST,Writing" "0,1"
newline
bitfld.long 0x10 1. "RX_RST,Writing" "0,1"
bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into" "0,1"
line.long 0x14 "UART_TIMEGUARD,Timeguard"
hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x18 "UART_TIMEOUTL,Timeout lower byte"
hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0 [Lower byte of the 16 bit value]"
line.long 0x1C "UART_TIMEOUTH,Timeout higher byte"
hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0 [Higher byte of the 16 bit value]"
line.long 0x20 "UART_SCCR,Smartcard (ISO7816) mode Control Register"
bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received The data will be loaded into the receiver FIFO and PE will be set when reading it" "0,1"
newline
bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge If not acknowledged after the max value is reached the UART transmitter will set parity error stop and not continue until it is cleared" "0,1,2,3,4,5,6,7"
line.long 0x24 "UART_ERHR,Extended Receive Holding Register"
hexmask.long.word 0x24 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit"
group.long 0xA4++0x0F
line.long 0x00 "UART_ETHR,Extended Transmit Holding Register"
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit"
line.long 0x04 "UART_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "UART_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "UART_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree.end
tree "UDMASS_INTA0_CFG"
tree "MCU_NAVSS0_UDMASS_INTA0_CFG"
base ad:0x283C0000
rgroup.quad 0x00++0x17
line.quad 0x00 "UDMA_INTA_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.quad.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.quad 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
bitfld.quad 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "UDMA_INTA_INTCAP,The IntCap Register contains information on virtual interrupts"
hexmask.quad.word 0x08 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count"
hexmask.quad.word 0x08 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers"
line.quad 0x10 "UDMA_INTA_AUXCAP,The AuxCap Register contains information on additional capabilities"
hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers NOTE: This value is 100h for MCU_NAVSS0_UDMASS_INTR_AGGR0"
hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation"
hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers NOTE: This value is 80h for MCU_NAVSS0_UDMASS_INTR_AGGR0"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG"
base ad:0x30802000
rgroup.quad 0x00++0x17
line.quad 0x00 "UDMA_INTA_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.quad.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.quad 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
bitfld.quad 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "UDMA_INTA_INTCAP,The IntCap Register contains information on virtual interrupts"
hexmask.quad.word 0x08 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count"
hexmask.quad.word 0x08 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers"
line.quad 0x10 "UDMA_INTA_AUXCAP,The AuxCap Register contains information on additional capabilities"
hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers NOTE: This value is 100h for MCU_NAVSS0_UDMASS_INTR_AGGR0"
hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation"
hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers NOTE: This value is 80h for MCU_NAVSS0_UDMASS_INTR_AGGR0"
tree.end
tree.end
tree "UDMASS_INTA0_CFG_GCNTCFG"
tree "MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG"
base ad:0x28480000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_MAP_j,The Global Event Mapping register controls the egress global event index for this event count"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX,Global event index"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG_GCNTCFG"
base ad:0x31040000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_MAP_j,The Global Event Mapping register controls the egress global event index for this event count"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX,Global event index"
tree.end
tree.end
tree "UDMASS_INTA0_CFG_GCNTRTI"
tree "MCU_NAVSS0_UDMASS_INTA0_GCNTRTI"
base ad:0x2A600000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_COUNT_j,The ETL Count register is read by software to determine how many times the event message has been received"
hexmask.quad 0x00 0.--31. 1. "CCNT,Current count"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG_GCNTRTI"
base ad:0x33800000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_COUNT_j,The ETL Count register is read by software to determine how many times the event message has been received"
hexmask.quad 0x00 0.--31. 1. "CCNT,Current count"
tree.end
tree.end
tree "UDMASS_INTA0_CFG_IMAP"
tree "MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP"
base ad:0x28560000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto"
hexmask.quad.word 0x00 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in"
bitfld.quad 0x00 0.--5. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG_IMAP"
base ad:0x30940000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_IMAP_j,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto"
hexmask.quad.word 0x00 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in"
bitfld.quad 0x00 0.--5. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree.end
tree "UDMASS_INTA0_CFG_INTR"
tree "MCU_NAVSS0_UDMASS_INTA0_CFG_INTR"
base ad:0x2A700000
group.quad 0x00++0x27
line.quad 0x00 "UDMA_INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x08 "UDMA_INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x10 "UDMA_INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x18 "UDMA_INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x20 "UDMA_INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG_INTR"
base ad:0x33D00000
group.quad 0x00++0x27
line.quad 0x00 "UDMA_INTA_ENABLE_SET_j,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x08 "UDMA_INTA_ENABLE_CLEAR_j,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x10 "UDMA_INTA_STATUS_SET_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x18 "UDMA_INTA_STATUS_CLEAR_j,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x20 "UDMA_INTA_STATUSM_j,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt"
tree.end
tree.end
tree "UDMASS_INTA0_CFG_L2G"
tree "MCU_NAVSS0_UDMASS_INTA0_CFG_L2G"
base ad:0x28570000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_MAP_j,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane"
bitfld.quad 0x00 31. "MODE,Local event detection mode" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX,Global event index"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG_L2G"
base ad:0x31100000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_MAP_j,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane"
bitfld.quad 0x00 31. "MODE,Local event detection mode" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX,Global event index"
tree.end
tree.end
tree "UDMASS_INTA0_CFG_MCAST"
tree "MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST"
base ad:0x28580000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_MCMAP_j,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces"
hexmask.quad.word 0x00 32.--47. 1. "GEVIDX1,Global event index 1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX0,Global event index 0"
tree.end
tree "NAVSS0_UDMASS_INTA0_CFG_MCAST"
base ad:0x31110000
group.quad 0x00++0x07
line.quad 0x00 "UDMA_INTA_MCMAP_j,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces"
hexmask.quad.word 0x00 32.--47. 1. "GEVIDX1,Global event index 1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX0,Global event index 0"
tree.end
tree.end
tree "UDMASS_RINGACC0_ISC_ISC"
tree "MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC"
base ad:0x45820000
group.long 0x00++0x07
line.long 0x00 "RINGACC_CONTROL_j,The ISC a Region b Control Register defines the control fields for the ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "RINGACC_CONTROL2_j,The ISC a Region b Control Register 2 defines the control fields for the ISC"
bitfld.long 0x04 31. "PASS_V,No virtID replacement pass through value" "0,1"
hexmask.long.word 0x04 16.--27. 1. "VIRTID,Virt ID"
tree.end
tree "NAVSS0_UDMASS_RINGACC0_ISC_ISC"
base ad:0x458C0000
group.long 0x00++0x07
line.long 0x00 "RINGACC_CONTROL_j,The ISC a Region b Control Register defines the control fields for the ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "RINGACC_CONTROL2_j,The ISC a Region b Control Register 2 defines the control fields for the ISC"
bitfld.long 0x04 31. "PASS_V,No virtID replacement pass through value" "0,1"
hexmask.long.word 0x04 16.--27. 1. "VIRTID,Virt ID"
tree.end
tree.end
tree "UDMASS_UDMAP0_CFG"
tree "MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG"
base ad:0x285C0000
rgroup.long 0x00++0x0B
line.long 0x00 "UDMA_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UDMA_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system"
hexmask.long.word 0x04 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles"
line.long 0x08 "UDMA_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted"
bitfld.long 0x08 1. "SOFT,Soft" "0,1"
bitfld.long 0x08 0. "FREE,Free" "0,1"
group.long 0x10++0x03
line.long 0x00 "UDMA_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
group.long 0x1C++0x13
line.long 0x00 "UDMA_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs"
hexmask.long.word 0x00 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC"
line.long 0x04 "UDMA_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports"
bitfld.long 0x04 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1"
bitfld.long 0x04 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1"
bitfld.long 0x04 17. "EOL,EOL field is supported" "0,1"
bitfld.long 0x04 16. "STATIC,STATIC field is supported" "0,1"
bitfld.long 0x04 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.long 0x04 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.long 0x04 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.long 0x04 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.long 0x04 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.long 0x04 10. "TYPE10,Type 10 TR is supported" "0,1"
bitfld.long 0x04 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.long 0x04 8. "TYPE8,Type 8 TR is supported" "0,1"
newline
bitfld.long 0x04 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.long 0x04 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.long 0x04 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.long 0x04 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.long 0x04 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.long 0x04 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.long 0x04 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.long 0x04 0. "TYPE0,Type 0 TR is supported" "0,1"
line.long 0x08 "UDMA_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports"
bitfld.long 0x08 3. "SECTR,Maximum second TR function that is supported" "0,1"
bitfld.long 0x08 2. "DFMT,Maximum data reformatting function that is supported" "0,1"
bitfld.long 0x08 1. "ELTYPE,Maximum element type value that is supported" "0,1"
bitfld.long 0x08 0. "AMODE,The maximum AMODE that is supported" "0,1"
line.long 0x0C "UDMA_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports"
hexmask.long.word 0x0C 18.--26. 1. "RCHAN_CNT,Rx internal channel count"
hexmask.long.word 0x0C 9.--17. 1. "ECHAN_CNT,Tx external channel count"
hexmask.long.word 0x0C 0.--8. 1. "TCHAN_CNT,Tx internal channel count"
line.long 0x10 "UDMA_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports"
hexmask.long.word 0x10 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count"
hexmask.long.word 0x10 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count"
hexmask.long.word 0x10 0.--13. 1. "RFLOW_CNT,Rx flow table entry count"
group.long 0x80++0x03
line.long 0x00 "UDMA_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.long 0x88++0x03
line.long 0x00 "UDMA_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check"
bitfld.long 0x00 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet" "0,1"
hexmask.long.word 0x00 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet"
hexmask.long.word 0x00 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received"
tree.end
tree "NAVSS0_UDMASS_UDMAP0_CFG"
base ad:0x31150000
rgroup.long 0x00++0x0B
line.long 0x00 "UDMA_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UDMA_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the UDMA-P in the system"
hexmask.long.word 0x04 0.--15. 1. "TIMEOUT_CNT,This field sets the timeout duration in clock cycles"
line.long 0x08 "UDMA_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted"
bitfld.long 0x08 1. "SOFT,Soft" "0,1"
bitfld.long 0x08 0. "FREE,Free" "0,1"
group.long 0x10++0x03
line.long 0x00 "UDMA_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
group.long 0x1C++0x13
line.long 0x00 "UDMA_UTC_CTRL,The external UTC control register provides a mapping of logical to physical thread IDs"
hexmask.long.word 0x00 0.--15. 1. "UTC_CHAN_START,This field specifies the starting PSI-L thread number for the external UTC"
line.long 0x04 "UDMA_CAP0,The Capabilities Register 0 specifies which standard features this UDMA-P instance supports"
bitfld.long 0x04 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1"
bitfld.long 0x04 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1"
bitfld.long 0x04 17. "EOL,EOL field is supported" "0,1"
bitfld.long 0x04 16. "STATIC,STATIC field is supported" "0,1"
bitfld.long 0x04 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.long 0x04 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.long 0x04 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.long 0x04 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.long 0x04 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.long 0x04 10. "TYPE10,Type 10 TR is supported" "0,1"
bitfld.long 0x04 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.long 0x04 8. "TYPE8,Type 8 TR is supported" "0,1"
newline
bitfld.long 0x04 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.long 0x04 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.long 0x04 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.long 0x04 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.long 0x04 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.long 0x04 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.long 0x04 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.long 0x04 0. "TYPE0,Type 0 TR is supported" "0,1"
line.long 0x08 "UDMA_CAP1,The Capabilities Register 1 specifies which standard features this UDMA-P instance supports"
bitfld.long 0x08 3. "SECTR,Maximum second TR function that is supported" "0,1"
bitfld.long 0x08 2. "DFMT,Maximum data reformatting function that is supported" "0,1"
bitfld.long 0x08 1. "ELTYPE,Maximum element type value that is supported" "0,1"
bitfld.long 0x08 0. "AMODE,The maximum AMODE that is supported" "0,1"
line.long 0x0C "UDMA_CAP2,The Capabilities Register 2 specifies how many resources this UDMA-P instance supports"
hexmask.long.word 0x0C 18.--26. 1. "RCHAN_CNT,Rx internal channel count"
hexmask.long.word 0x0C 9.--17. 1. "ECHAN_CNT,Tx external channel count"
hexmask.long.word 0x0C 0.--8. 1. "TCHAN_CNT,Tx internal channel count"
line.long 0x10 "UDMA_CAP3,The Capabilities Register 3 specifies how many resources this UDMA-P instance supports"
hexmask.long.word 0x10 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count"
hexmask.long.word 0x10 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count"
hexmask.long.word 0x10 0.--13. 1. "RFLOW_CNT,Rx flow table entry count"
group.long 0x80++0x03
line.long 0x00 "UDMA_RFLOWFWOES,The Rx Flow FW OES Register specifies a destination event number to which an event should be sent if an out of range flow ID is received on a packet"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.long 0x88++0x03
line.long 0x00 "UDMA_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check"
bitfld.long 0x00 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet" "0,1"
hexmask.long.word 0x00 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet"
hexmask.long.word 0x00 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received"
tree.end
tree.end
tree "UDMASS_UDMAP0_CFG_RCHAN"
tree "MCU_NAVSS0_UDMASS_UDMAP0_RCHAN"
base ad:0x284C0000
group.long 0x00++0x03
line.long 0x00 "UDMA_RCFG_j,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel"
bitfld.long 0x00 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel" "Pointers are physical addresses,Pointers are intermediate addresses which..,Pointers are virtual addresses which require..,?..."
newline
bitfld.long 0x00 16.--19. "CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "RESERVED,RESERVED,Channel performs packet oriented data transfers..,Channel performs packet oriented data transfers..,?,?,?,?,?,RESERVED,Channel performs Third Party DMA control..,Channel performs Third Party DMA control..,Channel performs Third Party Block Copy DMA..,Channel performs Third Party Block Copy DMA data..,Channel performs Third Party DMA data transfers..,Channel performs Third Party DMA data transfers.."
bitfld.long 0x00 15. "IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel" "Short packets are treated as exceptions and..,Short packets are ignored and the TR will.."
newline
bitfld.long 0x00 14. "IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel" "Long packets are treated as exceptions and..,Long packets are ignored and the next TR will be.."
bitfld.long 0x00 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch"
group.long 0x14++0x03
line.long 0x00 "UDMA_RCQ_j,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode"
hexmask.long.word 0x00 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to"
group.long 0x20++0x03
line.long 0x00 "UDMA_ROES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.long 0x60++0x0B
line.long 0x00 "UDMA_REOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
line.long 0x04 "UDMA_RPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x04 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--3. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread"
hexmask.long.word 0x08 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x80++0x03
line.long 0x00 "UDMA_RST_SCHED_j,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
group.long 0xF0++0x03
line.long 0x00 "UDMA_RFLOW_RNG_j,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel"
hexmask.long.word 0x00 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel"
hexmask.long.word 0x00 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range"
tree.end
tree "NAVSS0_UDMASS_UDMAP0_CFG_RCHAN"
base ad:0x30C00000
group.long 0x00++0x03
line.long 0x00 "UDMA_RCFG_j,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel"
bitfld.long 0x00 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel" "Pointers are physical addresses,Pointers are intermediate addresses which..,Pointers are virtual addresses which require..,?..."
newline
bitfld.long 0x00 16.--19. "CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "RESERVED,RESERVED,Channel performs packet oriented data transfers..,Channel performs packet oriented data transfers..,?,?,?,?,?,RESERVED,Channel performs Third Party DMA control..,Channel performs Third Party DMA control..,Channel performs Third Party Block Copy DMA..,Channel performs Third Party Block Copy DMA data..,Channel performs Third Party DMA data transfers..,Channel performs Third Party DMA data transfers.."
bitfld.long 0x00 15. "IGNORE_SHORT,This field controls whether or not short packets will be treated as exceptions or ignored for the channel" "Short packets are treated as exceptions and..,Short packets are ignored and the TR will.."
newline
bitfld.long 0x00 14. "IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel" "Long packets are treated as exceptions and..,Long packets are ignored and the next TR will be.."
bitfld.long 0x00 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch"
group.long 0x14++0x03
line.long 0x00 "UDMA_RCQ_j,The Rx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value TR based channel mode"
hexmask.long.word 0x00 0.--15. 1. "RXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to"
group.long 0x20++0x03
line.long 0x00 "UDMA_ROES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.long 0x60++0x0B
line.long 0x00 "UDMA_REOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
line.long 0x04 "UDMA_RPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x04 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--18. "QOS,Rx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--3. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread"
hexmask.long.word 0x08 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x80++0x03
line.long 0x00 "UDMA_RST_SCHED_j,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
group.long 0xF0++0x03
line.long 0x00 "UDMA_RFLOW_RNG_j,The flow range register is used to control which flows other than the default flow (0x3FFF / channel_number) are allowed to be used with this DMA channel"
hexmask.long.word 0x00 16.--30. 1. "FLOWID_CNT,Rx Flow ID Count: This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for this channel"
hexmask.long.word 0x00 0.--13. 1. "FLOWID_START,Rx Starting Flow ID: Beyond the default flow ID each channel can also make use of a single contiguous range of flow IDs and this field specifies the starting index for that range"
tree.end
tree.end
tree "UDMASS_UDMAP0_CFG_RCHANRT"
tree "MCU_NAVSS0_UDMASS_UDMAP_RCHANRT"
base ad:0x2A800000
group.long 0x00++0x03
line.long 0x00 "UDMA_RRT_CTL_j,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel"
bitfld.long 0x00 31. "EN,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TDOWN,This field indicates whether or not an Rx teardown operation is complete" "0,1"
bitfld.long 0x00 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
rbitfld.long 0x00 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "UDMA_RRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
group.long 0x80++0x03
line.long 0x00 "UDMA_RRT_STDATA_j_y,The State Data Registers contain the current working state of the Rx DMA channel"
group.long 0x200++0x3F
line.long 0x00 "UDMA_RRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400"
line.long 0x04 "UDMA_RRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401"
line.long 0x08 "UDMA_RRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402"
line.long 0x0C "UDMA_RRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403"
line.long 0x10 "UDMA_RRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404"
line.long 0x14 "UDMA_RRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405"
line.long 0x18 "UDMA_RRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406"
line.long 0x1C "UDMA_RRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407"
line.long 0x20 "UDMA_RRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408"
line.long 0x24 "UDMA_RRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409"
line.long 0x28 "UDMA_RRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x2C "UDMA_RRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x30 "UDMA_RRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x34 "UDMA_RRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x38 "UDMA_RRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x3C "UDMA_RRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "UDMA_RRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "UDMA_RRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "UDMA_RRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT"
base ad:0x34000000
group.long 0x00++0x03
line.long 0x00 "UDMA_RRT_CTL_j,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel"
bitfld.long 0x00 31. "EN,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TDOWN,This field indicates whether or not an Rx teardown operation is complete" "0,1"
bitfld.long 0x00 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
rbitfld.long 0x00 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "UDMA_RRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
group.long 0x80++0x03
line.long 0x00 "UDMA_RRT_STDATA_j_y,The State Data Registers contain the current working state of the Rx DMA channel"
group.long 0x200++0x3F
line.long 0x00 "UDMA_RRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400"
line.long 0x04 "UDMA_RRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401"
line.long 0x08 "UDMA_RRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402"
line.long 0x0C "UDMA_RRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403"
line.long 0x10 "UDMA_RRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404"
line.long 0x14 "UDMA_RRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405"
line.long 0x18 "UDMA_RRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406"
line.long 0x1C "UDMA_RRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407"
line.long 0x20 "UDMA_RRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408"
line.long 0x24 "UDMA_RRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409"
line.long 0x28 "UDMA_RRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x2C "UDMA_RRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x30 "UDMA_RRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x34 "UDMA_RRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x38 "UDMA_RRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x3C "UDMA_RRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "UDMA_RRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "UDMA_RRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "UDMA_RRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree.end
tree "UDMASS_UDMAP0_CFG_RFLOW"
tree "MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW"
base ad:0x28400000
group.long 0x00++0x1F
line.long 0x00 "UDMA_RFA_j,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow"
bitfld.long 0x00 30. "EINFO,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor" "0,1"
bitfld.long 0x00 29. "PSINFO,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor" "0,1"
newline
bitfld.long 0x00 28. "ERR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs)" "Starvation errors result in dropping packet and..,Starvation errors result in subsequent re-try of.."
bitfld.long 0x00 26.--27. "DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use" "Host,RESERVED,Monolithic,RESERVED"
newline
bitfld.long 0x00 25. "PS_LOC,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure" "0,1"
hexmask.long.word 0x00 16.--24. 1. "SOP_OFF,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer)"
newline
hexmask.long.word 0x00 0.--15. 1. "DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto"
line.long 0x04 "UDMA_RFB_j,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow"
hexmask.long.byte 0x04 24.--31. 1. "SRCTAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1"
hexmask.long.byte 0x04 16.--23. 1. "SRCTAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1"
newline
hexmask.long.byte 0x04 8.--15. 1. "DSTTAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1"
hexmask.long.byte 0x04 0.--7. 1. "DSTTAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1"
line.long 0x08 "UDMA_RFC_j,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow"
bitfld.long 0x08 28.--30. "SRCTAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_src_tag_hi,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with src_tag[7:0] from back end..,?..."
bitfld.long 0x08 24.--26. "SRCTAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_src_tag_lo,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with src_tag[7:0] from back end..,?..."
newline
bitfld.long 0x08 20.--22. "DSTTAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_dest_tag_hi,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with dest_tag[7:0] from back end..,overwrite with dest_tag[15:8] from back end..,?..."
bitfld.long 0x08 16.--18. "DSTTAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_dest_tag_lo,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with dest_tag[7:0] from back end..,overwrite with dest_tag[15:8] from back end..,?..."
newline
bitfld.long 0x08 0.--2. "SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the SOP.." "Do not use the threshold,Use the thresholds to select between the 4..,?..."
line.long 0x0C "UDMA_RFD_j,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x0C 16.--31. 1. "FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size"
hexmask.long.word 0x0C 0.--15. 1. "FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet"
line.long 0x10 "UDMA_RFE_j,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x10 16.--31. 1. "FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet"
hexmask.long.word 0x10 0.--15. 1. "FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet"
line.long 0x14 "UDMA_RFF_j,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x14 16.--31. 1. "SIZE_THRESH0,Rx Packet Size Threshold"
hexmask.long.word 0x14 0.--15. 1. "SIZE_THRESH1,Rx Packet Size Threshold"
line.long 0x18 "UDMA_RFG_j,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x18 16.--31. 1. "SIZE_THRESH2,Rx Packet Size Threshold"
hexmask.long.word 0x18 0.--15. 1. "FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size"
line.long 0x1C "UDMA_RFH_j,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x1C 16.--31. 1. "FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size"
hexmask.long.word 0x1C 0.--15. 1. "FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size"
tree.end
tree "NAVSS0_UDMASS_UDMAP0_CFG_RFLOW"
base ad:0x30D00000
group.long 0x00++0x1F
line.long 0x00 "UDMA_RFA_j,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow"
bitfld.long 0x00 30. "EINFO,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor" "0,1"
bitfld.long 0x00 29. "PSINFO,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor" "0,1"
newline
bitfld.long 0x00 28. "ERR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor or buffer starvation occurs)" "Starvation errors result in dropping packet and..,Starvation errors result in subsequent re-try of.."
bitfld.long 0x00 26.--27. "DESC_TYPE,Rx Descriptor Type: This field indicates the descriptor type to use" "Host,RESERVED,Monolithic,RESERVED"
newline
bitfld.long 0x00 25. "PS_LOC,Rx Protocol Specific Location: This bit controls where the Protocol Specific words will be placed in the Host Mode data structure" "0,1"
hexmask.long.word 0x00 16.--24. 1. "SOP_OFF,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer)"
newline
hexmask.long.word 0x00 0.--15. 1. "DEST_QNUM,Rx Destination Queue: This field indicates the default receive queue that packets on this flow should be placed onto"
line.long 0x04 "UDMA_RFB_j,The Rx Flow N Configuration Register B contains static configuration information for the Rx DMA flow"
hexmask.long.byte 0x04 24.--31. 1. "SRCTAG_HI,Rx Source Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1"
hexmask.long.byte 0x04 16.--23. 1. "SRCTAG_LO,Rx Source Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1"
newline
hexmask.long.byte 0x04 8.--15. 1. "DSTTAG_HI,Rx Destination Tag High Byte Constant Value: This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1"
hexmask.long.byte 0x04 0.--7. 1. "DSTTAG_LO,Rx Destination Tag Low Byte Constant Value: This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1"
line.long 0x08 "UDMA_RFC_j,The Rx Flow N Configuration Register C contains static configuration information for the Rx DMA flow"
bitfld.long 0x08 28.--30. "SRCTAG_HI_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_src_tag_hi,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with src_tag[7:0] from back end..,?..."
bitfld.long 0x08 24.--26. "SRCTAG_LO_SEL,Rx Source Tag Low Byte Selector: This field specifies the source for bits 7:0 of the source tag field in Word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_src_tag_lo,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with src_tag[7:0] from back end..,?..."
newline
bitfld.long 0x08 20.--22. "DSTTAG_HI_SEL,Rx Destination Tag High Byte Selector: This field specifies the source for bits 15:8 of the destination tag field in the word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_dest_tag_hi,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with dest_tag[7:0] from back end..,overwrite with dest_tag[15:8] from back end..,?..."
bitfld.long 0x08 16.--18. "DSTTAG_LO_SEL,Rx Destination Tag Low Byte Selector: This field specifies the source for bits 7:0 of the destination tag field in word 3 of the output Packet Descriptor" "do not over,overwrite with value given in rx_dest_tag_lo,overwrite with flow_id[7:0] from back end..,RESERVED,overwrite with dest_tag[7:0] from back end..,overwrite with dest_tag[15:8] from back end..,?..."
newline
bitfld.long 0x08 0.--2. "SIZE_THRESH_EN,Rx Packet Sized Based Free Buffer Queue Enables: These bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_threshN fields to determine which FDQ to allocate the SOP.." "Do not use the threshold,Use the thresholds to select between the 4..,?..."
line.long 0x0C "UDMA_RFD_j,The Rx Flow N Configuration Register D contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x0C 16.--31. 1. "FDQ0_SZ0_QNUM,Rx Free Descriptor 0 Queue Index - Size"
hexmask.long.word 0x0C 0.--15. 1. "FDQ1_QNUM,Rx Free Descriptor 1 Queue Index: This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet"
line.long 0x10 "UDMA_RFE_j,The Rx Flow N Configuration Register E contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x10 16.--31. 1. "FDQ2_QNUM,Rx Free Descriptor 2 Queue Index: This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet"
hexmask.long.word 0x10 0.--15. 1. "FDQ3_QNUM,Rx Free Descriptor 3 Queue Index: This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet"
line.long 0x14 "UDMA_RFF_j,The Rx Flow N Configuration Register F contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x14 16.--31. 1. "SIZE_THRESH0,Rx Packet Size Threshold"
hexmask.long.word 0x14 0.--15. 1. "SIZE_THRESH1,Rx Packet Size Threshold"
line.long 0x18 "UDMA_RFG_j,The Rx Flow N Configuration Register G contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x18 16.--31. 1. "SIZE_THRESH2,Rx Packet Size Threshold"
hexmask.long.word 0x18 0.--15. 1. "FDQ0_SZ1_QNUM,Rx Free Descriptor 0 Queue Index - Size"
line.long 0x1C "UDMA_RFH_j,The Rx Flow N Configuration Register H contains static configuration information for the Rx DMA flow"
hexmask.long.word 0x1C 16.--31. 1. "FDQ0_SZ2_QNUM,Rx Free Descriptor 0 Queue Index - Size"
hexmask.long.word 0x1C 0.--15. 1. "FDQ0_SZ3_QNUM,Rx Free Descriptor 0 Queue Index - Size"
tree.end
tree.end
tree "UDMASS_UDMAP0_CFG_TCHAN"
tree "MCU_NAVSS0_UDMASS_UDMAP0_TCHAN"
base ad:0x284A0000
group.long 0x00++0x07
line.long 0x00 "UDMA_TCFG_j,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel"
bitfld.long 0x00 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 30. "FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application" "DMA controller will pass extended packet info..,DMA controller will filter extended packet info.."
newline
bitfld.long 0x00 29. "FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application" "DMA controller will pass PS words if present in..,DMA controller will filter PS words"
bitfld.long 0x00 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel" "Pointers are physical addresses,Pointers are intermediate addresses which..,Pointers are virtual addresses which require..,?..."
newline
bitfld.long 0x00 16.--19. "CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "RESERVED,RESERVED,Channel performs packet oriented data transfers..,?,?,?,?,?,?,RESERVED,Channel performs Third Party DMA transfers using..,Channel performs Third Party DMA transfers using..,Channel performs Third Party Block Copy DMA..,Channel performs Third Party Block Copy DMA..,Channel performs Third Party DMA transfers using..,Channel performs Third Party DMA transfers using.."
bitfld.long 0x00 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "0,1,2,3"
newline
bitfld.long 0x00 9. "TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral" "0,1"
bitfld.long 0x00 8. "NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete" "TD packet is sent,Suppress sending TD packet"
newline
hexmask.long.byte 0x00 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch"
line.long 0x04 "UDMA_TCREDIT_j,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated"
bitfld.long 0x04 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "UDMA_TCQ_j,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode"
hexmask.long.word 0x00 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to"
group.long 0x20++0x03
line.long 0x00 "UDMA_TOES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.long 0x60++0x0B
line.long 0x00 "UDMA_TEOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
line.long 0x04 "UDMA_TPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x04 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--3. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread"
hexmask.long.word 0x08 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x70++0x03
line.long 0x00 "UDMA_TFIFO_DEPTH_j,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel"
hexmask.long.word 0x00 0.--12. 1. "FDEPTH,FIFO"
group.long 0x80++0x03
line.long 0x00 "UDMA_TST_SCHED_j,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree "NAVSS0_UDMASS_UDMAP0_CFG_TCHAN"
base ad:0x30B00000
group.long 0x00++0x07
line.long 0x00 "UDMA_TCFG_j,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel"
bitfld.long 0x00 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 30. "FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application" "DMA controller will pass extended packet info..,DMA controller will filter extended packet info.."
newline
bitfld.long 0x00 29. "FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application" "DMA controller will pass PS words if present in..,DMA controller will filter PS words"
bitfld.long 0x00 24.--25. "ATYPE,This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel" "Pointers are physical addresses,Pointers are intermediate addresses which..,Pointers are virtual addresses which require..,?..."
newline
bitfld.long 0x00 16.--19. "CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "RESERVED,RESERVED,Channel performs packet oriented data transfers..,?,?,?,?,?,?,RESERVED,Channel performs Third Party DMA transfers using..,Channel performs Third Party DMA transfers using..,Channel performs Third Party Block Copy DMA..,Channel performs Third Party Block Copy DMA..,Channel performs Third Party DMA transfers using..,Channel performs Third Party DMA transfers using.."
bitfld.long 0x00 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "0,1,2,3"
newline
bitfld.long 0x00 9. "TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral" "0,1"
bitfld.long 0x00 8. "NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete" "TD packet is sent,Suppress sending TD packet"
newline
hexmask.long.byte 0x00 0.--6. 1. "FETCH_SIZE,Specifies the # of 32-bit descriptor words to fetch"
line.long 0x04 "UDMA_TCREDIT_j,The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated"
bitfld.long 0x04 0.--2. "COUNT,Transfer Request Credit Count: this field specifies how many credits for complete TRs are available" "0,1,2,3,4,5,6,7"
group.long 0x14++0x03
line.long 0x00 "UDMA_TCQ_j,The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode"
hexmask.long.word 0x00 0.--15. 1. "TXCQ_QNUM,Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to"
group.long 0x20++0x03
line.long 0x00 "UDMA_TOES_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.long 0x60++0x0B
line.long 0x00 "UDMA_TEOES_j,The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel"
hexmask.long.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
line.long 0x04 "UDMA_TPRI_CTRL_j,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x04 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--18. "QOS,Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--3. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "UDMA_THREAD_j,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread"
hexmask.long.word 0x08 0.--15. 1. "ID,Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x70++0x03
line.long 0x00 "UDMA_TFIFO_DEPTH_j,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel"
hexmask.long.word 0x00 0.--12. 1. "FDEPTH,FIFO"
group.long 0x80++0x03
line.long 0x00 "UDMA_TST_SCHED_j,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree.end
tree "UDMASS_UDMAP0_CFG_TCHANRT"
tree "MCU_NAVSS0_UDMASS_UDMAP_TCHANRT"
base ad:0x2AA00000
group.long 0x00++0x03
line.long 0x00 "UDMA_TRT_CTL_j,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel"
bitfld.long 0x00 31. "EN,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.long 0x00 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
rbitfld.long 0x00 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "UDMA_TRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x80++0x03
line.long 0x00 "UDMA_TRT_STDATA_j_Y,The State Data Registers contain the current working state of the Tx DMA channel"
group.long 0x200++0x3F
line.long 0x00 "UDMA_TRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400"
line.long 0x04 "UDMA_TRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401"
line.long 0x08 "UDMA_TRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402"
line.long 0x0C "UDMA_TRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403"
line.long 0x10 "UDMA_TRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404"
line.long 0x14 "UDMA_TRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405"
line.long 0x18 "UDMA_TRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406"
line.long 0x1C "UDMA_TRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407"
line.long 0x20 "UDMA_TRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408"
line.long 0x24 "UDMA_TRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409"
line.long 0x28 "UDMA_TRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x2C "UDMA_TRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x30 "UDMA_TRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x34 "UDMA_TRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x38 "UDMA_TRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x3C "UDMA_TRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "UDMA_TRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "UDMA_TRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "UDMA_TRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT"
base ad:0x35000000
group.long 0x00++0x03
line.long 0x00 "UDMA_TRT_CTL_j,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel"
bitfld.long 0x00 31. "EN,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.long 0x00 29. "PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "FTDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
rbitfld.long 0x00 0. "ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "UDMA_TRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x80++0x03
line.long 0x00 "UDMA_TRT_STDATA_j_Y,The State Data Registers contain the current working state of the Tx DMA channel"
group.long 0x200++0x3F
line.long 0x00 "UDMA_TRT_PEER0_j,This register provides access to the remote peer's realtime register at 0x400"
line.long 0x04 "UDMA_TRT_PEER1_j,This register provides access to the remote peer's realtime register at 0x401"
line.long 0x08 "UDMA_TRT_PEER2_j,This register provides access to the remote peer's realtime register at 0x402"
line.long 0x0C "UDMA_TRT_PEER3_j,This register provides access to the remote peer's realtime register at 0x403"
line.long 0x10 "UDMA_TRT_PEER4_j,This register provides access to the remote peer's realtime register at 0x404"
line.long 0x14 "UDMA_TRT_PEER5_j,This register provides access to the remote peer's realtime register at 0x405"
line.long 0x18 "UDMA_TRT_PEER6_j,This register provides access to the remote peer's realtime register at 0x406"
line.long 0x1C "UDMA_TRT_PEER7_j,This register provides access to the remote peer's realtime register at 0x407"
line.long 0x20 "UDMA_TRT_PEER8_j,This register provides access to the remote peer's realtime register at 0x408"
line.long 0x24 "UDMA_TRT_PEER9_j,This register provides access to the remote peer's realtime register at 0x409"
line.long 0x28 "UDMA_TRT_PEER10_j,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x2C "UDMA_TRT_PEER11_j,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x30 "UDMA_TRT_PEER12_j,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x34 "UDMA_TRT_PEER13_j,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x38 "UDMA_TRT_PEER14_j,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x3C "UDMA_TRT_PEER15_j,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "UDMA_TRT_PCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "UDMA_TRT_BCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "UDMA_TRT_SBCNT_j,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree.end
tree "UFS0_HCLK_ECC_AGGR_CFG"
tree "UFS0_HCLK_ECC_AGGR_CFG"
base ad:0x2A28000
rgroup.long 0x00++0x03
line.long 0x00 "UFS_REV,Aggregator Revision Register Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom Version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "UFS_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Read Done Status to indicate if read on the serial VBUS interface is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address"
bitfld.long 0x00 15. "RD_SVBUS,Read Trigger Write 1h to trigger a read on the serial VBUS interface" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,ECC RAM ID Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "UFS_STAT,Misc Status Register"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Number of RAMs Indicates the number of RAMS serviced by the ECC Aggregator"
line.long 0x08 "UFS_RESERVED_SVBUS_y,Reserved Area For Serial VBUS Registers Offset = 10h + (y x 4h); where y = 0h to 7h;"
group.long 0x3C++0x07
line.long 0x00 "UFS_SEC_EOI_REG,SEC End Of Interrupt (EOI) Register The SEC End Of Interrupt (EOI) register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,End Of Interrupt (EOI)" "0,1"
line.long 0x04 "UFS_SEC_STATUS_REG0,SEC Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1"
bitfld.long 0x04 18. "MEM_CMU1_SVBUS_PEND,Interrupt Pending Status for mem_cmu1_svbus_pend" "0,1"
bitfld.long 0x04 17. "MEM_RTT_SVBUS_PEND,Interrupt Pending Status for mem_rtt_svbus_pend" "0,1"
bitfld.long 0x04 16. "MEM_WDC_SVBUS_PEND,Interrupt Pending Status for mem_wdc_svbus_pend" "0,1"
newline
bitfld.long 0x04 15. "MEM_RDF_SVBUS_PEND,Interrupt Pending Status for mem_rdf_svbus_pend" "0,1"
bitfld.long 0x04 14. "MEM_CMU3_SVBUS_PEND,Interrupt Pending Status for mem_cmu3_svbus_pend" "0,1"
bitfld.long 0x04 13. "MEM_TMU_SVBUS_PEND,Interrupt Pending Status for mem_tmu_svbus_pend" "0,1"
bitfld.long 0x04 12. "MEM_WDF_SVBUS_PEND,Interrupt Pending Status for mem_wdf_svbus_pend" "0,1"
newline
bitfld.long 0x04 11. "MEM_CMU5_SVBUS_PEND,Interrupt Pending Status for mem_cmu5_svbus_pend" "0,1"
bitfld.long 0x04 10. "MEM_CCI_SVBUS_PEND,Interrupt Pending Status for mem_cci_svbus_pend" "0,1"
bitfld.long 0x04 9. "MEM_CMU4_SVBUS_PEND,Interrupt Pending Status for mem_cmu4_svbus_pend" "0,1"
bitfld.long 0x04 8. "MEM_CMU2_SVBUS_PEND,Interrupt Pending Status for mem_cmu2_svbus_pend" "0,1"
newline
bitfld.long 0x04 7. "MEM_ID_SVBUS_PEND,Interrupt Pending Status for mem_id_svbus_pend" "0,1"
bitfld.long 0x04 6. "MEM_CIP_SVBUS_PEND,Interrupt Pending Status for mem_cip_svbus_pend" "0,1"
bitfld.long 0x04 5. "MEM_RDC_SVBUS_PEND,Interrupt Pending Status for mem_rdc_svbus_pend" "0,1"
bitfld.long 0x04 4. "MEM_CMU6_SVBUS_PEND,Interrupt Pending Status for mem_cmu6_svbus_pend" "0,1"
newline
bitfld.long 0x04 3. "MEM_WDCM_SVBUS_PEND,Interrupt Pending Status for mem_wdcm_svbus_pend" "0,1"
bitfld.long 0x04 2. "MEM_CMU7_SVBUS_PEND,Interrupt Pending Status for mem_cmu7_svbus_pend" "0,1"
bitfld.long 0x04 1. "MEM_WDCF_SVBUS_PEND,Interrupt Pending Status for mem_wdcf_svbus_pend" "0,1"
bitfld.long 0x04 0. "MEM_RX_TC0_SVBUS_PEND,Interrupt Pending Status for mem_rx_tc0_svbus_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "UFS_SEC_ENABLE_SET_REG0,SEC Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC_ENABLE_SET,Interrupt Enable Set for ramecc_pend" "0,1"
bitfld.long 0x00 18. "MEM_CMU1_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu1_svbus_pend" "0,1"
bitfld.long 0x00 17. "MEM_RTT_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rtt_svbus_pend" "0,1"
bitfld.long 0x00 16. "MEM_WDC_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "MEM_RDF_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rdf_svbus_pend" "0,1"
bitfld.long 0x00 14. "MEM_CMU3_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu3_svbus_pend" "0,1"
bitfld.long 0x00 13. "MEM_TMU_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_tmu_svbus_pend" "0,1"
bitfld.long 0x00 12. "MEM_WDF_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdf_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_CMU5_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu5_svbus_pend" "0,1"
bitfld.long 0x00 10. "MEM_CCI_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cci_svbus_pend" "0,1"
bitfld.long 0x00 9. "MEM_CMU4_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu4_svbus_pend" "0,1"
bitfld.long 0x00 8. "MEM_CMU2_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu2_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "MEM_ID_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_id_svbus_pend" "0,1"
bitfld.long 0x00 6. "MEM_CIP_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cip_svbus_pend" "0,1"
bitfld.long 0x00 5. "MEM_RDC_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rdc_svbus_pend" "0,1"
bitfld.long 0x00 4. "MEM_CMU6_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu6_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "MEM_WDCM_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdcm_svbus_pend" "0,1"
bitfld.long 0x00 2. "MEM_CMU7_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu7_svbus_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDCF_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdcf_svbus_pend" "0,1"
bitfld.long 0x00 0. "MEM_RX_TC0_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rx_tc0_svbus_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "UFS_SEC_ENABLE_CLR_REG0,SEC Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC_ENABLE_CLR,Interrupt Enable Clear for ramecc_pend" "0,1"
bitfld.long 0x00 18. "MEM_CMU1_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu1_svbus_pend" "0,1"
bitfld.long 0x00 17. "MEM_RTT_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rtt_svbus_pend" "0,1"
bitfld.long 0x00 16. "MEM_WDC_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "MEM_RDF_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rdf_svbus_pend" "0,1"
bitfld.long 0x00 14. "MEM_CMU3_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu3_svbus_pend" "0,1"
bitfld.long 0x00 13. "MEM_TMU_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_tmu_svbus_pend" "0,1"
bitfld.long 0x00 12. "MEM_WDF_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdf_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_CMU5_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu5_svbus_pend" "0,1"
bitfld.long 0x00 10. "MEM_CCI_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cci_svbus_pend" "0,1"
bitfld.long 0x00 9. "MEM_CMU4_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu4_svbus_pend" "0,1"
bitfld.long 0x00 8. "MEM_CMU2_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu2_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "MEM_ID_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_id_svbus_pend" "0,1"
bitfld.long 0x00 6. "MEM_CIP_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cip_svbus_pend" "0,1"
bitfld.long 0x00 5. "MEM_RDC_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rdc_svbus_pend" "0,1"
bitfld.long 0x00 4. "MEM_CMU6_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu6_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "MEM_WDCM_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdcm_svbus_pend" "0,1"
bitfld.long 0x00 2. "MEM_CMU7_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu7_svbus_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDCF_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdcf_svbus_pend" "0,1"
bitfld.long 0x00 0. "MEM_RX_TC0_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rx_tc0_svbus_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "UFS_DED_EOI_REG,DED End Of Interrupt (EOI) Register The DED End Of Interrupt (EOI) register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,End Of Interrupt (EOI)" "0,1"
line.long 0x04 "UFS_DED_STATUS_REG0,DED Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1"
bitfld.long 0x04 18. "MEM_CMU1_SVBUS_PEND,Interrupt Pending Status for mem_cmu1_svbus_pend" "0,1"
bitfld.long 0x04 17. "MEM_RTT_SVBUS_PEND,Interrupt Pending Status for mem_rtt_svbus_pend" "0,1"
bitfld.long 0x04 16. "MEM_WDC_SVBUS_PEND,Interrupt Pending Status for mem_wdc_svbus_pend" "0,1"
newline
bitfld.long 0x04 15. "MEM_RDF_SVBUS_PEND,Interrupt Pending Status for mem_rdf_svbus_pend" "0,1"
bitfld.long 0x04 14. "MEM_CMU3_SVBUS_PEND,Interrupt Pending Status for mem_cmu3_svbus_pend" "0,1"
bitfld.long 0x04 13. "MEM_TMU_SVBUS_PEND,Interrupt Pending Status for mem_tmu_svbus_pend" "0,1"
bitfld.long 0x04 12. "MEM_WDF_SVBUS_PEND,Interrupt Pending Status for mem_wdf_svbus_pend" "0,1"
newline
bitfld.long 0x04 11. "MEM_CMU5_SVBUS_PEND,Interrupt Pending Status for mem_cmu5_svbus_pend" "0,1"
bitfld.long 0x04 10. "MEM_CCI_SVBUS_PEND,Interrupt Pending Status for mem_cci_svbus_pend" "0,1"
bitfld.long 0x04 9. "MEM_CMU4_SVBUS_PEND,Interrupt Pending Status for mem_cmu4_svbus_pend" "0,1"
bitfld.long 0x04 8. "MEM_CMU2_SVBUS_PEND,Interrupt Pending Status for mem_cmu2_svbus_pend" "0,1"
newline
bitfld.long 0x04 7. "MEM_ID_SVBUS_PEND,Interrupt Pending Status for mem_id_svbus_pend" "0,1"
bitfld.long 0x04 6. "MEM_CIP_SVBUS_PEND,Interrupt Pending Status for mem_cip_svbus_pend" "0,1"
bitfld.long 0x04 5. "MEM_RDC_SVBUS_PEND,Interrupt Pending Status for mem_rdc_svbus_pend" "0,1"
bitfld.long 0x04 4. "MEM_CMU6_SVBUS_PEND,Interrupt Pending Status for mem_cmu6_svbus_pend" "0,1"
newline
bitfld.long 0x04 3. "MEM_WDCM_SVBUS_PEND,Interrupt Pending Status for mem_wdcm_svbus_pend" "0,1"
bitfld.long 0x04 2. "MEM_CMU7_SVBUS_PEND,Interrupt Pending Status for mem_cmu7_svbus_pend" "0,1"
bitfld.long 0x04 1. "MEM_WDCF_SVBUS_PEND,Interrupt Pending Status for mem_wdcf_svbus_pend" "0,1"
bitfld.long 0x04 0. "MEM_RX_TC0_SVBUS_PEND,Interrupt Pending Status for mem_rx_tc0_svbus_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "UFS_DED_ENABLE_SET_REG0,DED Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC_ENABLE_SET,Interrupt Enable Set for ramecc_pend" "0,1"
bitfld.long 0x00 18. "MEM_CMU1_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu1_svbus_pend" "0,1"
bitfld.long 0x00 17. "MEM_RTT_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rtt_svbus_pend" "0,1"
bitfld.long 0x00 16. "MEM_WDC_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "MEM_RDF_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rdf_svbus_pend" "0,1"
bitfld.long 0x00 14. "MEM_CMU3_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu3_svbus_pend" "0,1"
bitfld.long 0x00 13. "MEM_TMU_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_tmu_svbus_pend" "0,1"
bitfld.long 0x00 12. "MEM_WDF_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdf_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_CMU5_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu5_svbus_pend" "0,1"
bitfld.long 0x00 10. "MEM_CCI_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cci_svbus_pend" "0,1"
bitfld.long 0x00 9. "MEM_CMU4_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu4_svbus_pend" "0,1"
bitfld.long 0x00 8. "MEM_CMU2_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu2_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "MEM_ID_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_id_svbus_pend" "0,1"
bitfld.long 0x00 6. "MEM_CIP_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cip_svbus_pend" "0,1"
bitfld.long 0x00 5. "MEM_RDC_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rdc_svbus_pend" "0,1"
bitfld.long 0x00 4. "MEM_CMU6_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu6_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "MEM_WDCM_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdcm_svbus_pend" "0,1"
bitfld.long 0x00 2. "MEM_CMU7_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_cmu7_svbus_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDCF_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_wdcf_svbus_pend" "0,1"
bitfld.long 0x00 0. "MEM_RX_TC0_SVBUS_ENABLE_SET,Interrupt Enable Set for mem_rx_tc0_svbus_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "UFS_DED_ENABLE_CLR_REG0,DED Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC_ENABLE_CLR,Interrupt Enable Clear for ramecc_pend" "0,1"
bitfld.long 0x00 18. "MEM_CMU1_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu1_svbus_pend" "0,1"
bitfld.long 0x00 17. "MEM_RTT_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rtt_svbus_pend" "0,1"
bitfld.long 0x00 16. "MEM_WDC_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "MEM_RDF_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rdf_svbus_pend" "0,1"
bitfld.long 0x00 14. "MEM_CMU3_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu3_svbus_pend" "0,1"
bitfld.long 0x00 13. "MEM_TMU_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_tmu_svbus_pend" "0,1"
bitfld.long 0x00 12. "MEM_WDF_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdf_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "MEM_CMU5_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu5_svbus_pend" "0,1"
bitfld.long 0x00 10. "MEM_CCI_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cci_svbus_pend" "0,1"
bitfld.long 0x00 9. "MEM_CMU4_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu4_svbus_pend" "0,1"
bitfld.long 0x00 8. "MEM_CMU2_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu2_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "MEM_ID_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_id_svbus_pend" "0,1"
bitfld.long 0x00 6. "MEM_CIP_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cip_svbus_pend" "0,1"
bitfld.long 0x00 5. "MEM_RDC_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rdc_svbus_pend" "0,1"
bitfld.long 0x00 4. "MEM_CMU6_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu6_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "MEM_WDCM_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdcm_svbus_pend" "0,1"
bitfld.long 0x00 2. "MEM_CMU7_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_cmu7_svbus_pend" "0,1"
bitfld.long 0x00 1. "MEM_WDCF_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_wdcf_svbus_pend" "0,1"
bitfld.long 0x00 0. "MEM_RX_TC0_SVBUS_ENABLE_CLR,Interrupt Enable Clear for mem_rx_tc0_svbus_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "UFS_AGGR_ENABLE_SET,Aggregator Interrupt Enable Set Register"
bitfld.long 0x00 1. "TIMEOUT,Interrupt enable set for serial VBUS timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt enable set for parity errors" "0,1"
line.long 0x04 "UFS_AGGR_ENABLE_CLR,Aggregator Interrupt Enable Clear Register"
bitfld.long 0x04 1. "TIMEOUT,Interrupt enable clear for serial VBUS timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt enable clear for parity errors" "0,1"
line.long 0x08 "UFS_AGGR_STATUS_SET,Aggregator Interrupt Status Set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for serial VBUS timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "UFS_AGGR_STATUS_CLR,Aggregator Interrupt Status Clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for serial VBUS timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "UFS0_IPS_TCLK_ERR_INJ_CFG"
tree "UFS0_IPS_TCLK_ERR_INJ_CFG"
base ad:0x2A2A000
rgroup.long 0x00++0x0B
line.long 0x00 "UFS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UFS_INFO,The Info Register gives the configuration information of the module"
bitfld.long 0x04 0.--1. "ENDPOINTS,Total number of Targets supported by this configuration" "0,1,2,3"
line.long 0x08 "UFS_SFT_RST,The Global Soft Reset Register clears all programmable registers and returns the injector to idle state"
bitfld.long 0x08 0.--3. "KEY,Write Ah to issue a soft reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x13
line.long 0x00 "UFS_BIT1,The Bit 1 Mask Register defines the first bit to be flipped when injection is enabled"
hexmask.long.word 0x00 0.--15. 1. "BIT1,First bit to be flipped on an error injection"
line.long 0x04 "UFS_BIT2,The Bit 2 Mask Register defines the second bit to be flipped if 2-bit injection is enabled"
hexmask.long.word 0x04 0.--15. 1. "BIT2,Second bit to be flipped on an error injection if 2-bit injection is chosen"
line.long 0x08 "UFS_TRGT,The Target Select Register selects which target to interact with"
bitfld.long 0x08 0. "TRGT,Select which target to interact with" "0,1"
line.long 0x0C "UFS_CTRL,The Control Register controls the injection"
rbitfld.long 0x0C 8. "TRGT,Indicates which target is selected by theUFS_TRGT register" "0,1"
rbitfld.long 0x0C 2. "DONE,Indicates that the target selected by theUFS_TRGT register has completed error injection" "0,1"
bitfld.long 0x0C 1. "TWOBIT,Write 1h to trigger a 2-bit error in target selected by theUFS_TRGT register" "0,1"
bitfld.long 0x0C 0. "ONEBIT,Write 1h to trigger a 1-bit error in target selected by theUFS_TRGT register" "0,1"
line.long 0x10 "UFS_STATUS,The Status Register controls the injection"
bitfld.long 0x10 2. "ARMED,Indicates that the target selected by theUFS_TRGT register is ARMED for error injection" "0,1"
tree.end
tree.end
tree "UFS0_P2A_WRAP_CFG_VBP_UFSHCI"
tree "UFS0_P2A_WRAP_CFG_VBP_UFSHCI"
base ad:0x4E84000
rgroup.long 0x00++0x03
line.long 0x00 "UFS_CAP,Host Controller Capabilities Register This register describes the basic capabilities of the UFS host controller"
bitfld.long 0x00 29. "MHS,Multi-Host Support" "0,1"
bitfld.long 0x00 28. "CS,Crypto Support" "0,1"
bitfld.long 0x00 27. "DBMMS,Device Bus Master Mode Supported (Unified Memory (UM) UFSHCI Only)" "0,1"
newline
bitfld.long 0x00 26. "UICDMETMS,UIC DME_TEST_MODE Command Supported" "0,1"
bitfld.long 0x00 25. "OODDS,Out of Order Data Delivery Supported" "0,1"
bitfld.long 0x00 24. "AS64,64-bit Addressing Supported" "0,1"
newline
bitfld.long 0x00 23. "AUTOH8,Auto-Hibernation Support" "0,1"
bitfld.long 0x00 16.--18. "NUTMRS,Number of UTP Task Management Request Slots" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. "NORTT,Number of Pending RTTs supported"
newline
bitfld.long 0x00 0.--4. "NUTRS,Number of UTP Transfer Request Slots" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x08++0x03
line.long 0x00 "UFS_VER,UFS Version Register This register indicates the major and minor version of the UFSHCI specification that the controller implementation supports"
hexmask.long.byte 0x00 8.--15. 1. "MJR,Major Version Number"
bitfld.long 0x00 4.--7. "MNR,Minor Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "VER,Version Suffix (VS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x10++0x0B
line.long 0x00 "UFS_HCPID,Host Controller Identification Descriptor Register (Device ID and Device Class) This register indicates the product identification information for host controller"
line.long 0x04 "UFS_HCMID,Host Controller Identification Descriptor Register (Product ID and Manufacturer ID) This register provides Manufacturer identification information for host controller manufacturer"
hexmask.long.byte 0x04 8.--15. 1. "BI,Bank Index"
hexmask.long.byte 0x04 0.--7. 1. "MIC,Manufacturer Identification Code"
line.long 0x08 "UFS_AHIT,Auto-Hibernate Idle Timer Register The UFS utilizes UniPro and SCSI standards as its power management framework"
bitfld.long 0x08 10.--12. "TS,Time Scale" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x08 0.--9. 1. "AH8ITV,Auto-Hibernate Idle Timer Value"
group.long 0x20++0x07
line.long 0x00 "UFS_IS,Interrupt Status Register This register indicates pending interrupts that require service by the low level driver firmware"
bitfld.long 0x00 18. "CEFES,Crypto Engine Fatal Error Status" "0,1"
bitfld.long 0x00 17. "SBFES,System Bus Fatal Error Status" "0,1"
bitfld.long 0x00 16. "HCFES,Host Controller Fatal Error Status" "0,1"
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bitfld.long 0x00 12. "UTPES,UTP Error Status" "0,1"
bitfld.long 0x00 11. "DFES,Device Fatal Error Status" "0,1"
bitfld.long 0x00 10. "UCCS,UIC Command Completion Status" "0,1"
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bitfld.long 0x00 9. "UTMRCS,UTP Task Management Request Completion Status" "0,1"
bitfld.long 0x00 8. "ULSS,UIC Link Startup Status" "0,1"
bitfld.long 0x00 7. "ULLS,UIC Link Lost Status" "0,1"
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bitfld.long 0x00 6. "UHES,UIC Hibernate Enter Status" "0,1"
bitfld.long 0x00 5. "UHXS,UIC Hibernate Exit Status" "0,1"
bitfld.long 0x00 4. "UPMS,UIC Power Mode Status" "0,1"
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bitfld.long 0x00 3. "UTMS,UIC Test Mode Status" "0,1"
bitfld.long 0x00 2. "UE,UIC Error" "0,1"
bitfld.long 0x00 1. "UDEPRI,UIC DME_ENDPOINTRESET Indication" "0,1"
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bitfld.long 0x00 0. "UTRCS,UTP Transfer Request Completion Status" "0,1"
line.long 0x04 "UFS_IE,Interrupt Enable Register This register enables and disables the reporting of the corresponding interrupt to host software"
bitfld.long 0x04 18. "CEFEE,Crypto Engine Fatal Error Enable" "0,1"
bitfld.long 0x04 17. "SBFEE,System Bus Fatal Error Enable" "0,1"
bitfld.long 0x04 16. "HCFEE,Host Controller Fatal Error Enable" "0,1"
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bitfld.long 0x04 12. "UTPEE,UTP Error Enable" "0,1"
bitfld.long 0x04 11. "DFEE,Device Fatal Error Enable" "0,1"
bitfld.long 0x04 10. "UCCE,UIC COMMAND Completion Enable" "0,1"
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bitfld.long 0x04 9. "UTMRCE,UTP Task Management Request Completion Enable" "0,1"
bitfld.long 0x04 8. "ULSSE,UIC Link Startup Status Enable" "0,1"
bitfld.long 0x04 7. "ULLSE,UIC Link Lost Status Enable" "0,1"
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bitfld.long 0x04 6. "UHESE,UIC Hibernate Enter Status Enable" "0,1"
bitfld.long 0x04 5. "UHXSE,UIC Hibernate Exit Status Enable" "0,1"
bitfld.long 0x04 4. "UPMSE,UIC Power Mode Status Enable" "0,1"
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bitfld.long 0x04 3. "UTMSE,UIC Test Mode Status Enable" "0,1"
bitfld.long 0x04 2. "UEE,UIC Error Enable" "0,1"
bitfld.long 0x04 1. "UDEPRIE,UIC DME_ENDPOINTRESET" "0,1"
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bitfld.long 0x04 0. "UTRCE,UTP Transfer Request Completion Enable" "0,1"
rgroup.long 0x30++0x37
line.long 0x00 "UFS_HCS,Host Controller Status Register The software shall check that the [2] UTMRLRDY bit is set to 1h before issuing a Task Management command"
hexmask.long.byte 0x00 24.--31. 1. "TLUNUTPE,Target LUN of UTP Error"
hexmask.long.byte 0x00 16.--23. 1. "TTAGUTPE,Task Tag of UTP Error"
bitfld.long 0x00 12.--15. "UTPEC,UTP Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--10. "UPMCRS,UIC Power Mode Change Request Status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "UCRDY,UIC COMMAND Ready" "0,1"
bitfld.long 0x00 2. "UTMRLRDY,UTP Task Management Request List Ready" "0,1"
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bitfld.long 0x00 1. "UTRLRDY,UTP Transfer Request List Ready" "0,1"
bitfld.long 0x00 0. "DP,Device Present" "0,1"
line.long 0x04 "UFS_HCE,Host Controller Enable Register"
bitfld.long 0x04 1. "CGE,Crypto General Enable" "0,1"
bitfld.long 0x04 0. "HCE,Host Controller Enable" "0,1"
line.long 0x08 "UFS_UECPA,Host Controller UIC Error Code PHY Adapter Layer Register Note: The register content is automatically cleared after reading"
bitfld.long 0x08 31. "ERR,UIC PHY Adapter Layer Error" "0,1"
bitfld.long 0x08 0.--4. "EC,UIC Adapter Layer Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "UFS_UECDL,Host UIC Error Code Data Link Layer Register Note: The register content is automatically cleared after reading"
bitfld.long 0x0C 31. "ERR,UIC Data Link Layer Error" "0,1"
hexmask.long.word 0x0C 0.--14. 1. "EC,UIC Data Link Layer Error"
line.long 0x10 "UFS_UECN,Host UIC Error Code Network Layer Register Note: The register content is automatically cleared after reading"
bitfld.long 0x10 31. "ERR,UIC Network Layer Error" "0,1"
bitfld.long 0x10 0.--2. "EC,UIC Network Layer Error Code" "0,1,2,3,4,5,6,7"
line.long 0x14 "UFS_UECT,Host UIC Error Code Transport Layer Register Note: The register content is automatically cleared after reading"
bitfld.long 0x14 31. "ERR,UIC Transport Layer Error" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "EC,UIC Transport Layer Error Code"
line.long 0x18 "UFS_UECDME,Host UIC Error Code DME Register The register is reserved for future use and is fixed to 0000 0000h"
bitfld.long 0x18 31. "ERR,UIC DME Error" "0,1"
bitfld.long 0x18 0. "EC,UIC DME Error Code" "0,1"
line.long 0x1C "UFS_UTRIACR,UTP Transfer Request Interrupt Aggregation Control Register"
bitfld.long 0x1C 31. "IAEN,Interrupt Aggregation Enable/Disable" "0,1"
bitfld.long 0x1C 24. "IAPWEN,Interrupt Aggregation Parameter Write Enable" "0,1"
rbitfld.long 0x1C 20. "IASB,Interrupt Aggregation Status Bit" "0,1"
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bitfld.long 0x1C 16. "CTR,Counter and Timer Reset" "0,1"
bitfld.long 0x1C 8.--12. "IACTH,Interrupt Aggregation Counter Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x1C 0.--7. 1. "IATOVAL,Interrupt Aggregation Timeout Value"
line.long 0x20 "UFS_UTRLBA,UTP Transfer Request List Base Address Register"
hexmask.long.tbyte 0x20 10.--31. 1. "UTRLBA,UTP Transfer Request List Base Address"
line.long 0x24 "UFS_UTRLBAU,UTP Transfer Request List Base Address Upper 32-bits Register Note: Since this UFS host controller implementation supports an 32-bit address bus. the upper 32-bit of the base address are ignored"
line.long 0x28 "UFS_UTRLDBR,UTP Transfer Request List Door Bell Register This register controls the basic actions of the host controller"
line.long 0x2C "UFS_UTRLCLR,UTP Transfer Request List Clear Register"
line.long 0x30 "UFS_UTRLRSR,UTP Transfer Request List Run Stop Register This register controls the command processing of the UFS host controller"
bitfld.long 0x30 0. "UTRLRSR,UTP Transfer Request List Run-Stop" "0,1"
line.long 0x34 "UFS_UTRLCNR,UTP Transfer Request List Completion Notification Register"
group.long 0x70++0x13
line.long 0x00 "UFS_UTMRLBA,UTP Task Management Request List Base Address"
hexmask.long.tbyte 0x00 10.--31. 1. "UTMRLBA,UTP Task Management Request List Base Address"
line.long 0x04 "UFS_UTMRLBAU,UTP Task Management Request List Base Address Upper 32-bits Register Note: This register is only used when the host is configured to use a 64-bit address bus"
line.long 0x08 "UFS_UTMRLDBR,UTP Task Management Request List Door Bell Register"
hexmask.long.byte 0x08 0.--7. 1. "UTMRLDBR,UTP Task Management Request List Doorbell Register"
line.long 0x0C "UFS_UTMRLCLR,UTP Task Management Request List Clear Register"
hexmask.long.byte 0x0C 0.--7. 1. "UTMRLCLR,UTP Task Management List Clear Register"
line.long 0x10 "UFS_UTMRLRSR,- UTP Task Management Request List Run Stop Register"
bitfld.long 0x10 0. "UTMRLRSR,UTP Task Management Request List Run-Stop Register" "0,1"
group.long 0x90++0x13
line.long 0x00 "UFS_UICCMD,UIC Command Register Sending the DME_ENABLE UIC command is not permitted since this will be done automatically during the UFS host controller initialization"
hexmask.long.byte 0x00 0.--7. 1. "CMDOP,Command Opcode"
line.long 0x04 "UFS_UICCMDARG1,UIC Command Argument 1 Register MIBattribute: Indicates the ID of the attribute of the requested"
line.long 0x08 "UFS_UICCMDARG2,UIC Command Argument 2 Register AttrSetType: Indicates whether the attribute value (AttrSet = NORMAL) or the attribute non-volatile reset value (STATIC) setting is requested"
line.long 0x0C "UFS_UICCMDARG3,UIC Command Argument 3 Register MIBvalue_R: Indicates the value of the attribute as returned by the UIC command returned"
line.long 0x10 "UFS_SYSTHRTL,SYS Throttling Register In case of heavy data traffic. the UFS host controller might not leave sufficient bandwidth of the OCP/AXI fabric for other peripheral"
hexmask.long.word 0x10 16.--24. 1. "MAXOSYSRW,Max Outstanding SYS Write Requests (AXI Only)"
hexmask.long.byte 0x10 8.--15. 1. "MAXOSYSRR,Max Outstanding SYS Read Requests"
hexmask.long.byte 0x10 0.--7. 1. "SYSDLY,SYS Delay"
group.long 0xAC++0x03
line.long 0x00 "UFS_HCI_MMIO_TOSH_UNIRESPOL,UniPro Reset Polling Register"
bitfld.long 0x00 0. "RESPOL,UniPro Reset Polling" "0,1"
rgroup.long 0xC4++0x27
line.long 0x00 "UFS_OSYSR,Outstanding SYS Requests Register"
bitfld.long 0x00 6.--11. "OSYSW,Outstanding SYS Write Requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "OSYSR,Outstanding SYS Read Requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UFS_XCNF,Extended Configuration Register"
bitfld.long 0x04 16.--17. "PCPCONFEX,Peer C-Port Configuration Extended" "0,1,2,3"
bitfld.long 0x04 14.--15. "DSGM,Deep-Sleep Generation Mode" "0,1,2,3"
bitfld.long 0x04 12. "CAPWREN,Capability Register Write Enable" "0,1"
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bitfld.long 0x04 10. "MHSDIS,MHSDIS" "0,1"
bitfld.long 0x04 3.--7. "MCLKGE,Module Clock Gating Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 2. "AXIIDS,AXI ID support" "0,1"
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bitfld.long 0x04 1. "DSE,Deep Sleep Enable" "0,1"
bitfld.long 0x04 0. "XRSE,Extended Register Space Enable" "0,1"
line.long 0x08 "UFS_ADSIT,Auto-Deep-Sleep Idle Timer Register UFS utilizes UniPro and SCSI standards as its power management framework"
bitfld.long 0x08 10.--12. "TS,Time Scale" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x08 0.--9. 1. "ADSTV,Auto-Deep-Sleep Idle Timer Value"
line.long 0x0C "UFS_CDACFG,C-Port Direct Access Configuration Register This register configures and manages the basic functionality of this feature"
bitfld.long 0x0C 28. "CDAEN,C-Port Direct Access Enable" "0,1"
bitfld.long 0x0C 16. "CDAEOM,C-Port Direct Access" "0,1"
hexmask.long.byte 0x0C 8.--15. 1. "CDABE,C-Port Direct Access Byte Enables"
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hexmask.long.byte 0x0C 0.--7. 1. "CDABES,C-Port Direct Access Shadow Byte Enables"
line.long 0x10 "UFS_CDATX1,C-Port Direct Access Transmit 1 Register This register takes the lower 32 bit of the 64-bit data word to be transferred"
hexmask.long.byte 0x10 24.--31. 1. "CDATX1B4,CDATX1B"
hexmask.long.byte 0x10 16.--23. 1. "CDATX1B5,CDATX1B"
hexmask.long.byte 0x10 8.--15. 1. "CDATX1B6,CDATX1B"
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hexmask.long.byte 0x10 0.--7. 1. "CDATX1B7,CDATX1B"
line.long 0x14 "UFS_CDATX2,C-Port Direct Access Transmit 2 Register This register takes the lower 32 bit of the 64-bit data word to be transferred"
hexmask.long.byte 0x14 24.--31. 1. "CDATX2B0,CDATX2B"
hexmask.long.byte 0x14 16.--23. 1. "CDATX2B1,CDATX2B"
hexmask.long.byte 0x14 8.--15. 1. "CDATX2B2,CDATX2B"
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hexmask.long.byte 0x14 0.--7. 1. "CDATX2B3,CDATX2B"
line.long 0x18 "UFS_CDARX1,C-Port Direct Access Receive 1 Register This register takes the lower 32 bit of the received 64-bit data word in case of a 64-bit system bus configuration"
hexmask.long.byte 0x18 24.--31. 1. "CDARX1B4,CDARX1B"
hexmask.long.byte 0x18 16.--23. 1. "CDARX1B5,CDARX1B"
hexmask.long.byte 0x18 8.--15. 1. "CDARX1B6,CDARX1B"
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hexmask.long.byte 0x18 0.--7. 1. "CDARX1B7,CDARX1B"
line.long 0x1C "UFS_CDARX2,C-Port Direct Access Receive 2 Register This register takes the upper 32 bit of the received 64-bit data word"
hexmask.long.byte 0x1C 24.--31. 1. "CDARX2B0,CDARX2B"
hexmask.long.byte 0x1C 16.--23. 1. "CDARX2B1,CDARX2B"
hexmask.long.byte 0x1C 8.--15. 1. "CDARX2B2,CDARX2B"
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hexmask.long.byte 0x1C 0.--7. 1. "CDARX2B3,CDARX2B"
line.long 0x20 "UFS_CDASTA,C-Port Direct Access Status Register This register contains status information related to the last transfer"
bitfld.long 0x20 20.--22. "CDARES,C-Port Direct Access Result" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 19. "CDABUSY,C-Port Direct Access Busy" "0,1"
bitfld.long 0x20 18. "CDASTA,C-Port Direct Access Status" "0,1"
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bitfld.long 0x20 17. "CDAEOM,C-Port Direct Access EOM" "0,1"
bitfld.long 0x20 16. "CDASOM,C-Port Direct Access SOM" "0,1"
hexmask.long.byte 0x20 8.--15. 1. "CDABE,C-Port Direct Access Byte Enable"
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hexmask.long.byte 0x20 0.--7. 1. "CDASBE,C-Port Direct Access Shadow Byte Enable"
line.long 0x24 "UFS_XASB,Extended Address Space Base Register"
bitfld.long 0x24 8.--13. "PEP,Pseudo Error Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 0.--5. "XDP,Extended Debug Page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF0++0x17
line.long 0x00 "UFS_LBMCFG,UPIU Loopback Configuration Register"
bitfld.long 0x00 16.--19. "BEP,Byte Enable Pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "BEPS,Byte Enable Pattern Selection" "0,1"
bitfld.long 0x00 11.--14. "TRTLDV,Throttle Divide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "MRTTE,Multi RTT Enable" "0,1"
bitfld.long 0x00 9. "LBME,Loopback Enable bit" "0,1"
bitfld.long 0x00 5.--8. "PDSIZE,Data Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4. "USDLY,UPIU Source Delay" "0,1"
bitfld.long 0x00 0.--3. "UDLY,UPIU Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "UFS_LBMSTA,UPIU Loopback Status Register"
bitfld.long 0x04 0. "ERR,Error Indicator" "0,1"
line.long 0x08 "UFS_DBG,Debug Register"
bitfld.long 0x08 16.--17. "HCIER,Host Controller Internal Error Register" "0,1,2,3"
hexmask.long.word 0x08 0.--15. 1. "HCSTATE,Host Controller State"
line.long 0x0C "UFS_HCLKDIV,Host Clock Divider Register Note: This register configures the Tick1us clock required by UniPro"
hexmask.long.word 0x0C 0.--15. 1. "HCLKDIV,Host Clock Divide"
line.long 0x10 "UFS_CCAP,Crypto Capabilities Register"
hexmask.long.byte 0x10 24.--31. 1. "CFGPTR,Configuration Array Pointer"
hexmask.long.byte 0x10 8.--15. 1. "CFGC,Configuration Count"
hexmask.long.byte 0x10 0.--7. 1. "CC,Crypto Capabilities"
line.long 0x14 "UFS_CRYPTOCAP,Crypto Capability X Register"
hexmask.long.byte 0x14 16.--23. 1. "KS,Key Size"
hexmask.long.byte 0x14 8.--15. 1. "SDUSB,Supported Data Unit Size Bitmask"
hexmask.long.byte 0x14 0.--7. 1. "ALGID,Algorithm"
group.long 0x500++0x0F
line.long 0x00 "UFS_CRYPTOCFG0,Crypto Configuration 0 Register"
line.long 0x04 "UFS_CRYPTOCFG1,Crypto Configuration 1 Register"
line.long 0x08 "UFS_CRYPTOCFG2,Crypto Configuration 2 Register"
line.long 0x0C "UFS_CRYPTOCFG3,Crypto Configuration 3 Register"
group.long 0x540++0x07
line.long 0x00 "UFS_CRYPTOCFG16,Crypto Configuration 16 Register"
bitfld.long 0x00 31. "CFGE,Configuration Enable" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "CAPIDX,Crypto Capability Index"
hexmask.long.byte 0x00 0.--7. 1. "DUSIZE,Data Unit Size"
line.long 0x04 "UFS_CRYPTOCFG17,Crypto Configuration 17 Register"
hexmask.long.word 0x04 16.--31. 1. "VSB,Vendor-Specific Bits"
group.long 0x580++0x0F
line.long 0x00 "UFS_CRYPTOCFG32,Crypto Configuration 0 for Second Crypto Configuration Register"
line.long 0x04 "UFS_CRYPTOCFG33,Crypto Configuration 1 for Second Crypto Configuration Register"
line.long 0x08 "UFS_CRYPTOCFG34,Crypto Configuration 2 for Second Crypto Configuration Register"
line.long 0x0C "UFS_CRYPTOCFG35,Crypto Configuration 3 for Second Crypto Configuration Register"
group.long 0x5C0++0x07
line.long 0x00 "UFS_CRYPTOCFG48,Crypto Configuration 16 for Second Crypto Configuration Register"
bitfld.long 0x00 31. "CFGE1,Configuration Enable for second crypto configuration" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "CAPIDX1,Crypto Capability Index for second crypto configuration"
hexmask.long.byte 0x00 0.--7. 1. "DUSIZE1,Data Unit Size for second crypto configuration"
line.long 0x04 "UFS_CRYPTOCFG49,Crypto Configuration 17 for Second Crypto Configuration Register"
hexmask.long.word 0x04 16.--31. 1. "VSB1,Vendor-Specific Bits for Second Crypto Configuration"
group.long 0x1000++0x13
line.long 0x00 "UFS_ASF_INT_STATUS,ASF Interrupt Status Register This register indicates the source of ASF interrupts"
bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
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bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "UFS_ASF_INT_RAW_STATUS,ASF Interrupt Raw Status Register A bit set in this raw register indicates a source of ASF fault in the corresponding feature"
bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
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bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "UFS_ASF_INT_MASK,ASF Interrupt Mask Register The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked"
bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
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bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "UFS_ASF_INT_TEST,ASF Interrupt Test Register The ASF interrupt test register emulate hardware even"
bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
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bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "UFS_ASF_FATAL_NONFATAL_SELECT,Fatal or Non-Fatal Interrupt Register The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered"
bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
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bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x1020++0x0B
line.long 0x00 "UFS_ASF_SRAM_CORR_FAULT_STATUS,Status Register for SRAM Correctable Fault Register This captures all SRAM ECC Correctable Errors"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,This encoding indicates which SRAM Instance has a Correctable Fault"
hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,This indicates the address where the Correctable fault was observed"
line.long 0x04 "UFS_ASF_SRAM_UNCORR_FAULT_STATUS,Status Register (For SRAM Uncorrectable Fault) This captures all SRAM ECC UnCorrectable Errors"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,This encoding indicates which SRAM Instance has a UnCorrectable Fault"
hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,This indicates the address where the UnCorrectable fault was observed"
line.long 0x08 "UFS_ASF_SRAM_FAULT_STATS,Statistics Register (For SRAM Faults) Note that this register clears when software writes to any field"
hexmask.long.word 0x08 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS,Count of number of uncorrectable errors if implemented"
hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x1030++0x0B
line.long 0x00 "UFS_ASF_TRANS_TO_CTRL,Control Register (To Configure The ASF Transaction Timeout Monitors)"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Reserved"
line.long 0x04 "UFS_ASF_TRANS_TO_FAULT_MASK,Control Register (To Mask Out ASF Transaction Timeout Faults From Triggering Interrupts) On reset. all bits are set to mask out all sources"
bitfld.long 0x04 2. "TCX_REPL_TMR_MASK,TCx_REPLAY_TIMER_EXPIRED mask" "0,1"
bitfld.long 0x04 1. "AFCX_REQ_TMR_MASK,AFCx_REQUEST_TIMER_EXPIRED mask" "0,1"
bitfld.long 0x04 0. "FCX_PROT_TMR_MASK,FCx_PROTECTION_TIMER_EXPIRED mask" "0,1"
line.long 0x08 "UFS_ASF_TRANS_TO_FAULT_STATUS,Status Register (For Transaction Timeouts Fault) Status register for transaction timeouts fault"
bitfld.long 0x08 2. "TCX_REPL_TMR_ERR,TCx_REPLAY_TIMER_EXPIRED timeout detected" "0,1"
bitfld.long 0x08 1. "AFCX_REQ_TMR_ERR,AFCx_REQUEST_TIMER_EXPIRED timeout detected" "0,1"
bitfld.long 0x08 0. "FCX_PROT_TMR_ERR,FCx_PROTECTION_TIMER_EXPIRED timeout detected" "0,1"
group.long 0x1040++0x07
line.long 0x00 "UFS_ASF_PROTOCOL_FAULT_MASK,Control Register (To Mask Out ASF Protocol Faults From Triggering Interrupts) On reset. all bits are set to mask out all sources"
bitfld.long 0x00 11. "PA_IND_RCV_MASK,When set to 1h disables the UniPro PA_ERROR_IND_RECEIVED" "0,1"
bitfld.long 0x00 10. "PA_INT_MASK,When set to 1h disables the UniPro PA_INIT_ERROR" "0,1"
bitfld.long 0x00 9. "BAD_CTRL_S_MASK,When set to 1h disables the UniPro BAD_CTRL_SYMBOL_TYPE" "0,1"
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bitfld.long 0x00 8. "FRM_S_MASK,When set to 1h disables the UniPro FRAME_SYNTAX_ERROR" "0,1"
bitfld.long 0x00 7. "EOF_S_MASK,When set to 1h disables the UniPro EOF_SYNTAX_ERROR" "0,1"
bitfld.long 0x00 6. "NAC_F_S_MASK,When set to 1h disables the UniPro NAC_FRAME_SYNTAX_ERROR" "0,1"
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bitfld.long 0x00 5. "AFC_F_S_MASK,When set to 1h disables the UniPro AFC_FRAME_SYNTAX_ERROR" "0,1"
bitfld.long 0x00 4. "WSQ_NO_MASK,When set to 1h disables the UniPro WRONG_SEQUENCE_NUMBER" "0,1"
bitfld.long 0x00 3. "MFL_EX_MASK,When set to 1h disables the UniPro MAX_FRAME_LENGTH_EXCEEDED" "0,1"
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bitfld.long 0x00 2. "RXBUG_OF_MASK,When set to 1h disables the UniPro RX_BUFFER_OVERFLOW" "0,1"
bitfld.long 0x00 1. "CRC_ERR_MASK,When set to 1h disables the UniPro CRC_ERROR" "0,1"
bitfld.long 0x00 0. "NAC_RCV_MASK,When set to 1h disables the UniPro NAC_RECEIVED" "0,1"
line.long 0x04 "UFS_ASF_PROTOCOL_FAULT_STATUS,Status Register (For Protocol Faults) If a fault occurs the relevant status bit will be set to 1h"
bitfld.long 0x04 11. "PA_IND_RCV_ERR,UniPro PA_ERROR_IND_RECEIVED reported" "0,1"
bitfld.long 0x04 10. "PA_INT_ERR,UniPro PA_INIT_ERROR reported" "0,1"
bitfld.long 0x04 9. "BAD_CTRL_S_ERR,UniPro BAD_CTRL_SYMBOL_TYPE reported" "0,1"
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bitfld.long 0x04 8. "FRM_S_ERR,UniPro FRAME_SYNTAX_ERROR reported" "0,1"
bitfld.long 0x04 7. "EOF_S_ERR,UniPro EOF_SYNTAX_ERROR reported" "0,1"
bitfld.long 0x04 6. "NAC_F_S_ERR,UniPro NAC_FRAME_SYNTAX_ERROR reported" "0,1"
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bitfld.long 0x04 5. "AFC_F_S_ERR,UniPro AFC_FRAME_SYNTAX_ERROR reported" "0,1"
bitfld.long 0x04 4. "WSQ_NO_ERR,UniPro WRONG_SEQUENCE_NUMBER reported" "0,1"
bitfld.long 0x04 3. "MFL_EX_ERR,UniPro MAX_FRAME_LENGTH_EXCEEDED reported" "0,1"
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bitfld.long 0x04 2. "RXBUG_OF_ERR,UniPro RX_BUFFER_OVERFLOW reported" "0,1"
bitfld.long 0x04 1. "CRC_ERR_ERR,UniPro CRC_ERROR reported" "0,1"
bitfld.long 0x04 0. "NAC_RCV_ERR,UniPro NAC_RECEIVED reported" "0,1"
group.long 0x1058++0x03
line.long 0x00 "UFS_ASF_INTEGRITY_ERR_INJ,ASF Integrity Test Register Write one to the enable register inject error to individual n-bit (trigger asf integrity fail to the IP Fault Logging and Reporting module)"
bitfld.long 0x00 15. "ASF_INTEGRITY_ERR_INJ_EN,Enable integrity error injection" "0,1"
hexmask.long.word 0x00 0.--14. 1. "ASF_INTEGRITY_ERR_INJ_NUM,Bit number at which error is injected"
rgroup.long 0x1100++0x33
line.long 0x00 "UFS_MAG_NUM,Magic Number Register"
line.long 0x04 "UFS_MPHYSTAT_XCFGO1,Output Debug Bits For PHY 1 Register"
line.long 0x08 "UFS_MPHYSTAT_XCFGO2,Output Debug Bits For PHY 2 Register"
line.long 0x0C "UFS_MPHYSTAT_XCFGO3,Output Debug Bits For PHY 3 Register"
line.long 0x10 "UFS_MPHYSTAT_XCFGO4,Output Debug Bits For PHY 4 Register"
line.long 0x14 "UFS_MPHYSTAT_XCFGO5,Output Debug Bits For PHY 5 Register"
line.long 0x18 "UFS_MPHYSTAT_XCFGO6,Output Debug Bits For PHY 6 Register"
line.long 0x1C "UFS_MPHYSTAT_XCFGO7,Output Debug Bits For PHY 7 Register"
line.long 0x20 "UFS_MPHYSTAT_XCFGO8,Output Debug Bits For PHY 8 Register"
line.long 0x24 "UFS_MPHYSTAT_XCFGO9,Output Debug Bits For PHY 9 Register"
line.long 0x28 "UFS_MPHY_DEBUG_OUT,M-PHY Debug Out Register"
line.long 0x2C "UFS_MPHY_BIST,BIST pattern check passed for Lane 0 and Lane 1"
line.long 0x30 "UFS_MPHY_SF,Safety Register"
hgroup.long 0x1134++0x03
hide.long 0x00 "UFS_MPHYSTAT,MPHY Status Register"
group.long 0x1138++0x5B
line.long 0x00 "UFS_MPHY_MMIO_A,M-PHY Configuration - MMIO Access Register"
bitfld.long 0x00 0. "MMIO_A,This bit is read" "0,1"
line.long 0x04 "UFS_MPHYCFG_XCFGD1,M-PHY Configuration For Digital Part 1 Register"
line.long 0x08 "UFS_MPHYCFG_XCFGD2,M-PHY Configuration For Digital Part 2 Register"
line.long 0x0C "UFS_MPHYCFG_XCFGD3,M-PHY Configuration For Digital Part 3 Register"
line.long 0x10 "UFS_MPHYCFG_XCFGD4,M-PHY Configuration For Digital Part 4 Register"
line.long 0x14 "UFS_MPHYCFG_XCFGD5,M-PHY Configuration For Digital Part 5 Register"
bitfld.long 0x14 0.--4. "MPHYCFG_XCFGD5,This field is read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "UFS_MPHYCFG_XCFGA1,M-PHY Configuration For Analog Part 1 Register"
line.long 0x1C "UFS_MPHYCFG_XCFGA2,M-PHY Configuration For Analog Part 2 Register"
line.long 0x20 "UFS_MPHYCFG_XCFGA3,M-PHY Configuration For Analog Part 3 Register"
line.long 0x24 "UFS_MPHYCFG_XCFGA4,M-PHY Configuration For Analog Part 4 Register"
line.long 0x28 "UFS_MPHYCFG_XCFGA5,M-PHY Configuration For Analog Part 5 Register"
line.long 0x2C "UFS_MPHYCFG_XCFGA6,M-PHY Configuration For Analog Part 6 Register"
line.long 0x30 "UFS_MPHYCFG_XCFGA7,M-PHY Configuration For Analog Part 7 Register"
line.long 0x34 "UFS_MPHYCFG_XCFGA8,M-PHY Configuration For Analog Part 8 Register"
line.long 0x38 "UFS_MPHYCFG_XCFGA9,M-PHY Configuration For Analog Part 9 Register"
line.long 0x3C "UFS_MPHYCFG_XCFGA10,M-PHY Configuration For Analog Part 10 Register"
line.long 0x40 "UFS_MPHYCFG_XCFGA11,M-PHY Configuration For Analog Part 11 Register"
line.long 0x44 "UFS_MPHYCFG_XCFGA12,M-PHY Configuration For Analog Part 12 Register"
line.long 0x48 "UFS_MPHYCFG_XCFGA13,M-PHY Configuration For Analog Part 13 Register"
line.long 0x4C "UFS_MPHYCFG_MISC,M-PHY MISC Configuration Register"
bitfld.long 0x4C 29. "CMN_MPX_EN_MMIO,Special debug mode for PLL/CDR" "0,1"
bitfld.long 0x4C 26.--28. "CMN_MPX_SEL_MMIO,Special debug mode for PLL/CDR" "0,1,2,3,4,5,6,7"
bitfld.long 0x4C 25. "TX0_TEST_15_MMIO,Special debug mode for PLL/CDR" "0,1"
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bitfld.long 0x4C 24. "TX1_TEST_15_MMIO,Special debug mode for PLL/CDR" "0,1"
bitfld.long 0x4C 17. "REFCLK_NOGATED,This bit is read" "0,1"
bitfld.long 0x4C 15.--16. "REFCLK_FREQ_SEL,This field is read" "0,1,2,3"
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bitfld.long 0x4C 12. "TX_DEEP_STALL_EN,This bit is read" "0,1"
bitfld.long 0x4C 11. "RX_DEEP_STALL_EN,This bit is read" "0,1"
hexmask.long.byte 0x4C 0.--6. 1. "DEBUG_SEL,This field is read"
line.long 0x50 "UFS_MPHYCFG_VCONTROL,M-PHY VCONTROL Configuration Register"
bitfld.long 0x50 16. "VCONTROL_LA_SA_SEL,This bit is read" "0,1"
bitfld.long 0x50 10.--11. "VCONTROL_DEEMP_SEL,This field is read" "0,1,2,3"
hexmask.long.word 0x50 0.--9. 1. "VCONTROL,This field is read"
line.long 0x54 "UFS_MPHY_BIST_CTRLPIN,M-PHY BIST Control Pins Register"
line.long 0x58 "UFS_MPHY_SF_WD,M-PHY Safety Related Watch Dog Register"
bitfld.long 0x58 2. "SF_PLL_WATCHDOG_EN_MMIO,This bit is read" "0,1"
bitfld.long 0x58 1. "SF_CDR0_WATCHDOG_EN_MMIO,This bit is read" "0,1"
bitfld.long 0x58 0. "SF_CDR1_WATCHDOG_EN_MMIO,This bit is read" "0,1"
tree.end
tree.end
tree "UFS0_SYSCFG_SS_CFG"
tree "UFS0_SYSCFG_SS_CFG"
base ad:0x4E80000
rgroup.long 0x00++0x07
line.long 0x00 "UFS_SS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Register Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "UFS_SS_CTRL,The Control Register contains general control bits for the module"
bitfld.long 0x04 4.--5. "MPHY_REFCLK_FREQ_SEL,Reference Clock Frequency Selection" "19.2 MHz,26 MHz,Reserved,Reserved"
bitfld.long 0x04 2.--3. "MPHY_VCONTROL_DEEMP_SEL,M-PHY De-Emphasis Select" "No De-Emphasis,De-Emphasis,?..."
bitfld.long 0x04 1. "MPHY_VCONTROL_LA_SA_SEL,M-PHY Amplitude Select" "Small Amplitude,Large Amplitude"
bitfld.long 0x04 0. "RST_N_PCS,Active Low Reset to UFS Slave Device" "0,1"
tree.end
tree.end
tree "USB3P0SS_MMR_MMRVBP_USBSS_CMN"
tree "USB0_MMR_MMRVBP_USBSS_CMN"
base ad:0x4104000
rgroup.long 0x00++0x0F
line.long 0x00 "USB3P0SS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Rregister scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "USB3P0SS_W1,Wrapper register containing soft reset. mode selection. and overcurrent indicator"
bitfld.long 0x04 19. "USB2_ONLY_MODE,Selects USB2 only mode" "0,1"
bitfld.long 0x04 17.--18. "MODESTRAP,Modestrap input to the Controller" "0,1,2,3"
bitfld.long 0x04 16. "OVERCURRENT_N,Overcurrent indicator to the controller" "0,1"
bitfld.long 0x04 9. "MODESTRAP_SEL,This bit has to be always set to 1" "0,1"
bitfld.long 0x04 8. "OVERCURRENT_SEL,Overcurrent select" "0,1"
bitfld.long 0x04 0. "PWRUP_RST_N,Power up reset for the controller" "0,1"
line.long 0x08 "USB3P0SS_STATIC_CONFIG,Wrapper register containing static settings"
bitfld.long 0x08 5.--8. "PLL_REF_SEL,Indicates the frequency of the REF_CLOCK input used by the USB PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 1.--2. "VBUS_SEL,VBUS select" "0,1,2,3"
bitfld.long 0x08 0. "LANE_REVERSE,USB2PHY D+/D- reverse selection" "0,1"
line.long 0x0C "USB3P0SS_PHY_TEST,Register containing PLL bypass select. BIST control and status"
bitfld.long 0x0C 17. "BIST_MODE,Set for bist mode" "0,1"
hexmask.long.byte 0x0C 9.--16. 1. "BIST_ERROR_COUNT,Number of bytes that have errors while running BIST"
rbitfld.long 0x0C 8. "BIST_ERROR,If set this bit indicates that BIST completed with error" "0,1"
rbitfld.long 0x0C 7. "BIST_COMPLETE,If set this bit indicates that the BIST operation is completed" "0,1"
bitfld.long 0x0C 6. "BIST_ON,Setting this bit starts the BIST operation" "0,1"
bitfld.long 0x0C 5. "BIST_MODE_EN,BIST Mode Enable" "0,1"
newline
bitfld.long 0x0C 1.--4. "BIST_MODE_SEL,BIST Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "USB3P0SS_DEVICE_CTRL,Register for device control"
bitfld.long 0x00 0. "DEV_WAKEUP,Set this bit to trigger device wakeup interrupt on IRQ[7]" "0,1"
tree.end
tree "USB1_MMR_MMRVBP_USBSS_CMN"
base ad:0x4114000
rgroup.long 0x00++0x0F
line.long 0x00 "USB3P0SS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,Rregister scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "USB3P0SS_W1,Wrapper register containing soft reset. mode selection. and overcurrent indicator"
bitfld.long 0x04 19. "USB2_ONLY_MODE,Selects USB2 only mode" "0,1"
bitfld.long 0x04 17.--18. "MODESTRAP,Modestrap input to the Controller" "0,1,2,3"
bitfld.long 0x04 16. "OVERCURRENT_N,Overcurrent indicator to the controller" "0,1"
bitfld.long 0x04 9. "MODESTRAP_SEL,This bit has to be always set to 1" "0,1"
bitfld.long 0x04 8. "OVERCURRENT_SEL,Overcurrent select" "0,1"
bitfld.long 0x04 0. "PWRUP_RST_N,Power up reset for the controller" "0,1"
line.long 0x08 "USB3P0SS_STATIC_CONFIG,Wrapper register containing static settings"
bitfld.long 0x08 5.--8. "PLL_REF_SEL,Indicates the frequency of the REF_CLOCK input used by the USB PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 1.--2. "VBUS_SEL,VBUS select" "0,1,2,3"
bitfld.long 0x08 0. "LANE_REVERSE,USB2PHY D+/D- reverse selection" "0,1"
line.long 0x0C "USB3P0SS_PHY_TEST,Register containing PLL bypass select. BIST control and status"
bitfld.long 0x0C 17. "BIST_MODE,Set for bist mode" "0,1"
hexmask.long.byte 0x0C 9.--16. 1. "BIST_ERROR_COUNT,Number of bytes that have errors while running BIST"
rbitfld.long 0x0C 8. "BIST_ERROR,If set this bit indicates that BIST completed with error" "0,1"
rbitfld.long 0x0C 7. "BIST_COMPLETE,If set this bit indicates that the BIST operation is completed" "0,1"
bitfld.long 0x0C 6. "BIST_ON,Setting this bit starts the BIST operation" "0,1"
bitfld.long 0x0C 5. "BIST_MODE_EN,BIST Mode Enable" "0,1"
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bitfld.long 0x0C 1.--4. "BIST_MODE_SEL,BIST Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "USB3P0SS_DEVICE_CTRL,Register for device control"
bitfld.long 0x00 0. "DEV_WAKEUP,Set this bit to trigger device wakeup interrupt on IRQ[7]" "0,1"
tree.end
tree.end
tree "USB_ECC_AGGR_CFG"
tree "USB0_ECC_AGGR"
base ad:0x2A13000
rgroup.long 0x00++0x03
line.long 0x00 "USB_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "USB_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "USB_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "USB_RESERVED_SVBUS_y,Offset = 10h + (y * 4h); where y = 0h to 7h"
group.long 0x3C++0x07
line.long 0x00 "USB_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "USB_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "USB_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "USB_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "USB_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "USB_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "USB_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "USB_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "USB_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "USB_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "USB_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "USB_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "USB1_ECC_AGGR"
base ad:0x2A16000
rgroup.long 0x00++0x03
line.long 0x00 "USB_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "USB_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "USB_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "USB_RESERVED_SVBUS_y,Offset = 10h + (y * 4h); where y = 0h to 7h"
group.long 0x3C++0x07
line.long 0x00 "USB_SEC_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "USB_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "USB_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "USB_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "USB_DED_EOI_REG,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "USB_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RAMECC_PEND,Interrupt Pending Status for ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "USB_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_SET,Interrupt Enable Set Register for ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "USB_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "USB_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "USB_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "USB_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "USB_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "USB_RAMS_INJ_CFG"
tree "USB0_RAMS_INJ_CFG"
base ad:0x2A10000
rgroup.long 0x00++0x0B
line.long 0x00 "USB_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "USB_INFO,The Info Register gives the configuration Inforrmation of this module"
bitfld.long 0x04 0.--5. "ENDPOINTS,Total number of Targets supported by this configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "USB_SFT_RST,The Global Soft Reset Register clears all programmable registers and returns the injector to idle state"
bitfld.long 0x08 0.--3. "KEY,Write 4'b1010 to issue a soft reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x13
line.long 0x00 "USB_BIT1,This register defines the first bit to be flipped when injection is enabled"
hexmask.long.word 0x00 0.--15. 1. "BIT1,First bit to be flipped on an error injection"
line.long 0x04 "USB_BIT2,This register defines the second bit to be flipped if 2-bit injection is enabled"
hexmask.long.word 0x04 0.--15. 1. "BIT2,Second bit to be flipped on an error injection if"
line.long 0x08 "USB_TRGT,This is the target selection register"
bitfld.long 0x08 0.--4. "TRGT,Select which target to interact with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "USB_CTRL,Controls the injection"
rbitfld.long 0x0C 8.--12. "TRGT,Indicates which target is selected by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 2. "DONE,Indicates that the target selected by" "0,1"
bitfld.long 0x0C 1. "TWOBIT,Write 1 to trigger a 2-bit error in target selected by" "0,1"
bitfld.long 0x0C 0. "ONEBIT,Write 1 to trigger a 1-bit error in target selected by" "0,1"
line.long 0x10 "USB_STATUS,Controls the injection"
bitfld.long 0x10 2. "ARMED,Indicates that the target selected by" "0,1"
tree.end
tree "USB1_RAMS_INJ_CFG"
base ad:0x2A17000
rgroup.long 0x00++0x0B
line.long 0x00 "USB_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "USB_INFO,The Info Register gives the configuration Inforrmation of this module"
bitfld.long 0x04 0.--5. "ENDPOINTS,Total number of Targets supported by this configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "USB_SFT_RST,The Global Soft Reset Register clears all programmable registers and returns the injector to idle state"
bitfld.long 0x08 0.--3. "KEY,Write 4'b1010 to issue a soft reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x13
line.long 0x00 "USB_BIT1,This register defines the first bit to be flipped when injection is enabled"
hexmask.long.word 0x00 0.--15. 1. "BIT1,First bit to be flipped on an error injection"
line.long 0x04 "USB_BIT2,This register defines the second bit to be flipped if 2-bit injection is enabled"
hexmask.long.word 0x04 0.--15. 1. "BIT2,Second bit to be flipped on an error injection if"
line.long 0x08 "USB_TRGT,This is the target selection register"
bitfld.long 0x08 0.--4. "TRGT,Select which target to interact with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "USB_CTRL,Controls the injection"
rbitfld.long 0x0C 8.--12. "TRGT,Indicates which target is selected by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 2. "DONE,Indicates that the target selected by" "0,1"
bitfld.long 0x0C 1. "TWOBIT,Write 1 to trigger a 2-bit error in target selected by" "0,1"
bitfld.long 0x0C 0. "ONEBIT,Write 1 to trigger a 1-bit error in target selected by" "0,1"
line.long 0x10 "USB_STATUS,Controls the injection"
bitfld.long 0x10 2. "ARMED,Indicates that the target selected by" "0,1"
tree.end
tree.end
tree "VIM"
tree "ARMSS_VIC_CFG"
base ad:0xFF80000
rgroup.long 0x00++0x27
line.long 0x00 "VIM_PID,This register contains the major and minor revisions for the module"
line.long 0x04 "VIM_INFO,This contains information about the configuration of the VIM"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM"
line.long 0x08 "VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x08 16.--19. "PRI,This field indicates the priority of the pending IRQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority"
line.long 0x0C "VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x0C 16.--19. "PRI,This field indicates the priority of the pending FIQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority"
line.long 0x10 "VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts"
line.long 0x14 "VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts"
line.long 0x18 "VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by"
line.long 0x1C "VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by"
line.long 0x20 "VIM_ACTIRQ,This register contains the number of the active IRQ"
bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x20 16.--19. "PRI,This field indicates the priority of the active IRQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt"
line.long 0x24 "VIM_ACTFIQ,This register contains the number of the active FIQ"
bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x24 16.--19. "PRI,This field indicates the priority of the active FIQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt"
group.long 0x30++0x03
line.long 0x00 "VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors"
hexmask.long 0x00 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses"
group.long 0x400++0x1F
line.long 0x00 "VIM_RAW_j,This register indicates the raw status of the events in group M"
line.long 0x04 "VIM_STS_j,This register indicates the masked status of the events in group M"
line.long 0x08 "VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M"
line.long 0x0C "VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M"
line.long 0x10 "VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs"
line.long 0x14 "VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs"
line.long 0x18 "VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ"
line.long 0x1C "VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source"
group.long 0x1000++0x03
line.long 0x00 "VIM_PRI_INT_j,This register is used to set the priority of interrupt Q"
bitfld.long 0x00 0.--3. "VAL,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x03
line.long 0x00 "VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q"
hexmask.long 0x00 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q"
tree.end
tree "MCU_ARMSS_VIC_CFG"
base ad:0x40F80000
rgroup.long 0x00++0x27
line.long 0x00 "VIM_PID,This register contains the major and minor revisions for the module"
line.long 0x04 "VIM_INFO,This contains information about the configuration of the VIM"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM"
line.long 0x08 "VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x08 16.--19. "PRI,This field indicates the priority of the pending IRQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority"
line.long 0x0C "VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x0C 16.--19. "PRI,This field indicates the priority of the pending FIQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority"
line.long 0x10 "VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts"
line.long 0x14 "VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts"
line.long 0x18 "VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by"
line.long 0x1C "VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by"
line.long 0x20 "VIM_ACTIRQ,This register contains the number of the active IRQ"
bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x20 16.--19. "PRI,This field indicates the priority of the active IRQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt"
line.long 0x24 "VIM_ACTFIQ,This register contains the number of the active FIQ"
bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x24 16.--19. "PRI,This field indicates the priority of the active FIQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt"
group.long 0x30++0x03
line.long 0x00 "VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors"
hexmask.long 0x00 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses"
group.long 0x400++0x1F
line.long 0x00 "VIM_RAW_j,This register indicates the raw status of the events in group M"
line.long 0x04 "VIM_STS_j,This register indicates the masked status of the events in group M"
line.long 0x08 "VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M"
line.long 0x0C "VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M"
line.long 0x10 "VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs"
line.long 0x14 "VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs"
line.long 0x18 "VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ"
line.long 0x1C "VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source"
group.long 0x1000++0x03
line.long 0x00 "VIM_PRI_INT_j,This register is used to set the priority of interrupt Q"
bitfld.long 0x00 0.--3. "VAL,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x03
line.long 0x00 "VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q"
hexmask.long 0x00 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q"
tree.end
tree.end
tree "VIRTID_CFG_MMRS"
tree "NAV_DDR0_VIRTID_CFG_MMRS"
base ad:0x30A02000
rgroup.long 0x00++0x03
line.long 0x00 "VIRTID_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "VIRTID_WINDOW_y,The VirtID for window y"
hexmask.long.word 0x00 0.--11. 1. "VIRTID,VirtID for window y"
tree.end
tree "NAV_DDR1_VIRTID_CFG_MMRS"
base ad:0x30A03000
rgroup.long 0x00++0x03
line.long 0x00 "VIRTID_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "VIRTID_WINDOW_y,The VirtID for window y"
hexmask.long.word 0x00 0.--11. 1. "VIRTID,VirtID for window y"
tree.end
tree "NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS"
base ad:0x3810000
rgroup.long 0x00++0x03
line.long 0x00 "VIRTID_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "VIRTID_WINDOW_y,The VirtID for window y"
hexmask.long.word 0x00 0.--11. 1. "VIRTID,VirtID for window y"
tree.end
tree.end
tree "VPAC_CP_INTD"
tree "VPAC0_CP_INTD_CFG_INTD_CFG"
base ad:0xF004000
rgroup.long 0x00++0x03
line.long 0x00 "VPAC_INTD_REVISION,Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,Major" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "VPAC_INTD_EOI_REG,End of Interrupt Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "VPAC_INTD_INTR_VECTOR_REG,Interrupt Vector Register"
group.long 0x100++0x13
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_0,Enable Register 0"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_1,Enable Register 1"
bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_0_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_2,Enable Register 2"
bitfld.long 0x08 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_0_en_nf_frame_done" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_3,Enable Register 3"
bitfld.long 0x0C 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_0_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x0C 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_0_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x0C 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_0_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x0C 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_0_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x0C 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_0_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_0_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x0C 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_0_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x0C 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_0_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x0C 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_0_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for level_vpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x0C 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for level_vpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x0C 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_6,Enable Set for level_vpac_out_0_en_tdone_6" "0,1"
newline
bitfld.long 0x0C 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_5,Enable Set for level_vpac_out_0_en_tdone_5" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_4,Enable Set for level_vpac_out_0_en_tdone_4" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_2,Enable Set for level_vpac_out_0_en_tdone_2" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_0,Enable Set for level_vpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x0C 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_6,Enable Set for level_vpac_out_0_en_pipe_done_6" "0,1"
newline
bitfld.long 0x0C 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_5,Enable Set for level_vpac_out_0_en_pipe_done_5" "0,1"
newline
bitfld.long 0x0C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_4,Enable Set for level_vpac_out_0_en_pipe_done_4" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for level_vpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for level_vpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for level_vpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for level_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_4,Enable Register 4"
bitfld.long 0x10 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_0_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x10 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_0_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x10 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_0_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_0_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_0_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_0_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_0_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_0_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_0_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_0_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x10 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_0_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_0_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_0_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_0_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_0_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_0_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_0_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_0_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_0_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_0_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_0_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_0_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_0_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x10 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_0_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_0_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_0_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_0_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_0_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_0_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_0_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_0_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_0_en_utc0_complete_0" "0,1"
group.long 0x11C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_7,Enable Register 7"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_CTM_PULSE,Enable Set for level_vpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_0_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_0_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_ERROR,Enable Set for level_vpac_out_0_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_ERROR,Enable Set for level_vpac_out_0_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_0,Enable Register 8"
bitfld.long 0x04 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x04 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_1,Enable Register 9"
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_1_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_2,Enable Register 10"
bitfld.long 0x0C 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_1_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_3,Enable Register 11"
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_1_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_1_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_1_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_1_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_1_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_1_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_1_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_1_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_1_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for level_vpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for level_vpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_6,Enable Set for level_vpac_out_1_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_5,Enable Set for level_vpac_out_1_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_4,Enable Set for level_vpac_out_1_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_2,Enable Set for level_vpac_out_1_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_0,Enable Set for level_vpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_6,Enable Set for level_vpac_out_1_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_5,Enable Set for level_vpac_out_1_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_4,Enable Set for level_vpac_out_1_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for level_vpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for level_vpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for level_vpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for level_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_4,Enable Register 12"
bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_1_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_1_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_1_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_1_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_1_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_1_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_1_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_1_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_1_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_1_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_1_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_1_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_1_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_1_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_1_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_1_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_1_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_1_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_1_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_1_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_1_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_1_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_1_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_1_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_1_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_1_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_1_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_1_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_1_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_1_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_1_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_1_en_utc0_complete_0" "0,1"
group.long 0x13C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_7,Enable Register 15"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_CTM_PULSE,Enable Set for level_vpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_1_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_1_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_ERROR,Enable Set for level_vpac_out_1_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_ERROR,Enable Set for level_vpac_out_1_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_0,Enable Register 16"
bitfld.long 0x04 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x04 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_1,Enable Register 17"
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_2_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_2,Enable Register 18"
bitfld.long 0x0C 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_2_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_3,Enable Register 19"
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_2_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_2_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_2_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_2_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_2_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_2_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_2_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_2_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_2_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_1,Enable Set for level_vpac_out_2_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_0,Enable Set for level_vpac_out_2_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_6,Enable Set for level_vpac_out_2_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_5,Enable Set for level_vpac_out_2_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_4,Enable Set for level_vpac_out_2_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_2,Enable Set for level_vpac_out_2_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_0,Enable Set for level_vpac_out_2_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_6,Enable Set for level_vpac_out_2_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_5,Enable Set for level_vpac_out_2_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_4,Enable Set for level_vpac_out_2_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_3,Enable Set for level_vpac_out_2_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_2,Enable Set for level_vpac_out_2_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_1,Enable Set for level_vpac_out_2_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0,Enable Set for level_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_4,Enable Register 20"
bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_2_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_2_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_2_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_2_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_2_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_2_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_2_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_2_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_2_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_2_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_2_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_2_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_2_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_2_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_2_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_2_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_2_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_2_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_2_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_2_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_2_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_2_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_2_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_2_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_2_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_2_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_2_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_2_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_2_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_2_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_2_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_2_en_utc0_complete_0" "0,1"
group.long 0x15C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_7,Enable Register 23"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_CTM_PULSE,Enable Set for level_vpac_out_2_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_2_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_2_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_ERROR,Enable Set for level_vpac_out_2_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_ERROR,Enable Set for level_vpac_out_2_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_0,Enable Register 24"
bitfld.long 0x04 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x04 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_1,Enable Register 25"
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_3_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_2,Enable Register 26"
bitfld.long 0x0C 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_3_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_3,Enable Register 27"
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_3_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_3_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_3_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_3_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_3_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_3_en_spare_pend_1_level" "0,1"
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bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_3_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_3_en_spare_pend_0_level" "0,1"
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bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_3_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_1,Enable Set for level_vpac_out_3_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_0,Enable Set for level_vpac_out_3_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_6,Enable Set for level_vpac_out_3_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_5,Enable Set for level_vpac_out_3_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_4,Enable Set for level_vpac_out_3_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_2,Enable Set for level_vpac_out_3_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_0,Enable Set for level_vpac_out_3_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_6,Enable Set for level_vpac_out_3_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_5,Enable Set for level_vpac_out_3_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_4,Enable Set for level_vpac_out_3_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_3,Enable Set for level_vpac_out_3_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_2,Enable Set for level_vpac_out_3_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_1,Enable Set for level_vpac_out_3_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_0,Enable Set for level_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_4,Enable Register 28"
bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_3_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_3_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_3_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_3_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_3_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_3_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_3_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_3_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_3_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_3_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_3_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_3_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_3_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_3_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_3_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_3_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_3_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_3_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_3_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_3_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_3_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_3_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_3_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_3_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_3_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_3_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_3_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_3_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_3_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_3_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_3_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_3_en_utc0_complete_0" "0,1"
group.long 0x17C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_7,Enable Register 31"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_CTM_PULSE,Enable Set for level_vpac_out_3_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_3_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_3_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_ERROR,Enable Set for level_vpac_out_3_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_ERROR,Enable Set for level_vpac_out_3_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_0,Enable Register 32"
bitfld.long 0x04 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_1,Enable Register 33"
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_4_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_2,Enable Register 34"
bitfld.long 0x0C 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_4_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_3,Enable Register 35"
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_4_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_4_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_4_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_4_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_4_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_4_en_spare_pend_1_level" "0,1"
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bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_4_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_4_en_spare_pend_0_level" "0,1"
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bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_4_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_1,Enable Set for level_vpac_out_4_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_0,Enable Set for level_vpac_out_4_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_6,Enable Set for level_vpac_out_4_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_5,Enable Set for level_vpac_out_4_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_4,Enable Set for level_vpac_out_4_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_2,Enable Set for level_vpac_out_4_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_0,Enable Set for level_vpac_out_4_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_6,Enable Set for level_vpac_out_4_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_5,Enable Set for level_vpac_out_4_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_4,Enable Set for level_vpac_out_4_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_3,Enable Set for level_vpac_out_4_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_2,Enable Set for level_vpac_out_4_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_1,Enable Set for level_vpac_out_4_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0,Enable Set for level_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_4,Enable Register 36"
bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_4_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_4_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_4_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_4_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_4_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_4_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_4_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_4_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_4_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_4_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_4_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_4_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_4_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_4_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_4_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_4_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_4_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_4_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_4_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_4_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_4_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_4_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_4_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_4_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_4_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_4_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_4_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_4_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_4_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_4_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_4_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_4_en_utc0_complete_0" "0,1"
group.long 0x19C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_7,Enable Register 39"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_CTM_PULSE,Enable Set for level_vpac_out_4_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_4_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_4_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_ERROR,Enable Set for level_vpac_out_4_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_ERROR,Enable Set for level_vpac_out_4_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_0,Enable Register 40"
bitfld.long 0x04 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_1,Enable Register 41"
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_2,Enable Register 42"
bitfld.long 0x0C 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_FRAME_DONE,Enable Set for level_vpac_out_5_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_3,Enable Register 43"
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_5_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_5_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_5_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_5_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_5_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_5_en_spare_pend_1_level" "0,1"
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bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_5_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_5_en_spare_pend_0_level" "0,1"
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bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_5_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_1,Enable Set for level_vpac_out_5_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_0,Enable Set for level_vpac_out_5_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_6,Enable Set for level_vpac_out_5_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_5,Enable Set for level_vpac_out_5_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_4,Enable Set for level_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_2,Enable Set for level_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_0,Enable Set for level_vpac_out_5_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_6,Enable Set for level_vpac_out_5_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_5,Enable Set for level_vpac_out_5_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_4,Enable Set for level_vpac_out_5_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_3,Enable Set for level_vpac_out_5_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_2,Enable Set for level_vpac_out_5_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_1,Enable Set for level_vpac_out_5_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_0,Enable Set for level_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_4,Enable Register 44"
bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_5_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_5_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_5_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_5_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_5_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_5_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_5_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_5_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_5_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_5_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_5_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_5_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_5_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_5_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_5_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_5_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_5_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_5_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_5_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_5_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_5_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_5_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_5_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_5_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_5_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_5_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_5_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_5_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_5_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_5_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_5_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_5_en_utc0_complete_0" "0,1"
group.long 0x1BC++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_7,Enable Register 47"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_CTM_PULSE,Enable Set for level_vpac_out_5_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_PROT_ERR,Enable Set for level_vpac_out_5_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_5_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_ERROR,Enable Set for level_vpac_out_5_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_ERROR,Enable Set for level_vpac_out_5_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_0,Enable Register 48"
bitfld.long 0x04 24. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_1,Enable Register 49"
bitfld.long 0x08 8. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_2,Enable Register 50"
bitfld.long 0x0C 10. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_0_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_3,Enable Register 51"
bitfld.long 0x10 26. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_0_en_spare_pend_1_level" "0,1"
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bitfld.long 0x10 18. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0x10 17. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_0_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_6,Enable Set for pulse_vpac_out_0_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_5,Enable Set for pulse_vpac_out_0_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_4,Enable Set for pulse_vpac_out_0_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_2,Enable Set for pulse_vpac_out_0_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_0,Enable Set for pulse_vpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_0_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_0_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_0_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_4,Enable Register 52"
bitfld.long 0x14 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_0_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_0_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_0_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_0_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_0_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_0_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_0_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_0_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_0_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_0_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_0_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_0_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_0_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_0_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_0_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_0_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_0_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_0_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_0_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_0_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_0_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_0_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_0_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_0_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_0_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_0_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_0_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_0_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_0_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_0_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_0_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_0_en_utc0_complete_0" "0,1"
group.long 0x1DC++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_7,Enable Register 55"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_0_EN_CTM_PULSE,Enable Set for pulse_vpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_0_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_0_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_0_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_0_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_0,Enable Register 56"
bitfld.long 0x04 24. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_1,Enable Register 57"
bitfld.long 0x08 8. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_2,Enable Register 58"
bitfld.long 0x0C 10. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_1_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_3,Enable Register 59"
bitfld.long 0x10 26. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_1_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_1_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_6,Enable Set for pulse_vpac_out_1_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_5,Enable Set for pulse_vpac_out_1_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_4,Enable Set for pulse_vpac_out_1_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_2,Enable Set for pulse_vpac_out_1_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_0,Enable Set for pulse_vpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_1_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_1_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_1_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_4,Enable Register 60"
bitfld.long 0x14 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_1_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_1_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_1_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_1_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_1_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_1_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_1_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_1_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_1_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_1_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_1_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_1_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_1_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_1_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_1_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_1_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_1_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_1_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_1_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_1_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_1_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_1_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_1_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_1_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_1_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_1_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_1_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_1_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_1_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_1_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_1_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_1_en_utc0_complete_0" "0,1"
group.long 0x1FC++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_7,Enable Register 63"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_1_EN_CTM_PULSE,Enable Set for pulse_vpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_1_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_1_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_1_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_1_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_0,Enable Register 64"
bitfld.long 0x04 24. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_1,Enable Register 65"
bitfld.long 0x08 8. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_2,Enable Register 66"
bitfld.long 0x0C 10. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_2_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_3,Enable Register 67"
bitfld.long 0x10 26. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_2_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_2_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_2_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_2_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_6,Enable Set for pulse_vpac_out_2_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_5,Enable Set for pulse_vpac_out_2_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_4,Enable Set for pulse_vpac_out_2_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_2,Enable Set for pulse_vpac_out_2_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_0,Enable Set for pulse_vpac_out_2_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_2_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_2_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_2_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_2_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_2_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_2_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_4,Enable Register 68"
bitfld.long 0x14 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_2_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_2_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_2_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_2_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_2_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_2_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_2_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_2_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_2_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_2_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_2_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_2_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_2_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_2_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_2_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_2_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_2_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_2_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_2_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_2_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_2_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_2_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_2_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_2_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_2_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_2_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_2_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_2_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_2_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_2_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_2_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_2_en_utc0_complete_0" "0,1"
group.long 0x21C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_7,Enable Register 71"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_2_EN_CTM_PULSE,Enable Set for pulse_vpac_out_2_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_2_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_2_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_2_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_2_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_0,Enable Register 72"
bitfld.long 0x04 24. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x04 23. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x04 9. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_1,Enable Register 73"
bitfld.long 0x08 8. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_2,Enable Register 74"
bitfld.long 0x0C 10. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_3_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_3,Enable Register 75"
bitfld.long 0x10 26. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_3_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_3_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_3_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_3_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_6,Enable Set for pulse_vpac_out_3_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_5,Enable Set for pulse_vpac_out_3_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_4,Enable Set for pulse_vpac_out_3_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_2,Enable Set for pulse_vpac_out_3_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_0,Enable Set for pulse_vpac_out_3_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_3_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_3_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_3_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_3_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_3_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_3_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_4,Enable Register 76"
bitfld.long 0x14 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_3_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_3_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_3_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_3_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_3_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_3_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_3_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_3_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_3_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_3_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_3_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_3_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_3_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_3_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_3_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_3_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_3_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_3_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_3_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_3_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_3_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_3_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_3_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_3_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_3_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_3_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_3_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_3_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_3_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_3_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_3_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_3_en_utc0_complete_0" "0,1"
group.long 0x23C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_7,Enable Register 79"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_3_EN_CTM_PULSE,Enable Set for pulse_vpac_out_3_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_3_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_3_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_3_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_3_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_0,Enable Register 80"
bitfld.long 0x04 24. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_1,Enable Register 81"
bitfld.long 0x08 8. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_2,Enable Register 82"
bitfld.long 0x0C 10. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_4_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_3,Enable Register 83"
bitfld.long 0x10 26. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_4_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_4_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_4_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_4_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_6,Enable Set for pulse_vpac_out_4_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_5,Enable Set for pulse_vpac_out_4_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_4,Enable Set for pulse_vpac_out_4_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_2,Enable Set for pulse_vpac_out_4_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_0,Enable Set for pulse_vpac_out_4_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_4_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_4_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_4_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_4_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_4_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_4_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_4,Enable Register 84"
bitfld.long 0x14 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_4_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_4_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_4_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_4_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_4_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_4_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_4_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_4_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_4_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_4_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_4_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_4_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_4_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_4_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_4_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_4_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_4_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_4_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_4_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_4_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_4_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_4_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_4_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_4_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_4_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_4_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_4_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_4_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_4_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_4_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_4_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_4_en_utc0_complete_0" "0,1"
group.long 0x25C++0x17
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_7,Enable Register 87"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_4_EN_CTM_PULSE,Enable Set for pulse_vpac_out_4_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_4_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_4_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_4_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_4_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_0,Enable Register 88"
bitfld.long 0x04 24. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 21. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x04 20. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x04 18. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x04 14. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x04 8. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_1,Enable Register 89"
bitfld.long 0x08 8. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x08 5. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_2,Enable Register 90"
bitfld.long 0x0C 10. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_FRAME_DONE,Enable Set for pulse_vpac_out_5_en_nf_frame_done" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_3,Enable Register 91"
bitfld.long 0x10 26. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_5_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_5_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_5_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_5_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_6,Enable Set for pulse_vpac_out_5_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_5,Enable Set for pulse_vpac_out_5_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_4,Enable Set for pulse_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_2,Enable Set for pulse_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_0,Enable Set for pulse_vpac_out_5_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_5_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_5_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_5_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_5_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_5_en_pipe_done_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_5_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_4,Enable Register 92"
bitfld.long 0x14 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_5_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_5_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_5_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_5_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_5_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_5_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_5_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_5_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_5_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_5_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_5_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_5_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_5_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_5_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_5_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_5_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_5_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_5_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_5_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_5_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_5_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_5_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_5_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_5_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_5_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_5_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_5_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_5_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_5_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_5_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_5_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_5_en_utc0_complete_0" "0,1"
group.long 0x27C++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_7,Enable Register 95"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_5_EN_CTM_PULSE,Enable Set for pulse_vpac_out_5_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_PROT_ERR,Enable Set for pulse_vpac_out_5_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_5_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_ERROR,Enable Set for pulse_vpac_out_5_en_utc1_error" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_5_en_utc0_error" "0,1"
group.long 0x300++0x17F
line.long 0x00 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0,Enable Clear Register 0"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x04 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_1,Enable Clear Register 1"
bitfld.long 0x04 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x04 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x08 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_2,Enable Clear Register 2"
bitfld.long 0x08 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x08 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_0_en_nf_frame_done" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x08 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x08 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x0C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_3,Enable Clear Register 3"
bitfld.long 0x0C 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x0C 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x0C 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x0C 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x0C 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x0C 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x0C 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x0C 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x0C 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x0C 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_0_en_tdone_6" "0,1"
newline
bitfld.long 0x0C 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_0_en_tdone_5" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_0_en_tdone_4" "0,1"
newline
bitfld.long 0x0C 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_0_en_tdone_2" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x0C 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_6" "0,1"
newline
bitfld.long 0x0C 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_5" "0,1"
newline
bitfld.long 0x0C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_4" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x0C 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x0C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0x10 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_4,Enable Clear Register 4"
bitfld.long 0x10 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x10 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x10 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x10 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x10 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x10 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x10 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_0" "0,1"
line.long 0x14 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_5,Enable Clear Register 5"
bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_0" "0,1"
line.long 0x18 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_6,Enable Clear Register 6"
bitfld.long 0x18 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x18 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x18 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x18 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x18 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x18 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x18 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x18 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x18 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x18 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x18 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x18 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x18 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x18 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x18 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x18 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x18 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x18 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x18 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x18 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x18 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x18 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x18 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x18 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x18 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x18 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x18 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x18 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x18 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x18 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x18 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x18 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_0_en_utc1_complete_32" "0,1"
line.long 0x1C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_7,Enable Clear Register 7"
bitfld.long 0x1C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_0_en_ctm_pulse" "0,1"
newline
bitfld.long 0x1C 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_0_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x1C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_0_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x1C 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_0_en_utc1_error" "0,1"
newline
bitfld.long 0x1C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_0_en_utc0_error" "0,1"
line.long 0x20 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0,Enable Clear Register 8"
bitfld.long 0x20 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x20 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x20 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x20 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x20 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x20 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x20 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x20 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x20 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x20 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x20 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x20 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x20 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x20 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x20 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x20 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x20 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x20 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x20 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x20 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x20 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x20 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x20 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x20 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x20 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x24 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_1,Enable Clear Register 9"
bitfld.long 0x24 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x24 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x24 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x24 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x24 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x24 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x24 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x24 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x24 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x28 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_2,Enable Clear Register 10"
bitfld.long 0x28 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x28 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x28 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_1_en_nf_frame_done" "0,1"
newline
bitfld.long 0x28 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x28 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x28 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x28 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x2C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_3,Enable Clear Register 11"
bitfld.long 0x2C 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x2C 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x2C 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x2C 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x2C 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x2C 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x2C 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x2C 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x2C 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x2C 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x2C 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x2C 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_1_en_tdone_6" "0,1"
newline
bitfld.long 0x2C 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_1_en_tdone_5" "0,1"
newline
bitfld.long 0x2C 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_1_en_tdone_4" "0,1"
newline
bitfld.long 0x2C 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_1_en_tdone_2" "0,1"
newline
bitfld.long 0x2C 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_1_en_tdone_0" "0,1"
newline
bitfld.long 0x2C 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_6" "0,1"
newline
bitfld.long 0x2C 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_5" "0,1"
newline
bitfld.long 0x2C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_4" "0,1"
newline
bitfld.long 0x2C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_3" "0,1"
newline
bitfld.long 0x2C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_2" "0,1"
newline
bitfld.long 0x2C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_1" "0,1"
newline
bitfld.long 0x2C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0x30 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_4,Enable Clear Register 12"
bitfld.long 0x30 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x30 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x30 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x30 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x30 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x30 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x30 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x30 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x30 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x30 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x30 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x30 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x30 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x30 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x30 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x30 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x30 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x30 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x30 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x30 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x30 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x30 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x30 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x30 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x30 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x30 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x30 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x30 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x30 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x30 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x30 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x30 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_0" "0,1"
line.long 0x34 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_5,Enable Clear Register 13"
bitfld.long 0x34 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x34 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x34 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x34 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x34 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x34 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x34 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x34 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x34 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x34 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x34 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x34 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x34 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x34 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x34 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x34 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x34 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x34 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x34 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x34 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x34 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x34 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x34 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x34 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x34 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x34 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x34 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x34 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x34 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x34 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x34 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x34 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_0" "0,1"
line.long 0x38 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_6,Enable Clear Register 14"
bitfld.long 0x38 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x38 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x38 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x38 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x38 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x38 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x38 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x38 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x38 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x38 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x38 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x38 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x38 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x38 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x38 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x38 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x38 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x38 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x38 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x38 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x38 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x38 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x38 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x38 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x38 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x38 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x38 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x38 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x38 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x38 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x38 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x38 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_1_en_utc1_complete_32" "0,1"
line.long 0x3C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_7,Enable Clear Register 15"
bitfld.long 0x3C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x3C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_1_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x3C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_1_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x3C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_1_en_utc1_error" "0,1"
newline
bitfld.long 0x3C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_1_en_utc0_error" "0,1"
line.long 0x40 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0,Enable Clear Register 16"
bitfld.long 0x40 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x40 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x40 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x40 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x40 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x40 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x40 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x40 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x40 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x40 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x40 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x40 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x40 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x40 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x40 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x40 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x40 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x40 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x40 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x40 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x40 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x40 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x40 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x40 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x40 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x44 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_1,Enable Clear Register 17"
bitfld.long 0x44 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x44 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x44 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x44 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x44 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x44 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x44 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x44 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x44 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x48 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_2,Enable Clear Register 18"
bitfld.long 0x48 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x48 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x48 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_2_en_nf_frame_done" "0,1"
newline
bitfld.long 0x48 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x48 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x48 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x48 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x4C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_3,Enable Clear Register 19"
bitfld.long 0x4C 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x4C 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x4C 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x4C 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x4C 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x4C 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x4C 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x4C 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x4C 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x4C 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_2_en_spare_dec_1" "0,1"
newline
bitfld.long 0x4C 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_2_en_spare_dec_0" "0,1"
newline
bitfld.long 0x4C 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_2_en_tdone_6" "0,1"
newline
bitfld.long 0x4C 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_2_en_tdone_5" "0,1"
newline
bitfld.long 0x4C 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_2_en_tdone_4" "0,1"
newline
bitfld.long 0x4C 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_2_en_tdone_2" "0,1"
newline
bitfld.long 0x4C 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_2_en_tdone_0" "0,1"
newline
bitfld.long 0x4C 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_6" "0,1"
newline
bitfld.long 0x4C 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_5" "0,1"
newline
bitfld.long 0x4C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_4" "0,1"
newline
bitfld.long 0x4C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_3" "0,1"
newline
bitfld.long 0x4C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_2" "0,1"
newline
bitfld.long 0x4C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_1" "0,1"
newline
bitfld.long 0x4C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x50 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_4,Enable Clear Register 20"
bitfld.long 0x50 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x50 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x50 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x50 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x50 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x50 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x50 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x50 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x50 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x50 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x50 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x50 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x50 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x50 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x50 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x50 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x50 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x50 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x50 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x50 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x50 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x50 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x50 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x50 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x50 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x50 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x50 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x50 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x50 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x50 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x50 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x50 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_0" "0,1"
line.long 0x54 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_5,Enable Clear Register 21"
bitfld.long 0x54 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x54 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x54 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x54 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x54 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x54 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x54 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x54 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x54 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x54 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x54 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x54 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x54 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x54 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x54 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x54 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x54 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x54 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x54 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x54 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x54 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x54 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x54 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x54 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x54 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x54 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x54 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x54 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x54 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x54 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x54 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x54 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_0" "0,1"
line.long 0x58 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_6,Enable Clear Register 22"
bitfld.long 0x58 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x58 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x58 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x58 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x58 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x58 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x58 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x58 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x58 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x58 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x58 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x58 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x58 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x58 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x58 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x58 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x58 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x58 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x58 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x58 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x58 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x58 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x58 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x58 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x58 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x58 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x58 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x58 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x58 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x58 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x58 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x58 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_2_en_utc1_complete_32" "0,1"
line.long 0x5C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_7,Enable Clear Register 23"
bitfld.long 0x5C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_2_en_ctm_pulse" "0,1"
newline
bitfld.long 0x5C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_2_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x5C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_2_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x5C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_2_en_utc1_error" "0,1"
newline
bitfld.long 0x5C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_2_en_utc0_error" "0,1"
line.long 0x60 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_0,Enable Clear Register 24"
bitfld.long 0x60 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x60 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x60 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x60 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x60 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x60 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x60 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x60 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x60 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x60 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x60 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x60 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x60 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x60 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x60 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x60 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x60 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x60 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x60 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x60 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x60 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x60 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x60 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x60 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x60 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x64 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_1,Enable Clear Register 25"
bitfld.long 0x64 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x64 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x64 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x64 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x64 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x64 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x64 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x64 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x64 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x68 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_2,Enable Clear Register 26"
bitfld.long 0x68 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x68 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x68 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_3_en_nf_frame_done" "0,1"
newline
bitfld.long 0x68 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x68 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x68 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x68 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x6C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_3,Enable Clear Register 27"
bitfld.long 0x6C 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x6C 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x6C 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x6C 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x6C 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x6C 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x6C 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x6C 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x6C 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x6C 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_3_en_spare_dec_1" "0,1"
newline
bitfld.long 0x6C 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_3_en_spare_dec_0" "0,1"
newline
bitfld.long 0x6C 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_3_en_tdone_6" "0,1"
newline
bitfld.long 0x6C 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_3_en_tdone_5" "0,1"
newline
bitfld.long 0x6C 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_3_en_tdone_4" "0,1"
newline
bitfld.long 0x6C 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_3_en_tdone_2" "0,1"
newline
bitfld.long 0x6C 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_3_en_tdone_0" "0,1"
newline
bitfld.long 0x6C 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_6" "0,1"
newline
bitfld.long 0x6C 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_5" "0,1"
newline
bitfld.long 0x6C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_4" "0,1"
newline
bitfld.long 0x6C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_3" "0,1"
newline
bitfld.long 0x6C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_2" "0,1"
newline
bitfld.long 0x6C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_1" "0,1"
newline
bitfld.long 0x6C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x70 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_4,Enable Clear Register 28"
bitfld.long 0x70 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x70 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x70 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x70 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x70 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x70 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x70 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x70 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x70 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x70 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x70 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x70 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x70 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x70 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x70 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x70 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x70 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x70 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x70 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x70 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x70 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x70 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x70 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x70 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x70 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x70 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x70 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x70 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x70 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x70 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x70 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x70 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_0" "0,1"
line.long 0x74 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_5,Enable Clear Register 29"
bitfld.long 0x74 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x74 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x74 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x74 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x74 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x74 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x74 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x74 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x74 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x74 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x74 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x74 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x74 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x74 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x74 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x74 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x74 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x74 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x74 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x74 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x74 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x74 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x74 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x74 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x74 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x74 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x74 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x74 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x74 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x74 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x74 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x74 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_0" "0,1"
line.long 0x78 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_6,Enable Clear Register 30"
bitfld.long 0x78 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x78 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x78 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x78 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x78 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x78 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x78 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x78 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x78 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x78 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x78 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x78 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x78 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x78 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x78 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x78 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x78 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x78 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x78 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x78 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x78 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x78 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x78 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x78 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x78 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x78 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x78 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x78 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x78 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x78 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x78 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x78 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_3_en_utc1_complete_32" "0,1"
line.long 0x7C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_3_7,Enable Clear Register 31"
bitfld.long 0x7C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_3_en_ctm_pulse" "0,1"
newline
bitfld.long 0x7C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_3_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x7C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_3_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x7C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_3_en_utc1_error" "0,1"
newline
bitfld.long 0x7C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_3_en_utc0_error" "0,1"
line.long 0x80 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0,Enable Clear Register 32"
bitfld.long 0x80 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x80 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x80 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x80 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x80 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x80 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x80 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x80 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x80 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x80 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x80 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x80 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x80 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x80 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x80 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x80 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x80 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x80 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x80 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x80 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x80 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x80 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x80 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x80 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x80 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x84 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_1,Enable Clear Register 33"
bitfld.long 0x84 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x84 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x84 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x84 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x84 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x84 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x84 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x84 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x84 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x88 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_2,Enable Clear Register 34"
bitfld.long 0x88 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x88 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x88 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_4_en_nf_frame_done" "0,1"
newline
bitfld.long 0x88 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x88 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x88 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x88 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x8C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_3,Enable Clear Register 35"
bitfld.long 0x8C 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x8C 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x8C 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x8C 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x8C 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x8C 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x8C 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x8C 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x8C 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x8C 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_4_en_spare_dec_1" "0,1"
newline
bitfld.long 0x8C 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_4_en_spare_dec_0" "0,1"
newline
bitfld.long 0x8C 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_4_en_tdone_6" "0,1"
newline
bitfld.long 0x8C 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_4_en_tdone_5" "0,1"
newline
bitfld.long 0x8C 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_4_en_tdone_4" "0,1"
newline
bitfld.long 0x8C 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_4_en_tdone_2" "0,1"
newline
bitfld.long 0x8C 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_4_en_tdone_0" "0,1"
newline
bitfld.long 0x8C 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_6" "0,1"
newline
bitfld.long 0x8C 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_5" "0,1"
newline
bitfld.long 0x8C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_4" "0,1"
newline
bitfld.long 0x8C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_3" "0,1"
newline
bitfld.long 0x8C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_2" "0,1"
newline
bitfld.long 0x8C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_1" "0,1"
newline
bitfld.long 0x8C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x90 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_4,Enable Clear Register 36"
bitfld.long 0x90 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x90 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x90 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x90 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x90 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x90 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x90 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x90 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x90 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x90 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x90 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x90 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x90 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x90 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x90 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x90 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x90 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x90 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x90 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x90 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x90 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x90 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x90 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x90 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x90 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x90 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x90 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x90 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x90 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x90 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x90 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x90 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_0" "0,1"
line.long 0x94 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_5,Enable Clear Register 37"
bitfld.long 0x94 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x94 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x94 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x94 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x94 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x94 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x94 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x94 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x94 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x94 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x94 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x94 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_20" "0,1"
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bitfld.long 0x94 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_19" "0,1"
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bitfld.long 0x94 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_18" "0,1"
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bitfld.long 0x94 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x94 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_16" "0,1"
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bitfld.long 0x94 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_15" "0,1"
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bitfld.long 0x94 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x94 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x94 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x94 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x94 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x94 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x94 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x94 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x94 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x94 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x94 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x94 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x94 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_2" "0,1"
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bitfld.long 0x94 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x94 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_0" "0,1"
line.long 0x98 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_6,Enable Clear Register 38"
bitfld.long 0x98 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_63" "0,1"
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bitfld.long 0x98 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_62" "0,1"
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bitfld.long 0x98 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_61" "0,1"
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bitfld.long 0x98 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_60" "0,1"
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bitfld.long 0x98 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_59" "0,1"
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bitfld.long 0x98 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_58" "0,1"
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bitfld.long 0x98 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_57" "0,1"
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bitfld.long 0x98 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_56" "0,1"
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bitfld.long 0x98 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_55" "0,1"
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bitfld.long 0x98 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_54" "0,1"
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bitfld.long 0x98 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_53" "0,1"
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bitfld.long 0x98 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_52" "0,1"
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bitfld.long 0x98 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_51" "0,1"
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bitfld.long 0x98 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_50" "0,1"
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bitfld.long 0x98 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_49" "0,1"
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bitfld.long 0x98 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_48" "0,1"
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bitfld.long 0x98 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_47" "0,1"
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bitfld.long 0x98 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_46" "0,1"
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bitfld.long 0x98 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_45" "0,1"
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bitfld.long 0x98 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_44" "0,1"
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bitfld.long 0x98 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_43" "0,1"
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bitfld.long 0x98 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_42" "0,1"
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bitfld.long 0x98 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_41" "0,1"
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bitfld.long 0x98 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_40" "0,1"
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bitfld.long 0x98 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_39" "0,1"
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bitfld.long 0x98 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_38" "0,1"
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bitfld.long 0x98 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_37" "0,1"
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bitfld.long 0x98 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_36" "0,1"
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bitfld.long 0x98 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x98 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_34" "0,1"
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bitfld.long 0x98 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_33" "0,1"
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bitfld.long 0x98 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_4_en_utc1_complete_32" "0,1"
line.long 0x9C "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_7,Enable Clear Register 39"
bitfld.long 0x9C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_4_en_ctm_pulse" "0,1"
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bitfld.long 0x9C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_4_en_utc1_prot_err" "0,1"
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bitfld.long 0x9C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_4_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x9C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_4_en_utc1_error" "0,1"
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bitfld.long 0x9C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_4_en_utc0_error" "0,1"
line.long 0xA0 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_0,Enable Clear Register 40"
bitfld.long 0xA0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0xA0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0xA0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0xA0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0xA0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0xA0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0xA0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0xA0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0xA0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0xA0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0xA0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0xA0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0xA0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0xA0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0xA0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0xA0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0xA0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0xA0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0xA0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0xA0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0xA0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0xA0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0xA0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0xA0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0xA0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0xA4 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_1,Enable Clear Register 41"
bitfld.long 0xA4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0xA4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0xA4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0xA4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0xA4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0xA4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0xA4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0xA4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0xA4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0xA8 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_2,Enable Clear Register 42"
bitfld.long 0xA8 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0xA8 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0xA8 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_NF_FRAME_DONE_CLR,Enable Clear for level_vpac_out_5_en_nf_frame_done" "0,1"
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bitfld.long 0xA8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0xA8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0xA8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0xA8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0xAC "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_3,Enable Clear Register 43"
bitfld.long 0xAC 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0xAC 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0xAC 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0xAC 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0xAC 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0xAC 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_1_level" "0,1"
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bitfld.long 0xAC 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0xAC 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_0_level" "0,1"
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bitfld.long 0xAC 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0xAC 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_5_en_spare_dec_1" "0,1"
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bitfld.long 0xAC 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_5_en_spare_dec_0" "0,1"
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bitfld.long 0xAC 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_5_en_tdone_6" "0,1"
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bitfld.long 0xAC 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_5_en_tdone_5" "0,1"
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bitfld.long 0xAC 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0xAC 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0xAC 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_5_en_tdone_0" "0,1"
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bitfld.long 0xAC 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_6" "0,1"
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bitfld.long 0xAC 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_5" "0,1"
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bitfld.long 0xAC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_4" "0,1"
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bitfld.long 0xAC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_3" "0,1"
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bitfld.long 0xAC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_2" "0,1"
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bitfld.long 0xAC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_1" "0,1"
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bitfld.long 0xAC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0xB0 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_4,Enable Clear Register 44"
bitfld.long 0xB0 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_31" "0,1"
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bitfld.long 0xB0 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_30" "0,1"
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bitfld.long 0xB0 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_29" "0,1"
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bitfld.long 0xB0 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_28" "0,1"
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bitfld.long 0xB0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_27" "0,1"
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bitfld.long 0xB0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_26" "0,1"
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bitfld.long 0xB0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_25" "0,1"
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bitfld.long 0xB0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_24" "0,1"
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bitfld.long 0xB0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_23" "0,1"
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bitfld.long 0xB0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_22" "0,1"
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bitfld.long 0xB0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_21" "0,1"
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bitfld.long 0xB0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_20" "0,1"
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bitfld.long 0xB0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_19" "0,1"
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bitfld.long 0xB0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_18" "0,1"
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bitfld.long 0xB0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_17" "0,1"
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bitfld.long 0xB0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_16" "0,1"
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bitfld.long 0xB0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_15" "0,1"
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bitfld.long 0xB0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_14" "0,1"
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bitfld.long 0xB0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_13" "0,1"
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bitfld.long 0xB0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_12" "0,1"
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bitfld.long 0xB0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_11" "0,1"
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bitfld.long 0xB0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_10" "0,1"
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bitfld.long 0xB0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_9" "0,1"
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bitfld.long 0xB0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_8" "0,1"
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bitfld.long 0xB0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_7" "0,1"
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bitfld.long 0xB0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_6" "0,1"
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bitfld.long 0xB0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_5" "0,1"
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bitfld.long 0xB0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_4" "0,1"
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bitfld.long 0xB0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_3" "0,1"
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bitfld.long 0xB0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_2" "0,1"
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bitfld.long 0xB0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_1" "0,1"
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bitfld.long 0xB0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_0" "0,1"
line.long 0xB4 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_5,Enable Clear Register 45"
bitfld.long 0xB4 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_31_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_31" "0,1"
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bitfld.long 0xB4 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_30_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_30" "0,1"
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bitfld.long 0xB4 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_29_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_29" "0,1"
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bitfld.long 0xB4 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_28_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_28" "0,1"
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bitfld.long 0xB4 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_27_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_27" "0,1"
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bitfld.long 0xB4 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_26_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_26" "0,1"
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bitfld.long 0xB4 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_25_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_25" "0,1"
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bitfld.long 0xB4 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_24_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_24" "0,1"
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bitfld.long 0xB4 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_23_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_23" "0,1"
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bitfld.long 0xB4 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_22_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_22" "0,1"
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bitfld.long 0xB4 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_21_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_21" "0,1"
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bitfld.long 0xB4 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_20_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_20" "0,1"
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bitfld.long 0xB4 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_19_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_19" "0,1"
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bitfld.long 0xB4 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_18_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_18" "0,1"
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bitfld.long 0xB4 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_17_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_17" "0,1"
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bitfld.long 0xB4 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_16_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_16" "0,1"
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bitfld.long 0xB4 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_15_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_15" "0,1"
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bitfld.long 0xB4 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_14_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_14" "0,1"
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bitfld.long 0xB4 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_13_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_13" "0,1"
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bitfld.long 0xB4 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_12_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_12" "0,1"
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bitfld.long 0xB4 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_11_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_11" "0,1"
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bitfld.long 0xB4 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_10_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_10" "0,1"
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bitfld.long 0xB4 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_9_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_9" "0,1"
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bitfld.long 0xB4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_8_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_8" "0,1"
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bitfld.long 0xB4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_7_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_7" "0,1"
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bitfld.long 0xB4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_6_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_6" "0,1"
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bitfld.long 0xB4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_5_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_5" "0,1"
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bitfld.long 0xB4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_4_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_4" "0,1"
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bitfld.long 0xB4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_3_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_3" "0,1"
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bitfld.long 0xB4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_2_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_2" "0,1"
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bitfld.long 0xB4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_1_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_1" "0,1"
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bitfld.long 0xB4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_0_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_0" "0,1"
line.long 0xB8 "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_6,Enable Clear Register 46"
bitfld.long 0xB8 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_63_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_63" "0,1"
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bitfld.long 0xB8 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_62_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_62" "0,1"
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bitfld.long 0xB8 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_61_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_61" "0,1"
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bitfld.long 0xB8 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_60_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_60" "0,1"
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bitfld.long 0xB8 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_59_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_59" "0,1"
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bitfld.long 0xB8 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_58_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_58" "0,1"
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bitfld.long 0xB8 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_57_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_57" "0,1"
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bitfld.long 0xB8 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_56_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_56" "0,1"
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bitfld.long 0xB8 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_55_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_55" "0,1"
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bitfld.long 0xB8 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_54_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_54" "0,1"
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bitfld.long 0xB8 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_53_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_53" "0,1"
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bitfld.long 0xB8 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_52_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_52" "0,1"
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bitfld.long 0xB8 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_51_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_51" "0,1"
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bitfld.long 0xB8 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_50_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_50" "0,1"
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bitfld.long 0xB8 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_49_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_49" "0,1"
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bitfld.long 0xB8 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_48_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_48" "0,1"
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bitfld.long 0xB8 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_47_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_47" "0,1"
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bitfld.long 0xB8 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_46_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_46" "0,1"
newline
bitfld.long 0xB8 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_45_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_45" "0,1"
newline
bitfld.long 0xB8 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_44_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_44" "0,1"
newline
bitfld.long 0xB8 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_43_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_43" "0,1"
newline
bitfld.long 0xB8 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_42_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_42" "0,1"
newline
bitfld.long 0xB8 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_41_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_41" "0,1"
newline
bitfld.long 0xB8 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_40_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_40" "0,1"
newline
bitfld.long 0xB8 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_39_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_39" "0,1"
newline
bitfld.long 0xB8 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_38_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_38" "0,1"
newline
bitfld.long 0xB8 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_37_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_37" "0,1"
newline
bitfld.long 0xB8 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_36_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_36" "0,1"
newline
bitfld.long 0xB8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_35_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_35" "0,1"
newline
bitfld.long 0xB8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_34_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_34" "0,1"
newline
bitfld.long 0xB8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_33_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_33" "0,1"
newline
bitfld.long 0xB8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_32_CLR,Enable Clear for level_vpac_out_5_en_utc1_complete_32" "0,1"
line.long 0xBC "VPAC_INTD_ENABLE_CLR_REG_LEVEL_VPAC_OUT_5_7,Enable Clear Register 47"
bitfld.long 0xBC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_5_en_ctm_pulse" "0,1"
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bitfld.long 0xBC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_PROT_ERR_CLR,Enable Clear for level_vpac_out_5_en_utc1_prot_err" "0,1"
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bitfld.long 0xBC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_5_en_utc0_prot_err" "0,1"
newline
bitfld.long 0xBC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_ERROR_CLR,Enable Clear for level_vpac_out_5_en_utc1_error" "0,1"
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bitfld.long 0xBC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_5_en_utc0_error" "0,1"
line.long 0xC0 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_0,Enable Clear Register 48"
bitfld.long 0xC0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0xC0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0xC0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0xC0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0xC0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0xC0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0xC0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0xC0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0xC0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0xC0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0xC0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0xC0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0xC0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0xC0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0xC0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0xC0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0xC0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0xC0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0xC0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0xC0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0xC0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0xC0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0xC0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0xC0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0xC0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0xC4 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_1,Enable Clear Register 49"
bitfld.long 0xC4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0xC4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0xC4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0xC4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1"
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bitfld.long 0xC4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0xC4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0xC4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0xC4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0xC4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0xC8 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_2,Enable Clear Register 50"
bitfld.long 0xC8 10. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0xC8 9. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0xC8 8. "ENABLE_PULSE_VPAC_OUT_0_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_0_en_nf_frame_done" "0,1"
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bitfld.long 0xC8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0xC8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0xC8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0xC8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0xCC "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_3,Enable Clear Register 51"
bitfld.long 0xCC 26. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0xCC 25. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0xCC 24. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0xCC 22. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0xCC 20. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0xCC 19. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_1_level" "0,1"
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bitfld.long 0xCC 18. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0xCC 17. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_0_level" "0,1"
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bitfld.long 0xCC 16. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0xCC 15. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0xCC 14. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0xCC 13. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_6" "0,1"
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bitfld.long 0xCC 12. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_5" "0,1"
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bitfld.long 0xCC 11. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_4" "0,1"
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bitfld.long 0xCC 9. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_2" "0,1"
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bitfld.long 0xCC 7. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0xCC 6. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_6" "0,1"
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bitfld.long 0xCC 5. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_5" "0,1"
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bitfld.long 0xCC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_4" "0,1"
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bitfld.long 0xCC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0xCC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0xCC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0xCC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0xD0 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_4,Enable Clear Register 52"
bitfld.long 0xD0 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_31" "0,1"
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bitfld.long 0xD0 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_30" "0,1"
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bitfld.long 0xD0 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_29" "0,1"
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bitfld.long 0xD0 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_28" "0,1"
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bitfld.long 0xD0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_27" "0,1"
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bitfld.long 0xD0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_26" "0,1"
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bitfld.long 0xD0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_25" "0,1"
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bitfld.long 0xD0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_24" "0,1"
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bitfld.long 0xD0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_23" "0,1"
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bitfld.long 0xD0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_22" "0,1"
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bitfld.long 0xD0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_21" "0,1"
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bitfld.long 0xD0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_20" "0,1"
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bitfld.long 0xD0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_19" "0,1"
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bitfld.long 0xD0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_18" "0,1"
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bitfld.long 0xD0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_17" "0,1"
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bitfld.long 0xD0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_16" "0,1"
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bitfld.long 0xD0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_15" "0,1"
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bitfld.long 0xD0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_14" "0,1"
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bitfld.long 0xD0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_13" "0,1"
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bitfld.long 0xD0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_12" "0,1"
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bitfld.long 0xD0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_11" "0,1"
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bitfld.long 0xD0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_10" "0,1"
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bitfld.long 0xD0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_9" "0,1"
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bitfld.long 0xD0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_8" "0,1"
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bitfld.long 0xD0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_7" "0,1"
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bitfld.long 0xD0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_6" "0,1"
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bitfld.long 0xD0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_5" "0,1"
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bitfld.long 0xD0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_4" "0,1"
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bitfld.long 0xD0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_3" "0,1"
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bitfld.long 0xD0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_2" "0,1"
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bitfld.long 0xD0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_1" "0,1"
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bitfld.long 0xD0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_0" "0,1"
line.long 0xD4 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_5,Enable Clear Register 53"
bitfld.long 0xD4 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_31" "0,1"
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bitfld.long 0xD4 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_30" "0,1"
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bitfld.long 0xD4 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_29" "0,1"
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bitfld.long 0xD4 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_28" "0,1"
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bitfld.long 0xD4 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_27" "0,1"
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bitfld.long 0xD4 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_26" "0,1"
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bitfld.long 0xD4 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_25" "0,1"
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bitfld.long 0xD4 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_24" "0,1"
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bitfld.long 0xD4 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_23" "0,1"
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bitfld.long 0xD4 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_22" "0,1"
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bitfld.long 0xD4 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_21" "0,1"
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bitfld.long 0xD4 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_20" "0,1"
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bitfld.long 0xD4 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_19" "0,1"
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bitfld.long 0xD4 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_18" "0,1"
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bitfld.long 0xD4 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_17" "0,1"
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bitfld.long 0xD4 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_16" "0,1"
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bitfld.long 0xD4 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_15" "0,1"
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bitfld.long 0xD4 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_14" "0,1"
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bitfld.long 0xD4 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_13" "0,1"
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bitfld.long 0xD4 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_12" "0,1"
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bitfld.long 0xD4 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_11" "0,1"
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bitfld.long 0xD4 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_10" "0,1"
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bitfld.long 0xD4 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_9" "0,1"
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bitfld.long 0xD4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_8" "0,1"
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bitfld.long 0xD4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_7" "0,1"
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bitfld.long 0xD4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_6" "0,1"
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bitfld.long 0xD4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_5" "0,1"
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bitfld.long 0xD4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_4" "0,1"
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bitfld.long 0xD4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_3" "0,1"
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bitfld.long 0xD4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_2" "0,1"
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bitfld.long 0xD4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_1" "0,1"
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bitfld.long 0xD4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_0" "0,1"
line.long 0xD8 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_6,Enable Clear Register 54"
bitfld.long 0xD8 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_63" "0,1"
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bitfld.long 0xD8 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_62" "0,1"
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bitfld.long 0xD8 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_61" "0,1"
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bitfld.long 0xD8 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_60" "0,1"
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bitfld.long 0xD8 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_59" "0,1"
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bitfld.long 0xD8 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_58" "0,1"
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bitfld.long 0xD8 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_57" "0,1"
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bitfld.long 0xD8 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_56" "0,1"
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bitfld.long 0xD8 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_55" "0,1"
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bitfld.long 0xD8 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_54" "0,1"
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bitfld.long 0xD8 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_53" "0,1"
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bitfld.long 0xD8 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_52" "0,1"
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bitfld.long 0xD8 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_51" "0,1"
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bitfld.long 0xD8 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_50" "0,1"
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bitfld.long 0xD8 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_49" "0,1"
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bitfld.long 0xD8 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_48" "0,1"
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bitfld.long 0xD8 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_47" "0,1"
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bitfld.long 0xD8 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_46" "0,1"
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bitfld.long 0xD8 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_45" "0,1"
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bitfld.long 0xD8 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_44" "0,1"
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bitfld.long 0xD8 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_43" "0,1"
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bitfld.long 0xD8 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_42" "0,1"
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bitfld.long 0xD8 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_41" "0,1"
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bitfld.long 0xD8 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_40" "0,1"
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bitfld.long 0xD8 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_39" "0,1"
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bitfld.long 0xD8 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_38" "0,1"
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bitfld.long 0xD8 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_37" "0,1"
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bitfld.long 0xD8 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_36" "0,1"
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bitfld.long 0xD8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_35" "0,1"
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bitfld.long 0xD8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_34" "0,1"
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bitfld.long 0xD8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_33" "0,1"
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bitfld.long 0xD8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_complete_32" "0,1"
line.long 0xDC "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_0_7,Enable Clear Register 55"
bitfld.long 0xDC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0xDC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_prot_err" "0,1"
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bitfld.long 0xDC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_prot_err" "0,1"
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bitfld.long 0xDC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_error" "0,1"
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bitfld.long 0xDC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_error" "0,1"
line.long 0xE0 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_0,Enable Clear Register 56"
bitfld.long 0xE0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0xE0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0xE0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0xE0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0xE0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0xE0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0xE0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0xE0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0xE0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0xE0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0xE0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0xE0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0xE0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0xE0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0xE0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0xE0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0xE0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0xE0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0xE0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0xE0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0xE0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0xE0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0xE0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0xE0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0xE0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0xE4 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_1,Enable Clear Register 57"
bitfld.long 0xE4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0xE4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0xE4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0xE4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1"
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bitfld.long 0xE4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0xE4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0xE4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0xE4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0xE4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0xE8 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_2,Enable Clear Register 58"
bitfld.long 0xE8 10. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0xE8 9. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0xE8 8. "ENABLE_PULSE_VPAC_OUT_1_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_1_en_nf_frame_done" "0,1"
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bitfld.long 0xE8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0xE8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0xE8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0xE8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0xEC "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_3,Enable Clear Register 59"
bitfld.long 0xEC 26. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0xEC 25. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0xEC 24. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0xEC 22. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0xEC 20. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0xEC 19. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_1_level" "0,1"
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bitfld.long 0xEC 18. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0xEC 17. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_0_level" "0,1"
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bitfld.long 0xEC 16. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0xEC 15. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0xEC 14. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0xEC 13. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_6" "0,1"
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bitfld.long 0xEC 12. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_5" "0,1"
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bitfld.long 0xEC 11. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_4" "0,1"
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bitfld.long 0xEC 9. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_2" "0,1"
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bitfld.long 0xEC 7. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0xEC 6. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_6" "0,1"
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bitfld.long 0xEC 5. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_5" "0,1"
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bitfld.long 0xEC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_4" "0,1"
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bitfld.long 0xEC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0xEC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0xEC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0xEC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0xF0 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_4,Enable Clear Register 60"
bitfld.long 0xF0 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_31" "0,1"
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bitfld.long 0xF0 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_30" "0,1"
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bitfld.long 0xF0 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_29" "0,1"
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bitfld.long 0xF0 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_28" "0,1"
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bitfld.long 0xF0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_27" "0,1"
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bitfld.long 0xF0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_26" "0,1"
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bitfld.long 0xF0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_25" "0,1"
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bitfld.long 0xF0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_24" "0,1"
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bitfld.long 0xF0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_23" "0,1"
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bitfld.long 0xF0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_22" "0,1"
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bitfld.long 0xF0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_21" "0,1"
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bitfld.long 0xF0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_20" "0,1"
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bitfld.long 0xF0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_19" "0,1"
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bitfld.long 0xF0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_18" "0,1"
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bitfld.long 0xF0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_17" "0,1"
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bitfld.long 0xF0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_16" "0,1"
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bitfld.long 0xF0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_15" "0,1"
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bitfld.long 0xF0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_14" "0,1"
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bitfld.long 0xF0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_13" "0,1"
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bitfld.long 0xF0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_12" "0,1"
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bitfld.long 0xF0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_11" "0,1"
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bitfld.long 0xF0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_10" "0,1"
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bitfld.long 0xF0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_9" "0,1"
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bitfld.long 0xF0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_8" "0,1"
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bitfld.long 0xF0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_7" "0,1"
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bitfld.long 0xF0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_6" "0,1"
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bitfld.long 0xF0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_5" "0,1"
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bitfld.long 0xF0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_4" "0,1"
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bitfld.long 0xF0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_3" "0,1"
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bitfld.long 0xF0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_2" "0,1"
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bitfld.long 0xF0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_1" "0,1"
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bitfld.long 0xF0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_0" "0,1"
line.long 0xF4 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_5,Enable Clear Register 61"
bitfld.long 0xF4 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_31" "0,1"
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bitfld.long 0xF4 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_30" "0,1"
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bitfld.long 0xF4 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_29" "0,1"
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bitfld.long 0xF4 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_28" "0,1"
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bitfld.long 0xF4 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_27" "0,1"
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bitfld.long 0xF4 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_26" "0,1"
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bitfld.long 0xF4 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_25" "0,1"
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bitfld.long 0xF4 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_24" "0,1"
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bitfld.long 0xF4 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_23" "0,1"
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bitfld.long 0xF4 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_22" "0,1"
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bitfld.long 0xF4 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_21" "0,1"
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bitfld.long 0xF4 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_20" "0,1"
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bitfld.long 0xF4 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_19" "0,1"
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bitfld.long 0xF4 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_18" "0,1"
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bitfld.long 0xF4 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_17" "0,1"
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bitfld.long 0xF4 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_16" "0,1"
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bitfld.long 0xF4 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_15" "0,1"
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bitfld.long 0xF4 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_14" "0,1"
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bitfld.long 0xF4 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_13" "0,1"
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bitfld.long 0xF4 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_12" "0,1"
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bitfld.long 0xF4 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_11" "0,1"
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bitfld.long 0xF4 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_10" "0,1"
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bitfld.long 0xF4 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_9" "0,1"
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bitfld.long 0xF4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_8" "0,1"
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bitfld.long 0xF4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_7" "0,1"
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bitfld.long 0xF4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_6" "0,1"
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bitfld.long 0xF4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_5" "0,1"
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bitfld.long 0xF4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_4" "0,1"
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bitfld.long 0xF4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_3" "0,1"
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bitfld.long 0xF4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_2" "0,1"
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bitfld.long 0xF4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_1" "0,1"
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bitfld.long 0xF4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_0" "0,1"
line.long 0xF8 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_6,Enable Clear Register 62"
bitfld.long 0xF8 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_63" "0,1"
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bitfld.long 0xF8 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_62" "0,1"
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bitfld.long 0xF8 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_61" "0,1"
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bitfld.long 0xF8 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_60" "0,1"
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bitfld.long 0xF8 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_59" "0,1"
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bitfld.long 0xF8 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_58" "0,1"
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bitfld.long 0xF8 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_57" "0,1"
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bitfld.long 0xF8 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_56" "0,1"
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bitfld.long 0xF8 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_55" "0,1"
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bitfld.long 0xF8 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_54" "0,1"
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bitfld.long 0xF8 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_53" "0,1"
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bitfld.long 0xF8 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_52" "0,1"
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bitfld.long 0xF8 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_51" "0,1"
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bitfld.long 0xF8 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_50" "0,1"
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bitfld.long 0xF8 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_49" "0,1"
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bitfld.long 0xF8 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_48" "0,1"
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bitfld.long 0xF8 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_47" "0,1"
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bitfld.long 0xF8 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_46" "0,1"
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bitfld.long 0xF8 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_45" "0,1"
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bitfld.long 0xF8 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_44" "0,1"
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bitfld.long 0xF8 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_43" "0,1"
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bitfld.long 0xF8 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_42" "0,1"
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bitfld.long 0xF8 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_41" "0,1"
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bitfld.long 0xF8 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_40" "0,1"
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bitfld.long 0xF8 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_39" "0,1"
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bitfld.long 0xF8 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_38" "0,1"
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bitfld.long 0xF8 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_37" "0,1"
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bitfld.long 0xF8 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_36" "0,1"
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bitfld.long 0xF8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_35" "0,1"
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bitfld.long 0xF8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_34" "0,1"
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bitfld.long 0xF8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_33" "0,1"
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bitfld.long 0xF8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_complete_32" "0,1"
line.long 0xFC "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_1_7,Enable Clear Register 63"
bitfld.long 0xFC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0xFC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_prot_err" "0,1"
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bitfld.long 0xFC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_prot_err" "0,1"
newline
bitfld.long 0xFC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_error" "0,1"
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bitfld.long 0xFC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_error" "0,1"
line.long 0x100 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_0,Enable Clear Register 64"
bitfld.long 0x100 24. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x100 23. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x100 22. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x100 21. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x100 20. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x100 19. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x100 18. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x100 17. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x100 16. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x100 15. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x100 14. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x100 13. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x100 12. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x100 11. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x100 10. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x100 9. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x100 8. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x100 7. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x100 6. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x100 5. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x100 4. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x100 3. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x100 2. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x100 1. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x100 0. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x104 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_1,Enable Clear Register 65"
bitfld.long 0x104 8. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x104 7. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x104 6. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x104 5. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x104 4. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x104 3. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x104 2. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x104 1. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x104 0. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x108 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_2,Enable Clear Register 66"
bitfld.long 0x108 10. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x108 9. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x108 8. "ENABLE_PULSE_VPAC_OUT_2_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_2_en_nf_frame_done" "0,1"
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bitfld.long 0x108 3. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x108 2. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x108 1. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x108 0. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_3,Enable Clear Register 67"
bitfld.long 0x10C 26. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10C 25. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10C 24. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10C 22. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10C 20. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x10C 19. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_1_level" "0,1"
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bitfld.long 0x10C 18. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1"
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bitfld.long 0x10C 17. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_0_level" "0,1"
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bitfld.long 0x10C 16. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10C 15. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_2_en_spare_dec_1" "0,1"
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bitfld.long 0x10C 14. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_2_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10C 13. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_6" "0,1"
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bitfld.long 0x10C 12. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_5" "0,1"
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bitfld.long 0x10C 11. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_4" "0,1"
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bitfld.long 0x10C 9. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_2" "0,1"
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bitfld.long 0x10C 7. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_0" "0,1"
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bitfld.long 0x10C 6. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_6" "0,1"
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bitfld.long 0x10C 5. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_5" "0,1"
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bitfld.long 0x10C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_4" "0,1"
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bitfld.long 0x10C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_3" "0,1"
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bitfld.long 0x10C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_2" "0,1"
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bitfld.long 0x10C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_1" "0,1"
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bitfld.long 0x10C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x110 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_4,Enable Clear Register 68"
bitfld.long 0x110 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_31" "0,1"
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bitfld.long 0x110 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_30" "0,1"
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bitfld.long 0x110 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_29" "0,1"
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bitfld.long 0x110 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_28" "0,1"
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bitfld.long 0x110 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_27" "0,1"
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bitfld.long 0x110 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_26" "0,1"
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bitfld.long 0x110 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_25" "0,1"
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bitfld.long 0x110 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_24" "0,1"
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bitfld.long 0x110 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_23" "0,1"
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bitfld.long 0x110 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_22" "0,1"
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bitfld.long 0x110 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_21" "0,1"
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bitfld.long 0x110 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_20" "0,1"
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bitfld.long 0x110 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_19" "0,1"
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bitfld.long 0x110 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_18" "0,1"
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bitfld.long 0x110 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_17" "0,1"
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bitfld.long 0x110 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_16" "0,1"
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bitfld.long 0x110 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_15" "0,1"
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bitfld.long 0x110 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_14" "0,1"
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bitfld.long 0x110 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_13" "0,1"
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bitfld.long 0x110 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_12" "0,1"
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bitfld.long 0x110 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_11" "0,1"
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bitfld.long 0x110 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_10" "0,1"
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bitfld.long 0x110 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_9" "0,1"
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bitfld.long 0x110 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_8" "0,1"
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bitfld.long 0x110 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_7" "0,1"
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bitfld.long 0x110 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_6" "0,1"
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bitfld.long 0x110 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_5" "0,1"
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bitfld.long 0x110 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_4" "0,1"
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bitfld.long 0x110 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_3" "0,1"
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bitfld.long 0x110 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_2" "0,1"
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bitfld.long 0x110 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_1" "0,1"
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bitfld.long 0x110 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_0" "0,1"
line.long 0x114 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_5,Enable Clear Register 69"
bitfld.long 0x114 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_31" "0,1"
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bitfld.long 0x114 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_30" "0,1"
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bitfld.long 0x114 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_29" "0,1"
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bitfld.long 0x114 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_28" "0,1"
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bitfld.long 0x114 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_27" "0,1"
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bitfld.long 0x114 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_26" "0,1"
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bitfld.long 0x114 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_25" "0,1"
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bitfld.long 0x114 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_24" "0,1"
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bitfld.long 0x114 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_23" "0,1"
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bitfld.long 0x114 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_22" "0,1"
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bitfld.long 0x114 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_21" "0,1"
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bitfld.long 0x114 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_20" "0,1"
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bitfld.long 0x114 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_19" "0,1"
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bitfld.long 0x114 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_18" "0,1"
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bitfld.long 0x114 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_17" "0,1"
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bitfld.long 0x114 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_16" "0,1"
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bitfld.long 0x114 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_15" "0,1"
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bitfld.long 0x114 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_14" "0,1"
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bitfld.long 0x114 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_13" "0,1"
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bitfld.long 0x114 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_12" "0,1"
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bitfld.long 0x114 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_11" "0,1"
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bitfld.long 0x114 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_10" "0,1"
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bitfld.long 0x114 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_9" "0,1"
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bitfld.long 0x114 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_8" "0,1"
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bitfld.long 0x114 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_7" "0,1"
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bitfld.long 0x114 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_6" "0,1"
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bitfld.long 0x114 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_5" "0,1"
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bitfld.long 0x114 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_4" "0,1"
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bitfld.long 0x114 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_3" "0,1"
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bitfld.long 0x114 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_2" "0,1"
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bitfld.long 0x114 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_1" "0,1"
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bitfld.long 0x114 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_0" "0,1"
line.long 0x118 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_6,Enable Clear Register 70"
bitfld.long 0x118 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_63" "0,1"
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bitfld.long 0x118 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_62" "0,1"
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bitfld.long 0x118 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_61" "0,1"
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bitfld.long 0x118 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_60" "0,1"
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bitfld.long 0x118 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_59" "0,1"
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bitfld.long 0x118 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_58" "0,1"
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bitfld.long 0x118 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_57" "0,1"
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bitfld.long 0x118 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_56" "0,1"
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bitfld.long 0x118 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_55" "0,1"
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bitfld.long 0x118 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_54" "0,1"
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bitfld.long 0x118 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_53" "0,1"
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bitfld.long 0x118 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_52" "0,1"
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bitfld.long 0x118 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_51" "0,1"
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bitfld.long 0x118 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_50" "0,1"
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bitfld.long 0x118 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_49" "0,1"
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bitfld.long 0x118 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_48" "0,1"
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bitfld.long 0x118 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_47" "0,1"
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bitfld.long 0x118 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_46" "0,1"
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bitfld.long 0x118 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_45" "0,1"
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bitfld.long 0x118 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_44" "0,1"
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bitfld.long 0x118 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_43" "0,1"
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bitfld.long 0x118 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_42" "0,1"
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bitfld.long 0x118 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_41" "0,1"
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bitfld.long 0x118 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_40" "0,1"
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bitfld.long 0x118 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_39" "0,1"
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bitfld.long 0x118 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_38" "0,1"
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bitfld.long 0x118 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_37" "0,1"
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bitfld.long 0x118 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_36" "0,1"
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bitfld.long 0x118 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_35" "0,1"
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bitfld.long 0x118 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_34" "0,1"
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bitfld.long 0x118 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_33" "0,1"
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bitfld.long 0x118 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_complete_32" "0,1"
line.long 0x11C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_2_7,Enable Clear Register 71"
bitfld.long 0x11C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_ctm_pulse" "0,1"
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bitfld.long 0x11C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_prot_err" "0,1"
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bitfld.long 0x11C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_prot_err" "0,1"
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bitfld.long 0x11C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_error" "0,1"
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bitfld.long 0x11C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_error" "0,1"
line.long 0x120 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_0,Enable Clear Register 72"
bitfld.long 0x120 24. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x120 23. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x120 22. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x120 21. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x120 20. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x120 19. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x120 18. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x120 17. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x120 16. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x120 15. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x120 14. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x120 13. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x120 12. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x120 11. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x120 10. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x120 9. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x120 8. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x120 7. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x120 6. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x120 5. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x120 4. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x120 3. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x120 2. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x120 1. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x120 0. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x124 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_1,Enable Clear Register 73"
bitfld.long 0x124 8. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x124 7. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x124 6. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x124 5. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x124 4. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x124 3. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x124 2. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x124 1. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x124 0. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x128 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_2,Enable Clear Register 74"
bitfld.long 0x128 10. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x128 9. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x128 8. "ENABLE_PULSE_VPAC_OUT_3_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_3_en_nf_frame_done" "0,1"
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bitfld.long 0x128 3. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x128 2. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x128 1. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x128 0. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x12C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_3,Enable Clear Register 75"
bitfld.long 0x12C 26. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x12C 25. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x12C 24. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x12C 22. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x12C 20. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x12C 19. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x12C 18. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x12C 17. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x12C 16. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x12C 15. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_3_en_spare_dec_1" "0,1"
newline
bitfld.long 0x12C 14. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_3_en_spare_dec_0" "0,1"
newline
bitfld.long 0x12C 13. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_6" "0,1"
newline
bitfld.long 0x12C 12. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_5" "0,1"
newline
bitfld.long 0x12C 11. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_4" "0,1"
newline
bitfld.long 0x12C 9. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_2" "0,1"
newline
bitfld.long 0x12C 7. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_0" "0,1"
newline
bitfld.long 0x12C 6. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_6" "0,1"
newline
bitfld.long 0x12C 5. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_5" "0,1"
newline
bitfld.long 0x12C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_4" "0,1"
newline
bitfld.long 0x12C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_3" "0,1"
newline
bitfld.long 0x12C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_2" "0,1"
newline
bitfld.long 0x12C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_1" "0,1"
newline
bitfld.long 0x12C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x130 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_4,Enable Clear Register 76"
bitfld.long 0x130 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x130 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x130 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x130 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x130 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x130 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x130 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x130 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x130 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x130 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x130 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x130 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x130 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x130 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x130 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x130 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x130 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x130 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x130 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x130 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x130 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x130 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x130 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x130 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x130 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x130 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x130 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x130 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x130 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x130 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x130 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x130 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_0" "0,1"
line.long 0x134 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_5,Enable Clear Register 77"
bitfld.long 0x134 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x134 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x134 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x134 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x134 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x134 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x134 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x134 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x134 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x134 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x134 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x134 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x134 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x134 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x134 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x134 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x134 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x134 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x134 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x134 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x134 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x134 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x134 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x134 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x134 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x134 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x134 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x134 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x134 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x134 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x134 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x134 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_0" "0,1"
line.long 0x138 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_6,Enable Clear Register 78"
bitfld.long 0x138 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x138 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x138 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x138 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x138 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x138 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x138 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x138 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x138 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x138 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x138 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x138 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x138 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x138 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x138 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x138 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x138 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x138 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x138 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x138 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x138 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x138 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x138 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x138 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x138 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x138 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x138 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x138 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x138 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x138 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x138 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x138 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_complete_32" "0,1"
line.long 0x13C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_3_7,Enable Clear Register 79"
bitfld.long 0x13C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_ctm_pulse" "0,1"
newline
bitfld.long 0x13C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x13C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x13C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_error" "0,1"
newline
bitfld.long 0x13C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_error" "0,1"
line.long 0x140 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_0,Enable Clear Register 80"
bitfld.long 0x140 24. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x140 23. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x140 22. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x140 21. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x140 20. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x140 19. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x140 18. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x140 17. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x140 16. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x140 15. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x140 14. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x140 13. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x140 12. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x140 11. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x140 10. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x140 9. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x140 8. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x140 7. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x140 6. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x140 5. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x140 4. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x140 3. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x140 2. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x140 1. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x140 0. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x144 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_1,Enable Clear Register 81"
bitfld.long 0x144 8. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x144 7. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x144 6. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x144 5. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x144 4. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x144 3. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x144 2. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x144 1. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x144 0. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x148 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_2,Enable Clear Register 82"
bitfld.long 0x148 10. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x148 9. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x148 8. "ENABLE_PULSE_VPAC_OUT_4_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_4_en_nf_frame_done" "0,1"
newline
bitfld.long 0x148 3. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x148 2. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x148 1. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x148 0. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x14C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_3,Enable Clear Register 83"
bitfld.long 0x14C 26. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x14C 25. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x14C 24. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x14C 22. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x14C 20. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x14C 19. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x14C 18. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x14C 17. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x14C 16. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x14C 15. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_4_en_spare_dec_1" "0,1"
newline
bitfld.long 0x14C 14. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_4_en_spare_dec_0" "0,1"
newline
bitfld.long 0x14C 13. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_6" "0,1"
newline
bitfld.long 0x14C 12. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_5" "0,1"
newline
bitfld.long 0x14C 11. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_4" "0,1"
newline
bitfld.long 0x14C 9. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_2" "0,1"
newline
bitfld.long 0x14C 7. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_0" "0,1"
newline
bitfld.long 0x14C 6. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_6" "0,1"
newline
bitfld.long 0x14C 5. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_5" "0,1"
newline
bitfld.long 0x14C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_4" "0,1"
newline
bitfld.long 0x14C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_3" "0,1"
newline
bitfld.long 0x14C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_2" "0,1"
newline
bitfld.long 0x14C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_1" "0,1"
newline
bitfld.long 0x14C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x150 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_4,Enable Clear Register 84"
bitfld.long 0x150 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x150 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x150 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x150 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x150 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x150 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x150 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x150 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x150 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x150 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x150 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x150 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x150 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x150 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x150 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x150 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x150 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x150 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x150 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x150 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x150 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x150 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x150 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x150 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x150 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x150 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x150 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x150 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x150 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x150 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x150 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x150 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_0" "0,1"
line.long 0x154 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_5,Enable Clear Register 85"
bitfld.long 0x154 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_31" "0,1"
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bitfld.long 0x154 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_30" "0,1"
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bitfld.long 0x154 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_29" "0,1"
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bitfld.long 0x154 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_28" "0,1"
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bitfld.long 0x154 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_27" "0,1"
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bitfld.long 0x154 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x154 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_25" "0,1"
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bitfld.long 0x154 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_24" "0,1"
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bitfld.long 0x154 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_23" "0,1"
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bitfld.long 0x154 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x154 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x154 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x154 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x154 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x154 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x154 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x154 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x154 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x154 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x154 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x154 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x154 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x154 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x154 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x154 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x154 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x154 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x154 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x154 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x154 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_2" "0,1"
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bitfld.long 0x154 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_1" "0,1"
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bitfld.long 0x154 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_0" "0,1"
line.long 0x158 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_6,Enable Clear Register 86"
bitfld.long 0x158 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_63" "0,1"
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bitfld.long 0x158 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_62" "0,1"
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bitfld.long 0x158 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_61" "0,1"
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bitfld.long 0x158 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x158 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_59" "0,1"
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bitfld.long 0x158 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_58" "0,1"
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bitfld.long 0x158 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x158 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_56" "0,1"
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bitfld.long 0x158 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x158 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_54" "0,1"
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bitfld.long 0x158 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_53" "0,1"
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bitfld.long 0x158 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_52" "0,1"
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bitfld.long 0x158 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x158 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x158 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x158 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x158 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x158 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x158 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x158 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x158 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x158 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x158 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x158 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x158 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x158 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_38" "0,1"
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bitfld.long 0x158 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x158 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x158 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x158 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x158 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x158 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_complete_32" "0,1"
line.long 0x15C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_4_7,Enable Clear Register 87"
bitfld.long 0x15C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_ctm_pulse" "0,1"
newline
bitfld.long 0x15C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x15C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x15C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_error" "0,1"
newline
bitfld.long 0x15C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_error" "0,1"
line.long 0x160 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_0,Enable Clear Register 88"
bitfld.long 0x160 24. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x160 23. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x160 22. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x160 21. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x160 20. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x160 19. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x160 18. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x160 17. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x160 16. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x160 15. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x160 14. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x160 13. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x160 12. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x160 11. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x160 10. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
newline
bitfld.long 0x160 9. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x160 8. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x160 7. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x160 6. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x160 5. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x160 4. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x160 3. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x160 2. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x160 1. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x160 0. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x164 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_1,Enable Clear Register 89"
bitfld.long 0x164 8. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x164 7. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x164 6. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x164 5. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x164 4. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x164 3. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x164 2. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x164 1. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x164 0. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x168 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_2,Enable Clear Register 90"
bitfld.long 0x168 10. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x168 9. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x168 8. "ENABLE_PULSE_VPAC_OUT_5_EN_NF_FRAME_DONE_CLR,Enable Clear for pulse_vpac_out_5_en_nf_frame_done" "0,1"
newline
bitfld.long 0x168 3. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x168 2. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x168 1. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x168 0. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x16C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_3,Enable Clear Register 91"
bitfld.long 0x16C 26. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x16C 25. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x16C 24. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x16C 22. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x16C 20. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x16C 19. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_1_level" "0,1"
newline
bitfld.long 0x16C 18. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1"
newline
bitfld.long 0x16C 17. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_0_level" "0,1"
newline
bitfld.long 0x16C 16. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x16C 15. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_5_en_spare_dec_1" "0,1"
newline
bitfld.long 0x16C 14. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_5_en_spare_dec_0" "0,1"
newline
bitfld.long 0x16C 13. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_6" "0,1"
newline
bitfld.long 0x16C 12. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_5" "0,1"
newline
bitfld.long 0x16C 11. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_4" "0,1"
newline
bitfld.long 0x16C 9. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_2" "0,1"
newline
bitfld.long 0x16C 7. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_0" "0,1"
newline
bitfld.long 0x16C 6. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_6" "0,1"
newline
bitfld.long 0x16C 5. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_5" "0,1"
newline
bitfld.long 0x16C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_4" "0,1"
newline
bitfld.long 0x16C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_3" "0,1"
newline
bitfld.long 0x16C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_2" "0,1"
newline
bitfld.long 0x16C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_1" "0,1"
newline
bitfld.long 0x16C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0x170 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_4,Enable Clear Register 92"
bitfld.long 0x170 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x170 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x170 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x170 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x170 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x170 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x170 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x170 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x170 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x170 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x170 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x170 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x170 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x170 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x170 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x170 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x170 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x170 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x170 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x170 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x170 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x170 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x170 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x170 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x170 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x170 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x170 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x170 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x170 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x170 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x170 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x170 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_0" "0,1"
line.long 0x174 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_5,Enable Clear Register 93"
bitfld.long 0x174 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x174 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x174 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x174 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x174 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x174 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x174 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x174 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x174 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x174 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x174 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x174 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x174 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x174 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x174 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x174 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x174 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x174 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x174 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x174 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x174 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x174 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x174 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x174 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x174 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x174 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x174 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x174 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x174 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x174 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x174 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x174 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_0" "0,1"
line.long 0x178 "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_6,Enable Clear Register 94"
bitfld.long 0x178 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x178 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x178 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x178 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x178 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x178 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x178 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x178 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x178 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x178 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x178 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x178 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x178 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x178 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x178 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x178 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x178 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x178 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x178 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x178 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x178 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x178 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x178 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x178 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x178 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x178 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x178 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x178 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x178 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x178 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x178 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x178 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_complete_32" "0,1"
line.long 0x17C "VPAC_INTD_ENABLE_CLR_REG_PULSE_VPAC_OUT_5_7,Enable Clear Register 95"
bitfld.long 0x17C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_ctm_pulse" "0,1"
newline
bitfld.long 0x17C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x17C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x17C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_ERROR_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_error" "0,1"
newline
bitfld.long 0x17C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_error" "0,1"
group.long 0x500++0x13
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_0,Status Register 0"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
newline
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
newline
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
newline
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_1,Status Register 1"
bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_0_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_0_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_0_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
newline
bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_0_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
newline
bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
newline
bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
newline
bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
newline
bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_2,Status Register 2"
bitfld.long 0x08 10. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_nf_sl2_rd_err" "0,1"
newline
bitfld.long 0x08 9. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_0_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_0_en_nf_frame_done" "0,1"
newline
bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
newline
bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_3,Status Register 3"
bitfld.long 0x0C 26. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x0C 25. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x0C 24. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x0C 22. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x0C 20. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x0C 19. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_1_LEVEL,Status for level_vpac_out_0_en_spare_pend_1_level" "0,1"
newline
rbitfld.long 0x0C 18. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_1_PULSE,Status for level_vpac_out_0_en_spare_pend_1_pulse" "0,1"
newline
rbitfld.long 0x0C 17. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_0_LEVEL,Status for level_vpac_out_0_en_spare_pend_0_level" "0,1"
newline
rbitfld.long 0x0C 16. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_0_PULSE,Status for level_vpac_out_0_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x0C 15. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for level_vpac_out_0_en_spare_dec_1" "0,1"
newline
bitfld.long 0x0C 14. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for level_vpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x0C 13. "STATUS_LEVEL_VPAC_OUT_0_TDONE_6,Status write 1 to set for level_vpac_out_0_en_tdone_6" "0,1"
newline
bitfld.long 0x0C 12. "STATUS_LEVEL_VPAC_OUT_0_TDONE_5,Status write 1 to set for level_vpac_out_0_en_tdone_5" "0,1"
newline
bitfld.long 0x0C 11. "STATUS_LEVEL_VPAC_OUT_0_TDONE_4,Status write 1 to set for level_vpac_out_0_en_tdone_4" "0,1"
newline
bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_0_TDONE_2,Status write 1 to set for level_vpac_out_0_en_tdone_2" "0,1"
newline
bitfld.long 0x0C 7. "STATUS_LEVEL_VPAC_OUT_0_TDONE_0,Status write 1 to set for level_vpac_out_0_en_tdone_0" "0,1"
newline
bitfld.long 0x0C 6. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_6,Status write 1 to set for level_vpac_out_0_en_pipe_done_6" "0,1"
newline
bitfld.long 0x0C 5. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_5,Status write 1 to set for level_vpac_out_0_en_pipe_done_5" "0,1"
newline
bitfld.long 0x0C 4. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_4,Status write 1 to set for level_vpac_out_0_en_pipe_done_4" "0,1"
newline
bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for level_vpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for level_vpac_out_0_en_pipe_done_2" "0,1"
newline
bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for level_vpac_out_0_en_pipe_done_1" "0,1"
newline
bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for level_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_4,Status Register 4"
bitfld.long 0x10 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_0_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x10 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_0_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x10 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_0_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x10 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_0_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x10 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_0_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_0_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_0_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_0_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x10 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_0_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_0_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x10 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_0_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_0_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_0_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_0_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_0_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_0_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_0_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_0_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_0_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_0_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_0_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x10 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_0_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_0_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x10 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_0_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_0_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_0_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_0_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_0_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_0_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_0_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_0_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_0_en_utc0_complete_0" "0,1"
group.long 0x51C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_7,Status Register 7"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_0_CTM_PULSE,Status write 1 to set for level_vpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_0_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_0_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_ERROR,Status write 1 to set for level_vpac_out_0_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_ERROR,Status write 1 to set for level_vpac_out_0_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_0,Status Register 8"
bitfld.long 0x04 24. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_1,Status Register 9"
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_1_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_LEVEL_VPAC_OUT_1_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_LEVEL_VPAC_OUT_1_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_LEVEL_VPAC_OUT_1_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_LEVEL_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_2,Status Register 10"
bitfld.long 0x0C 10. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_VPAC_OUT_1_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_1_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_3,Status Register 11"
bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_1_LEVEL,Status for level_vpac_out_1_en_spare_pend_1_level" "0,1"
newline
rbitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_1_PULSE,Status for level_vpac_out_1_en_spare_pend_1_pulse" "0,1"
newline
rbitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_0_LEVEL,Status for level_vpac_out_1_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_0_PULSE,Status for level_vpac_out_1_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for level_vpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for level_vpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_1_TDONE_6,Status write 1 to set for level_vpac_out_1_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_1_TDONE_5,Status write 1 to set for level_vpac_out_1_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_1_TDONE_4,Status write 1 to set for level_vpac_out_1_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_1_TDONE_2,Status write 1 to set for level_vpac_out_1_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_1_TDONE_0,Status write 1 to set for level_vpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_6,Status write 1 to set for level_vpac_out_1_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_5,Status write 1 to set for level_vpac_out_1_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_4,Status write 1 to set for level_vpac_out_1_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for level_vpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for level_vpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for level_vpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for level_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_4,Status Register 12"
bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_1_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_1_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_1_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_1_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_1_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_1_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_1_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_1_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_1_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_1_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_1_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_1_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_1_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_1_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_1_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_1_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_1_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_1_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_1_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_1_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_1_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_1_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_1_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_1_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_1_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_1_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_1_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_1_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_1_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_1_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_1_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_1_en_utc0_complete_0" "0,1"
group.long 0x53C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_7,Status Register 15"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_1_CTM_PULSE,Status write 1 to set for level_vpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_1_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_1_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_ERROR,Status write 1 to set for level_vpac_out_1_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_ERROR,Status write 1 to set for level_vpac_out_1_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_0,Status Register 16"
bitfld.long 0x04 24. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_1,Status Register 17"
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_2_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_LEVEL_VPAC_OUT_2_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_LEVEL_VPAC_OUT_2_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_LEVEL_VPAC_OUT_2_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_LEVEL_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_2,Status Register 18"
bitfld.long 0x0C 10. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_VPAC_OUT_2_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_2_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_3,Status Register 19"
bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_0" "0,1"
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rbitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_1_LEVEL,Status for level_vpac_out_2_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_1_PULSE,Status for level_vpac_out_2_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_0_LEVEL,Status for level_vpac_out_2_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_0_PULSE,Status for level_vpac_out_2_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_1,Status write 1 to set for level_vpac_out_2_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_0,Status write 1 to set for level_vpac_out_2_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_2_TDONE_6,Status write 1 to set for level_vpac_out_2_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_2_TDONE_5,Status write 1 to set for level_vpac_out_2_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_2_TDONE_4,Status write 1 to set for level_vpac_out_2_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_2_TDONE_2,Status write 1 to set for level_vpac_out_2_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_2_TDONE_0,Status write 1 to set for level_vpac_out_2_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_6,Status write 1 to set for level_vpac_out_2_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_5,Status write 1 to set for level_vpac_out_2_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_4,Status write 1 to set for level_vpac_out_2_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_3,Status write 1 to set for level_vpac_out_2_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_2,Status write 1 to set for level_vpac_out_2_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_1,Status write 1 to set for level_vpac_out_2_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_0,Status write 1 to set for level_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_4,Status Register 20"
bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_2_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_2_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_2_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_2_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_2_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_2_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_2_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_2_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_2_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_2_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_2_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_2_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_2_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_2_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_2_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_2_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_2_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_2_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_2_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_2_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_2_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_2_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_2_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_2_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_2_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_2_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_2_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_2_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_2_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_2_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_2_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_2_en_utc0_complete_0" "0,1"
group.long 0x55C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_7,Status Register 23"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_2_CTM_PULSE,Status write 1 to set for level_vpac_out_2_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_2_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_2_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_ERROR,Status write 1 to set for level_vpac_out_2_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_ERROR,Status write 1 to set for level_vpac_out_2_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_0,Status Register 24"
bitfld.long 0x04 24. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_1,Status Register 25"
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_3_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_LEVEL_VPAC_OUT_3_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_LEVEL_VPAC_OUT_3_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_LEVEL_VPAC_OUT_3_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_LEVEL_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_2,Status Register 26"
bitfld.long 0x0C 10. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_VPAC_OUT_3_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_3_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_3,Status Register 27"
bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_0" "0,1"
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rbitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_1_LEVEL,Status for level_vpac_out_3_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_1_PULSE,Status for level_vpac_out_3_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_0_LEVEL,Status for level_vpac_out_3_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_0_PULSE,Status for level_vpac_out_3_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_1,Status write 1 to set for level_vpac_out_3_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_0,Status write 1 to set for level_vpac_out_3_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_3_TDONE_6,Status write 1 to set for level_vpac_out_3_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_3_TDONE_5,Status write 1 to set for level_vpac_out_3_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_3_TDONE_4,Status write 1 to set for level_vpac_out_3_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_3_TDONE_2,Status write 1 to set for level_vpac_out_3_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_3_TDONE_0,Status write 1 to set for level_vpac_out_3_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_6,Status write 1 to set for level_vpac_out_3_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_5,Status write 1 to set for level_vpac_out_3_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_4,Status write 1 to set for level_vpac_out_3_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_3,Status write 1 to set for level_vpac_out_3_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_2,Status write 1 to set for level_vpac_out_3_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_1,Status write 1 to set for level_vpac_out_3_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_0,Status write 1 to set for level_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_4,Status Register 28"
bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_3_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_3_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_3_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_3_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_3_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_3_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_3_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_3_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_3_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_3_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_3_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_3_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_3_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_3_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_3_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_3_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_3_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_3_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_3_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_3_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_3_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_3_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_3_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_3_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_3_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_3_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_3_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_3_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_3_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_3_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_3_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_3_en_utc0_complete_0" "0,1"
group.long 0x57C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_7,Status Register 31"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_3_CTM_PULSE,Status write 1 to set for level_vpac_out_3_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_3_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_3_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_ERROR,Status write 1 to set for level_vpac_out_3_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_ERROR,Status write 1 to set for level_vpac_out_3_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_0,Status Register 32"
bitfld.long 0x04 24. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_1,Status Register 33"
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_4_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_LEVEL_VPAC_OUT_4_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_LEVEL_VPAC_OUT_4_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_LEVEL_VPAC_OUT_4_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_LEVEL_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_2,Status Register 34"
bitfld.long 0x0C 10. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_VPAC_OUT_4_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_4_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_3,Status Register 35"
bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_0" "0,1"
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rbitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_1_LEVEL,Status for level_vpac_out_4_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_1_PULSE,Status for level_vpac_out_4_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_0_LEVEL,Status for level_vpac_out_4_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_0_PULSE,Status for level_vpac_out_4_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_1,Status write 1 to set for level_vpac_out_4_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_0,Status write 1 to set for level_vpac_out_4_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_4_TDONE_6,Status write 1 to set for level_vpac_out_4_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_4_TDONE_5,Status write 1 to set for level_vpac_out_4_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_4_TDONE_4,Status write 1 to set for level_vpac_out_4_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_4_TDONE_2,Status write 1 to set for level_vpac_out_4_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_4_TDONE_0,Status write 1 to set for level_vpac_out_4_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_6,Status write 1 to set for level_vpac_out_4_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_5,Status write 1 to set for level_vpac_out_4_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_4,Status write 1 to set for level_vpac_out_4_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_3,Status write 1 to set for level_vpac_out_4_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_2,Status write 1 to set for level_vpac_out_4_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_1,Status write 1 to set for level_vpac_out_4_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_0,Status write 1 to set for level_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_4,Status Register 36"
bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_4_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_4_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_4_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_4_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_4_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_4_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_4_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_4_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_4_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_4_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_4_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_4_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_4_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_4_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_4_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_4_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_4_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_4_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_4_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_4_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_4_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_4_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_4_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_4_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_4_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_4_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_4_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_4_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_4_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_4_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_4_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_4_en_utc0_complete_0" "0,1"
group.long 0x59C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_7,Status Register 39"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_4_CTM_PULSE,Status write 1 to set for level_vpac_out_4_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_4_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_4_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_ERROR,Status write 1 to set for level_vpac_out_4_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_ERROR,Status write 1 to set for level_vpac_out_4_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_0,Status Register 40"
bitfld.long 0x04 24. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_1,Status Register 41"
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_5_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_LEVEL_VPAC_OUT_5_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_LEVEL_VPAC_OUT_5_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_LEVEL_VPAC_OUT_5_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_LEVEL_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_2,Status Register 42"
bitfld.long 0x0C 10. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_LEVEL_VPAC_OUT_5_NF_FRAME_DONE,Status write 1 to set for level_vpac_out_5_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_3,Status Register 43"
bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_0" "0,1"
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rbitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_1_LEVEL,Status for level_vpac_out_5_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_1_PULSE,Status for level_vpac_out_5_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_0_LEVEL,Status for level_vpac_out_5_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_0_PULSE,Status for level_vpac_out_5_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_1,Status write 1 to set for level_vpac_out_5_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_0,Status write 1 to set for level_vpac_out_5_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_5_TDONE_6,Status write 1 to set for level_vpac_out_5_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_5_TDONE_5,Status write 1 to set for level_vpac_out_5_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_5_TDONE_4,Status write 1 to set for level_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_5_TDONE_2,Status write 1 to set for level_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_5_TDONE_0,Status write 1 to set for level_vpac_out_5_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_6,Status write 1 to set for level_vpac_out_5_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_5,Status write 1 to set for level_vpac_out_5_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_4,Status write 1 to set for level_vpac_out_5_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_3,Status write 1 to set for level_vpac_out_5_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_2,Status write 1 to set for level_vpac_out_5_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_1,Status write 1 to set for level_vpac_out_5_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_0,Status write 1 to set for level_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_4,Status Register 44"
bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_5_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_5_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_5_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_5_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_5_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_5_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_5_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_5_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_5_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_5_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_5_en_utc0_complete_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_5_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_5_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_5_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_5_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_5_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_5_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_5_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_5_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_5_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_5_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_5_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_5_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_5_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_5_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_5_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_5_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_5_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_5_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_5_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_5_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_5_en_utc0_complete_0" "0,1"
group.long 0x5BC++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_7,Status Register 47"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_5_CTM_PULSE,Status write 1 to set for level_vpac_out_5_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_PROT_ERR,Status write 1 to set for level_vpac_out_5_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_5_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_ERROR,Status write 1 to set for level_vpac_out_5_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_ERROR,Status write 1 to set for level_vpac_out_5_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_0,Status Register 48"
bitfld.long 0x04 24. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_1,Status Register 49"
bitfld.long 0x08 8. "STATUS_PULSE_VPAC_OUT_0_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_PULSE_VPAC_OUT_0_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_PULSE_VPAC_OUT_0_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_PULSE_VPAC_OUT_0_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_PULSE_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_2,Status Register 50"
bitfld.long 0x0C 10. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_PULSE_VPAC_OUT_0_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_0_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_3,Status Register 51"
bitfld.long 0x10 26. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1"
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rbitfld.long 0x10 19. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_0_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_0_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "STATUS_PULSE_VPAC_OUT_0_TDONE_6,Status write 1 to set for pulse_vpac_out_0_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_PULSE_VPAC_OUT_0_TDONE_5,Status write 1 to set for pulse_vpac_out_0_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "STATUS_PULSE_VPAC_OUT_0_TDONE_4,Status write 1 to set for pulse_vpac_out_0_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_PULSE_VPAC_OUT_0_TDONE_2,Status write 1 to set for pulse_vpac_out_0_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_PULSE_VPAC_OUT_0_TDONE_0,Status write 1 to set for pulse_vpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_4,Status Register 52"
bitfld.long 0x14 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_0" "0,1"
group.long 0x5DC++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_7,Status Register 55"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_0_CTM_PULSE,Status write 1 to set for pulse_vpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_0_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_0_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_0_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_0_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_0,Status Register 56"
bitfld.long 0x04 24. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
newline
bitfld.long 0x04 17. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
newline
bitfld.long 0x04 13. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
newline
bitfld.long 0x04 6. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
newline
bitfld.long 0x04 5. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_1,Status Register 57"
bitfld.long 0x08 8. "STATUS_PULSE_VPAC_OUT_1_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "STATUS_PULSE_VPAC_OUT_1_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "STATUS_PULSE_VPAC_OUT_1_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_PULSE_VPAC_OUT_1_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_PULSE_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_2,Status Register 58"
bitfld.long 0x0C 10. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "STATUS_PULSE_VPAC_OUT_1_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_1_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_3,Status Register 59"
bitfld.long 0x10 26. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x10 19. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_1_en_spare_pend_1_level" "0,1"
newline
rbitfld.long 0x10 18. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1"
newline
rbitfld.long 0x10 17. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_1_en_spare_pend_0_level" "0,1"
newline
rbitfld.long 0x10 16. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_1_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "STATUS_PULSE_VPAC_OUT_1_TDONE_6,Status write 1 to set for pulse_vpac_out_1_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "STATUS_PULSE_VPAC_OUT_1_TDONE_5,Status write 1 to set for pulse_vpac_out_1_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_PULSE_VPAC_OUT_1_TDONE_4,Status write 1 to set for pulse_vpac_out_1_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_PULSE_VPAC_OUT_1_TDONE_2,Status write 1 to set for pulse_vpac_out_1_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_PULSE_VPAC_OUT_1_TDONE_0,Status write 1 to set for pulse_vpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_4,Status Register 60"
bitfld.long 0x14 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x14 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x14 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_0" "0,1"
group.long 0x5FC++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_7,Status Register 63"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_1_CTM_PULSE,Status write 1 to set for pulse_vpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_1_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_1_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_1_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_1_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_0,Status Register 64"
bitfld.long 0x04 24. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
newline
bitfld.long 0x04 12. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
newline
bitfld.long 0x04 7. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
newline
bitfld.long 0x04 4. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
newline
bitfld.long 0x04 3. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
newline
bitfld.long 0x04 1. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_1,Status Register 65"
bitfld.long 0x08 8. "STATUS_PULSE_VPAC_OUT_2_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
newline
bitfld.long 0x08 7. "STATUS_PULSE_VPAC_OUT_2_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 6. "STATUS_PULSE_VPAC_OUT_2_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_PULSE_VPAC_OUT_2_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1"
newline
bitfld.long 0x08 4. "STATUS_PULSE_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_2,Status Register 66"
bitfld.long 0x0C 10. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x0C 8. "STATUS_PULSE_VPAC_OUT_2_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_2_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_3,Status Register 67"
bitfld.long 0x10 26. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1"
newline
bitfld.long 0x10 25. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1"
newline
bitfld.long 0x10 24. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1"
newline
bitfld.long 0x10 22. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x10 20. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x10 19. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_2_en_spare_pend_1_level" "0,1"
newline
rbitfld.long 0x10 18. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1"
newline
rbitfld.long 0x10 17. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_2_en_spare_pend_0_level" "0,1"
newline
rbitfld.long 0x10 16. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1"
newline
bitfld.long 0x10 15. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_2_en_spare_dec_1" "0,1"
newline
bitfld.long 0x10 14. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_2_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "STATUS_PULSE_VPAC_OUT_2_TDONE_6,Status write 1 to set for pulse_vpac_out_2_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "STATUS_PULSE_VPAC_OUT_2_TDONE_5,Status write 1 to set for pulse_vpac_out_2_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "STATUS_PULSE_VPAC_OUT_2_TDONE_4,Status write 1 to set for pulse_vpac_out_2_en_tdone_4" "0,1"
newline
bitfld.long 0x10 9. "STATUS_PULSE_VPAC_OUT_2_TDONE_2,Status write 1 to set for pulse_vpac_out_2_en_tdone_2" "0,1"
newline
bitfld.long 0x10 7. "STATUS_PULSE_VPAC_OUT_2_TDONE_0,Status write 1 to set for pulse_vpac_out_2_en_tdone_0" "0,1"
newline
bitfld.long 0x10 6. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_4,Status Register 68"
bitfld.long 0x14 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x14 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_0" "0,1"
group.long 0x61C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_7,Status Register 71"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_2_CTM_PULSE,Status write 1 to set for pulse_vpac_out_2_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_2_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_2_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_2_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_2_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_0,Status Register 72"
bitfld.long 0x04 24. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_1,Status Register 73"
bitfld.long 0x08 8. "STATUS_PULSE_VPAC_OUT_3_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_PULSE_VPAC_OUT_3_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_PULSE_VPAC_OUT_3_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_PULSE_VPAC_OUT_3_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_PULSE_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_2,Status Register 74"
bitfld.long 0x0C 10. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_PULSE_VPAC_OUT_3_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_3_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_3,Status Register 75"
bitfld.long 0x10 26. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x10 19. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_3_en_spare_pend_1_level" "0,1"
newline
rbitfld.long 0x10 18. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1"
newline
rbitfld.long 0x10 17. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_3_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_3_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_3_en_spare_dec_0" "0,1"
newline
bitfld.long 0x10 13. "STATUS_PULSE_VPAC_OUT_3_TDONE_6,Status write 1 to set for pulse_vpac_out_3_en_tdone_6" "0,1"
newline
bitfld.long 0x10 12. "STATUS_PULSE_VPAC_OUT_3_TDONE_5,Status write 1 to set for pulse_vpac_out_3_en_tdone_5" "0,1"
newline
bitfld.long 0x10 11. "STATUS_PULSE_VPAC_OUT_3_TDONE_4,Status write 1 to set for pulse_vpac_out_3_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_PULSE_VPAC_OUT_3_TDONE_2,Status write 1 to set for pulse_vpac_out_3_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_PULSE_VPAC_OUT_3_TDONE_0,Status write 1 to set for pulse_vpac_out_3_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_4" "0,1"
newline
bitfld.long 0x10 3. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_3" "0,1"
newline
bitfld.long 0x10 2. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_1" "0,1"
newline
bitfld.long 0x10 0. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_4,Status Register 76"
bitfld.long 0x14 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x14 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x14 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x14 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x14 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x14 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x14 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x14 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x14 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_14" "0,1"
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bitfld.long 0x14 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_0" "0,1"
group.long 0x63C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_7,Status Register 79"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_3_CTM_PULSE,Status write 1 to set for pulse_vpac_out_3_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_3_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_3_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_3_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_3_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_0,Status Register 80"
bitfld.long 0x04 24. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_1,Status Register 81"
bitfld.long 0x08 8. "STATUS_PULSE_VPAC_OUT_4_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_PULSE_VPAC_OUT_4_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_PULSE_VPAC_OUT_4_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_PULSE_VPAC_OUT_4_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_PULSE_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_2,Status Register 82"
bitfld.long 0x0C 10. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_PULSE_VPAC_OUT_4_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_4_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_3,Status Register 83"
bitfld.long 0x10 26. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x10 19. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_4_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_4_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_4_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_4_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_PULSE_VPAC_OUT_4_TDONE_6,Status write 1 to set for pulse_vpac_out_4_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_PULSE_VPAC_OUT_4_TDONE_5,Status write 1 to set for pulse_vpac_out_4_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_PULSE_VPAC_OUT_4_TDONE_4,Status write 1 to set for pulse_vpac_out_4_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_PULSE_VPAC_OUT_4_TDONE_2,Status write 1 to set for pulse_vpac_out_4_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_PULSE_VPAC_OUT_4_TDONE_0,Status write 1 to set for pulse_vpac_out_4_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_4,Status Register 84"
bitfld.long 0x14 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_26" "0,1"
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bitfld.long 0x14 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x14 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_0" "0,1"
group.long 0x65C++0x17
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_7,Status Register 87"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_4_CTM_PULSE,Status write 1 to set for pulse_vpac_out_4_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_4_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_4_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_4_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_4_en_utc0_error" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_0,Status Register 88"
bitfld.long 0x04 24. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x04 23. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x04 22. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x04 21. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x04 20. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x04 19. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x04 18. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x04 17. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x04 16. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x04 15. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x04 14. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x04 13. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x04 12. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x04 11. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x04 10. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x04 9. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x04 8. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x04 7. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x04 6. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x04 5. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x04 4. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x04 3. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x04 2. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x04 1. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x04 0. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_1,Status Register 89"
bitfld.long 0x08 8. "STATUS_PULSE_VPAC_OUT_5_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x08 7. "STATUS_PULSE_VPAC_OUT_5_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x08 6. "STATUS_PULSE_VPAC_OUT_5_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x08 5. "STATUS_PULSE_VPAC_OUT_5_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x08 4. "STATUS_PULSE_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x08 3. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x08 2. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x08 1. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x08 0. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_2,Status Register 90"
bitfld.long 0x0C 10. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x0C 9. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x0C 8. "STATUS_PULSE_VPAC_OUT_5_NF_FRAME_DONE,Status write 1 to set for pulse_vpac_out_5_en_nf_frame_done" "0,1"
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bitfld.long 0x0C 3. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x0C 2. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x0C 1. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_3,Status Register 91"
bitfld.long 0x10 26. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10 25. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10 24. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10 22. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10 20. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1"
newline
rbitfld.long 0x10 19. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_5_en_spare_pend_1_level" "0,1"
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rbitfld.long 0x10 18. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1"
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rbitfld.long 0x10 17. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_5_en_spare_pend_0_level" "0,1"
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rbitfld.long 0x10 16. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1"
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bitfld.long 0x10 15. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_5_en_spare_dec_1" "0,1"
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bitfld.long 0x10 14. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_5_en_spare_dec_0" "0,1"
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bitfld.long 0x10 13. "STATUS_PULSE_VPAC_OUT_5_TDONE_6,Status write 1 to set for pulse_vpac_out_5_en_tdone_6" "0,1"
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bitfld.long 0x10 12. "STATUS_PULSE_VPAC_OUT_5_TDONE_5,Status write 1 to set for pulse_vpac_out_5_en_tdone_5" "0,1"
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bitfld.long 0x10 11. "STATUS_PULSE_VPAC_OUT_5_TDONE_4,Status write 1 to set for pulse_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0x10 9. "STATUS_PULSE_VPAC_OUT_5_TDONE_2,Status write 1 to set for pulse_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0x10 7. "STATUS_PULSE_VPAC_OUT_5_TDONE_0,Status write 1 to set for pulse_vpac_out_5_en_tdone_0" "0,1"
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bitfld.long 0x10 6. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_6" "0,1"
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bitfld.long 0x10 5. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_5" "0,1"
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bitfld.long 0x10 4. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_4" "0,1"
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bitfld.long 0x10 3. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_3" "0,1"
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bitfld.long 0x10 2. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_2" "0,1"
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bitfld.long 0x10 1. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_1" "0,1"
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bitfld.long 0x10 0. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_4,Status Register 92"
bitfld.long 0x14 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_31" "0,1"
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bitfld.long 0x14 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_30" "0,1"
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bitfld.long 0x14 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_29" "0,1"
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bitfld.long 0x14 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_28" "0,1"
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bitfld.long 0x14 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_27" "0,1"
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bitfld.long 0x14 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x14 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_25" "0,1"
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bitfld.long 0x14 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x14 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x14 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x14 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x14 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x14 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x14 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x14 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x14 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x14 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x14 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x14 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x14 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x14 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x14 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x14 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_0" "0,1"
group.long 0x67C++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_7,Status Register 95"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_5_CTM_PULSE,Status write 1 to set for pulse_vpac_out_5_en_ctm_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_PROT_ERR,Status write 1 to set for pulse_vpac_out_5_en_utc1_prot_err" "0,1"
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bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_5_en_utc0_prot_err" "0,1"
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bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_ERROR,Status write 1 to set for pulse_vpac_out_5_en_utc1_error" "0,1"
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bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_5_en_utc0_error" "0,1"
group.long 0x700++0x17F
line.long 0x00 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_0,Status Clear Register 0"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
newline
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
newline
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x04 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_1,Status Clear Register 1"
bitfld.long 0x04 8. "STATUS_LEVEL_VPAC_OUT_0_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x04 7. "STATUS_LEVEL_VPAC_OUT_0_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x04 6. "STATUS_LEVEL_VPAC_OUT_0_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x04 5. "STATUS_LEVEL_VPAC_OUT_0_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x04 4. "STATUS_LEVEL_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x04 3. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x04 2. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x04 1. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x04 0. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x08 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_2,Status Clear Register 2"
bitfld.long 0x08 10. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x08 9. "STATUS_LEVEL_VPAC_OUT_0_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_nf_sl2_wr_err" "0,1"
newline
bitfld.long 0x08 8. "STATUS_LEVEL_VPAC_OUT_0_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_0_en_nf_frame_done" "0,1"
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bitfld.long 0x08 3. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x08 2. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x08 1. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
newline
bitfld.long 0x08 0. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x0C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_3,Status Clear Register 3"
bitfld.long 0x0C 26. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x0C 25. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x0C 24. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x0C 22. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_2" "0,1"
newline
bitfld.long 0x0C 20. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_0" "0,1"
newline
bitfld.long 0x0C 15. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0x0C 14. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_0_en_spare_dec_0" "0,1"
newline
bitfld.long 0x0C 13. "STATUS_LEVEL_VPAC_OUT_0_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_6" "0,1"
newline
bitfld.long 0x0C 12. "STATUS_LEVEL_VPAC_OUT_0_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_5" "0,1"
newline
bitfld.long 0x0C 11. "STATUS_LEVEL_VPAC_OUT_0_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_4" "0,1"
newline
bitfld.long 0x0C 9. "STATUS_LEVEL_VPAC_OUT_0_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_2" "0,1"
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bitfld.long 0x0C 7. "STATUS_LEVEL_VPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0x0C 6. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_6" "0,1"
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bitfld.long 0x0C 5. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_5" "0,1"
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bitfld.long 0x0C 4. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_4" "0,1"
newline
bitfld.long 0x0C 3. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_3" "0,1"
newline
bitfld.long 0x0C 2. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0x0C 1. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0x0C 0. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0x10 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_4,Status Clear Register 4"
bitfld.long 0x10 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x10 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x10 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x10 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_28" "0,1"
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bitfld.long 0x10 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_27" "0,1"
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bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_25" "0,1"
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bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_24" "0,1"
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bitfld.long 0x10 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_22" "0,1"
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bitfld.long 0x10 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x10 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x10 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_0" "0,1"
line.long 0x14 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_5,Status Clear Register 5"
bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_24" "0,1"
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bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_23" "0,1"
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bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_22" "0,1"
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bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_21" "0,1"
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bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_20" "0,1"
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bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_19" "0,1"
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bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_18" "0,1"
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bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_17" "0,1"
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bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_16" "0,1"
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bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_15" "0,1"
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bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_14" "0,1"
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bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_13" "0,1"
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bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_12" "0,1"
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bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_11" "0,1"
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bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_10" "0,1"
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bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_9" "0,1"
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bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_8" "0,1"
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bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_7" "0,1"
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bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_6" "0,1"
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bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_5" "0,1"
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bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_4" "0,1"
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bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_3" "0,1"
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bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_2" "0,1"
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bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_1" "0,1"
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bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_0" "0,1"
line.long 0x18 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_6,Status Clear Register 6"
bitfld.long 0x18 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_63" "0,1"
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bitfld.long 0x18 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_62" "0,1"
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bitfld.long 0x18 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_61" "0,1"
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bitfld.long 0x18 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_60" "0,1"
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bitfld.long 0x18 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_59" "0,1"
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bitfld.long 0x18 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_58" "0,1"
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bitfld.long 0x18 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_57" "0,1"
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bitfld.long 0x18 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_56" "0,1"
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bitfld.long 0x18 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_55" "0,1"
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bitfld.long 0x18 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_54" "0,1"
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bitfld.long 0x18 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_53" "0,1"
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bitfld.long 0x18 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_52" "0,1"
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bitfld.long 0x18 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_51" "0,1"
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bitfld.long 0x18 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_50" "0,1"
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bitfld.long 0x18 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_49" "0,1"
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bitfld.long 0x18 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_48" "0,1"
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bitfld.long 0x18 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_47" "0,1"
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bitfld.long 0x18 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_46" "0,1"
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bitfld.long 0x18 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_45" "0,1"
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bitfld.long 0x18 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_44" "0,1"
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bitfld.long 0x18 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_43" "0,1"
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bitfld.long 0x18 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_42" "0,1"
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bitfld.long 0x18 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_41" "0,1"
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bitfld.long 0x18 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_40" "0,1"
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bitfld.long 0x18 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_39" "0,1"
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bitfld.long 0x18 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_38" "0,1"
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bitfld.long 0x18 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_37" "0,1"
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bitfld.long 0x18 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_36" "0,1"
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bitfld.long 0x18 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_35" "0,1"
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bitfld.long 0x18 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_34" "0,1"
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bitfld.long 0x18 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_33" "0,1"
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bitfld.long 0x18 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_complete_32" "0,1"
line.long 0x1C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_0_7,Status Clear Register 7"
bitfld.long 0x1C 4. "STATUS_LEVEL_VPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0x1C 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_prot_err" "0,1"
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bitfld.long 0x1C 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_prot_err" "0,1"
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bitfld.long 0x1C 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_error" "0,1"
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bitfld.long 0x1C 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_error" "0,1"
line.long 0x20 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_0,Status Clear Register 8"
bitfld.long 0x20 24. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x20 23. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x20 22. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x20 21. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x20 20. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x20 19. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x20 18. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x20 17. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x20 16. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x20 15. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x20 14. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x20 13. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x20 12. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x20 11. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x20 10. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x20 9. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x20 8. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x20 7. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x20 6. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x20 5. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x20 4. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x20 3. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x20 2. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x20 1. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x20 0. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x24 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_1,Status Clear Register 9"
bitfld.long 0x24 8. "STATUS_LEVEL_VPAC_OUT_1_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x24 7. "STATUS_LEVEL_VPAC_OUT_1_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x24 6. "STATUS_LEVEL_VPAC_OUT_1_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x24 5. "STATUS_LEVEL_VPAC_OUT_1_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x24 4. "STATUS_LEVEL_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x24 3. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x24 2. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x24 1. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x24 0. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x28 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_2,Status Clear Register 10"
bitfld.long 0x28 10. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x28 9. "STATUS_LEVEL_VPAC_OUT_1_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x28 8. "STATUS_LEVEL_VPAC_OUT_1_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_1_en_nf_frame_done" "0,1"
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bitfld.long 0x28 3. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x28 2. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x28 1. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x28 0. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x2C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_3,Status Clear Register 11"
bitfld.long 0x2C 26. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x2C 25. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x2C 24. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x2C 22. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x2C 20. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x2C 15. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0x2C 14. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_1_en_spare_dec_0" "0,1"
newline
bitfld.long 0x2C 13. "STATUS_LEVEL_VPAC_OUT_1_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_6" "0,1"
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bitfld.long 0x2C 12. "STATUS_LEVEL_VPAC_OUT_1_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_5" "0,1"
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bitfld.long 0x2C 11. "STATUS_LEVEL_VPAC_OUT_1_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_4" "0,1"
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bitfld.long 0x2C 9. "STATUS_LEVEL_VPAC_OUT_1_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_2" "0,1"
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bitfld.long 0x2C 7. "STATUS_LEVEL_VPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0x2C 6. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_6" "0,1"
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bitfld.long 0x2C 5. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_5" "0,1"
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bitfld.long 0x2C 4. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_4" "0,1"
newline
bitfld.long 0x2C 3. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0x2C 2. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0x2C 1. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0x2C 0. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0x30 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_4,Status Clear Register 12"
bitfld.long 0x30 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x30 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x30 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x30 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x30 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x30 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x30 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x30 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x30 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x30 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_22" "0,1"
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bitfld.long 0x30 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_21" "0,1"
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bitfld.long 0x30 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_20" "0,1"
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bitfld.long 0x30 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_19" "0,1"
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bitfld.long 0x30 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_18" "0,1"
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bitfld.long 0x30 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_17" "0,1"
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bitfld.long 0x30 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_16" "0,1"
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bitfld.long 0x30 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_15" "0,1"
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bitfld.long 0x30 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x30 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_13" "0,1"
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bitfld.long 0x30 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_12" "0,1"
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bitfld.long 0x30 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_11" "0,1"
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bitfld.long 0x30 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_10" "0,1"
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bitfld.long 0x30 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_9" "0,1"
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bitfld.long 0x30 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_8" "0,1"
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bitfld.long 0x30 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_7" "0,1"
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bitfld.long 0x30 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_6" "0,1"
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bitfld.long 0x30 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_5" "0,1"
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bitfld.long 0x30 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_4" "0,1"
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bitfld.long 0x30 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x30 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_2" "0,1"
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bitfld.long 0x30 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x30 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_0" "0,1"
line.long 0x34 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_5,Status Clear Register 13"
bitfld.long 0x34 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x34 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x34 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x34 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x34 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x34 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x34 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x34 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x34 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x34 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x34 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x34 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x34 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x34 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x34 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x34 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x34 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x34 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x34 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x34 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x34 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x34 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x34 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x34 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x34 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x34 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x34 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x34 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x34 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x34 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x34 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x34 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_0" "0,1"
line.long 0x38 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_6,Status Clear Register 14"
bitfld.long 0x38 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x38 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x38 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x38 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x38 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x38 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x38 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x38 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x38 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x38 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x38 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x38 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x38 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x38 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x38 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x38 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x38 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x38 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x38 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x38 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x38 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x38 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x38 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x38 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x38 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x38 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x38 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x38 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x38 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x38 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x38 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x38 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_complete_32" "0,1"
line.long 0x3C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_1_7,Status Clear Register 15"
bitfld.long 0x3C 4. "STATUS_LEVEL_VPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_ctm_pulse" "0,1"
newline
bitfld.long 0x3C 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x3C 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x3C 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_error" "0,1"
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bitfld.long 0x3C 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_error" "0,1"
line.long 0x40 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_0,Status Clear Register 16"
bitfld.long 0x40 24. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x40 23. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x40 22. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x40 21. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x40 20. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x40 19. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x40 18. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x40 17. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x40 16. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x40 15. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x40 14. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x40 13. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x40 12. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x40 11. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x40 10. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x40 9. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x40 8. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x40 7. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x40 6. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x40 5. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x40 4. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x40 3. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x40 2. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x40 1. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x40 0. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x44 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_1,Status Clear Register 17"
bitfld.long 0x44 8. "STATUS_LEVEL_VPAC_OUT_2_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x44 7. "STATUS_LEVEL_VPAC_OUT_2_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x44 6. "STATUS_LEVEL_VPAC_OUT_2_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x44 5. "STATUS_LEVEL_VPAC_OUT_2_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x44 4. "STATUS_LEVEL_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x44 3. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x44 2. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x44 1. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x44 0. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x48 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_2,Status Clear Register 18"
bitfld.long 0x48 10. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x48 9. "STATUS_LEVEL_VPAC_OUT_2_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x48 8. "STATUS_LEVEL_VPAC_OUT_2_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_2_en_nf_frame_done" "0,1"
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bitfld.long 0x48 3. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x48 2. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x48 1. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x48 0. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x4C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_3,Status Clear Register 19"
bitfld.long 0x4C 26. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x4C 25. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x4C 24. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x4C 22. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x4C 20. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x4C 15. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_2_en_spare_dec_1" "0,1"
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bitfld.long 0x4C 14. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_2_en_spare_dec_0" "0,1"
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bitfld.long 0x4C 13. "STATUS_LEVEL_VPAC_OUT_2_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_6" "0,1"
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bitfld.long 0x4C 12. "STATUS_LEVEL_VPAC_OUT_2_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_5" "0,1"
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bitfld.long 0x4C 11. "STATUS_LEVEL_VPAC_OUT_2_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_4" "0,1"
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bitfld.long 0x4C 9. "STATUS_LEVEL_VPAC_OUT_2_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_2" "0,1"
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bitfld.long 0x4C 7. "STATUS_LEVEL_VPAC_OUT_2_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_0" "0,1"
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bitfld.long 0x4C 6. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_6" "0,1"
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bitfld.long 0x4C 5. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_5" "0,1"
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bitfld.long 0x4C 4. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_4" "0,1"
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bitfld.long 0x4C 3. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_3" "0,1"
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bitfld.long 0x4C 2. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_2" "0,1"
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bitfld.long 0x4C 1. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_1" "0,1"
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bitfld.long 0x4C 0. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x50 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_4,Status Clear Register 20"
bitfld.long 0x50 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_31" "0,1"
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bitfld.long 0x50 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_30" "0,1"
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bitfld.long 0x50 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_29" "0,1"
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bitfld.long 0x50 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_28" "0,1"
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bitfld.long 0x50 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_27" "0,1"
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bitfld.long 0x50 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_26" "0,1"
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bitfld.long 0x50 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_25" "0,1"
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bitfld.long 0x50 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_24" "0,1"
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bitfld.long 0x50 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_23" "0,1"
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bitfld.long 0x50 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_22" "0,1"
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bitfld.long 0x50 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_21" "0,1"
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bitfld.long 0x50 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_20" "0,1"
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bitfld.long 0x50 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_19" "0,1"
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bitfld.long 0x50 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_18" "0,1"
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bitfld.long 0x50 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_17" "0,1"
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bitfld.long 0x50 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_16" "0,1"
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bitfld.long 0x50 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_15" "0,1"
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bitfld.long 0x50 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_14" "0,1"
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bitfld.long 0x50 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_13" "0,1"
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bitfld.long 0x50 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_12" "0,1"
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bitfld.long 0x50 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_11" "0,1"
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bitfld.long 0x50 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_10" "0,1"
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bitfld.long 0x50 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_9" "0,1"
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bitfld.long 0x50 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_8" "0,1"
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bitfld.long 0x50 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_7" "0,1"
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bitfld.long 0x50 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_6" "0,1"
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bitfld.long 0x50 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_5" "0,1"
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bitfld.long 0x50 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_4" "0,1"
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bitfld.long 0x50 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_3" "0,1"
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bitfld.long 0x50 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_2" "0,1"
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bitfld.long 0x50 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_1" "0,1"
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bitfld.long 0x50 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_0" "0,1"
line.long 0x54 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_5,Status Clear Register 21"
bitfld.long 0x54 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_31" "0,1"
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bitfld.long 0x54 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_30" "0,1"
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bitfld.long 0x54 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_29" "0,1"
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bitfld.long 0x54 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_28" "0,1"
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bitfld.long 0x54 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_27" "0,1"
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bitfld.long 0x54 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_26" "0,1"
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bitfld.long 0x54 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_25" "0,1"
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bitfld.long 0x54 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_24" "0,1"
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bitfld.long 0x54 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_23" "0,1"
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bitfld.long 0x54 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_22" "0,1"
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bitfld.long 0x54 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_21" "0,1"
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bitfld.long 0x54 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_20" "0,1"
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bitfld.long 0x54 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_19" "0,1"
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bitfld.long 0x54 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_18" "0,1"
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bitfld.long 0x54 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_17" "0,1"
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bitfld.long 0x54 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_16" "0,1"
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bitfld.long 0x54 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_15" "0,1"
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bitfld.long 0x54 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_14" "0,1"
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bitfld.long 0x54 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_13" "0,1"
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bitfld.long 0x54 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_12" "0,1"
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bitfld.long 0x54 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_11" "0,1"
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bitfld.long 0x54 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_10" "0,1"
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bitfld.long 0x54 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_9" "0,1"
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bitfld.long 0x54 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_8" "0,1"
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bitfld.long 0x54 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_7" "0,1"
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bitfld.long 0x54 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_6" "0,1"
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bitfld.long 0x54 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_5" "0,1"
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bitfld.long 0x54 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_4" "0,1"
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bitfld.long 0x54 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_3" "0,1"
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bitfld.long 0x54 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_2" "0,1"
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bitfld.long 0x54 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_1" "0,1"
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bitfld.long 0x54 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_0" "0,1"
line.long 0x58 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_6,Status Clear Register 22"
bitfld.long 0x58 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_63" "0,1"
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bitfld.long 0x58 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_62" "0,1"
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bitfld.long 0x58 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_61" "0,1"
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bitfld.long 0x58 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_60" "0,1"
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bitfld.long 0x58 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_59" "0,1"
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bitfld.long 0x58 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_58" "0,1"
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bitfld.long 0x58 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_57" "0,1"
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bitfld.long 0x58 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_56" "0,1"
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bitfld.long 0x58 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_55" "0,1"
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bitfld.long 0x58 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_54" "0,1"
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bitfld.long 0x58 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_53" "0,1"
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bitfld.long 0x58 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_52" "0,1"
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bitfld.long 0x58 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_51" "0,1"
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bitfld.long 0x58 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_50" "0,1"
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bitfld.long 0x58 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_49" "0,1"
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bitfld.long 0x58 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_48" "0,1"
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bitfld.long 0x58 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_47" "0,1"
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bitfld.long 0x58 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_46" "0,1"
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bitfld.long 0x58 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_45" "0,1"
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bitfld.long 0x58 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_44" "0,1"
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bitfld.long 0x58 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_43" "0,1"
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bitfld.long 0x58 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_42" "0,1"
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bitfld.long 0x58 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_41" "0,1"
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bitfld.long 0x58 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_40" "0,1"
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bitfld.long 0x58 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_39" "0,1"
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bitfld.long 0x58 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_38" "0,1"
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bitfld.long 0x58 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_37" "0,1"
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bitfld.long 0x58 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_36" "0,1"
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bitfld.long 0x58 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_35" "0,1"
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bitfld.long 0x58 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_34" "0,1"
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bitfld.long 0x58 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_33" "0,1"
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bitfld.long 0x58 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_complete_32" "0,1"
line.long 0x5C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_2_7,Status Clear Register 23"
bitfld.long 0x5C 4. "STATUS_LEVEL_VPAC_OUT_2_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_ctm_pulse" "0,1"
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bitfld.long 0x5C 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_prot_err" "0,1"
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bitfld.long 0x5C 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_prot_err" "0,1"
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bitfld.long 0x5C 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_error" "0,1"
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bitfld.long 0x5C 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_error" "0,1"
line.long 0x60 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_0,Status Clear Register 24"
bitfld.long 0x60 24. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x60 23. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x60 22. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x60 21. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x60 20. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x60 19. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x60 18. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x60 17. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x60 16. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x60 15. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x60 14. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x60 13. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x60 12. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x60 11. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x60 10. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x60 9. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x60 8. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x60 7. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x60 6. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x60 5. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x60 4. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x60 3. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x60 2. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x60 1. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x60 0. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x64 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_1,Status Clear Register 25"
bitfld.long 0x64 8. "STATUS_LEVEL_VPAC_OUT_3_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x64 7. "STATUS_LEVEL_VPAC_OUT_3_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x64 6. "STATUS_LEVEL_VPAC_OUT_3_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x64 5. "STATUS_LEVEL_VPAC_OUT_3_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x64 4. "STATUS_LEVEL_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x64 3. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x64 2. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x64 1. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x64 0. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x68 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_2,Status Clear Register 26"
bitfld.long 0x68 10. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x68 9. "STATUS_LEVEL_VPAC_OUT_3_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x68 8. "STATUS_LEVEL_VPAC_OUT_3_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_3_en_nf_frame_done" "0,1"
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bitfld.long 0x68 3. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x68 2. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x68 1. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x68 0. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x6C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_3,Status Clear Register 27"
bitfld.long 0x6C 26. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x6C 25. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x6C 24. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x6C 22. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x6C 20. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x6C 15. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_3_en_spare_dec_1" "0,1"
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bitfld.long 0x6C 14. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_3_en_spare_dec_0" "0,1"
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bitfld.long 0x6C 13. "STATUS_LEVEL_VPAC_OUT_3_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_6" "0,1"
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bitfld.long 0x6C 12. "STATUS_LEVEL_VPAC_OUT_3_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_5" "0,1"
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bitfld.long 0x6C 11. "STATUS_LEVEL_VPAC_OUT_3_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_4" "0,1"
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bitfld.long 0x6C 9. "STATUS_LEVEL_VPAC_OUT_3_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_2" "0,1"
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bitfld.long 0x6C 7. "STATUS_LEVEL_VPAC_OUT_3_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_0" "0,1"
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bitfld.long 0x6C 6. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_6" "0,1"
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bitfld.long 0x6C 5. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_5" "0,1"
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bitfld.long 0x6C 4. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_4" "0,1"
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bitfld.long 0x6C 3. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_3" "0,1"
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bitfld.long 0x6C 2. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_2" "0,1"
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bitfld.long 0x6C 1. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_1" "0,1"
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bitfld.long 0x6C 0. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x70 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_4,Status Clear Register 28"
bitfld.long 0x70 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_31" "0,1"
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bitfld.long 0x70 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_30" "0,1"
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bitfld.long 0x70 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_29" "0,1"
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bitfld.long 0x70 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_28" "0,1"
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bitfld.long 0x70 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_27" "0,1"
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bitfld.long 0x70 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_26" "0,1"
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bitfld.long 0x70 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x70 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x70 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_23" "0,1"
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bitfld.long 0x70 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x70 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x70 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_20" "0,1"
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bitfld.long 0x70 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_19" "0,1"
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bitfld.long 0x70 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_18" "0,1"
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bitfld.long 0x70 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_17" "0,1"
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bitfld.long 0x70 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_16" "0,1"
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bitfld.long 0x70 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_15" "0,1"
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bitfld.long 0x70 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_14" "0,1"
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bitfld.long 0x70 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_13" "0,1"
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bitfld.long 0x70 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_12" "0,1"
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bitfld.long 0x70 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_11" "0,1"
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bitfld.long 0x70 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_10" "0,1"
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bitfld.long 0x70 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_9" "0,1"
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bitfld.long 0x70 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_8" "0,1"
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bitfld.long 0x70 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_7" "0,1"
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bitfld.long 0x70 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_6" "0,1"
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bitfld.long 0x70 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_5" "0,1"
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bitfld.long 0x70 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_4" "0,1"
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bitfld.long 0x70 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_3" "0,1"
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bitfld.long 0x70 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_2" "0,1"
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bitfld.long 0x70 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_1" "0,1"
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bitfld.long 0x70 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_0" "0,1"
line.long 0x74 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_5,Status Clear Register 29"
bitfld.long 0x74 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_31" "0,1"
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bitfld.long 0x74 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_30" "0,1"
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bitfld.long 0x74 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_29" "0,1"
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bitfld.long 0x74 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_28" "0,1"
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bitfld.long 0x74 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_27" "0,1"
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bitfld.long 0x74 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_26" "0,1"
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bitfld.long 0x74 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x74 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_24" "0,1"
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bitfld.long 0x74 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_23" "0,1"
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bitfld.long 0x74 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_22" "0,1"
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bitfld.long 0x74 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_21" "0,1"
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bitfld.long 0x74 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_20" "0,1"
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bitfld.long 0x74 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_19" "0,1"
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bitfld.long 0x74 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_18" "0,1"
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bitfld.long 0x74 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_17" "0,1"
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bitfld.long 0x74 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_16" "0,1"
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bitfld.long 0x74 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_15" "0,1"
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bitfld.long 0x74 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_14" "0,1"
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bitfld.long 0x74 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x74 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_12" "0,1"
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bitfld.long 0x74 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_11" "0,1"
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bitfld.long 0x74 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_10" "0,1"
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bitfld.long 0x74 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_9" "0,1"
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bitfld.long 0x74 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x74 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x74 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x74 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_5" "0,1"
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bitfld.long 0x74 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_4" "0,1"
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bitfld.long 0x74 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x74 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x74 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x74 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_0" "0,1"
line.long 0x78 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_6,Status Clear Register 30"
bitfld.long 0x78 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_63" "0,1"
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bitfld.long 0x78 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_62" "0,1"
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bitfld.long 0x78 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_61" "0,1"
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bitfld.long 0x78 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_60" "0,1"
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bitfld.long 0x78 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x78 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x78 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x78 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x78 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x78 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x78 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x78 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x78 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x78 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x78 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x78 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x78 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x78 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x78 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x78 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x78 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x78 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x78 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x78 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x78 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x78 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x78 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x78 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x78 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x78 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x78 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x78 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_complete_32" "0,1"
line.long 0x7C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_3_7,Status Clear Register 31"
bitfld.long 0x7C 4. "STATUS_LEVEL_VPAC_OUT_3_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_ctm_pulse" "0,1"
newline
bitfld.long 0x7C 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x7C 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x7C 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_error" "0,1"
newline
bitfld.long 0x7C 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_error" "0,1"
line.long 0x80 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_0,Status Clear Register 32"
bitfld.long 0x80 24. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
newline
bitfld.long 0x80 23. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
newline
bitfld.long 0x80 22. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
newline
bitfld.long 0x80 21. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x80 20. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x80 19. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x80 18. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x80 17. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x80 16. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x80 15. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x80 14. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x80 13. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x80 12. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x80 11. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x80 10. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x80 9. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x80 8. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x80 7. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x80 6. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x80 5. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x80 4. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x80 3. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x80 2. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x80 1. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x80 0. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x84 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_1,Status Clear Register 33"
bitfld.long 0x84 8. "STATUS_LEVEL_VPAC_OUT_4_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x84 7. "STATUS_LEVEL_VPAC_OUT_4_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x84 6. "STATUS_LEVEL_VPAC_OUT_4_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x84 5. "STATUS_LEVEL_VPAC_OUT_4_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x84 4. "STATUS_LEVEL_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x84 3. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x84 2. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x84 1. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x84 0. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x88 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_2,Status Clear Register 34"
bitfld.long 0x88 10. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x88 9. "STATUS_LEVEL_VPAC_OUT_4_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x88 8. "STATUS_LEVEL_VPAC_OUT_4_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_4_en_nf_frame_done" "0,1"
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bitfld.long 0x88 3. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x88 2. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x88 1. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x88 0. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x8C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_3,Status Clear Register 35"
bitfld.long 0x8C 26. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x8C 25. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x8C 24. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x8C 22. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x8C 20. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x8C 15. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_4_en_spare_dec_1" "0,1"
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bitfld.long 0x8C 14. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_4_en_spare_dec_0" "0,1"
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bitfld.long 0x8C 13. "STATUS_LEVEL_VPAC_OUT_4_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_6" "0,1"
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bitfld.long 0x8C 12. "STATUS_LEVEL_VPAC_OUT_4_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_5" "0,1"
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bitfld.long 0x8C 11. "STATUS_LEVEL_VPAC_OUT_4_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_4" "0,1"
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bitfld.long 0x8C 9. "STATUS_LEVEL_VPAC_OUT_4_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_2" "0,1"
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bitfld.long 0x8C 7. "STATUS_LEVEL_VPAC_OUT_4_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_0" "0,1"
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bitfld.long 0x8C 6. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_6" "0,1"
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bitfld.long 0x8C 5. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_5" "0,1"
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bitfld.long 0x8C 4. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_4" "0,1"
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bitfld.long 0x8C 3. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_3" "0,1"
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bitfld.long 0x8C 2. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_2" "0,1"
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bitfld.long 0x8C 1. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_1" "0,1"
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bitfld.long 0x8C 0. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x90 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_4,Status Clear Register 36"
bitfld.long 0x90 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_31" "0,1"
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bitfld.long 0x90 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_30" "0,1"
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bitfld.long 0x90 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_29" "0,1"
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bitfld.long 0x90 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_28" "0,1"
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bitfld.long 0x90 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_27" "0,1"
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bitfld.long 0x90 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_26" "0,1"
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bitfld.long 0x90 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_25" "0,1"
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bitfld.long 0x90 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_24" "0,1"
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bitfld.long 0x90 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_23" "0,1"
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bitfld.long 0x90 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_22" "0,1"
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bitfld.long 0x90 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_21" "0,1"
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bitfld.long 0x90 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_20" "0,1"
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bitfld.long 0x90 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_19" "0,1"
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bitfld.long 0x90 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_18" "0,1"
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bitfld.long 0x90 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_17" "0,1"
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bitfld.long 0x90 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_16" "0,1"
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bitfld.long 0x90 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_15" "0,1"
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bitfld.long 0x90 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_14" "0,1"
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bitfld.long 0x90 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_13" "0,1"
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bitfld.long 0x90 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_12" "0,1"
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bitfld.long 0x90 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_11" "0,1"
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bitfld.long 0x90 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_10" "0,1"
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bitfld.long 0x90 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_9" "0,1"
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bitfld.long 0x90 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_8" "0,1"
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bitfld.long 0x90 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_7" "0,1"
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bitfld.long 0x90 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_6" "0,1"
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bitfld.long 0x90 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_5" "0,1"
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bitfld.long 0x90 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_4" "0,1"
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bitfld.long 0x90 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_3" "0,1"
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bitfld.long 0x90 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_2" "0,1"
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bitfld.long 0x90 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_1" "0,1"
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bitfld.long 0x90 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_0" "0,1"
line.long 0x94 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_5,Status Clear Register 37"
bitfld.long 0x94 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_31" "0,1"
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bitfld.long 0x94 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_30" "0,1"
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bitfld.long 0x94 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_29" "0,1"
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bitfld.long 0x94 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_28" "0,1"
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bitfld.long 0x94 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_27" "0,1"
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bitfld.long 0x94 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_26" "0,1"
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bitfld.long 0x94 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_25" "0,1"
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bitfld.long 0x94 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_24" "0,1"
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bitfld.long 0x94 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_23" "0,1"
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bitfld.long 0x94 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_22" "0,1"
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bitfld.long 0x94 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_21" "0,1"
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bitfld.long 0x94 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_20" "0,1"
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bitfld.long 0x94 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_19" "0,1"
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bitfld.long 0x94 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_18" "0,1"
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bitfld.long 0x94 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_17" "0,1"
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bitfld.long 0x94 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_16" "0,1"
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bitfld.long 0x94 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_15" "0,1"
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bitfld.long 0x94 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_14" "0,1"
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bitfld.long 0x94 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_13" "0,1"
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bitfld.long 0x94 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_12" "0,1"
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bitfld.long 0x94 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_11" "0,1"
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bitfld.long 0x94 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_10" "0,1"
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bitfld.long 0x94 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_9" "0,1"
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bitfld.long 0x94 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_8" "0,1"
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bitfld.long 0x94 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_7" "0,1"
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bitfld.long 0x94 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_6" "0,1"
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bitfld.long 0x94 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_5" "0,1"
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bitfld.long 0x94 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_4" "0,1"
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bitfld.long 0x94 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_3" "0,1"
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bitfld.long 0x94 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_2" "0,1"
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bitfld.long 0x94 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_1" "0,1"
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bitfld.long 0x94 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_0" "0,1"
line.long 0x98 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_6,Status Clear Register 38"
bitfld.long 0x98 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_63" "0,1"
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bitfld.long 0x98 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_62" "0,1"
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bitfld.long 0x98 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_61" "0,1"
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bitfld.long 0x98 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_60" "0,1"
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bitfld.long 0x98 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_59" "0,1"
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bitfld.long 0x98 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_58" "0,1"
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bitfld.long 0x98 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_57" "0,1"
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bitfld.long 0x98 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_56" "0,1"
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bitfld.long 0x98 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_55" "0,1"
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bitfld.long 0x98 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_54" "0,1"
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bitfld.long 0x98 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_53" "0,1"
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bitfld.long 0x98 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_52" "0,1"
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bitfld.long 0x98 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_51" "0,1"
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bitfld.long 0x98 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_50" "0,1"
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bitfld.long 0x98 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_49" "0,1"
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bitfld.long 0x98 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_48" "0,1"
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bitfld.long 0x98 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_47" "0,1"
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bitfld.long 0x98 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_46" "0,1"
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bitfld.long 0x98 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_45" "0,1"
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bitfld.long 0x98 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_44" "0,1"
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bitfld.long 0x98 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_43" "0,1"
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bitfld.long 0x98 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_42" "0,1"
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bitfld.long 0x98 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_41" "0,1"
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bitfld.long 0x98 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_40" "0,1"
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bitfld.long 0x98 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_39" "0,1"
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bitfld.long 0x98 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_38" "0,1"
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bitfld.long 0x98 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_37" "0,1"
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bitfld.long 0x98 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_36" "0,1"
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bitfld.long 0x98 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_35" "0,1"
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bitfld.long 0x98 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_34" "0,1"
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bitfld.long 0x98 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_33" "0,1"
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bitfld.long 0x98 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_complete_32" "0,1"
line.long 0x9C "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_4_7,Status Clear Register 39"
bitfld.long 0x9C 4. "STATUS_LEVEL_VPAC_OUT_4_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_ctm_pulse" "0,1"
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bitfld.long 0x9C 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_prot_err" "0,1"
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bitfld.long 0x9C 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_prot_err" "0,1"
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bitfld.long 0x9C 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_error" "0,1"
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bitfld.long 0x9C 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_error" "0,1"
line.long 0xA0 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_0,Status Clear Register 40"
bitfld.long 0xA0 24. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0xA0 23. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0xA0 22. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0xA0 21. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0xA0 20. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0xA0 19. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0xA0 18. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0xA0 17. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0xA0 16. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0xA0 15. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0xA0 14. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0xA0 13. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0xA0 12. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0xA0 11. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0xA0 10. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0xA0 9. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0xA0 8. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0xA0 7. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0xA0 6. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0xA0 5. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0xA0 4. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0xA0 3. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0xA0 2. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0xA0 1. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0xA0 0. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0xA4 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_1,Status Clear Register 41"
bitfld.long 0xA4 8. "STATUS_LEVEL_VPAC_OUT_5_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0xA4 7. "STATUS_LEVEL_VPAC_OUT_5_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0xA4 6. "STATUS_LEVEL_VPAC_OUT_5_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0xA4 5. "STATUS_LEVEL_VPAC_OUT_5_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0xA4 4. "STATUS_LEVEL_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0xA4 3. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0xA4 2. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0xA4 1. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0xA4 0. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0xA8 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_2,Status Clear Register 42"
bitfld.long 0xA8 10. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0xA8 9. "STATUS_LEVEL_VPAC_OUT_5_NF_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0xA8 8. "STATUS_LEVEL_VPAC_OUT_5_NF_FRAME_DONE_CLR,Status write 1 to clear for level_vpac_out_5_en_nf_frame_done" "0,1"
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bitfld.long 0xA8 3. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0xA8 2. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0xA8 1. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0xA8 0. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0xAC "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_3,Status Clear Register 43"
bitfld.long 0xAC 26. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0xAC 25. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0xAC 24. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0xAC 22. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0xAC 20. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0xAC 15. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_5_en_spare_dec_1" "0,1"
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bitfld.long 0xAC 14. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_5_en_spare_dec_0" "0,1"
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bitfld.long 0xAC 13. "STATUS_LEVEL_VPAC_OUT_5_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_6" "0,1"
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bitfld.long 0xAC 12. "STATUS_LEVEL_VPAC_OUT_5_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_5" "0,1"
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bitfld.long 0xAC 11. "STATUS_LEVEL_VPAC_OUT_5_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0xAC 9. "STATUS_LEVEL_VPAC_OUT_5_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0xAC 7. "STATUS_LEVEL_VPAC_OUT_5_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_0" "0,1"
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bitfld.long 0xAC 6. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_6" "0,1"
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bitfld.long 0xAC 5. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_5" "0,1"
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bitfld.long 0xAC 4. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_4" "0,1"
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bitfld.long 0xAC 3. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_3" "0,1"
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bitfld.long 0xAC 2. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_2" "0,1"
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bitfld.long 0xAC 1. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_1" "0,1"
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bitfld.long 0xAC 0. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0xB0 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_4,Status Clear Register 44"
bitfld.long 0xB0 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_31" "0,1"
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bitfld.long 0xB0 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_30" "0,1"
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bitfld.long 0xB0 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_29" "0,1"
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bitfld.long 0xB0 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_28" "0,1"
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bitfld.long 0xB0 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_27" "0,1"
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bitfld.long 0xB0 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_26" "0,1"
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bitfld.long 0xB0 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_25" "0,1"
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bitfld.long 0xB0 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_24" "0,1"
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bitfld.long 0xB0 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_23" "0,1"
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bitfld.long 0xB0 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_22" "0,1"
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bitfld.long 0xB0 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_21" "0,1"
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bitfld.long 0xB0 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_20" "0,1"
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bitfld.long 0xB0 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_19" "0,1"
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bitfld.long 0xB0 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_18" "0,1"
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bitfld.long 0xB0 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_17" "0,1"
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bitfld.long 0xB0 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_16" "0,1"
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bitfld.long 0xB0 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_15" "0,1"
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bitfld.long 0xB0 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_14" "0,1"
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bitfld.long 0xB0 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_13" "0,1"
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bitfld.long 0xB0 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_12" "0,1"
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bitfld.long 0xB0 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_11" "0,1"
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bitfld.long 0xB0 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_10" "0,1"
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bitfld.long 0xB0 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_9" "0,1"
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bitfld.long 0xB0 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_8" "0,1"
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bitfld.long 0xB0 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_7" "0,1"
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bitfld.long 0xB0 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_6" "0,1"
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bitfld.long 0xB0 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_5" "0,1"
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bitfld.long 0xB0 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_4" "0,1"
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bitfld.long 0xB0 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_3" "0,1"
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bitfld.long 0xB0 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_2" "0,1"
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bitfld.long 0xB0 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_1" "0,1"
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bitfld.long 0xB0 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_0" "0,1"
line.long 0xB4 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_5,Status Clear Register 45"
bitfld.long 0xB4 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_31" "0,1"
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bitfld.long 0xB4 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_30" "0,1"
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bitfld.long 0xB4 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_29" "0,1"
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bitfld.long 0xB4 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_28" "0,1"
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bitfld.long 0xB4 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_27" "0,1"
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bitfld.long 0xB4 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_26" "0,1"
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bitfld.long 0xB4 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_25" "0,1"
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bitfld.long 0xB4 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_24" "0,1"
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bitfld.long 0xB4 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_23" "0,1"
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bitfld.long 0xB4 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_22" "0,1"
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bitfld.long 0xB4 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_21" "0,1"
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bitfld.long 0xB4 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_20" "0,1"
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bitfld.long 0xB4 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_19" "0,1"
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bitfld.long 0xB4 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_18" "0,1"
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bitfld.long 0xB4 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_17" "0,1"
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bitfld.long 0xB4 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_16" "0,1"
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bitfld.long 0xB4 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_15" "0,1"
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bitfld.long 0xB4 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_14" "0,1"
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bitfld.long 0xB4 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_13" "0,1"
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bitfld.long 0xB4 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_12" "0,1"
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bitfld.long 0xB4 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_11" "0,1"
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bitfld.long 0xB4 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_10" "0,1"
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bitfld.long 0xB4 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_9" "0,1"
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bitfld.long 0xB4 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_8" "0,1"
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bitfld.long 0xB4 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_7" "0,1"
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bitfld.long 0xB4 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_6" "0,1"
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bitfld.long 0xB4 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_5" "0,1"
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bitfld.long 0xB4 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_4" "0,1"
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bitfld.long 0xB4 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_3" "0,1"
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bitfld.long 0xB4 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_2" "0,1"
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bitfld.long 0xB4 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_1" "0,1"
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bitfld.long 0xB4 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_0" "0,1"
line.long 0xB8 "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_6,Status Clear Register 46"
bitfld.long 0xB8 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_63" "0,1"
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bitfld.long 0xB8 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_62" "0,1"
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bitfld.long 0xB8 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_61" "0,1"
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bitfld.long 0xB8 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_60" "0,1"
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bitfld.long 0xB8 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_59" "0,1"
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bitfld.long 0xB8 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_58" "0,1"
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bitfld.long 0xB8 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_57" "0,1"
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bitfld.long 0xB8 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_56" "0,1"
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bitfld.long 0xB8 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_55" "0,1"
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bitfld.long 0xB8 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_54" "0,1"
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bitfld.long 0xB8 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_53" "0,1"
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bitfld.long 0xB8 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_52" "0,1"
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bitfld.long 0xB8 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_51" "0,1"
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bitfld.long 0xB8 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_50" "0,1"
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bitfld.long 0xB8 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_49" "0,1"
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bitfld.long 0xB8 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_48" "0,1"
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bitfld.long 0xB8 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_47" "0,1"
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bitfld.long 0xB8 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_46" "0,1"
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bitfld.long 0xB8 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_45" "0,1"
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bitfld.long 0xB8 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_44" "0,1"
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bitfld.long 0xB8 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_43" "0,1"
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bitfld.long 0xB8 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_42" "0,1"
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bitfld.long 0xB8 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_41" "0,1"
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bitfld.long 0xB8 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_40" "0,1"
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bitfld.long 0xB8 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_39" "0,1"
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bitfld.long 0xB8 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_38" "0,1"
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bitfld.long 0xB8 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_37" "0,1"
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bitfld.long 0xB8 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_36" "0,1"
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bitfld.long 0xB8 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_35" "0,1"
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bitfld.long 0xB8 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_34" "0,1"
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bitfld.long 0xB8 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_33" "0,1"
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bitfld.long 0xB8 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_complete_32" "0,1"
line.long 0xBC "VPAC_INTD_STATUS_CLR_REG_LEVEL_VPAC_OUT_5_7,Status Clear Register 47"
bitfld.long 0xBC 4. "STATUS_LEVEL_VPAC_OUT_5_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_ctm_pulse" "0,1"
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bitfld.long 0xBC 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_prot_err" "0,1"
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bitfld.long 0xBC 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_prot_err" "0,1"
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bitfld.long 0xBC 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_ERROR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_error" "0,1"
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bitfld.long 0xBC 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_error" "0,1"
line.long 0xC0 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_0,Status Clear Register 48"
bitfld.long 0xC0 24. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0xC0 23. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0xC0 22. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0xC0 21. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0xC0 20. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0xC0 19. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0xC0 18. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0xC0 17. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0xC0 16. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0xC0 15. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0xC0 14. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0xC0 13. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0xC0 12. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0xC0 11. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0xC0 10. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0xC0 9. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0xC0 8. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0xC0 7. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0xC0 6. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0xC0 5. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0xC0 4. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0xC0 3. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0xC0 2. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0xC0 1. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0xC0 0. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1"
line.long 0xC4 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_1,Status Clear Register 49"
bitfld.long 0xC4 8. "STATUS_PULSE_VPAC_OUT_0_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0xC4 7. "STATUS_PULSE_VPAC_OUT_0_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0xC4 6. "STATUS_PULSE_VPAC_OUT_0_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0xC4 5. "STATUS_PULSE_VPAC_OUT_0_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1"
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bitfld.long 0xC4 4. "STATUS_PULSE_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0xC4 3. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0xC4 2. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0xC4 1. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0xC4 0. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0xC8 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_2,Status Clear Register 50"
bitfld.long 0xC8 10. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0xC8 9. "STATUS_PULSE_VPAC_OUT_0_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0xC8 8. "STATUS_PULSE_VPAC_OUT_0_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_nf_frame_done" "0,1"
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bitfld.long 0xC8 3. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0xC8 2. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0xC8 1. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0xC8 0. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0xCC "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_3,Status Clear Register 51"
bitfld.long 0xCC 26. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0xCC 25. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0xCC 24. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0xCC 22. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0xCC 20. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0xCC 15. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_spare_dec_1" "0,1"
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bitfld.long 0xCC 14. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_spare_dec_0" "0,1"
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bitfld.long 0xCC 13. "STATUS_PULSE_VPAC_OUT_0_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_6" "0,1"
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bitfld.long 0xCC 12. "STATUS_PULSE_VPAC_OUT_0_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_5" "0,1"
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bitfld.long 0xCC 11. "STATUS_PULSE_VPAC_OUT_0_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_4" "0,1"
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bitfld.long 0xCC 9. "STATUS_PULSE_VPAC_OUT_0_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_2" "0,1"
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bitfld.long 0xCC 7. "STATUS_PULSE_VPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_0" "0,1"
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bitfld.long 0xCC 6. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_6" "0,1"
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bitfld.long 0xCC 5. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_5" "0,1"
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bitfld.long 0xCC 4. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_4" "0,1"
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bitfld.long 0xCC 3. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_3" "0,1"
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bitfld.long 0xCC 2. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_2" "0,1"
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bitfld.long 0xCC 1. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_1" "0,1"
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bitfld.long 0xCC 0. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_0" "0,1"
line.long 0xD0 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_4,Status Clear Register 52"
bitfld.long 0xD0 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_31" "0,1"
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bitfld.long 0xD0 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_30" "0,1"
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bitfld.long 0xD0 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_29" "0,1"
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bitfld.long 0xD0 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_28" "0,1"
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bitfld.long 0xD0 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_27" "0,1"
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bitfld.long 0xD0 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_26" "0,1"
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bitfld.long 0xD0 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_25" "0,1"
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bitfld.long 0xD0 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_24" "0,1"
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bitfld.long 0xD0 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_23" "0,1"
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bitfld.long 0xD0 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_22" "0,1"
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bitfld.long 0xD0 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_21" "0,1"
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bitfld.long 0xD0 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_20" "0,1"
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bitfld.long 0xD0 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_19" "0,1"
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bitfld.long 0xD0 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_18" "0,1"
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bitfld.long 0xD0 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_17" "0,1"
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bitfld.long 0xD0 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_16" "0,1"
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bitfld.long 0xD0 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_15" "0,1"
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bitfld.long 0xD0 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_14" "0,1"
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bitfld.long 0xD0 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_13" "0,1"
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bitfld.long 0xD0 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_12" "0,1"
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bitfld.long 0xD0 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_11" "0,1"
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bitfld.long 0xD0 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_10" "0,1"
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bitfld.long 0xD0 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_9" "0,1"
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bitfld.long 0xD0 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_8" "0,1"
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bitfld.long 0xD0 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_7" "0,1"
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bitfld.long 0xD0 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_6" "0,1"
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bitfld.long 0xD0 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_5" "0,1"
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bitfld.long 0xD0 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_4" "0,1"
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bitfld.long 0xD0 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_3" "0,1"
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bitfld.long 0xD0 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_2" "0,1"
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bitfld.long 0xD0 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_1" "0,1"
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bitfld.long 0xD0 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_0" "0,1"
line.long 0xD4 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_5,Status Clear Register 53"
bitfld.long 0xD4 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_31" "0,1"
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bitfld.long 0xD4 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_30" "0,1"
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bitfld.long 0xD4 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_29" "0,1"
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bitfld.long 0xD4 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_28" "0,1"
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bitfld.long 0xD4 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_27" "0,1"
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bitfld.long 0xD4 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_26" "0,1"
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bitfld.long 0xD4 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_25" "0,1"
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bitfld.long 0xD4 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_24" "0,1"
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bitfld.long 0xD4 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_23" "0,1"
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bitfld.long 0xD4 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_22" "0,1"
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bitfld.long 0xD4 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_21" "0,1"
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bitfld.long 0xD4 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_20" "0,1"
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bitfld.long 0xD4 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_19" "0,1"
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bitfld.long 0xD4 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_18" "0,1"
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bitfld.long 0xD4 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_17" "0,1"
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bitfld.long 0xD4 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_16" "0,1"
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bitfld.long 0xD4 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_15" "0,1"
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bitfld.long 0xD4 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_14" "0,1"
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bitfld.long 0xD4 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_13" "0,1"
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bitfld.long 0xD4 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_12" "0,1"
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bitfld.long 0xD4 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_11" "0,1"
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bitfld.long 0xD4 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_10" "0,1"
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bitfld.long 0xD4 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_9" "0,1"
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bitfld.long 0xD4 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_8" "0,1"
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bitfld.long 0xD4 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_7" "0,1"
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bitfld.long 0xD4 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_6" "0,1"
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bitfld.long 0xD4 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_5" "0,1"
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bitfld.long 0xD4 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_4" "0,1"
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bitfld.long 0xD4 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_3" "0,1"
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bitfld.long 0xD4 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_2" "0,1"
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bitfld.long 0xD4 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_1" "0,1"
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bitfld.long 0xD4 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_0" "0,1"
line.long 0xD8 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_6,Status Clear Register 54"
bitfld.long 0xD8 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_63" "0,1"
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bitfld.long 0xD8 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_62" "0,1"
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bitfld.long 0xD8 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_61" "0,1"
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bitfld.long 0xD8 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_60" "0,1"
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bitfld.long 0xD8 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_59" "0,1"
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bitfld.long 0xD8 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_58" "0,1"
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bitfld.long 0xD8 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_57" "0,1"
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bitfld.long 0xD8 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_56" "0,1"
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bitfld.long 0xD8 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_55" "0,1"
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bitfld.long 0xD8 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_54" "0,1"
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bitfld.long 0xD8 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_53" "0,1"
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bitfld.long 0xD8 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_52" "0,1"
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bitfld.long 0xD8 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_51" "0,1"
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bitfld.long 0xD8 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_50" "0,1"
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bitfld.long 0xD8 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_49" "0,1"
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bitfld.long 0xD8 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_48" "0,1"
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bitfld.long 0xD8 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_47" "0,1"
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bitfld.long 0xD8 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_46" "0,1"
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bitfld.long 0xD8 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_45" "0,1"
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bitfld.long 0xD8 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_44" "0,1"
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bitfld.long 0xD8 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_43" "0,1"
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bitfld.long 0xD8 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_42" "0,1"
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bitfld.long 0xD8 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_41" "0,1"
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bitfld.long 0xD8 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_40" "0,1"
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bitfld.long 0xD8 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_39" "0,1"
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bitfld.long 0xD8 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_38" "0,1"
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bitfld.long 0xD8 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_37" "0,1"
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bitfld.long 0xD8 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_36" "0,1"
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bitfld.long 0xD8 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_35" "0,1"
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bitfld.long 0xD8 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_34" "0,1"
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bitfld.long 0xD8 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_33" "0,1"
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bitfld.long 0xD8 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_complete_32" "0,1"
line.long 0xDC "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_0_7,Status Clear Register 55"
bitfld.long 0xDC 4. "STATUS_PULSE_VPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ctm_pulse" "0,1"
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bitfld.long 0xDC 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_prot_err" "0,1"
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bitfld.long 0xDC 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_prot_err" "0,1"
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bitfld.long 0xDC 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_error" "0,1"
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bitfld.long 0xDC 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_error" "0,1"
line.long 0xE0 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_0,Status Clear Register 56"
bitfld.long 0xE0 24. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0xE0 23. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0xE0 22. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0xE0 21. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0xE0 20. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0xE0 19. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0xE0 18. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0xE0 17. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0xE0 16. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0xE0 15. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0xE0 14. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0xE0 13. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0xE0 12. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0xE0 11. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0xE0 10. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0xE0 9. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0xE0 8. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0xE0 7. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0xE0 6. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0xE0 5. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0xE0 4. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0xE0 3. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0xE0 2. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0xE0 1. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0xE0 0. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1"
line.long 0xE4 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_1,Status Clear Register 57"
bitfld.long 0xE4 8. "STATUS_PULSE_VPAC_OUT_1_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0xE4 7. "STATUS_PULSE_VPAC_OUT_1_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0xE4 6. "STATUS_PULSE_VPAC_OUT_1_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0xE4 5. "STATUS_PULSE_VPAC_OUT_1_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1"
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bitfld.long 0xE4 4. "STATUS_PULSE_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0xE4 3. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0xE4 2. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0xE4 1. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0xE4 0. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0xE8 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_2,Status Clear Register 58"
bitfld.long 0xE8 10. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0xE8 9. "STATUS_PULSE_VPAC_OUT_1_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0xE8 8. "STATUS_PULSE_VPAC_OUT_1_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_nf_frame_done" "0,1"
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bitfld.long 0xE8 3. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0xE8 2. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0xE8 1. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0xE8 0. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0xEC "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_3,Status Clear Register 59"
bitfld.long 0xEC 26. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0xEC 25. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0xEC 24. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0xEC 22. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0xEC 20. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0xEC 15. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_spare_dec_1" "0,1"
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bitfld.long 0xEC 14. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_spare_dec_0" "0,1"
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bitfld.long 0xEC 13. "STATUS_PULSE_VPAC_OUT_1_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_6" "0,1"
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bitfld.long 0xEC 12. "STATUS_PULSE_VPAC_OUT_1_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_5" "0,1"
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bitfld.long 0xEC 11. "STATUS_PULSE_VPAC_OUT_1_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_4" "0,1"
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bitfld.long 0xEC 9. "STATUS_PULSE_VPAC_OUT_1_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_2" "0,1"
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bitfld.long 0xEC 7. "STATUS_PULSE_VPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_0" "0,1"
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bitfld.long 0xEC 6. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_6" "0,1"
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bitfld.long 0xEC 5. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_5" "0,1"
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bitfld.long 0xEC 4. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_4" "0,1"
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bitfld.long 0xEC 3. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_3" "0,1"
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bitfld.long 0xEC 2. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_2" "0,1"
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bitfld.long 0xEC 1. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_1" "0,1"
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bitfld.long 0xEC 0. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_0" "0,1"
line.long 0xF0 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_4,Status Clear Register 60"
bitfld.long 0xF0 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_31" "0,1"
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bitfld.long 0xF0 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_30" "0,1"
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bitfld.long 0xF0 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_29" "0,1"
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bitfld.long 0xF0 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_28" "0,1"
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bitfld.long 0xF0 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_27" "0,1"
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bitfld.long 0xF0 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_26" "0,1"
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bitfld.long 0xF0 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_25" "0,1"
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bitfld.long 0xF0 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_24" "0,1"
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bitfld.long 0xF0 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_23" "0,1"
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bitfld.long 0xF0 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_22" "0,1"
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bitfld.long 0xF0 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_21" "0,1"
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bitfld.long 0xF0 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_20" "0,1"
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bitfld.long 0xF0 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_19" "0,1"
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bitfld.long 0xF0 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_18" "0,1"
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bitfld.long 0xF0 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_17" "0,1"
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bitfld.long 0xF0 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_16" "0,1"
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bitfld.long 0xF0 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_15" "0,1"
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bitfld.long 0xF0 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_14" "0,1"
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bitfld.long 0xF0 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_13" "0,1"
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bitfld.long 0xF0 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_12" "0,1"
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bitfld.long 0xF0 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_11" "0,1"
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bitfld.long 0xF0 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_10" "0,1"
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bitfld.long 0xF0 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_9" "0,1"
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bitfld.long 0xF0 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_8" "0,1"
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bitfld.long 0xF0 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_7" "0,1"
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bitfld.long 0xF0 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_6" "0,1"
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bitfld.long 0xF0 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_5" "0,1"
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bitfld.long 0xF0 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_4" "0,1"
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bitfld.long 0xF0 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_3" "0,1"
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bitfld.long 0xF0 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_2" "0,1"
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bitfld.long 0xF0 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_1" "0,1"
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bitfld.long 0xF0 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_0" "0,1"
line.long 0xF4 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_5,Status Clear Register 61"
bitfld.long 0xF4 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_31" "0,1"
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bitfld.long 0xF4 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_30" "0,1"
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bitfld.long 0xF4 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_29" "0,1"
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bitfld.long 0xF4 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_28" "0,1"
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bitfld.long 0xF4 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_27" "0,1"
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bitfld.long 0xF4 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_26" "0,1"
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bitfld.long 0xF4 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_25" "0,1"
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bitfld.long 0xF4 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_24" "0,1"
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bitfld.long 0xF4 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_23" "0,1"
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bitfld.long 0xF4 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_22" "0,1"
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bitfld.long 0xF4 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_21" "0,1"
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bitfld.long 0xF4 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_20" "0,1"
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bitfld.long 0xF4 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_19" "0,1"
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bitfld.long 0xF4 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_18" "0,1"
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bitfld.long 0xF4 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_17" "0,1"
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bitfld.long 0xF4 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_16" "0,1"
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bitfld.long 0xF4 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_15" "0,1"
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bitfld.long 0xF4 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_14" "0,1"
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bitfld.long 0xF4 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_13" "0,1"
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bitfld.long 0xF4 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_12" "0,1"
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bitfld.long 0xF4 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_11" "0,1"
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bitfld.long 0xF4 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_10" "0,1"
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bitfld.long 0xF4 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_9" "0,1"
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bitfld.long 0xF4 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_8" "0,1"
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bitfld.long 0xF4 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_7" "0,1"
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bitfld.long 0xF4 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_6" "0,1"
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bitfld.long 0xF4 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_5" "0,1"
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bitfld.long 0xF4 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_4" "0,1"
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bitfld.long 0xF4 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_3" "0,1"
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bitfld.long 0xF4 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_2" "0,1"
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bitfld.long 0xF4 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_1" "0,1"
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bitfld.long 0xF4 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_0" "0,1"
line.long 0xF8 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_6,Status Clear Register 62"
bitfld.long 0xF8 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_63" "0,1"
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bitfld.long 0xF8 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_62" "0,1"
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bitfld.long 0xF8 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_61" "0,1"
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bitfld.long 0xF8 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_60" "0,1"
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bitfld.long 0xF8 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_59" "0,1"
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bitfld.long 0xF8 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_58" "0,1"
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bitfld.long 0xF8 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_57" "0,1"
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bitfld.long 0xF8 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_56" "0,1"
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bitfld.long 0xF8 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_55" "0,1"
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bitfld.long 0xF8 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_54" "0,1"
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bitfld.long 0xF8 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_53" "0,1"
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bitfld.long 0xF8 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_52" "0,1"
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bitfld.long 0xF8 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_51" "0,1"
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bitfld.long 0xF8 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_50" "0,1"
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bitfld.long 0xF8 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_49" "0,1"
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bitfld.long 0xF8 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_48" "0,1"
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bitfld.long 0xF8 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_47" "0,1"
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bitfld.long 0xF8 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_46" "0,1"
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bitfld.long 0xF8 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_45" "0,1"
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bitfld.long 0xF8 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_44" "0,1"
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bitfld.long 0xF8 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_43" "0,1"
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bitfld.long 0xF8 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_42" "0,1"
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bitfld.long 0xF8 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_41" "0,1"
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bitfld.long 0xF8 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_40" "0,1"
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bitfld.long 0xF8 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_39" "0,1"
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bitfld.long 0xF8 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_38" "0,1"
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bitfld.long 0xF8 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_37" "0,1"
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bitfld.long 0xF8 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_36" "0,1"
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bitfld.long 0xF8 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_35" "0,1"
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bitfld.long 0xF8 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_34" "0,1"
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bitfld.long 0xF8 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_33" "0,1"
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bitfld.long 0xF8 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_complete_32" "0,1"
line.long 0xFC "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_1_7,Status Clear Register 63"
bitfld.long 0xFC 4. "STATUS_PULSE_VPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ctm_pulse" "0,1"
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bitfld.long 0xFC 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_prot_err" "0,1"
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bitfld.long 0xFC 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_prot_err" "0,1"
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bitfld.long 0xFC 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_error" "0,1"
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bitfld.long 0xFC 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_error" "0,1"
line.long 0x100 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_0,Status Clear Register 64"
bitfld.long 0x100 24. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x100 23. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x100 22. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x100 21. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x100 20. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x100 19. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x100 18. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x100 17. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x100 16. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x100 15. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x100 14. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x100 13. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x100 12. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x100 11. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x100 10. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x100 9. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x100 8. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x100 7. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x100 6. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x100 5. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x100 4. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x100 3. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x100 2. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x100 1. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x100 0. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x104 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_1,Status Clear Register 65"
bitfld.long 0x104 8. "STATUS_PULSE_VPAC_OUT_2_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x104 7. "STATUS_PULSE_VPAC_OUT_2_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x104 6. "STATUS_PULSE_VPAC_OUT_2_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x104 5. "STATUS_PULSE_VPAC_OUT_2_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x104 4. "STATUS_PULSE_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x104 3. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x104 2. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x104 1. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x104 0. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x108 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_2,Status Clear Register 66"
bitfld.long 0x108 10. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x108 9. "STATUS_PULSE_VPAC_OUT_2_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x108 8. "STATUS_PULSE_VPAC_OUT_2_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_nf_frame_done" "0,1"
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bitfld.long 0x108 3. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x108 2. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x108 1. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x108 0. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x10C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_3,Status Clear Register 67"
bitfld.long 0x10C 26. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x10C 25. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x10C 24. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x10C 22. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x10C 20. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x10C 15. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_spare_dec_1" "0,1"
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bitfld.long 0x10C 14. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_spare_dec_0" "0,1"
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bitfld.long 0x10C 13. "STATUS_PULSE_VPAC_OUT_2_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_6" "0,1"
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bitfld.long 0x10C 12. "STATUS_PULSE_VPAC_OUT_2_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_5" "0,1"
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bitfld.long 0x10C 11. "STATUS_PULSE_VPAC_OUT_2_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_4" "0,1"
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bitfld.long 0x10C 9. "STATUS_PULSE_VPAC_OUT_2_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_2" "0,1"
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bitfld.long 0x10C 7. "STATUS_PULSE_VPAC_OUT_2_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_0" "0,1"
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bitfld.long 0x10C 6. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_6" "0,1"
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bitfld.long 0x10C 5. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_5" "0,1"
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bitfld.long 0x10C 4. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_4" "0,1"
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bitfld.long 0x10C 3. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_3" "0,1"
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bitfld.long 0x10C 2. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_2" "0,1"
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bitfld.long 0x10C 1. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_1" "0,1"
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bitfld.long 0x10C 0. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_0" "0,1"
line.long 0x110 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_4,Status Clear Register 68"
bitfld.long 0x110 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_31" "0,1"
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bitfld.long 0x110 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_30" "0,1"
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bitfld.long 0x110 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_29" "0,1"
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bitfld.long 0x110 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_28" "0,1"
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bitfld.long 0x110 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_27" "0,1"
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bitfld.long 0x110 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_26" "0,1"
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bitfld.long 0x110 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_25" "0,1"
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bitfld.long 0x110 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_24" "0,1"
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bitfld.long 0x110 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_23" "0,1"
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bitfld.long 0x110 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_22" "0,1"
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bitfld.long 0x110 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_21" "0,1"
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bitfld.long 0x110 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_20" "0,1"
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bitfld.long 0x110 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_19" "0,1"
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bitfld.long 0x110 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_18" "0,1"
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bitfld.long 0x110 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_17" "0,1"
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bitfld.long 0x110 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_16" "0,1"
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bitfld.long 0x110 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_15" "0,1"
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bitfld.long 0x110 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_14" "0,1"
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bitfld.long 0x110 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_13" "0,1"
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bitfld.long 0x110 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_12" "0,1"
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bitfld.long 0x110 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_11" "0,1"
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bitfld.long 0x110 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_10" "0,1"
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bitfld.long 0x110 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_9" "0,1"
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bitfld.long 0x110 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_8" "0,1"
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bitfld.long 0x110 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_7" "0,1"
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bitfld.long 0x110 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_6" "0,1"
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bitfld.long 0x110 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_5" "0,1"
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bitfld.long 0x110 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_4" "0,1"
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bitfld.long 0x110 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_3" "0,1"
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bitfld.long 0x110 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_2" "0,1"
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bitfld.long 0x110 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_1" "0,1"
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bitfld.long 0x110 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_0" "0,1"
line.long 0x114 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_5,Status Clear Register 69"
bitfld.long 0x114 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_31" "0,1"
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bitfld.long 0x114 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_30" "0,1"
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bitfld.long 0x114 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_29" "0,1"
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bitfld.long 0x114 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_28" "0,1"
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bitfld.long 0x114 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_27" "0,1"
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bitfld.long 0x114 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_26" "0,1"
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bitfld.long 0x114 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_25" "0,1"
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bitfld.long 0x114 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_24" "0,1"
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bitfld.long 0x114 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_23" "0,1"
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bitfld.long 0x114 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_22" "0,1"
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bitfld.long 0x114 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_21" "0,1"
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bitfld.long 0x114 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_20" "0,1"
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bitfld.long 0x114 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_19" "0,1"
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bitfld.long 0x114 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_18" "0,1"
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bitfld.long 0x114 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_17" "0,1"
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bitfld.long 0x114 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_16" "0,1"
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bitfld.long 0x114 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_15" "0,1"
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bitfld.long 0x114 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_14" "0,1"
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bitfld.long 0x114 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_13" "0,1"
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bitfld.long 0x114 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_12" "0,1"
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bitfld.long 0x114 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_11" "0,1"
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bitfld.long 0x114 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_10" "0,1"
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bitfld.long 0x114 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_9" "0,1"
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bitfld.long 0x114 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_8" "0,1"
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bitfld.long 0x114 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_7" "0,1"
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bitfld.long 0x114 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_6" "0,1"
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bitfld.long 0x114 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_5" "0,1"
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bitfld.long 0x114 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_4" "0,1"
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bitfld.long 0x114 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_3" "0,1"
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bitfld.long 0x114 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_2" "0,1"
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bitfld.long 0x114 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_1" "0,1"
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bitfld.long 0x114 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_0" "0,1"
line.long 0x118 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_6,Status Clear Register 70"
bitfld.long 0x118 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_63" "0,1"
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bitfld.long 0x118 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_62" "0,1"
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bitfld.long 0x118 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_61" "0,1"
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bitfld.long 0x118 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_60" "0,1"
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bitfld.long 0x118 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_59" "0,1"
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bitfld.long 0x118 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_58" "0,1"
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bitfld.long 0x118 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_57" "0,1"
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bitfld.long 0x118 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_56" "0,1"
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bitfld.long 0x118 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_55" "0,1"
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bitfld.long 0x118 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_54" "0,1"
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bitfld.long 0x118 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_53" "0,1"
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bitfld.long 0x118 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_52" "0,1"
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bitfld.long 0x118 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_51" "0,1"
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bitfld.long 0x118 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_50" "0,1"
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bitfld.long 0x118 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_49" "0,1"
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bitfld.long 0x118 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_48" "0,1"
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bitfld.long 0x118 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_47" "0,1"
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bitfld.long 0x118 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_46" "0,1"
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bitfld.long 0x118 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_45" "0,1"
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bitfld.long 0x118 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_44" "0,1"
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bitfld.long 0x118 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_43" "0,1"
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bitfld.long 0x118 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_42" "0,1"
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bitfld.long 0x118 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_41" "0,1"
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bitfld.long 0x118 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_40" "0,1"
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bitfld.long 0x118 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_39" "0,1"
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bitfld.long 0x118 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_38" "0,1"
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bitfld.long 0x118 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_37" "0,1"
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bitfld.long 0x118 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_36" "0,1"
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bitfld.long 0x118 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_35" "0,1"
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bitfld.long 0x118 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_34" "0,1"
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bitfld.long 0x118 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_33" "0,1"
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bitfld.long 0x118 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_complete_32" "0,1"
line.long 0x11C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_2_7,Status Clear Register 71"
bitfld.long 0x11C 4. "STATUS_PULSE_VPAC_OUT_2_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ctm_pulse" "0,1"
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bitfld.long 0x11C 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_prot_err" "0,1"
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bitfld.long 0x11C 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_prot_err" "0,1"
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bitfld.long 0x11C 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_error" "0,1"
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bitfld.long 0x11C 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_error" "0,1"
line.long 0x120 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_0,Status Clear Register 72"
bitfld.long 0x120 24. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x120 23. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x120 22. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x120 21. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x120 20. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x120 19. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x120 18. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x120 17. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x120 16. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x120 15. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x120 14. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x120 13. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x120 12. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x120 11. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x120 10. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x120 9. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x120 8. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x120 7. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x120 6. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x120 5. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x120 4. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x120 3. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x120 2. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x120 1. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x120 0. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x124 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_1,Status Clear Register 73"
bitfld.long 0x124 8. "STATUS_PULSE_VPAC_OUT_3_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x124 7. "STATUS_PULSE_VPAC_OUT_3_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x124 6. "STATUS_PULSE_VPAC_OUT_3_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x124 5. "STATUS_PULSE_VPAC_OUT_3_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x124 4. "STATUS_PULSE_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x124 3. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x124 2. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x124 1. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x124 0. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x128 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_2,Status Clear Register 74"
bitfld.long 0x128 10. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x128 9. "STATUS_PULSE_VPAC_OUT_3_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x128 8. "STATUS_PULSE_VPAC_OUT_3_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_nf_frame_done" "0,1"
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bitfld.long 0x128 3. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x128 2. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x128 1. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x128 0. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x12C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_3,Status Clear Register 75"
bitfld.long 0x12C 26. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x12C 25. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x12C 24. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x12C 22. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x12C 20. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x12C 15. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_spare_dec_1" "0,1"
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bitfld.long 0x12C 14. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_spare_dec_0" "0,1"
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bitfld.long 0x12C 13. "STATUS_PULSE_VPAC_OUT_3_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_6" "0,1"
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bitfld.long 0x12C 12. "STATUS_PULSE_VPAC_OUT_3_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_5" "0,1"
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bitfld.long 0x12C 11. "STATUS_PULSE_VPAC_OUT_3_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_4" "0,1"
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bitfld.long 0x12C 9. "STATUS_PULSE_VPAC_OUT_3_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_2" "0,1"
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bitfld.long 0x12C 7. "STATUS_PULSE_VPAC_OUT_3_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_0" "0,1"
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bitfld.long 0x12C 6. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_6" "0,1"
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bitfld.long 0x12C 5. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_5" "0,1"
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bitfld.long 0x12C 4. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_4" "0,1"
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bitfld.long 0x12C 3. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_3" "0,1"
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bitfld.long 0x12C 2. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_2" "0,1"
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bitfld.long 0x12C 1. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_1" "0,1"
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bitfld.long 0x12C 0. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_0" "0,1"
line.long 0x130 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_4,Status Clear Register 76"
bitfld.long 0x130 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_31" "0,1"
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bitfld.long 0x130 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_30" "0,1"
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bitfld.long 0x130 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_29" "0,1"
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bitfld.long 0x130 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_28" "0,1"
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bitfld.long 0x130 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_27" "0,1"
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bitfld.long 0x130 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_26" "0,1"
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bitfld.long 0x130 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_25" "0,1"
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bitfld.long 0x130 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_24" "0,1"
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bitfld.long 0x130 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_23" "0,1"
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bitfld.long 0x130 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_22" "0,1"
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bitfld.long 0x130 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_21" "0,1"
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bitfld.long 0x130 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_20" "0,1"
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bitfld.long 0x130 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_19" "0,1"
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bitfld.long 0x130 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_18" "0,1"
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bitfld.long 0x130 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_17" "0,1"
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bitfld.long 0x130 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_16" "0,1"
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bitfld.long 0x130 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_15" "0,1"
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bitfld.long 0x130 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_14" "0,1"
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bitfld.long 0x130 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_13" "0,1"
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bitfld.long 0x130 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_12" "0,1"
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bitfld.long 0x130 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_11" "0,1"
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bitfld.long 0x130 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_10" "0,1"
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bitfld.long 0x130 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_9" "0,1"
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bitfld.long 0x130 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_8" "0,1"
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bitfld.long 0x130 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_7" "0,1"
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bitfld.long 0x130 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_6" "0,1"
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bitfld.long 0x130 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_5" "0,1"
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bitfld.long 0x130 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_4" "0,1"
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bitfld.long 0x130 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_3" "0,1"
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bitfld.long 0x130 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_2" "0,1"
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bitfld.long 0x130 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_1" "0,1"
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bitfld.long 0x130 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_0" "0,1"
line.long 0x134 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_5,Status Clear Register 77"
bitfld.long 0x134 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_31" "0,1"
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bitfld.long 0x134 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_30" "0,1"
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bitfld.long 0x134 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_29" "0,1"
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bitfld.long 0x134 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_28" "0,1"
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bitfld.long 0x134 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_27" "0,1"
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bitfld.long 0x134 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_26" "0,1"
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bitfld.long 0x134 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_25" "0,1"
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bitfld.long 0x134 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_24" "0,1"
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bitfld.long 0x134 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_23" "0,1"
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bitfld.long 0x134 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_22" "0,1"
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bitfld.long 0x134 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_21" "0,1"
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bitfld.long 0x134 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_20" "0,1"
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bitfld.long 0x134 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_19" "0,1"
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bitfld.long 0x134 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_18" "0,1"
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bitfld.long 0x134 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_17" "0,1"
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bitfld.long 0x134 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_16" "0,1"
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bitfld.long 0x134 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_15" "0,1"
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bitfld.long 0x134 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_14" "0,1"
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bitfld.long 0x134 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_13" "0,1"
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bitfld.long 0x134 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_12" "0,1"
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bitfld.long 0x134 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_11" "0,1"
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bitfld.long 0x134 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_10" "0,1"
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bitfld.long 0x134 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_9" "0,1"
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bitfld.long 0x134 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_8" "0,1"
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bitfld.long 0x134 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_7" "0,1"
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bitfld.long 0x134 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_6" "0,1"
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bitfld.long 0x134 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_5" "0,1"
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bitfld.long 0x134 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_4" "0,1"
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bitfld.long 0x134 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_3" "0,1"
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bitfld.long 0x134 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_2" "0,1"
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bitfld.long 0x134 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_1" "0,1"
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bitfld.long 0x134 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_0" "0,1"
line.long 0x138 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_6,Status Clear Register 78"
bitfld.long 0x138 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_63" "0,1"
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bitfld.long 0x138 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_62" "0,1"
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bitfld.long 0x138 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_61" "0,1"
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bitfld.long 0x138 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_60" "0,1"
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bitfld.long 0x138 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_59" "0,1"
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bitfld.long 0x138 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_58" "0,1"
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bitfld.long 0x138 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_57" "0,1"
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bitfld.long 0x138 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_56" "0,1"
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bitfld.long 0x138 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_55" "0,1"
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bitfld.long 0x138 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_54" "0,1"
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bitfld.long 0x138 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_53" "0,1"
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bitfld.long 0x138 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_52" "0,1"
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bitfld.long 0x138 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_51" "0,1"
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bitfld.long 0x138 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_50" "0,1"
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bitfld.long 0x138 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_49" "0,1"
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bitfld.long 0x138 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_48" "0,1"
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bitfld.long 0x138 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_47" "0,1"
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bitfld.long 0x138 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_46" "0,1"
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bitfld.long 0x138 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_45" "0,1"
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bitfld.long 0x138 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_44" "0,1"
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bitfld.long 0x138 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_43" "0,1"
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bitfld.long 0x138 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_42" "0,1"
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bitfld.long 0x138 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_41" "0,1"
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bitfld.long 0x138 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_40" "0,1"
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bitfld.long 0x138 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_39" "0,1"
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bitfld.long 0x138 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_38" "0,1"
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bitfld.long 0x138 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_37" "0,1"
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bitfld.long 0x138 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_36" "0,1"
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bitfld.long 0x138 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x138 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_34" "0,1"
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bitfld.long 0x138 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_33" "0,1"
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bitfld.long 0x138 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_complete_32" "0,1"
line.long 0x13C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_3_7,Status Clear Register 79"
bitfld.long 0x13C 4. "STATUS_PULSE_VPAC_OUT_3_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ctm_pulse" "0,1"
newline
bitfld.long 0x13C 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_prot_err" "0,1"
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bitfld.long 0x13C 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x13C 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_error" "0,1"
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bitfld.long 0x13C 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_error" "0,1"
line.long 0x140 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_0,Status Clear Register 80"
bitfld.long 0x140 24. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x140 23. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x140 22. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x140 21. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x140 20. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x140 19. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x140 18. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x140 17. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x140 16. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x140 15. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x140 14. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x140 13. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x140 12. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x140 11. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x140 10. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x140 9. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x140 8. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x140 7. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x140 6. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x140 5. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x140 4. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x140 3. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x140 2. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x140 1. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x140 0. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x144 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_1,Status Clear Register 81"
bitfld.long 0x144 8. "STATUS_PULSE_VPAC_OUT_4_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x144 7. "STATUS_PULSE_VPAC_OUT_4_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x144 6. "STATUS_PULSE_VPAC_OUT_4_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x144 5. "STATUS_PULSE_VPAC_OUT_4_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x144 4. "STATUS_PULSE_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x144 3. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x144 2. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x144 1. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x144 0. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x148 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_2,Status Clear Register 82"
bitfld.long 0x148 10. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x148 9. "STATUS_PULSE_VPAC_OUT_4_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x148 8. "STATUS_PULSE_VPAC_OUT_4_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_nf_frame_done" "0,1"
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bitfld.long 0x148 3. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x148 2. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x148 1. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x148 0. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x14C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_3,Status Clear Register 83"
bitfld.long 0x14C 26. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x14C 25. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x14C 24. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x14C 22. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x14C 20. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x14C 15. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_spare_dec_1" "0,1"
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bitfld.long 0x14C 14. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_spare_dec_0" "0,1"
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bitfld.long 0x14C 13. "STATUS_PULSE_VPAC_OUT_4_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_6" "0,1"
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bitfld.long 0x14C 12. "STATUS_PULSE_VPAC_OUT_4_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_5" "0,1"
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bitfld.long 0x14C 11. "STATUS_PULSE_VPAC_OUT_4_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_4" "0,1"
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bitfld.long 0x14C 9. "STATUS_PULSE_VPAC_OUT_4_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_2" "0,1"
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bitfld.long 0x14C 7. "STATUS_PULSE_VPAC_OUT_4_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_0" "0,1"
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bitfld.long 0x14C 6. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_6" "0,1"
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bitfld.long 0x14C 5. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_5" "0,1"
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bitfld.long 0x14C 4. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_4" "0,1"
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bitfld.long 0x14C 3. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_3" "0,1"
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bitfld.long 0x14C 2. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_2" "0,1"
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bitfld.long 0x14C 1. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_1" "0,1"
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bitfld.long 0x14C 0. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_0" "0,1"
line.long 0x150 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_4,Status Clear Register 84"
bitfld.long 0x150 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_31" "0,1"
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bitfld.long 0x150 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_30" "0,1"
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bitfld.long 0x150 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_29" "0,1"
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bitfld.long 0x150 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_28" "0,1"
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bitfld.long 0x150 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_27" "0,1"
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bitfld.long 0x150 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_26" "0,1"
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bitfld.long 0x150 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_25" "0,1"
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bitfld.long 0x150 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_24" "0,1"
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bitfld.long 0x150 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_23" "0,1"
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bitfld.long 0x150 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_22" "0,1"
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bitfld.long 0x150 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_21" "0,1"
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bitfld.long 0x150 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_20" "0,1"
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bitfld.long 0x150 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_19" "0,1"
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bitfld.long 0x150 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_18" "0,1"
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bitfld.long 0x150 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_17" "0,1"
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bitfld.long 0x150 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_16" "0,1"
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bitfld.long 0x150 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_15" "0,1"
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bitfld.long 0x150 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_14" "0,1"
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bitfld.long 0x150 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_13" "0,1"
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bitfld.long 0x150 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_12" "0,1"
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bitfld.long 0x150 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_11" "0,1"
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bitfld.long 0x150 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_10" "0,1"
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bitfld.long 0x150 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_9" "0,1"
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bitfld.long 0x150 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_8" "0,1"
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bitfld.long 0x150 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_7" "0,1"
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bitfld.long 0x150 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_6" "0,1"
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bitfld.long 0x150 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_5" "0,1"
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bitfld.long 0x150 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_4" "0,1"
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bitfld.long 0x150 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_3" "0,1"
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bitfld.long 0x150 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_2" "0,1"
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bitfld.long 0x150 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_1" "0,1"
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bitfld.long 0x150 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_0" "0,1"
line.long 0x154 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_5,Status Clear Register 85"
bitfld.long 0x154 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_31" "0,1"
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bitfld.long 0x154 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_30" "0,1"
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bitfld.long 0x154 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_29" "0,1"
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bitfld.long 0x154 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_28" "0,1"
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bitfld.long 0x154 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_27" "0,1"
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bitfld.long 0x154 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_26" "0,1"
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bitfld.long 0x154 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_25" "0,1"
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bitfld.long 0x154 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_24" "0,1"
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bitfld.long 0x154 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_23" "0,1"
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bitfld.long 0x154 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_22" "0,1"
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bitfld.long 0x154 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_21" "0,1"
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bitfld.long 0x154 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_20" "0,1"
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bitfld.long 0x154 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_19" "0,1"
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bitfld.long 0x154 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_18" "0,1"
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bitfld.long 0x154 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_17" "0,1"
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bitfld.long 0x154 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_16" "0,1"
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bitfld.long 0x154 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_15" "0,1"
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bitfld.long 0x154 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_14" "0,1"
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bitfld.long 0x154 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_13" "0,1"
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bitfld.long 0x154 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_12" "0,1"
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bitfld.long 0x154 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_11" "0,1"
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bitfld.long 0x154 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_10" "0,1"
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bitfld.long 0x154 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_9" "0,1"
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bitfld.long 0x154 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_8" "0,1"
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bitfld.long 0x154 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_7" "0,1"
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bitfld.long 0x154 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_6" "0,1"
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bitfld.long 0x154 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_5" "0,1"
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bitfld.long 0x154 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_4" "0,1"
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bitfld.long 0x154 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_3" "0,1"
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bitfld.long 0x154 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_2" "0,1"
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bitfld.long 0x154 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_1" "0,1"
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bitfld.long 0x154 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_0" "0,1"
line.long 0x158 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_6,Status Clear Register 86"
bitfld.long 0x158 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_63" "0,1"
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bitfld.long 0x158 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_62" "0,1"
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bitfld.long 0x158 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_61" "0,1"
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bitfld.long 0x158 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_60" "0,1"
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bitfld.long 0x158 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_59" "0,1"
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bitfld.long 0x158 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_58" "0,1"
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bitfld.long 0x158 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_57" "0,1"
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bitfld.long 0x158 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_56" "0,1"
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bitfld.long 0x158 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_55" "0,1"
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bitfld.long 0x158 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_54" "0,1"
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bitfld.long 0x158 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_53" "0,1"
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bitfld.long 0x158 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_52" "0,1"
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bitfld.long 0x158 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_51" "0,1"
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bitfld.long 0x158 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_50" "0,1"
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bitfld.long 0x158 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_49" "0,1"
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bitfld.long 0x158 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_48" "0,1"
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bitfld.long 0x158 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_47" "0,1"
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bitfld.long 0x158 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_46" "0,1"
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bitfld.long 0x158 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_45" "0,1"
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bitfld.long 0x158 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_44" "0,1"
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bitfld.long 0x158 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_43" "0,1"
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bitfld.long 0x158 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_42" "0,1"
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bitfld.long 0x158 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_41" "0,1"
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bitfld.long 0x158 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_40" "0,1"
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bitfld.long 0x158 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_39" "0,1"
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bitfld.long 0x158 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_38" "0,1"
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bitfld.long 0x158 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_37" "0,1"
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bitfld.long 0x158 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_36" "0,1"
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bitfld.long 0x158 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_35" "0,1"
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bitfld.long 0x158 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_34" "0,1"
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bitfld.long 0x158 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_33" "0,1"
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bitfld.long 0x158 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_complete_32" "0,1"
line.long 0x15C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_4_7,Status Clear Register 87"
bitfld.long 0x15C 4. "STATUS_PULSE_VPAC_OUT_4_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ctm_pulse" "0,1"
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bitfld.long 0x15C 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_prot_err" "0,1"
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bitfld.long 0x15C 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_prot_err" "0,1"
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bitfld.long 0x15C 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_error" "0,1"
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bitfld.long 0x15C 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_error" "0,1"
line.long 0x160 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_0,Status Clear Register 88"
bitfld.long 0x160 24. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1"
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bitfld.long 0x160 23. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1"
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bitfld.long 0x160 22. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1"
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bitfld.long 0x160 21. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1"
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bitfld.long 0x160 20. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1"
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bitfld.long 0x160 19. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1"
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bitfld.long 0x160 18. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1"
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bitfld.long 0x160 17. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1"
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bitfld.long 0x160 16. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1"
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bitfld.long 0x160 15. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1"
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bitfld.long 0x160 14. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1"
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bitfld.long 0x160 13. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1"
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bitfld.long 0x160 12. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1"
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bitfld.long 0x160 11. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1"
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bitfld.long 0x160 10. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1"
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bitfld.long 0x160 9. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1"
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bitfld.long 0x160 8. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1"
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bitfld.long 0x160 7. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1"
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bitfld.long 0x160 6. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1"
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bitfld.long 0x160 5. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1"
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bitfld.long 0x160 4. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1"
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bitfld.long 0x160 3. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1"
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bitfld.long 0x160 2. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1"
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bitfld.long 0x160 1. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1"
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bitfld.long 0x160 0. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1"
line.long 0x164 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_1,Status Clear Register 89"
bitfld.long 0x164 8. "STATUS_PULSE_VPAC_OUT_5_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1"
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bitfld.long 0x164 7. "STATUS_PULSE_VPAC_OUT_5_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1"
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bitfld.long 0x164 6. "STATUS_PULSE_VPAC_OUT_5_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1"
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bitfld.long 0x164 5. "STATUS_PULSE_VPAC_OUT_5_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1"
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bitfld.long 0x164 4. "STATUS_PULSE_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1"
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bitfld.long 0x164 3. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1"
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bitfld.long 0x164 2. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1"
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bitfld.long 0x164 1. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1"
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bitfld.long 0x164 0. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1"
line.long 0x168 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_2,Status Clear Register 90"
bitfld.long 0x168 10. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_nf_sl2_rd_err" "0,1"
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bitfld.long 0x168 9. "STATUS_PULSE_VPAC_OUT_5_NF_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_nf_sl2_wr_err" "0,1"
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bitfld.long 0x168 8. "STATUS_PULSE_VPAC_OUT_5_NF_FRAME_DONE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_nf_frame_done" "0,1"
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bitfld.long 0x168 3. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1"
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bitfld.long 0x168 2. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1"
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bitfld.long 0x168 1. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1"
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bitfld.long 0x168 0. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1"
line.long 0x16C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_3,Status Clear Register 91"
bitfld.long 0x16C 26. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1"
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bitfld.long 0x16C 25. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1"
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bitfld.long 0x16C 24. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1"
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bitfld.long 0x16C 22. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1"
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bitfld.long 0x16C 20. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1"
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bitfld.long 0x16C 15. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_spare_dec_1" "0,1"
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bitfld.long 0x16C 14. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_spare_dec_0" "0,1"
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bitfld.long 0x16C 13. "STATUS_PULSE_VPAC_OUT_5_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_6" "0,1"
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bitfld.long 0x16C 12. "STATUS_PULSE_VPAC_OUT_5_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_5" "0,1"
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bitfld.long 0x16C 11. "STATUS_PULSE_VPAC_OUT_5_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_4" "0,1"
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bitfld.long 0x16C 9. "STATUS_PULSE_VPAC_OUT_5_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_2" "0,1"
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bitfld.long 0x16C 7. "STATUS_PULSE_VPAC_OUT_5_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_0" "0,1"
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bitfld.long 0x16C 6. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_6" "0,1"
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bitfld.long 0x16C 5. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_5" "0,1"
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bitfld.long 0x16C 4. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_4" "0,1"
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bitfld.long 0x16C 3. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_3" "0,1"
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bitfld.long 0x16C 2. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_2" "0,1"
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bitfld.long 0x16C 1. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_1" "0,1"
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bitfld.long 0x16C 0. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_0" "0,1"
line.long 0x170 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_4,Status Clear Register 92"
bitfld.long 0x170 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_31" "0,1"
newline
bitfld.long 0x170 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_30" "0,1"
newline
bitfld.long 0x170 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_29" "0,1"
newline
bitfld.long 0x170 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_28" "0,1"
newline
bitfld.long 0x170 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_27" "0,1"
newline
bitfld.long 0x170 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_26" "0,1"
newline
bitfld.long 0x170 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_25" "0,1"
newline
bitfld.long 0x170 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_24" "0,1"
newline
bitfld.long 0x170 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_23" "0,1"
newline
bitfld.long 0x170 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_22" "0,1"
newline
bitfld.long 0x170 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_21" "0,1"
newline
bitfld.long 0x170 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_20" "0,1"
newline
bitfld.long 0x170 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_19" "0,1"
newline
bitfld.long 0x170 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_18" "0,1"
newline
bitfld.long 0x170 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_17" "0,1"
newline
bitfld.long 0x170 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_16" "0,1"
newline
bitfld.long 0x170 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_15" "0,1"
newline
bitfld.long 0x170 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_14" "0,1"
newline
bitfld.long 0x170 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_13" "0,1"
newline
bitfld.long 0x170 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_12" "0,1"
newline
bitfld.long 0x170 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_11" "0,1"
newline
bitfld.long 0x170 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_10" "0,1"
newline
bitfld.long 0x170 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_9" "0,1"
newline
bitfld.long 0x170 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_8" "0,1"
newline
bitfld.long 0x170 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_7" "0,1"
newline
bitfld.long 0x170 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_6" "0,1"
newline
bitfld.long 0x170 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_5" "0,1"
newline
bitfld.long 0x170 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_4" "0,1"
newline
bitfld.long 0x170 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_3" "0,1"
newline
bitfld.long 0x170 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_2" "0,1"
newline
bitfld.long 0x170 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_1" "0,1"
newline
bitfld.long 0x170 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_0" "0,1"
line.long 0x174 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_5,Status Clear Register 93"
bitfld.long 0x174 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_31" "0,1"
newline
bitfld.long 0x174 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x174 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_29" "0,1"
newline
bitfld.long 0x174 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x174 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_27" "0,1"
newline
bitfld.long 0x174 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x174 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_25" "0,1"
newline
bitfld.long 0x174 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x174 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_23" "0,1"
newline
bitfld.long 0x174 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x174 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_21" "0,1"
newline
bitfld.long 0x174 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x174 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_19" "0,1"
newline
bitfld.long 0x174 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x174 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_17" "0,1"
newline
bitfld.long 0x174 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x174 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_15" "0,1"
newline
bitfld.long 0x174 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x174 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_13" "0,1"
newline
bitfld.long 0x174 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x174 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_11" "0,1"
newline
bitfld.long 0x174 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x174 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_9" "0,1"
newline
bitfld.long 0x174 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x174 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_7" "0,1"
newline
bitfld.long 0x174 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x174 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_5" "0,1"
newline
bitfld.long 0x174 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x174 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_3" "0,1"
newline
bitfld.long 0x174 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x174 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_1" "0,1"
newline
bitfld.long 0x174 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_0" "0,1"
line.long 0x178 "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_6,Status Clear Register 94"
bitfld.long 0x178 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_63" "0,1"
newline
bitfld.long 0x178 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_62" "0,1"
newline
bitfld.long 0x178 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_61" "0,1"
newline
bitfld.long 0x178 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_60" "0,1"
newline
bitfld.long 0x178 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_59" "0,1"
newline
bitfld.long 0x178 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_58" "0,1"
newline
bitfld.long 0x178 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_57" "0,1"
newline
bitfld.long 0x178 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_56" "0,1"
newline
bitfld.long 0x178 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_55" "0,1"
newline
bitfld.long 0x178 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_54" "0,1"
newline
bitfld.long 0x178 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_53" "0,1"
newline
bitfld.long 0x178 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_52" "0,1"
newline
bitfld.long 0x178 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_51" "0,1"
newline
bitfld.long 0x178 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_50" "0,1"
newline
bitfld.long 0x178 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_49" "0,1"
newline
bitfld.long 0x178 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_48" "0,1"
newline
bitfld.long 0x178 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_47" "0,1"
newline
bitfld.long 0x178 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_46" "0,1"
newline
bitfld.long 0x178 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_45" "0,1"
newline
bitfld.long 0x178 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_44" "0,1"
newline
bitfld.long 0x178 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_43" "0,1"
newline
bitfld.long 0x178 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_42" "0,1"
newline
bitfld.long 0x178 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_41" "0,1"
newline
bitfld.long 0x178 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_40" "0,1"
newline
bitfld.long 0x178 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_39" "0,1"
newline
bitfld.long 0x178 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_38" "0,1"
newline
bitfld.long 0x178 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_37" "0,1"
newline
bitfld.long 0x178 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_36" "0,1"
newline
bitfld.long 0x178 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_35" "0,1"
newline
bitfld.long 0x178 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_34" "0,1"
newline
bitfld.long 0x178 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_33" "0,1"
newline
bitfld.long 0x178 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_complete_32" "0,1"
line.long 0x17C "VPAC_INTD_STATUS_CLR_REG_PULSE_VPAC_OUT_5_7,Status Clear Register 95"
bitfld.long 0x17C 4. "STATUS_PULSE_VPAC_OUT_5_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ctm_pulse" "0,1"
newline
bitfld.long 0x17C 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_prot_err" "0,1"
newline
bitfld.long 0x17C 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_prot_err" "0,1"
newline
bitfld.long 0x17C 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_error" "0,1"
newline
bitfld.long 0x17C 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_error" "0,1"
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
rgroup.long ($2+0xA98)++0x03
line.long 0x00 "VPAC_INTD_INTR_VECTOR_REG_PULSE_VPAC_OUT_$1,Interrupt Vector for pulse_vpac_out_0"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
rgroup.long ($2+0xA80)++0x03
line.long 0x00 "VPAC_INTD_INTR_VECTOR_REG_LEVEL_VPAC_OUT_$1,Interrupt Vector for level_vpac_out_0"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x674)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_5_$1,Status Register 93"
bitfld.long 0x00 31. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_5_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x654)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_4_$1,Status Register 85"
bitfld.long 0x00 31. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_4_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x634)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_3_$1,Status Register 77"
bitfld.long 0x00 31. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_3_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x614)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_2_$1,Status Register 69"
bitfld.long 0x00 31. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_2_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x5F4)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_1_$1,Status Register 61"
bitfld.long 0x00 31. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_1_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x5D4)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_PULSE_VPAC_OUT_0_$1,Status Register 53"
bitfld.long 0x00 31. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_31,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_30,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_29,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_28,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_27,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_26,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_25,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_24,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_23,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_22,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_21,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_20,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_19,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_18,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_17,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_16,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_15,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_14,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_13,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_12,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_11,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_10,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_9,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_8,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_7,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_6,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_5,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_4,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_3,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_2,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_1,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_COMPLETE_0,Status write 1 to set for pulse_vpac_out_0_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x5B4)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_5_$1,Status Register 45"
bitfld.long 0x00 31. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_5_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_5_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_5_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_5_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_5_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_5_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_5_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_5_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_5_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_5_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_5_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_5_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_5_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_5_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_5_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_5_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_5_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_5_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_5_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_5_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_5_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_5_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_5_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_5_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_5_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_5_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_5_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_5_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_5_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_5_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_5_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_5_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x594)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_4_$1,Status Register 37"
bitfld.long 0x00 31. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_4_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_4_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_4_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_4_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_4_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_4_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_4_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_4_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_4_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_4_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_4_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_4_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_4_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_4_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_4_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_4_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_4_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_4_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_4_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_4_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_4_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_4_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_4_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_4_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_4_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_4_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_4_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_4_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_4_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_4_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_4_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_4_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x574)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_3_$1,Status Register 29"
bitfld.long 0x00 31. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_3_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_3_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_3_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_3_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_3_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_3_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_3_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_3_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_3_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_3_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_3_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_3_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_3_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_3_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_3_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_3_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_3_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_3_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_3_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_3_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_3_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_3_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_3_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_3_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_3_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_3_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_3_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_3_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_3_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x554)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_2_$1,Status Register 21"
bitfld.long 0x00 31. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_2_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_2_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_2_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_2_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_2_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_2_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_2_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_2_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_2_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_2_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_2_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_2_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_2_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_2_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_2_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_2_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_2_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_2_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_2_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_2_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_2_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_2_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_2_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_2_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_2_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_2_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_2_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_2_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_2_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_2_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_2_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_2_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x534)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_1_$1,Status Register 13"
bitfld.long 0x00 31. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_1_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_1_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_1_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_1_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_1_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_1_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_1_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_1_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_1_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_1_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_1_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_1_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_1_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_1_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_1_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_1_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_1_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_1_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_1_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_1_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_1_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_1_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_1_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_1_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_1_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_1_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_1_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_1_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_1_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_1_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_1_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_1_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x514)++0x03
line.long 0x00 "VPAC_INTD_STATUS_REG_LEVEL_VPAC_OUT_0_$1,Status Register 5"
bitfld.long 0x00 31. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_31,Status write 1 to set for level_vpac_out_0_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_30,Status write 1 to set for level_vpac_out_0_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_29,Status write 1 to set for level_vpac_out_0_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_28,Status write 1 to set for level_vpac_out_0_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_27,Status write 1 to set for level_vpac_out_0_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_26,Status write 1 to set for level_vpac_out_0_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_25,Status write 1 to set for level_vpac_out_0_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_24,Status write 1 to set for level_vpac_out_0_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_23,Status write 1 to set for level_vpac_out_0_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_22,Status write 1 to set for level_vpac_out_0_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_21,Status write 1 to set for level_vpac_out_0_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_20,Status write 1 to set for level_vpac_out_0_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_19,Status write 1 to set for level_vpac_out_0_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_18,Status write 1 to set for level_vpac_out_0_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_17,Status write 1 to set for level_vpac_out_0_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_16,Status write 1 to set for level_vpac_out_0_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_15,Status write 1 to set for level_vpac_out_0_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_14,Status write 1 to set for level_vpac_out_0_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_13,Status write 1 to set for level_vpac_out_0_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_12,Status write 1 to set for level_vpac_out_0_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_11,Status write 1 to set for level_vpac_out_0_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_10,Status write 1 to set for level_vpac_out_0_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_9,Status write 1 to set for level_vpac_out_0_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_8,Status write 1 to set for level_vpac_out_0_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_7,Status write 1 to set for level_vpac_out_0_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_6,Status write 1 to set for level_vpac_out_0_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_5,Status write 1 to set for level_vpac_out_0_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_4,Status write 1 to set for level_vpac_out_0_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_3,Status write 1 to set for level_vpac_out_0_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_2,Status write 1 to set for level_vpac_out_0_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_1,Status write 1 to set for level_vpac_out_0_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_COMPLETE_0,Status write 1 to set for level_vpac_out_0_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x274)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_5_$1,Enable Register 93"
bitfld.long 0x00 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_5_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_5_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_5_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_5_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_5_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_5_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_5_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_5_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_5_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_5_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_5_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_5_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_5_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_5_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_5_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_5_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_5_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_5_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_5_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_5_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_5_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_5_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_5_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_5_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_5_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_5_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_5_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_5_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_5_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_5_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_5_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_5_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x254)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_4_$1,Enable Register 85"
bitfld.long 0x00 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_4_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_4_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_4_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_4_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_4_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_4_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_4_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_4_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_4_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_4_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_4_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_4_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_4_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_4_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_4_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_4_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_4_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_4_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_4_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_4_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_4_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_4_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_4_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_4_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_4_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_4_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_4_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_4_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_4_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_4_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_4_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_4_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x234)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_3_$1,Enable Register 77"
bitfld.long 0x00 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_3_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_3_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_3_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_3_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_3_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_3_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_3_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_3_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_3_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_3_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_3_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_3_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_3_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_3_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_3_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_3_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_3_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_3_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_3_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_3_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_3_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_3_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_3_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_3_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_3_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_3_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_3_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_3_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_3_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x214)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_2_$1,Enable Register 69"
bitfld.long 0x00 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_2_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_2_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_2_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_2_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_2_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_2_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_2_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_2_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_2_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_2_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_2_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_2_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_2_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_2_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_2_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_2_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_2_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_2_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_2_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_2_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_2_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_2_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_2_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_2_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_2_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_2_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_2_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_2_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_2_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_2_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_2_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_2_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x1F4)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_1_$1,Enable Register 61"
bitfld.long 0x00 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_1_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_1_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_1_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_1_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_1_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_1_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_1_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_1_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_1_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_1_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_1_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_1_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_1_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_1_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_1_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_1_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_1_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_1_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_1_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_1_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_1_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_1_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_1_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_1_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_1_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_1_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_1_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_1_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_1_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_1_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_1_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_1_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x1D4)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_PULSE_VPAC_OUT_0_$1,Enable Register 53"
bitfld.long 0x00 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_31,Enable Set for pulse_vpac_out_0_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_30,Enable Set for pulse_vpac_out_0_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_29,Enable Set for pulse_vpac_out_0_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_28,Enable Set for pulse_vpac_out_0_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_27,Enable Set for pulse_vpac_out_0_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_26,Enable Set for pulse_vpac_out_0_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_25,Enable Set for pulse_vpac_out_0_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_24,Enable Set for pulse_vpac_out_0_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_23,Enable Set for pulse_vpac_out_0_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_22,Enable Set for pulse_vpac_out_0_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_21,Enable Set for pulse_vpac_out_0_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_20,Enable Set for pulse_vpac_out_0_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_19,Enable Set for pulse_vpac_out_0_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_18,Enable Set for pulse_vpac_out_0_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_17,Enable Set for pulse_vpac_out_0_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_16,Enable Set for pulse_vpac_out_0_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_15,Enable Set for pulse_vpac_out_0_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_14,Enable Set for pulse_vpac_out_0_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_13,Enable Set for pulse_vpac_out_0_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_12,Enable Set for pulse_vpac_out_0_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_11,Enable Set for pulse_vpac_out_0_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_10,Enable Set for pulse_vpac_out_0_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_9,Enable Set for pulse_vpac_out_0_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_8,Enable Set for pulse_vpac_out_0_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_7,Enable Set for pulse_vpac_out_0_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_6,Enable Set for pulse_vpac_out_0_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_5,Enable Set for pulse_vpac_out_0_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_4,Enable Set for pulse_vpac_out_0_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_3,Enable Set for pulse_vpac_out_0_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_2,Enable Set for pulse_vpac_out_0_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_1,Enable Set for pulse_vpac_out_0_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_COMPLETE_0,Enable Set for pulse_vpac_out_0_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x1B4)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_5_$1,Enable Register 45"
bitfld.long 0x00 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_5_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_5_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_5_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_5_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_5_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_5_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_5_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_5_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_5_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_5_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_5_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_5_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_5_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_5_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_5_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_5_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_5_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_5_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_5_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_5_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_5_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_5_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_5_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_5_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_5_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_5_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_5_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_5_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_5_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_5_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_5_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_5_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x194)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_4_$1,Enable Register 37"
bitfld.long 0x00 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_4_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_4_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_4_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_4_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_4_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_4_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_4_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_4_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_4_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_4_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_4_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_4_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_4_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_4_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_4_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_4_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_4_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_4_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_4_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_4_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_4_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_4_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_4_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_4_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_4_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_4_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_4_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_4_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_4_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_4_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_4_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_4_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x174)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_3_$1,Enable Register 29"
bitfld.long 0x00 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_3_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_3_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_3_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_3_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_3_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_3_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_3_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_3_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_3_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_3_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_3_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_3_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_3_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_3_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_3_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_3_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_3_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_3_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_3_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_3_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_3_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_3_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_3_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_3_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_3_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_3_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_3_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_3_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_3_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_3_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_3_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_3_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x154)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_2_$1,Enable Register 21"
bitfld.long 0x00 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_2_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_2_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_2_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_2_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_2_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_2_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_2_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_2_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_2_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_2_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_2_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_2_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_2_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_2_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_2_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_2_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_2_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_2_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_2_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_2_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_2_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_2_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_2_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_2_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_2_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_2_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_2_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_2_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_2_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_2_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_2_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_2_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x134)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_1_$1,Enable Register 13"
bitfld.long 0x00 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_1_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_1_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_1_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_1_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_1_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_1_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_1_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_1_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_1_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_1_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_1_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_1_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_1_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_1_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_1_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_1_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_1_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_1_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_1_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_1_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_1_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_1_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_1_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_1_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_1_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_1_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_1_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_1_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_1_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_1_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_1_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_1_en_utc1_complete_0" "0,1"
repeat.end
repeat 2. (list 5. 6. )(list 0x00 0x04 )
group.long ($2+0x114)++0x03
line.long 0x00 "VPAC_INTD_ENABLE_REG_LEVEL_VPAC_OUT_0_$1,Enable Register 5"
bitfld.long 0x00 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_31,Enable Set for level_vpac_out_0_en_utc1_complete_31" "0,1"
bitfld.long 0x00 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_30,Enable Set for level_vpac_out_0_en_utc1_complete_30" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_29,Enable Set for level_vpac_out_0_en_utc1_complete_29" "0,1"
bitfld.long 0x00 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_28,Enable Set for level_vpac_out_0_en_utc1_complete_28" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_27,Enable Set for level_vpac_out_0_en_utc1_complete_27" "0,1"
bitfld.long 0x00 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_26,Enable Set for level_vpac_out_0_en_utc1_complete_26" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_25,Enable Set for level_vpac_out_0_en_utc1_complete_25" "0,1"
bitfld.long 0x00 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_24,Enable Set for level_vpac_out_0_en_utc1_complete_24" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_23,Enable Set for level_vpac_out_0_en_utc1_complete_23" "0,1"
bitfld.long 0x00 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_22,Enable Set for level_vpac_out_0_en_utc1_complete_22" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_21,Enable Set for level_vpac_out_0_en_utc1_complete_21" "0,1"
bitfld.long 0x00 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_20,Enable Set for level_vpac_out_0_en_utc1_complete_20" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_19,Enable Set for level_vpac_out_0_en_utc1_complete_19" "0,1"
bitfld.long 0x00 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_18,Enable Set for level_vpac_out_0_en_utc1_complete_18" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_17,Enable Set for level_vpac_out_0_en_utc1_complete_17" "0,1"
bitfld.long 0x00 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_16,Enable Set for level_vpac_out_0_en_utc1_complete_16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_15,Enable Set for level_vpac_out_0_en_utc1_complete_15" "0,1"
bitfld.long 0x00 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_14,Enable Set for level_vpac_out_0_en_utc1_complete_14" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_13,Enable Set for level_vpac_out_0_en_utc1_complete_13" "0,1"
bitfld.long 0x00 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_12,Enable Set for level_vpac_out_0_en_utc1_complete_12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_11,Enable Set for level_vpac_out_0_en_utc1_complete_11" "0,1"
bitfld.long 0x00 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_10,Enable Set for level_vpac_out_0_en_utc1_complete_10" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_9,Enable Set for level_vpac_out_0_en_utc1_complete_9" "0,1"
bitfld.long 0x00 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_8,Enable Set for level_vpac_out_0_en_utc1_complete_8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_7,Enable Set for level_vpac_out_0_en_utc1_complete_7" "0,1"
bitfld.long 0x00 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_6,Enable Set for level_vpac_out_0_en_utc1_complete_6" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_5,Enable Set for level_vpac_out_0_en_utc1_complete_5" "0,1"
bitfld.long 0x00 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_4,Enable Set for level_vpac_out_0_en_utc1_complete_4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_3,Enable Set for level_vpac_out_0_en_utc1_complete_3" "0,1"
bitfld.long 0x00 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_2,Enable Set for level_vpac_out_0_en_utc1_complete_2" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_1,Enable Set for level_vpac_out_0_en_utc1_complete_1" "0,1"
bitfld.long 0x00 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_COMPLETE_0,Enable Set for level_vpac_out_0_en_utc1_complete_0" "0,1"
repeat.end
tree.end
tree.end
tree "VPAC_CTSET"
tree "VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG"
base ad:0xF002000
rgroup.long 0x00++0x03
line.long 0x00 "VPAC_CTSET_CTSETID,CTSET identification register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,The value 10b designates this as Processor Business Unit IP" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Function : Indicates a Debug IP (0x2nn) and 0x80 is the identifier for CT-SET"
bitfld.long 0x00 11.--15. "RTL_VERSION,This field changes on bug fix and resets to '0' when either Minor Revision or Major Revision field changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x0F
line.long 0x00 "VPAC_CTSET_CTSETSYSCFG,CTSET system configuration register"
bitfld.long 0x00 2.--3. "IDLEMODE,Sets the Idle Mode for CTSET (" "0,1,2,3"
bitfld.long 0x00 0. "SOFTRESET,This will reset entire CTSET except the registers and the CFG interface" "0,1"
line.long 0x04 "VPAC_CTSET_SETSTR,CTSET status register"
bitfld.long 0x04 8. "HWFIFOEMPTY,System Event Trace FIFO status 1 is empty 0 means captured data not yet exported" "0,1"
bitfld.long 0x04 0. "RESETDONE,Reset status 0 means reset ongoing 1 indicates completed" "0,1"
line.long 0x08 "VPAC_CTSET_DBGTIMELOW,The 32 low order bits of the debug time value supplied on the time input interface"
line.long 0x0C "VPAC_CTSET_DBGTIMEHI,The 32 high order bits of the debug time value supplied on the time input interface"
group.long 0x24++0x07
line.long 0x00 "VPAC_CTSET_CTSETCFG,The 32 low order bits of the debug time value supplied on the time input interface The 32 high order bits of the debug time value supplied on the time input interface"
bitfld.long 0x00 28.--31. "CLAIM,Claim control and status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "SYSEVENTCAPTEN,When 1 the System event capture is enabled" "0,1"
bitfld.long 0x00 4. "EVENTLEVEL,0 enables low level event detection 1 enables high level event detection" "0,1"
bitfld.long 0x00 3. "MSGMODE,Message generated based on event detection 0 is sampling window 1 is event detection" "0,1"
bitfld.long 0x00 2. "STOPCAPT,Stop capturing system events from external trigger detection" "0,1"
bitfld.long 0x00 1. "STARTCAPT,Start capturing system events from external trigger detection" "0,1"
line.long 0x04 "VPAC_CTSET_SETSPLREG,System Event Sampling Window register"
hexmask.long.byte 0x04 0.--7. 1. "WINDOWSIZE,System events sampling window size expressed as CTSET cycles"
group.long 0x30++0x23
line.long 0x00 "VPAC_CTSET_SETEVTENBL1,System event detection enable register 1"
bitfld.long 0x00 31. "EVENT32DETEN,Event(32) Detection Enable" "0,1"
bitfld.long 0x00 30. "EVENT31DETEN,Event(31) Detection Enable" "0,1"
bitfld.long 0x00 29. "EVENT30DETEN,Event(30) Detection Enable" "0,1"
bitfld.long 0x00 28. "EVENT29DETEN,Event(29) Detection Enable" "0,1"
bitfld.long 0x00 27. "EVENT28DETEN,Event(28) Detection Enable" "0,1"
bitfld.long 0x00 26. "EVENT27DETEN,Event(27) Detection Enable" "0,1"
newline
bitfld.long 0x00 25. "EVENT26DETEN,Event(26) Detection Enable" "0,1"
bitfld.long 0x00 24. "EVENT25DETEN,Event(25) Detection Enable" "0,1"
bitfld.long 0x00 23. "EVENT24DETEN,Event(24) Detection Enable" "0,1"
bitfld.long 0x00 22. "EVENT23DETEN,Event(23) Detection Enable" "0,1"
bitfld.long 0x00 21. "EVENT22DETEN,Event(22) Detection Enable" "0,1"
bitfld.long 0x00 20. "EVENT21DETEN,Event(21) Detection Enable" "0,1"
newline
bitfld.long 0x00 19. "EVENT20DETEN,Event(20) Detection Enable" "0,1"
bitfld.long 0x00 18. "EVENT19DETEN,Event(19) Detection Enable" "0,1"
bitfld.long 0x00 17. "EVENT18DETEN,Event(18) Detection Enable" "0,1"
bitfld.long 0x00 16. "EVENT17DETEN,Event(17) Detection Enable" "0,1"
bitfld.long 0x00 15. "EVENT16DETEN,Event(16) Detection Enable" "0,1"
bitfld.long 0x00 14. "EVENT15DETEN,Event(15) Detection Enable" "0,1"
newline
bitfld.long 0x00 13. "EVENT14DETEN,Event(14) Detection Enable" "0,1"
bitfld.long 0x00 12. "EVENT13DETEN,Event(13) Detection Enable" "0,1"
bitfld.long 0x00 11. "EVENT12DETEN,Event(12) Detection Enable" "0,1"
bitfld.long 0x00 10. "EVENT11DETEN,Event(11) Detection Enable" "0,1"
bitfld.long 0x00 9. "EVENT10DETEN,Event(10) Detection Enable" "0,1"
bitfld.long 0x00 8. "EVENT9DETEN,Event(9) Detection Enable" "0,1"
newline
bitfld.long 0x00 7. "EVENT8DETEN,Event(8) Detection Enable" "0,1"
bitfld.long 0x00 6. "EVENT7DETEN,Event(7) Detection Enable" "0,1"
bitfld.long 0x00 5. "EVENT6DETEN,Event(6) Detection Enable" "0,1"
bitfld.long 0x00 4. "EVENT5DETEN,Event(5) Detection Enable" "0,1"
bitfld.long 0x00 3. "EVENT4DETEN,Event(4) Detection Enable" "0,1"
bitfld.long 0x00 2. "EVENT3DETEN,Event(3) Detection Enable" "0,1"
newline
bitfld.long 0x00 1. "EVENT2DETEN,Event(2) Detection Enable" "0,1"
bitfld.long 0x00 0. "EVENT1DETEN,Event(1) Detection Enable" "0,1"
line.long 0x04 "VPAC_CTSET_SETEVTENBL2,System event detection enable register 2 (if number of events > 32)"
bitfld.long 0x04 31. "EVENT64DETEN,Event(64) Detection Enable" "0,1"
bitfld.long 0x04 30. "EVENT63DETEN,Event(63) Detection Enable" "0,1"
bitfld.long 0x04 29. "EVENT62DETEN,Event(62) Detection Enable" "0,1"
bitfld.long 0x04 28. "EVENT61DETEN,Event(61) Detection Enable" "0,1"
bitfld.long 0x04 27. "EVENT60DETEN,Event(60) Detection Enable" "0,1"
bitfld.long 0x04 26. "EVENT59DETEN,Event(59) Detection Enable" "0,1"
newline
bitfld.long 0x04 25. "EVENT58DETEN,Event(58) Detection Enable" "0,1"
bitfld.long 0x04 24. "EVENT57DETEN,Event(57) Detection Enable" "0,1"
bitfld.long 0x04 23. "EVENT56DETEN,Event(56) Detection Enable" "0,1"
bitfld.long 0x04 22. "EVENT55DETEN,Event(55) Detection Enable" "0,1"
bitfld.long 0x04 21. "EVENT54DETEN,Event(54) Detection Enable" "0,1"
bitfld.long 0x04 20. "EVENT53DETEN,Event(53) Detection Enable" "0,1"
newline
bitfld.long 0x04 19. "EVENT52DETEN,Event(52) Detection Enable" "0,1"
bitfld.long 0x04 18. "EVENT51DETEN,Event(51) Detection Enable" "0,1"
bitfld.long 0x04 17. "EVENT50DETEN,Event(50) Detection Enable" "0,1"
bitfld.long 0x04 16. "EVENT49DETEN,Event(49) Detection Enable" "0,1"
bitfld.long 0x04 15. "EVENT48DETEN,Event(48) Detection Enable" "0,1"
bitfld.long 0x04 14. "EVENT47DETEN,Event(47) Detection Enable" "0,1"
newline
bitfld.long 0x04 13. "EVENT46DETEN,Event(46) Detection Enable" "0,1"
bitfld.long 0x04 12. "EVENT45DETEN,Event(45) Detection Enable" "0,1"
bitfld.long 0x04 11. "EVENT44DETEN,Event(44) Detection Enable" "0,1"
bitfld.long 0x04 10. "EVENT43DETEN,Event(43) Detection Enable" "0,1"
bitfld.long 0x04 9. "EVENT42DETEN,Event(42) Detection Enable" "0,1"
bitfld.long 0x04 8. "EVENT41DETEN,Event(41) Detection Enable" "0,1"
newline
bitfld.long 0x04 7. "EVENT40DETEN,Event(40) Detection Enable" "0,1"
bitfld.long 0x04 6. "EVENT39DETEN,Event(39) Detection Enable" "0,1"
bitfld.long 0x04 5. "EVENT38DETEN,Event(38) Detection Enable" "0,1"
bitfld.long 0x04 4. "EVENT37DETEN,Event(37) Detection Enable" "0,1"
bitfld.long 0x04 3. "EVENT36DETEN,Event(36) Detection Enable" "0,1"
bitfld.long 0x04 2. "EVENT35DETEN,Event(35) Detection Enable" "0,1"
newline
bitfld.long 0x04 1. "EVENT34DETEN,Event(34) Detection Enable" "0,1"
bitfld.long 0x04 0. "EVENT33DETEN,Event(33) Detection Enable" "0,1"
line.long 0x08 "VPAC_CTSET_SETEVTENBL3,System event detection enable register 3 (if number of events > 64)"
bitfld.long 0x08 31. "EVENT96DETEN,Event(96) Detection Enable" "0,1"
bitfld.long 0x08 30. "EVENT95DETEN,Event(95) Detection Enable" "0,1"
bitfld.long 0x08 29. "EVENT94DETEN,Event(94) Detection Enable" "0,1"
bitfld.long 0x08 28. "EVENT93DETEN,Event(93) Detection Enable" "0,1"
bitfld.long 0x08 27. "EVENT92DETEN,Event(92) Detection Enable" "0,1"
bitfld.long 0x08 26. "EVENT91DETEN,Event(91) Detection Enable" "0,1"
newline
bitfld.long 0x08 25. "EVENT90DETEN,Event(90) Detection Enable" "0,1"
bitfld.long 0x08 24. "EVENT89DETEN,Event(89) Detection Enable" "0,1"
bitfld.long 0x08 23. "EVENT88DETEN,Event(88) Detection Enable" "0,1"
bitfld.long 0x08 22. "EVENT87DETEN,Event(87) Detection Enable" "0,1"
bitfld.long 0x08 21. "EVENT86DETEN,Event(86) Detection Enable" "0,1"
bitfld.long 0x08 20. "EVENT85DETEN,Event(85) Detection Enable" "0,1"
newline
bitfld.long 0x08 19. "EVENT84DETEN,Event(84) Detection Enable" "0,1"
bitfld.long 0x08 18. "EVENT83DETEN,Event(83) Detection Enable" "0,1"
bitfld.long 0x08 17. "EVENT82DETEN,Event(82) Detection Enable" "0,1"
bitfld.long 0x08 16. "EVENT81DETEN,Event(81) Detection Enable" "0,1"
bitfld.long 0x08 15. "EVENT80DETEN,Event(80) Detection Enable" "0,1"
bitfld.long 0x08 14. "EVENT79DETEN,Event(79) Detection Enable" "0,1"
newline
bitfld.long 0x08 13. "EVENT78DETEN,Event(78) Detection Enable" "0,1"
bitfld.long 0x08 12. "EVENT77DETEN,Event(77) Detection Enable" "0,1"
bitfld.long 0x08 11. "EVENT76DETEN,Event(76) Detection Enable" "0,1"
bitfld.long 0x08 10. "EVENT75DETEN,Event(75) Detection Enable" "0,1"
bitfld.long 0x08 9. "EVENT74DETEN,Event(74) Detection Enable" "0,1"
bitfld.long 0x08 8. "EVENT73DETEN,Event(73) Detection Enable" "0,1"
newline
bitfld.long 0x08 7. "EVENT72DETEN,Event(72) Detection Enable" "0,1"
bitfld.long 0x08 6. "EVENT71DETEN,Event(71) Detection Enable" "0,1"
bitfld.long 0x08 5. "EVENT70DETEN,Event(70) Detection Enable" "0,1"
bitfld.long 0x08 4. "EVENT69DETEN,Event(69) Detection Enable" "0,1"
bitfld.long 0x08 3. "EVENT68DETEN,Event(68) Detection Enable" "0,1"
bitfld.long 0x08 2. "EVENT67DETEN,Event(67) Detection Enable" "0,1"
newline
bitfld.long 0x08 1. "EVENT66DETEN,Event(66) Detection Enable" "0,1"
bitfld.long 0x08 0. "EVENT65DETEN,Event(65) Detection Enable" "0,1"
line.long 0x0C "VPAC_CTSET_SETEVTENBL4,System event detection enable register 4 (if number of events > 96)"
bitfld.long 0x0C 31. "EVENT128DETEN,Event(128) Detection Enable" "0,1"
bitfld.long 0x0C 30. "EVENT127DETEN,Event(127) Detection Enable" "0,1"
bitfld.long 0x0C 29. "EVENT126DETEN,Event(126) Detection Enable" "0,1"
bitfld.long 0x0C 28. "EVENT125DETEN,Event(125) Detection Enable" "0,1"
bitfld.long 0x0C 27. "EVENT124DETEN,Event(124) Detection Enable" "0,1"
bitfld.long 0x0C 26. "EVENT123DETEN,Event(123) Detection Enable" "0,1"
newline
bitfld.long 0x0C 25. "EVENT122DETEN,Event(122) Detection Enable" "0,1"
bitfld.long 0x0C 24. "EVENT121DETEN,Event(121) Detection Enable" "0,1"
bitfld.long 0x0C 23. "EVENT120DETEN,Event(120) Detection Enable" "0,1"
bitfld.long 0x0C 22. "EVENT119DETEN,Event(119) Detection Enable" "0,1"
bitfld.long 0x0C 21. "EVENT118DETEN,Event(118) Detection Enable" "0,1"
bitfld.long 0x0C 20. "EVENT117DETEN,Event(117) Detection Enable" "0,1"
newline
bitfld.long 0x0C 19. "EVENT116DETEN,Event(116) Detection Enable" "0,1"
bitfld.long 0x0C 18. "EVENT115DETEN,Event(115) Detection Enable" "0,1"
bitfld.long 0x0C 17. "EVENT114DETEN,Event(114) Detection Enable" "0,1"
bitfld.long 0x0C 16. "EVENT113DETEN,Event(113) Detection Enable" "0,1"
bitfld.long 0x0C 15. "EVENT112DETEN,Event(112) Detection Enable" "0,1"
bitfld.long 0x0C 14. "EVENT111DETEN,Event(111) Detection Enable" "0,1"
newline
bitfld.long 0x0C 13. "EVENT110DETEN,Event(110) Detection Enable" "0,1"
bitfld.long 0x0C 12. "EVENT109DETEN,Event(109) Detection Enable" "0,1"
bitfld.long 0x0C 11. "EVENT108DETEN,Event(108) Detection Enable" "0,1"
bitfld.long 0x0C 10. "EVENT107DETEN,Event(107) Detection Enable" "0,1"
bitfld.long 0x0C 9. "EVENT106DETEN,Event(106) Detection Enable" "0,1"
bitfld.long 0x0C 8. "EVENT105DETEN,Event(105) Detection Enable" "0,1"
newline
bitfld.long 0x0C 7. "EVENT104DETEN,Event(104) Detection Enable" "0,1"
bitfld.long 0x0C 6. "EVENT103DETEN,Event(103) Detection Enable" "0,1"
bitfld.long 0x0C 5. "EVENT102DETEN,Event(102) Detection Enable" "0,1"
bitfld.long 0x0C 4. "EVENT101DETEN,Event(101) Detection Enable" "0,1"
bitfld.long 0x0C 3. "EVENT100DETEN,Event(100) Detection Enable" "0,1"
bitfld.long 0x0C 2. "EVENT99DETEN,Event(99) Detection Enable" "0,1"
newline
bitfld.long 0x0C 1. "EVENT98DETEN,Event(98) Detection Enable" "0,1"
bitfld.long 0x0C 0. "EVENT97DETEN,Event(97) Detection Enable" "0,1"
line.long 0x10 "VPAC_CTSET_SETEVTENBL5,System event detection enable register 5 (if number of events > 128)"
bitfld.long 0x10 31. "EVENT160DETEN,Event(160) Detection Enable" "0,1"
bitfld.long 0x10 30. "EVENT159DETEN,Event(159) Detection Enable" "0,1"
bitfld.long 0x10 29. "EVENT158DETEN,Event(158) Detection Enable" "0,1"
bitfld.long 0x10 28. "EVENT157DETEN,Event(157) Detection Enable" "0,1"
bitfld.long 0x10 27. "EVENT156DETEN,Event(156) Detection Enable" "0,1"
bitfld.long 0x10 26. "EVENT155DETEN,Event(155) Detection Enable" "0,1"
newline
bitfld.long 0x10 25. "EVENT154DETEN,Event(154) Detection Enable" "0,1"
bitfld.long 0x10 24. "EVENT153DETEN,Event(153) Detection Enable" "0,1"
bitfld.long 0x10 23. "EVENT152DETEN,Event(152) Detection Enable" "0,1"
bitfld.long 0x10 22. "EVENT151DETEN,Event(151) Detection Enable" "0,1"
bitfld.long 0x10 21. "EVENT150DETEN,Event(150) Detection Enable" "0,1"
bitfld.long 0x10 20. "EVENT149DETEN,Event(149) Detection Enable" "0,1"
newline
bitfld.long 0x10 19. "EVENT148DETEN,Event(148) Detection Enable" "0,1"
bitfld.long 0x10 18. "EVENT147DETEN,Event(147) Detection Enable" "0,1"
bitfld.long 0x10 17. "EVENT1468DETEN,Event(146) Detection Enable" "0,1"
bitfld.long 0x10 16. "EVENT145DETEN,Event(145) Detection Enable" "0,1"
bitfld.long 0x10 15. "EVENT144DETEN,Event(144) Detection Enable" "0,1"
bitfld.long 0x10 14. "EVENT143DETEN,Event(143) Detection Enable" "0,1"
newline
bitfld.long 0x10 13. "EVENT142DETEN,Event(142) Detection Enable" "0,1"
bitfld.long 0x10 12. "EVENT141DETEN,Event(141) Detection Enable" "0,1"
bitfld.long 0x10 11. "EVENT140DETEN,Event(140) Detection Enable" "0,1"
bitfld.long 0x10 10. "EVENT139DETEN,Event(139) Detection Enable" "0,1"
bitfld.long 0x10 9. "EVENT138DETEN,Event(138) Detection Enable" "0,1"
bitfld.long 0x10 8. "EVENT137DETEN,Event(137) Detection Enable" "0,1"
newline
bitfld.long 0x10 7. "EVENT136DETEN,Event(136) Detection Enable" "0,1"
bitfld.long 0x10 6. "EVENT135DETEN,Event(135) Detection Enable" "0,1"
bitfld.long 0x10 5. "EVENT134DETEN,Event(134) Detection Enable" "0,1"
bitfld.long 0x10 4. "EVENT133DETEN,Event(133) Detection Enable" "0,1"
bitfld.long 0x10 3. "EVENT132DETEN,Event(132) Detection Enable" "0,1"
bitfld.long 0x10 2. "EVENT131DETEN,Event(131) Detection Enable" "0,1"
newline
bitfld.long 0x10 1. "EVENT130DETEN,Event(130) Detection Enable" "0,1"
bitfld.long 0x10 0. "EVENT129DETEN,Event(129) Detection Enable" "0,1"
line.long 0x14 "VPAC_CTSET_SETEVTENBL6,System event detection enable register 6 (if number of events > 160)"
bitfld.long 0x14 31. "EVENT192DETEN,Event(192) Detection Enable" "0,1"
bitfld.long 0x14 30. "EVENT191DETEN,Event(191) Detection Enable" "0,1"
bitfld.long 0x14 29. "EVENT190DETEN,Event(190) Detection Enable" "0,1"
bitfld.long 0x14 28. "EVENT189DETEN,Event(189) Detection Enable" "0,1"
bitfld.long 0x14 27. "EVENT188DETEN,Event(188) Detection Enable" "0,1"
bitfld.long 0x14 26. "EVENT187DETEN,Event(187) Detection Enable" "0,1"
newline
bitfld.long 0x14 25. "EVENT186DETEN,Event(186) Detection Enable" "0,1"
bitfld.long 0x14 24. "EVENT185DETEN,Event(185) Detection Enable" "0,1"
bitfld.long 0x14 23. "EVENT184DETEN,Event(184) Detection Enable" "0,1"
bitfld.long 0x14 22. "EVENT183DETEN,Event(183) Detection Enable" "0,1"
bitfld.long 0x14 21. "EVENT182DETEN,Event(182) Detection Enable" "0,1"
bitfld.long 0x14 20. "EVENT181DETEN,Event(181) Detection Enable" "0,1"
newline
bitfld.long 0x14 19. "EVENT180DETEN,Event(180) Detection Enable" "0,1"
bitfld.long 0x14 18. "EVENT179DETEN,Event(179) Detection Enable" "0,1"
bitfld.long 0x14 17. "EVENT178DETEN,Event(178) Detection Enable" "0,1"
bitfld.long 0x14 16. "EVENT177DETEN,Event(177) Detection Enable" "0,1"
bitfld.long 0x14 15. "EVENT176DETEN,Event(176) Detection Enable" "0,1"
bitfld.long 0x14 14. "EVENT175DETEN,Event(175) Detection Enable" "0,1"
newline
bitfld.long 0x14 13. "EVENT174DETEN,Event(174) Detection Enable" "0,1"
bitfld.long 0x14 12. "EVENT173DETEN,Event(173) Detection Enable" "0,1"
bitfld.long 0x14 11. "EVENT172DETEN,Event(172) Detection Enable" "0,1"
bitfld.long 0x14 10. "EVENT171DETEN,Event(171) Detection Enable" "0,1"
bitfld.long 0x14 9. "EVENT170DETEN,Event(170) Detection Enable" "0,1"
bitfld.long 0x14 8. "EVENT169DETEN,Event(169) Detection Enable" "0,1"
newline
bitfld.long 0x14 7. "EVENT168DETEN,Event(168) Detection Enable" "0,1"
bitfld.long 0x14 6. "EVENT167DETEN,Event(167) Detection Enable" "0,1"
bitfld.long 0x14 5. "EVENT166DETEN,Event(166) Detection Enable" "0,1"
bitfld.long 0x14 4. "EVENT165DETEN,Event(165) Detection Enable" "0,1"
bitfld.long 0x14 3. "EVENT164DETEN,Event(164) Detection Enable" "0,1"
bitfld.long 0x14 2. "EVENT163DETEN,Event(163) Detection Enable" "0,1"
newline
bitfld.long 0x14 1. "EVENT162DETEN,Event(162) Detection Enable" "0,1"
bitfld.long 0x14 0. "EVENT161DETEN,Event(161) Detection Enable" "0,1"
line.long 0x18 "VPAC_CTSET_SETEVTENBL7,System event detection enable register 7 (if number of events > 192)"
bitfld.long 0x18 31. "EVENT224DETEN,Event(224) Detection Enable" "0,1"
bitfld.long 0x18 30. "EVENT223DETEN,Event(223) Detection Enable" "0,1"
bitfld.long 0x18 29. "EVENT222DETEN,Event(222) Detection Enable" "0,1"
bitfld.long 0x18 28. "EVENT221DETEN,Event(221) Detection Enable" "0,1"
bitfld.long 0x18 27. "EVENT220DETEN,Event(220) Detection Enable" "0,1"
bitfld.long 0x18 26. "EVENT219DETEN,Event(219) Detection Enable" "0,1"
newline
bitfld.long 0x18 25. "EVENT218DETEN,Event(218) Detection Enable" "0,1"
bitfld.long 0x18 24. "EVENT217DETEN,Event(217) Detection Enable" "0,1"
bitfld.long 0x18 23. "EVENT216DETEN,Event(216) Detection Enable" "0,1"
bitfld.long 0x18 22. "EVENT215DETEN,Event(215) Detection Enable" "0,1"
bitfld.long 0x18 21. "EVENT214DETEN,Event(214) Detection Enable" "0,1"
bitfld.long 0x18 20. "EVENT213DETEN,Event(213) Detection Enable" "0,1"
newline
bitfld.long 0x18 19. "EVENT212DETEN,Event(212) Detection Enable" "0,1"
bitfld.long 0x18 18. "EVENT211DETEN,Event(211) Detection Enable" "0,1"
bitfld.long 0x18 17. "EVENT210DETEN,Event(210) Detection Enable" "0,1"
bitfld.long 0x18 16. "EVENT209DETEN,Event(209) Detection Enable" "0,1"
bitfld.long 0x18 15. "EVENT208DETEN,Event(208) Detection Enable" "0,1"
bitfld.long 0x18 14. "EVENT207DETEN,Event(207) Detection Enable" "0,1"
newline
bitfld.long 0x18 13. "EVENT206DETEN,Event(206) Detection Enable" "0,1"
bitfld.long 0x18 12. "EVENT205DETEN,Event(205) Detection Enable" "0,1"
bitfld.long 0x18 11. "EVENT204DETEN,Event(204) Detection Enable" "0,1"
bitfld.long 0x18 10. "EVENT203DETEN,Event(203) Detection Enable" "0,1"
bitfld.long 0x18 9. "EVENT202DETEN,Event(202) Detection Enable" "0,1"
bitfld.long 0x18 8. "EVENT201DETEN,Event(201) Detection Enable" "0,1"
newline
bitfld.long 0x18 7. "EVENT200DETEN,Event(200) Detection Enable" "0,1"
bitfld.long 0x18 6. "EVENT199DETEN,Event(199) Detection Enable" "0,1"
bitfld.long 0x18 5. "EVENT198DETEN,Event(198) Detection Enable" "0,1"
bitfld.long 0x18 4. "EVENT197DETEN,Event(197) Detection Enable" "0,1"
bitfld.long 0x18 3. "EVENT196DETEN,Event(196) Detection Enable" "0,1"
bitfld.long 0x18 2. "EVENT195DETEN,Event(195) Detection Enable" "0,1"
newline
bitfld.long 0x18 1. "EVENT194DETEN,Event(194) Detection Enable" "0,1"
bitfld.long 0x18 0. "EVENT193DETEN,Event(193) Detection Enable" "0,1"
line.long 0x1C "VPAC_CTSET_SETEVTENBL8,System event detection enable register 8 (if number of events > 224)"
bitfld.long 0x1C 31. "EVENT256DETEN,Event(256) Detection Enable" "0,1"
bitfld.long 0x1C 30. "EVENT255DETEN,Event(255) Detection Enable" "0,1"
bitfld.long 0x1C 29. "EVENT254DETEN,Event(254) Detection Enable" "0,1"
bitfld.long 0x1C 28. "EVENT253DETEN,Event(253) Detection Enable" "0,1"
bitfld.long 0x1C 27. "EVENT252DETEN,Event(252) Detection Enable" "0,1"
bitfld.long 0x1C 26. "EVENT251DETEN,Event(251) Detection Enable" "0,1"
newline
bitfld.long 0x1C 25. "EVENT250DETEN,Event(250) Detection Enable" "0,1"
bitfld.long 0x1C 24. "EVENT249DETEN,Event(249) Detection Enable" "0,1"
bitfld.long 0x1C 23. "EVENT248DETEN,Event(248) Detection Enable" "0,1"
bitfld.long 0x1C 22. "EVENT247DETEN,Event(247) Detection Enable" "0,1"
bitfld.long 0x1C 21. "EVENT246DETEN,Event(246) Detection Enable" "0,1"
bitfld.long 0x1C 20. "EVENT245DETEN,Event(245) Detection Enable" "0,1"
newline
bitfld.long 0x1C 19. "EVENT244DETEN,Event(244) Detection Enable" "0,1"
bitfld.long 0x1C 18. "EVENT243DETEN,Event(243) Detection Enable" "0,1"
bitfld.long 0x1C 17. "EVENT242DETEN,Event(242) Detection Enable" "0,1"
bitfld.long 0x1C 16. "EVENT241DETEN,Event(241) Detection Enable" "0,1"
bitfld.long 0x1C 15. "EVENT240DETEN,Event(240) Detection Enable" "0,1"
bitfld.long 0x1C 14. "EVENT239DETEN,Event(239) Detection Enable" "0,1"
newline
bitfld.long 0x1C 13. "EVENT238DETEN,Event(238) Detection Enable" "0,1"
bitfld.long 0x1C 12. "EVENT237DETEN,Event(237) Detection Enable" "0,1"
bitfld.long 0x1C 11. "EVENT236DETEN,Event(236) Detection Enable" "0,1"
bitfld.long 0x1C 10. "EVENT235DETEN,Event(235) Detection Enable" "0,1"
bitfld.long 0x1C 9. "EVENT234DETEN,Event(234) Detection Enable" "0,1"
bitfld.long 0x1C 8. "EVENT233DETEN,Event(233) Detection Enable" "0,1"
newline
bitfld.long 0x1C 7. "EVENT232DETEN,Event(232) Detection Enable" "0,1"
bitfld.long 0x1C 6. "EVENT231DETEN,Event(231) Detection Enable" "0,1"
bitfld.long 0x1C 5. "EVENT230DETEN,Event(230) Detection Enable" "0,1"
bitfld.long 0x1C 4. "EVENT229DETEN,Event(229) Detection Enable" "0,1"
bitfld.long 0x1C 3. "EVENT228DETEN,Event(228) Detection Enable" "0,1"
bitfld.long 0x1C 2. "EVENT227DETEN,Event(227) Detection Enable" "0,1"
newline
bitfld.long 0x1C 1. "EVENT226DETEN,Event(226) Detection Enable" "0,1"
bitfld.long 0x1C 0. "EVENT225DETEN,Event(225) Detection Enable" "0,1"
line.long 0x20 "VPAC_CTSET_SETMSTID,System Event Master ID"
hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for System Event module"
rgroup.long 0x800++0x0B
line.long 0x00 "VPAC_CTSET_CTCNTL,Counter Timer Control"
bitfld.long 0x00 26.--31. "NUMSTM,Number of counters that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals"
bitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 3.--6. "REVID,Revision ID of CTSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "NUMCOREMD,Indicated the number of mode bus interfaces 0 is 2 CPU buses 1 is 4 buses" "0,1"
line.long 0x04 "VPAC_CTSET_CTNUMDBG,Counter Timer Number Debug Event Register"
bitfld.long 0x04 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7"
line.long 0x08 "VPAC_CTSET_CTUSERACCCTL,Counter Timer User Access Control. can only be written in priviledged mode"
bitfld.long 0x08 2. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x08 1. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x08 0. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
group.long 0x820++0x13
line.long 0x00 "VPAC_CTSET_CTSTMCNTL,Counter Timer STM Control register"
rbitfld.long 0x00 6.--11. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 5. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1"
bitfld.long 0x00 4. "CCMPORT,SW control of CCM message export" "0,1"
bitfld.long 0x00 3. "CCMAVAIL,CTSET supports CCM export" "0,1"
bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1"
bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1"
newline
bitfld.long 0x00 0. "ENBL,CTSET STM global enable for counter/timer messages" "0,1"
line.long 0x04 "VPAC_CTSET_CTSTMMSTID,Counter Timer STM Master ID register"
hexmask.long.byte 0x04 0.--7. 1. "MASTID,HW Master ID for System Event module"
line.long 0x08 "VPAC_CTSET_CTSTMINTVL,Counter Timer STM Interval Register"
hexmask.long.word 0x08 0.--14. 1. "INTERVAL,Counter Timer Periodic export interval"
line.long 0x0C "VPAC_CTSET_CTSTMSEL0,Counter Timer STM Counter Select Register 0"
line.long 0x10 "VPAC_CTSET_CTSTMSEL1,Counter Timer STM Counter Select Register 1"
group.long 0x8A0++0x03
line.long 0x00 "VPAC_CTSET_CTDBGSGL0,Timer Interval Register 0"
hexmask.long.byte 0x00 0.--7. 1. "INPSEL,Counter Timer input selection"
group.long 0x9F0++0x0F
line.long 0x00 "VPAC_CTSET_CTGNBL0,Counter Timer Global Enable Register 0"
hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter"
line.long 0x04 "VPAC_CTSET_CTGNBL1,Counter Timer Global Enable Register 1"
hexmask.long.byte 0x04 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter"
line.long 0x08 "VPAC_CTSET_CTGRST0,Counter Timer Global Reset Register 0"
hexmask.long.byte 0x08 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter"
line.long 0x0C "VPAC_CTSET_CTGRST1,Counter Timer Global Reset Register 0"
hexmask.long.byte 0x0C 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter"
group.long 0xB00++0x7F
line.long 0x00 "VPAC_CTSET_CTFILT0,Counter Timer 0 Filter Register"
bitfld.long 0x00 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x00 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x00 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x00 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x00 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x00 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x00 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x00 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x04 "VPAC_CTSET_CTFILT1,Counter Timer 1 Filter Register"
bitfld.long 0x04 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x04 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x04 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x04 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x04 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x04 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x04 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x04 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x08 "VPAC_CTSET_CTFILT2,Counter Timer 2 Filter Register"
bitfld.long 0x08 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x08 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x08 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x08 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x08 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x08 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x08 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x08 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x0C "VPAC_CTSET_CTFILT3,Counter Timer 3 Filter Register"
bitfld.long 0x0C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x0C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x0C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x0C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x0C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x0C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x0C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x0C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x10 "VPAC_CTSET_CTFILT4,Counter Timer 4 Filter Register"
bitfld.long 0x10 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x10 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x10 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x10 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x10 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x10 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x10 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x10 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x14 "VPAC_CTSET_CTFILT5,Counter Timer 5 Filter Register"
bitfld.long 0x14 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x14 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x14 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x14 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x14 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x14 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x14 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x14 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x18 "VPAC_CTSET_CTFILT6,Counter Timer 6 Filter Register"
bitfld.long 0x18 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x18 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x18 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x18 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x18 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x18 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x18 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x18 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x1C "VPAC_CTSET_CTFILT7,Counter Timer 7 Filter Register"
bitfld.long 0x1C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x1C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x1C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x1C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x1C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x1C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x1C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x1C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x20 "VPAC_CTSET_CTFILT8,Counter Timer 8 Filter Register"
bitfld.long 0x20 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x20 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x20 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x20 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x20 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x20 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x20 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x20 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x24 "VPAC_CTSET_CTFILT9,Counter Timer 9 Filter Register"
bitfld.long 0x24 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x24 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x24 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x24 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x24 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x24 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x24 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x24 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x28 "VPAC_CTSET_CTFILT10,Counter Timer 10 Filter Register"
bitfld.long 0x28 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x28 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x28 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x28 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x28 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x28 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x28 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x28 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x2C "VPAC_CTSET_CTFILT11,Counter Timer 11 Filter Register"
bitfld.long 0x2C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x2C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x2C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x2C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x2C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x2C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x2C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x2C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x30 "VPAC_CTSET_CTFILT12,Counter Timer 12 Filter Register"
bitfld.long 0x30 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x30 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x30 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x30 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x30 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x30 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x30 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x30 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x34 "VPAC_CTSET_CTFILT13,Counter Timer 13 Filter Register"
bitfld.long 0x34 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x34 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x34 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x34 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x34 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x34 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x34 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x34 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x38 "VPAC_CTSET_CTFILT14,Counter Timer 14 Filter Register"
bitfld.long 0x38 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x38 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x38 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x38 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x38 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x38 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x38 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x38 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x3C "VPAC_CTSET_CTFILT15,Counter Timer 15 Filter Register"
bitfld.long 0x3C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x3C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x3C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x3C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x3C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x3C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x3C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x3C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x40 "VPAC_CTSET_CTFILT16,Counter Timer 16 Filter Register"
bitfld.long 0x40 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x40 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x40 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x40 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x40 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x40 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x40 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x40 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x44 "VPAC_CTSET_CTFILT17,Counter Timer 17 Filter Register"
bitfld.long 0x44 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x44 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x44 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x44 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x44 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x44 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x44 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x44 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x48 "VPAC_CTSET_CTFILT18,Counter Timer 18 Filter Register"
bitfld.long 0x48 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x48 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x48 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x48 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x48 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x48 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x48 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x48 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x4C "VPAC_CTSET_CTFILT19,Counter Timer 19 Filter Register"
bitfld.long 0x4C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x4C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x4C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x4C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x4C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x4C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x4C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x4C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x50 "VPAC_CTSET_CTFILT20,Counter Timer 20 Filter Register"
bitfld.long 0x50 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x50 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x50 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x50 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x50 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x50 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x50 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x50 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x54 "VPAC_CTSET_CTFILT21,Counter Timer 21 Filter Register"
bitfld.long 0x54 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x54 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x54 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x54 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x54 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x54 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x54 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x54 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x58 "VPAC_CTSET_CTFILT22,Counter Timer 22 Filter Register"
bitfld.long 0x58 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x58 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x58 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x58 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x58 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x58 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x58 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x58 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x5C "VPAC_CTSET_CTFILT23,Counter Timer 23 Filter Register"
bitfld.long 0x5C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x5C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x5C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x5C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x5C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x5C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x5C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x5C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x60 "VPAC_CTSET_CTFILT24,Counter Timer 24 Filter Register"
bitfld.long 0x60 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x60 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x60 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x60 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x60 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x60 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x60 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x60 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x64 "VPAC_CTSET_CTFILT25,Counter Timer 25 Filter Register"
bitfld.long 0x64 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x64 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x64 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x64 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x64 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x64 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x64 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x64 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x68 "VPAC_CTSET_CTFILT26,Counter Timer 26 Filter Register"
bitfld.long 0x68 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x68 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x68 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x68 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x68 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x68 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x68 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x68 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x6C "VPAC_CTSET_CTFILT27,Counter Timer 27 Filter Register"
bitfld.long 0x6C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x6C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x6C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x6C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x6C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x6C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x6C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x6C 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x70 "VPAC_CTSET_CTFILT28,Counter Timer 28 Filter Register"
bitfld.long 0x70 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x70 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x70 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x70 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x70 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x70 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x70 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x70 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x74 "VPAC_CTSET_CTFILT29,Counter Timer 29 Filter Register"
bitfld.long 0x74 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x74 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x74 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x74 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x74 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x74 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x74 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x74 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x78 "VPAC_CTSET_CTFILT30,Counter Timer 30 Filter Register"
bitfld.long 0x78 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x78 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x78 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x78 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x78 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x78 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x78 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x78 0. "FREE,Counter functions while system/core is halted" "0,1"
line.long 0x7C "VPAC_CTSET_CTFILT31,Counter Timer 31 Filter Register"
bitfld.long 0x7C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1"
bitfld.long 0x7C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1"
bitfld.long 0x7C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1"
bitfld.long 0x7C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1"
bitfld.long 0x7C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1"
bitfld.long 0x7C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1"
newline
bitfld.long 0x7C 1. "IDLE,Counter functions while system/core is in idle" "0,1"
bitfld.long 0x7C 0. "FREE,Counter functions while system/core is halted" "0,1"
group.long 0xC00++0x13
line.long 0x00 "VPAC_CTSET_CT_EOI,Counter Timer EOI Register"
bitfld.long 0x00 0. "EOI,EOI value" "0,1"
line.long 0x04 "VPAC_CTSET_CTIRQSTAT_RAW,Counter Timer IRQSTATUS RAW Register"
line.long 0x08 "VPAC_CTSET_CTIRQSTAT,Counter Timer IRQSTATUS Register"
line.long 0x0C "VPAC_CTSET_CTIRQENABLE_SET,Counter Timer IRQENABLE_SET Register"
line.long 0x10 "VPAC_CTSET_CTIRQENABLE_CLR,Counter Timer IRQENABLE_CLR Register"
group.long 0x1800++0x07
line.long 0x00 "VPAC_CTSET_STPTCR,STP Trace Control Register"
rbitfld.long 0x00 24. "MOD_FIFOFULL,STPMI2ATB internal MID packet fifo is full" "0,1"
rbitfld.long 0x00 23. "DATA_FIFOFULL,STPMI2ATB internal Data packet fifo is full" "0,1"
bitfld.long 0x00 5. "COMPEN,Compression of Data enable" "0,1"
rbitfld.long 0x00 2. "SYNCEN,The value 1 indicates" "0,1"
bitfld.long 0x00 1. "TSEN,Timestamp Enable" "0,1"
line.long 0x04 "VPAC_CTSET_STPTID,STP Trace ID Register"
hexmask.long.byte 0x04 0.--6. 1. "TRACEID,Trace ID value"
group.long 0x1810++0x0B
line.long 0x00 "VPAC_CTSET_STPASYNC,STP Synchronization Control Register"
bitfld.long 0x00 12. "EXPMODE,Exponent mode A value of 1 sets count to 2 to the Nth where Nth is ((bits" "0,1"
hexmask.long.word 0x00 0.--11. 1. "COUNT,The number of bytes between Synchronization packets"
line.long 0x04 "VPAC_CTSET_STPFFCR,STP Flush Control Register"
bitfld.long 0x04 5. "FORCEFLUSH,Write a 1 to force a flush automatically clears after the operation is complete" "0,1"
bitfld.long 0x04 1. "ASYNCPE,Async Priority Enable" "0,1"
bitfld.long 0x04 0. "AUTOFLUSH,Auto flush enable" "0,1"
line.long 0x08 "VPAC_CTSET_STPFEAT1,STP Features 1 Register"
bitfld.long 0x08 27.--31. "STP_RTLVER,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 24.--26. "STP_MAJVER,Functional Major Version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 22.--23. "STP_CUSTVER,Custom Version (not used)" "0,1,2,3"
bitfld.long 0x08 17.--21. "STP_MINVER,Functional Minor Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--6. "VERSION,STP2.0 Time Stamp Value of 011 indicates Natural binary timestamp a value of 100 indicates gray binary timestamps" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--3. "PROT,Protocol Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0xBC0)++0x03
line.long 0x00 "VPAC_CTSET_CTCNTR$1,Counter Timer Counter Register 16"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0xB80)++0x03
line.long 0x00 "VPAC_CTSET_CTCNTR$1,Counter Timer Counter Register 0"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xAC0)++0x03
line.long 0x00 "VPAC_CTSET_CTOWN$1,Counter/Timer Ownership register 16"
bitfld.long 0x00 30.--31. "OWNERSHIP,Counter/Timer Ownership Status" "0,1,2,3"
bitfld.long 0x00 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1"
newline
rbitfld.long 0x00 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state " "0,1"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA80)++0x03
line.long 0x00 "VPAC_CTSET_CTOWN$1,Counter/Timer Ownership register 0"
bitfld.long 0x00 30.--31. "OWNERSHIP,Counter/Timer Ownership Status" "0,1,2,3"
bitfld.long 0x00 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1"
newline
rbitfld.long 0x00 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state " "0,1"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA40)++0x03
line.long 0x00 "VPAC_CTSET_CTCR$1,Counter Timer Control Register 16"
hexmask.long.byte 0x00 24.--31. 1. "WDRESET,WD reset event input selector"
hexmask.long.byte 0x00 16.--23. 1. "INPSEL,Counter Timer input selection"
newline
bitfld.long 0x00 14.--15. "MODESEL,Counter is in duration or occurrence mode" "0,1,2,3"
bitfld.long 0x00 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1"
newline
bitfld.long 0x00 12. "DBG_TRIG_STAT,Debug event triggered" "0,1"
bitfld.long 0x00 11. "WDMODE,WD Timer mode selection" "0,1"
newline
bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1"
bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1"
newline
bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1"
bitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "0,1"
newline
bitfld.long 0x00 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1"
bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1"
bitfld.long 0x00 1. "RESET,Counter reset control" "0,1"
newline
bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA00)++0x03
line.long 0x00 "VPAC_CTSET_CTCR$1,Counter Timer Control Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDRESET,WD reset event input selector"
hexmask.long.byte 0x00 16.--23. 1. "INPSEL,Counter Timer input selection"
newline
bitfld.long 0x00 14.--15. "MODESEL,Counter is in duration or occurrence mode" "0,1,2,3"
bitfld.long 0x00 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1"
newline
bitfld.long 0x00 12. "DBG_TRIG_STAT,Debug event triggered" "0,1"
bitfld.long 0x00 11. "WDMODE,WD Timer mode selection" "0,1"
newline
bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1"
bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1"
newline
bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1"
bitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "0,1"
newline
bitfld.long 0x00 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1"
bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1"
newline
bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1"
bitfld.long 0x00 1. "RESET,Counter reset control" "0,1"
newline
bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1"
repeat.end
repeat 7. (list 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x8A4)++0x03
line.long 0x00 "VPAC_CTSET_CTDBGSGL$1,Counter Timer Debug Event Register 1"
hexmask.long.byte 0x00 0.--7. 1. "INPSEL,Counter Timer input selection"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x840)++0x03
line.long 0x00 "VPAC_CTSET_CTINTVLR$1,These registers contain the interval match value for the corresponding timers in the CTSET"
repeat.end
tree.end
tree.end
tree "VPAC_ECC_AGGR"
tree "VPAC0_KSDW_ECC_AGGR_CFG"
base ad:0x2A60000
rgroup.long 0x00++0x03
line.long 0x00 "VPAC_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "VPAC_ECC_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "VPAC_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "VPAC_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "VPAC_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "VPAC_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 13. "UTC1_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x04 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x04 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 8. "UTC1_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc1_dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x04 7. "UTC1_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc1_dru_eng_edc_pend" "0,1"
bitfld.long 0x04 6. "UTC0_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_state_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer2_ecc_pend" "0,1"
bitfld.long 0x04 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer1_ecc_pend" "0,1"
newline
bitfld.long 0x04 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 1. "UTC0_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc0_dru_psi_edc_pend" "0,1"
bitfld.long 0x04 0. "UTC0_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc0_dru_eng_edc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "VPAC_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 8. "UTC1_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "UTC1_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_eng_edc_pend" "0,1"
bitfld.long 0x00 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_state_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer2_ecc_pend" "0,1"
bitfld.long 0x00 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer1_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 1. "UTC0_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_psi_edc_pend" "0,1"
bitfld.long 0x00 0. "UTC0_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_eng_edc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "VPAC_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 8. "UTC1_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "UTC1_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_eng_edc_pend" "0,1"
bitfld.long 0x00 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_state_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer2_ecc_pend" "0,1"
bitfld.long 0x00 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer1_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 1. "UTC0_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_psi_edc_pend" "0,1"
bitfld.long 0x00 0. "UTC0_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_eng_edc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "VPAC_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "VPAC_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 13. "UTC1_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x04 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x04 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 8. "UTC1_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc1_dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x04 7. "UTC1_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc1_dru_eng_edc_pend" "0,1"
bitfld.long 0x04 6. "UTC0_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_state_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer2_ecc_pend" "0,1"
bitfld.long 0x04 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer1_ecc_pend" "0,1"
newline
bitfld.long 0x04 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer0_ecc_pend" "0,1"
bitfld.long 0x04 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x04 1. "UTC0_DRU_PSI_EDC_PEND,Interrupt Pending Status for utc0_dru_psi_edc_pend" "0,1"
bitfld.long 0x04 0. "UTC0_DRU_ENG_EDC_PEND,Interrupt Pending Status for utc0_dru_eng_edc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "VPAC_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 8. "UTC1_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "UTC1_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc1_dru_eng_edc_pend" "0,1"
bitfld.long 0x00 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_state_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer2_ecc_pend" "0,1"
bitfld.long 0x00 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer1_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 1. "UTC0_DRU_PSI_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_psi_edc_pend" "0,1"
bitfld.long 0x00 0. "UTC0_DRU_ENG_EDC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_eng_edc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "VPAC_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 13. "UTC1_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_state_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 12. "UTC1_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer2_ecc_pend" "0,1"
newline
bitfld.long 0x00 11. "UTC1_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer1_ecc_pend" "0,1"
bitfld.long 0x00 10. "UTC1_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_queue_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 9. "UTC1_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_tpram_dru_response_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 8. "UTC1_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_psi_edc_pend" "0,1"
newline
bitfld.long 0x00 7. "UTC1_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc1_dru_eng_edc_pend" "0,1"
bitfld.long 0x00 6. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_state_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer2_ecc_pend" "0,1"
bitfld.long 0x00 4. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer1_ecc_pend" "0,1"
newline
bitfld.long 0x00 3. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer0_ecc_pend" "0,1"
bitfld.long 0x00 2. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1"
newline
bitfld.long 0x00 1. "UTC0_DRU_PSI_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_psi_edc_pend" "0,1"
bitfld.long 0x00 0. "UTC0_DRU_ENG_EDC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_eng_edc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "VPAC_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "VPAC_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "VPAC_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "VPAC_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "VPAC_HTS"
tree "VPAC0_HTS_S_VBUSP"
base ad:0xF008000
group.long 0x00++0x1B
line.long 0x00 "VPAC_HTS_PIPELINE_CONTROL_0,Enable pipeline to activate all connected scheduler"
bitfld.long 0x00 0. "PIPE_EN,Pipeline 0 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x04 "VPAC_HTS_PIPELINE_CONTROL_1,Enable pipeline to activate all connected scheduler"
bitfld.long 0x04 0. "PIPE_EN,Pipeline 1 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x08 "VPAC_HTS_PIPELINE_CONTROL_2,Enable pipeline to activate all connected scheduler"
bitfld.long 0x08 0. "PIPE_EN,Pipeline 2 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x0C "VPAC_HTS_PIPELINE_CONTROL_3,Enable pipeline to activate all connected scheduler"
bitfld.long 0x0C 0. "PIPE_EN,Pipeline 3 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x10 "VPAC_HTS_PIPELINE_CONTROL_4,Enable pipeline to activate all connected scheduler"
bitfld.long 0x10 0. "PIPE_EN,Pipeline 4 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x14 "VPAC_HTS_PIPELINE_CONTROL_5,Enable pipeline to activate all connected scheduler"
bitfld.long 0x14 0. "PIPE_EN,Pipeline 5 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
line.long 0x18 "VPAC_HTS_PIPELINE_CONTROL_6,Enable pipeline to activate all connected scheduler"
bitfld.long 0x18 0. "PIPE_EN,Pipeline 6 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0,1"
group.long 0x50++0x5B
line.long 0x00 "VPAC_HTS_HWA0_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA0 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA0 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA0 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA0_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA0_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA0 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA0 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA0_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA0 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA0_CONS0_CONTROL,Controlling consumer socket 0 for HWA0"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA0_CONS1_CONTROL,Controlling consumer socket 1 for HWA0"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA0_CONS2_CONTROL,Controlling consumer socket 2 for HWA0"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA0_CONS3_CONTROL,Controlling consumer socket 3 for HWA0"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA0_CONS4_CONTROL,Controlling consumer socket 4 for HWA0"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "VPAC_HTS_HWA0_CONS5_CONTROL,Controlling consumer socket 5 for HWA0"
hexmask.long.word 0x24 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 5"
bitfld.long 0x24 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1"
line.long 0x28 "VPAC_HTS_HWA0_PROD0_CONTROL,Controlling producer socket0 for HWA0"
hexmask.long.byte 0x28 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 0"
bitfld.long 0x28 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA0_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA0"
bitfld.long 0x2C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x2C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x2C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x30 "VPAC_HTS_HWA0_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod0"
hexmask.long.word 0x30 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x30 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x30 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x34 "VPAC_HTS_HWA0_PA0_CONTROL,control register to manage pattern adapter on HWA0 prod socket0"
hexmask.long.word 0x34 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x34 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x34 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x34 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x34 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x38 "VPAC_HTS_HWA0_PA0_PRODCOUNT,count values for HWA0 prod socket0"
hexmask.long.word 0x38 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x38 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "VPAC_HTS_HWA0_PROD1_CONTROL,Controlling producer socket1 for HWA0"
hexmask.long.byte 0x3C 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 1"
bitfld.long 0x3C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA0_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA0"
bitfld.long 0x40 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x40 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x40 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x44 "VPAC_HTS_HWA0_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod1"
hexmask.long.word 0x44 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x44 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x44 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x48 "VPAC_HTS_HWA0_PA1_CONTROL,control register to manage pattern adapter on HWA0 prod socket1"
hexmask.long.word 0x48 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x48 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x48 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x48 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x48 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x4C "VPAC_HTS_HWA0_PA1_PRODCOUNT,count values for HWA0 prod socket1"
hexmask.long.word 0x4C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x4C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x50 "VPAC_HTS_HWA0_PROD2_CONTROL,Controlling producer socket2 for HWA0"
hexmask.long.byte 0x50 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 2"
bitfld.long 0x50 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x54 "VPAC_HTS_HWA0_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA0"
bitfld.long 0x54 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x54 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x54 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x58 "VPAC_HTS_HWA0_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod2"
hexmask.long.word 0x58 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x58 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x58 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xB4++0x0B
line.long 0x00 "VPAC_HTS_HWA0_PROD3_CONTROL,Controlling producer socket3 for HWA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 3"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA0_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA0_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xC8++0x0B
line.long 0x00 "VPAC_HTS_HWA0_PROD4_CONTROL,Controlling producer socket4 for HWA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 4"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA0_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA0_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xDC++0x0B
line.long 0x00 "VPAC_HTS_HWA0_PROD5_CONTROL,Controlling producer socket5 for HWA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 5"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA0_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA0_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xF0++0x0B
line.long 0x00 "VPAC_HTS_HWA0_PROD6_CONTROL,Controlling producer socket6 for HWA0"
bitfld.long 0x00 24.--26. "MASK_SELECT,define which tdone_mask apply to prod socket 6" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 6"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA0_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA0_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA0 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x104++0x5B
line.long 0x00 "VPAC_HTS_HWA1_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA1 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA1 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA1 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA1_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA1_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA1 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA1 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA1_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA1 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA1_CONS0_CONTROL,Controlling consumer socket 0 for HWA1"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA1_CONS1_CONTROL,Controlling consumer socket 1 for HWA1"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA1_CONS2_CONTROL,Controlling consumer socket 2 for HWA1"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA1_CONS3_CONTROL,Controlling consumer socket 3 for HWA1"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA1_CONS4_CONTROL,Controlling consumer socket 4 for HWA1"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "VPAC_HTS_HWA1_CONS5_CONTROL,Controlling consumer socket 5 for HWA1"
hexmask.long.word 0x24 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 5"
bitfld.long 0x24 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "0,1"
line.long 0x28 "VPAC_HTS_HWA1_PROD0_CONTROL,Controlling producer socket0 for HWA1"
hexmask.long.byte 0x28 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 0"
bitfld.long 0x28 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA1_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA1"
bitfld.long 0x2C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x2C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x2C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x30 "VPAC_HTS_HWA1_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod0"
hexmask.long.word 0x30 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x30 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x30 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x34 "VPAC_HTS_HWA1_PA0_CONTROL,control register to manage pattern adapter on HWA1 prod socket0"
hexmask.long.word 0x34 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x34 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x34 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x34 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x34 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x38 "VPAC_HTS_HWA1_PA0_PRODCOUNT,count values for HWA1 prod socket0"
hexmask.long.word 0x38 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x38 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "VPAC_HTS_HWA1_PROD1_CONTROL,Controlling producer socket1 for HWA1"
hexmask.long.byte 0x3C 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 1"
bitfld.long 0x3C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA1_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA1"
bitfld.long 0x40 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x40 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x40 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x44 "VPAC_HTS_HWA1_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod1"
hexmask.long.word 0x44 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x44 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x44 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x48 "VPAC_HTS_HWA1_PA1_CONTROL,control register to manage pattern adapter on HWA1 prod socket1"
hexmask.long.word 0x48 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x48 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x48 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x48 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x48 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x4C "VPAC_HTS_HWA1_PA1_PRODCOUNT,count values for HWA1 prod socket1"
hexmask.long.word 0x4C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x4C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x50 "VPAC_HTS_HWA1_PROD2_CONTROL,Controlling producer socket2 for HWA1"
hexmask.long.byte 0x50 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 2"
bitfld.long 0x50 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x54 "VPAC_HTS_HWA1_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA1"
bitfld.long 0x54 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x54 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x54 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x58 "VPAC_HTS_HWA1_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod2"
hexmask.long.word 0x58 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x58 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x58 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x168++0x0B
line.long 0x00 "VPAC_HTS_HWA1_PROD3_CONTROL,Controlling producer socket3 for HWA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 3"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA1_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA1_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x17C++0x0B
line.long 0x00 "VPAC_HTS_HWA1_PROD4_CONTROL,Controlling producer socket4 for HWA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 4"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA1_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA1_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x190++0x0B
line.long 0x00 "VPAC_HTS_HWA1_PROD5_CONTROL,Controlling producer socket5 for HWA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 5"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA1_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA1_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x1A4++0x0B
line.long 0x00 "VPAC_HTS_HWA1_PROD6_CONTROL,Controlling producer socket6 for HWA1"
bitfld.long 0x00 24.--26. "MASK_SELECT,define which tdone_mask apply to prod socket 6" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 6"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA1_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA1_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA1 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x1B8++0xB3
line.long 0x00 "VPAC_HTS_HWA2_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA2 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA2 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA2 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA2_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA2_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA2 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA2 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA2_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA2 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA2_CONS0_CONTROL,Controlling consumer socket 0 for HWA2"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA2_CONS1_CONTROL,Controlling consumer socket 1 for HWA2"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA2_CONS2_CONTROL,Controlling consumer socket 2 for HWA2"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA2_PROD0_CONTROL,Controlling producer socket0 for HWA2"
bitfld.long 0x1C 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x1C 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 0"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA2_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA2"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA2_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod0"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA2_PA0_CONTROL,control register to manage pattern adapter on HWA2 prod socket0"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA2_PA0_PRODCOUNT,count values for HWA2 prod socket0"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA2_PROD1_CONTROL,Controlling producer socket1 for HWA2"
bitfld.long 0x30 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x30 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 1"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA2_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA2"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA2_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod1"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA2_PA1_CONTROL,control register to manage pattern adapter on HWA2 prod socket1"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA2_PA1_PRODCOUNT,count values for HWA2 prod socket1"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA2_PROD2_CONTROL,Controlling producer socket2 for HWA2"
bitfld.long 0x44 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x44 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 2"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA2_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA2"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA2_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod2"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x50 "VPAC_HTS_HWA2_PA2_CONTROL,control register to manage pattern adapter on HWA2 prod socket2"
hexmask.long.word 0x50 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x50 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x50 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x50 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x50 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x54 "VPAC_HTS_HWA2_PA2_PRODCOUNT,count values for HWA2 prod socket2"
hexmask.long.word 0x54 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x54 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x58 "VPAC_HTS_HWA2_PROD3_CONTROL,Controlling producer socket3 for HWA2"
bitfld.long 0x58 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x58 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x58 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 3"
bitfld.long 0x58 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x5C "VPAC_HTS_HWA2_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA2"
bitfld.long 0x5C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x5C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x5C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x60 "VPAC_HTS_HWA2_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod3"
hexmask.long.word 0x60 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x60 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x60 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x64 "VPAC_HTS_HWA2_PA3_CONTROL,control register to manage pattern adapter on HWA2 prod socket3"
hexmask.long.word 0x64 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x64 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x64 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x64 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x64 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x68 "VPAC_HTS_HWA2_PA3_PRODCOUNT,count values for HWA2 prod socket3"
hexmask.long.word 0x68 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x68 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x6C "VPAC_HTS_HWA2_PROD4_CONTROL,Controlling producer socket4 for HWA2"
bitfld.long 0x6C 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4" "0,1,2,3"
hexmask.long.byte 0x6C 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 4"
bitfld.long 0x6C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x70 "VPAC_HTS_HWA2_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA2"
bitfld.long 0x70 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x70 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x70 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x74 "VPAC_HTS_HWA2_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod4"
hexmask.long.word 0x74 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x74 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x74 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x78 "VPAC_HTS_HWA2_PA4_CONTROL,control register to manage pattern adapter on HWA2 prod socket4"
hexmask.long.word 0x78 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x78 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x78 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x78 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x78 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x7C "VPAC_HTS_HWA2_PA4_PRODCOUNT,count values for HWA2 prod socket4"
hexmask.long.word 0x7C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x7C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "VPAC_HTS_HWA2_PROD5_CONTROL,Controlling producer socket5 for HWA2"
bitfld.long 0x80 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 5" "0,1,2,3"
hexmask.long.byte 0x80 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 5"
bitfld.long 0x80 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x84 "VPAC_HTS_HWA2_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA2"
bitfld.long 0x84 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x84 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x84 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x88 "VPAC_HTS_HWA2_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod5"
hexmask.long.word 0x88 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x88 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x88 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x8C "VPAC_HTS_HWA2_PA5_CONTROL,control register to manage pattern adapter on HWA2 prod socket5"
hexmask.long.word 0x8C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x8C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x8C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x8C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x8C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x90 "VPAC_HTS_HWA2_PA5_PRODCOUNT,count values for HWA2 prod socket5"
hexmask.long.word 0x90 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x90 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x94 "VPAC_HTS_HWA2_PROD6_CONTROL,Controlling producer socket6 for HWA2"
bitfld.long 0x94 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 6" "0,1,2,3"
hexmask.long.byte 0x94 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 6"
bitfld.long 0x94 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x98 "VPAC_HTS_HWA2_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA2"
bitfld.long 0x98 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x98 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x98 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x9C "VPAC_HTS_HWA2_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod6"
hexmask.long.word 0x9C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x9C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x9C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0xA0 "VPAC_HTS_HWA2_PA6_CONTROL,control register to manage pattern adapter on HWA2 prod socket6"
hexmask.long.word 0xA0 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0xA0 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0xA0 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0xA0 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0xA0 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0xA4 "VPAC_HTS_HWA2_PA6_PRODCOUNT,count values for HWA2 prod socket6"
hexmask.long.word 0xA4 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0xA4 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "VPAC_HTS_HWA2_PROD7_CONTROL,Controlling producer socket7 for HWA2"
bitfld.long 0xA8 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 7" "0,1,2,3"
hexmask.long.byte 0xA8 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 7"
bitfld.long 0xA8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0xAC "VPAC_HTS_HWA2_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA2"
bitfld.long 0xAC 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0xAC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0xAC 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0xB0 "VPAC_HTS_HWA2_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA2 prod7"
hexmask.long.word 0xB0 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0xB0 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0xB0 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x274++0xB3
line.long 0x00 "VPAC_HTS_HWA3_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "0,1"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA3 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA3 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA3 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA3_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA3_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA3 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA3 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA3_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA3 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA3_CONS0_CONTROL,Controlling consumer socket 0 for HWA3"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA3_CONS1_CONTROL,Controlling consumer socket 1 for HWA3"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA3_CONS2_CONTROL,Controlling consumer socket 2 for HWA3"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA3_PROD0_CONTROL,Controlling producer socket0 for HWA3"
bitfld.long 0x1C 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x1C 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 0"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA3_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA3"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA3_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod0"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA3_PA0_CONTROL,control register to manage pattern adapter on HWA3 prod socket0"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA3_PA0_PRODCOUNT,count values for HWA3 prod socket0"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA3_PROD1_CONTROL,Controlling producer socket1 for HWA3"
bitfld.long 0x30 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x30 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 1"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA3_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA3"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA3_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod1"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA3_PA1_CONTROL,control register to manage pattern adapter on HWA3 prod socket1"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA3_PA1_PRODCOUNT,count values for HWA3 prod socket1"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA3_PROD2_CONTROL,Controlling producer socket2 for HWA3"
bitfld.long 0x44 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x44 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 2"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA3_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA3"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA3_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod2"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x50 "VPAC_HTS_HWA3_PA2_CONTROL,control register to manage pattern adapter on HWA3 prod socket2"
hexmask.long.word 0x50 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x50 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x50 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x50 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x50 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x54 "VPAC_HTS_HWA3_PA2_PRODCOUNT,count values for HWA3 prod socket2"
hexmask.long.word 0x54 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x54 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x58 "VPAC_HTS_HWA3_PROD3_CONTROL,Controlling producer socket3 for HWA3"
bitfld.long 0x58 22.--23. "PARTIAL_BPR_TRIGMODE," "0,1,2,3"
bitfld.long 0x58 18.--21. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x58 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 3"
bitfld.long 0x58 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x5C "VPAC_HTS_HWA3_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA3"
bitfld.long 0x5C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x5C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x5C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x60 "VPAC_HTS_HWA3_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod3"
hexmask.long.word 0x60 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x60 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x60 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x64 "VPAC_HTS_HWA3_PA3_CONTROL,control register to manage pattern adapter on HWA3 prod socket3"
hexmask.long.word 0x64 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x64 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x64 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x64 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x64 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x68 "VPAC_HTS_HWA3_PA3_PRODCOUNT,count values for HWA3 prod socket3"
hexmask.long.word 0x68 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x68 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x6C "VPAC_HTS_HWA3_PROD4_CONTROL,Controlling producer socket4 for HWA3"
bitfld.long 0x6C 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4" "0,1,2,3"
hexmask.long.byte 0x6C 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 4"
bitfld.long 0x6C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x70 "VPAC_HTS_HWA3_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA3"
bitfld.long 0x70 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x70 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x70 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x74 "VPAC_HTS_HWA3_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod4"
hexmask.long.word 0x74 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x74 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x74 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x78 "VPAC_HTS_HWA3_PA4_CONTROL,control register to manage pattern adapter on HWA3 prod socket4"
hexmask.long.word 0x78 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x78 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x78 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x78 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x78 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x7C "VPAC_HTS_HWA3_PA4_PRODCOUNT,count values for HWA3 prod socket4"
hexmask.long.word 0x7C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x7C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x80 "VPAC_HTS_HWA3_PROD5_CONTROL,Controlling producer socket5 for HWA3"
bitfld.long 0x80 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 5" "0,1,2,3"
hexmask.long.byte 0x80 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 5"
bitfld.long 0x80 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x84 "VPAC_HTS_HWA3_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA3"
bitfld.long 0x84 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x84 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x84 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x88 "VPAC_HTS_HWA3_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod5"
hexmask.long.word 0x88 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x88 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x88 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x8C "VPAC_HTS_HWA3_PA5_CONTROL,control register to manage pattern adapter on HWA3 prod socket5"
hexmask.long.word 0x8C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x8C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x8C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x8C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x8C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x90 "VPAC_HTS_HWA3_PA5_PRODCOUNT,count values for HWA3 prod socket5"
hexmask.long.word 0x90 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x90 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x94 "VPAC_HTS_HWA3_PROD6_CONTROL,Controlling producer socket6 for HWA3"
bitfld.long 0x94 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 6" "0,1,2,3"
hexmask.long.byte 0x94 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 6"
bitfld.long 0x94 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x98 "VPAC_HTS_HWA3_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA3"
bitfld.long 0x98 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x98 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x98 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x9C "VPAC_HTS_HWA3_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod6"
hexmask.long.word 0x9C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x9C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x9C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0xA0 "VPAC_HTS_HWA3_PA6_CONTROL,control register to manage pattern adapter on HWA3 prod socket6"
hexmask.long.word 0xA0 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0xA0 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0xA0 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0xA0 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0xA0 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0xA4 "VPAC_HTS_HWA3_PA6_PRODCOUNT,count values for HWA3 prod socket6"
hexmask.long.word 0xA4 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0xA4 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xA8 "VPAC_HTS_HWA3_PROD7_CONTROL,Controlling producer socket7 for HWA3"
bitfld.long 0xA8 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 7" "0,1,2,3"
hexmask.long.byte 0xA8 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 7"
bitfld.long 0xA8 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0xAC "VPAC_HTS_HWA3_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA3"
bitfld.long 0xAC 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0xAC 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0xAC 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0xB0 "VPAC_HTS_HWA3_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA3 prod7"
hexmask.long.word 0xB0 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0xB0 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0xB0 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x330++0x23
line.long 0x00 "VPAC_HTS_HWA4_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA4 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA4 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA4 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA4_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA4 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA4 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA4_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA4 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA4_CONS0_CONTROL,Controlling consumer socket 0 for HWA4"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA4_CONS1_CONTROL,Controlling consumer socket 1 for HWA4"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA4_PROD0_CONTROL,Controlling producer socket0 for HWA4"
hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 0"
bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA4_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA4"
bitfld.long 0x1C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x20 "VPAC_HTS_HWA4_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod0"
hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x35C++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD1_CONTROL,Controlling producer socket1 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 1"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod1"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x370++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD2_CONTROL,Controlling producer socket2 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 2"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod2"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x384++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD3_CONTROL,Controlling producer socket3 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 3"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x398++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD4_CONTROL,Controlling producer socket4 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 4"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3AC++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD5_CONTROL,Controlling producer socket5 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 5"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3C0++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD6_CONTROL,Controlling producer socket6 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 6"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3D4++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD7_CONTROL,Controlling producer socket7 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 7"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod7"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3E8++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD8_CONTROL,Controlling producer socket8 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 8"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD8_BUF_CONTROL,Controlling producer socket8 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD8_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod8"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x3FC++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD9_CONTROL,Controlling producer socket9 for HWA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 9"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD9_BUF_CONTROL,Controlling producer socket9 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD9_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod9"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x410++0x0B
line.long 0x00 "VPAC_HTS_HWA4_PROD10_CONTROL,Controlling producer socket10 for HWA4"
bitfld.long 0x00 24.--27. "MASK_SELECT,define which tdone_mask apply to prod socket 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 10"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA4_PROD10_BUF_CONTROL,Controlling producer socket10 buffer for HWA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA4_PROD10_COUNT,Defining count values for pre/post load for generating pend by HWA4 prod10"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x424++0x23
line.long 0x00 "VPAC_HTS_HWA5_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA5 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA5 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA5 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA5_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA5 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA5 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA5_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA5 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA5_CONS0_CONTROL,Controlling consumer socket 0 for HWA5"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA5_CONS1_CONTROL,Controlling consumer socket 1 for HWA5"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA5_PROD0_CONTROL,Controlling producer socket0 for HWA5"
hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 0"
bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA5_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA5"
bitfld.long 0x1C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x20 "VPAC_HTS_HWA5_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod0"
hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x450++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD1_CONTROL,Controlling producer socket1 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 1"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod1"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x464++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD2_CONTROL,Controlling producer socket2 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 2"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod2"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x478++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD3_CONTROL,Controlling producer socket3 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 3"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod3"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x48C++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD4_CONTROL,Controlling producer socket4 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 4"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod4"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4A0++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD5_CONTROL,Controlling producer socket5 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 5"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD5_BUF_CONTROL,Controlling producer socket5 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD5_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod5"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4B4++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD6_CONTROL,Controlling producer socket6 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 6"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD6_BUF_CONTROL,Controlling producer socket6 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD6_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod6"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4C8++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD7_CONTROL,Controlling producer socket7 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 7"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD7_BUF_CONTROL,Controlling producer socket7 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD7_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod7"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4DC++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD8_CONTROL,Controlling producer socket8 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 8"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD8_BUF_CONTROL,Controlling producer socket8 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD8_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod8"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x4F0++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD9_CONTROL,Controlling producer socket9 for HWA5"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 9"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD9_BUF_CONTROL,Controlling producer socket9 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD9_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod9"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x504++0x0B
line.long 0x00 "VPAC_HTS_HWA5_PROD10_CONTROL,Controlling producer socket10 for HWA5"
bitfld.long 0x00 24.--27. "MASK_SELECT,define which tdone_mask apply to prod socket 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 10"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA5_PROD10_BUF_CONTROL,Controlling producer socket10 buffer for HWA5"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA5_PROD10_COUNT,Defining count values for pre/post load for generating pend by HWA5 prod10"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x518++0x23
line.long 0x00 "VPAC_HTS_HWA6_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA6 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA6 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA6 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA6_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA6_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA6 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA6 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA6_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA6 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA6_CONS0_CONTROL,Controlling consumer socket 0 for HWA6"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA6_CONS1_CONTROL,Controlling consumer socket 1 for HWA6"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA6_PROD0_CONTROL,Controlling producer socket0 for HWA6"
hexmask.long.byte 0x18 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 0"
bitfld.long 0x18 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA6_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA6"
bitfld.long 0x1C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x1C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x1C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x20 "VPAC_HTS_HWA6_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA6 prod0"
hexmask.long.word 0x20 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x20 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x20 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x544++0x0B
line.long 0x00 "VPAC_HTS_HWA6_PROD1_CONTROL,Controlling producer socket1 for HWA6"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 1"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA6_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA6"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_HWA6_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA6 prod1"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x558++0x7F
line.long 0x00 "VPAC_HTS_HWA7_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA7 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA7 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA7 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA7_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA7_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA7 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA7 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA7_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA7 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA7_CONS0_CONTROL,Controlling consumer socket 0 for HWA7"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA7_CONS1_CONTROL,Controlling consumer socket 1 for HWA7"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA7_CONS2_CONTROL,Controlling consumer socket 2 for HWA7"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA7_CONS3_CONTROL,Controlling consumer socket 3 for HWA7"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA7_CONS4_CONTROL,Controlling consumer socket 4 for HWA7"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "VPAC_HTS_HWA7_PROD0_CONTROL,Controlling producer socket0 for HWA7"
hexmask.long.byte 0x24 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 0"
bitfld.long 0x24 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x28 "VPAC_HTS_HWA7_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA7"
bitfld.long 0x28 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x28 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x28 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x2C "VPAC_HTS_HWA7_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod0"
hexmask.long.word 0x2C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x2C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x2C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x30 "VPAC_HTS_HWA7_PA0_CONTROL,control register to manage pattern adapter on HWA7 prod socket0"
hexmask.long.word 0x30 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x30 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x30 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x30 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x30 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA7_PA0_PRODCOUNT,count values for HWA7 prod socket0"
hexmask.long.word 0x34 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x34 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "VPAC_HTS_HWA7_PROD1_CONTROL,Controlling producer socket1 for HWA7"
hexmask.long.byte 0x38 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 1"
bitfld.long 0x38 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x3C "VPAC_HTS_HWA7_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA7"
bitfld.long 0x3C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x3C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x3C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x40 "VPAC_HTS_HWA7_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod1"
hexmask.long.word 0x40 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x40 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x40 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x44 "VPAC_HTS_HWA7_PA1_CONTROL,control register to manage pattern adapter on HWA7 prod socket1"
hexmask.long.word 0x44 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x44 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x44 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x44 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x44 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA7_PA1_PRODCOUNT,count values for HWA7 prod socket1"
hexmask.long.word 0x48 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x48 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4C "VPAC_HTS_HWA7_PROD2_CONTROL,Controlling producer socket2 for HWA7"
hexmask.long.byte 0x4C 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 2"
bitfld.long 0x4C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x50 "VPAC_HTS_HWA7_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA7"
bitfld.long 0x50 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x50 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x50 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x54 "VPAC_HTS_HWA7_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod2"
hexmask.long.word 0x54 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x54 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x54 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x58 "VPAC_HTS_HWA7_PA2_CONTROL,control register to manage pattern adapter on HWA7 prod socket2"
hexmask.long.word 0x58 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x58 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x58 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x58 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x58 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x5C "VPAC_HTS_HWA7_PA2_PRODCOUNT,count values for HWA7 prod socket2"
hexmask.long.word 0x5C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x5C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "VPAC_HTS_HWA7_PROD3_CONTROL,Controlling producer socket3 for HWA7"
hexmask.long.byte 0x60 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 3"
bitfld.long 0x60 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x64 "VPAC_HTS_HWA7_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA7"
bitfld.long 0x64 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x64 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x64 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x68 "VPAC_HTS_HWA7_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod3"
hexmask.long.word 0x68 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x68 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x68 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x6C "VPAC_HTS_HWA7_PA3_CONTROL,control register to manage pattern adapter on HWA7 prod socket3"
hexmask.long.word 0x6C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x6C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x6C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x6C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x6C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x70 "VPAC_HTS_HWA7_PA3_PRODCOUNT,count values for HWA7 prod socket3"
hexmask.long.word 0x70 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x70 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x74 "VPAC_HTS_HWA7_PROD4_CONTROL,Controlling producer socket4 for HWA7"
bitfld.long 0x74 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4" "0,1,2,3"
hexmask.long.byte 0x74 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 4"
bitfld.long 0x74 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x78 "VPAC_HTS_HWA7_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA7"
bitfld.long 0x78 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x78 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x78 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x7C "VPAC_HTS_HWA7_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA7 prod4"
hexmask.long.word 0x7C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x7C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x7C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x5E0++0x7F
line.long 0x00 "VPAC_HTS_HWA8_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA8 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA8 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
newline
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA8 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA8_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
line.long 0x08 "VPAC_HTS_HWA8_WDTIMER,Watchdog timer control register"
hexmask.long.tbyte 0x08 8.--24. 1. "WDTIMER_COUNT,Current value of HWA8 Scheduler watchdog timer count"
bitfld.long 0x08 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0,1"
rbitfld.long 0x08 1. "WDTIMER_STATUS,HWA8 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0,1"
bitfld.long 0x08 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0,1"
line.long 0x0C "VPAC_HTS_HWA8_BW_LIMITER,Scheduler BW Control Register"
hexmask.long.word 0x0C 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start"
bitfld.long 0x0C 1.--4. "BW_TOKEN_COUNT,Max Token count to create average BW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA8 sch '0' --> Disable" "0,1"
line.long 0x10 "VPAC_HTS_HWA8_CONS0_CONTROL,Controlling consumer socket 0 for HWA8"
hexmask.long.word 0x10 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 0"
bitfld.long 0x10 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x14 "VPAC_HTS_HWA8_CONS1_CONTROL,Controlling consumer socket 1 for HWA8"
hexmask.long.word 0x14 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 1"
bitfld.long 0x14 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA8_CONS2_CONTROL,Controlling consumer socket 2 for HWA8"
hexmask.long.word 0x18 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 2"
bitfld.long 0x18 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "0,1"
line.long 0x1C "VPAC_HTS_HWA8_CONS3_CONTROL,Controlling consumer socket 3 for HWA8"
hexmask.long.word 0x1C 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 3"
bitfld.long 0x1C 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA8_CONS4_CONTROL,Controlling consumer socket 4 for HWA8"
hexmask.long.word 0x20 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 4"
bitfld.long 0x20 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "0,1"
line.long 0x24 "VPAC_HTS_HWA8_PROD0_CONTROL,Controlling producer socket0 for HWA8"
hexmask.long.byte 0x24 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 0"
bitfld.long 0x24 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x28 "VPAC_HTS_HWA8_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA8"
bitfld.long 0x28 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x28 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x28 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x2C "VPAC_HTS_HWA8_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod0"
hexmask.long.word 0x2C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x2C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x2C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x30 "VPAC_HTS_HWA8_PA0_CONTROL,control register to manage pattern adapter on HWA8 prod socket0"
hexmask.long.word 0x30 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x30 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x30 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x30 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x30 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA8_PA0_PRODCOUNT,count values for HWA8 prod socket0"
hexmask.long.word 0x34 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x34 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "VPAC_HTS_HWA8_PROD1_CONTROL,Controlling producer socket1 for HWA8"
hexmask.long.byte 0x38 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 1"
bitfld.long 0x38 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x3C "VPAC_HTS_HWA8_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA8"
bitfld.long 0x3C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x3C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x3C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x40 "VPAC_HTS_HWA8_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod1"
hexmask.long.word 0x40 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x40 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x40 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x44 "VPAC_HTS_HWA8_PA1_CONTROL,control register to manage pattern adapter on HWA8 prod socket1"
hexmask.long.word 0x44 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x44 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x44 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x44 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x44 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA8_PA1_PRODCOUNT,count values for HWA8 prod socket1"
hexmask.long.word 0x48 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x48 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4C "VPAC_HTS_HWA8_PROD2_CONTROL,Controlling producer socket2 for HWA8"
hexmask.long.byte 0x4C 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 2"
bitfld.long 0x4C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x50 "VPAC_HTS_HWA8_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA8"
bitfld.long 0x50 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x50 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x50 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x54 "VPAC_HTS_HWA8_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod2"
hexmask.long.word 0x54 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x54 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x54 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x58 "VPAC_HTS_HWA8_PA2_CONTROL,control register to manage pattern adapter on HWA8 prod socket2"
hexmask.long.word 0x58 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x58 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x58 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x58 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x58 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x5C "VPAC_HTS_HWA8_PA2_PRODCOUNT,count values for HWA8 prod socket2"
hexmask.long.word 0x5C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x5C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "VPAC_HTS_HWA8_PROD3_CONTROL,Controlling producer socket3 for HWA8"
hexmask.long.byte 0x60 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 3"
bitfld.long 0x60 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x64 "VPAC_HTS_HWA8_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA8"
bitfld.long 0x64 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x64 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x64 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x68 "VPAC_HTS_HWA8_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod3"
hexmask.long.word 0x68 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x68 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x68 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x6C "VPAC_HTS_HWA8_PA3_CONTROL,control register to manage pattern adapter on HWA8 prod socket3"
hexmask.long.word 0x6C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x6C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x6C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x6C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x6C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x70 "VPAC_HTS_HWA8_PA3_PRODCOUNT,count values for HWA8 prod socket3"
hexmask.long.word 0x70 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x70 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x74 "VPAC_HTS_HWA8_PROD4_CONTROL,Controlling producer socket4 for HWA8"
bitfld.long 0x74 24.--25. "MASK_SELECT,define which tdone_mask apply to prod socket 4" "0,1,2,3"
hexmask.long.byte 0x74 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 4"
bitfld.long 0x74 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x78 "VPAC_HTS_HWA8_PROD4_BUF_CONTROL,Controlling producer socket4 buffer for HWA8"
bitfld.long 0x78 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x78 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x78 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x7C "VPAC_HTS_HWA8_PROD4_COUNT,Defining count values for pre/post load for generating pend by HWA8 prod4"
hexmask.long.word 0x7C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x7C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x7C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x668++0x07
line.long 0x00 "VPAC_HTS_HWA12_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA12"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA12 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA12 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA12 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA12_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x678++0x4F
line.long 0x00 "VPAC_HTS_HWA12_CONS0_CONTROL,Controlling consumer socket 0 for HWA12"
bitfld.long 0x00 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1"
bitfld.long 0x00 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA12_CONS1_CONTROL,Controlling consumer socket 1 for HWA12"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA12_PROD0_CONTROL,Controlling producer socket0 for HWA12"
bitfld.long 0x08 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1"
bitfld.long 0x08 30. "PROD_DEC,writing '1' decrement prod count value" "0,1"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA12_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA12"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA12_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA12_PA0_CONTROL,control register to manage pattern adapter on HWA12 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA12_PA0_PRODCOUNT,count values for HWA12 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA12_PROD1_CONTROL,Controlling producer socket1 for HWA12"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA12_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA12"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA12_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA12_PA1_CONTROL,control register to manage pattern adapter on HWA12 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA12_PA1_PRODCOUNT,count values for HWA12 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA12_PROD2_CONTROL,Controlling producer socket2 for HWA12"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA12_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA12"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA12_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA12_PA2_CONTROL,control register to manage pattern adapter on HWA12 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA12_PA2_PRODCOUNT,count values for HWA12 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA12_PROD3_CONTROL,Controlling producer socket3 for HWA12"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA12_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA12"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA12_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA12 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x6D0++0x07
line.long 0x00 "VPAC_HTS_HWA13_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA13"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA13 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA13 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA13 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA13_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x6E0++0x4F
line.long 0x00 "VPAC_HTS_HWA13_CONS0_CONTROL,Controlling consumer socket 0 for HWA13"
bitfld.long 0x00 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "0,1"
bitfld.long 0x00 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA13_CONS1_CONTROL,Controlling consumer socket 1 for HWA13"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA13_PROD0_CONTROL,Controlling producer socket0 for HWA13"
bitfld.long 0x08 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "0,1"
bitfld.long 0x08 30. "PROD_DEC,writing '1' decrement prod count value" "0,1"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA13_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA13"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA13_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA13_PA0_CONTROL,control register to manage pattern adapter on HWA13 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA13_PA0_PRODCOUNT,count values for HWA13 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA13_PROD1_CONTROL,Controlling producer socket1 for HWA13"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA13_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA13"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA13_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA13_PA1_CONTROL,control register to manage pattern adapter on HWA13 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA13_PA1_PRODCOUNT,count values for HWA13 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA13_PROD2_CONTROL,Controlling producer socket2 for HWA13"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA13_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA13"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA13_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA13_PA2_CONTROL,control register to manage pattern adapter on HWA13 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA13_PA2_PRODCOUNT,count values for HWA13 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA13_PROD3_CONTROL,Controlling producer socket3 for HWA13"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA13_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA13"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA13_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA13 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x738++0x07
line.long 0x00 "VPAC_HTS_HWA14_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA14"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA14 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA14 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA14 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA14_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x748++0x4F
line.long 0x00 "VPAC_HTS_HWA14_CONS0_CONTROL,Controlling consumer socket 0 for HWA14"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA14_CONS1_CONTROL,Controlling consumer socket 1 for HWA14"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA14_PROD0_CONTROL,Controlling producer socket0 for HWA14"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA14_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA14"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA14_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA14_PA0_CONTROL,control register to manage pattern adapter on HWA14 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA14_PA0_PRODCOUNT,count values for HWA14 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA14_PROD1_CONTROL,Controlling producer socket1 for HWA14"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA14_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA14"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA14_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA14_PA1_CONTROL,control register to manage pattern adapter on HWA14 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA14_PA1_PRODCOUNT,count values for HWA14 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA14_PROD2_CONTROL,Controlling producer socket2 for HWA14"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA14_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA14"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA14_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA14_PA2_CONTROL,control register to manage pattern adapter on HWA14 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA14_PA2_PRODCOUNT,count values for HWA14 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA14_PROD3_CONTROL,Controlling producer socket3 for HWA14"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA14_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA14"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA14_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA14 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x7A0++0x07
line.long 0x00 "VPAC_HTS_HWA15_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA15"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA15 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA15 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA15 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA15_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x7B0++0x4F
line.long 0x00 "VPAC_HTS_HWA15_CONS0_CONTROL,Controlling consumer socket 0 for HWA15"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA15_CONS1_CONTROL,Controlling consumer socket 1 for HWA15"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA15_PROD0_CONTROL,Controlling producer socket0 for HWA15"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA15_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA15"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA15_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA15_PA0_CONTROL,control register to manage pattern adapter on HWA15 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA15_PA0_PRODCOUNT,count values for HWA15 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA15_PROD1_CONTROL,Controlling producer socket1 for HWA15"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA15_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA15"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA15_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA15_PA1_CONTROL,control register to manage pattern adapter on HWA15 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA15_PA1_PRODCOUNT,count values for HWA15 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA15_PROD2_CONTROL,Controlling producer socket2 for HWA15"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA15_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA15"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA15_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA15_PA2_CONTROL,control register to manage pattern adapter on HWA15 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA15_PA2_PRODCOUNT,count values for HWA15 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA15_PROD3_CONTROL,Controlling producer socket3 for HWA15"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA15_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA15"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA15_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA15 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x808++0x07
line.long 0x00 "VPAC_HTS_HWA16_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA16"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA16 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA16 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA16 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA16_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x818++0x4F
line.long 0x00 "VPAC_HTS_HWA16_CONS0_CONTROL,Controlling consumer socket 0 for HWA16"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA16_CONS1_CONTROL,Controlling consumer socket 1 for HWA16"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA16_PROD0_CONTROL,Controlling producer socket0 for HWA16"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA16_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA16"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA16_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA16_PA0_CONTROL,control register to manage pattern adapter on HWA16 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA16_PA0_PRODCOUNT,count values for HWA16 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA16_PROD1_CONTROL,Controlling producer socket1 for HWA16"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA16_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA16"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA16_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA16_PA1_CONTROL,control register to manage pattern adapter on HWA16 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA16_PA1_PRODCOUNT,count values for HWA16 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA16_PROD2_CONTROL,Controlling producer socket2 for HWA16"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA16_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA16"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA16_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA16_PA2_CONTROL,control register to manage pattern adapter on HWA16 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA16_PA2_PRODCOUNT,count values for HWA16 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA16_PROD3_CONTROL,Controlling producer socket3 for HWA16"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA16_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA16"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA16_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA16 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x870++0x07
line.long 0x00 "VPAC_HTS_HWA17_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA17"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA17 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA17 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA17 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA17_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x880++0x4F
line.long 0x00 "VPAC_HTS_HWA17_CONS0_CONTROL,Controlling consumer socket 0 for HWA17"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA17_CONS1_CONTROL,Controlling consumer socket 1 for HWA17"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA17_PROD0_CONTROL,Controlling producer socket0 for HWA17"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA17_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA17"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA17_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA17_PA0_CONTROL,control register to manage pattern adapter on HWA17 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA17_PA0_PRODCOUNT,count values for HWA17 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA17_PROD1_CONTROL,Controlling producer socket1 for HWA17"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA17_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA17"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA17_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA17_PA1_CONTROL,control register to manage pattern adapter on HWA17 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA17_PA1_PRODCOUNT,count values for HWA17 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA17_PROD2_CONTROL,Controlling producer socket2 for HWA17"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA17_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA17"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA17_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA17_PA2_CONTROL,control register to manage pattern adapter on HWA17 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA17_PA2_PRODCOUNT,count values for HWA17 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA17_PROD3_CONTROL,Controlling producer socket3 for HWA17"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA17_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA17"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA17_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA17 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x8D8++0x07
line.long 0x00 "VPAC_HTS_HWA18_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA18"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA18 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA18 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA18 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA18_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x8E8++0x4F
line.long 0x00 "VPAC_HTS_HWA18_CONS0_CONTROL,Controlling consumer socket 0 for HWA18"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA18_CONS1_CONTROL,Controlling consumer socket 1 for HWA18"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA18_PROD0_CONTROL,Controlling producer socket0 for HWA18"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA18_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA18"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA18_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA18_PA0_CONTROL,control register to manage pattern adapter on HWA18 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA18_PA0_PRODCOUNT,count values for HWA18 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA18_PROD1_CONTROL,Controlling producer socket1 for HWA18"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA18_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA18"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA18_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA18_PA1_CONTROL,control register to manage pattern adapter on HWA18 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA18_PA1_PRODCOUNT,count values for HWA18 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA18_PROD2_CONTROL,Controlling producer socket2 for HWA18"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA18_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA18"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA18_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA18_PA2_CONTROL,control register to manage pattern adapter on HWA18 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA18_PA2_PRODCOUNT,count values for HWA18 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA18_PROD3_CONTROL,Controlling producer socket3 for HWA18"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA18_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA18"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA18_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA18 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x940++0x07
line.long 0x00 "VPAC_HTS_HWA19_SCHEDULER_CONTROL,Scheduler Control Register"
bitfld.long 0x00 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "0,1"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA19"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> HWA19 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of HWA19 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of HWA19 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_HWA19_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x950++0x4F
line.long 0x00 "VPAC_HTS_HWA19_CONS0_CONTROL,Controlling consumer socket 0 for HWA19"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_HWA19_CONS1_CONTROL,Controlling consumer socket 1 for HWA19"
hexmask.long.word 0x04 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 1"
bitfld.long 0x04 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "0,1"
line.long 0x08 "VPAC_HTS_HWA19_PROD0_CONTROL,Controlling producer socket0 for HWA19"
hexmask.long.byte 0x08 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 0"
bitfld.long 0x08 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x0C "VPAC_HTS_HWA19_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for HWA19"
bitfld.long 0x0C 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x0C 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x0C 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x10 "VPAC_HTS_HWA19_PROD0_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod0"
hexmask.long.word 0x10 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x10 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x10 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x14 "VPAC_HTS_HWA19_PA0_CONTROL,control register to manage pattern adapter on HWA19 prod socket0"
hexmask.long.word 0x14 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x14 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x14 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x14 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x14 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x18 "VPAC_HTS_HWA19_PA0_PRODCOUNT,count values for HWA19 prod socket0"
hexmask.long.word 0x18 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x18 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "VPAC_HTS_HWA19_PROD1_CONTROL,Controlling producer socket1 for HWA19"
hexmask.long.byte 0x1C 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 1"
bitfld.long 0x1C 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x20 "VPAC_HTS_HWA19_PROD1_BUF_CONTROL,Controlling producer socket1 buffer for HWA19"
bitfld.long 0x20 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x20 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x20 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x24 "VPAC_HTS_HWA19_PROD1_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod1"
hexmask.long.word 0x24 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x24 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x24 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x28 "VPAC_HTS_HWA19_PA1_CONTROL,control register to manage pattern adapter on HWA19 prod socket1"
hexmask.long.word 0x28 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x28 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x28 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x28 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x28 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x2C "VPAC_HTS_HWA19_PA1_PRODCOUNT,count values for HWA19 prod socket1"
hexmask.long.word 0x2C 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x2C 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x30 "VPAC_HTS_HWA19_PROD2_CONTROL,Controlling producer socket2 for HWA19"
hexmask.long.byte 0x30 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 2"
bitfld.long 0x30 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x34 "VPAC_HTS_HWA19_PROD2_BUF_CONTROL,Controlling producer socket2 buffer for HWA19"
bitfld.long 0x34 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x34 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x34 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x38 "VPAC_HTS_HWA19_PROD2_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod2"
hexmask.long.word 0x38 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x38 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x38 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x3C "VPAC_HTS_HWA19_PA2_CONTROL,control register to manage pattern adapter on HWA19 prod socket2"
hexmask.long.word 0x3C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x3C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x3C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x3C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x3C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x40 "VPAC_HTS_HWA19_PA2_PRODCOUNT,count values for HWA19 prod socket2"
hexmask.long.word 0x40 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x40 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x44 "VPAC_HTS_HWA19_PROD3_CONTROL,Controlling producer socket3 for HWA19"
hexmask.long.byte 0x44 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 3"
bitfld.long 0x44 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x48 "VPAC_HTS_HWA19_PROD3_BUF_CONTROL,Controlling producer socket3 buffer for HWA19"
bitfld.long 0x48 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x48 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x48 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x4C "VPAC_HTS_HWA19_PROD3_COUNT,Defining count values for pre/post load for generating pend by HWA19 prod3"
hexmask.long.word 0x4C 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x4C 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x4C 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x9A8++0x07
line.long 0x00 "VPAC_HTS_DMA0_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA0"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA0 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA0 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA0 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA0_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x9B8++0x13
line.long 0x00 "VPAC_HTS_DMA0_PROD0_CONTROL,Controlling producer socket0 for DMA0"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA0 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA0_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA0"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA0_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA0 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA1_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA1"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA1 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA1 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA1 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA1_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x9D4++0x13
line.long 0x00 "VPAC_HTS_DMA1_PROD0_CONTROL,Controlling producer socket0 for DMA1"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA1 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA1_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA1"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA1_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA1 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA2_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA2"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA2 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA2 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA2 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA2_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x9F0++0x13
line.long 0x00 "VPAC_HTS_DMA2_PROD0_CONTROL,Controlling producer socket0 for DMA2"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA2 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA2_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA2"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA2_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA2 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA3_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA3"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA3 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA3 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA3 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA3_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xA0C++0x13
line.long 0x00 "VPAC_HTS_DMA3_PROD0_CONTROL,Controlling producer socket0 for DMA3"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA3 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA3_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA3"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA3_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA3 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA4_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA4"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA4 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA4 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA4 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA4_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xA28++0x0B
line.long 0x00 "VPAC_HTS_DMA4_PROD0_CONTROL,Controlling producer socket0 for DMA4"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA4 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA4_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA4"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA4_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA4 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xA88++0x07
line.long 0x00 "VPAC_HTS_DMA8_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA8"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA8 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA8 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA8 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA8_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xA98++0x1B
line.long 0x00 "VPAC_HTS_DMA8_PROD0_CONTROL,Controlling producer socket0 for DMA8"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA8 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA8_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA8"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA8_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA8 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA8_PA0_CONTROL,control register to manage pattern adapter on DMA8 prod socket0"
hexmask.long.word 0x0C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x0C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x0C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x0C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x0C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x10 "VPAC_HTS_DMA8_PA0_PRODCOUNT,count values for HWA8 prod socket0"
hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x10 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "VPAC_HTS_DMA9_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x14 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA9"
bitfld.long 0x14 12. "DEBUG_RDY,'0' -> DMA9 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x14 7.--10. "STATE,Current state of DMA9 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x14 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x14 1.--3. "PIPELINE_NUM,Pipeline Number of DMA9 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x18 "VPAC_HTS_DMA9_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x18 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x18 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xABC++0x1B
line.long 0x00 "VPAC_HTS_DMA9_PROD0_CONTROL,Controlling producer socket0 for DMA9"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA9 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA9_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA9"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA9_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA9 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA9_PA0_CONTROL,control register to manage pattern adapter on DMA9 prod socket0"
hexmask.long.word 0x0C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x0C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x0C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x0C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x0C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x10 "VPAC_HTS_DMA9_PA0_PRODCOUNT,count values for HWA9 prod socket0"
hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x10 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "VPAC_HTS_DMA10_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x14 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA10"
bitfld.long 0x14 12. "DEBUG_RDY,'0' -> DMA10 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x14 7.--10. "STATE,Current state of DMA10 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x14 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x14 1.--3. "PIPELINE_NUM,Pipeline Number of DMA10 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x18 "VPAC_HTS_DMA10_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x18 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x18 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xAE0++0x13
line.long 0x00 "VPAC_HTS_DMA10_PROD0_CONTROL,Controlling producer socket0 for DMA10"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA10 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA10_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA10"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA10_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA10 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA10_PA0_CONTROL,control register to manage pattern adapter on DMA10 prod socket0"
hexmask.long.word 0x0C 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N"
hexmask.long.word 0x0C 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N"
bitfld.long 0x0C 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter" "0,1"
bitfld.long 0x0C 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0,1"
newline
bitfld.long 0x0C 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0,1"
line.long 0x10 "VPAC_HTS_DMA10_PA0_PRODCOUNT,count values for HWA10 prod socket0"
hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count"
bitfld.long 0x10 0.--5. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xD40++0x07
line.long 0x00 "VPAC_HTS_DMA32_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA32"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA32 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA32 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA32 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA32_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xD50++0x0B
line.long 0x00 "VPAC_HTS_DMA32_PROD0_CONTROL,Controlling producer socket0 for DMA32"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA32 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA32_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA32"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA32_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA32 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xE20++0x07
line.long 0x00 "VPAC_HTS_DMA40_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA40"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA40 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA40 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA40 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA40_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xE30++0x0B
line.long 0x00 "VPAC_HTS_DMA40_PROD0_CONTROL,Controlling producer socket0 for DMA40"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA40 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA40_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA40"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA40_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA40 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xF00++0x07
line.long 0x00 "VPAC_HTS_DMA48_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA48"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA48 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA48 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA48 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA48_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xF10++0x0B
line.long 0x00 "VPAC_HTS_DMA48_PROD0_CONTROL,Controlling producer socket0 for DMA48"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA48 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA48_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA48"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA48_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA48 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0xFE0++0x07
line.long 0x00 "VPAC_HTS_DMA56_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA56"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA56 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA56 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA56 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA56_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0xFF0++0x13
line.long 0x00 "VPAC_HTS_DMA56_PROD0_CONTROL,Controlling producer socket0 for DMA56"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA56 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA56_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA56"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA56_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA56 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA57_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA57"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA57 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA57 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA57 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA57_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x100C++0x13
line.long 0x00 "VPAC_HTS_DMA57_PROD0_CONTROL,Controlling producer socket0 for DMA57"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA57 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA57_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA57"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA57_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA57 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA58_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA58"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA58 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA58 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA58 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA58_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1028++0x13
line.long 0x00 "VPAC_HTS_DMA58_PROD0_CONTROL,Controlling producer socket0 for DMA58"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA58 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA58_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA58"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA58_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA58 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA59_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA59"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA59 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA59 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA59 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA59_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1044++0x0B
line.long 0x00 "VPAC_HTS_DMA59_PROD0_CONTROL,Controlling producer socket0 for DMA59"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA59 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA59_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA59"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA59_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA59 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x10C0++0x07
line.long 0x00 "VPAC_HTS_DMA64_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA64"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA64 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA64 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA64 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x04 "VPAC_HTS_DMA64_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x04 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x04 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x10D0++0x13
line.long 0x00 "VPAC_HTS_DMA64_PROD0_CONTROL,Controlling producer socket0 for DMA64"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA64 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA64_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA64"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA64_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA64 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA65_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA65"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA65 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA65 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA65 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA65_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x10EC++0x13
line.long 0x00 "VPAC_HTS_DMA65_PROD0_CONTROL,Controlling producer socket0 for DMA65"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA65 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA65_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA65"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA65_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA65 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA66_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA66"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA66 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA66 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA66 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA66_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1108++0x13
line.long 0x00 "VPAC_HTS_DMA66_PROD0_CONTROL,Controlling producer socket0 for DMA66"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA66 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA66_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA66"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA66_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA66 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
line.long 0x0C "VPAC_HTS_DMA67_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x0C 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA67"
bitfld.long 0x0C 12. "DEBUG_RDY,'0' -> DMA67 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x0C 7.--10. "STATE,Current state of DMA67 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x0C 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x0C 1.--3. "PIPELINE_NUM,Pipeline Number of DMA67 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "SCH_EN,scheduler enable" "0,1"
line.long 0x10 "VPAC_HTS_DMA67_HOP,Scheduler HOP Control Register"
hexmask.long.word 0x10 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe"
bitfld.long 0x10 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0,1"
group.long 0x1124++0x0B
line.long 0x00 "VPAC_HTS_DMA67_PROD0_CONTROL,Controlling producer socket0 for DMA67"
hexmask.long.byte 0x00 1.--8. 1. "CONS_SELECT,consumer select for DMA67 prod socket 0"
bitfld.long 0x00 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA67_PROD0_BUF_CONTROL,Controlling producer socket0 buffer for DMA67"
bitfld.long 0x04 21.--26. "COUNT_DEC,Count decrement value for prod count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x04 13.--20. 1. "THRESHOLD,Count threshold to generate pend for consumer"
hexmask.long.word 0x04 0.--12. 1. "DEPTH,Maximum number of producer buffer count"
line.long 0x08 "VPAC_HTS_DMA67_PROD0_COUNT,Defining count values for pre/post load for generating pend by DMA67 prod0"
hexmask.long.word 0x08 16.--28. 1. "COUNT,current count value"
hexmask.long.byte 0x08 8.--15. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached"
hexmask.long.byte 0x08 0.--7. 1. "COUNT_PRELOAD,count preload after scheduler start/init"
group.long 0x21B4++0x03
line.long 0x00 "VPAC_HTS_DMA240_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x00 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA240"
bitfld.long 0x00 12. "DEBUG_RDY,'0' -> DMA240 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x00 7.--10. "STATE,Current state of DMA240 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x00 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x00 1.--3. "PIPELINE_NUM,Pipeline Number of DMA240 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x21C4++0x07
line.long 0x00 "VPAC_HTS_DMA240_CONS0_CONTROL,Controlling consumer socket 0 for DMA240"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA240 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA241_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA241"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA241 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA241 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA241 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x21D8++0x07
line.long 0x00 "VPAC_HTS_DMA241_CONS0_CONTROL,Controlling consumer socket 0 for DMA241"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA241 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA242_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA242"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA242 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA242 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA242 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x21EC++0x07
line.long 0x00 "VPAC_HTS_DMA242_CONS0_CONTROL,Controlling consumer socket 0 for DMA242"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA242 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA243_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA243"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA243 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA243 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA243 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2200++0x07
line.long 0x00 "VPAC_HTS_DMA243_CONS0_CONTROL,Controlling consumer socket 0 for DMA243"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA243 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA244_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA244"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA244 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA244 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA244 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2214++0x07
line.long 0x00 "VPAC_HTS_DMA244_CONS0_CONTROL,Controlling consumer socket 0 for DMA244"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA244 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA245_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA245"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA245 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA245 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA245 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2228++0x07
line.long 0x00 "VPAC_HTS_DMA245_CONS0_CONTROL,Controlling consumer socket 0 for DMA245"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA245 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA256_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA256"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA256 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA256 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA256 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x223C++0x07
line.long 0x00 "VPAC_HTS_DMA256_CONS0_CONTROL,Controlling consumer socket 0 for DMA256"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA256 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA257_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA257"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA257 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA257 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA257 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2250++0x07
line.long 0x00 "VPAC_HTS_DMA257_CONS0_CONTROL,Controlling consumer socket 0 for DMA257"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA257 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA258_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA258"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA258 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA258 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA258 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2264++0x07
line.long 0x00 "VPAC_HTS_DMA258_CONS0_CONTROL,Controlling consumer socket 0 for DMA258"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA258 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA259_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA259"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA259 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA259 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA259 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2278++0x07
line.long 0x00 "VPAC_HTS_DMA259_CONS0_CONTROL,Controlling consumer socket 0 for DMA259"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA259 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA260_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA260"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA260 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA260 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA260 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x228C++0x07
line.long 0x00 "VPAC_HTS_DMA260_CONS0_CONTROL,Controlling consumer socket 0 for DMA260"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA260 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA261_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA261"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA261 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA261 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA261 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x22A0++0x07
line.long 0x00 "VPAC_HTS_DMA261_CONS0_CONTROL,Controlling consumer socket 0 for DMA261"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA261 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA272_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA272"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA272 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA272 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA272 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x22B4++0x07
line.long 0x00 "VPAC_HTS_DMA272_CONS0_CONTROL,Controlling consumer socket 0 for DMA272"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA272 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA273_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA273"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA273 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA273 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA273 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x22C8++0x07
line.long 0x00 "VPAC_HTS_DMA273_CONS0_CONTROL,Controlling consumer socket 0 for DMA273"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA273 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA274_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA274"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA274 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA274 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA274 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x22DC++0x07
line.long 0x00 "VPAC_HTS_DMA274_CONS0_CONTROL,Controlling consumer socket 0 for DMA274"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA274 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA275_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA275"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA275 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA275 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA275 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x22F0++0x07
line.long 0x00 "VPAC_HTS_DMA275_CONS0_CONTROL,Controlling consumer socket 0 for DMA275"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA275 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA288_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA288"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA288 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA288 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA288 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2304++0x07
line.long 0x00 "VPAC_HTS_DMA288_CONS0_CONTROL,Controlling consumer socket 0 for DMA288"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA288 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA289_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA289"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA289 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA289 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA289 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2318++0x07
line.long 0x00 "VPAC_HTS_DMA289_CONS0_CONTROL,Controlling consumer socket 0 for DMA289"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA289 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA290_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA290"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA290 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA290 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA290 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x232C++0x07
line.long 0x00 "VPAC_HTS_DMA290_CONS0_CONTROL,Controlling consumer socket 0 for DMA290"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA290 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA291_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA291"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA291 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA291 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA291 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2340++0x07
line.long 0x00 "VPAC_HTS_DMA291_CONS0_CONTROL,Controlling consumer socket 0 for DMA291"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA291 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA304_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA304"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA304 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA304 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA304 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2354++0x07
line.long 0x00 "VPAC_HTS_DMA304_CONS0_CONTROL,Controlling consumer socket 0 for DMA304"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA304 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA305_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA305"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA305 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA305 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA305 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2368++0x07
line.long 0x00 "VPAC_HTS_DMA305_CONS0_CONTROL,Controlling consumer socket 0 for DMA305"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA305 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA306_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA306"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA306 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA306 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA306 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x237C++0x07
line.long 0x00 "VPAC_HTS_DMA306_CONS0_CONTROL,Controlling consumer socket 0 for DMA306"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA306 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA307_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA307"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA307 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA307 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA307 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2390++0x07
line.long 0x00 "VPAC_HTS_DMA307_CONS0_CONTROL,Controlling consumer socket 0 for DMA307"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA307 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA308_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA308"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA308 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA308 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA308 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x23A4++0x07
line.long 0x00 "VPAC_HTS_DMA308_CONS0_CONTROL,Controlling consumer socket 0 for DMA308"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA308 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA309_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA309"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA309 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA309 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA309 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x23B8++0x07
line.long 0x00 "VPAC_HTS_DMA309_CONS0_CONTROL,Controlling consumer socket 0 for DMA309"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA309 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA310_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA310"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA310 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA310 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA310 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x23CC++0x07
line.long 0x00 "VPAC_HTS_DMA310_CONS0_CONTROL,Controlling consumer socket 0 for DMA310"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA310 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA311_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA311"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA311 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA311 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA311 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x23E0++0x07
line.long 0x00 "VPAC_HTS_DMA311_CONS0_CONTROL,Controlling consumer socket 0 for DMA311"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA311 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA312_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA312"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA312 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA312 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA312 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x23F4++0x07
line.long 0x00 "VPAC_HTS_DMA312_CONS0_CONTROL,Controlling consumer socket 0 for DMA312"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA312 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA313_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA313"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA313 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA313 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA313 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2408++0x07
line.long 0x00 "VPAC_HTS_DMA313_CONS0_CONTROL,Controlling consumer socket 0 for DMA313"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA313 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA336_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA336"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA336 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA336 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA336 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x241C++0x07
line.long 0x00 "VPAC_HTS_DMA336_CONS0_CONTROL,Controlling consumer socket 0 for DMA336"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA336 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA352_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA352"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA352 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA352 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA352 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2430++0x07
line.long 0x00 "VPAC_HTS_DMA352_CONS0_CONTROL,Controlling consumer socket 0 for DMA352"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA352 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA353_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA353"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA353 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA353 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA353 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2444++0x07
line.long 0x00 "VPAC_HTS_DMA353_CONS0_CONTROL,Controlling consumer socket 0 for DMA353"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA353 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA354_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA354"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA354 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA354 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA354 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2458++0x07
line.long 0x00 "VPAC_HTS_DMA354_CONS0_CONTROL,Controlling consumer socket 0 for DMA354"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA354 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA355_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA355"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA355 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA355 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA355 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x246C++0x07
line.long 0x00 "VPAC_HTS_DMA355_CONS0_CONTROL,Controlling consumer socket 0 for DMA355"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA355 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA368_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA368"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA368 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA368 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA368 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2480++0x07
line.long 0x00 "VPAC_HTS_DMA368_CONS0_CONTROL,Controlling consumer socket 0 for DMA368"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA368 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA369_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA369"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA369 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA369 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA369 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x2494++0x07
line.long 0x00 "VPAC_HTS_DMA369_CONS0_CONTROL,Controlling consumer socket 0 for DMA369"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA369 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA370_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA370"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA370 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA370 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
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bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA370 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x24A8++0x07
line.long 0x00 "VPAC_HTS_DMA370_CONS0_CONTROL,Controlling consumer socket 0 for DMA370"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA370 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
line.long 0x04 "VPAC_HTS_DMA371_SCHEDULER_CONTROL,Scheduler Control Register"
hexmask.long.byte 0x04 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA371"
bitfld.long 0x04 12. "DEBUG_RDY,'0' -> DMA371 Scheduler resources must not be read during halted state" "0,1"
rbitfld.long 0x04 7.--10. "STATE,Current state of DMA371 Scheduler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0,1"
newline
bitfld.long 0x04 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "0,1"
bitfld.long 0x04 1.--3. "PIPELINE_NUM,Pipeline Number of DMA371 Scheduler" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0. "SCH_EN,scheduler enable" "0,1"
group.long 0x24BC++0x03
line.long 0x00 "VPAC_HTS_DMA371_CONS0_CONTROL,Controlling consumer socket 0 for DMA371"
hexmask.long.word 0x00 1.--9. 1. "PROD_SELECT,producer select for DMA371 cons socket 0"
bitfld.long 0x00 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "0,1"
group.long 0x2650++0x0B
line.long 0x00 "VPAC_HTS_PIPE_DBG_CNTL,Pipeline Debug Control register is used by debug software to control pipeline debug behavior"
rbitfld.long 0x00 17.--19. "DEBUG_STATE,Current state of Debug activity" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "ABORT_DEBUG,'1' -> Abort Debug activity on debug enabled pipelines '0' no impact" "0,1"
bitfld.long 0x00 6. "PIPE_DBG_DIS_6,'1' -> Pipeline6 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1"
bitfld.long 0x00 5. "PIPE_DBG_DIS_5,'1' -> Pipeline5 doesn't respond to debug events '0' Pipeline5 respond to debug events" "0,1"
newline
bitfld.long 0x00 4. "PIPE_DBG_DIS_4,'1' -> Pipeline4 doesn't respond to debug events '0' Pipeline4 respond to debug events" "0,1"
bitfld.long 0x00 3. "PIPE_DBG_DIS_3,'1' -> Pipeline3 doesn't respond to debug events '0' Pipeline3 respond to debug events" "0,1"
bitfld.long 0x00 2. "PIPE_DBG_DIS_2,'1' -> Pipeline2 doesn't respond to debug events '0' Pipeline2 respond to debug events" "0,1"
bitfld.long 0x00 1. "PIPE_DBG_DIS_1,'1' -> Pipeline1 doesn't respond to debug events '0' Pipeline1 respond to debug events" "0,1"
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bitfld.long 0x00 0. "PIPE_DBG_DIS_0,'1' -> Pipeline0 doesn't respond to debug events '0' Pipeline0 respond to debug events" "0,1"
line.long 0x04 "VPAC_HTS_DBG_CAP,Debug Capability register is used by debug software to determine which optional debug modules are present and how many instances of each module exist"
bitfld.long 0x04 30. "DBG_INT_STEP_SUP,Indicates that debug execution control can determine if single step blocks or allows interrupts" "0,1"
bitfld.long 0x04 29. "DBG_WP_DATA_SUP,Indicates if the WP resources has corresponding data qualification" "0,1"
bitfld.long 0x04 28. "DBG_OWN_SUP,Indicates if the HWA supports an module ownership" "0,1"
bitfld.long 0x04 27. "DBG_INDIRECT_SUP,Indicates if the HWA supports an indirect memory access port" "0,1"
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bitfld.long 0x04 26. "DBG_SWBP_SUP,Whether HWA Core supports SWBP or not" "0,1"
bitfld.long 0x04 25. "DBQ_RESET_SUP,Whether HWA Core reset is supported or not which does not affect debug logic" "0,1"
bitfld.long 0x04 24. "SYS_EXE_REQ,Whether HWA Core Execution status and control is supported" "0,1"
bitfld.long 0x04 23. "TRIG_OUTPUT,b" "0,1"
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bitfld.long 0x04 22. "TRIG_INPUT,b" "0,1"
bitfld.long 0x04 20.--21. "TRIG_CHNS,Number of Trigger Channels Supported" "0,1,2,3"
bitfld.long 0x04 16.--19. "NUM_CNTRS,The number of counter modules that exist" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "NUM_WPS,The number of watchpoint modules that exist" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "NUM_BPS,The number of breakpoint modules that exist" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "REV_MAJ,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "REV_MIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "VPAC_HTS_DBG_CNTL,Debug Control register is used by debug software to control all of the basic debug functions"
bitfld.long 0x08 26. "DBG_RESET_OCC,Sticky status bit to reflect reset has been generated" "0,1"
bitfld.long 0x08 16.--19. "DBG_EMU0_CNTL,EMU0 output control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x08 12. "DBG_HALT_EMU0,Execution halted due to trigger in on EMU0 input Set to '1' when halt due to EMU0 input completes Set to '0' when execution resumes" "0,1"
rbitfld.long 0x08 11. "DBG_HALT_USER,Execution halted due to register update of DBG_HALT Set to '1' when halt due to DBG_HALT update completes Set to '0' when execution resumes" "0,1"
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rbitfld.long 0x08 10. "DBG_HALT_STEP,Execution halted due to single step completion Set to '1' when the single step completes Set to '0' when execution resumes" "0,1"
rbitfld.long 0x08 7. "DBG_EXE_STAT,The execution status of the module Set to '1' when halted due to debug event Set to '0' when execution resumes" "0,1"
bitfld.long 0x08 5. "DBG_EMU0_EN,EMU0 input trigger enable Writing '1' enables halting on the falling edge of the EMU0 input Writing '0' disables halts via EMU0 input" "0,1"
bitfld.long 0x08 2. "DBG_SINGLE_STEP_EN,Single Step Execution enable" "0,1"
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bitfld.long 0x08 1. "DBG_RESTART,Debug Restart Status bit.This bit is normally set when the DBG_HALT bit transitions from '1' to '0' when the natural execution state is entered.It is a sticky bit" "0,1"
bitfld.long 0x08 0. "DBG_HALT,Global debug run control" "0,1"
tree.end
tree.end
tree "VPAC_LDC"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP"
base ad:0xF020000
rgroup.long 0x00++0x63
line.long 0x00 "VPAC_LDC_REVISION_REG,LDC PID"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VPAC_LDC_PRIVATE_MEMSIZE,Memory size mentioned is for both ping and pong combined"
hexmask.long.byte 0x04 16.--23. 1. "MESH,Mesh Private pixel memory size in KBytes"
hexmask.long.byte 0x04 8.--15. 1. "CHROMA,Chroma Private pixel memory size in KBytes"
hexmask.long.byte 0x04 0.--7. 1. "LUMA,Luma Private pixel memory size in KBytes"
line.long 0x08 "VPAC_LDC_CTRL,Control Register to Enable/Disable and select modes of operation"
bitfld.long 0x08 13. "REGMODE_EN,Enables for Frame division into multiple regions" "0,1"
bitfld.long 0x08 11. "OP_DATAMODE,Output Pixel Data Mode" "0,1"
bitfld.long 0x08 10. "IP_HTS_ROWSYNC,Enables control of Input Fetch with HTS at Block Row level" "0,1"
bitfld.long 0x08 9. "IP_CIRCEN,Enables circular addressing mode on input pixel fetch" "0,1"
bitfld.long 0x08 8. "ALIGN_12BIT,Alignment of" "0,1"
bitfld.long 0x08 7. "PWARPEN,Perspective warp transform Enable" "0,1"
newline
bitfld.long 0x08 5.--6. "IP_DFMT,Input Pixel Data Format" "0,1,2,3"
bitfld.long 0x08 3.--4. "IP_DATAMODE,Input Pixel Data Mode" "0,1,2,3"
rbitfld.long 0x08 2. "BUSY,Idle/Busy Status " "0,1"
bitfld.long 0x08 1. "LDMAPEN,Distortion Back Mapping Enable" "0,1"
bitfld.long 0x08 0. "LDC_EN,Write 1 to Start LDC function" "0,1"
line.long 0x0C "VPAC_LDC_CFG,LDC Configuration register"
bitfld.long 0x0C 6. "YINT_TYP,Interpolation type for Y data" "0,1"
bitfld.long 0x0C 1. "CLKCG_OVERIDE,Override power saving clock gating inserted by design" "0,1"
line.long 0x10 "VPAC_LDC_MESHTABLE_CFG,Defines the down-sampling factors used for the mesh offset tables"
bitfld.long 0x10 0.--2. "M,Mesh table down-sampling factor (by 2" "0,1,2,3,4,5,6,7"
line.long 0x14 "VPAC_LDC_MESH_FRSZ,Mesh data mapping is available for this Frame size"
hexmask.long.word 0x14 16.--29. 1. "H,Mesh Frame height in Lines"
hexmask.long.word 0x14 0.--13. 1. "W,Mesh Frame Width"
line.long 0x18 "VPAC_LDC_COMPUTE_FRSZ,H corresponds to the total number of lines to process"
hexmask.long.word 0x18 16.--29. 1. "H,Output Frame height in Lines"
hexmask.long.word 0x18 0.--13. 1. "W,Output Frame Width"
line.long 0x1C "VPAC_LDC_INITXY,LDC Initial Output Co-ordinate to process"
hexmask.long.word 0x1C 16.--28. 1. "INITY,Output starting Y-coordinate"
hexmask.long.word 0x1C 0.--12. 1. "INITX,Output starting X-coordinate"
line.long 0x20 "VPAC_LDC_INPUT_FRSZ,Defines the total input frame size"
hexmask.long.word 0x20 16.--29. 1. "H,Input Frame height in Lines"
hexmask.long.word 0x20 0.--13. 1. "W,Input Frame Width in Pixels"
line.long 0x24 "VPAC_LDC_OUT_BLKSZ,LDC Output Block parameter registers"
bitfld.long 0x24 16.--19. "PIXPAD,Pixel pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 8.--15. 1. "OBH,Output block height must be >0 and even"
hexmask.long.byte 0x24 0.--7. 1. "OBW,Output block width must be >0 and multiple of 8"
line.long 0x28 "VPAC_LDC_AFF_AB,LDC Affine Transwarp A/B"
hexmask.long.word 0x28 16.--31. 1. "B,Affine transwarp B (S16Q12)"
hexmask.long.word 0x28 0.--15. 1. "A,Affine transwarp A (S16Q12)"
line.long 0x2C "VPAC_LDC_AFF_CD,LDC Affine Transwarp C/D"
hexmask.long.word 0x2C 16.--31. 1. "D,Affine transwarp D (S16Q12)"
hexmask.long.word 0x2C 0.--15. 1. "C,Affine transwarp C (S16Q3)"
line.long 0x30 "VPAC_LDC_AFF_EF,LDC Affine Transwarp E/F"
hexmask.long.word 0x30 16.--31. 1. "F,Affine transwarp F (S16Q3)"
hexmask.long.word 0x30 0.--15. 1. "E,Affine transwarp E (S16Q12)"
line.long 0x34 "VPAC_LDC_PWARP_GH,LDC Perspective Transformation Parameters. G and H"
hexmask.long.word 0x34 16.--31. 1. "H,Perspective Transformation H (S16Q23)"
hexmask.long.word 0x34 0.--15. 1. "G,Perspective Transformation H (S16Q23)"
line.long 0x38 "VPAC_LDC_MESH_BASE_H,Higher 16-bit of Mesh Table Base Address"
hexmask.long.word 0x38 0.--15. 1. "ADDR,Higher"
line.long 0x3C "VPAC_LDC_MESH_BASE_l,Lower 32-bit of Mesh Table Base Address"
line.long 0x40 "VPAC_LDC_MESH_OFST,Defines the stride between rows for the Mesh table in bytes"
hexmask.long.word 0x40 0.--15. 1. "OFST,LDC Mesh table line offset must be"
line.long 0x44 "VPAC_LDC_RD_BASE_H,Higher 16-bit of Input Frame Base Address"
hexmask.long.word 0x44 0.--15. 1. "ADDR,Higher"
line.long 0x48 "VPAC_LDC_RD_BASE_l,Lower 32-bit of Input Frame Base Address"
line.long 0x4C "VPAC_LDC_RD_420C_BASE_H,Higher 16-bit of Input Frame 420C Base Address"
hexmask.long.word 0x4C 0.--15. 1. "ADDR,Higher"
line.long 0x50 "VPAC_LDC_RD_420C_BASE_l,Lower 32-bit of Input Frame Chroma Base Address in YUV420"
line.long 0x54 "VPAC_LDC_RD_OFST,Defines the stride between rows for the Input Frame in bytes"
hexmask.long.word 0x54 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used"
hexmask.long.word 0x54 0.--15. 1. "OFST,Read frame line offset must be"
line.long 0x58 "VPAC_LDC_VBUSMR_CFG,Control VBUSM Read Interface"
hexmask.long.word 0x58 16.--27. 1. "BW_CTRL,Limits the mean bandwidth (computed over one block) that the LDC module can request for read from system memory"
bitfld.long 0x58 3.--7. "TAG_CNT,Limits the maximum number of outstanding LDC requests to TAG_CNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 1.--2. "MAX_BURSTLEN,Limits the maximum burst length that could be used by LDC" "0,1,2,3"
line.long 0x5C "VPAC_LDC_COREOUT_CHANCFG,LDC Core to LSE output channel enable control"
bitfld.long 0x5C 3. "CH3_EN,Enable for LDC Core to LSE Channel_3 connection used for Chroma Dual output" "0,1"
bitfld.long 0x5C 2. "CH2_EN,Enable for LDC Core to LSE Channel_2 connection used for Luma Dual output" "0,1"
rbitfld.long 0x5C 1. "RSRV_CH1,Primary Chroma channel (LSE Channel_1) enable extracted from output data mode" "0,1"
rbitfld.long 0x5C 0. "RSRV_CH0,Primary Luuma channel (LSE Channel_0) enable extracted from output data mode" "0,1"
line.long 0x60 "VPAC_LDC_DUALOUT_CFG,Configuration for Dual Luma and Chroma channels and LUT"
bitfld.long 0x60 21.--24. "COUT_BITDPTH,Chroma Output Data Bit depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x60 17.--20. "CIN_BITDPTH,Chroma Input Data Bit depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x60 16. "CLUT_EN,Chroma LUT mapping enable" "0,1"
bitfld.long 0x60 5.--8. "YOUT_BITDPTH,Luma Output Data Bit depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x60 1.--4. "YIN_BITDPTH,Luma Input Data Bit depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x60 0. "YLUT_EN,Luma LUT mapping enable" "0,1"
group.long 0x80++0x0F
line.long 0x00 "VPAC_LDC_REGN_W12_SZ,Horizontal slice width for Region division"
hexmask.long.word 0x00 16.--29. 1. "W2,Width of second horizontal slice"
hexmask.long.word 0x00 0.--13. 1. "W1,Width of first horizontal slice"
line.long 0x04 "VPAC_LDC_REGN_W3_SZ,Horizontal slice width for Region division"
hexmask.long.word 0x04 0.--13. 1. "W3,Width of third horizontal slice"
line.long 0x08 "VPAC_LDC_REGN_H12_SZ,vertical slice height for Region division"
hexmask.long.word 0x08 16.--29. 1. "H2,Height of second vertical slice"
hexmask.long.word 0x08 0.--13. 1. "H1,Height of first vertical slice"
line.long 0x0C "VPAC_LDC_REGN_H3_SZ,vertical slice height for Region division"
hexmask.long.word 0x0C 0.--13. 1. "H3,Height of third vertical slice"
group.long 0xA0++0x07
line.long 0x00 "VPAC_LDC_CTRL_j,Region Control Register Offset = 000200A0h + (j * 8h); where j = 0h to 8h"
bitfld.long 0x00 0. "ENABLE,Enable for processing of this region" "0,1"
line.long 0x04 "VPAC_LDC_OUT_BLKSZ_j,Block size and Pixel Pad config Offset = 000200A4h + (j * 8h); where j = 0h to 8h"
bitfld.long 0x04 16.--19. "PIXPAD,Pixel pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x04 8.--15. 1. "OBH,Output block height must be >0 and even"
hexmask.long.byte 0x04 0.--7. 1. "OBW,Output block width must be >0 and multiple of 8"
group.long 0x200++0x1F
line.long 0x00 "VPAC_LDC_ERR_STATUS,Control VBUSM Read Interface"
bitfld.long 0x00 8.--10. "VBUSMR_ERR,VBUSM Read I/F Last Error Status" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5. "INT_SZOVF,Internal operation has overflown the HW supported block or frame sizes" "0,1"
bitfld.long 0x00 4. "M_IBLK_MEMOVF,Mesh block storage requirement is more than internal memory available" "0,1"
bitfld.long 0x00 3. "P_IBLK_MEMOVF,Input pixel block storage requirement is more than internal memory available" "0,1"
bitfld.long 0x00 2. "IFRAME_OUTB,Either Mesh data or Input pixel data required is going out of valid frame available" "0,1"
bitfld.long 0x00 1. "M_IBLK_OUTB,Mesh Input Block out of Bound" "0,1"
newline
bitfld.long 0x00 0. "P_IBLK_OUTB,Pixel Input Block out of Bound" "0,1"
line.long 0x04 "VPAC_LDC_DEBUG_CTRL,Control the memory access selection"
bitfld.long 0x04 0. "CFG_MEMACC_SEL,VBUSP Configuration access control" "0,1"
line.long 0x08 "VPAC_LDC_DEBUG_STATUS,LDC Debug Status Register"
bitfld.long 0x08 24. "PROC_STATUS,Block Processing status" "0,1"
bitfld.long 0x08 16.--18. "FETCH_RESPSTATE,VBUSM Fetch Response state machine 3'd" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--12. "FETCH_REQSTATE,VBUSM Fetch Request state machine 5'b00_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--3. "CTRL_STATE,Main Control State machine 4'd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "VPAC_LDC_FR_PDFTCH,Pixel bytes fetched by VBUSM Read Interface"
line.long 0x10 "VPAC_LDC_FR_MDFTCH,Mesh bytes fetched by VBUSM Read Interface"
line.long 0x14 "VPAC_LDC_PIXMEMOVF_BLK,Starting co-ordinates of first output block for which input pixel buffer overflowed"
hexmask.long.word 0x14 16.--28. 1. "Y,Start Y Co-ordinate"
hexmask.long.word 0x14 0.--12. 1. "X,Start X Co-ordinate"
line.long 0x18 "VPAC_LDC_MESHMEMOVF_BLK,Starting co-ordinates of first output block for which input mesh buffer overflowed"
hexmask.long.word 0x18 16.--28. 1. "Y,Start Y Co-ordinate"
hexmask.long.word 0x18 0.--12. 1. "X,Start X Co-ordinate"
line.long 0x1C "VPAC_LDC_OUTOFBOUND_BLK,Starting co-ordinates of first output block for which PIX_PAD is not enough"
hexmask.long.word 0x1C 16.--28. 1. "Y,Start Y Co-ordinate"
hexmask.long.word 0x1C 0.--12. 1. "X,Start X Co-ordinate"
tree.end
tree.end
tree "VPAC_LDC_LSE"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP"
base ad:0xF020400
rgroup.long 0x00++0x0F
line.long 0x00 "VPAC_LDC_LSE_STATUS_PARAM,The register returns the LSE compile configuration parameters"
bitfld.long 0x00 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3"
bitfld.long 0x00 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1"
bitfld.long 0x00 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1"
bitfld.long 0x00 23.--27. "CORE_OUT_DW,Core Output Channel Data Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1"
newline
bitfld.long 0x00 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1"
bitfld.long 0x00 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1"
bitfld.long 0x00 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--16. "CORE_DW,Core Input Data Bus Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3"
newline
bitfld.long 0x00 6.--9. "SL2_OUT_CH,Number of SL2 Output Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "VPORT_THR,Number of VPORT input enabled" "0,1"
bitfld.long 0x00 0.--1. "NTHR,Number of threads supported" "0,1,2,3"
line.long 0x04 "VPAC_LDC_LSE_STATUS_ERROR,The register returns the LSE error status"
hexmask.long.byte 0x04 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status"
line.long 0x08 "VPAC_LDC_LSE_STATUS_IDLE_MODE,The register returns IDLE status of LSE VBUSM port and in/output"
bitfld.long 0x08 12.--15. "LSE_OUT_CHAN,Output Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1"
line.long 0x0C "VPAC_LDC_LSE_CFG_LSE,The register configures the LSE general hardware modes"
bitfld.long 0x0C 8. "PSA_EN,Test mode Output Channel Signature Generation Enable" "0,1"
bitfld.long 0x0C 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select" "0,1"
group.long 0x50++0x0F
line.long 0x00 "VPAC_LDC_LSE_BUF_CFG_j,The DST_BUF_CFG register configures the output buffer channel"
rbitfld.long 0x00 31. "CH_DISABLED,Channel Disable Status (read-only)" "0,1"
bitfld.long 0x00 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection" "0,1"
bitfld.long 0x00 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable" "0,1"
bitfld.long 0x00 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment" "0,1"
bitfld.long 0x00 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "PIX_FMT_PW,Output Pixel Width Sel" "0,1,2,3"
line.long 0x04 "VPAC_LDC_LSE_BUF_ATTR0_j,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "VPAC_LDC_LSE_BUF_ATTR1_j,The DST_BUF_ATTR1 register configures the 2D Block attributes of the output SL2 buffer"
hexmask.long.word 0x08 16.--25. 1. "CBUF_BPR_CHAN,Circular Buffer - 2D blocks per row defined by cbuf_stride (selected when bpr_sel_mode=0)"
bitfld.long 0x08 2. "TDONE_GEN_MODE,HTS Tdone Generation Mode for 2D transfer" "0,1"
bitfld.long 0x08 1. "BPR_SEL_MODE,CBUF BPR Selection mode" "0,1"
bitfld.long 0x08 0. "CBUF_VWRAP_EN,CBUF Vertical Wrap Enable" "0,1"
line.long 0x0C "VPAC_LDC_LSE_BUF_BA_j,The DST_BUF_BA register configures the base address of the output SL2 circular buffer"
bitfld.long 0x0C 31. "ENABLE,Output Channel Enable" "0,1"
hexmask.long.tbyte 0x0C 6.--23. 1. "ADDR,Base Address"
rbitfld.long 0x0C 0.--5. "ADDR_6_LSB,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "VPAC_LDC_LSE_ROW_j,The COMMON_CFG_ROW registers configure the common CBUF_BPR values for regions of all output channels"
hexmask.long.word 0x00 20.--29. 1. "BPR0,Region [a 0] CBUF_BPR value"
hexmask.long.word 0x00 10.--19. 1. "BPR1,Region [a 1] CBUF_BPR value"
hexmask.long.word 0x00 0.--9. 1. "BPR2,Region [a 2] CBUF_BPR value"
rgroup.long 0x140++0x03
line.long 0x00 "VPAC_LDC_LSE_PSA_SIGNATURE_y,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]"
rgroup.long 0x1E0++0x03
line.long 0x00 "VPAC_LDC_LSE_DBG_y,The DBG register returns the current status of internal FSM - TI internal use only"
tree.end
tree.end
tree "VPAC_LDC_MEMCFG_LOOP_CBCR"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM"
base ad:0xF030000
group.long 0x00++0x03
line.long 0x00 "VPAC_LDC_LOOP_CBCR_RAM_y,cbcr memory Offset = 00030000h + (y * 4h); where y = 0h to 13FFh"
hexmask.long.tbyte 0x00 0.--23. 1. "MEM,Memory location"
tree.end
tree.end
tree "VPAC_LDC_MEMCFG_LOOP_MESH"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM"
base ad:0xF022000
group.long 0x00++0x03
line.long 0x00 "VPAC_LDC_LOOP_MESH_RAM_y,mesh memory Offset = 00022000h + (y * 4h); where y = 0h to 4FFh"
tree.end
tree.end
tree "VPAC_LDC_MEMCFG_LOOP_Y"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM"
base ad:0xF028000
group.long 0x00++0x03
line.long 0x00 "VPAC_LDC_LOOP_Y_RAM_y,y memory Offset = 00028000h + (y * 4h); where y = 0h to 1BFFh"
hexmask.long.tbyte 0x00 0.--23. 1. "MEM,Memory location"
tree.end
tree.end
tree "VPAC_LDC_PIXWRINTF_DUALC_LUT"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT"
base ad:0xF021000
group.long 0x00++0x03
line.long 0x00 "VPAC_LDC_DUALC_LUT_y,dualc width conversion LUT Offset = 00021000h + (y * 4h); where y = 0h to 100h"
hexmask.long.word 0x00 16.--27. 1. "LUT_1,Bank-1"
hexmask.long.word 0x00 0.--11. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_LDC_PIXWRINTF_DUALY_LUT"
tree "VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT"
base ad:0xF020800
group.long 0x00++0x03
line.long 0x00 "VPAC_LDC_DUALY_LUT_y,dualy width conversion LUT Offset = 00020800h + (y * 4h); where y = 0h to 100h"
hexmask.long.word 0x00 16.--27. 1. "LUT_1,Bank-1"
hexmask.long.word 0x00 0.--11. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_MSC_CORE"
tree "VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP"
base ad:0xF1C0000
rgroup.long 0x00++0x07
line.long 0x00 "VPAC_MSC_CORE_REVISION,The Register contains the major and minor revisions for the VPAC MSC HWA module"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VPAC_MSC_CORE_CONTROL,The Register allows the CPU to various aspects of the module"
bitfld.long 0x04 0. "MSC_ENABLE,MSC Core Enable: Enables the MSC HWA" "0,1"
group.long 0x10++0x13
line.long 0x00 "VPAC_MSC_CORE_CFG_j,The FILT[a]_CFG register configures the modes of FILTER channel [a]"
bitfld.long 0x00 22. "SIGNED_DATA,Integer type of input and output frame data" "0,1"
bitfld.long 0x00 18.--21. "COEF_SHIFT,Coef Shift Size: configures the precision of" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 17. "UV_MODE,Source data interleave format" "0,1"
bitfld.long 0x00 16. "SAT_MODE,Filter Output Saturation Mode" "0,1"
bitfld.long 0x00 12.--15. "SP_VS_COEF_SEL,Single Phase Vertical Filter Coef Selection (sp_vs_coef_src = 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SP_VS_COEF_SRC,Single Phase Vertical Filter Coef Source Selection" "0,1"
newline
bitfld.long 0x00 7.--10. "SP_HS_COEF_SEL,Single Phase Horizontal Filter Coef Selection (sp_hs_coef_src = 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6. "SP_HS_COEF_SRC,Single Phase Horizontal Filter Coef Source Selection" "0,1"
bitfld.long 0x00 4.--5. "VS_COEF_SEL,Multi-phase Vertical Coef Selection (Phase_mode=0)" "0,1,2,3"
bitfld.long 0x00 2.--3. "HS_COEF_SEL,Multi-phase Horizontal Coef Selection (Phase_mode=0)" "0,1,2,3"
bitfld.long 0x00 1. "PHASE_MODE,Filter Phase mode selection" "0,1"
bitfld.long 0x00 0. "FILTER_MODE,Filter Mode" "0,1"
line.long 0x04 "VPAC_MSC_CORE_SRC_ROI_j,The FILT[a]_SRC_ROI register configures the input ROI position within the input super frame for FILTER channel [a]"
hexmask.long.word 0x04 16.--28. 1. "Y_OFFSET,Source Y offset"
hexmask.long.word 0x04 0.--12. 1. "X_OFFSET,Source X offset (Must be an even # when FILT_CFG.uv_mode=1)"
line.long 0x08 "VPAC_MSC_CORE_OUT_SIZE_j,The FILT[a]_OUT_SIZE configures the output size for FILTER channel [a]"
hexmask.long.word 0x08 16.--28. 1. "HEIGHT,Output Height"
hexmask.long.word 0x08 0.--12. 1. "WIDTH,Output Width"
line.long 0x0C "VPAC_MSC_CORE_FIRINC_j,The FILT[a]_FIRINC register configures the FIRINC attributes of FILTER channel [a]"
hexmask.long.word 0x0C 16.--30. 1. "VS,FIRINC of VS filter"
hexmask.long.word 0x0C 0.--14. 1. "HS,FIRINC of HS filter"
line.long 0x10 "VPAC_MSC_CORE_ACC_INIT_J,The FILT[a]_ACC_INIT register configures the FIRINC attributes of FILTER channel [a]"
hexmask.long.word 0x10 16.--27. 1. "VS,ACC_INIT of VS filter"
hexmask.long.word 0x10 0.--11. 1. "HS,ACC_INIT of HS filter"
group.long 0x180++0x07
line.long 0x00 "VPAC_MSC_CORE_C210_j,Single Phase Coef Set[a] coefficients C2/C1/C0 Offset = 001C0180h + (j * 8h); where j = 0h to 1h"
hexmask.long.word 0x00 20.--29. 1. "FIR_C2,Signed coefficient C2"
hexmask.long.word 0x00 10.--19. 1. "FIR_C1,Signed coefficient C1"
hexmask.long.word 0x00 0.--9. 1. "FIR_C0,Signed coefficient C0"
line.long 0x04 "VPAC_MSC_CORE_C43_j,Single Phase Coef Set[a] coefficients C4/C3 Offset = 001C0184h + (j * 8h); where j = 0h to 1h"
hexmask.long.word 0x04 10.--19. 1. "FIR_C4,Signed coefficient C4"
hexmask.long.word 0x04 0.--9. 1. "FIR_C3,Signed coefficient C3"
group.long 0x200++0x07
line.long 0x00 "VPAC_MSC_CORE_C210_j_k,Multi Phase Coef Set[a] Phase[b] coefficients C2/C1/C0 Offset = 001C0200h + (j * 100h) + (k * 8h); where j = 0h to 3h. k = 0h to 1Fh"
hexmask.long.word 0x00 20.--29. 1. "FIR_C2,Signed coefficient C2"
hexmask.long.word 0x00 10.--19. 1. "FIR_C1,Signed coefficient C1"
hexmask.long.word 0x00 0.--9. 1. "FIR_C0,Signed coefficient C0"
line.long 0x04 "VPAC_MSC_CORE_C43_j_k,Multi Phase Coef Set[a] Phase[b] coefficients C4/C3 Offset = 001C0204h + (j * 100h) + (k * 8h); where j = 0h to 3h. k = 0h to 1Fh"
hexmask.long.word 0x04 10.--19. 1. "FIR_C4,Signed coefficient C4"
hexmask.long.word 0x04 0.--9. 1. "FIR_C3,Signed coefficient C3"
tree.end
tree.end
tree "VPAC_MSC_LSE"
tree "VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP"
base ad:0xF1C0800
rgroup.long 0x00++0x13
line.long 0x00 "VPAC_MSC_STATUS_PARAM,The register returns the LSE compile configuration parameters"
bitfld.long 0x00 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3"
bitfld.long 0x00 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1"
bitfld.long 0x00 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1"
bitfld.long 0x00 23.--27. "CORE_OUT_DW,Core Output Channel Data Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1"
newline
bitfld.long 0x00 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1"
bitfld.long 0x00 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1"
bitfld.long 0x00 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--16. "CORE_DW,Core Input Data Bus Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3"
newline
bitfld.long 0x00 6.--9. "SL2_OUT_CH,Number of SL2 Output Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "VPORT_THR,Number of VPORT input enabled" "0,1"
bitfld.long 0x00 0.--1. "NTHR,Number of threads supported" "0,1,2,3"
line.long 0x04 "VPAC_MSC_STATUS_ERROR,The register returns the LSE error status"
hexmask.long.byte 0x04 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status"
bitfld.long 0x04 0.--4. "VM_RD_ERR,VBUSM I/F Last Read Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "VPAC_MSC_STATUS_IDLE_MODE,The register returns IDLE status of LSE VBUSM port and in/output"
hexmask.long.word 0x08 12.--21. 1. "LSE_OUT_CHAN,Output Channel"
bitfld.long 0x08 4.--5. "LSE_IN_CHAN,Input Channel" "0,1,2,3"
bitfld.long 0x08 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1"
bitfld.long 0x08 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1"
line.long 0x0C "VPAC_MSC_CFG_LSE,The register configures the LSE general hardware modes"
bitfld.long 0x0C 8. "PSA_EN,Test mode Output Channel Signature Generation Enable" "0,1"
bitfld.long 0x0C 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select" "0,1"
bitfld.long 0x0C 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode" "0,1"
bitfld.long 0x0C 0. "LOOPBACK_EN,LSE loopback mode enable" "0,1"
line.long 0x10 "VPAC_MSC_CFG_j,The SRC[a]_CFG register configures the input channels for the processing thread [a] Offset = 001C0810h + (j * 20h); where j = 0h to 1h"
bitfld.long 0x10 19.--21. "KERN_TPAD_SZ,Input kernel top padding lines valid=0..2 for msc" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "KERN_BPAD_SZ,Input kernel bottom padding lines valid=0..2 for msc" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 12.--15. "KERN_LN_OFFSET,Input kernel starting line position valid=0..4 for msc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "KERN_SZ_HEIGHT,Actual number of input kernel lines (height) valid=1..5 for msc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable" "0,1"
newline
bitfld.long 0x10 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment" "0,1"
bitfld.long 0x10 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIX_FMT_PW,Input Pixel Width Sel" "0,1,2,3"
group.long 0x18++0x07
line.long 0x00 "VPAC_MSC_FRAME_SIZE_j,The SRC[a]_FRAME_SIZE register configures the frame size of all input buffers for the processing thread [a]"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,SL"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,SL"
line.long 0x04 "VPAC_MSC_BUF_ATTR_j,The SRC[a]_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread [a]"
hexmask.long.byte 0x04 25.--31. 1. "START_NIB_OFFSET,Buffer Line start offset within the first SL2 data word - in half-byte (nibble) resolution"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x07
line.long 0x00 "VPAC_MSC_BUF_CFG_j,The DST[a]_BUF_CFG register configures the output buffer channel [a]"
bitfld.long 0x00 7. "THREAD_MAP,Output" "0,1"
bitfld.long 0x00 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment" "0,1"
bitfld.long 0x00 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel" "0,1,2,3"
bitfld.long 0x00 0.--1. "PIX_FMT_PW,Output Pixel Width Sel" "0,1,2,3"
line.long 0x04 "VPAC_MSC_BUF_ATTR0_j,The DST[a]_BUF_ATTR0 register configures the attributes of the output SL2 buffer [a]"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5C++0x03
line.long 0x00 "VPAC_MSC_BUF_BA_j,The SRC[a]_BUF_BA register configures the base address of the SL2 source buffer for the processing thread [a]"
bitfld.long 0x00 31. "ENABLE,Input Buffer Enable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x140++0x03
line.long 0x00 "VPAC_MSC_PSA_SIGNATURE_y,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]"
rgroup.long 0x1E0++0x03
line.long 0x00 "VPAC_MSC_DBG_y,The DBG register returns the current status of internal FSM - TI internal use only"
tree.end
tree.end
tree "VPAC_NF_CORE"
tree "VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG"
base ad:0xF1C2000
rgroup.long 0x00++0x0B
line.long 0x00 "VPAC_NF_CORE_REVISION,The Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VPAC_NF_CORE_CONTROL,This contains parameters to NF Core"
bitfld.long 0x04 29.--31. "SUB_TABLE_SELECT,Defines which sub table is used statically" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 27.--28. "NUM_SUB_TABLES,Defines the number of sub-tables" "0,1,2,3"
hexmask.long.word 0x04 15.--26. 1. "OUTPUT_OFFSET,unsigned offset value to added to output after shifting and before clipping"
bitfld.long 0x04 11.--14. "OUTPUT_SHIFT,Signed 4 bit (24 is added before using it inside IP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 6.--10. "RSVD,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 5. "INTERLEAVE_MODE,Interleave Mode" "0,1"
bitfld.long 0x04 4. "SKIP_ODD_MODE,Skip Odd Mode" "0,1"
bitfld.long 0x04 3. "SKIP_MODE,Skip Mode" "0,1"
newline
bitfld.long 0x04 2. "ADAPTIVE_MODE,Defines what controls the selection of the sub table" "0,1"
bitfld.long 0x04 1. "ENABLE_GENERIC_FILTERING,Filter mode " "0,1"
line.long 0x08 "VPAC_NF_CORE_CENTER_WEIGHT,Contain center weight parameter"
hexmask.long.tbyte 0x08 9.--31. 1. "RSVD,Always read as 0"
hexmask.long.word 0x08 0.--8. 1. "CENTRAL_PIXEL_WEIGHT_W00,Central pixel weight 8 bit unsigned in Bi-lateral filtering 9 bit signed in Generic 2D Filtering"
group.long 0x80++0x03
line.long 0x00 "VPAC_NF_CORE_DEBUG,"
bitfld.long 0x00 31. "BYPASS,Bypass Mode When enabled output equals the input namely C2_R0 input matrix" "0,1"
hexmask.long.tbyte 0x00 12.--29. 1. "RSVD,Always read as 0"
rbitfld.long 0x00 8.--11. "OUT_COUNT,output free running counter gets reset on start of line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "IN_COUNT,input free running counter gets reset on start of line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "T_STATE,StateMachine State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x100++0x03
line.long 0x00 "VPAC_NF_CORE_WEIGHT_LUT_Y,This contains weights for LUT"
hexmask.long.byte 0x00 24.--31. 1. "W_3,weight W_3"
hexmask.long.byte 0x00 16.--23. 1. "W_2,weight W_2"
hexmask.long.byte 0x00 8.--15. 1. "W_1,weight W_1"
hexmask.long.byte 0x00 0.--7. 1. "W_0,weight W_0"
tree.end
tree.end
tree "VPAC_NF_LSE"
tree "VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP"
base ad:0xF1C3000
rgroup.long 0x00++0x13
line.long 0x00 "VPAC_NF_LSE_STATUS_PARAM,The register returns the LSE compile configuration parameters"
bitfld.long 0x00 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3"
bitfld.long 0x00 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1"
bitfld.long 0x00 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1"
bitfld.long 0x00 23.--27. "CORE_OUT_DW,Core Output Channel Data Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1"
newline
bitfld.long 0x00 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1"
bitfld.long 0x00 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1"
bitfld.long 0x00 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--16. "CORE_DW,Core Input Data Bus Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3"
newline
bitfld.long 0x00 6.--9. "SL2_OUT_CH,Number of SL2 Output Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "VPORT_THR,Number of VPORT input enabled" "0,1"
bitfld.long 0x00 0.--1. "NTHR,Number of threads supported" "0,1,2,3"
line.long 0x04 "VPAC_NF_LSE_STATUS_ERROR,The register returns the LSE error status"
hexmask.long.byte 0x04 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status"
bitfld.long 0x04 0.--4. "VM_RD_ERR,VBUSM I/F Last Read Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "VPAC_NF_LSE_STATUS_IDLE_MODE,The register returns IDLE status of LSE VBUSM port and in/output"
bitfld.long 0x08 12. "LSE_OUT_CHAN,Output Channel" "0,1"
bitfld.long 0x08 4. "LSE_IN_CHAN,Input Channel" "0,1"
bitfld.long 0x08 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1"
bitfld.long 0x08 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1"
line.long 0x0C "VPAC_NF_LSE_CFG_LSE,The register configures the LSE general hardware modes"
bitfld.long 0x0C 8. "PSA_EN,Test mode Output Channel Signature Generation Enable" "0,1"
bitfld.long 0x0C 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select" "0,1"
bitfld.long 0x0C 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode" "0,1"
bitfld.long 0x0C 0. "LOOPBACK_EN,LSE loopback mode enable" "0,1"
line.long 0x10 "VPAC_NF_LSE_CFG,The SRC_CFG register configures the input channels for the processing thread"
bitfld.long 0x10 19.--21. "KERN_TPAD_SZ,Input kernel top padding lines valid=0..2 for nf" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "KERN_BPAD_SZ,Input kernel bottom padding lines valid=0..2 for nf" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 12.--15. "KERN_LN_OFFSET,Input kernel starting line position valid=0..4 for nf" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "KERN_SZ_HEIGHT,Actual number of input kernel lines (height) valid=1..5 for nf" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable" "0,1"
newline
bitfld.long 0x10 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment" "0,1"
bitfld.long 0x10 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIX_FMT_PW,Input Pixel Width Sel" "0,1,2,3"
group.long 0x18++0x07
line.long 0x00 "VPAC_NF_LSE_FRAME_SIZE,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,SL"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,SL"
line.long 0x04 "VPAC_NF_LSE_BUF_ATTR,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread"
hexmask.long.byte 0x04 25.--31. 1. "START_NIB_OFFSET,Buffer Line start offset within the first SL2 data word - in half-byte (nibble) resolution"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x07
line.long 0x00 "VPAC_NF_LSE_BUF_CFG,The DST_BUF_CFG register configures the output buffer channel"
bitfld.long 0x00 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment" "0,1"
bitfld.long 0x00 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel" "0,1,2,3"
bitfld.long 0x00 0.--1. "PIX_FMT_PW,Output Pixel Width Sel" "0,1,2,3"
line.long 0x04 "VPAC_NF_LSE_BUF_ATTR0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5C++0x03
line.long 0x00 "VPAC_NF_LSE_BUF_BA,The SRC_BUF_BA register configures the base address of the SL2 source buffer for the processing thread"
bitfld.long 0x00 31. "ENABLE,Input Buffer Enable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x140++0x03
line.long 0x00 "VPAC_NF_LSE_PSA_SIGNATURE,The register returns the captured PSA signature value of the last frame data of output channel [a]"
rgroup.long 0x1E0++0x03
line.long 0x00 "VPAC_NF_LSE_DBG_y,The DBG register returns the current status of internal FSM - TI internal use only"
tree.end
tree.end
tree "VPAC_TOP"
tree "VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS"
base ad:0xF000000
rgroup.long 0x00++0x03
line.long 0x00 "VPAC_PID,VPAC PID"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "VPAC_CTRL,Register to control and do event selection for VPAC module"
bitfld.long 0x00 4. "CTSET_DMA_SOC_DBG,select config for CTSET" "0,1"
bitfld.long 0x00 3. "CTSET_UTC_SL2_DBG,select config for CTSET" "0,1"
bitfld.long 0x00 2. "CTSET_HWA_SL2_DBG,select config for CTSET" "0,1"
bitfld.long 0x00 1. "CTSET_RT_UTC_OUT,select config for CTSET" "0,1"
bitfld.long 0x00 0. "CTSET_RT_UTC_IN,select config for CTSET" "0,1"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU"
base ad:0xF200000
rgroup.quad 0x00++0x0F
line.quad 0x00 "VPAC_UTC0_RT_DRU_PID,Peripheral ID Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad 0x00 0.--31. 1. "REVISION,PID Revision"
line.quad 0x08 "VPAC_UTC0_RT_DRU_CAPABILITIES,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions"
hexmask.quad.tbyte 0x08 47.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 43.--46. "SECTR,Maximum second TR function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 39.--42. "DFMT,Maximum data reformatting function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 35.--38. "ELTYPE,Maximum element type value that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 32.--34. "AMODE,The maximum AMODE that is supported" "0,1,2,3,4,5,6,7"
hexmask.quad.word 0x08 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features"
newline
bitfld.quad 0x08 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1"
bitfld.quad 0x08 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1"
bitfld.quad 0x08 17. "EOL,EOL Field is supported" "0,1"
bitfld.quad 0x08 16. "TRSTATIC,STATIC Field is supported" "0,1"
bitfld.quad 0x08 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.quad 0x08 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.quad 0x08 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.quad 0x08 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.quad 0x08 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.quad 0x08 10. "TYPE10,Type 10 TR is supported" "0,1"
bitfld.quad 0x08 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.quad 0x08 8. "TYPE8,Type 8 TR is supported" "0,1"
newline
bitfld.quad 0x08 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.quad 0x08 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.quad 0x08 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.quad 0x08 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.quad 0x08 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.quad 0x08 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.quad 0x08 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.quad 0x08 0. "TYPE0,Type 0 TR is supported" "0,1"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU_CAUSE"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE"
base ad:0xF2E0000
rgroup.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_CAUSE_y,Error Register cause for channels 0 to 15 Offset = 002E0000h + (y * 8h); where y = 0h to 1h"
bitfld.quad 0x00 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1"
bitfld.quad 0x00 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1"
bitfld.quad 0x00 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1"
newline
bitfld.quad 0x00 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1"
bitfld.quad 0x00 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1"
bitfld.quad 0x00 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1"
newline
bitfld.quad 0x00 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1"
bitfld.quad 0x00 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1"
bitfld.quad 0x00 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1"
newline
bitfld.quad 0x00 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1"
bitfld.quad 0x00 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1"
bitfld.quad 0x00 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1"
newline
bitfld.quad 0x00 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1"
bitfld.quad 0x00 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1"
bitfld.quad 0x00 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1"
newline
bitfld.quad 0x00 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1"
bitfld.quad 0x00 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1"
bitfld.quad 0x00 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1"
newline
bitfld.quad 0x00 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1"
bitfld.quad 0x00 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 3. "R_ERR0,Masked error bit for Tx channel n" "0,1"
bitfld.quad 0x00 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1"
bitfld.quad 0x00 1. "T_ERR0,Masked error bit for Tx channel n" "0,1"
newline
bitfld.quad 0x00 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU_CHATOMIC_DEBUG"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG"
base ad:0xF280000
rgroup.quad 0x00++0x7F
line.quad 0x00 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD0_1_j,The first TR submission word Offset = 00280000h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x00 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x00 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x00 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x08 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD2_3_j,The second TR submission word Offset = 00280008h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x08 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x08 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x10 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD4_5_j,The third TR submission word Offset = 00280010h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x10 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x18 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD6_7_j,The fourth TR submission word Offset = 00280018h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x18 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x18 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x20 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD8_9_j,The fifth TR submission word Offset = 00280020h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x28 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD10_11_j,The sixth TR submission word Offset = 00280028h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x28 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x30 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD12_13_j,The seventh TR submission word Offset = 00280030h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x38 "VPAC_UTC0_RT_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD14_15_j,The eight TR submission word Offset = 00280038h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
line.quad 0x40 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD0_1_j_k,The first TR submission word Offset = 00280040h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x40 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x40 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x40 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x48 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD2_3_j_k,The second TR submission word Offset = 00280048h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x48 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x48 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x50 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD4_5_j_k,The third TR submission word Offset = 00280050h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x50 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x50 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x50 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x58 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD6_7_j_k,The fourth TR submission word Offset = 00280058h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x58 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x58 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x60 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD8_9_j_k,The fifth TR submission word Offset = 00280060h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x60 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x60 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x68 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD10_11_j_k,The sixth TR submission word Offset = 00280068h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x68 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x68 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x70 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD12_13_j_k,The seventh TR submission word Offset = 00280070h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad 0x70 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x70 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x78 "VPAC_UTC0_RT_DRU_DEBUG_NEXT_TR_WORD14_15_j_k,The eight TR submission word Offset = 00280078h + (j * 100h) + (k * 40h); where j = 0h to 1Fh. k = 0h to 2h"
hexmask.quad.word 0x78 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x78 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x78 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x78 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU_CHNRT"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT"
base ad:0xF240000
group.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_CHNRT_CFG_j,Channel Configuration Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,RESERVED"
bitfld.quad 0x00 31. "PAUSE_ON_ERR,Pause on Error" "0,1"
bitfld.quad 0x00 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC" "0,1"
rbitfld.quad 0x00 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC" "0,1,2,3,4,5,6,7"
group.quad 0x20++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_CHNRT_CHOES0_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.quad 0x00 16.--63. 1. "RSVD,RESERVED"
hexmask.quad.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.quad 0x60++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_CHNRT_CHST_SCHED_j,Channel Static Scheduler Config Register Offset = 00240060h + (j * 100h); where j = 0h to 1Fh"
bitfld.quad 0x00 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU_CHRT"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT"
base ad:0xF260000
group.quad 0x00++0x1F
line.quad 0x00 "VPAC_UTC0_RT_DRU_CHRT_CHRT_CTL_j,The channel realtime control register contains real-time cotrol and status information for the DMA Channel"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 31. "ENABLE,This field enables or disables the channel" "0,1"
bitfld.quad 0x00 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.quad 0x00 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary" "0,1"
line.quad 0x08 "VPAC_UTC0_RT_DRU_CHRT_CHRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
hexmask.quad 0x08 3.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
bitfld.quad 0x08 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
bitfld.quad 0x08 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
line.quad 0x10 "VPAC_UTC0_RT_DRU_CHRT_CHRT_STATUS_DET_j,The channel status details Offset = 00260010h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad 0x10 16.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x10 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue"
bitfld.quad 0x10 4.--7. "INFO,The info of the error that was received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x10 0.--3. "STATUS_TYPE,The type of error that was received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x18 "VPAC_UTC0_RT_DRU_CHRT_CHRT_STATUS_CNT_j,The channel count details Offset = 00260018h + (j * 100h); where j = 0h to 1Fh"
hexmask.quad.word 0x18 48.--63. 1. "ICNT3,The last icnt3 given to the write queue"
hexmask.quad.word 0x18 32.--47. 1. "ICNT2,The last icnt2 given to the write queue"
hexmask.quad.word 0x18 16.--31. 1. "ICNT1,The last icnt1 given to the write queue"
hexmask.quad.word 0x18 0.--15. 1. "ICNT0,The last icnt0 given to the write queue"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU_QUEUE"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE"
base ad:0xF208000
group.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_QUEUE_CFG_y,Configuration Register for Queue 0 Offset = 00208000h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x00 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands"
hexmask.quad.byte 0x00 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands"
bitfld.quad 0x00 8.--10. "QOS,This configures the QOS for QUEUE0" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 4.--7. "ORDERID,This configures the orderid for QUEUE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0.--2. "PRI,This configures the priority for QUEUE0" "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_QUEUE_STATUS_y,Status Register for Queue 0 Offset = 00208040h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 36.--63. 1. "RSVD,Reserved"
hexmask.quad.word 0x00 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on"
tree.end
tree.end
tree "VPAC_UTC0_RT_DRU_SET"
tree "VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET"
base ad:0xF204000
group.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_SHARED_EVT_SET,DRU Shared Event Set Register"
hexmask.quad 0x00 1.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 0. "PROT_ERR,Set the Prot Error event" "0,1"
group.quad 0x40++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_COMP_EVT_SET0,DRU Completion Event Set Register"
bitfld.quad 0x00 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1"
bitfld.quad 0x00 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1"
newline
bitfld.quad 0x00 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1"
bitfld.quad 0x00 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1"
bitfld.quad 0x00 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1"
newline
bitfld.quad 0x00 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1"
bitfld.quad 0x00 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1"
bitfld.quad 0x00 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1"
newline
bitfld.quad 0x00 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1"
bitfld.quad 0x00 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1"
newline
bitfld.quad 0x00 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1"
group.quad 0x80++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_ERR_EVT_SET0,DRU Error Event Set Register"
bitfld.quad 0x00 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1"
bitfld.quad 0x00 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1"
bitfld.quad 0x00 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1"
bitfld.quad 0x00 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1"
bitfld.quad 0x00 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1"
bitfld.quad 0x00 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1"
bitfld.quad 0x00 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1"
newline
bitfld.quad 0x00 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1"
bitfld.quad 0x00 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1"
bitfld.quad 0x00 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1"
bitfld.quad 0x00 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1"
bitfld.quad 0x00 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1"
bitfld.quad 0x00 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1"
bitfld.quad 0x00 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1"
newline
bitfld.quad 0x00 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1"
bitfld.quad 0x00 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1"
bitfld.quad 0x00 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1"
bitfld.quad 0x00 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1"
bitfld.quad 0x00 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1"
bitfld.quad 0x00 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1"
bitfld.quad 0x00 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1"
newline
bitfld.quad 0x00 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1"
bitfld.quad 0x00 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1"
bitfld.quad 0x00 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1"
bitfld.quad 0x00 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1"
bitfld.quad 0x00 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1"
bitfld.quad 0x00 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1"
bitfld.quad 0x00 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1"
newline
bitfld.quad 0x00 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1"
bitfld.quad 0x00 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1"
bitfld.quad 0x00 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1"
bitfld.quad 0x00 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1"
group.quad 0xC0++0x07
line.quad 0x00 "VPAC_UTC0_RT_DRU_LOCAL_EVT_SET0,DRU Local Event Set Register"
bitfld.quad 0x00 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1"
bitfld.quad 0x00 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1"
newline
bitfld.quad 0x00 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1"
bitfld.quad 0x00 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1"
bitfld.quad 0x00 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1"
newline
bitfld.quad 0x00 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1"
bitfld.quad 0x00 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1"
bitfld.quad 0x00 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1"
newline
bitfld.quad 0x00 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1"
bitfld.quad 0x00 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1"
newline
bitfld.quad 0x00 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU"
base ad:0xF300000
rgroup.quad 0x00++0x0F
line.quad 0x00 "VPAC_UTC1_DRU_PID,Peripheral ID Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad 0x00 0.--31. 1. "REVISION,PID Revision"
line.quad 0x08 "VPAC_UTC1_DRU_CAPABILITIES,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions"
hexmask.quad.tbyte 0x08 47.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 43.--46. "SECTR,Maximum second TR function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 39.--42. "DFMT,Maximum data reformatting function that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 35.--38. "ELTYPE,Maximum element type value that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 32.--34. "AMODE,The maximum AMODE that is supported" "0,1,2,3,4,5,6,7"
hexmask.quad.word 0x08 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features"
newline
bitfld.quad 0x08 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1"
bitfld.quad 0x08 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1"
bitfld.quad 0x08 17. "EOL,EOL Field is supported" "0,1"
bitfld.quad 0x08 16. "TRSTATIC,STATIC Field is supported" "0,1"
bitfld.quad 0x08 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.quad 0x08 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.quad 0x08 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.quad 0x08 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.quad 0x08 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.quad 0x08 10. "TYPE10,Type 10 TR is supported" "0,1"
bitfld.quad 0x08 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.quad 0x08 8. "TYPE8,Type 8 TR is supported" "0,1"
newline
bitfld.quad 0x08 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.quad 0x08 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.quad 0x08 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.quad 0x08 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.quad 0x08 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.quad 0x08 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.quad 0x08 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.quad 0x08 0. "TYPE0,Type 0 TR is supported" "0,1"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU_CAUSE"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE"
base ad:0xF3E0000
rgroup.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC1_DRU_CAUSE_y,Error Register cause for channels 0 to 15 Offset = 003E0000h + (y * 8h); where y = 0h to 3h"
bitfld.quad 0x00 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1"
bitfld.quad 0x00 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1"
bitfld.quad 0x00 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1"
bitfld.quad 0x00 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1"
bitfld.quad 0x00 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1"
newline
bitfld.quad 0x00 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1"
bitfld.quad 0x00 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1"
bitfld.quad 0x00 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1"
bitfld.quad 0x00 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1"
bitfld.quad 0x00 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1"
newline
bitfld.quad 0x00 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1"
bitfld.quad 0x00 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1"
bitfld.quad 0x00 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1"
bitfld.quad 0x00 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1"
bitfld.quad 0x00 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1"
newline
bitfld.quad 0x00 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1"
bitfld.quad 0x00 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1"
bitfld.quad 0x00 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1"
bitfld.quad 0x00 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1"
bitfld.quad 0x00 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1"
bitfld.quad 0x00 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1"
newline
bitfld.quad 0x00 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1"
bitfld.quad 0x00 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1"
bitfld.quad 0x00 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1"
bitfld.quad 0x00 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1"
bitfld.quad 0x00 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1"
newline
bitfld.quad 0x00 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1"
bitfld.quad 0x00 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1"
bitfld.quad 0x00 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1"
bitfld.quad 0x00 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1"
bitfld.quad 0x00 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1"
newline
bitfld.quad 0x00 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1"
bitfld.quad 0x00 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1"
bitfld.quad 0x00 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1"
bitfld.quad 0x00 3. "R_ERR0,Masked error bit for Tx channel n" "0,1"
bitfld.quad 0x00 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1"
bitfld.quad 0x00 1. "T_ERR0,Masked error bit for Tx channel n" "0,1"
newline
bitfld.quad 0x00 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU_CHATOMIC_DEBUG"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG"
base ad:0xF380000
rgroup.quad 0x00++0x7F
line.quad 0x00 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD0_1_j,The first TR submission word Offset = 00380000h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x00 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x00 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x00 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x08 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD2_3_j,The second TR submission word Offset = 00380008h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x08 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x08 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x10 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD4_5_j,The third TR submission word Offset = 00380010h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x10 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x18 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD6_7_j,The fourth TR submission word Offset = 00380018h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad 0x18 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x18 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x20 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD8_9_j,The fifth TR submission word Offset = 00380020h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x28 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD10_11_j,The sixth TR submission word Offset = 00380028h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x28 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x30 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD12_13_j,The seventh TR submission word Offset = 00380030h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x38 "VPAC_UTC1_DRU_DEBUG_ATOMIC_SUBMIT_CURR_TR_WORD14_15_j,The eight TR submission word Offset = 00380038h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
line.quad 0x40 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD0_1_j_k,The first TR submission word Offset = 00380040h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad.word 0x40 48.--63. 1. "ICNT1,Lines in a transfer"
hexmask.quad.word 0x40 32.--47. 1. "ICNT0,Bytes in a transfer"
hexmask.quad 0x40 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor"
line.quad 0x48 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD2_3_j_k,The second TR submission word Offset = 00380048h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad.word 0x48 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x48 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed"
line.quad 0x50 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD4_5_j_k,The third TR submission word Offset = 00380050h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad.word 0x50 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer"
hexmask.quad.word 0x50 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer"
hexmask.quad 0x50 0.--31. 1. "DIM1,The first dimension width of the source data"
line.quad 0x58 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD6_7_j_k,The fourth TR submission word Offset = 00380058h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad 0x58 32.--63. 1. "DIM3,The third dimension width of the source data"
hexmask.quad 0x58 0.--31. 1. "DIM2,The second dimension width of the source data"
line.quad 0x60 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD8_9_j_k,The fifth TR submission word Offset = 00380060h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad 0x60 32.--63. 1. "DDIM1,The first dimension width of the destination data"
hexmask.quad 0x60 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR"
line.quad 0x68 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD10_11_j_k,The sixth TR submission word Offset = 00380068h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad.word 0x68 48.--63. 1. "RSVD,Reserved"
hexmask.quad 0x68 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed"
line.quad 0x70 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD12_13_j_k,The seventh TR submission word Offset = 00380070h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad 0x70 32.--63. 1. "DDIM3,The third dimension width of the destination data"
hexmask.quad 0x70 0.--31. 1. "DDIM2,The second dimension width of the destination data"
line.quad 0x78 "VPAC_UTC1_DRU_DEBUG_NEXT_TR_WORD14_15_j_k,The eight TR submission word Offset = 00380078h + (j * 100h) + (k * 40h); where j = 0h to 3Fh. k = 0h to 2h"
hexmask.quad.word 0x78 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source"
hexmask.quad.word 0x78 32.--47. 1. "DICNT2,The third count of the destination if different than the source"
hexmask.quad.word 0x78 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source"
hexmask.quad.word 0x78 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU_CHNRT"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT"
base ad:0xF340000
group.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC1_DRU_CHNRT_CFG_j,Channel Configuration Register"
hexmask.quad 0x00 32.--63. 1. "RSVD,RESERVED"
bitfld.quad 0x00 31. "PAUSE_ON_ERR,Pause on Error" "0,1"
bitfld.quad 0x00 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC" "0,1"
rbitfld.quad 0x00 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC" "0,1,2,3,4,5,6,7"
group.quad 0x20++0x07
line.quad 0x00 "VPAC_UTC1_DRU_CHNRT_CHOES0_j,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met"
hexmask.quad 0x00 16.--63. 1. "RSVD,RESERVED"
hexmask.quad.word 0x00 0.--15. 1. "EVT_NUM,This is the global event number to be generated"
group.quad 0x60++0x07
line.quad 0x00 "VPAC_UTC1_DRU_CHNRT_CHST_SCHED_j,Channel Static Scheduler Config Register Offset = 00340060h + (j * 100h); where j = 0h to 3Fh"
bitfld.quad 0x00 0.--2. "QUEUE,This is the queue number that is written" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU_CHRT"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT"
base ad:0xF360000
group.quad 0x00++0x1F
line.quad 0x00 "VPAC_UTC1_DRU_CHRT_CTL_j,The channel realtime control register contains real-time cotrol and status information for the DMA Channel"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 31. "ENABLE,This field enables or disables the channel" "0,1"
bitfld.quad 0x00 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.quad 0x00 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary" "0,1"
line.quad 0x08 "VPAC_UTC1_DRU_CHRT_SWTRIG_j,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
hexmask.quad 0x08 3.--63. 1. "RSVD,Reserved"
bitfld.quad 0x08 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
bitfld.quad 0x08 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
bitfld.quad 0x08 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
line.quad 0x10 "VPAC_UTC1_DRU_CHRT_STATUS_DET_j,The channel status details Offset = 00360010h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad 0x10 16.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x10 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue"
bitfld.quad 0x10 4.--7. "INFO,The info of the error that was received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x10 0.--3. "STATUS_TYPE,The type of error that was received" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x18 "VPAC_UTC1_DRU_CHRT_STATUS_CNT_j,The channel count details Offset = 00360018h + (j * 100h); where j = 0h to 3Fh"
hexmask.quad.word 0x18 48.--63. 1. "ICNT3,The last icnt3 given to the write queue"
hexmask.quad.word 0x18 32.--47. 1. "ICNT2,The last icnt2 given to the write queue"
hexmask.quad.word 0x18 16.--31. 1. "ICNT1,The last icnt1 given to the write queue"
hexmask.quad.word 0x18 0.--15. 1. "ICNT0,The last icnt0 given to the write queue"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU_QUEUE"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE"
base ad:0xF308000
group.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC1_DRU_QUEUE_CFG_y,Configuration Register for Queue 0 Offset = 00308000h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 32.--63. 1. "RSVD,Reserved"
hexmask.quad.byte 0x00 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands"
hexmask.quad.byte 0x00 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands"
bitfld.quad 0x00 8.--10. "QOS,This configures the QOS for QUEUE0" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 4.--7. "ORDERID,This configures the orderid for QUEUE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0.--2. "PRI,This configures the priority for QUEUE0" "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x07
line.quad 0x00 "VPAC_UTC1_DRU_QUEUE_STATUS_y,Status Register for Queue 0 Offset = 00308040h + (y * 8h); where y = 0h to 4h"
hexmask.quad 0x00 36.--63. 1. "RSVD,Reserved"
hexmask.quad.word 0x00 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on"
hexmask.quad.word 0x00 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on"
tree.end
tree.end
tree "VPAC_UTC1_NRT_DRU_SET"
tree "VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET"
base ad:0xF304000
group.quad 0x00++0x07
line.quad 0x00 "VPAC_UTC1_DRU_SHARED_EVT_SET,DRU Shared Event Set Register"
hexmask.quad 0x00 1.--63. 1. "RSVD,Reserved"
bitfld.quad 0x00 0. "PROT_ERR,Set the Prot Error event" "0,1"
group.quad 0x40++0x07
line.quad 0x00 "VPAC_UTC1_DRU_COMP_EVT_SET0,DRU Completion Event Set Register"
bitfld.quad 0x00 63. "COMP_EVT63,Set the Completion Event for channel 63" "0,1"
bitfld.quad 0x00 62. "COMP_EVT62,Set the Completion Event for channel 62" "0,1"
bitfld.quad 0x00 61. "COMP_EVT61,Set the Completion Event for channel 61" "0,1"
bitfld.quad 0x00 60. "COMP_EVT60,Set the Completion Event for channel 60" "0,1"
bitfld.quad 0x00 59. "COMP_EVT59,Set the Completion Event for channel 59" "0,1"
bitfld.quad 0x00 58. "COMP_EVT58,Set the Completion Event for channel 58" "0,1"
bitfld.quad 0x00 57. "COMP_EVT57,Set the Completion Event for channel 57" "0,1"
bitfld.quad 0x00 56. "COMP_EVT56,Set the Completion Event for channel 56" "0,1"
newline
bitfld.quad 0x00 55. "COMP_EVT55,Set the Completion Event for channel 55" "0,1"
bitfld.quad 0x00 54. "COMP_EVT54,Set the Completion Event for channel 54" "0,1"
bitfld.quad 0x00 53. "COMP_EVT53,Set the Completion Event for channel 53" "0,1"
bitfld.quad 0x00 52. "COMP_EVT52,Set the Completion Event for channel 52" "0,1"
bitfld.quad 0x00 51. "COMP_EVT51,Set the Completion Event for channel 51" "0,1"
bitfld.quad 0x00 50. "COMP_EVT50,Set the Completion Event for channel 50" "0,1"
bitfld.quad 0x00 49. "COMP_EVT49,Set the Completion Event for channel 49" "0,1"
bitfld.quad 0x00 48. "COMP_EVT48,Set the Completion Event for channel 48" "0,1"
newline
bitfld.quad 0x00 47. "COMP_EVT47,Set the Completion Event for channel 47" "0,1"
bitfld.quad 0x00 46. "COMP_EVT46,Set the Completion Event for channel 46" "0,1"
bitfld.quad 0x00 45. "COMP_EVT45,Set the Completion Event for channel 45" "0,1"
bitfld.quad 0x00 44. "COMP_EVT44,Set the Completion Event for channel 44" "0,1"
bitfld.quad 0x00 43. "COMP_EVT43,Set the Completion Event for channel 43" "0,1"
bitfld.quad 0x00 42. "COMP_EVT42,Set the Completion Event for channel 42" "0,1"
bitfld.quad 0x00 41. "COMP_EVT41,Set the Completion Event for channel 41" "0,1"
bitfld.quad 0x00 40. "COMP_EVT40,Set the Completion Event for channel 40" "0,1"
newline
bitfld.quad 0x00 39. "COMP_EVT39,Set the Completion Event for channel 39" "0,1"
bitfld.quad 0x00 38. "COMP_EVT38,Set the Completion Event for channel 38" "0,1"
bitfld.quad 0x00 37. "COMP_EVT37,Set the Completion Event for channel 37" "0,1"
bitfld.quad 0x00 36. "COMP_EVT36,Set the Completion Event for channel 36" "0,1"
bitfld.quad 0x00 35. "COMP_EVT35,Set the Completion Event for channel 35" "0,1"
bitfld.quad 0x00 34. "COMP_EVT34,Set the Completion Event for channel 34" "0,1"
bitfld.quad 0x00 33. "COMP_EVT33,Set the Completion Event for channel 33" "0,1"
bitfld.quad 0x00 32. "COMP_EVT32,Set the Completion Event for channel 32" "0,1"
newline
bitfld.quad 0x00 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1"
bitfld.quad 0x00 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1"
bitfld.quad 0x00 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1"
bitfld.quad 0x00 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1"
bitfld.quad 0x00 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1"
bitfld.quad 0x00 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1"
bitfld.quad 0x00 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1"
bitfld.quad 0x00 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1"
group.quad 0x80++0x07
line.quad 0x00 "VPAC_UTC1_DRU_ERR_EVT_SET0,DRU Error Event Set Register"
bitfld.quad 0x00 63. "ERR_EVT63,Set the Error Event for channel 63" "0,1"
bitfld.quad 0x00 62. "ERR_EVT62,Set the Error Event for channel 62" "0,1"
bitfld.quad 0x00 61. "ERR_EVT61,Set the Error Event for channel 61" "0,1"
bitfld.quad 0x00 60. "ERR_EVT60,Set the Error Event for channel 60" "0,1"
bitfld.quad 0x00 59. "ERR_EVT59,Set the Error Event for channel 59" "0,1"
bitfld.quad 0x00 58. "ERR_EVT58,Set the Error Event for channel 58" "0,1"
bitfld.quad 0x00 57. "ERR_EVT57,Set the Error Event for channel 57" "0,1"
bitfld.quad 0x00 56. "ERR_EVT56,Set the Error Event for channel 56" "0,1"
newline
bitfld.quad 0x00 55. "ERR_EVT55,Set the Error Event for channel 55" "0,1"
bitfld.quad 0x00 54. "ERR_EVT54,Set the Error Event for channel 54" "0,1"
bitfld.quad 0x00 53. "ERR_EVT53,Set the Error Event for channel 53" "0,1"
bitfld.quad 0x00 52. "ERR_EVT52,Set the Error Event for channel 52" "0,1"
bitfld.quad 0x00 51. "ERR_EVT51,Set the Error Event for channel 51" "0,1"
bitfld.quad 0x00 50. "ERR_EVT50,Set the Error Event for channel 50" "0,1"
bitfld.quad 0x00 49. "ERR_EVT49,Set the Error Event for channel 49" "0,1"
bitfld.quad 0x00 48. "ERR_EVT48,Set the Error Event for channel 48" "0,1"
newline
bitfld.quad 0x00 47. "ERR_EVT47,Set the Error Event for channel 47" "0,1"
bitfld.quad 0x00 46. "ERR_EVT46,Set the Error Event for channel 46" "0,1"
bitfld.quad 0x00 45. "ERR_EVT45,Set the Error Event for channel 45" "0,1"
bitfld.quad 0x00 44. "ERR_EVT44,Set the Error Event for channel 44" "0,1"
bitfld.quad 0x00 43. "ERR_EVT43,Set the Error Event for channel 43" "0,1"
bitfld.quad 0x00 42. "ERR_EVT42,Set the Error Event for channel 42" "0,1"
bitfld.quad 0x00 41. "ERR_EVT41,Set the Error Event for channel 41" "0,1"
bitfld.quad 0x00 40. "ERR_EVT40,Set the Error Event for channel 40" "0,1"
newline
bitfld.quad 0x00 39. "ERR_EVT39,Set the Error Event for channel 39" "0,1"
bitfld.quad 0x00 38. "ERR_EVT38,Set the Error Event for channel 38" "0,1"
bitfld.quad 0x00 37. "ERR_EVT37,Set the Error Event for channel 37" "0,1"
bitfld.quad 0x00 36. "ERR_EVT36,Set the Error Event for channel 36" "0,1"
bitfld.quad 0x00 35. "ERR_EVT35,Set the Error Event for channel 35" "0,1"
bitfld.quad 0x00 34. "ERR_EVT34,Set the Error Event for channel 34" "0,1"
bitfld.quad 0x00 33. "ERR_EVT33,Set the Error Event for channel 33" "0,1"
bitfld.quad 0x00 32. "ERR_EVT32,Set the Error Event for channel 32" "0,1"
newline
bitfld.quad 0x00 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1"
bitfld.quad 0x00 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1"
bitfld.quad 0x00 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1"
bitfld.quad 0x00 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1"
bitfld.quad 0x00 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1"
bitfld.quad 0x00 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1"
bitfld.quad 0x00 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1"
bitfld.quad 0x00 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1"
bitfld.quad 0x00 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1"
bitfld.quad 0x00 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1"
bitfld.quad 0x00 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1"
bitfld.quad 0x00 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1"
bitfld.quad 0x00 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1"
bitfld.quad 0x00 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1"
bitfld.quad 0x00 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1"
bitfld.quad 0x00 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1"
bitfld.quad 0x00 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1"
bitfld.quad 0x00 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1"
bitfld.quad 0x00 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1"
bitfld.quad 0x00 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1"
bitfld.quad 0x00 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1"
bitfld.quad 0x00 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1"
bitfld.quad 0x00 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1"
bitfld.quad 0x00 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1"
bitfld.quad 0x00 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1"
bitfld.quad 0x00 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1"
bitfld.quad 0x00 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1"
bitfld.quad 0x00 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1"
bitfld.quad 0x00 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1"
group.quad 0xC0++0x07
line.quad 0x00 "VPAC_UTC1_DRU_LOCAL_EVT_SET0,DRU Local Event Set Register"
bitfld.quad 0x00 63. "COMP_EVT63,Set the Local Event for channel 63" "0,1"
bitfld.quad 0x00 62. "COMP_EVT62,Set the Local Event for channel 62" "0,1"
bitfld.quad 0x00 61. "COMP_EVT61,Set the Local Event for channel 61" "0,1"
bitfld.quad 0x00 60. "COMP_EVT60,Set the Local Event for channel 60" "0,1"
bitfld.quad 0x00 59. "COMP_EVT59,Set the Local Event for channel 59" "0,1"
bitfld.quad 0x00 58. "COMP_EVT58,Set the Local Event for channel 58" "0,1"
bitfld.quad 0x00 57. "COMP_EVT57,Set the Local Event for channel 57" "0,1"
bitfld.quad 0x00 56. "COMP_EVT56,Set the Local Event for channel 56" "0,1"
newline
bitfld.quad 0x00 55. "COMP_EVT55,Set the Local Event for channel 55" "0,1"
bitfld.quad 0x00 54. "COMP_EVT54,Set the Local Event for channel 54" "0,1"
bitfld.quad 0x00 53. "COMP_EVT53,Set the Local Event for channel 53" "0,1"
bitfld.quad 0x00 52. "COMP_EVT52,Set the Local Event for channel 52" "0,1"
bitfld.quad 0x00 51. "COMP_EVT51,Set the Local Event for channel 51" "0,1"
bitfld.quad 0x00 50. "COMP_EVT50,Set the Local Event for channel 50" "0,1"
bitfld.quad 0x00 49. "COMP_EVT49,Set the Local Event for channel 49" "0,1"
bitfld.quad 0x00 48. "COMP_EVT48,Set the Local Event for channel 48" "0,1"
newline
bitfld.quad 0x00 47. "COMP_EVT47,Set the Local Event for channel 47" "0,1"
bitfld.quad 0x00 46. "COMP_EVT46,Set the Local Event for channel 46" "0,1"
bitfld.quad 0x00 45. "COMP_EVT45,Set the Local Event for channel 45" "0,1"
bitfld.quad 0x00 44. "COMP_EVT44,Set the Local Event for channel 44" "0,1"
bitfld.quad 0x00 43. "COMP_EVT43,Set the Local Event for channel 43" "0,1"
bitfld.quad 0x00 42. "COMP_EVT42,Set the Local Event for channel 42" "0,1"
bitfld.quad 0x00 41. "COMP_EVT41,Set the Local Event for channel 41" "0,1"
bitfld.quad 0x00 40. "COMP_EVT40,Set the Local Event for channel 40" "0,1"
newline
bitfld.quad 0x00 39. "COMP_EVT39,Set the Local Event for channel 39" "0,1"
bitfld.quad 0x00 38. "COMP_EVT38,Set the Local Event for channel 38" "0,1"
bitfld.quad 0x00 37. "COMP_EVT37,Set the Local Event for channel 37" "0,1"
bitfld.quad 0x00 36. "COMP_EVT36,Set the Local Event for channel 36" "0,1"
bitfld.quad 0x00 35. "COMP_EVT35,Set the Local Event for channel 35" "0,1"
bitfld.quad 0x00 34. "COMP_EVT34,Set the Local Event for channel 34" "0,1"
bitfld.quad 0x00 33. "COMP_EVT33,Set the Local Event for channel 33" "0,1"
bitfld.quad 0x00 32. "COMP_EVT32,Set the Local Event for channel 32" "0,1"
newline
bitfld.quad 0x00 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1"
bitfld.quad 0x00 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1"
bitfld.quad 0x00 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1"
bitfld.quad 0x00 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1"
bitfld.quad 0x00 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1"
bitfld.quad 0x00 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1"
bitfld.quad 0x00 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1"
bitfld.quad 0x00 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1"
newline
bitfld.quad 0x00 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1"
bitfld.quad 0x00 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1"
bitfld.quad 0x00 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1"
bitfld.quad 0x00 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1"
bitfld.quad 0x00 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1"
bitfld.quad 0x00 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1"
bitfld.quad 0x00 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1"
bitfld.quad 0x00 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1"
newline
bitfld.quad 0x00 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1"
bitfld.quad 0x00 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1"
bitfld.quad 0x00 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1"
bitfld.quad 0x00 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1"
bitfld.quad 0x00 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1"
bitfld.quad 0x00 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1"
bitfld.quad 0x00 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1"
bitfld.quad 0x00 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1"
newline
bitfld.quad 0x00 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1"
bitfld.quad 0x00 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1"
bitfld.quad 0x00 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1"
bitfld.quad 0x00 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1"
bitfld.quad 0x00 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1"
bitfld.quad 0x00 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1"
bitfld.quad 0x00 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1"
bitfld.quad 0x00 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1"
tree.end
tree.end
tree "VPAC_VISS_ECC_AGGR"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG"
base ad:0x2A61000
rgroup.long 0x00++0x03
line.long 0x00 "VPAC_VISS_ECC_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "VPAC_VISS_ECC_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "VPAC_VISS_ECC_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "VPAC_VISS_ECC_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x0B
line.long 0x00 "VPAC_VISS_ECC_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "VPAC_VISS_ECC_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 30. "FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 29. "FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 28. "FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 27. "FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 26. "FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 25. "FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 24. "FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 23. "FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 22. "FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 21. "FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 20. "FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 19. "STAT_MEM7_RAMECC_PEND,Interrupt Pending Status for stat_mem7_ramecc_pend" "0,1"
bitfld.long 0x04 18. "STAT_MEM6_RAMECC_PEND,Interrupt Pending Status for stat_mem6_ramecc_pend" "0,1"
bitfld.long 0x04 17. "STAT_MEM5_RAMECC_PEND,Interrupt Pending Status for stat_mem5_ramecc_pend" "0,1"
newline
bitfld.long 0x04 16. "STAT_MEM4_RAMECC_PEND,Interrupt Pending Status for stat_mem4_ramecc_pend" "0,1"
bitfld.long 0x04 15. "STAT_MEM3_RAMECC_PEND,Interrupt Pending Status for stat_mem3_ramecc_pend" "0,1"
bitfld.long 0x04 14. "STAT_MEM2_RAMECC_PEND,Interrupt Pending Status for stat_mem2_ramecc_pend" "0,1"
newline
bitfld.long 0x04 13. "STAT_MEM1_RAMECC_PEND,Interrupt Pending Status for stat_mem1_ramecc_pend" "0,1"
bitfld.long 0x04 12. "STAT_MEM0_RAMECC_PEND,Interrupt Pending Status for stat_mem0_ramecc_pend" "0,1"
bitfld.long 0x04 11. "H3A_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 10. "H3A_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 9. "LSC_RAMECC_PEND,Interrupt Pending Status for lsc_ramecc_pend" "0,1"
bitfld.long 0x04 8. "DPC_LUT_RAMECC_PEND,Interrupt Pending Status for dpc_lut_ramecc_pend" "0,1"
newline
bitfld.long 0x04 7. "WDR_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 6. "WDR_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 5. "LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 4. "LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 3. "LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for lut2_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 1. "LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for lut3_ram0_ramecc_pend" "0,1"
line.long 0x08 "VPAC_VISS_ECC_SEC_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 5. "EELUT_1_RAMECC_PEND,Interrupt Pending Status for eelut_1_ramecc_pend" "0,1"
bitfld.long 0x08 4. "EELUT_0_RAMECC_PEND,Interrupt Pending Status for eelut_0_ramecc_pend" "0,1"
bitfld.long 0x08 3. "LUT_1_RAMECC_PEND,Interrupt Pending Status for lut_1_ramecc_pend" "0,1"
newline
bitfld.long 0x08 2. "LUT_0_RAMECC_PEND,Interrupt Pending Status for lut_0_ramecc_pend" "0,1"
bitfld.long 0x08 1. "FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x08 0. "FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram0_ramecc_pend" "0,1"
group.long 0x80++0x07
line.long 0x00 "VPAC_VISS_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 21. "FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 20. "FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 19. "STAT_MEM7_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem7_ramecc_pend" "0,1"
bitfld.long 0x00 18. "STAT_MEM6_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem6_ramecc_pend" "0,1"
bitfld.long 0x00 17. "STAT_MEM5_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem5_ramecc_pend" "0,1"
newline
bitfld.long 0x00 16. "STAT_MEM4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem4_ramecc_pend" "0,1"
bitfld.long 0x00 15. "STAT_MEM3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem3_ramecc_pend" "0,1"
bitfld.long 0x00 14. "STAT_MEM2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem2_ramecc_pend" "0,1"
newline
bitfld.long 0x00 13. "STAT_MEM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem1_ramecc_pend" "0,1"
bitfld.long 0x00 12. "STAT_MEM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "H3A_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 10. "H3A_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 9. "LSC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lsc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "DPC_LUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_lut_ramecc_pend" "0,1"
newline
bitfld.long 0x00 7. "WDR_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 6. "WDR_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 5. "LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 4. "LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 3. "LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram0_ramecc_pend" "0,1"
line.long 0x04 "VPAC_VISS_ECC_SEC_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 5. "EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_1_ramecc_pend" "0,1"
bitfld.long 0x04 4. "EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_0_ramecc_pend" "0,1"
bitfld.long 0x04 3. "LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram0_ramecc_pend" "0,1"
group.long 0xC0++0x07
line.long 0x00 "VPAC_VISS_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 21. "FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 20. "FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 19. "STAT_MEM7_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem7_ramecc_pend" "0,1"
bitfld.long 0x00 18. "STAT_MEM6_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem6_ramecc_pend" "0,1"
bitfld.long 0x00 17. "STAT_MEM5_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem5_ramecc_pend" "0,1"
newline
bitfld.long 0x00 16. "STAT_MEM4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem4_ramecc_pend" "0,1"
bitfld.long 0x00 15. "STAT_MEM3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem3_ramecc_pend" "0,1"
bitfld.long 0x00 14. "STAT_MEM2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem2_ramecc_pend" "0,1"
newline
bitfld.long 0x00 13. "STAT_MEM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem1_ramecc_pend" "0,1"
bitfld.long 0x00 12. "STAT_MEM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "H3A_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 10. "H3A_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 9. "LSC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lsc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "DPC_LUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_lut_ramecc_pend" "0,1"
newline
bitfld.long 0x00 7. "WDR_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 6. "WDR_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 5. "LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 4. "LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 3. "LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram0_ramecc_pend" "0,1"
line.long 0x04 "VPAC_VISS_ECC_SEC_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 5. "EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_1_ramecc_pend" "0,1"
bitfld.long 0x04 4. "EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_0_ramecc_pend" "0,1"
bitfld.long 0x04 3. "LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram0_ramecc_pend" "0,1"
group.long 0x13C++0x0B
line.long 0x00 "VPAC_VISS_ECC_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "VPAC_VISS_ECC_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 31. "FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 30. "FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 29. "FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 28. "FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 27. "FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 26. "FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 25. "FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 24. "FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 23. "FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 22. "FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 21. "FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 20. "FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 19. "STAT_MEM7_RAMECC_PEND,Interrupt Pending Status for stat_mem7_ramecc_pend" "0,1"
bitfld.long 0x04 18. "STAT_MEM6_RAMECC_PEND,Interrupt Pending Status for stat_mem6_ramecc_pend" "0,1"
bitfld.long 0x04 17. "STAT_MEM5_RAMECC_PEND,Interrupt Pending Status for stat_mem5_ramecc_pend" "0,1"
newline
bitfld.long 0x04 16. "STAT_MEM4_RAMECC_PEND,Interrupt Pending Status for stat_mem4_ramecc_pend" "0,1"
bitfld.long 0x04 15. "STAT_MEM3_RAMECC_PEND,Interrupt Pending Status for stat_mem3_ramecc_pend" "0,1"
bitfld.long 0x04 14. "STAT_MEM2_RAMECC_PEND,Interrupt Pending Status for stat_mem2_ramecc_pend" "0,1"
newline
bitfld.long 0x04 13. "STAT_MEM1_RAMECC_PEND,Interrupt Pending Status for stat_mem1_ramecc_pend" "0,1"
bitfld.long 0x04 12. "STAT_MEM0_RAMECC_PEND,Interrupt Pending Status for stat_mem0_ramecc_pend" "0,1"
bitfld.long 0x04 11. "H3A_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 10. "H3A_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 9. "LSC_RAMECC_PEND,Interrupt Pending Status for lsc_ramecc_pend" "0,1"
bitfld.long 0x04 8. "DPC_LUT_RAMECC_PEND,Interrupt Pending Status for dpc_lut_ramecc_pend" "0,1"
newline
bitfld.long 0x04 7. "WDR_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 6. "WDR_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 5. "LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 4. "LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x04 3. "LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for lut2_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 1. "LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for lut3_ram0_ramecc_pend" "0,1"
line.long 0x08 "VPAC_VISS_ECC_DED_STATUS_REG1,Interrupt Status Register 1"
bitfld.long 0x08 5. "EELUT_1_RAMECC_PEND,Interrupt Pending Status for eelut_1_ramecc_pend" "0,1"
bitfld.long 0x08 4. "EELUT_0_RAMECC_PEND,Interrupt Pending Status for eelut_0_ramecc_pend" "0,1"
bitfld.long 0x08 3. "LUT_1_RAMECC_PEND,Interrupt Pending Status for lut_1_ramecc_pend" "0,1"
newline
bitfld.long 0x08 2. "LUT_0_RAMECC_PEND,Interrupt Pending Status for lut_0_ramecc_pend" "0,1"
bitfld.long 0x08 1. "FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x08 0. "FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram0_ramecc_pend" "0,1"
group.long 0x180++0x07
line.long 0x00 "VPAC_VISS_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 21. "FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 20. "FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 19. "STAT_MEM7_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem7_ramecc_pend" "0,1"
bitfld.long 0x00 18. "STAT_MEM6_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem6_ramecc_pend" "0,1"
bitfld.long 0x00 17. "STAT_MEM5_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem5_ramecc_pend" "0,1"
newline
bitfld.long 0x00 16. "STAT_MEM4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem4_ramecc_pend" "0,1"
bitfld.long 0x00 15. "STAT_MEM3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem3_ramecc_pend" "0,1"
bitfld.long 0x00 14. "STAT_MEM2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem2_ramecc_pend" "0,1"
newline
bitfld.long 0x00 13. "STAT_MEM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem1_ramecc_pend" "0,1"
bitfld.long 0x00 12. "STAT_MEM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "H3A_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 10. "H3A_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 9. "LSC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lsc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "DPC_LUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_lut_ramecc_pend" "0,1"
newline
bitfld.long 0x00 7. "WDR_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 6. "WDR_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 5. "LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 4. "LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 3. "LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram0_ramecc_pend" "0,1"
line.long 0x04 "VPAC_VISS_ECC_DED_ENABLE_SET_REG1,Interrupt Enable Set Register 1"
bitfld.long 0x04 5. "EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_1_ramecc_pend" "0,1"
bitfld.long 0x04 4. "EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_0_ramecc_pend" "0,1"
bitfld.long 0x04 3. "LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram0_ramecc_pend" "0,1"
group.long 0x1C0++0x07
line.long 0x00 "VPAC_VISS_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 31. "FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 30. "FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 29. "FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram1_ramecc_pend" "0,1"
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bitfld.long 0x00 28. "FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 27. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 26. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 25. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 24. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 23. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 22. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 21. "FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 20. "FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 19. "STAT_MEM7_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem7_ramecc_pend" "0,1"
bitfld.long 0x00 18. "STAT_MEM6_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem6_ramecc_pend" "0,1"
bitfld.long 0x00 17. "STAT_MEM5_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem5_ramecc_pend" "0,1"
newline
bitfld.long 0x00 16. "STAT_MEM4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem4_ramecc_pend" "0,1"
bitfld.long 0x00 15. "STAT_MEM3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem3_ramecc_pend" "0,1"
bitfld.long 0x00 14. "STAT_MEM2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem2_ramecc_pend" "0,1"
newline
bitfld.long 0x00 13. "STAT_MEM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem1_ramecc_pend" "0,1"
bitfld.long 0x00 12. "STAT_MEM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "H3A_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 10. "H3A_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 9. "LSC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lsc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "DPC_LUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_lut_ramecc_pend" "0,1"
newline
bitfld.long 0x00 7. "WDR_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 6. "WDR_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 5. "LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 4. "LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram0_ramecc_pend" "0,1"
bitfld.long 0x00 3. "LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 1. "LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram0_ramecc_pend" "0,1"
line.long 0x04 "VPAC_VISS_ECC_DED_ENABLE_CLR_REG1,Interrupt Enable Clear Register 1"
bitfld.long 0x04 5. "EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_1_ramecc_pend" "0,1"
bitfld.long 0x04 4. "EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_0_ramecc_pend" "0,1"
bitfld.long 0x04 3. "LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 2. "LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram0_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "VPAC_VISS_ECC_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "VPAC_VISS_ECC_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "VPAC_VISS_ECC_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "VPAC_VISS_ECC_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "VPAC_VISS_FCP_CFA"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA"
base ad:0xF088000
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_CFA_LUT_y,The LUT table contains the information used to reduce the pixle width to 12 from 13-16 Offset = 00088000h + (y * 4h); where y = 0h to 13Fh"
hexmask.long.word 0x00 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1"
hexmask.long.word 0x00 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0"
group.long 0x1004++0x0B
line.long 0x00 "VISS_FCP_CFA_CFG_0,The Control Register controls the input width and height of the module"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,Height of the input image"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,Width of the input image"
line.long 0x04 "VISS_FCP_CFA_CFG_1,The Control Register identifies the bit width of the input image"
bitfld.long 0x04 11. "BYPASS_CORE3,Setting the ~ibypass_core3 bit will bypass filtering operation output = input" "0,1"
bitfld.long 0x04 10. "BYPASS_CORE2,Setting the ~ibypass_core2 bit will bypass filtering operation output = input" "0,1"
bitfld.long 0x04 9. "BYPASS_CORE1,Setting the ~ibypass_core1 bit will bypass filtering operation output = input" "0,1"
bitfld.long 0x04 8. "BYPASS_CORE0,Setting the ~ibypass_core0 bit will bypass filtering operation output = input" "0,1"
bitfld.long 0x04 5. "LUT_ENABLE," "0,1"
newline
bitfld.long 0x04 0.--4. "BITWIDTH,BitWidth of the input image values greater than 16 will be treated as 16 and values less than 12 will be treated as 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "VISS_FCP_CFA_COEF_j_k_l_m_N,Coefficients for a=core. b=dir. c=phase. d=row. column=e*2+1 and e*2 Offset = 0008900Ch + (j * 360h) + (k * 120h) + (l * 48h) + (m * Ch) + (n * 4h); where j = 0h to 3h. k = 0h to 2h. l = 0h to 3h. m = 0h to 5h. n = 0h to 2h"
hexmask.long.word 0x08 16.--24. 1. "COEF_1,Coefficient - e*2+1"
hexmask.long.word 0x08 0.--8. 1. "COEF_0,Coefficient - e*2"
group.long 0x1D8C++0x0B
line.long 0x00 "VISS_FCP_CFA_GRAD_CFG,Gradient configuration for all 4 cores"
bitfld.long 0x00 25.--26. "BLENDMODECORE3,Core-3 Blend (" "0,1,2,3"
bitfld.long 0x00 24. "BITMASKSELCORE3,Core-3 Bitmask Select (" "0,1"
bitfld.long 0x00 17.--18. "BLENDMODECORE2,Core-2 Blend (" "0,1,2,3"
bitfld.long 0x00 16. "BITMASKSELCORE2,Core-2 Bitmask Select (" "0,1"
bitfld.long 0x00 9.--10. "BLENDMODECORE1,Core-1 Blend (" "0,1,2,3"
newline
bitfld.long 0x00 8. "BITMASKSELCORE1,Core-1 Bitmask Select (" "0,1"
bitfld.long 0x00 1.--2. "BLENDMODECORE0,Core-0 Blend (" "0,1,2,3"
bitfld.long 0x00 0. "BITMASKSELCORE0,Core-0 Bitmask Select (" "0,1"
line.long 0x04 "VISS_FCP_CFA_SET0_GRAD_HZ,Gradient Bitfield selector. Set-0 for Horizontal"
hexmask.long.byte 0x04 24.--31. 1. "PHASE3,Bitfield selector for Phase-3"
hexmask.long.byte 0x04 16.--23. 1. "PHASE2,Bitfield selector for Phase-2"
hexmask.long.byte 0x04 8.--15. 1. "PHASE1,Bitfield selector for Phase-1"
hexmask.long.byte 0x04 0.--7. 1. "PHASE0,Bitfield selector for Phase-0"
line.long 0x08 "VISS_FCP_CFA_SET0_GRAD_VT,Gradient Bitfield selector. Set-0 for Vertical"
hexmask.long.byte 0x08 24.--31. 1. "PHASE3,Bitfield selector for Phase-3"
hexmask.long.byte 0x08 16.--23. 1. "PHASE2,Bitfield selector for Phase-2"
hexmask.long.byte 0x08 8.--15. 1. "PHASE1,Bitfield selector for Phase-1"
hexmask.long.byte 0x08 0.--7. 1. "PHASE0,Bitfield selector for Phase-0"
group.long 0x1DA0++0x07
line.long 0x00 "VISS_FCP_CFA_SET1_GRAD_HZ,Gradient Bitfield selector. Set-1 for Horizontal"
hexmask.long.byte 0x00 24.--31. 1. "PHASE3,Bitfield selector for Phase-3"
hexmask.long.byte 0x00 16.--23. 1. "PHASE2,Bitfield selector for Phase-2"
hexmask.long.byte 0x00 8.--15. 1. "PHASE1,Bitfield selector for Phase-1"
hexmask.long.byte 0x00 0.--7. 1. "PHASE0,Bitfield selector for Phase-0"
line.long 0x04 "VISS_FCP_CFA_SET1_GRAD_VT,Gradient Bitfield selector. Set-1 for Vertical"
hexmask.long.byte 0x04 24.--31. 1. "PHASE3,Bitfield selector for Phase-3"
hexmask.long.byte 0x04 16.--23. 1. "PHASE2,Bitfield selector for Phase-2"
hexmask.long.byte 0x04 8.--15. 1. "PHASE1,Bitfield selector for Phase-1"
hexmask.long.byte 0x04 0.--7. 1. "PHASE0,Bitfield selector for Phase-0"
group.long 0x1DB0++0x23
line.long 0x00 "VISS_FCP_CFA_SET0_THR0_1,Set0 Thr0_1 for H/V Grad difference"
hexmask.long.word 0x00 16.--31. 1. "THR_1,H/V Grad diff Threshold_1"
hexmask.long.word 0x00 0.--15. 1. "THR_0,H/V Grad diff Threshold_0"
line.long 0x04 "VISS_FCP_CFA_SET0_THR2_3,Set0 Thr2_3 for H/V Grad difference"
hexmask.long.word 0x04 16.--31. 1. "THR_3,H/V Grad diff Threshold_3"
hexmask.long.word 0x04 0.--15. 1. "THR_2,H/V Grad diff Threshold_2"
line.long 0x08 "VISS_FCP_CFA_SET0_THR4_5,Set0 Thr4_5 for H/V Grad difference"
hexmask.long.word 0x08 16.--31. 1. "THR_5,H/V Grad diff Threshold_5"
hexmask.long.word 0x08 0.--15. 1. "THR_4,H/V Grad diff Threshold_4"
line.long 0x0C "VISS_FCP_CFA_SET0_THR6,Set0 Thr6 for H/V Grad difference"
hexmask.long.word 0x0C 0.--15. 1. "THR_6,H/V Grad diff Threshold_6"
line.long 0x10 "VISS_FCP_CFA_SET1_THR0_1,Set1 Thr0_1 for H/V Grad difference"
hexmask.long.word 0x10 16.--31. 1. "THR_1,H/V Grad diff Threshold_1"
hexmask.long.word 0x10 0.--15. 1. "THR_0,H/V Grad diff Threshold_0"
line.long 0x14 "VISS_FCP_CFA_SET1_THR2_3,Set1 Thr2_3 for H/V Grad difference"
hexmask.long.word 0x14 16.--31. 1. "THR_3,H/V Grad diff Threshold_3"
hexmask.long.word 0x14 0.--15. 1. "THR_2,H/V Grad diff Threshold_2"
line.long 0x18 "VISS_FCP_CFA_SET1_THR4_5,Set1 Thr4_5 for H/V Grad difference"
hexmask.long.word 0x18 16.--31. 1. "THR_5,H/V Grad diff Threshold_5"
hexmask.long.word 0x18 0.--15. 1. "THR_4,H/V Grad diff Threshold_4"
line.long 0x1C "VISS_FCP_CFA_SET1_THR6,Set1 Thr6 for H/V Grad difference"
hexmask.long.word 0x1C 0.--15. 1. "THR_6,H/V Grad diff Threshold_6"
line.long 0x20 "VISS_FCP_CFA_INT_STATUS,Status/clear register for flexcfa interrupts"
bitfld.long 0x20 2. "CFA_MMR_ERR,status/clear for error writes to the FIR Filter MMRs during active frame causing potential frame corruption" "0,1"
bitfld.long 0x20 1. "CFA_PIX_ERR,status/clear for error on line array set when software accesses pixel array during active frame causing potential frame corruption" "0,1"
bitfld.long 0x20 0. "LUT_CFG_ERR,status/clear for error on LUT cfg set when software accesses LUT during active frame causing potential frame corruption" "0,1"
group.long 0x2000++0x0B
line.long 0x00 "VISS_FCP_CFA_DEBUG_CTL,Enable for different debug events"
bitfld.long 0x00 2. "SOF_EN,Enable for sof event" "0,1"
bitfld.long 0x00 1. "SOL_EN,Enable for sol event" "0,1"
bitfld.long 0x00 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1"
line.long 0x04 "VISS_FCP_CFA_DEBUG_STATUS,Set/Clear for debug events"
bitfld.long 0x04 2. "SOF_EVENT,Status/Clear for sof event write '1' to clear" "0,1"
bitfld.long 0x04 1. "SOL_EVENT,Status/Clear for sol event write '1' to clear" "0,1"
line.long 0x08 "VISS_FCP_CFA_LINE_SEL,Selector for which line memory is read or written"
bitfld.long 0x08 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array" "0,1,2,3,4,5,6,7"
group.long 0x4000++0x03
line.long 0x00 "VISS_FCP_CFA_PIXEL_RAM_y,The pixel RAM contains the array of 12 bit pixels stored and used by the CFA logic"
hexmask.long.word 0x00 16.--27. 1. "PIXEL_HI,The 12 bit pixel data for the selected line upper pixel 'n+1'"
hexmask.long.word 0x00 0.--11. 1. "PIXEL_LO,The 12 bit pixel data for the selected line lower pixel 'n'"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x1DA8)++0x03
line.long 0x00 "VISS_FCP_CFA_SET1_INTENSITY$1,Intensity Bitfield selector and shift for phase0/1"
bitfld.long 0x00 28.--30. "SHIFT_PH1,Intensity shift for Phase-1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--14. "SHIFT_PH0,Intensity shift for Phase-0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x1D98)++0x03
line.long 0x00 "VISS_FCP_CFA_SET0_INTENSITY$1,Intensity Bitfield selector and shift for phase0/1"
bitfld.long 0x00 28.--30. "SHIFT_PH1,Intensity shift for Phase-1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--14. "SHIFT_PH0,Intensity shift for Phase-0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
tree.end
tree "VPAC_VISS_FCP_EE"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE"
base ad:0xF0D0000
group.long 0x00++0x0F
line.long 0x00 "VISS_FCP_EE_EE_CFG_0,The Control Register controls the input width and height of the module"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,Height of the input image"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,Width of the input image"
line.long 0x04 "VISS_FCP_EE_EE_CFG_1,The CEE route config Register controls the routing of trafic through and around the EE"
bitfld.long 0x04 28. "YUV12_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv12 stream" "0,1"
bitfld.long 0x04 24. "YUV8_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv8 stream" "0,1"
bitfld.long 0x04 22. "EE_FE_MUX_SEL,Selects which data stream to pass through the EE block" "0,1"
bitfld.long 0x04 18.--19. "SHIFTLEFT_NUM,Sects the amount to shift left the incoming pixel to the EE block" "0,1,2,3"
bitfld.long 0x04 16.--17. "SHIFTRIGHT_NUM,Sects the amount to shift right the outgoing pixel from the EE block" "0,1,2,3"
bitfld.long 0x04 12. "LLSE12_MUX_SEL,Selects Luma stream for the yuv12 output" "0,1"
newline
bitfld.long 0x04 8. "CLSE12_MUX_SEL,Selects Chroma stream for the yuv12 output" "0,1"
bitfld.long 0x04 4. "LLSE8_MUX_SEL,Selects Luma stream for the yuv8 output" "0,1"
bitfld.long 0x04 0. "CLSE8_MUX_SEL,Selects Chroma stream for the yuv8 output" "0,1"
line.long 0x08 "VISS_FCP_EE_EE_ENABLE,The EE Enable register control the internal bypass of the EE block"
bitfld.long 0x08 0. "YEE_ENABLE,The EE Enable register control the internal bypass of the EE block" "0,1"
line.long 0x0C "VISS_FCP_EE_YEE_SHIFT,The YEE Shift register controls"
bitfld.long 0x0C 0.--5. "YEE_SHIFT,The YEE Shift register controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x40++0x1F
line.long 0x00 "VISS_FCP_EE_YEE_E_THR,"
hexmask.long.word 0x00 0.--9. 1. "YEE_E_THR,"
line.long 0x04 "VISS_FCP_EE_YEE_MERGESEL,The Merge selects the output that is added to the target pixel"
bitfld.long 0x04 0. "YEE_MERGESEL," "0,1"
line.long 0x08 "VISS_FCP_EE_YES_E_HAL,The Halo selects Halo reduction mode"
bitfld.long 0x08 0. "YES_E_HAL," "0,1"
line.long 0x0C "VISS_FCP_EE_YES_G_GAIN,"
hexmask.long.byte 0x0C 0.--7. 1. "YES_G_GAIN,The Gradient Gain"
line.long 0x10 "VISS_FCP_EE_YES_E_GAIN,"
hexmask.long.word 0x10 0.--11. 1. "YES_E_GAIN,The Band-pass filter gain"
line.long 0x14 "VISS_FCP_EE_YES_E_THR1,"
hexmask.long.word 0x14 0.--15. 1. "YES_E_THR1,The shrink threshold"
line.long 0x18 "VISS_FCP_EE_YES_E_THR2,"
hexmask.long.word 0x18 0.--9. 1. "YES_E_THR2,The clip threshold"
line.long 0x1C "VISS_FCP_EE_YES_G_OFT,"
hexmask.long.word 0x1C 0.--9. 1. "YES_G_OFT,The offset applied to the Gradient gain"
group.long 0x100++0x03
line.long 0x00 "VISS_FCP_EE_INT_STATUS,Status/clear register for flexee interrupts"
bitfld.long 0x00 3. "EE_HZ_ALIGN8,status/clear for EE horizontal aligner yuv8 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits" "0,1"
bitfld.long 0x00 2. "EE_HZ_ALIGN12,status/clear for EE horizontal aligner yuv12 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits" "0,1"
bitfld.long 0x00 1. "EE_PIX_ERR,status/clear for error on line array set when software accesses EE pixel array during active frame causing potential frame corruption" "0,1"
bitfld.long 0x00 0. "EELUT_CFG_ERR,status/clear for error on EE LUT cfg set when software accesses EE LUT during active frame causing potential frame corruption" "0,1"
group.long 0x1008++0x03
line.long 0x00 "VISS_FCP_EE_LINE_SEL,Selector for which line memory is read or written"
bitfld.long 0x00 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array" "0,1,2,3,4,5,6,7"
group.long 0x2000++0x03
line.long 0x00 "VISS_FCP_EE_EELUT_RAM_y,The host will program the EE LUT RAM so that the pixels are translated from 14 bit to 12 bit using LUT entries"
hexmask.long.word 0x00 16.--28. 1. "EELUT_ENTRY_HI,The lower EE LUT entry n+1"
hexmask.long.word 0x00 0.--12. 1. "EELUT_ENTRY_LO,The lower EE LUT entry n+0"
group.long 0x4000++0x03
line.long 0x00 "VISS_FCP_EE_PIXEL_RAM_y,The pixel RAM contains the array of 12 bit pixels stored and used by the CFA logic"
hexmask.long.word 0x00 16.--27. 1. "PIXEL_HI,The 12 bit pixel data for the selected line upper pixel 'n+1'"
hexmask.long.word 0x00 0.--11. 1. "PIXEL_LO,The 12 bit pixel data for the selected line lower pixel 'n'"
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x30)++0x03
line.long 0x00 "VISS_FCP_EE_YEE_COEF_R2_C$1,The YEE Coefficient Row x Column x defines"
hexmask.long.word 0x00 0.--9. 1. "YEE_COEF_R2_C0,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x20)++0x03
line.long 0x00 "VISS_FCP_EE_YEE_COEF_R1_C$1,The YEE Coefficient Row x Column x defines"
hexmask.long.word 0x00 0.--9. 1. "YEE_COEF_R1_C0,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x10)++0x03
line.long 0x00 "VISS_FCP_EE_YEE_COEF_R0_C$1,The YEE Coefficient Row x Column x defines"
hexmask.long.word 0x00 0.--9. 1. "YEE_COEF_R0_C0,"
repeat.end
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC"
base ad:0xF090000
group.long 0x00++0x6B
line.long 0x00 "VISS_FCP_FCC_CFG_0,The Control Register controls the input width and height of the module"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,Height of the input image"
rbitfld.long 0x00 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,Width of the input image"
line.long 0x04 "VISS_FCP_FCC_CFG_1,Configuration Register for top level data flow"
rbitfld.long 0x04 28.--31. "RSVD_3,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 27. "CHROMA_MODE,Mux for 422/420 (" "0,1"
bitfld.long 0x04 26. "MUXRGBHSV_MUX_V,Mux for V calculation (" "0,1"
bitfld.long 0x04 25. "MUXRGBHSV_H2,Mux for S/V calculation (" "0,1"
newline
bitfld.long 0x04 24. "MUXRGBHSV_H1,Mux for S/V calculation (" "0,1"
rbitfld.long 0x04 20.--23. "RSVD_2,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 18.--19. "S8B8OUTEN,'0': Disable All '1': S8 enable " "0,1,2,3"
bitfld.long 0x04 16.--17. "C8G8OUTEN,'0': Disable All '1': C8 enable " "0,1,2,3"
newline
bitfld.long 0x04 14.--15. "Y8R8OUTEN,'0': Disable all '1': Y8 enable " "0,1,2,3"
bitfld.long 0x04 12.--13. "C12OUTEN,'0': Disable all '1': C12 enable '2': C1 enable" "0,1,2,3"
bitfld.long 0x04 11. "Y12OUTEN,'0': Disable Y12 output '1': Enable Y12 output" "0,1"
rbitfld.long 0x04 7.--10. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 6. "MUXRGBHSV,Input Select for RGBHSV (" "0,1"
bitfld.long 0x04 4.--5. "MUXY8_OUT,Mux for Y-8 Output (" "0,1,2,3"
bitfld.long 0x04 2.--3. "MUXY12_OUT,Mux for Y-12 Output (" "0,1,2,3"
bitfld.long 0x04 0.--1. "MUXC1_4,Mux for selecting C input (" "0,1,2,3"
line.long 0x08 "VISS_FCP_FCC_CFG_2,Configuration Register-2"
hexmask.long.word 0x08 17.--31. 1. "RSVD_1,reserved"
bitfld.long 0x08 13.--16. "Y8INBITWIDTH,Bitwidth of input to 12to8 module (Y8) for shift(Program as 12 or lower)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 9.--12. "CONTRASTBITCLIP,Clip Value set as 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8. "CONTRASTEN," "0,1"
newline
rbitfld.long 0x08 7. "RSVD_0,reserved" "0,1"
bitfld.long 0x08 6. "HSVSATMODE," "0,1"
bitfld.long 0x08 4.--5. "HSVSATDIVMODE," "0,1,2,3"
bitfld.long 0x08 3. "SATLUTEN,'1':Use LUT '0':Use shift" "0,1"
newline
bitfld.long 0x08 2. "RGB8LUTEN,'1':Use LUT '0':Use shift" "0,1"
bitfld.long 0x08 1. "Y8LUTEN,'1':Use LUT '0':Use shift" "0,1"
bitfld.long 0x08 0. "C8LUTEN,'1':Use LUT '0':Use shift" "0,1"
line.long 0x0C "VISS_FCP_FCC_CFG_HIST_1,Configuration-1 Register for histogram"
rbitfld.long 0x0C 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0C 16.--28. 1. "HISTSTARTY,Y Start for Histogram ROI should be >= 1"
rbitfld.long 0x0C 15. "RSVD_0,reserved" "0,1"
bitfld.long 0x0C 14. "BANK,bank select for Histogram" "0,1"
newline
hexmask.long.word 0x0C 1.--13. 1. "HISTSTARTX,X Start for Histogram ROI should be even"
bitfld.long 0x0C 0. "HISTEN,Enable bit for histogram" "0,1"
line.long 0x10 "VISS_FCP_FCC_CFG_HIST_2,Configuration-2 Register for histogram"
rbitfld.long 0x10 29.--31. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x10 16.--28. 1. "HISTSIZEY,Y Size (Height) for Histogram ROI"
bitfld.long 0x10 13.--15. "HISTMODE,Histogram Mode(0:Col-0(R) 1:Col-1(G) 2:Col-2(B) 3:MuxC1_4 4:R+2G+B/4 )" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x10 0.--12. 1. "HISTSIZEX,X Size (Width) for Histogram ROI should be > 256 & even"
line.long 0x14 "VISS_FCP_FCC_CCM_W0_0_1,CCM Weights for Row0"
rbitfld.long 0x14 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 16.--27. 1. "W_1,Weight W_"
rbitfld.long 0x14 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--11. 1. "W_0,Weight W_"
line.long 0x18 "VISS_FCP_FCC_CCM_W0_2_3,CCM Weights for Row0"
rbitfld.long 0x18 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 16.--27. 1. "W_3,Weight W_"
rbitfld.long 0x18 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--11. 1. "W_2,Weight W_"
line.long 0x1C "VISS_FCP_FCC_CCM_OFFSET_0,CCM OFFSET for Row0"
hexmask.long.tbyte 0x1C 13.--31. 1. "RSVD_0,reserved"
hexmask.long.word 0x1C 0.--12. 1. "OFFSET_0,OFFSET_"
line.long 0x20 "VISS_FCP_FCC_CCM_W1_0_1,CCM Weights for Row1"
rbitfld.long 0x20 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 16.--27. 1. "W_1,Weight W_"
rbitfld.long 0x20 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--11. 1. "W_0,Weight W_"
line.long 0x24 "VISS_FCP_FCC_CCM_W1_2_3,CCM Weights for Row1"
rbitfld.long 0x24 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 16.--27. 1. "W_3,Weight W_"
rbitfld.long 0x24 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--11. 1. "W_2,Weight W_"
line.long 0x28 "VISS_FCP_FCC_CCM_OFFSET_1,CCM OFFSET for Row1"
hexmask.long.tbyte 0x28 13.--31. 1. "RSVD_0,reserved"
hexmask.long.word 0x28 0.--12. 1. "OFFSET_1,OFFSET_"
line.long 0x2C "VISS_FCP_FCC_CCM_W2_0_1,CCM Weights for Row2"
rbitfld.long 0x2C 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x2C 16.--27. 1. "W_1,Weight W_"
rbitfld.long 0x2C 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x2C 0.--11. 1. "W_0,Weight W_"
line.long 0x30 "VISS_FCP_FCC_CCM_W2_2_3,CCM Weights for Row2"
rbitfld.long 0x30 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 16.--27. 1. "W_3,Weight W_"
rbitfld.long 0x30 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--11. 1. "W_2,Weight W_"
line.long 0x34 "VISS_FCP_FCC_CCM_OFFSET_2,CCM OFFSET for Row2"
hexmask.long.tbyte 0x34 13.--31. 1. "RSVD_0,reserved"
hexmask.long.word 0x34 0.--12. 1. "OFFSET_2,OFFSET_"
line.long 0x38 "VISS_FCP_FCC_RGBYUV_W01,Weight/Offset for Row0"
rbitfld.long 0x38 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x38 16.--27. 1. "W_02,Weight W_"
rbitfld.long 0x38 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x38 0.--11. 1. "W_01,Weight W_"
line.long 0x3C "VISS_FCP_FCC_RGBYUV_W02,Weight/Offset for Row0"
rbitfld.long 0x3C 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x3C 16.--28. 1. "OFFSET_0,Offset_"
rbitfld.long 0x3C 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x3C 0.--11. 1. "W_03,Weight W_"
line.long 0x40 "VISS_FCP_FCC_RGBYUV_W11,Weight/Offset for Row1"
rbitfld.long 0x40 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x40 16.--27. 1. "W_12,Weight W_"
rbitfld.long 0x40 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x40 0.--11. 1. "W_11,Weight W_"
line.long 0x44 "VISS_FCP_FCC_RGBYUV_W12,Weight/Offset for Row1"
rbitfld.long 0x44 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x44 16.--28. 1. "OFFSET_1,Offset_"
rbitfld.long 0x44 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x44 0.--11. 1. "W_13,Weight W_"
line.long 0x48 "VISS_FCP_FCC_RGBYUV_W21,Weight/Offset for Row2"
rbitfld.long 0x48 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x48 16.--27. 1. "W_22,Weight W_"
rbitfld.long 0x48 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x48 0.--11. 1. "W_21,Weight W_"
line.long 0x4C "VISS_FCP_FCC_RGBYUV_W22,Weight/Offset for Row2"
rbitfld.long 0x4C 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4C 16.--28. 1. "OFFSET_2,Offset_"
rbitfld.long 0x4C 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x4C 0.--11. 1. "W_23,Weight W_"
line.long 0x50 "VISS_FCP_FCC_RGBHSV_W0,Weights 11/12 for V calculation"
rbitfld.long 0x50 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x50 16.--27. 1. "W12,Weight W12 (Signed 12b)"
rbitfld.long 0x50 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x50 0.--11. 1. "W11,Weight W11 (Signed 12b)"
line.long 0x54 "VISS_FCP_FCC_RGBHSV_W1,Weights13 and Offset_1 for V Calculation"
rbitfld.long 0x54 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x54 16.--28. 1. "OFFSET_1,Offset_1 (Signed 13b)"
rbitfld.long 0x54 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x54 0.--11. 1. "W13,Weight W13 (Signed 12b)"
line.long 0x58 "VISS_FCP_FCC_RGBHSV_WB_LINLOGTHR_1,Dynamic WB Thr limit"
rbitfld.long 0x58 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x58 16.--27. 1. "THR_1,THR_1 / G-Channel Thr (U 12b)"
rbitfld.long 0x58 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x58 0.--11. 1. "THR_0,THR_0 / R-Channel Thr (U 12b)"
line.long 0x5C "VISS_FCP_FCC_RGBHSV_WB_LINLOGTHR_2,Dynamic WB Thr limit and SatMinThr"
rbitfld.long 0x5C 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x5C 16.--27. 1. "SATMINTHR,Thr for comparing Min(RGB) limit"
rbitfld.long 0x5C 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x5C 0.--11. 1. "THR_2,THR_2 / B-Channel Thr (U 12b)"
line.long 0x60 "VISS_FCP_FCC_RGBHSV_OFF1,WB Offset for Saturation"
rbitfld.long 0x60 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x60 16.--27. 1. "OFFSET_2,Offset_2 (U 12b)"
rbitfld.long 0x60 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x60 0.--11. 1. "OFFSET_1,Offset-1 (U 12b)"
line.long 0x64 "VISS_FCP_FCC_RGBHSV_OFF2,WB Offsets for Saturation"
hexmask.long.tbyte 0x64 13.--31. 1. "RSVD_0,reserved"
hexmask.long.word 0x64 0.--11. 1. "OFFSET_3,Offset-3 (U 12b)"
line.long 0x68 "VISS_FCP_FCC_FLEXCC_INT_STATUS,Status/clear register for flexcc interrupts"
hexmask.long.tbyte 0x68 12.--31. 1. "RSVD_0,reserved"
bitfld.long 0x68 11. "HIST_READ_ERR,status/clear for histogram memory set when mem access has occurred to the first location but not to the last location during active frame implying that full histogram was not" "0,1"
bitfld.long 0x68 10. "LUT_12TO82_CFG_ERR,status/clear for 12to8_2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption" "0,1"
bitfld.long 0x68 9. "LUT_12TO81_CFG_ERR,status/clear for 12to8_1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption" "0,1"
newline
bitfld.long 0x68 8. "LUT_12TO80_CFG_ERR,status/clear for 12to8_0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption" "0,1"
bitfld.long 0x68 7. "CONTRAST2_CFG_ERR,status/clear for contrast2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption" "0,1"
bitfld.long 0x68 6. "CONTRAST1_CFG_ERR,status/clear for contrast1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption" "0,1"
bitfld.long 0x68 5. "CONTRAST0_CFG_ERR,status/clear for contrast0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption" "0,1"
newline
bitfld.long 0x68 4. "OVERFLOW_IF_S8B8,status/clear for overflow on s8b8 i/f set when fifo overflows causing frame corruption" "0,1"
bitfld.long 0x68 3. "OVERFLOW_IF_C8G8,status/clear for overflow on c8g8 i/f set when fifo overflows causing frame corruption" "0,1"
bitfld.long 0x68 2. "OVERFLOW_IF_Y8R8,status/clear for overflow on y8r8 i/f set when fifo overflows causing frame corruption" "0,1"
bitfld.long 0x68 1. "OVERFLOW_IF_UV12,status/clear for overflow on uv12 i/f set when fifo overflows causing frame corruption" "0,1"
newline
bitfld.long 0x68 0. "OVERFLOW_IF_Y12,status/clear for overflow on y12 i/f set when fifo overflows causing frame corruption" "0,1"
group.long 0x100++0x0B
line.long 0x00 "VISS_FCP_FCC_DEBUG_CTL,Enable for different debug events"
hexmask.long.tbyte 0x00 13.--31. 1. "RSVD_0,reserved"
bitfld.long 0x00 12. "FLEXCC_EOP_EN,Enable for flexcc eop" "0,1"
bitfld.long 0x00 11. "EOF_IF_S8B8_EN,Enable for eof on s8b8" "0,1"
bitfld.long 0x00 10. "EOL_IF_S8B8_EN,Enable for eol on s8b8" "0,1"
newline
bitfld.long 0x00 9. "EOF_IF_C8G8_EN,Enable for eof on c8g8" "0,1"
bitfld.long 0x00 8. "EOL_IF_C8G8_EN,Enable for eol on c8g8" "0,1"
bitfld.long 0x00 7. "EOF_IF_Y8R8_EN,Enable for eof on y8r8" "0,1"
bitfld.long 0x00 6. "EOL_IF_Y8R8_EN,Enable for eol on y8r8" "0,1"
newline
bitfld.long 0x00 5. "EOF_IF_UV12_EN,Enable for eof on uv12" "0,1"
bitfld.long 0x00 4. "EOL_IF_UV12_EN,Enable for eol on uv12" "0,1"
bitfld.long 0x00 3. "EOF_IF_Y12_EN,Enable for eof on y12" "0,1"
bitfld.long 0x00 2. "EOL_IF_Y12_EN,Enable for eol on y12" "0,1"
newline
bitfld.long 0x00 1. "STALL_EN,Enable for stall event" "0,1"
bitfld.long 0x00 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1"
line.long 0x04 "VISS_FCP_FCC_DEBUG_STATUS,Set/Clear for debug events"
hexmask.long.tbyte 0x04 13.--31. 1. "RSVD_0,reserved"
bitfld.long 0x04 12. "FLEXCC_EOP_EVENT,Status/Clear for flexcc eop write '1' to clear" "0,1"
bitfld.long 0x04 11. "EOF_IF_S8B8_EVENT,Status/Clear for eof on s8b8 write '1' to clear" "0,1"
bitfld.long 0x04 10. "EOL_IF_S8B8_EVENT,Status/Clear for eol on s8b8 write '1' to clear" "0,1"
newline
bitfld.long 0x04 9. "EOF_IF_C8G8_EVENT,Status/Clear for eof on c8g8 write '1' to clear" "0,1"
bitfld.long 0x04 8. "EOL_IF_C8G8_EVENT,Status/Clear for eol on c8g8 write '1' to clear" "0,1"
bitfld.long 0x04 7. "EOF_IF_Y8R8_EVENT,Status/Clear for eof on y8r8 write '1' to clear" "0,1"
bitfld.long 0x04 6. "EOL_IF_Y8R8_EVENT,Status/Clear for eol on y8r8 write '1' to clear" "0,1"
newline
bitfld.long 0x04 5. "EOF_IF_UV12_EVENT,Status/Clear for eof on uv12 write '1' to clear" "0,1"
bitfld.long 0x04 4. "EOL_IF_UV12_EVENT,Status/Clear for eol on uv12 write '1' to clear" "0,1"
bitfld.long 0x04 3. "EOF_IF_Y12_EVENT,Status/Clear for eof on y12 write '1' to clear" "0,1"
bitfld.long 0x04 2. "EOL_IF_Y12_EVENT,Status/Clear for eol on y12 write '1' to clear" "0,1"
newline
bitfld.long 0x04 1. "STALL_EVENT,Status/Clear for stall event write '1' to clear" "0,1"
rbitfld.long 0x04 0. "RSVD,reserved" "0,1"
line.long 0x08 "VISS_FCP_FCC_DEBUG_RAW,Set/Clear for debug RAW mode"
bitfld.long 0x08 0. "DBG_RAW_MODE,Enable debug RAW mode takes input from RAWFE and delivers to FlexCC as C" "0,1"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_C8G8"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8"
base ad:0xF092800
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LUT_C8G8_y,Memory for 12to8 LUT Offset = 00092800h + (y * 4h); where y = 0h to 100h"
hexmask.long.byte 0x00 24.--31. 1. "rsvd_1,reserved"
hexmask.long.byte 0x00 16.--23. 1. "LUT_1,Bank-1"
hexmask.long.byte 0x00 8.--15. 1. "rsvd_0,reserved"
hexmask.long.byte 0x00 0.--7. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_CONTRASTC1"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1"
base ad:0xF090800
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LUT_CONTRASTC1_y,Memory for contrast C1 Offset = 00090800h + (y * 4h); where y = 0h to 100h"
rbitfld.long 0x00 28.--31. "rsvd_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "LUT_1,Bank-1"
rbitfld.long 0x00 12.--15. "rsvd_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_CONTRASTC2"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2"
base ad:0xF091000
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LUT_CONTRASTC2_y,Memory for contrast C2 Offset = 00091000h + (y * 4h); where y = 0h to 100h"
rbitfld.long 0x00 28.--31. "rsvd_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "LUT_1,Bank-1"
rbitfld.long 0x00 12.--15. "rsvd_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_CONTRASTC3"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3"
base ad:0xF091800
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LUT_CONTRASTC3_y,Memory for contrast C3 Offset = 00091800h + (y * 4h); where y = 0h to 100h"
rbitfld.long 0x00 28.--31. "rsvd_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "LUT_1,Bank-1"
rbitfld.long 0x00 12.--15. "rsvd_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_HIST"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST"
base ad:0xF093800
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_HIST_y,Memory for Histogram Offset = 00093800h + (y * 4h); where y = 0h to FFh"
hexmask.long.word 0x00 20.--31. 1. "rsvd_0,reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "HIST_VAL,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_LINE"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE"
base ad:0xF098000
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LINE_MEM_y,Memory for 2 lines of yuv444to420 Offset = 00098000h + (y * 4h); where y = 0h to FFFh"
rbitfld.long 0x00 28.--31. "rsvd_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "LINE_1,Line-1"
rbitfld.long 0x00 12.--15. "rsvd_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "LINE_0,Line-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_S8B8"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8"
base ad:0xF093000
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LUT_S8B8_y,Memory for 12to8 LUT Offset = 00093000h + (y * 4h); where y = 0h to 100h"
hexmask.long.byte 0x00 24.--31. 1. "rsvd_1,reserved"
hexmask.long.byte 0x00 16.--23. 1. "LUT_1,Bank-1"
hexmask.long.byte 0x00 8.--15. 1. "rsvd_0,reserved"
hexmask.long.byte 0x00 0.--7. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_FCP_FCC_Y8R8"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8"
base ad:0xF092000
group.long 0x00++0x03
line.long 0x00 "VISS_FCP_LUT_Y8R8_y,Memory for 12to8 LUT Offset = 00092000h + (y * 4h); where y = 0h to 100h"
hexmask.long.byte 0x00 24.--31. 1. "rsvd_1,reserved"
hexmask.long.byte 0x00 16.--23. 1. "LUT_1,Bank-1"
hexmask.long.byte 0x00 8.--15. 1. "rsvd_0,reserved"
hexmask.long.byte 0x00 0.--7. 1. "LUT_0,Bank-0"
tree.end
tree.end
tree "VPAC_VISS_GLBCE_STATMEM"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM"
base ad:0xF084000
group.long 0x00++0x03
line.long 0x00 "VISS_GLBCE_STATMEM_y,odd and even banks are combined for one 32-bit access Offset = 00084000h + (y * 4h); where y = 0h to FFFh"
hexmask.long.word 0x00 16.--31. 1. "ODD,Odd bank"
hexmask.long.word 0x00 0.--15. 1. "EVEN,Even bank"
tree.end
tree.end
tree "VPAC_VISS_GLBCE_TOP"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE"
base ad:0xF083800
group.long 0x00++0x2B
line.long 0x00 "VISS_GLBCE_CFG,GLBCE Configuration Registers"
bitfld.long 0x00 0. "SWRST,Reserved for this version for HW" "0,1"
line.long 0x04 "VISS_GLBCE_MODE,GLBCE Mode Control register"
bitfld.long 0x04 0. "OST,One shot mode or continuous mode One shot mode turns itself off after each frame Note that this bit only controls the enable signal and does not revert the statistics to the default status To revert the cache content to the default status you either.." "0,1"
line.long 0x08 "VISS_GLBCE_CONTROL0,GLBCE Control Register 0 (control_0)"
rbitfld.long 0x08 4. "CCTL,Color Control [CCTL] - Enabling this processing will result in more accurate colors processing The color correction algorithm is required on gamma corrected sources It reduces the saturation in dark areas when they are being amplified and saturates.." "0,1"
newline
bitfld.long 0x08 3. "MB,Max Bayer Type- Use this bit to select the algorithm used for calculating intensity" "Algorithm 1,Algorithm 2 [Recommended]"
newline
bitfld.long 0x08 0. "ONOFF,GLBCE On/Off - This bit turns GLBCE processing ON and OFF When GLBCE is OFF the video data passes to the output without any changes Disabling GLBCE using this bit is equivalent to setting the Strength parameter to 0 Many internal modules run in.." "Disable GLBCE processing,Enable GLBCE processing"
line.long 0x0C "VISS_GLBCE_CONTROL1,Connected to iridix_control1 parameter in GLBCE Core"
hexmask.long.byte 0x0C 0.--7. 1. "CONTROL1,Connected Control1 port"
line.long 0x10 "VISS_GLBCE_BLACK_LEVEL,Black Level Register (black_level)"
hexmask.long.word 0x10 0.--15. 1. "VAL,The value stored in Black Level Port will be used as zero level for GLBCE processing in all unsigned data channels Data below Black level will not be processed and stay unchanged"
line.long 0x14 "VISS_GLBCE_WHITE_LEVEL,White Level Register (white_level)"
hexmask.long.word 0x14 0.--15. 1. "VAL,The value stored in White Level Port will be used as white level for GLBCE processing in all unsigned data channels Data above White level will not be processed and stay unchanged"
line.long 0x18 "VISS_GLBCE_VARIANCE,Affects the sensitivity of the transform to different areas of the image. and can be increased in order to emphasize small regions (e.g. faces)"
bitfld.long 0x18 4.--7. "VARIANCEINTENSITY,Variance Intensity - Sets the degree of sensitivity in the luminance domain Maximum Variance is 0xF and minimum Variance is 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "VARIANCESPACE,Variance Space - Sets the degree of spatial sensitivity of the algorithm As this parameter is made smaller the algorithm focuses on smaller regions within the image Maximum Variance is 0xF and minimum Variance is 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "VISS_GLBCE_LIMIT_AMPL,The parameters dark amplification limit bright amplification limit are used to restrict the luminance space in which GLBCE can adaptively generate tone curves for each pixel"
bitfld.long 0x1C 4.--7. "BRIGHTAMPLIFICATIONLIMIT,Bright amplification limit - The resultant tone curve cannot be lower than bright amplification limit line controlled by the bright amplification limit parameter See Chapter 4 of the spec document for more explanation Maximum.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 0.--3. "DARKAMPLIFICATIONLIMIT,Dark amplification limit - The resultant tone curve cannot be higher than dark amplification limit line controlled by the dark amplification limit parameter See Chapter 4 of the spec for more explanation Maximum limit is 0xF when.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "VISS_GLBCE_DITHER,Dithering Register (dither)"
bitfld.long 0x20 0.--2. "DITHER," "?,One least significant bit of the output signal..,Two bits are dithered,Three bits are dithered,Four bits are dithered All other values,?..."
line.long 0x24 "VISS_GLBCE_SLOPE_MAX,Slope Max Limit Register (slope_max)"
hexmask.long.byte 0x24 0.--7. 1. "SLOPEMAXLIMIT,Slope Max Limit - Slope Max Limit is used to restrict the slope of the tone-curve generated by GLBCE When Slope Max Limit parameter is set to 0xFF the tone curve slope generated by GLBCE is not limited [maximum slope 15] When this value is.."
line.long 0x28 "VISS_GLBCE_SLOPE_MIN,Slope Min Limit Register (slope_min)"
hexmask.long.byte 0x28 0.--7. 1. "SLOPEMINLIMIT,Slope Min Limit - Slope Min Limit is used to restrict the slope of the tone-curve generated by GLBCE When Slope Min Limit parameter is set to 0x00 the tone curve slope generated by GLBCE is not limited When this value is set to FF GLBCE.."
group.long 0xAC++0x1B
line.long 0x00 "VISS_GLBCE_LUT_FI_32,Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits"
hexmask.long.word 0x00 0.--15. 1. "VAL,Asymmetry LUT Entry"
line.long 0x04 "VISS_GLBCE_FORMAT_CONTROL_REG0,Data format port specifies the input data format so that the GLBCE core can process the different input data formats"
bitfld.long 0x04 0.--1. "DATAFORMAT,This value is reserved The color format is always RGB and this value should be fixed 0" "0,1,2,3"
line.long 0x08 "VISS_GLBCE_FORMAT_CONTROL_REG1,Control Reg1"
bitfld.long 0x08 7. "AUTOSIZE,This value is read only" "0,1"
newline
bitfld.long 0x08 6. "AUTOPOS,This value is read only" "0,1"
newline
bitfld.long 0x08 4.--5. "FCMODE,Field Correction Mode" "0,1,2,3"
newline
bitfld.long 0x08 1. "VSPOL,Vertical Sync Polarity This value is read only The SWITCH block always convert the polarity to rising edge active" "0,1"
newline
bitfld.long 0x08 0. "HSPOL,Horizontal Sync Polarity This value is read only The SWITCH block always convert the polarity to rising edge active" "0,1"
line.long 0x0C "VISS_GLBCE_FRAME_WIDTH,Frame Width is the number of pixels in an active line"
hexmask.long.word 0x0C 0.--15. 1. "VAL,Frame Width"
line.long 0x10 "VISS_GLBCE_FRAME_HEIGHT,Frame Height is the number of active lines in one field"
hexmask.long.word 0x10 0.--15. 1. "VAL,Frame Height"
line.long 0x14 "VISS_GLBCE_STRENGTH_IR,Strength (Strength of GLBCE) - This Port sets processing Strength"
hexmask.long.byte 0x14 0.--7. 1. "VAL,0x"
line.long 0x18 "VISS_GLBCE_PERCEPT_EN,Enable for GLBCE Perceptual LUT function"
bitfld.long 0x18 1. "FWD_EN,Forward Perceptual LUT enable" "0,1"
newline
bitfld.long 0x18 0. "REV_EN,Reverse Perceptual LUT enable[" "0,1"
group.long 0x1C8++0x03
line.long 0x00 "VISS_GLBCE_REV_PERCEPT_LUT_64,Reverse Perceptual LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
group.long 0x2CC++0x07
line.long 0x00 "VISS_GLBCE_FWD_PERCEPT_LUT_64,Forward Perception LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
line.long 0x04 "VISS_GLBCE_WDR_GAMMA_EN,WDR Gamma LUT Enable"
bitfld.long 0x04 0. "EN,Frontend WDR LUT enable" "0,1"
group.long 0x6D4++0x07
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_256,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
line.long 0x04 "VISS_GLBCE_TILE_OUT_POS,Tile processing signals"
hexmask.long.word 0x04 16.--31. 1. "TOP,Tile Top position"
newline
hexmask.long.word 0x04 0.--15. 1. "LEFT,Tile Left position"
group.long 0x6E0++0x03
line.long 0x00 "VISS_GLBCE_TILE_OUT_SIZE,Tile processing signals"
hexmask.long.word 0x00 16.--31. 1. "HEIGHT,Tile Height"
newline
hexmask.long.word 0x00 0.--15. 1. "WIDTH,Tile Width"
group.long 0x6E8++0x07
line.long 0x00 "VISS_GLBCE_TILE_CONTROL,Tile Processing Control register"
bitfld.long 0x00 4. "LAST,Last time" "0,1"
newline
bitfld.long 0x00 3. "COLLECTION_DISABLE,Statistics collection disable" "0,1"
newline
bitfld.long 0x00 2. "UPDATE_DSABLE,Statistics update disable" "0,1"
newline
bitfld.long 0x00 0. "ENABLE,Tile processing Enable" "0,1"
line.long 0x04 "VISS_GLBCE_OUTPUT_FLAGS,Tile status register"
hexmask.long.word 0x04 0.--15. 1. "TILE_STATUS,Tile Status"
repeat 16. (list 240. 241. 242. 243. 244. 245. 246. 247. 248. 249. 250. 251. 252. 253. 254. 255. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x694)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 224. 225. 226. 227. 228. 229. 230. 231. 232. 233. 234. 235. 236. 237. 238. 239. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x654)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 208. 209. 210. 211. 212. 213. 214. 215. 216. 217. 218. 219. 220. 221. 222. 223. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x614)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x5D4)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. 190. 191. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x594)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x554)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x514)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x4D4)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x494)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x454)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x414)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3D4)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x394)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x354)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x314)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2D4)++0x03
line.long 0x00 "VISS_GLBCE_WDR_GAMMA_LUT_$1,Frontend WDR LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x28C)++0x03
line.long 0x00 "VISS_GLBCE_FWD_PERCEPT_LUT_$1,Forward Perception LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x24C)++0x03
line.long 0x00 "VISS_GLBCE_FWD_PERCEPT_LUT_$1,Forward Perception LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x20C)++0x03
line.long 0x00 "VISS_GLBCE_FWD_PERCEPT_LUT_$1,Forward Perception LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1CC)++0x03
line.long 0x00 "VISS_GLBCE_FWD_PERCEPT_LUT_$1,Forward Perception LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x188)++0x03
line.long 0x00 "VISS_GLBCE_REV_PERCEPT_LUT_$1,Reverse Perceptual LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x148)++0x03
line.long 0x00 "VISS_GLBCE_REV_PERCEPT_LUT_$1,Reverse Perceptual LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x108)++0x03
line.long 0x00 "VISS_GLBCE_REV_PERCEPT_LUT_$1,Reverse Perceptual LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC8)++0x03
line.long 0x00 "VISS_GLBCE_REV_PERCEPT_LUT_$1,Reverse Perceptual LUT"
hexmask.long.word 0x00 0.--15. 1. "VAL,LUT Value"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x6C)++0x03
line.long 0x00 "VISS_GLBCE_LUT_FI_$1,Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits"
hexmask.long.word 0x00 0.--15. 1. "VAL,Asymmetry LUT Entry"
repeat.end
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C)++0x03
line.long 0x00 "VISS_GLBCE_LUT_FI_$1,Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits"
hexmask.long.word 0x00 0.--15. 1. "VAL,Asymmetry LUT Entry"
repeat.end
tree.end
tree.end
tree "VPAC_VISS_LSE"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP"
base ad:0xF080400
rgroup.long 0x00++0x1B
line.long 0x00 "VISS_LSE_STATUS_PARAM,The register returns the LSE compile configuration parameters"
bitfld.long 0x00 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3"
bitfld.long 0x00 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1"
bitfld.long 0x00 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1"
bitfld.long 0x00 23.--27. "CORE_OUT_DW,Core Output Channel Data Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1"
newline
bitfld.long 0x00 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1"
bitfld.long 0x00 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1"
bitfld.long 0x00 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--16. "CORE_DW,Core Input Data Bus Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3"
newline
bitfld.long 0x00 6.--9. "SL2_OUT_CH,Number of SL2 Output Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "VPORT_THR,Number of VPORT input enabled" "0,1"
bitfld.long 0x00 0.--1. "NTHR,Number of threads supported" "0,1,2,3"
line.long 0x04 "VISS_LSE_STATUS_ERROR,The register returns the LSE error status"
hexmask.long.word 0x04 16.--26. 1. "VPORT_IN_ERR,VPORT_CAL Input Error Status Protocol Errors [26] VS without HS [25] VE without HE [24] VS-VS (missing VE) Error [23] HS-HS (missing HE) Error [22] HE-HE (missing HS) Error [21] VE-VE (missing VS) Error Frame Size Errors [20] Frame Skipped.."
hexmask.long.byte 0x04 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status"
bitfld.long 0x04 0.--4. "VM_RD_ERR,VBUSM I/F Last Read Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "VISS_LSE_STATUS_IDLE_MODE,The register returns IDLE status of LSE VBUSM port and in/output"
bitfld.long 0x08 24. "LSE_OUT_H3A_CHAN,Output H3A Channel Status" "0,1"
bitfld.long 0x08 12.--16. "LSE_OUT_CHAN,Output Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 11. "VPORT_IN_CHAN,CAL I/F Vport Input Cahnnel Status" "0,1"
bitfld.long 0x08 4.--6. "LSE_IN_CHAN,Input Channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1"
newline
bitfld.long 0x08 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1"
line.long 0x0C "VISS_LSE_CFG_LSE,The register configures the LSE general hardware modes"
bitfld.long 0x0C 8. "PSA_EN,Test mode Output Channel Signature Generation Enable" "0,1"
bitfld.long 0x0C 5. "IN_CH_SYNC_MODE,Input Channel Transfer Sync Mode (applicable only for VISS)" "0,1"
bitfld.long 0x0C 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select" "0,1"
bitfld.long 0x0C 2.--3. "LOOPBACK_IN_CH_SEL,Loopback Input Channel Select (applicable only for VISS)" "0,1,2,3"
bitfld.long 0x0C 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode" "0,1"
newline
bitfld.long 0x0C 0. "LOOPBACK_EN,LSE loopback mode enable" "0,1"
line.long 0x10 "VISS_LSE_CFG,The SRC_CFG register configures the input channels for the processing thread"
hexmask.long.word 0x10 22.--31. 1. "VP_HBLNK_CNT,Number of HBlank Pixels to insert between active lines for internal vport interface to core"
bitfld.long 0x10 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment" "0,1"
bitfld.long 0x10 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel" "0,1,2,3"
bitfld.long 0x10 0.--1. "PIX_FMT_PW,Input Pixel Width Sel" "0,1,2,3"
line.long 0x14 "VISS_LSE_VPIN_CFG,The SRC_VPIN_CFG register configures the VPORT input channel for the processing thread"
bitfld.long 0x14 4. "VP_PROTOCOL_CHK,Vport Input Data Protocol Check Enable" "0,1"
bitfld.long 0x14 2.--3. "VPORT_PW,Vport Pixel Data Width Sel" "0,1,2,3"
bitfld.long 0x14 1. "VPORT_TWO_PIXEL,Number of pixels per vport cycles" "0,1"
bitfld.long 0x14 0. "VPORT_EN,vport_en" "0,1"
line.long 0x18 "VISS_LSE_FRAME_SIZE,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread"
hexmask.long.word 0x18 16.--28. 1. "HEIGHT,SL"
hexmask.long.word 0x18 0.--12. 1. "WIDTH,SL"
group.long 0x20++0x03
line.long 0x00 "VISS_LSE_BUF_BA_y,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread"
bitfld.long 0x00 31. "ENABLE,Input Buffer Enable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x50++0x07
line.long 0x00 "VISS_LSE_BUF_CFG_j,The DST_BUF_CFG register configures the output buffer channel"
rbitfld.long 0x00 31. "CH_DISABLED,Channel Disable Status (read-only)" "0,1"
bitfld.long 0x00 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection" "0,1"
bitfld.long 0x00 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable" "0,1"
bitfld.long 0x00 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment" "0,1"
bitfld.long 0x00 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "PIX_FMT_PW,Output Pixel Width Sel" "0,1,2,3"
line.long 0x04 "VISS_LSE_BUF_ATTR0_j,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer"
hexmask.long.byte 0x04 25.--31. 1. "LOUT_SKIP_INIT,Line Out Initial Skip Count - The number of initial HTS tstart/tdone cycles with no output from the core on this output channel"
hexmask.long.word 0x04 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x04 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x04 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5C++0x03
line.long 0x00 "VISS_LSE_BUF_BA_j,The DST_BUF_BA register configures the base address of the output SL2 circular buffer"
bitfld.long 0x00 31. "ENABLE,Output Channel Enable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF0++0x03
line.long 0x00 "VISS_LSE_BUF_ATTR,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread"
hexmask.long.word 0x00 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)"
hexmask.long.word 0x00 6.--15. 1. "BUF_STRIDE,Buffer Stride Size"
rbitfld.long 0x00 0.--5. "BUF_STRIDE_6_LSB,Buffer Stride Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8++0x03
line.long 0x00 "VISS_LSE_BUF_BA,The H3A_BUF_BA register configures the base address of the H3A output SL2 circular buffer"
bitfld.long 0x00 31. "ENABLE,Output H3A Buffer Enable" "0,1"
hexmask.long.tbyte 0x00 6.--23. 1. "ADDR,Base Address"
rbitfld.long 0x00 0.--5. "ADDR_6_LSB,Base Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x140++0x03
line.long 0x00 "VISS_LSE_PSA_SIGNATURE_y,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]"
rgroup.long 0x1E0++0x03
line.long 0x00 "VISS_LSE_DBG_y,The DBG register returns the current status of internal FSM - TI internal use only"
tree.end
tree.end
tree "VPAC_VISS_NSF4V"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE"
base ad:0xF0C0000
group.long 0x04++0x13
line.long 0x00 "VISS_NSF4V_DBG,Diagnostic Register Control"
bitfld.long 0x00 0.--5. "RAM_MUX_CFG,Diagnostic Rd Wr access to Embedded RAM Selector Mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VISS_NSF4V_CTRL,All modes are set here"
bitfld.long 0x04 12. "LSCC_EN_CFG,enable Lens Shading Correction Compensation" "0,1"
bitfld.long 0x04 8.--11. "LSCC_SETSEL_CFG,bit per BAYER color component indicating which of two sets of 16 segment PWL Curve to use for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4. "TN_MODE_CFG,single bit controlling T_n calculation" "0,1"
bitfld.long 0x04 0.--3. "U_MODE_CFG,bit per BAYER color component indicating Decomp sub component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "VISS_NSF4V_DIM,Input Output Frame dimensions in units of pixels"
hexmask.long.word 0x08 16.--28. 1. "IH_CFG,(U13) input height in units of pixels minus 1"
hexmask.long.word 0x08 0.--12. 1. "IW_CFG,(U13) input width in units of pixels minus 1"
line.long 0x0C "VISS_NSF4V_LSCC,Lens Shading Correction Compensation"
hexmask.long.word 0x0C 20.--28. 1. "GMAX_CFG,(U4.5)"
bitfld.long 0x0C 16.--19. "T_CFG,(U4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x0C 8.--15. 1. "KV_CFG,(U2.6)"
hexmask.long.byte 0x0C 0.--7. 1. "KH_CFG,(U2.6)"
line.long 0x10 "VISS_NSF4V_LSCC_CENT,Lens Shading Correction Compensation"
hexmask.long.word 0x10 16.--29. 1. "Y_CFG,(S14) Vertical (Y) position of lens center"
hexmask.long.word 0x10 0.--13. 1. "X_CFG,(S14) Horizontal (X) position of lens center"
group.long 0x1C++0x0F
line.long 0x00 "VISS_NSF4V_TN_SCALE,Tn scaling factor multiplied by all 4 color components Tn after 12 segment PWL"
hexmask.long.byte 0x00 16.--23. 1. "TN3_CFG,(U3.5) Level3"
hexmask.long.byte 0x00 8.--15. 1. "TN2_CFG,(U3.5) Level2"
hexmask.long.byte 0x00 0.--7. 1. "TN1_CFG,(U3.5) Level1"
line.long 0x04 "VISS_NSF4V_U_KNEE,U suppression curve knee"
bitfld.long 0x04 0.--5. "U_KNEE_CFG,(U0.6) U Suppress curve knee" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "VISS_NSF4V_WHITEBAL0,White Balance Gain (Part0)"
hexmask.long.word 0x08 16.--28. 1. "GAIN1_CFG,(U4.9) Gain for color 1"
hexmask.long.word 0x08 0.--12. 1. "GAIN0_CFG,(U4.9) Gain for color 0"
line.long 0x0C "VISS_NSF4V_WHITEBAL1,White Balance Gain (Part1)"
hexmask.long.word 0x0C 16.--28. 1. "GAIN3_CFG,(U4.9) Gain for color 3"
hexmask.long.word 0x0C 0.--12. 1. "GAIN2_CFG,(U4.9) Gain for color 2"
group.long 0x60++0x07
line.long 0x00 "VISS_NSF4V_TN0_j_k,T_n 12 segment piecewise linear curve Part0 (4 color x 12 segment) Offset = 000C0060h + (j * 60h) + (k * 8h); where j = 0h to 3h. k = 0h to Bh"
hexmask.long.word 0x00 16.--30. 1. "Y_CFG,(U15) Y (U) value"
hexmask.long.word 0x00 0.--15. 1. "X_CFG,(U16) X (LL2) value"
line.long 0x04 "VISS_NSF4V_TN1_j_k,T_n 12 segment piecewise linear curve Part1 (4 color x 12 segment) Offset = 000C0064h + (j * 60h) + (k * 8h); where j = 0h to 3h. k = 0h to Bh"
hexmask.long.word 0x04 0.--15. 1. "S_CFG,(S5.11) S value"
group.long 0x200++0x07
line.long 0x00 "VISS_NSF4V_LSCCCURVE0_j_k,16 segment piecewise linear curve Part0 (2 set x 16 segment) Offset = 000C0200h + (j * 80h) + (k * 8h); where j = 0h to 1h. k = 0h to Fh"
hexmask.long.word 0x00 16.--24. 1. "Y_CFG,(U15.0) Y (U) value"
hexmask.long.word 0x00 0.--15. 1. "X_CFG,(U16) X (normalized radius from center) value"
line.long 0x04 "VISS_NSF4V_LSCCCURVE1_j_k,16 segment piecewise linear curve Part1 (2 set x 16 segment) Offset = 000C0204h + (j * 80h) + (k * 8h); where j = 0h to 1h. k = 0h to Fh"
hexmask.long.word 0x04 16.--31. 1. "RSVD,Reserved"
hexmask.long.word 0x04 0.--15. 1. "S_CFG,(S5.11) S value"
tree.end
tree.end
tree "VPAC_VISS_NSF4V_RAM"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM"
base ad:0xF0C4000
group.long 0x00++0x03
line.long 0x00 "VISS_NSF4V_DBG_MEM_y,Warning: reading or writing this MMR during operation will corrupt processing resulting in bad output data and will result in error interrupt firing"
tree.end
tree.end
tree "VPAC_VISS_RAWFE"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG"
base ad:0xF0A0000
group.long 0x00++0x2F
line.long 0x00 "VISS_RAWFE_IMAGE_CFG,Input image width and height"
rbitfld.long 0x00 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--28. 1. "HEIGHT,image height"
rbitfld.long 0x00 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--12. 1. "WIDTH,image width"
line.long 0x04 "VISS_RAWFE_SHADOW_CFG,shadow configuration"
bitfld.long 0x04 0. "LUT3_SHDW_EN,use LUT2 ram as LUT table for LUT3 processing" "0,1"
line.long 0x08 "VISS_RAWFE_PWL1_MASK_SH,Long frame PWL mask and shift values"
hexmask.long.word 0x08 20.--31. 1. "RSVD,reserved"
bitfld.long 0x08 16.--19. "SHIFT,number of right shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--15. 1. "MASK,mask bit pattern"
line.long 0x0C "VISS_RAWFE_PWL1_EN,Long frame PWL enable"
hexmask.long 0x0C 1.--31. 1. "RSVD,reserved"
bitfld.long 0x0C 0. "ENABLE,enable" "0,1"
line.long 0x10 "VISS_RAWFE_PWL1_THRX12,Long frame PWL threshold X1 and X2 - Unsigned"
hexmask.long.word 0x10 16.--31. 1. "THR_X2,threshold X2"
hexmask.long.word 0x10 0.--15. 1. "THR_X1,threshold X1"
line.long 0x14 "VISS_RAWFE_PWL1_THRX3,Long frame PWL threshold X3 - Unsigned"
hexmask.long.word 0x14 16.--31. 1. "RSVD,reserved"
hexmask.long.word 0x14 0.--15. 1. "THR_X3,threshold X3"
line.long 0x18 "VISS_RAWFE_PWL1_THRY1,Long frame PWL threshold Y1 - Unsigned"
hexmask.long.byte 0x18 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x18 0.--23. 1. "THR_Y1,threshold Y1"
line.long 0x1C "VISS_RAWFE_PWL1_THRY2,Long frame PWL threshold Y2 - Unsigned"
hexmask.long.byte 0x1C 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x1C 0.--23. 1. "THR_Y2,threshold Y2"
line.long 0x20 "VISS_RAWFE_PWL1_THRY3,Long frame PWL threshold Y3 - Unsigned"
hexmask.long.byte 0x20 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x20 0.--23. 1. "THR_Y3,threshold Y3"
line.long 0x24 "VISS_RAWFE_PWL1_SLP12,Long frame PWL slope 1 and"
hexmask.long.word 0x24 16.--31. 1. "SLOPE_2,slope 2"
hexmask.long.word 0x24 0.--15. 1. "SLOPE_1,slope 1"
line.long 0x28 "VISS_RAWFE_PWL1_SLP34,Long frame PWL slope 3 and"
hexmask.long.word 0x28 16.--31. 1. "SLOPE_4,slope 4"
hexmask.long.word 0x28 0.--15. 1. "SLOPE_3,slope 3"
line.long 0x2C "VISS_RAWFE_PWL1_SLPSH_CLIP,Long frame PWL slope shift and clip"
hexmask.long.tbyte 0x2C 8.--31. 1. "CLIP,clip value"
hexmask.long.byte 0x2C 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 33"
group.long 0x40++0x43
line.long 0x00 "VISS_RAWFE_PWL1_WB_GAIN12,Long Frame white balance gain 1 and 2"
rbitfld.long 0x00 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01"
rbitfld.long 0x00 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00"
line.long 0x04 "VISS_RAWFE_PWL1_WB_GAIN34,Long Frame white balance gain 3 and 4"
rbitfld.long 0x04 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11"
rbitfld.long 0x04 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10"
line.long 0x08 "VISS_RAWFE_PWL1_LUT,Long frame PWL LUT configuration"
hexmask.long 0x08 6.--31. 1. "RSVD,reserved"
bitfld.long 0x08 1.--5. "LUT_BITS,LUT input bit depth up to 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0. "LUT_EN,enable LUT based compression" "0,1"
line.long 0x0C "VISS_RAWFE_PWL1_LUTCLIP,Long frame PWL LUT output clip value"
hexmask.long.word 0x0C 16.--31. 1. "RSVD,reserved"
hexmask.long.word 0x0C 0.--15. 1. "LUTCLIP,LUT clip value"
line.long 0x10 "VISS_RAWFE_PWL2_MASK_SH,Short frame PWL mask and shift values"
hexmask.long.word 0x10 20.--31. 1. "RSVD,reserved"
bitfld.long 0x10 16.--19. "SHIFT,number of right shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 0.--15. 1. "MASK,mask bit pattern"
line.long 0x14 "VISS_RAWFE_PWL2_EN,Short frame PWL enable"
hexmask.long 0x14 1.--31. 1. "RSVD,reserved"
bitfld.long 0x14 0. "ENABLE,enable" "0,1"
line.long 0x18 "VISS_RAWFE_PWL2_THRX12,Short frame PWL threshold X1 and X2 - Unsigned"
hexmask.long.word 0x18 16.--31. 1. "THR_X2,threshold X2"
hexmask.long.word 0x18 0.--15. 1. "THR_X1,threshold X1"
line.long 0x1C "VISS_RAWFE_PWL2_THRX3,Short frame PWL threshold X3 - Unsigned"
hexmask.long.word 0x1C 16.--31. 1. "RSVD,reserved"
hexmask.long.word 0x1C 0.--15. 1. "THR_X3,threshold X3"
line.long 0x20 "VISS_RAWFE_PWL2_THRY1,Short frame PWL threshold Y1 - Unsigned"
hexmask.long.byte 0x20 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x20 0.--23. 1. "THR_Y1,threshold Y1"
line.long 0x24 "VISS_RAWFE_PWL2_THRY2,Short frame PWL threshold Y2 - Unsigned"
hexmask.long.byte 0x24 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "THR_Y2,threshold Y2"
line.long 0x28 "VISS_RAWFE_PWL2_THRY3,Short frame PWL threshold Y3 - Unsigned"
hexmask.long.byte 0x28 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x28 0.--23. 1. "THR_Y3,threshold Y3"
line.long 0x2C "VISS_RAWFE_PWL2_SLP12,Short frame PWL slope 1 and"
hexmask.long.word 0x2C 16.--31. 1. "SLOPE_2,slope 2"
hexmask.long.word 0x2C 0.--15. 1. "SLOPE_1,slope 1"
line.long 0x30 "VISS_RAWFE_PWL2_SLP34,Short frame PWL slope 3 and"
hexmask.long.word 0x30 16.--31. 1. "SLOPE_4,slope 4"
hexmask.long.word 0x30 0.--15. 1. "SLOPE_3,slope 3"
line.long 0x34 "VISS_RAWFE_PWL2_SLPSH_CLIP,Short frame PWL slope shift and clip"
hexmask.long.tbyte 0x34 8.--31. 1. "CLIP,clip value"
hexmask.long.byte 0x34 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 33"
line.long 0x38 "VISS_RAWFE_PWL2_LUT,Short frame PWL LUT configuration"
hexmask.long 0x38 6.--31. 1. "RSVD,reserved"
bitfld.long 0x38 1.--5. "LUT_BITS,LUT input bit depth up to 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 0. "LUT_EN,enable LUT based compression" "0,1"
line.long 0x3C "VISS_RAWFE_PWL2_LUTCLIP,Short frame PWL LUT output clip value"
hexmask.long.word 0x3C 16.--31. 1. "RSVD,reserved"
hexmask.long.word 0x3C 0.--15. 1. "LUTCLIP,LUT clip value"
line.long 0x40 "VISS_RAWFE_PWL2_OFF1,Short frame WB Offset 1"
hexmask.long.byte 0x40 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x40 0.--23. 1. "OFST00,S24 WB Offset at pixel 00"
group.long 0x90++0x37
line.long 0x00 "VISS_RAWFE_PWL2_WB_GAIN12,Short Frame white balance gain 1 and 2"
rbitfld.long 0x00 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01"
rbitfld.long 0x00 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00"
line.long 0x04 "VISS_RAWFE_PWL2_WB_GAIN34,Short Frame white balance gain 3 and 4"
rbitfld.long 0x04 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11"
rbitfld.long 0x04 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10"
line.long 0x08 "VISS_RAWFE_PWL3_MASK_SH,Very short frame PWL mask and shift values"
hexmask.long.word 0x08 20.--31. 1. "RSVD,reserved"
bitfld.long 0x08 16.--19. "SHIFT,number of right shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--15. 1. "MASK,mask bit pattern"
line.long 0x0C "VISS_RAWFE_PWL3_EN,Very short frame PWL enable"
hexmask.long 0x0C 1.--31. 1. "RSVD,reserved"
bitfld.long 0x0C 0. "ENABLE,enable" "0,1"
line.long 0x10 "VISS_RAWFE_PWL3_THRX12,Very short frame PWL threshold X1 and X2 - Unsigned"
hexmask.long.word 0x10 16.--31. 1. "THR_X2,threshold X2"
hexmask.long.word 0x10 0.--15. 1. "THR_X1,threshold X1"
line.long 0x14 "VISS_RAWFE_PWL3_THRX3,Very short frame PWL threshold X3 - Unsigned"
hexmask.long.word 0x14 16.--31. 1. "RSVD,reserved"
hexmask.long.word 0x14 0.--15. 1. "THR_X3,threshold X3"
line.long 0x18 "VISS_RAWFE_PWL3_THRY1,Very short frame PWL threshold Y1 - Unsigned"
hexmask.long.byte 0x18 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x18 0.--23. 1. "THR_Y1,threshold Y1"
line.long 0x1C "VISS_RAWFE_PWL3_THRY2,Very short frame PWL threshold Y2 - Unsigned"
hexmask.long.byte 0x1C 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x1C 0.--23. 1. "THR_Y2,threshold Y2"
line.long 0x20 "VISS_RAWFE_PWL3_THRY3,Very short frame PWL threshold Y3 - Unsigned"
hexmask.long.byte 0x20 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x20 0.--23. 1. "THR_Y3,threshold Y3"
line.long 0x24 "VISS_RAWFE_PWL3_SLP12,Very short frame PWL slope 1 and"
hexmask.long.word 0x24 16.--31. 1. "SLOPE_2,slope 2"
hexmask.long.word 0x24 0.--15. 1. "SLOPE_1,slope 1"
line.long 0x28 "VISS_RAWFE_PWL3_SLP34,Very short frame PWL slope 3 and"
hexmask.long.word 0x28 16.--31. 1. "SLOPE_4,slope 4"
hexmask.long.word 0x28 0.--15. 1. "SLOPE_3,slope 3"
line.long 0x2C "VISS_RAWFE_PWL3_SLPSH_CLIP,Very short frame PWL slope shift and clip"
hexmask.long.tbyte 0x2C 8.--31. 1. "CLIP,clip value"
hexmask.long.byte 0x2C 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 33"
line.long 0x30 "VISS_RAWFE_PWL3_LUT,Very short frame PWL LUT configuration"
hexmask.long 0x30 6.--31. 1. "RSVD,reserved"
bitfld.long 0x30 1.--5. "LUT_BITS,LUT input bit depth up to 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0. "LUT_EN,enable LUT based compression" "0,1"
line.long 0x34 "VISS_RAWFE_PWL3_LUTCLIP,Very short frame PWL LUT output clip value"
hexmask.long.word 0x34 16.--31. 1. "RSVD,reserved"
hexmask.long.word 0x34 0.--15. 1. "LUTCLIP,LUT clip value"
group.long 0xD8++0x83
line.long 0x00 "VISS_RAWFE_PWL3_WB_GAIN12,Very Short Frame white balance gain 1 and 2"
rbitfld.long 0x00 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01"
rbitfld.long 0x00 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00"
line.long 0x04 "VISS_RAWFE_PWL3_WB_GAIN34,Very Short Frame white balance gain 3 and 4"
rbitfld.long 0x04 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11"
rbitfld.long 0x04 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10"
line.long 0x08 "VISS_RAWFE_WDRMRG1_CFG,First stage WDR merge configuration"
hexmask.long.tbyte 0x08 15.--31. 1. "RSVD,reserved"
bitfld.long 0x08 14. "CFG_WGT_SEL,Select source for weight calculation (" "0,1"
bitfld.long 0x08 10.--13. "CFG_SBIT,U4 short exposure image bit shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 6.--9. "CFG_LBIT,U4 long exposure image bit shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 1.--5. "CFG_DST,U5 down shift value after WDR merge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0. "CFG_EN,enable" "0,1"
line.long 0x0C "VISS_RAWFE_WDRMRG1_GAIN,First stage WDR merge gain"
hexmask.long.word 0x0C 16.--31. 1. "GSHORT,U16Q15 gain for long frame"
hexmask.long.word 0x0C 0.--15. 1. "GLONG,U16Q15 gain for short frame"
line.long 0x10 "VISS_RAWFE_WDRMRG1_LBLK12,First stage WDR merge black level 1 and 2 for long frame"
rbitfld.long 0x10 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 16.--27. 1. "LBK01,U12 black level for long frame at pixel 01"
rbitfld.long 0x10 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 0.--11. 1. "LBK00,U12 black level for long frame at pixel 00"
line.long 0x14 "VISS_RAWFE_WDRMRG1_LBLK34,First stage WDR merge black level 3 and 4 for long frame"
rbitfld.long 0x14 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 16.--27. 1. "LBK11,U12 black level for long frame at pixel 11"
rbitfld.long 0x14 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--11. 1. "LBK10,U12 black level for long frame at pixel 10"
line.long 0x18 "VISS_RAWFE_WDRMRG1_SBLK12,First stage WDR merge black level 1 and 2 for short frame"
rbitfld.long 0x18 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 16.--27. 1. "SBK01,U12 black level for short frame at pixel 01"
rbitfld.long 0x18 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--11. 1. "SBK00,U12 black level for short frame at pixel 00"
line.long 0x1C "VISS_RAWFE_WDRMRG1_SBLK34,First stage WDR merge black level 3 and 4 for short frame"
rbitfld.long 0x1C 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 16.--27. 1. "SBK11,U12 black level for short frame at pixel 11"
rbitfld.long 0x1C 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--11. 1. "SBK10,U12 black level for short frame at pixel 10"
line.long 0x20 "VISS_RAWFE_WDRMRG1_LWB12,First stage WDR merge WB gain 1 and 2 for long frame"
rbitfld.long 0x20 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x20 16.--28. 1. "WB01,U13Q9 WB gain for long frame at pixel 01"
rbitfld.long 0x20 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x20 0.--12. 1. "WB00,U13Q9 WB gain for long frame at pixel 00"
line.long 0x24 "VISS_RAWFE_WDRMRG1_LWB34,First stage WDR merge WB gain 3 and 4 for long frame"
rbitfld.long 0x24 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x24 16.--28. 1. "WB11,U13Q9 WB gain for long frame at pixel 11"
rbitfld.long 0x24 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x24 0.--12. 1. "WB10,U13Q9 WB gain for long frame at pixel 10"
line.long 0x28 "VISS_RAWFE_WDRMRG1_SWB12,First stage WDR merge WB gain 1 and 2 for short frame"
rbitfld.long 0x28 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x28 16.--28. 1. "WB01,U13Q9 WB gain for short frame at pixel 01"
rbitfld.long 0x28 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x28 0.--12. 1. "WB00,U13Q9 WB gain for short frame at pixel 00"
line.long 0x2C "VISS_RAWFE_WDRMRG1_SWB34,First stage WDR merge WB gain 3 and 4 for short frame"
rbitfld.long 0x2C 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x2C 16.--28. 1. "WB11,U13Q9 WB gain for short frame at pixel 11"
rbitfld.long 0x2C 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x2C 0.--12. 1. "WB10,U13Q9 WB gain for short frame at pixel 10"
line.long 0x30 "VISS_RAWFE_WDRMRG1_WDRTHR_BF,First stage WDR merge parameter WDRTHR and BF"
hexmask.long.word 0x30 16.--31. 1. "BF,S16 bf parameter for merge"
hexmask.long.word 0x30 0.--15. 1. "WDRTHR,U16 WDR threshold for merge"
line.long 0x34 "VISS_RAWFE_WDRMRG1_AF,First stage WDR merge parameter AF"
hexmask.long.word 0x34 22.--31. 1. "RSVD,reserved"
bitfld.long 0x34 16.--21. "AFE,U6 af_e parameter for merge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x34 0.--15. 1. "AFM,S16 af_m parameter for merge"
line.long 0x38 "VISS_RAWFE_WDRMRG1_MA,First stage WDR merge parameter MA"
hexmask.long.word 0x38 16.--31. 1. "MAS,U16 slope for merge MA filter"
hexmask.long.word 0x38 0.--15. 1. "MAD,U16 lower threshold for merge MA filter"
line.long 0x3C "VISS_RAWFE_WDRMRG1_CLIP_SFT,First stage WDR merge clip value and shift before weight block"
hexmask.long.word 0x3C 23.--31. 1. "RSVD,reserved"
bitfld.long 0x3C 20.--22. "WTSFT,U3 shift before weight block" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x3C 0.--19. 1. "CLIP,U20 output clip value"
line.long 0x40 "VISS_RAWFE_WDRMRG2_CFG,Second stage WDR merge configuration"
hexmask.long.tbyte 0x40 15.--31. 1. "RSVD,reserved"
bitfld.long 0x40 14. "CFG_WGT_SEL,Select source for weight calculation (" "0,1"
bitfld.long 0x40 10.--13. "CFG_SBIT,U4 short exposure image bit shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x40 6.--9. "CFG_LBIT,U4 long exposure image bit shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x40 1.--5. "CFG_DST,U5 down shift value after WDR merge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 0. "CFG_EN,enable" "0,1"
line.long 0x44 "VISS_RAWFE_WDRMRG2_GAIN,Second stage WDR merge gain"
hexmask.long.word 0x44 16.--31. 1. "GSHORT,U16Q15 gain for long frame"
hexmask.long.word 0x44 0.--15. 1. "GLONG,U16Q15 gain for short frame"
line.long 0x48 "VISS_RAWFE_WDRMRG2_LBLK12,Second stage WDR merge black level 1 and 2 for long frame"
rbitfld.long 0x48 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x48 16.--27. 1. "LBK01,U12 black level for long frame at pixel 01"
rbitfld.long 0x48 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x48 0.--11. 1. "LBK00,U12 black level for long frame at pixel 00"
line.long 0x4C "VISS_RAWFE_WDRMRG2_LBLK34,Second stage WDR merge black level 3 and 4 for long frame"
rbitfld.long 0x4C 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x4C 16.--27. 1. "LBK11,U12 black level for long frame at pixel 11"
rbitfld.long 0x4C 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x4C 0.--11. 1. "LBK10,U12 black level for long frame at pixel 10"
line.long 0x50 "VISS_RAWFE_WDRMRG2_SBLK12,Second stage WDR merge black level 1 and 2 for short frame"
rbitfld.long 0x50 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x50 16.--27. 1. "SBK01,U12 black level for short frame at pixel 01"
rbitfld.long 0x50 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x50 0.--11. 1. "SBK00,U12 black level for short frame at pixel 00"
line.long 0x54 "VISS_RAWFE_WDRMRG2_SBLK34,Second stage WDR merge black level 3 and 4 for short frame"
rbitfld.long 0x54 28.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x54 16.--27. 1. "SBK11,U12 black level for short frame at pixel 11"
rbitfld.long 0x54 12.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x54 0.--11. 1. "SBK10,U12 black level for short frame at pixel 10"
line.long 0x58 "VISS_RAWFE_WDRMRG2_LWB12,Second stage WDR merge WB gain 1 and 2 for long frame"
rbitfld.long 0x58 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x58 16.--28. 1. "WB01,U13Q9 WB gain for long frame at pixel 01"
rbitfld.long 0x58 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x58 0.--12. 1. "WB00,U13Q9 WB gain for long frame at pixel 00"
line.long 0x5C "VISS_RAWFE_WDRMRG2_LWB34,Second stage WDR merge WB gain 3 and 4 for long frame"
rbitfld.long 0x5C 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x5C 16.--28. 1. "WB11,U13Q9 WB gain for long frame at pixel 11"
rbitfld.long 0x5C 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x5C 0.--12. 1. "WB10,U13Q9 WB gain for long frame at pixel 10"
line.long 0x60 "VISS_RAWFE_WDRMRG2_SWB12,Second stage WDR merge WB gain 1 and 2 for short frame"
rbitfld.long 0x60 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x60 16.--28. 1. "WB01,U13Q9 WB gain for short frame at pixel 01"
rbitfld.long 0x60 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x60 0.--12. 1. "WB00,U13Q9 WB gain for short frame at pixel 00"
line.long 0x64 "VISS_RAWFE_WDRMRG2_SWB34,Second stage WDR merge WB gain 3 and 4 for short frame"
rbitfld.long 0x64 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x64 16.--28. 1. "WB11,U13Q9 WB gain for short frame at pixel 11"
rbitfld.long 0x64 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x64 0.--12. 1. "WB10,U13Q9 WB gain for short frame at pixel 10"
line.long 0x68 "VISS_RAWFE_WDRMRG2_WDRTHR_BF,Second stage WDR merge parameter WDRTHR and BF"
hexmask.long.word 0x68 16.--31. 1. "BF,S16 bf parameter for merge"
hexmask.long.word 0x68 0.--15. 1. "WDRTHR,U16 WDR threshold for merge"
line.long 0x6C "VISS_RAWFE_WDRMRG2_AF,Second stage WDR merge parameter AF"
hexmask.long.word 0x6C 22.--31. 1. "RSVD,reserved"
bitfld.long 0x6C 16.--21. "AFE,U6 af_e parameter for merge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x6C 0.--15. 1. "AFM,S16 af_m parameter for merge"
line.long 0x70 "VISS_RAWFE_WDRMRG2_MA,Second stage WDR merge parameter MA"
hexmask.long.word 0x70 16.--31. 1. "MAS,U16 slope for merge MA filter"
hexmask.long.word 0x70 0.--15. 1. "MAD,U16 lower threshold for merge MA filter"
line.long 0x74 "VISS_RAWFE_WDRMRG2_CLIP_SFT,Second stage WDR merge clip value and shift before weight block"
hexmask.long.word 0x74 23.--31. 1. "RSVD,reserved"
bitfld.long 0x74 20.--22. "WTSFT,U3 shift before weight block" "0,1,2,3,4,5,6,7"
hexmask.long.tbyte 0x74 0.--19. 1. "CLIP,U20 output clip value"
line.long 0x78 "VISS_RAWFE_MRGLUT_CFG,Merge LUT configuration"
hexmask.long.word 0x78 16.--31. 1. "CLIP,U16 LUT output clip"
hexmask.long.word 0x78 6.--15. 1. "RSVD,reserved"
bitfld.long 0x78 1.--5. "BITS,U5 LUT input bit depth up to 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 0. "EN,LUT enable" "0,1"
line.long 0x7C "VISS_RAWFE_LUTDPC_CFG,LUTDPC configuration"
hexmask.long.tbyte 0x7C 10.--31. 1. "RSVD,reserved"
hexmask.long.byte 0x7C 2.--9. 1. "SIZE,U8 number of LUT entires - 1"
bitfld.long 0x7C 1. "SEL,replace with black (0) or whithe (1)" "0,1"
bitfld.long 0x7C 0. "EN,LUTDPC enable" "0,1"
line.long 0x80 "VISS_RAWFE_OTFDPC_EN,OTFDPC enable"
hexmask.long 0x80 1.--31. 1. "RSVD,reserved"
bitfld.long 0x80 0. "EN,OTF DPC enable" "0,1"
group.long 0x17C++0x1F
line.long 0x00 "VISS_RAWFE_LSC_CFG,LSC configuration"
hexmask.long.tbyte 0x00 10.--31. 1. "RSVD,reserved"
bitfld.long 0x00 7.--9. "GAIN_FORMAT,LSC LUT gain format " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "MODE_N,vertical LSC LUT downsampling " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1.--3. "MODE_M,horizontal LSC LUT downsampling " "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "EN,LSC enable" "0,1"
line.long 0x04 "VISS_RAWFE_WB2_OFFSET12,WB2 white balance offset 1 and 2"
hexmask.long.word 0x04 16.--31. 1. "WB_OFST01,S16 WB offset at pixel 01"
hexmask.long.word 0x04 0.--15. 1. "WB_OFST00,S16 WB offset at pixel 00"
line.long 0x08 "VISS_RAWFE_WB2_OFFSET34,WB2 white balance offset 3 and 4"
hexmask.long.word 0x08 16.--31. 1. "WB_OFST11,S16 WB offset at pixel 11"
hexmask.long.word 0x08 0.--15. 1. "WB_OFST10,S16 WB offset at pixel 10"
line.long 0x0C "VISS_RAWFE_WB2_GAIN12,WB2 white balance gain 1 and 2"
rbitfld.long 0x0C 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0C 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01"
rbitfld.long 0x0C 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0C 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00"
line.long 0x10 "VISS_RAWFE_WB2_GAIN34,WB2 white balance gain 3 and 4"
rbitfld.long 0x10 29.--31. "RSVD_1,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x10 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11"
rbitfld.long 0x10 13.--15. "RSVD_0,reserved" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x10 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10"
line.long 0x14 "VISS_RAWFE_H3AMUX_CFG,H3A MUX configuration"
hexmask.long 0x14 6.--31. 1. "RSVD,reserved"
bitfld.long 0x14 2.--5. "SHIFT,U8 number of right shift from 0 to 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "SEL,H3A input selection " "0,1,2,3"
line.long 0x18 "VISS_RAWFE_H3ALUT_CFG,H3A LUT configuration"
rbitfld.long 0x18 26.--31. "RSVD_2,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x18 16.--25. 1. "CLIP,U10 LUT output clip value"
hexmask.long.word 0x18 6.--15. 1. "RSVD,reserved"
bitfld.long 0x18 1.--5. "BITS,U5 LUT input bit depth up to 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 0. "EN,LUT enable" "0,1"
line.long 0x1C "VISS_RAWFE_INT_STAT,status/clear register for rawfe interrupts"
bitfld.long 0x1C 9. "LSC_CFG_ERR,status/clear for lsc config error" "0,1"
bitfld.long 0x1C 8. "DPC_LINE_CFG_ERR,status/clear for dpc line config error" "0,1"
bitfld.long 0x1C 7. "DPC_LUT_CFG_ERR,status/clear for dpc lut configuration error" "0,1"
bitfld.long 0x1C 6. "H3A_ACCM_CFG_ERR,status/clear for h3a accum configuration error" "0,1"
newline
bitfld.long 0x1C 5. "H3A_LINE_CFG_ERR,status/clear for h3a line configuration error" "0,1"
bitfld.long 0x1C 4. "H3A_LUT_CFG_ERR,status/clear for h3a lut configuration error" "0,1"
bitfld.long 0x1C 3. "WDR_LUT_CFG_ERR,status/clear for wdr lut configuration error" "0,1"
bitfld.long 0x1C 2. "LUT3_CFG_ERR,status/clear for lut3 configuration error" "0,1"
newline
bitfld.long 0x1C 1. "LUT2_CFG_ERR,status/clear for lut2 configuration error" "0,1"
bitfld.long 0x1C 0. "LUT1_CFG_ERR,status/clear for lut1 configuration error" "0,1"
group.long 0x200++0x17
line.long 0x00 "VISS_RAWFE_DBG_CTL,debug event and control register"
bitfld.long 0x00 12.--13. "DPC_LINE_SEL,select for which dpc line ram to read on debug interface" "0,1,2,3"
bitfld.long 0x00 11. "PIPE_ADV_EN_EVENT,enable for pixal pipe line advanced" "0,1"
bitfld.long 0x00 10. "DPC_OTF_CORR_EN_EVENT,enable for dpc otf corrected a pixel" "0,1"
bitfld.long 0x00 9. "LSE_INTF_STALL_EN_EVENT,enable for lse slave port stalled by rawfe" "0,1"
newline
bitfld.long 0x00 8. "LSE_MST_STALL_EN_EVENT,enable for lse maaster port stalled on H3A out I/F" "0,1"
bitfld.long 0x00 7. "LSE_SLV_STALL_EN_EVENT,enable for lse not sending data in frame on pixel I/F" "0,1"
bitfld.long 0x00 6. "HE_EN_EVENT,enable for horizantal end" "0,1"
bitfld.long 0x00 5. "HS_EN_EVENT,enable for horizantal start" "0,1"
newline
bitfld.long 0x00 4. "VE_EN_EVENT,enable for verticle end" "0,1"
bitfld.long 0x00 3. "VS_EN_EVENT,enable for verticle start" "0,1"
bitfld.long 0x00 2. "X_Y_EN_EVENT,enable for x y position match event" "0,1"
bitfld.long 0x00 1. "X_Y_EN_HALT,enable for x y position match halt" "0,1"
newline
bitfld.long 0x00 0. "DBG_EN,Enable debug features set to '0' to disable all events" "0,1"
line.long 0x04 "VISS_RAWFE_DBG_HWBP,x.y event for event matching"
hexmask.long.word 0x04 16.--28. 1. "Y_POS,pixel y position"
hexmask.long.word 0x04 0.--12. 1. "X_POS,pixel x position"
line.long 0x08 "VISS_RAWFE_DBG_STAT1,status/clear register for debug events"
bitfld.long 0x08 11. "PIPE_ADV_EVENT,status/clear for pixal pipe line advanced" "0,1"
bitfld.long 0x08 10. "DPC_OTF_CORR_EVENT,status/clear for dpc otf corrected a pixel" "0,1"
bitfld.long 0x08 9. "LSE_INTF_STALL_EVENT,status/clear for lse slave port stalled by rawfe" "0,1"
bitfld.long 0x08 8. "LSE_MST_STALL_EVENT,status/clear for lse maaster port stalled" "0,1"
newline
bitfld.long 0x08 7. "LSE_SLV_STALL_EVENT,status/clear for lse not sending data in frame" "0,1"
bitfld.long 0x08 6. "HE_EVENT,status/clear for horizantal end" "0,1"
bitfld.long 0x08 5. "HS_EVENT,status/clear for horizantal start" "0,1"
bitfld.long 0x08 4. "VE_EVENT,status/clear for verticle end" "0,1"
newline
bitfld.long 0x08 3. "VS_EVENT,status/clear for verticle start" "0,1"
bitfld.long 0x08 2. "X_Y_EVENT,status/clear for x y position match event" "0,1"
bitfld.long 0x08 1. "X_Y_HALT,status/clear for x y position match halt" "0,1"
line.long 0x0C "VISS_RAWFE_DBG_STAT2,current x.y position in frame"
hexmask.long.word 0x0C 16.--28. 1. "Y_POS,current y position"
hexmask.long.word 0x0C 0.--12. 1. "X_POS,current x position"
line.long 0x10 "VISS_RAWFE_DBG_STAT3,internal state status"
hexmask.long 0x10 2.--31. 1. "DPC_MIRROR_STAT,dpc mirror status"
bitfld.long 0x10 0.--1. "DPC_LINE_RAM_CTL,ram control for understanding the phase of DPC line rams circular buffer for debug reads" "0,1,2,3"
line.long 0x14 "VISS_RAWFE_DBG_STAT4,internal state status"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x15C)++0x03
line.long 0x00 "VISS_RAWFE_OTFDPC_THRSLP$1,OTFDPC threshold and slope 1"
rbitfld.long 0x00 28.--31. "RSVD,reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "SLP1,S12Q8 slope at 0"
newline
hexmask.long.word 0x00 0.--15. 1. "THR1,U16 threshold at 0"
repeat.end
repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xC8)++0x03
line.long 0x00 "VISS_RAWFE_PWL3_OFF$1,Very Short frame Offset 1"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "OFST00,S24 Offset at pixel 00"
repeat.end
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x84)++0x03
line.long 0x00 "VISS_RAWFE_PWL2_OFF$1,Short frame Offset 2"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "OFST01,S24 Offset at pixel 01"
repeat.end
repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x30)++0x03
line.long 0x00 "VISS_RAWFE_PWL1_OFF$1,Long frame Offset 1"
hexmask.long.byte 0x00 24.--31. 1. "RSVD,reserved"
hexmask.long.tbyte 0x00 0.--23. 1. "OFST00,S24 Offset at pixel 00"
repeat.end
tree.end
tree.end
tree "VPAC_VISS_RAWFE_H3A"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG"
base ad:0xF0A0400
rgroup.long 0x00++0x7F
line.long 0x00 "VISS_RAWFE_H3A_PID,Peripheral Revision and Class Information"
bitfld.long 0x00 30.--31. "SCHEME,PID scheme type" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,PID func revision"
bitfld.long 0x00 11.--15. "RTL,PID rtl revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,PID major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--5. "MINOR,PID minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VISS_RAWFE_H3A_PCR,Peripheral Control Register"
hexmask.long.word 0x04 22.--31. 1. "AVE2LMT,AE/AWB Saturation Limit This is the value that all sub sampled pixels in the AE/AWB engine are compared to If the data is greater or equal to this data then the block is considered saturated"
bitfld.long 0x04 21. "OVF,H3A module overflow status bit If the H3A module overflows it will keep sending data The software can read this status bit during vertical blanking period to ensure that no overflow happened while writing out the data to SDRAM There is also an.." "0,1"
bitfld.long 0x04 20. "AF_VF_EN,AF Vertical Focus Enable" "0,1"
bitfld.long 0x04 19. "AEW_MED_EN,AE/AWB Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not filtered" "0,1"
rbitfld.long 0x04 18. "BUSYAEAWB,Busy bit for AE/AWB" "0,1"
bitfld.long 0x04 17. "AEW_ALAW_EN,AE/AWB A-law Enable" "0,1"
bitfld.long 0x04 16. "AEW_EN,AE/AWB enable" "0,1"
newline
rbitfld.long 0x04 15. "BUSYAF,Busy bit for AF" "0,1"
bitfld.long 0x04 14. "FVMODE,Focus Value Accumulation Mode" "0,1"
bitfld.long 0x04 11.--13. "RGBPOS,Red Green and blue pixel location in the AF windows RGBPOS[0]: GR and GB as Bayer pattern RGBPOS[1]: RG and GB as Bayer pattern RGBPOS[2]: GR and BG as Bayer pattern RGBPOS[3]: RG and BG as Bayer pattern RGBPOS[4]: GG and RB as custom pattern.." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x04 3.--10. 1. "MED_TH,Median filter threshold"
bitfld.long 0x04 2. "AF_MED_EN,Auto Focus Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not in the valid region Therefore the paxel start/end and IIR filter start positions should not be set within the 1st and last 2.." "0,1"
bitfld.long 0x04 1. "AF_ALAW_EN,AF A-law table enable" "0,1"
bitfld.long 0x04 0. "AF_EN,AF enable" "0,1"
line.long 0x08 "VISS_RAWFE_H3A_AFPAX1,Setup for the AF Engine Paxel Configuration"
hexmask.long.byte 0x08 16.--23. 1. "PAXW,AF Engine Paxel Width The width of the paxel is the value of this register plus 1 multiplied by 2 The minimum width is 16 pixels if pixel clock is or less of the vpss clock If pixel clock is equal to vpss clock the minimum width is 32 pixels * This.."
hexmask.long.byte 0x08 0.--7. 1. "PAXH,AF Engine Paxel Height The height of the paxel is the value of this register plus 1 multiplied by 2 with a final value of"
line.long 0x0C "VISS_RAWFE_H3A_AFPAX2,Setup for the AF Engine Paxel Configuration"
bitfld.long 0x0C 17.--20. "AFINCH,AF Engine Column Increments Number of columns to increment in a paxel plus 1 multiplied by 2 Thus the number of columns that can be skipped between two processed line pairs is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 13.--16. "AFINCV,AF Engine Line Increments Number of lines to increment in a Paxel plus 1 multiplied by 2 Incrementing the line in a paxel is always done on a line pair due to the fact that the RGB pattern falls in two lines If all the lines are to be processed.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x0C 6.--12. 1. "PAXVC,AF Engine Vertical Paxel Count The number of paxels in the vertical direction plus 1 The maximum number of vertical paxels in a frame should not exceed 128 The value should be set to ensure that the bandwidth requirements and buffer size are not.."
bitfld.long 0x0C 0.--5. "PAXHC,AF Engine Horizontal Paxel Count The number of paxels in the horizontal direction plus 1 It is illegal to set a number that is greater than 35 [total of 36 paxels in the horizontal direction] The minimum number of paxels should be 2 [valid range.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "VISS_RAWFE_H3A_AFPAXSTART,Start Position for AF Engine Paxels"
hexmask.long.word 0x10 16.--27. 1. "PAXSH,AF Engine Paxel Horizontal start position Range"
hexmask.long.word 0x10 0.--11. 1. "PAXSV,AF Engine Paxel Vertical start position Range"
line.long 0x14 "VISS_RAWFE_H3A_AFIIRSH,Start Position for IIRSH"
hexmask.long.word 0x14 0.--11. 1. "IIRSH,AF Engine IIR Horizontal Start Position Range from"
line.long 0x18 "VISS_RAWFE_H3A_AFBUFST,SDRAM destination address for AF engine statistics"
hexmask.long 0x18 5.--31. 1. "AFBUFST,SDRAM destination address for AF engine statistics The SDRAM destination address for the AF statistics The 6 LSBs are ignored address shall be on a"
line.long 0x1C "VISS_RAWFE_H3A_AFCOEF010,IIR filter coefficient data for SET 0"
hexmask.long.word 0x1C 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 [Set 0] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x1C 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 [Set 0] The range is signed -32 <= value <= 31 +63/64"
line.long 0x20 "VISS_RAWFE_H3A_AFCOEF032,IIR filter coefficient data for SET 0"
hexmask.long.word 0x20 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 [Set 0] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x20 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 [Set 0] The range is signed -32 <= value <= 31 +63/64"
line.long 0x24 "VISS_RAWFE_H3A_AFCOEF054,IIR filter coefficient data for SET 0"
hexmask.long.word 0x24 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 [Set 0] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x24 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 [Set 0] The range is signed -32 <= value <= 31 +63/64"
line.long 0x28 "VISS_RAWFE_H3A_AFCOEF076,IIR filter coefficient data for SET 0"
hexmask.long.word 0x28 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 [Set 0] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x28 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 [Set 0] The range is signed -32 <= value <= 31 +63/64"
line.long 0x2C "VISS_RAWFE_H3A_AFCOEF098,IIR filter coefficient data for SET 0"
hexmask.long.word 0x2C 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 [Set 0] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x2C 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 [Set 0] The range is signed -32 <= value <= 31 +63/64"
line.long 0x30 "VISS_RAWFE_H3A_AFCOEF0010,IIR filter coefficient data for SET 0"
hexmask.long.word 0x30 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 [Set 0] The range is signed -32 <= value <= 31 +63/64"
line.long 0x34 "VISS_RAWFE_H3A_AFCOEF110,IIR filter coefficient data for SET 1"
hexmask.long.word 0x34 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 [Set 1] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x34 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 [Set 1] The range is signed -32 <= value <= 31 +63/64"
line.long 0x38 "VISS_RAWFE_H3A_AFCOEF132,IIR filter coefficient data for SET 1"
hexmask.long.word 0x38 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 [Set 1] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x38 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 [Set 1] The range is signed -32 <= value <= 31 +63/64"
line.long 0x3C "VISS_RAWFE_H3A_AFCOEF154,IIR filter coefficient data for SET 1"
hexmask.long.word 0x3C 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 [Set 1] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x3C 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 [Set 1] The range is signed -32 <= value <= 31 +63/64"
line.long 0x40 "VISS_RAWFE_H3A_AFCOEF176,IIR filter coefficient data for SET 1"
hexmask.long.word 0x40 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 [Set 1] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x40 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 [Set 1] The range is signed -32 <= value <= 31 +63/64"
line.long 0x44 "VISS_RAWFE_H3A_AFCOEF198,IIR filter coefficient data for SET 1"
hexmask.long.word 0x44 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 [Set 1] The range is signed -32 <= value <= 31 +63/64"
hexmask.long.word 0x44 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 [Set 1] The range is signed -32 <= value <= 31 +63/64"
line.long 0x48 "VISS_RAWFE_H3A_AFCOEF1010,IIR filter coefficient data for SET 1"
hexmask.long.word 0x48 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 [Set 1] The range is signed -32 <= value <= 31 +63/64"
line.long 0x4C "VISS_RAWFE_H3A_AEWWIN1,Configuration for AE/AWB Windows"
hexmask.long.byte 0x4C 24.--31. 1. "WINH,AE/AWB Engine Window Height This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2 The final value can be from"
hexmask.long.byte 0x4C 13.--20. 1. "WINW,AE/AWB Engine Window Width This specifies the window width in an even number of pixels the window width is the value plus 1 multiplied by 2 The minimum width is expected to be 8 pixels * This value is shadowed and latched on the rising edge of VSYNC"
hexmask.long.byte 0x4C 6.--12. 1. "WINVC,AE/AWB Engine Vertical Window Count The number of windows in the vertical direction plus 1 The maximum number of vertical windows in a frame should not exceed 128 The value should be set to ensure that the bandwidth requirements and buffer size.."
bitfld.long 0x4C 0.--5. "WINHC,AE/AWB Engine Horizontal Window Count The number of horizontal windows plus 1 The maximum number of horizontal windows is 35 plus 1 [36] The minimum number of windows should be 2 [valid range for the field is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x50 "VISS_RAWFE_H3A_AEWINSTART,Start position for AE/AWB Windows"
hexmask.long.word 0x50 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position Sets the first line for the first window Range"
hexmask.long.word 0x50 0.--11. 1. "WINSH,AE/AWB Engine Horizontal Window Start Position Sets the horizontal position for the first window on each line Range"
line.long 0x54 "VISS_RAWFE_H3A_AEWINBLK,Start position and height for black line of AE/AWB Windows"
hexmask.long.word 0x54 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position for single black line of windows Sets the first line for the single black line of windows * This value is shadowed and latched on the rising edge of VSYNC Range"
hexmask.long.byte 0x54 0.--6. 1. "WINH,AE/AWB Engine Window Height for the single black line of windows This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2 The final value can be from"
line.long 0x58 "VISS_RAWFE_H3A_AEWSUBWIN,Configuration for subsample data in AE/AWB window"
bitfld.long 0x58 8.--11. "AEWINCV,AE/AWB Engine Vertical Sampling Point Increment Sets vertical distance between sub-samples within a window plus 1 multiplied by 2 The final range is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 0.--3. "AEWINCH,AE/AWB Engine Horizontal Sampling Point Increment Sets horizontal distance between sub-samples within a window plus 1 multiplied by 2 The final range is" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "VISS_RAWFE_H3A_AEWBUFST,SDRAM destination address for AE/AWB engine statistics"
hexmask.long 0x5C 5.--31. 1. "AEWBUFST,SDRAM destination address for AE/AWB engine statistics The start location in SDRAM for the AE/AWB statistics The 6 LSB are ignored address should be on a"
line.long 0x60 "VISS_RAWFE_H3A_AEWCFG,Configuration for AE/AWB"
bitfld.long 0x60 8.--9. "AEFMT,AE/AWB output format" "0,1,2,3"
bitfld.long 0x60 0.--3. "SUMSHFT,AE/AWB engine shift value for the accumulation of pixel values This bitfield sets the right shift value which is applied on the result of the pixel accumulation before it is stored in the packet The accumulation takes place on 26 bits which is.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "VISS_RAWFE_H3A_LINE_START,Line Framing Logic Register In certain cases the number of clock cycles between HD pulses will be greater than the line buffer included in the H3A module"
hexmask.long.word 0x64 16.--31. 1. "SLV,Start Line Vertical Specifies how many lines after the VD rising edge the real frame starts"
hexmask.long.word 0x64 0.--15. 1. "LINE_START,Line Start The framing module uses the LINE_START bitfield to find the position of the first pixel to place into the line buffer Range"
line.long 0x68 "VISS_RAWFE_H3A_VFV_CFG1,Vertical focus value configuration 1"
hexmask.long.byte 0x68 24.--31. 1. "VCOEF1_3,Vertical FV FIR 1 coefficient 3"
hexmask.long.byte 0x68 16.--23. 1. "VCOEF1_2,Vertical FV FIR 1 coefficient 2"
hexmask.long.byte 0x68 8.--15. 1. "VCOEF1_1,Vertical FV FIR 1 coefficient 1"
hexmask.long.byte 0x68 0.--7. 1. "VCOEF1_0,Vertical FV FIR 1 coefficient 0"
line.long 0x6C "VISS_RAWFE_H3A_VFV_CFG2,Vertical focus value configuration 2"
hexmask.long.word 0x6C 16.--31. 1. "VTHR1,Threshold for vertical FV FIR 1"
hexmask.long.byte 0x6C 0.--7. 1. "VCOEF1_4,Vertical FV FIR 1 coefficient 4"
line.long 0x70 "VISS_RAWFE_H3A_VFV_CFG3,Vertical focus value configuration 4"
hexmask.long.byte 0x70 24.--31. 1. "VCOEF2_3,Vertical FV FIR 2 coefficient 3"
hexmask.long.byte 0x70 16.--23. 1. "VCOEF2_2,Vertical FV FIR 2 coefficient 2"
hexmask.long.byte 0x70 8.--15. 1. "VCOEF2_1,Vertical FV FIR 2 coefficient 1"
hexmask.long.byte 0x70 0.--7. 1. "VCOEF2_0,Vertical FV FIR 2 coefficient 0"
line.long 0x74 "VISS_RAWFE_H3A_VFV_CFG4,Vertical focus value configuration 4"
hexmask.long.word 0x74 16.--31. 1. "VTHR2,Threshold for vertical FV FIR 2"
hexmask.long.byte 0x74 0.--7. 1. "VCOEF2_4,Vertical FV FIR 2 coefficient 4"
line.long 0x78 "VISS_RAWFE_H3A_HVF_THR,Horizontal Focus Value Threshold"
hexmask.long.word 0x78 16.--31. 1. "HTHR2,Threshold for horizontal FV IIR 2"
hexmask.long.word 0x78 0.--15. 1. "HTHR1,Threshold for horizontal FV IIR 1"
line.long 0x7C "VISS_RAWFE_H3A_ADVANCED,advanced setting register. NOT FOR TRM"
hexmask.long.word 0x7C 16.--31. 1. "ID,Below information should not be in TRM To access the other bitfields [AF_MODE/AEW_MODE] certain value should be written to this ID field first First the ID is written to this field Second the AF_MODE or/and AEW_MODE is written"
bitfld.long 0x7C 4. "AEW_MODE,This bit should not be included in TRM This bit is accesible only if ID is set to 0xDC00 AE/AWB engine custom mode [AVE2 mode] select" "0,1"
bitfld.long 0x7C 0. "AF_MODE,AF engine mode Below information should not be included in TRM The effect of this bit changes based on the ID value If other value than 0xCA00 or 0xDC00 is set to ID this field has no effect" "0,1"
tree.end
tree.end
tree "VPAC_VISS_TOP"
tree "VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP"
base ad:0xF080000
rgroup.long 0x00++0x03
line.long 0x00 "VISS_REVISION_REG,VISS PID"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "VISS_LINEMEM_SIZE,Captures the no"
hexmask.long.word 0x00 0.--13. 1. "LINEMEM_SZ,No"
group.long 0x10++0x03
line.long 0x00 "VISS_CNTL,VISS top control"
bitfld.long 0x00 1. "NSF4V_EN,'1' -> NSF4V is ON '0' -> NSF4V is off i.e" "0,1"
bitfld.long 0x00 0. "GLBCE_EN,'1' -> GLBCE is ON '0' -> GLBCE is off i.e" "0,1"
group.long 0x80++0x07
line.long 0x00 "VISS_DBG_CTL,Enable for VISS debug staus capture"
bitfld.long 0x00 1. "PRTL_WR_EN,Enable to Capture Partial Write to any VISS end point" "0,1"
line.long 0x04 "VISS_DBG_STAT,Set/Clear for VISS debug status"
bitfld.long 0x04 1. "PRTL_WR,Status/Clear for Partial Write to any VISS end point" "0,1"
group.long 0x100++0x13
line.long 0x00 "VISS_GLBCECONFIG,GLBCE Configuration"
bitfld.long 0x00 0. "GLBCE_PCLKFREE,'1'-> GLBCE pclk is free running '0' -> GLBCE pclk is gated pixel clock" "0,1"
line.long 0x04 "VISS_GLBCE_VPSYNCDLY,Delay of GLBCE Core. used to regenerate VS/VE VPORT signals"
hexmask.long.byte 0x04 8.--15. 1. "V_DLY,Line delay between GLBCE.VS_In to GLBCE.VS_Out"
hexmask.long.byte 0x04 0.--7. 1. "H_DLY,Cycle delay between GLBCE.HS_In to GLBCE.HS_Out minus 1"
line.long 0x08 "VISS_GLBCE_INT_STAT,Set on internal interutp event and clr by SW"
bitfld.long 0x08 6. "VSYNC_ERR,status/clear for GLBCE VSYNC Delay programmation error" "0,1"
bitfld.long 0x08 5. "HSYNC_ERR,status/clear for GLBCE HSYNC Delay programmation error" "0,1"
bitfld.long 0x08 4. "VP_ERR,status/clear for GLBCE Input frame start error" "0,1"
bitfld.long 0x08 3. "FILT_DONE,status/clear for GLBCE Filtering Done event" "0,1"
bitfld.long 0x08 2. "FILT_START,status/clear for GLBCE Filtering Start event" "0,1"
bitfld.long 0x08 1. "STATMEM_CFG_ERR,status/clear for statastics memory configuration error" "0,1"
newline
bitfld.long 0x08 0. "MMR_CFG_ERR,status/clear for mmr configuration error" "0,1"
line.long 0x0C "VISS_GLBCE_DBG_CTL,Enable for GLBCE debug events"
bitfld.long 0x0C 4. "EOF_EN,Enable for EOF at GLBCE output" "0,1"
bitfld.long 0x0C 3. "EOL_EN,Enable for EOF at GLBCE output" "0,1"
bitfld.long 0x0C 2. "SOF_EN,Enable for SOF at GLBCE input" "0,1"
bitfld.long 0x0C 1. "SOL_EN,Enable for SOL at GLBCE input" "0,1"
bitfld.long 0x0C 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1"
line.long 0x10 "VISS_GLBCE_DBG_STAT,Set/Clear for GLBCE debug events"
bitfld.long 0x10 4. "EOF,Status/Clear for EOF at GLBCE output" "0,1"
bitfld.long 0x10 3. "EOL,Status/Clear for EOF at GLBCE output" "0,1"
bitfld.long 0x10 2. "SOF,Status/Clear for SOF at GLBCE input" "0,1"
bitfld.long 0x10 1. "SOL,Status/Clear for SOL at GLBCE input" "0,1"
tree.end
tree.end
tree "VPFE"
tree "VPFE0_MMRS"
base ad:0x2F00000
rgroup.long 0x00++0x07
line.long 0x00 "VPFE_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,VPFE_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTLVPFE_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,MajorVPFE_REVISION" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,MinorVPFE_REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VPFE_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "VPFE_CTRL_j,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits.0 = 1 byte " "?,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "VPFE_BASE_j,The Base Address for Region a"
line.long 0x08 "VPFE_TRANS_l_j,The Translated Lower Address Bits for Region a"
line.long 0x0C "VPFE_TRANS_U_j,The Translated Upper Address Bits for Region a"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
group.long 0x804++0x03
line.long 0x00 "VPFE_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "VPFE_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "VPFE_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type.4 = RAT"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "VPFE_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code.1 = Boundary crossing error"
line.long 0x0C "VPFE_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "VPFE_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "VPFE_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
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bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "VPFE_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "VPFE_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "VPFE_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "VPFE_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "VPFE_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "VPFE_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "VPFE0_VPFE"
base ad:0x2F08000
rgroup.long 0x00++0x3F
line.long 0x00 "VPFE_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function value"
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bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "VPFE_PCR,Peripheral Control Register"
bitfld.long 0x04 3. "EXPG_EN,External pattern generator enable" "0,1"
bitfld.long 0x04 2. "PG_EN,Pattern generator enable" "0,1"
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bitfld.long 0x04 1. "BUSY,VPFE busy bit" "Not busy,Busy"
bitfld.long 0x04 0. "ENABLE,This bit is latched by VD [start of frame]" "Disable,Enable"
line.long 0x08 "VPFE_SYNMODE,SYNC and Mode Set Register"
bitfld.long 0x08 17. "WEN,Data write enable Controls whether or not input raw data is written to external memory This bit is latched by VD" "Disable,Enable"
bitfld.long 0x08 16. "VDHDEN,VD/HD enable Activates internal timing generator to synchronize with external VD/HD signals This bit should be set to 1 when HD and VD signals are used at any time" "Disable,Enable"
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bitfld.long 0x08 15. "FLDSTAT,Field status Indicates the status of the current field when in interlaced mode" "Odd field,Even field"
bitfld.long 0x08 14. "LPF,3-tap low-pass [anti-aliasing] filter This bit is latched by VD" "Off,On"
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bitfld.long 0x08 12.--13. "INPMOD,Setting data input mode" "Raw Data,YCbCr 16 bit,YCbCr 8 bit,Reserved"
bitfld.long 0x08 11. "PACK8,Pack to8-bit/pixel [into external memory]" "Normal 16bits/pixel,8 bits/pixel"
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bitfld.long 0x08 8.--10. "DATSIZ,CCD data width is only valid when INPMOD is set to 0" "16 bits,15 bits,14 bits,13 bits,12 bits,11 bits,10 bits,8 bits"
bitfld.long 0x08 7. "FLDMODE,Sensor field mode" "Non-interlacedn,interlaced"
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bitfld.long 0x08 6. "DATAPOL,Input data polarity" "Normal,Ones complement"
bitfld.long 0x08 5. "EXWEN,External WEN selection When set to 1 and when VDHDEN is set to 1 the WEN signal is used as the external memory write enable [to external memory] The data is stored to memory only when the external sync [HD and VD] signals are active" "Do not use external WEN,Use external WEN"
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bitfld.long 0x08 4. "FLDPOL,Field indicator polarity" "Positive,Negative"
bitfld.long 0x08 3. "HDPOL,HD sync polarity" "Positive,Negative"
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bitfld.long 0x08 2. "VDPOL,VD sync polarity" "Positive,Negative"
bitfld.long 0x08 1. "FLDOUT,Field ID Direction" "Input,Output"
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bitfld.long 0x08 0. "VDHDOUT,VD/HD Sync Direction" "Input,Output"
line.long 0x0C "VPFE_HD_VD_WID,"
hexmask.long.word 0x0C 16.--27. 1. "HDW,Width of HD sync pulse if output HDW+1 pixel clocks HDWIDTH is not used when HD is input ie when VDHDOUT in SYN_MODE register is cleared to '0' *This bit field is latched by VD"
hexmask.long.word 0x0C 0.--11. 1. "VDW,Width of VD sync pulse if output VDW+1 lines VDWIDTH is not used when VD is input ie when VDHDOUT in SYN_MODE register is cleared to '0' *This bit field is latched by VD"
line.long 0x10 "VPFE_PIX_LINES,Number of pixels in a horizontal line and number of lines in a frame"
hexmask.long.word 0x10 16.--31. 1. "PPLN,Pixels per line - number of pixel clock periods in one line HD period = PPLN+1 pixel clocks PPLN is not used when HD and VD are inputs ie when VDHDOUT in SYN_MODE register is cleared to '0' *This bit field is latched by VD"
hexmask.long.word 0x10 0.--15. 1. "HLPFR,Half lines per field or frame - sets number of half lines per frame or field VD period = [HLPFR+1]/2 lines HLPFR is not used when HD and VD are inputs ie when VDHDOUT in SYN_MODE register is cleared to '0' This tells the internal timing generator.."
line.long 0x14 "VPFE_HORZ_INFO,Horizontal Pixel Information Register"
hexmask.long.word 0x14 16.--30. 1. "SPH,Start pixel horizontal The SPH sets the pixel clock position at which data output to external memory begins measured from the start of HD This bit field is latched by VD"
hexmask.long.word 0x14 0.--14. 1. "NPH,Number of pixels horizontal NPH sets the number of horizontal pixels that is output to external memory = [NPH + 1] and 0xFFF0 [ie the number of horizontal output pixels truncates to multiples of 16] This bit field is latched by VD"
line.long 0x18 "VPFE_VERT_START,Vertical Line - Settings for the Starting Pixel Register"
hexmask.long.word 0x18 16.--30. 1. "SLV0,Start line vertical [field 0] SLV0 sets line at which data output to external memory will begin measured from the start of VD This bit field is latched by VD"
hexmask.long.word 0x18 0.--14. 1. "SLV1,Start line vertical [field 1] SLV1 sets line at which data output to external memory will begin measured from the start of VD For a progressive sensor this field is ignored This bit field is latched by VD"
line.long 0x1C "VPFE_VERT_LINES,Number of Vertical Lines Register"
hexmask.long.word 0x1C 0.--14. 1. "NLV,Number of lines vertical NLV sets the number of vertical lines that will be output to external memory The number of lines output to external memory = [NLV + 1] This bit field is latched by VD"
line.long 0x20 "VPFE_CULLING,Culling Information in Horizontal and Vertical Directions Register"
abitfld.long 0x20 24.--31. "CULHEVN,Horizontal Culling Pattern for Even Line 8-bit mask LSB is first pixel MSB is 8th pixel then pattern repeats This bit field is latched by VD" "0x00=Culling(Deletion),0x01=Retain(to be saved in the memory)"
abitfld.long 0x20 16.--23. "CULHODD,Horizontal Culling Pattern for Odd Line 8-bit mask LSB is first pixel MSB is 8th pixel then pattern repeats This bit field is latched by VD" "0x00=Culling(Deletion),0x01=Retain(to be saved in the memory)"
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abitfld.long 0x20 0.--7. "CULV,Vertical Culling Pattern 8-bit mask LSB is first line MSB is 8th line then pattern repeats This bit field is latched by VD" "0x00=Culling(Deletion),0x01=Retain(to be saved in the memory)"
line.long 0x24 "VPFE_HSIZE_OFF,Horizontal Size Register"
hexmask.long.word 0x24 0.--15. 1. "LNOFST,Address offset for each line LNOFST Sets offset for each output line in external memory Either 16 or 32 pixels depending on setting of PACK8 the offset will be on a 32-byte boundary For optimal performance in the system the address offset should.."
line.long 0x28 "VPFE_SDOFST,External Memory Line Offset Register"
bitfld.long 0x28 14. "FIINV,Field identification signal inverse This field is latched by VD" "Non-inverse,Inverse"
bitfld.long 0x28 12.--13. "FOFST,Line offset value of field ID = 1 This field is latched by VD" "+1 line,+2 lines,+3 lines,+4 lines"
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bitfld.long 0x28 9.--11. "LOFTS0,Line offset values of even line and even field ID = 0 This field is latched by VD" "+1 line,+2 lines,+3 lines,+4 lines,-1 line,-2 lines,-3 lines,-4 lines"
bitfld.long 0x28 6.--8. "LOFTS1,Line offset values of odd line and even field ID = 0 This field is latched by VD" "+1 line,+2 lines,+3 lines,+4 lines,-1 line,-2 lines,-3 lines,-4 lines"
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bitfld.long 0x28 3.--5. "LOFTS2,Line offset values of even line and odd field ID = 1 This field is latched by VD" "+1 line,+2 lines,+3 lines,+4 lines,-1 line,-2 lines,-3 lines,-4 lines"
bitfld.long 0x28 0.--2. "LOFTS3,Line offset values of odd line and odd field ID = 1 This field is latched by VD" "+1 line,+2 lines,+3 lines,+4 lines,-1 line,-2 lines,-3 lines,-4 lines"
line.long 0x2C "VPFE_SDR_ADDR,External Memory Address Register"
hexmask.long 0x2C 5.--31. 1. "ADR_MSB,32-bit external memory starting address for VPFE output This bit field is latched by VD The address should be aligned on a 32-byte boundary Therefore the 5 LSB's are ignored Furthermore reading this register will always show the 5 LSB's as 0 For.."
rbitfld.long 0x2C 0.--4. "ADR_LSB,32-bit external memory starting address for VPFE output This bit field is latched by VD The address should be aligned on a 32-byte boundary Therefore the 5 LSB's are ignored Furthermore reading this register will always show the 5 LSB's as 0 For.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "VPFE_CLAMP,Optical Black Clamping Setting Register"
bitfld.long 0x30 31. "CLAMPEN,Clamp enable Enable or disable clamping of CCD data based on the calculated average of optical black samples This bit is latched by VD" "Disable,Enable"
bitfld.long 0x30 28.--30. "OBSLEN,Optical black sample length Number of Optical Black Sample pixels per line to include in the average calculation" "1 pixels,2 pixels,4 pixels,8 pixels,16 pixels,Reserved,Reserved,Reserved"
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bitfld.long 0x30 25.--27. "OBSLN,Optical black sample lines Number of Optical Black Sample lines to include in the average calculation" "1 lines,2 lines,4 lines,8 lines,16 lines,Reserved,Reserved,Reserved"
hexmask.long.word 0x30 10.--24. 1. "OBST,Start pixel of optical black samples The start pixel position of optical black samples specified from the start of HD in pixel clocks"
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bitfld.long 0x30 0.--4. "OBGAIN,Gain to apply to the optical black average Multiply the optical black average with the specified gain" "0 + 0/16,0 + 1/16,0 + 2/16,?,?,?,?,?,?,?,?,?,?,0 + 13/16,0 + 14/16,0 + 15/16,1 + 0/16,?,?,?,?,?,?,?,?,?,?,?,?,?,1 + 14/16 ..=,1 + 15/16"
line.long 0x34 "VPFE_DCSUB,DC Clamp Register"
hexmask.long.word 0x34 0.--13. 1. "DCSUB,DC level to subtract from CCD data The DC value set here is subtracted from the CCD data when OBS clamping is disabled - CLAMPCLAMPEN"
line.long 0x38 "VPFE_COLPTN,CCD Color Pattern Register"
bitfld.long 0x38 30.--31. "CP3LPC3,Color Pattern for 3rd Line Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 28.--29. "CP3LPC2,Color Pattern for 3rd Line Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 26.--27. "CP3LPC1,Color Pattern for 3rd Line Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 24.--25. "CP3LPC0,Color Pattern for 3rd Line Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 22.--23. "CP2LPC3,Color Pattern for 2nd Line Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 20.--21. "CP2LPC2,Color Pattern for 2nd Line Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 18.--19. "CP2LPC1,Color Pattern for 2nd Line Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 16.--17. "CP2LPC0,Color Pattern for 2nd Line Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 14.--15. "CP1LPC3,Color Pattern for 1st Line Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 12.--13. "CP1LPC2,Color Pattern for 1st Line Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 10.--11. "CP1LPC1,Color Pattern for 1st Line Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 8.--9. "CP1LPC0,Color Pattern for 1st Line Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 6.--7. "CP0LPC3,Color Pattern for 0th Line Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 4.--5. "CP0LPC2,Color Pattern for 0th Line Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
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bitfld.long 0x38 2.--3. "CP0LPC1,Color Pattern for 0th Line Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
bitfld.long 0x38 0.--1. "CP0LPC0,Color Pattern for 0th Line Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
line.long 0x3C "VPFE_BLKCMP,Black Compensation Register"
hexmask.long.byte 0x3C 24.--31. 1. "RYE,Black level compensation for R/Ye pixels [-128:+127] 2's complement MSB is sign bit"
hexmask.long.byte 0x3C 16.--23. 1. "GRCY,Black level compensation for Gr/Cy pixels [-128:+127] 2's complement MSB is sign bit"
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hexmask.long.byte 0x3C 8.--15. 1. "GBG,Black level compensation for Gb/G pixels [-128:+127] 2's complement MSB is sign bit"
hexmask.long.byte 0x3C 0.--7. 1. "BMG,Black level compensation for B/Mg pixels [-128:+127] 2's complement MSB is sign bit"
group.long 0x48++0x0F
line.long 0x00 "VPFE_VDINT,VPFE Interrupt Control Register"
hexmask.long.word 0x00 16.--30. 1. "VDINT0,CCDC_VD0_INT interrupt timing Specify VDINT0 in units of horizontal lines from the start of VD pulse Resulting value is VDINT0+1 Note that if the rising edge [or falling edge if programmed] of the HD lines up with the rising edge [or falling edge.."
hexmask.long.word 0x00 0.--14. 1. "VDINT1,CCDC_VD1_INT interrupt timing Specify VDINT1 in units of horizontal lines from the start of VD pulse Resulting value is VDINT1+1 Note that if the rising edge [or falling edge if programmed] of the HD lines up with the rising edge [or falling edge.."
line.long 0x04 "VPFE_ALAW,Configuration Register"
bitfld.long 0x04 3. "CCDTBL,Apply Gamma [A-LAW] to VPFE data saved to external memory" "Disable,Enable"
bitfld.long 0x04 0.--2. "GWDI,A-law Width Input [A-LAW table]" "Bits15-6,Bits 14-5,Bits 13-4,Bits 12-3,Bits 11-2,Bits 10-1,Bits 9-0,?..."
line.long 0x08 "VPFE_REC656IF,Configuration Register"
bitfld.long 0x08 1. "ECCFVH,FVH error correction enable" "Disable,Enable"
bitfld.long 0x08 0. "R656ON,REC656 interface enable" "Disable,Enable"
line.long 0x0C "VPFE_CCDCFG,CCD Configuration Register"
bitfld.long 0x0C 15. "VDLC,Enable latching function registers on internal VSYNC If this bit is set all the register fields that are VSYNC latched will take on new value immediately Care should be taken not to alter fields that can cause undesired behavior to the output data" "Latched on VSYNC,Not latched on VSYNC"
bitfld.long 0x0C 14. "MSBINVO,MSB of Chroma signal output inverted" "Normal,MSB inverted"
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bitfld.long 0x0C 13. "MSBINVI,MSB of Chroma input signal stored to SDRAM inverted" "Normal,MSB inverted"
bitfld.long 0x0C 12. "BSWD,Byte Swap Data stored to SDRAM" "Normal,Swap bytes"
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bitfld.long 0x0C 11. "Y8POS,Location of Y signal when YCbCr 8bit data is input" "Even pixel,Odd pixel"
bitfld.long 0x0C 8. "WENLOG,Specifies CCD valid area" "Internal valid signal WEN signal is ANDed..,Internal valid signal and WEN signal is ORed.."
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bitfld.long 0x0C 5. "BW656,The data width in CCIR656 input mode" "8 bits,10 bits"
bitfld.long 0x0C 4. "YCINSWP,Y input [YIN[7:0]] and C input [CIN[7:0]] are swapped" "0,1"
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bitfld.long 0x0C 2. "YCOUTSWP,Y output [YOUT[7:0]] and C output [COUT[7:0]] are swapped" "0,1"
group.long 0x98++0x03
line.long 0x00 "VPFE_DMA_CNTL,DMA Status and Control"
bitfld.long 0x00 31. "OVERFLOW,DMA Overflow Flag Flag bit that is set when data is dropped due to a delay in writing data out the DMA interface This bit remains set until a 1 is written by software" "No overflow has occured,Overflow has occured"
group.long 0x104++0x07
line.long 0x00 "VPFE_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode By definition initiator may generate read/write transaction as long as it is out of STANDBY state" "Force Standby mode local initiator is..,No Standby mode local initiator is..,Smart Standby mode local initiator standby..,Smart Standby wakeup capable mode local.."
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "Force Idle mode local targets idle state follows..,No idle mode local target never enters idle state,Smart Idle mode local targets idle eventually..,Smart idle wakeup capable mode local targets.."
line.long 0x04 "VPFE_CONFIG,Module configuration register"
bitfld.long 0x04 2. "VPFE_ST,VPFE Master OCP interface Status" "OCP master interface is avctive,OCP master interface is in standby mode"
bitfld.long 0x04 1. "VPFE_EN,VPFE Master OCP interface enable Software can has to use this bit to enable/disable the VPFE master OCP interface When the master OCP interface is disabled it is placed in Standby mode Standby mode can also be entered by using the right setting.." "Disable VPFE master OCP interface,Enable VPFE master OCP interface"
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bitfld.long 0x04 0. "PCLK_INV,Pixel clock inversion enable" "Pixel clock is not inverted data is sampled on..,pixel clock is inverted data is sampled on the.."
group.long 0x110++0x13
line.long 0x00 "VPFE_IRQ_EOI,Module EOI register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI,EOI for VPFE This register allows software to acknowledge the completion of an interrupt When this register is written an eoi_write signal is generated internal to the module and another interrupt will be triggered if the interrupt sources are still.." "0,1"
line.long 0x04 "VPFE_IRQ_STATUS_RAW,Interrupt raw status register"
bitfld.long 0x04 2. "VD2_INT_RAW,CCDC VD2 interrupt status raw value - A read value of 1 from this register indicates that the VD2 interrupt status is1 - When the read value is 0 software can write the value to 1 to set the interrupt - Writing a 0 to this bit has no effect" "0,1"
bitfld.long 0x04 1. "VD1_INT_RAW,CCDC VD1 interrupt status raw value - A read value of 1 from this register indicates that the VD1 interrupt status is1 - When the read value is 0 software can write the value to 1 to set the interrupt - Writing a 0 to this bit has no effect" "0,1"
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bitfld.long 0x04 0. "VD0_INT_RAW,CCDC VD0 interrupt status raw value - A read value of 1 from this register indicates that the VD0 interrupt status is1 - When the read value is 0 software can write the value to 1 to set the interrupt - Writing a 0 to this bit has no effect" "0,1"
line.long 0x08 "VPFE_IRQ_STATUS,Interrupt status register"
bitfld.long 0x08 2. "VD2_INT,CCDC VD2 interrupt status value - A read value of 1 from this register indicates that the VD2 interrupt status is 1 if it is enabled - When the read value is 1 software can write a 1 to clear the interrupt - Writing a 0 to this bit has no effect" "0,1"
bitfld.long 0x08 1. "VD1_INT,CCDC VD1 interrupt status value - A read value of 1 from this register indicates that the VD2 interrupt status is 1 if it is enabled - When the read value is 1 software can write a 1 to clear the interrupt - Writing a 0 to this bit has no effect" "0,1"
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bitfld.long 0x08 0. "VD0_INT,CCDC VD0 interrupt status value - A read value of 1 from this register indicates that the VD2 interrupt status is 1 if it is enabled - When the read value is 1 software can write a 1 to clear the interrupt - Writing a 0 to this bit has no effect" "0,1"
line.long 0x0C "VPFE_IRQ_ENABLE_SET,Interrupt enable set"
bitfld.long 0x0C 2. "VD2_INT_EN,CCDC VD2 interrupt enable - Write 1 to enable this interrupt - Write 0 has no effect - Read 1 indicates interrupt is enabled - Read 0 indicates interrupt is not enabled" "0,1"
bitfld.long 0x0C 1. "VD1_INT_EN,CCDC VD1 interrupt enable - Write 1 to enable this interrupt - Write 0 has no effect - Read 1 indicates interrupt is enabled - Read 0 indicates interrupt is not enabled" "0,1"
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bitfld.long 0x0C 0. "VD0_INT_EN,CCDC VD0 interrupt enable - Write 1 to enable this interrupt - Write 0 has no effect - Read 1 indicates interrupt is enabled - Read 0 indicates interrupt is not enabled" "0,1"
line.long 0x10 "VPFE_IRQ_ENABLE_CLR,Interrupt enable clear"
bitfld.long 0x10 2. "VD2_INT_DIS,CCDC VD2 interrupt disable - Write 1 to disable this interrupt - Write 0 has no effect - Read 1 indicates interrupt is enabled - Read 0 indicates interrupt is not enabled" "0,1"
bitfld.long 0x10 1. "VD1_INT_DIS,CCDC VD1 interrupt disable - Write 1 to disable this interrupt - Write 0 has no effect - Read 1 indicates interrupt is enabled - Read 0 indicates interrupt is not enabled" "0,1"
newline
bitfld.long 0x10 0. "VD0_INT_DIS,CCDC VD0 interrupt disable - Write 1 to disable this interrupt - Write 0 has no effect - Read 1 indicates interrupt is enabled - Read 0 indicates interrupt is not enabled" "0,1"
tree.end
tree.end
tree "WKUP_CTRL_MMR0"
tree "WKUP_CTRL_MMR0"
base ad:0x43000000
rgroup.long 0x00++0x03
line.long 0x00 "CTRLMMR_WKUP_PID,Peripheral release details"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business unit" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module functional identifier"
bitfld.long 0x00 11.--15. "R_RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CTRLMMR_WKUP_MMR_CFG1,Indicates the MMR configuration"
hexmask.long.byte 0x00 0.--7. 1. "PARTITIONS,Indicates present partitions"
rgroup.long 0x14++0x03
line.long 0x00 "CTRLMMR_WKUP_JTAGID,The register must be readable by the configuration bus so that this can be accessed via the JTAG and CPU"
bitfld.long 0x00 28.--31. "VARIANT,Used to indicate new PGs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 12.--27. 1. "PARTNO,Part number for boundary scan"
newline
hexmask.long.word 0x00 1.--11. 1. "MFG,Indicates manufacturer"
bitfld.long 0x00 0. "LSB,Always 1" "0,1"
group.long 0x30++0x0F
line.long 0x00 "CTRLMMR_WKUP_DEVSTAT,Indicates MCU bootstrap selection"
hexmask.long.word 0x00 0.--9. 1. "BOOTMODE,Indicates MCU bootstrap selection"
line.long 0x04 "CTRLMMR_WKUP_BOOTCFG,Indicates MCU bootstrap selection latched at power-on reset by PORz"
hexmask.long.word 0x04 0.--9. 1. "BOOTMODE,Indicates MCU boot mode as latched at power-on reset"
line.long 0x08 "CTRLMMR_WKUP_POST_SEL_STAT,Indicates which power-on self test option was performed"
bitfld.long 0x08 0.--1. "POST_SEL_STAT,Indicates which POST option was selected at power-up" "0,1,2,3"
line.long 0x0C "CTRLMMR_WKUP_POST_OPT,Indicates the 3 available power-on self test (POST) options: Bits"
bitfld.long 0x0C 19. "OPT3_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1"
bitfld.long 0x0C 18. "OPT3_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1"
newline
bitfld.long 0x0C 17. "OPT3_DMSC_LBIST_EN,DMSC LBIST enabled" "0,1"
bitfld.long 0x0C 16. "OPT3_PARALLEL_EN,Selects DMSC/MCU R5 LBIST sequencing" "0,1"
newline
bitfld.long 0x0C 11. "OPT2_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1"
bitfld.long 0x0C 10. "OPT2_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1"
newline
bitfld.long 0x0C 9. "OPT2_DMSC_LBIST_EN,DMSC LBIST enabled" "0,1"
bitfld.long 0x0C 8. "OPT2_PARALLEL_EN,Selects DMSC/MCU R5 LBIST sequencing" "0,1"
newline
bitfld.long 0x0C 3. "OPT1_MCU_PBIST_EN,MCU R5 PBIST enabled" "0,1"
bitfld.long 0x0C 2. "OPT1_MCU_LBIST_EN,MCU R5 LBIST enabled" "0,1"
newline
bitfld.long 0x0C 1. "OPT1_DMSC_LBIST_EN,DMSC LBIST enabled" "0,1"
bitfld.long 0x0C 0. "OPT1_PARALLEL_EN,Selects DMSC/MCU R5 LBIST sequencing" "0,1"
group.long 0x50++0x03
line.long 0x00 "CTRLMMR_WKUP_RESET_SRC_STAT,Indicates source of last device reset"
bitfld.long 0x00 24. "THERMAL_RST,When set indicates that a VTM Max Temp Thermal reset occurred" "0,1"
bitfld.long 0x00 20. "DBUGSS_RST,When set indicates that a Debug reset occurred" "0,1"
newline
bitfld.long 0x00 19. "COLD_OUT_RST,When set indicates that a DMSC Cold reset occurred" "0,1"
bitfld.long 0x00 16. "WARM_OUT_RST,When set indicates that a DSMC Warm reset occured" "0,1"
newline
bitfld.long 0x00 11. "PORZ_PIN,When set indicates that a PORz pin reset occurred" "0,1"
bitfld.long 0x00 9. "RESET_REQZ_PIN,When set indicates that a RESET_REQz pin reset occurred" "0,1"
newline
bitfld.long 0x00 8. "MCU_RSTZ_PIN,When set indicates that a MCU_RESETz pin reset occurred" "0,1"
bitfld.long 0x00 3. "SW_MAIN_POR,When set indicates that a Software MAIN Power-on reset occurred" "0,1"
newline
bitfld.long 0x00 1. "SW_MAIN_WARMRST,When set indicates that a Software MAIN Warm reset occurred" "0,1"
bitfld.long 0x00 0. "SW_MCU_WARMRST,When set indicates that a Software MCU Warm reset occurred" "0,1"
rgroup.long 0x60++0x1B
line.long 0x00 "CTRLMMR_WKUP_DEVICE_FEATURE0,Indicates enabled MPU processing elements on the device"
bitfld.long 0x00 1. "MPU_CLUSTER0_CORE1,MPU Cluster0 Core 1 is enabled when set" "0,1"
bitfld.long 0x00 0. "MPU_CLUSTER0_CORE0,MPU Cluster0 Core 0 is enabled when set" "0,1"
line.long 0x04 "CTRLMMR_WKUP_DEVICE_FEATURE1,Indicates enabled non-MPU processing elements on the device"
bitfld.long 0x04 16. "C71_CORE0,C71 Core0 is enabled when set" "0,1"
bitfld.long 0x04 12. "GPU,GPU is enabled when set" "0,1"
newline
bitfld.long 0x04 9. "C66_CORE1,C66 Core1 is enabled when set" "0,1"
bitfld.long 0x04 8. "C66_CORE0,C66 Core0 is enabled when set" "0,1"
newline
bitfld.long 0x04 3. "MCU_CLUSTER1_CORE1,MAIN MCU Cluster1 Core1 is enabled when set" "0,1"
bitfld.long 0x04 2. "MCU_CLUSTER1_CORE0,MAIN MCU Cluster1 Core0 is enabled when set" "0,1"
newline
bitfld.long 0x04 1. "MCU_CLUSTER0_CORE1,MAIN MCU Cluster0 Core1 is enabled when set" "0,1"
bitfld.long 0x04 0. "MCU_CLUSTER0_CORE0,MAIN MCU Cluster0 Core0 is enabled when set" "0,1"
line.long 0x08 "CTRLMMR_WKUP_DEVICE_FEATURE2,Indicates enabled MCU domain interface elements on the device"
bitfld.long 0x08 10. "CRYPTO_PKA_EN,MCU SA2_UL Crypto Module PKA enabled" "0,1"
bitfld.long 0x08 9. "CRYPTO_ENCR_EN,MCU SA2_UL Crypto Module AES/3DES/DBRG enabled" "0,1"
newline
bitfld.long 0x08 8. "CRYPTO_SHA_EN,MCU SA2_UL Crypto Module SHA/MD5 enabled" "0,1"
bitfld.long 0x08 7. "AES_AUTH_EN,AES authentication is enabled in MCU_FlashSS and DMSC when set" "0,1"
newline
bitfld.long 0x08 6. "HYPERBUS,MCU_FSS0_HPB0 is enabled when set" "0,1"
bitfld.long 0x08 5. "OSPI1,MCU_OSPI1 is enabled when set" "0,1"
newline
bitfld.long 0x08 4. "OSPI0,MCU_OSPI0 is enabled when set" "0,1"
bitfld.long 0x08 3. "MCU_MCAN1,MCU_MCAN1 is enabled when set" "0,1"
newline
bitfld.long 0x08 1. "MCU_MCAN0,MCU_MCAN0 is enabled when set" "0,1"
bitfld.long 0x08 0. "MCU_MCAN_FD_MODE,FD mode is supported on MCU_MCAN[1:0] when set" "0,1"
line.long 0x0C "CTRLMMR_WKUP_DEVICE_FEATURE3,Indicates enabled MAIN domain interface elements on the device"
bitfld.long 0x0C 28. "EMIF0,EMIF0 is enabled when set" "0,1"
bitfld.long 0x0C 21. "MMC_4B0,4-bit MMCSD1 is enabled when set" "0,1"
newline
bitfld.long 0x0C 20. "MMC_8B,8-bit MMCSD0 is enabled when set" "0,1"
bitfld.long 0x0C 17. "ICSS_G1,ICSS_G1 is enabled when set" "0,1"
newline
bitfld.long 0x0C 16. "ICSS_G0,ICSS_G0 is enabled when set" "0,1"
bitfld.long 0x0C 12. "SERDES4,10G SERDES4 is enabled when set" "0,1"
newline
bitfld.long 0x0C 11. "SERDES3,16G SERDES3 is enabled when set" "0,1"
bitfld.long 0x0C 10. "SERDES2,16G SERDES2 is enabled when set" "0,1"
newline
bitfld.long 0x0C 9. "SERDES1,16G SERDES1 is enabled when set" "0,1"
bitfld.long 0x0C 8. "SERDES0,16G SERDES0 is enabled when set" "0,1"
newline
bitfld.long 0x0C 7. "PCIE3,PCIe3 is enabled when set" "0,1"
bitfld.long 0x0C 6. "PCIE2,PCIe2 is enabled when set" "0,1"
newline
bitfld.long 0x0C 5. "PCIE1,PCIe1 is enabled when set" "0,1"
bitfld.long 0x0C 4. "PCIE0,PCIe0 is enabled when set" "0,1"
newline
bitfld.long 0x0C 1. "USB1,USB1 is enabled when set" "0,1"
bitfld.long 0x0C 0. "USB0,USB0 is enabled when set" "0,1"
line.long 0x10 "CTRLMMR_WKUP_DEVICE_FEATURE4,Indicates enabled MAIN domain interface elements on the device"
bitfld.long 0x10 25. "DECODER,Video decoder is enabled when set" "0,1"
bitfld.long 0x10 24. "ENCODER,Video encoder is enabled when set" "0,1"
newline
bitfld.long 0x10 20. "VPFE,VPFE is enabled when set" "0,1"
bitfld.long 0x10 19. "VPE,Video processing engine is enabled when set" "0,1"
newline
bitfld.long 0x10 18. "VPAC,VPAC is enabled when set" "0,1"
bitfld.long 0x10 17. "SDE,DMPAC Stereo Disparity Engine is enabled when set" "0,1"
newline
bitfld.long 0x10 16. "DMPAC,DMPAC is enabled when set" "0,1"
bitfld.long 0x10 12. "EDP0,Embedded display port 0 is enabled when set" "0,1"
newline
bitfld.long 0x10 8. "CSITX0,CSI_TX0 is enabled when set" "0,1"
bitfld.long 0x10 5. "CSIRX1,CSI_RX1 is enabled when set" "0,1"
newline
bitfld.long 0x10 4. "CSIRX0,CSI_RX0 is enabled when set" "0,1"
bitfld.long 0x10 2. "DSI,DSI is enabled when set" "0,1"
newline
bitfld.long 0x10 0. "DSS,DSS is enabled when set" "0,1"
line.long 0x14 "CTRLMMR_WKUP_DEVICE_FEATURE5,Indicates enabled MAIN domain interface elements on the device"
bitfld.long 0x14 13. "MCAN13,MCAN13 is enabled when set" "0,1"
bitfld.long 0x14 12. "MCAN12,MCAN12 is enabled when set" "0,1"
newline
bitfld.long 0x14 11. "MCAN11,MCAN11 is enabled when set" "0,1"
bitfld.long 0x14 10. "MCAN10,MCAN10 is enabled when set" "0,1"
newline
bitfld.long 0x14 9. "MCAN9,MCAN9 is enabled when set" "0,1"
bitfld.long 0x14 8. "MCAN8,MCAN8 is enabled when set" "0,1"
newline
bitfld.long 0x14 7. "MCAN7,MCAN7 is enabled when set" "0,1"
bitfld.long 0x14 6. "MCAN6,MCAN6 is enabled when set" "0,1"
newline
bitfld.long 0x14 5. "MCAN5,MCAN5 is enabled when set" "0,1"
bitfld.long 0x14 4. "MCAN4,MCAN4 is enabled when set" "0,1"
newline
bitfld.long 0x14 3. "MCAN3,MCAN3 is enabled when set" "0,1"
bitfld.long 0x14 2. "MCAN2,MCAN2 is enabled when set" "0,1"
newline
bitfld.long 0x14 1. "MCAN1,MCAN1 is enabled when set" "0,1"
bitfld.long 0x14 0. "MCAN0,MCAN0 is enabled when set" "0,1"
line.long 0x18 "CTRLMMR_WKUP_DEVICE_FEATURE6,Indicates enabled MAIN domain interface elements on the device"
bitfld.long 0x18 9. "I3C,MAIN domain I3C is enabled when set" "0,1"
bitfld.long 0x18 8. "MOTOR_PER,Motor control peripherals (eCAP eQEP eHRPWM) are enabled when set" "0,1"
newline
bitfld.long 0x18 7. "ATL,Audio tracking logic is enabled when set" "0,1"
bitfld.long 0x18 6. "MLB,Media local bus is enabled when set" "0,1"
newline
bitfld.long 0x18 5. "SA2_UL,MAIN domain security accelerator is enabled when set" "0,1"
bitfld.long 0x18 4. "CPSW9G,8 Channel Q/SGMII Ethernet switch enabled when set" "0,1"
newline
bitfld.long 0x18 0. "UFS0,UFS interface 0 is enabled when set" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "CTRLMMR_WKUP_LOCK0_KICK0,Lower 32-bits of Partition0 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LOCK0_KICK1,Upper 32-bits of Partition 0 write lock key"
line.long 0x08 "CTRLMMR_WKUP_INTR_RAW_STAT,Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test)"
bitfld.long 0x08 2. "LOCK_ERR,Lock violation occurred (attempt to write a write-locked register with partition locked)" "0,1"
bitfld.long 0x08 1. "ADDR_ERR,Address violation occurred (attempt to read or write an invalid register address)" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)" "0,1"
line.long 0x0C "CTRLMMR_WKUP_INTR_STAT_CLR,Shows the enabled interrupt status and allows the interrupt to be cleared"
bitfld.long 0x0C 2. "EN_LOCK_ERR,Enabled lock interrupt event status" "0,1"
bitfld.long 0x0C 1. "EN_ADDR_ERR,Enabled address interrupt event status" "0,1"
newline
bitfld.long 0x0C 0. "EN_PROT_ERR,Enabled protection interrupt event status" "0,1"
line.long 0x10 "CTRLMMR_WKUP_INTR_EN_SET,Allows interrupt enables to be set"
bitfld.long 0x10 2. "LOCK_ERR_EN_SET,Lock interrupt enable" "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN_SET,Address interrupt enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_SET,Protection interrupt enable" "0,1"
line.long 0x14 "CTRLMMR_WKUP_INTR_EN_CLR,Allows interrupt enables to be cleared"
bitfld.long 0x14 2. "LOCK_ERR_EN_CLR,Lock interrupt disable" "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Address interrupt disable" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection interrupt disable" "0,1"
line.long 0x18 "CTRLMMR_WKUP_EOI,EOI Vector value"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "CTRLMMR_WKUP_FAULT_ADDR,Indicates the address of the first transfer that caused a fault to occur"
line.long 0x20 "CTRLMMR_WKUP_FAULT_TYPE,Indicates the access type of the first transfer that caused a fault to occur"
bitfld.long 0x20 0.--5. "TYPE,Type of access which faulted" "No fault,User execute access,User write access,?,User read access,?,?,?,Supervisor execute access,?,?,?,?,?,?,?,Supervisor write access,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read access,?..."
line.long 0x24 "CTRLMMR_WKUP_FAULT_ATTR,Indicates the attributes of the first transfer that caused a fault to occur"
hexmask.long.word 0x24 20.--31. 1. "XID,Transaction ID"
hexmask.long.word 0x24 8.--19. 1. "ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "PRIVID,Privilege ID"
line.long 0x28 "CTRLMMR_WKUP_FAULT_CLR,Allows software to clear the current fault"
bitfld.long 0x28 0. "CLEAR,Fault clear" "0,1"
group.long 0x4004++0x03
line.long 0x00 "CTRLMMR_WKUP_MAIN_PWR_CTRL,Controls power options for the MAIN voltage domain"
bitfld.long 0x00 0. "PWR_EN,When set drives the PMIC_POWER_EN1 output pin causing PMIC to turn on the MAIN voltage domain" "0,1"
group.long 0x4020++0x03
line.long 0x00 "CTRLMMR_WKUP_GPIO_CTRL,Controls operation of the WKUP_GPIO module"
bitfld.long 0x00 0. "WAKEN,Enables WKUP_GPIO wakeup event operation by controling the WKUP_GPIO LPSC clockstop_ack behavior" "No WKUP_GPIO wakeup support,WKUP_GPIO wakeup enabled"
group.long 0x4030++0x03
line.long 0x00 "CTRLMMR_WKUP_I2C0_CTRL,Controls WKUP_I2C0 operation"
bitfld.long 0x00 0. "HS_MCS_EN,HS Mode master current source enable" "0,1"
group.long 0x4084++0x17
line.long 0x00 "CTRLMMR_WKUP_DBOUNCE_CFG1,Configures IO debounce selections"
bitfld.long 0x00 0.--5. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL set to 1h" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CTRLMMR_WKUP_DBOUNCE_CFG2,Configures IO debounce selections"
bitfld.long 0x04 0.--5. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL set to 2h" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CTRLMMR_WKUP_DBOUNCE_CFG3,Configures IO debounce selections"
bitfld.long 0x08 0.--5. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL set to 3h" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CTRLMMR_WKUP_DBOUNCE_CFG4,Configures IO debounce selections"
bitfld.long 0x0C 0.--5. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL set to 4h" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "CTRLMMR_WKUP_DBOUNCE_CFG5,Configures IO debounce selections"
bitfld.long 0x10 0.--5. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL set to 5h" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "CTRLMMR_WKUP_DBOUNCE_CFG6,Configures IO debounce selections"
bitfld.long 0x14 0.--5. "DB_CFG,Configures the debounce period used for I/Os with DEBOUNCE_SEL set to 6h" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x5008++0x07
line.long 0x00 "CTRLMMR_WKUP_LOCK1_KICK0,Lower 32-bits of Partition1 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LOCK1_KICK1,Upper 32-bits of Partition 1 write lock key"
group.long 0x8000++0x03
line.long 0x00 "CTRLMMR_WKUP_MCU_OBSCLK_CTRL,Controls which internal clock is made observable on the MCU_OBSCLK output pin"
bitfld.long 0x00 24. "OUT_MUX_SEL,MCU_OBSCLK pin output mux selection" "0,1"
bitfld.long 0x00 16. "CLK_DIV_LD,Load the output divider value" "0,1"
newline
bitfld.long 0x00 8.--11. "CLK_DIV,MCU_OBSCLK pin clock selection output divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CLK_SEL,MCU_OBSCLK pin clock selection" "CLK_12M_RC,'0',MCU_PLL0_HSDIV0_CLKOUT,MCU_PLLCTL_OBSCLK,MCU_PLL1_HSDIV1_CLKOUT,MCU_PLL1_HSDIV2_CLKOUT,MCU_PLL1_HSDIV3_CLKOUT,MCU_PLL1_HSDIV4_CLKOUT,MCU_PLL2_HSDIV0_CLKOUT,CLK_32K,MCU_PLL2_HSDIV1_CLKOUT,MCU_PLL2_HSDIV2_CLKOUT,MCU_PLL2_HSDIV3_CLKOUT,MCU_PLL2_HSDIV4_CLKOUT,WKUP_HFOSC0_CLKOUT,WKUP_LFOSC0_CLKOUT"
group.long 0x8030++0x07
line.long 0x00 "CTRLMMR_WKUP_LFXOSC_CTRL,Controls the operation of the low frequency oscillator"
bitfld.long 0x00 7. "PD_C,Oscillator powerdown control" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LFXOSC_TRIM,Provides frequency trimming for the low frequency oscillator module"
bitfld.long 0x04 16.--18. "I_MULT,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7"
group.long 0x8050++0x03
line.long 0x00 "CTRLMMR_WKUP_MCU_PLL_CLKSEL,Controls the clock source for MCU voltage domain PLL[2:0]"
bitfld.long 0x00 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x00 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x00 8. "CLKLOSS_SWTCH_EN,When set enables automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if WKUP_HFOSC0 clock loss is detected" "0,1"
group.long 0x8060++0x07
line.long 0x00 "CTRLMMR_WKUP_PER_CLKSEL,Controls the wakeup peripheral functional clock source"
bitfld.long 0x00 0. "MCUPLL_BYPASS,Select the main oscillator clock rather than the PLL generated clock as the functional clock (PLL BYPASS mode)" "0,1"
line.long 0x04 "CTRLMMR_WKUP_USART_CLKSEL,Controls the functional clock source for WKUP_USART0"
bitfld.long 0x04 0. "CLK_SEL,WKUP_USART0 FCLK selection" "0,1"
group.long 0x8070++0x03
line.long 0x00 "CTRLMMR_WKUP_GPIO_CLKSEL,Controls the functional clock source for WKUP_GPIO"
bitfld.long 0x00 0.--1. "WAKE_CLK_SEL,WKUP_GPIO clock selection" "MCU_SYSCLK0 / 6,MCU_SYSCLK0 / 6,CLK_32K,CLK_12M_RC"
group.long 0x8080++0x23
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL0_CLKSEL,Controls the clock source for MAIN voltage domain PLL0"
bitfld.long 0x00 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x00 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x00 0. "CLK_SEL,Selects the clock source for MAIN PLL0" "0,1"
line.long 0x04 "CTRLMMR_WKUP_MAIN_PLL1_CLKSEL,Controls the clock source for MAIN voltage domain PLL1"
bitfld.long 0x04 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x04 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x04 0. "CLK_SEL,Selects the clock source for MAIN PLL1" "0,1"
line.long 0x08 "CTRLMMR_WKUP_MAIN_PLL2_CLKSEL,Controls the clock source for MAIN voltage domain PLL2"
bitfld.long 0x08 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x08 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x08 0. "CLK_SEL,Selects the clock source for MAIN PLL2" "0,1"
line.long 0x0C "CTRLMMR_WKUP_MAIN_PLL3_CLKSEL,Controls the clock source for MAIN voltage domain PLL3"
bitfld.long 0x0C 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0C 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x0C 0. "CLK_SEL,Selects the clock source for MAIN PLL3" "0,1"
line.long 0x10 "CTRLMMR_WKUP_MAIN_PLL4_CLKSEL,Controls the clock source for MAIN voltage domain PLL4"
bitfld.long 0x10 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x10 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x10 4. "XREF_SEL,Selects the alternate clock source for MAIN PLL4" "0,1"
bitfld.long 0x10 0. "CLK_SEL,Selects the clock source for MAIN PLL4" "0,1"
line.long 0x14 "CTRLMMR_WKUP_MAIN_PLL5_CLKSEL,Controls the clock source for MAIN voltage domain PLL5"
bitfld.long 0x14 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x14 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x14 0. "CLK_SEL,Selects the clock source for MAIN PLL5" "0,1"
line.long 0x18 "CTRLMMR_WKUP_MAIN_PLL6_CLKSEL,Controls the clock source for MAIN voltage domain PLL6"
bitfld.long 0x18 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x18 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x18 0. "CLK_SEL,Selects the clock source for MAIN PLL6" "0,1"
line.long 0x1C "CTRLMMR_WKUP_MAIN_PLL7_CLKSEL,Controls the clock source for MAIN voltage domain PLL7"
bitfld.long 0x1C 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x1C 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x1C 0. "CLK_SEL,Selects the clock source for MAIN PLL7" "0,1"
line.long 0x20 "CTRLMMR_WKUP_MAIN_PLL8_CLKSEL,Controls the clock source for MAIN voltage domain PLL8"
bitfld.long 0x20 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x20 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x20 0. "CLK_SEL,Selects the clock source for MAIN PLL8" "0,1"
group.long 0x80B0++0x1F
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL12_CLKSEL,Controls the clock source for MAIN voltage domain PLL12"
bitfld.long 0x00 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x00 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x00 0. "CLK_SEL,Selects the clock source for MAIN PLL12" "0,1"
line.long 0x04 "CTRLMMR_WKUP_MAIN_PLL13_CLKSEL,Controls the clock source for MAIN voltage domain PLL13"
bitfld.long 0x04 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x04 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x04 0. "CLK_SEL,Selects the clock source for MAIN PLL13" "0,1"
line.long 0x08 "CTRLMMR_WKUP_MAIN_PLL14_CLKSEL,Controls the clock source for MAIN voltage domain PLL14"
bitfld.long 0x08 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x08 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x08 0. "CLK_SEL,Selects the clock source for MAIN PLL14" "0,1"
line.long 0x0C "CTRLMMR_WKUP_MAIN_PLL15_CLKSEL,Controls the clock source for MAIN voltage domain PLL15"
bitfld.long 0x0C 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x0C 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x0C 4. "XREF_SEL,Selects the alternate clock source for MAIN PLL15" "0,1"
bitfld.long 0x0C 0. "CLK_SEL,Selects the clock source for MAIN PLL15" "0,1"
line.long 0x10 "CTRLMMR_WKUP_MAIN_PLL16_CLKSEL,Controls the clock source for MAIN voltage domain PLL16"
bitfld.long 0x10 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x10 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x10 0. "CLK_SEL,Selects the clock source for MAIN PLL16" "0,1"
line.long 0x14 "CTRLMMR_WKUP_MAIN_PLL17_CLKSEL,Controls the clock source for MAIN voltage domain PLL17"
bitfld.long 0x14 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x14 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x14 0. "CLK_SEL,Selects the clock source for MAIN PLL17" "0,1"
line.long 0x18 "CTRLMMR_WKUP_MAIN_PLL18_CLKSEL,Controls the clock source for MAIN voltage domain PLL18"
bitfld.long 0x18 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x18 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x18 0. "CLK_SEL,Selects the clock source for MAIN PLL18" "0,1"
line.long 0x1C "CTRLMMR_WKUP_MAIN_PLL19_CLKSEL,Controls the clock source for MAIN voltage domain PLL19"
bitfld.long 0x1C 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x1C 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x1C 0. "CLK_SEL,Selects the clock source for MAIN PLL19" "0,1"
group.long 0x80DC++0x0B
line.long 0x00 "CTRLMMR_WKUP_MAIN_PLL23_CLKSEL,Controls the clock source for MAIN voltage domain PLL23"
bitfld.long 0x00 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x00 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x00 0. "CLK_SEL,Selects the clock source for MAIN PLL23" "0,1"
line.long 0x04 "CTRLMMR_WKUP_MAIN_PLL24_CLKSEL,Controls the clock source for MAIN voltage domain PLL24"
bitfld.long 0x04 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x04 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x04 0. "CLK_SEL,Selects the clock source for MAIN PLL24" "0,1"
line.long 0x08 "CTRLMMR_WKUP_MAIN_PLL25_CLKSEL,Controls the clock source for MAIN voltage domain PLL25"
bitfld.long 0x08 31. "BYPASS_SW_OVRD,PLL Bypass warm reset software override" "0,1"
bitfld.long 0x08 23. "BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
newline
bitfld.long 0x08 0. "CLK_SEL,Selects the clock source for MAIN PLL25" "0,1"
group.long 0x8100++0x03
line.long 0x00 "CTRLMMR_WKUP_MAIN_SYSCLK_CTRL,Controls clock gating of the MAIN PLL Controller SYSCLK outputs"
bitfld.long 0x00 8. "SYSCLK1_GATE,When set gates off SYSCLK1 output of the MAIN PLL Controller" "0,1"
bitfld.long 0x00 0. "SYSCLK0_GATE,When set gates off SYSCLK0 (MCLK1) output of the MAIN PLL Controller" "0,1"
group.long 0x8110++0x07
line.long 0x00 "CTRLMMR_WKUP_MCU_SPI0_CLKSEL,MCU_SPI0 clock control"
bitfld.long 0x00 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
line.long 0x04 "CTRLMMR_WKUP_MCU_SPI1_CLKSEL,MCU_SPI1 clock control"
bitfld.long 0x04 16. "MSTR_LB_CLKSEL,Master mode receive capture clock loopback selection" "0,1"
group.long 0x9008++0x07
line.long 0x00 "CTRLMMR_WKUP_LOCK2_KICK0,Lower 32-bits of Partition2 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LOCK2_KICK1,Upper 32-bits of Partition 2 write lock key"
rgroup.long 0xC280++0x03
line.long 0x00 "CTRLMMR_WKUP_DMSC_LBIST_SIG,Contains expected MISR output value"
rgroup.long 0xC2C0++0x03
line.long 0x00 "CTRLMMR_WKUP_POST_STAT,Contains the result of power-on self tests"
bitfld.long 0x00 17. "FPOST_PLL_LOCK_TIMEOUT,Indicates PLL lock timeout for Fast POST mode operation" "0,1"
bitfld.long 0x00 16. "FPOST_PLL_LOCKLOSS,Indicates if PLL lock was lost during POST" "0,1"
newline
bitfld.long 0x00 15. "POST_MCU_PBIST_FAIL,MCU PBIST failed" "0,1"
bitfld.long 0x00 9. "POST_MCU_PBIST_TIMEOUT,MCU PBIST timed out" "0,1"
newline
bitfld.long 0x00 8. "POST_MCU_PBIST_DONE,MCU PBIST done" "0,1"
bitfld.long 0x00 5. "POST_MCU_LBIST_TIMEOUT,MCU LBIST timed out" "0,1"
newline
bitfld.long 0x00 4. "POST_DMSC_LBIST_TIMEOUT,DMSC LBIST timed out" "0,1"
bitfld.long 0x00 1. "POST_MCU_LBIST_DONE,MCU LBIST done" "0,1"
newline
bitfld.long 0x00 0. "POST_DMSC_LBIST_DONE,DMSC LBIST done" "0,1"
rgroup.long 0xC320++0x03
line.long 0x00 "CTRLMMR_WKUP_FUSE_CRC_STAT,Indicates status of fuse chain CRC"
bitfld.long 0x00 7. "CRC_ERR_7,Indicates eFuse CRC error on chain 7" "0,1"
bitfld.long 0x00 6. "CRC_ERR_6,Indicates eFuse CRC error on chain 6" "0,1"
newline
bitfld.long 0x00 4. "CRC_ERR_4,Indicates eFuse CRC error on chain 4" "0,1"
bitfld.long 0x00 3. "CRC_ERR_3,Indicates eFuse CRC error on chain 3" "0,1"
newline
bitfld.long 0x00 2. "CRC_ERR_2,Indicates eFuse CRC error on chain 2" "0,1"
bitfld.long 0x00 1. "CRC_ERR_1,Indicates eFuse CRC error on chain 1" "0,1"
group.long 0xD008++0x07
line.long 0x00 "CTRLMMR_WKUP_LOCK3_KICK0,Lower 32-bits of Partition3 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LOCK3_KICK1,Upper 32-bits of Partition 3 write lock key"
group.long 0x18000++0x1B
line.long 0x00 "CTRLMMR_WKUP_POR_CTRL,Configures POR module reset behavior"
bitfld.long 0x00 29. "OVRD_SET5,Reserved override set" "0,1"
bitfld.long 0x00 28. "OVRD_SET4,POKLVB override set" "0,1"
newline
bitfld.long 0x00 27. "OVRD_SET3,POKLVA override set" "0,1"
bitfld.long 0x00 26. "OVRD_SET2,POKHV override set" "0,1"
newline
bitfld.long 0x00 25. "OVRD_SET1,BGOK override set" "0,1"
bitfld.long 0x00 24. "OVRD_SET0,PORHV override set" "0,1"
newline
bitfld.long 0x00 21. "OVRD5,Reserved override enable" "0,1"
bitfld.long 0x00 20. "OVRD4,POKLVB override enable" "0,1"
newline
bitfld.long 0x00 19. "OVRD3,POKLVA override enable" "0,1"
bitfld.long 0x00 18. "OVRD2,POKHV override enable" "0,1"
newline
bitfld.long 0x00 17. "OVRD1,BGOK override enable" "0,1"
bitfld.long 0x00 16. "OVRD0,PORHV override enable" "0,1"
newline
bitfld.long 0x00 7. "TRIM_SEL,POR Trim Select" "0,1"
bitfld.long 0x00 4. "MASK_HHV,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1"
line.long 0x04 "CTRLMMR_WKUP_POR_STAT,Shows POR module status"
bitfld.long 0x04 8. "BGOK,Bandgap OK status" "0,1"
bitfld.long 0x04 4. "SOC_POR,POR module status" "0,1"
line.long 0x08 "CTRLMMR_WKUP_PRG0_CTRL,Configures the WKUP domain PRG0 controller"
bitfld.long 0x08 15. "POK_EN_SEL,Select POK enable source" "0,1"
bitfld.long 0x08 13. "POK_VDDR_MCU_OV_EN,Enable VDDR_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x08 12. "POK_VDDSHV_WKUP_GEN_OV_EN,Enable VDDSHV_WKUP_GENERAL overvoltage POK detection" "0,1"
bitfld.long 0x08 10. "POK_VDD_MCU_OV_EN,Enable VDD_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x08 5. "POK_VDDR_MCU_UV_EN,Enable VDDR_MCU undervoltage POK detection" "0,1"
bitfld.long 0x08 4. "POK_VDDSHV_WKUP_GEN_UV_EN,Enable VDDSHV_WKUP_GENERAL undervoltage POK detection" "0,1"
newline
bitfld.long 0x08 1. "POK_VDDA_PMIC_IN_EN,Enable VDDA_PMIC_IN POK detection" "0,1"
line.long 0x0C "CTRLMMR_WKUP_PRG0_STAT,Provides WKUP domain PRG0 controller status and status clear control"
bitfld.long 0x0C 31. "POK_CLR,When set resets pgood sticky bits for VDDA_PMIC_IN VDDR_MCU VDDSHV_WKUP_GENERAL and VDD_MCU_OV voltage POK detection" "0,1"
rbitfld.long 0x0C 13. "POK_VDDR_MCU_OV,VDDR_MCU overvoltage POK" "0,1"
newline
rbitfld.long 0x0C 12. "POK_VDDSHV_WKUP_GEN_OV,VDDSHV_WKUP_GENERAL overvoltage POK" "0,1"
rbitfld.long 0x0C 10. "POK_VDD_MCU_OV,VDD_MCU overvoltage POK" "0,1"
newline
rbitfld.long 0x0C 5. "POK_VDDR_MCU_UV,VDDR_MCU undervoltage POK" "0,1"
rbitfld.long 0x0C 4. "POK_VDDSHV_WKUP_GEN_UV,VDDSHV_WKUP_GENERAL undervoltage POK" "0,1"
newline
rbitfld.long 0x0C 1. "POK_VDDA_PMIC_IN,VDDA_PMIC_IN POK" "0,1"
line.long 0x10 "CTRLMMR_WKUP_POK_VDDA_PMIC_IN_CTRL,Controls operation of the VDDA_PMIC_IN POK module"
bitfld.long 0x10 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x10 0. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
line.long 0x14 "CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_UV_CTRL,Controls operation of the VDDSHV_WKUP_GENERAL undervoltage POK module"
bitfld.long 0x14 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x14 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x18 "CTRLMMR_WKUP_POK_VDDR_MCU_UV_CTRL,Controls operation of the VDDR_MCU undervoltage POK module"
bitfld.long 0x18 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x18 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "POK_TRIM,POK trim bits"
group.long 0x18020++0x0B
line.long 0x00 "CTRLMMR_WKUP_POK_VDD_MCU_OV_CTRL,Controls operation of the VDD_MCU overvoltage POK module"
bitfld.long 0x00 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x00 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x04 "CTRLMMR_WKUP_POK_VDDSHV_WKUP_GEN_OV_CTRL,Controls operation of the VDDSHV_WKUP_GENERAL overvoltage POK module"
bitfld.long 0x04 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x04 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x04 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x08 "CTRLMMR_WKUP_POK_VDDR_MCU_OV_CTRL,Controls operation of the VDDR_MCU overvoltage POK module"
bitfld.long 0x08 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x08 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x08 0.--6. 1. "POK_TRIM,POK trim bits"
group.long 0x18058++0x07
line.long 0x00 "CTRLMMR_WKUP_PRG1_CTRL,Configures the WKUP domain PRG1 controller"
bitfld.long 0x00 15. "POK_EN_SEL,Select POK enable source" "0,1"
bitfld.long 0x00 8. "POKHV_OV_EN,Enable 1.8V VDDA_MCU overvoltage POK detection" "0,1"
newline
bitfld.long 0x00 1. "POKLV_UV_EN,Enable VDD_MCU undervoltage POK detection" "0,1"
bitfld.long 0x00 0. "POKHV_UV_EN,Enable 1.8V VDDA_MCU undervoltage POK detection" "0,1"
line.long 0x04 "CTRLMMR_WKUP_PRG1_STAT,Provides WKUP domain PRG1 controller status and status clear control"
bitfld.long 0x04 31. "POK_CLR,When set resets pgood sticky bits for 1.8V VDDA_MCU and VDD_MCU_UV voltage POK detection" "0,1"
rbitfld.long 0x04 8. "POKHV_OV,1.8V VDDA_MCU overvoltage POK" "0,1"
newline
rbitfld.long 0x04 1. "POKLV_UV,VDD_MCU under voltage POK" "0,1"
rbitfld.long 0x04 0. "POKHV_UV,1.8V VDDA_MCU undervoltage POK" "0,1"
group.long 0x18070++0x03
line.long 0x00 "CTRLMMR_WKUP_MAIN_VDOM_CTRL,Provides MAIN voltage domain isolation for deep sleep operation"
bitfld.long 0x00 0. "MAIN_VD_OFF,MAIN deep sleep isolation enable" "0,1"
group.long 0x18080++0x0F
line.long 0x00 "CTRLMMR_WKUP_POR_POKHV_UV_CTRL,Controls operation of the 1.8V VDDA_MCU undervoltage POK within the POR"
bitfld.long 0x00 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x00 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x04 "CTRLMMR_WKUP_POR_POKLV_UV_CTRL,Controls operation of the VDD_MCU undervoltage POK within the POR"
bitfld.long 0x04 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x04 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x04 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x08 "CTRLMMR_WKUP_POR_POKHV_OV_CTRL,Controls operation of the 1.8V VDDA_MCU overvoltage POK within the POR"
bitfld.long 0x08 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x08 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x08 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x0C "CTRLMMR_WKUP_POR_BANDGAP_CTRL,Controls the operation of the bandgap module within the POR"
bitfld.long 0x0C 16.--19. "BGAPI,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x0C 8.--15. 1. "BGAPV,Bandgap output voltage magnitude trim bits"
newline
hexmask.long.byte 0x0C 0.--7. 1. "BGAPC,Bandgap slope trim bits"
group.long 0x180A0++0x03
line.long 0x00 "CTRLMMR_WKUP_TEMP_DIODE_TRIM,Trims the silicon junction temperature diode calculation"
hexmask.long.word 0x00 0.--13. 1. "TRIM,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down"
rgroup.long 0x180B0++0x03
line.long 0x00 "CTRLMMR_WKUP_IO_VOLTAGE_STAT,Indicates the I/O voltage of each LVCMOS dual I/O group"
bitfld.long 0x00 15. "MAIN_RGMII6,Indicates the voltage for the RGMII6 I/O group" "0,1"
bitfld.long 0x00 14. "MAIN_RGMII5,Indicates the voltage for the RGMII5 I/O group" "0,1"
newline
bitfld.long 0x00 13. "MAIN_PRG1,Indicates the voltage for the PRG1 I/O group" "0,1"
bitfld.long 0x00 12. "MAIN_PRG0,Indicates the voltage for the PRG0 I/O group" "0,1"
newline
bitfld.long 0x00 11. "MAIN_MMC2,Indicates the voltage for the MMC2 I/O group" "0,1"
bitfld.long 0x00 10. "MAIN_MMC1,Indicates the voltage for the MMC1 I/O group" "0,1"
newline
bitfld.long 0x00 8. "MAIN_GEN,Indicates the voltage for the General I/O group" "0,1"
bitfld.long 0x00 2. "MCU_RGMII,Indicates the voltage for the MCU CPSW2G RGMII I/O group" "0,1"
newline
bitfld.long 0x00 1. "MCU_FLASH,Indicates the voltage for the MCU Flash I/O group" "0,1"
bitfld.long 0x00 0. "MCU_GEN,Indicates the voltage for the MCU General I/O group" "0,1"
group.long 0x18104++0x2B
line.long 0x00 "CTRLMMR_WKUP_MAIN_POR_TO_CTRL,Indicates the MAIN PORz timeout period"
bitfld.long 0x00 0.--2. "TIMEOUT_PER,MAIN PORz hardware timeout period" "0,1,2,3,4,5,6,7"
line.long 0x04 "CTRLMMR_WKUP_MAIN_PRG_CTRL,Configures the MAIN domain PRG controller"
bitfld.long 0x04 15. "POK_EN_SEL,Select POK enable source" "0,1"
bitfld.long 0x04 14. "POK_VDDR_CORE_OV_EN,Enable VDDR_CORE overvoltage POK detection" "0,1"
newline
bitfld.long 0x04 12. "POK_VMON_EXT_OV_EN,Enable VMON_EXT overvoltage POK detection" "0,1"
bitfld.long 0x04 9. "POK_VDD_CPU_OV_EN,Enable VDD_CORE overvoltage POK detection" "0,1"
newline
bitfld.long 0x04 8. "POK_VDD_CORE_OV_EN,Enable VDD_CORE overvoltage POK detection" "0,1"
bitfld.long 0x04 6. "POK_VDDR_CORE_UV_EN,Enable VDDR_CORE undervoltage POK detection" "0,1"
newline
bitfld.long 0x04 4. "POK_VMON_EXT_UV_EN,Enable VMON_EXT undervoltage POK detection" "0,1"
bitfld.long 0x04 1. "POK_VDD_CPU_UV_EN,Enable VDD_CORE undervoltage POK detection" "0,1"
newline
bitfld.long 0x04 0. "POK_VDD_CORE_UV_EN,Enable VDD_CORE undervoltage POK detection" "0,1"
line.long 0x08 "CTRLMMR_WKUP_MAIN_PRG_STAT,Provides MAIN domain PRG controller status"
bitfld.long 0x08 31. "POK_CLR,When set resets pgood sticky bits for VDD_CORE VDD_CPU VMON_EXT and CDDR_CORE voltage POK detection" "0,1"
rbitfld.long 0x08 14. "POK_VDDR_CORE_OV,VDDR_CORE overvoltage POK" "0,1"
newline
rbitfld.long 0x08 12. "POK_VMON_EXT_OV,VMON_EXT overvoltage POK" "0,1"
rbitfld.long 0x08 9. "POK_VDD_CPU_OV,VDD_CPU overvoltage POK" "0,1"
newline
rbitfld.long 0x08 8. "POK_VDD_CORE_OV,VDD_CORE overvoltage POK" "0,1"
rbitfld.long 0x08 6. "POK_VDDR_CORE_UV,VDDR_CORE undervoltage POK" "0,1"
newline
rbitfld.long 0x08 4. "POK_VMON_EXT_UV,VMON_EXT undervoltage POK" "0,1"
rbitfld.long 0x08 1. "POK_VDD_CPU_UV,VDD_CPU undervoltage POK" "0,1"
newline
rbitfld.long 0x08 0. "POK_VDD_CORE_UV,VDD_CORE undervoltage POK" "0,1"
line.long 0x0C "CTRLMMR_WKUP_POK_VDD_CORE_UV_CTRL,Controls operation of the VDD_CORE undervoltage POK module"
bitfld.long 0x0C 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x0C 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x0C 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x10 "CTRLMMR_WKUP_POK_VDD_CPU_UV_CTRL,Controls operation of the VDD_CPU undervoltage POK module"
bitfld.long 0x10 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x10 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x10 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x14 "CTRLMMR_WKUP_POK_VMON_EXT_UV_CTRL,Controls operation of the VMON_EXTC undervoltage POK module"
bitfld.long 0x14 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x14 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x18 "CTRLMMR_WKUP_POK_VDDR_CORE_UV_CTRL,Controls operation of the VDDR_CORE undervoltage POK module"
bitfld.long 0x18 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x18 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x1C "CTRLMMR_WKUP_POK_VDD_CORE_OV_CTRL,Controls operation of the VDD_CORE overvoltage POK module"
bitfld.long 0x1C 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x1C 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x1C 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x20 "CTRLMMR_WKUP_POK_VDD_CPU_OV_CTRL,Controls operation of the VDD_CPU overvoltage POK module"
bitfld.long 0x20 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x20 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x20 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x24 "CTRLMMR_WKUP_POK_VMON_EXT_OV_CTRL,Controls operation of the VMON_EXT overvoltage POK module"
bitfld.long 0x24 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x24 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "POK_TRIM,POK trim bits"
line.long 0x28 "CTRLMMR_WKUP_POK_VDDR_CORE_OV_CTRL,Controls operation of the VDDR_CORE overvoltage POK module"
bitfld.long 0x28 31. "HYST_EN,Enable POK hysteresis" "0,1"
bitfld.long 0x28 7. "OVER_VOLT_DET,Over / under voltage detection mode" "0,1"
newline
hexmask.long.byte 0x28 0.--6. 1. "POK_TRIM,POK trim bits"
group.long 0x18160++0x03
line.long 0x00 "CTRLMMR_WKUP_DEEPSLEEP_CTRL,Used to control IO deepsleep operation"
bitfld.long 0x00 8. "FORCE_DS_MAIN,Force all MAIN IOs into deepsleep mode when set" "0,1"
bitfld.long 0x00 0. "FORCE_DS_WKUP,Force all WKUP IOs into deepsleep mode when set" "0,1"
group.long 0x18170++0x13
line.long 0x00 "CTRLMMR_WKUP_POR_RST_CTRL,Controls MAIN domain power-on reset behavior"
bitfld.long 0x00 24. "MAIN_PORZ_DAISYCHAIN_EN,MAIN PORz daisy-chain event enable" "0,1"
bitfld.long 0x00 16.--19. "SW_MAIN_POR,Main Domain software power-on reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "MAIN_PORZ_DS_STRETCH,DeepSleep mode MAIN PORz stretch" "0,1"
bitfld.long 0x00 0. "POR_RST_ISO_DONE_Z,Reset isolation completion (active low)" "0,1"
line.long 0x04 "CTRLMMR_WKUP_MAIN_WARM_RST_CTRL,Controls warm reset propagation to the MAIN domain"
bitfld.long 0x04 16.--19. "SW_WARMRST,Main Domain software warm reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0. "SOC_WARMRST_ISO_DONE_Z,Reset isolation completion (active low)" "0,1"
line.long 0x08 "CTRLMMR_WKUP_RST_STAT,Shows the reset status"
bitfld.long 0x08 16. "MCU_RST_DONE,Indicates MCU domain reset status" "0,1"
bitfld.long 0x08 0. "MAIN_RST_DONE,Indicates MAIN domain Warm reset status" "0,1"
line.long 0x0C "CTRLMMR_WKUP_MCU_WARM_RST_CTRL,Controls warm reset propagation to the MCU domain"
bitfld.long 0x0C 16.--19. "SW_WARMRST,Chip software warm reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VDD_CPU voltage domain"
bitfld.long 0x10 31. "PWDB,Power down - active low" "0,1"
bitfld.long 0x10 30. "RSTB,Reset - active low" "0,1"
newline
bitfld.long 0x10 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--13. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 0.--5. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x18190++0x0B
line.long 0x00 "CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VDD_CORE voltage domain"
bitfld.long 0x00 31. "PWDB,Power down - active low" "0,1"
bitfld.long 0x00 30. "RSTB,Reset - active low" "0,1"
newline
bitfld.long 0x00 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--13. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VDDR_CORE voltage domain"
bitfld.long 0x04 31. "PWDB,Power down - active low" "0,1"
bitfld.long 0x04 30. "RSTB,Reset - active low" "0,1"
newline
bitfld.long 0x04 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--13. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 0.--5. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VDDR_CPU voltage domain"
bitfld.long 0x08 31. "PWDB,Power down - active low" "0,1"
bitfld.long 0x08 30. "RSTB,Reset - active low" "0,1"
newline
bitfld.long 0x08 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--13. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 0.--5. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x181A0++0x03
line.long 0x00 "CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VDD_CPU voltage domain"
bitfld.long 0x00 8. "THRESH_HI_FLAG,High voltage flag" "0,1"
bitfld.long 0x00 0. "THRESH_LOW_FLAG,Low voltage flag" "0,1"
rgroup.long 0x181B0++0x0B
line.long 0x00 "CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VDD_CORE voltage domain"
bitfld.long 0x00 8. "THRESH_HI_FLAG,High voltage flag" "0,1"
bitfld.long 0x00 0. "THRESH_LOW_FLAG,Low voltage flag" "0,1"
line.long 0x04 "CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VDDR_CPU voltage domain"
bitfld.long 0x04 8. "THRESH_HI_FLAG,High voltage flag" "0,1"
bitfld.long 0x04 0. "THRESH_LOW_FLAG,Low voltage flag" "0,1"
line.long 0x08 "CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VDDR_CORE voltage domain"
bitfld.long 0x08 8. "THRESH_HI_FLAG,High voltage flag" "0,1"
bitfld.long 0x08 0. "THRESH_LOW_FLAG,Low voltage flag" "0,1"
group.long 0x181C0++0x07
line.long 0x00 "CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VDD_MCU voltage domain"
bitfld.long 0x00 31. "PWDB,Power down - active low" "0,1"
bitfld.long 0x00 30. "RSTB,Reset - active low" "0,1"
newline
bitfld.long 0x00 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--13. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL,Controls the voltage glitch detector circuit monitoring the VDDR_MCU voltage domain"
bitfld.long 0x04 31. "PWDB,Power down - active low" "0,1"
bitfld.long 0x04 30. "RSTB,Reset - active low" "0,1"
newline
bitfld.long 0x04 16.--18. "LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--13. "THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 0.--5. "THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x181D0++0x07
line.long 0x00 "CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VDD_MCU voltage domain"
bitfld.long 0x00 8. "THRESH_HI_FLAG,High voltage flag" "0,1"
bitfld.long 0x00 0. "THRESH_LOW_FLAG,Low voltage flag" "0,1"
line.long 0x04 "CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT,Shows the status of the voltage glitch detector circuit monitoring the VDDR_MCU voltage domain"
bitfld.long 0x04 8. "THRESH_HI_FLAG,High voltage flag" "0,1"
bitfld.long 0x04 0. "THRESH_LOW_FLAG,Low voltage flag" "0,1"
group.long 0x19008++0x07
line.long 0x00 "CTRLMMR_WKUP_LOCK6_KICK0,Lower 32-bits of Partition6 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LOCK6_KICK1,Upper 32-bits of Partition 6 write lock key"
group.long 0x1D008++0x07
line.long 0x00 "CTRLMMR_WKUP_LOCK7_KICK0,Lower 32-bits of Partition7 write lock key"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CTRLMMR_WKUP_LOCK7_KICK1,Upper 32-bits of Partition 7 write lock key"
repeat 16. (list 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C130)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
repeat.end
repeat 10. (list 68. 69. 70. 71. 72. 73. 74. 75. 92. 93. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x60 0x64 )
group.long ($2+0x1C110)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output enable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strentgth Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,?,?,?,?,?,?,?,Mux Mode 15"
repeat.end
repeat 4. (list 62. 63. 64. 65. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x1C0F8)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output enable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
newline
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
newline
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
newline
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,?,?,?,?,?,?,?,Mux Mode 15"
repeat.end
repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 66. 67. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x48 0x4C )
group.long ($2+0x1C0C0)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output enable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strentgth Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,?,?,?,?,?,?,?,Mux Mode 15"
repeat.end
repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C080)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output enable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strentgth Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,?,?,?,?,?,?,?,Mux Mode 15"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C040)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output enable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strentgth Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,?,?,?,?,?,?,?,Mux Mode 15"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C000)++0x03
line.long 0x00 "CTRLMMR_WKUP_PADCONFIG$1,Register to control pin configuration and muxing"
bitfld.long 0x00 31. "LOCK,Lock" "0,1"
rbitfld.long 0x00 30. "WKUP_EVT,Wakeup event status" "0,1"
newline
bitfld.long 0x00 29. "WKUP_EN,Wakeup enable" "0,1"
bitfld.long 0x00 28. "DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "0,1"
newline
bitfld.long 0x00 27. "DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "0,1"
bitfld.long 0x00 26. "DSOUT_VAL,Deep Sleep output value" "0,1"
newline
bitfld.long 0x00 25. "DSOUT_DIS,Deep Sleep output enable" "0,1"
bitfld.long 0x00 24. "DS_EN,Deep Sleep override control" "0,1"
newline
bitfld.long 0x00 23. "ISO_BYP,Isolation Bypass" "0,1"
bitfld.long 0x00 22. "ISO_OVR,Isolation Override" "0,1"
newline
bitfld.long 0x00 21. "TX_DIS,Driver Disable" "0,1"
bitfld.long 0x00 19.--20. "DRV_STR,Drive Strentgth Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "RXACTIVE,Input enable for the Pad" "0,1"
bitfld.long 0x00 17. "PULLTYPESEL,Pad Pullup / Pulldown type selection" "0,1"
newline
bitfld.long 0x00 16. "PULLUDEN,Pad Pullup / Pulldown enable" "0,1"
bitfld.long 0x00 15. "FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "0,1"
newline
bitfld.long 0x00 14. "ST_EN,Receiver Schmitt Trigger enable" "0,1"
bitfld.long 0x00 11.--13. "DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--5. "VGPIO_SEL,Virtual WKUP_GPIO instance select" "Implement GPIO in GPIO_WKUP_0 instance,Implement GPIO in GPIO_WKUP_1 instance,?..."
bitfld.long 0x00 0.--3. "MUXMODE,Pad functional signal mux selection" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,?,?,?,?,?,?,?,Mux Mode 15"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x20)++0x03
line.long 0x00 "CTRLMMR_WKUP_DIE_ID$1,Contains information to identify this particular die"
repeat.end
tree.end
tree.end
tree "WKUP_GPIOMUX_INTRTR0"
tree "C66SS0_INTROUTER0_INTR_ROUTER_CFG"
base ad:0xAC0000
rgroup.long 0x00++0x07
line.long 0x00 "C66SS0_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "C66SS0_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "C66SS1_INTROUTER0_INTR_ROUTER_CFG"
base ad:0xAD0000
rgroup.long 0x00++0x07
line.long 0x00 "C66SS1_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "C66SS1_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "GPIOMUX_INTRTR0_INTR_ROUTER_CFG"
base ad:0xA00000
rgroup.long 0x00++0x07
line.long 0x00 "GPIOMUX_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "GPIOMUX_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "MAIN2MCU_LVL_INTRTR0_CFG"
base ad:0xA10000
rgroup.long 0x00++0x07
line.long 0x00 "MAIN2MCU_LVL_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "MAIN2MCU_LVL_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "MAIN2MCU_PLS_INTRTR0_CFG"
base ad:0xA20000
rgroup.long 0x00++0x07
line.long 0x00 "MAIN2MCU_PLS_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "MAIN2MCU_PLS_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "R5FSS0_INTROUTER0_INTR_ROUTER_CFG"
base ad:0xA60000
rgroup.long 0x00++0x07
line.long 0x00 "R5FSS0_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "R5FSS0_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "R5FSS1_INTROUTER0_INTR_ROUTER_CFG"
base ad:0xA70000
rgroup.long 0x00++0x07
line.long 0x00 "R5FSS1_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "R5FSS1_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.word 0x04 0.--8. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree "WKUP_GPIOMUX_INTRTR0_CFG"
base ad:0x42200000
rgroup.long 0x00++0x07
line.long 0x00 "WKUP_GPIOMUX_INTRTR0_PID,Peripheral identification register"
line.long 0x04 "WKUP_GPIOMUX_INTRTR0_MUXCNTL_n,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,Enable for interrupt output N" "0,1"
hexmask.long.byte 0x04 0.--6. 1. "ENABLE,Mux control for interrupt output N"
tree.end
tree.end
tree "WKUP_VTM0"
tree "WKUP_VTM0_ECCAGGR_CFG"
base ad:0x42810000
rgroup.long 0x00++0x03
line.long 0x00 "WKUP_VTM_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "WKUP_VTM_VECTOR,ECC Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "WKUP_VTM_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "WKUP_VTM_RESERVED_SVBUS_y,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "WKUP_VTM_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "WKUP_VTM_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "WKUP_VTM_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "WKUP_VTM_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "WKUP_VTM_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "WKUP_VTM_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 0. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "WKUP_VTM_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 0. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "WKUP_VTM_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 3. "K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 0. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "WKUP_VTM_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "WKUP_VTM_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "WKUP_VTM_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "WKUP_VTM_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "WKUP_VTM0_MMR_VBUSP_CFG1"
base ad:0x42040000
rgroup.long 0x00++0x07
line.long 0x00 "WKUP_VTM_PID,VTM Peripheral Identification Register"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business unit - Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module functional identifier - CTRL MMR"
bitfld.long 0x00 11.--15. "R_RTL,RTL revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number - actual value determined by RTL" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision number - actual value determined by RTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "WKUP_VTM_DEVINFO_PWR0,Device specific voltage domain and temp sensor information register"
bitfld.long 0x04 16.--19. "VTM_VD_MAP,Core voltage domain cVD global mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12. "VD_RTC,RTC voltage domain presence" "0,1"
bitfld.long 0x04 4.--7. "TMPSENS_CT,Number of temperature sensors associated with this VTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "CVD_CT,Number of core voltage domains in device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x100++0x13
line.long 0x00 "WKUP_VTM_VD_DEVINFO_j,Voltage domain a information register"
bitfld.long 0x00 12. "AVS0_SUP,Indicates VD0 AVS class0 support" "0,1"
rbitfld.long 0x00 8.--11. "VD_MAP,Indicates the core voltage domain mapping of VTM VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "WKUP_VTM_VD_OPPVID_j,Voltage domain a VID actual code used as reference by Firmware to set the various voltage domain supply voltages"
hexmask.long.byte 0x04 24.--31. 1. "OPP_3,OPP 3 default VID"
hexmask.long.byte 0x04 16.--23. 1. "OPP_2,OPP 2 default VID"
hexmask.long.byte 0x04 8.--15. 1. "OPP_1,OPP 1 default VID"
hexmask.long.byte 0x04 0.--7. 1. "OPP_0,OPP 0 default VID"
line.long 0x08 "WKUP_VTM_VD_EVT_STAT_j,Voltage domain a event and control status register"
bitfld.long 0x08 2. "LT_TH0_ALERT,This bit reflects the status of the TH0 undertemp alert resulting from the AND of all the similar alerts produced by the temp sensors selected by VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel" "0,1"
bitfld.long 0x08 1. "GT_TH2_ALERT,This bit reflects the status of the merged temperature alert resulting from the combination of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel" "0,1"
bitfld.long 0x08 0. "GT_TH1_ALERT,This bit reflects the status of the merged temperature alert resulting from the OR of all the similar alerts produced by the temp-monitors selected as showed in field VTM_VD[a]_EVT_SEL_SET.tsens_evt_sel" "0,1"
line.long 0x0C "WKUP_VTM_VD_EVT_SEL_SET_j,Voltage domain a event select and control set register"
hexmask.long.byte 0x0C 16.--23. 1. "TSENS_EVT_SEL,In this field we select which of the event contributions of"
line.long 0x10 "WKUP_VTM_VD_EVT_SEL_CLR_j,Voltage domain a event select and control clear register"
hexmask.long.byte 0x10 16.--23. 1. "TSENS_EVT_SEL,In this field we select which of the event contributions of"
group.long 0x204++0x07
line.long 0x00 "WKUP_VTM_GT_TH1_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt GT_TH1 for each voltage domain"
hexmask.long.byte 0x00 0.--7. 1. "INT_VD,Interrupt pending bit set for gt_th1_int from VD"
line.long 0x04 "WKUP_VTM_GT_TH1_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt GT_TH1 per voltage domain"
hexmask.long.byte 0x04 0.--7. 1. "INT_VD,Interrupt masked pending bit for gt_th1_int from VD"
group.long 0x214++0x07
line.long 0x00 "WKUP_VTM_GT_TH1_INT_EN_SET,Enable set MMR for interrupt GT_TH1 for each voltage domain"
hexmask.long.byte 0x00 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th1_int from VD"
line.long 0x04 "WKUP_VTM_GT_TH1_INT_EN_CLR,Enable clear MMR for interrupt GT_TH1 for each voltage domain"
hexmask.long.byte 0x04 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th1_int from VD"
group.long 0x224++0x07
line.long 0x00 "WKUP_VTM_GT_TH2_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt GT_TH2 for each voltage domain"
hexmask.long.byte 0x00 0.--7. 1. "INT_VD,Interrupt pending bit set for gt_th2_int from VD"
line.long 0x04 "WKUP_VTM_GT_TH2_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt GT_TH2 per voltage domain"
hexmask.long.byte 0x04 0.--7. 1. "INT_VD,Interrupt enabled pending bit for gt_th2_int from VD"
group.long 0x234++0x07
line.long 0x00 "WKUP_VTM_GT_TH2_INT_EN_SET,Enable set MMR for interrupt GT_TH2 for each voltage domain"
hexmask.long.byte 0x00 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th2_int from VD"
line.long 0x04 "WKUP_VTM_GT_TH2_INT_EN_CLR,Enable clear MMR for interrupt GT_TH2 for each voltage domain"
hexmask.long.byte 0x04 0.--7. 1. "INT_VD,Interrupt enable bit for gt_th2_int from VD"
group.long 0x244++0x07
line.long 0x00 "WKUP_VTM_LT_TH0_INT_RAW_STAT_SET,Interrupt RAW event status and set MMR for interrupt LT_TH0 for each voltage domain"
hexmask.long.byte 0x00 0.--7. 1. "INT_VD,Interrupt pending bit set for lt_th0_int from VD"
line.long 0x04 "WKUP_VTM_LT_TH0_INT_EN_STAT_CLR,Enabled interrupt event status and clear MMR for interrupt LT_TH0 per voltage domain"
hexmask.long.byte 0x04 0.--7. 1. "INT_VD,Interrupt enabled pending status bit for lt_th0_int from VD"
group.long 0x254++0x07
line.long 0x00 "WKUP_VTM_LT_TH0_INT_EN_SET,Enable set MMR for interrupt LT_TH0 for each voltage domain"
hexmask.long.byte 0x00 0.--7. 1. "INT_VD,Interrupt enable bit for lt_th0_int from VD"
line.long 0x04 "WKUP_VTM_LT_TH0_INT_EN_CLR,Enable clear MMR for interrupt LT_TH0 for each voltage domain"
hexmask.long.byte 0x04 0.--7. 1. "INT_VD,Interrupt enable bit for lt_th0_int from VD"
group.long 0x300++0x03
line.long 0x00 "WKUP_VTM_TMPSENS_CTRL_j,Temperature Sensor Band-gap control register for sensor a"
bitfld.long 0x00 10. "LT_TH0_EN,Enable under-threshold0 event" "0,1"
bitfld.long 0x00 9. "GT_TH2_EN,Enable over-threshold2 event" "0,1"
bitfld.long 0x00 8. "GT_TH1_EN,Enable over-threshold1 event" "0,1"
rgroup.long 0x308++0x0B
line.long 0x00 "WKUP_VTM_TMPSENS_STAT_j,Temperature Sensor Band-gap Status register for sensor a"
bitfld.long 0x00 16.--19. "VD_MAP,Indicates the core voltage domain placement of the temp sensor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "MAXT_OUTRG_ALERT,This bit will be driven to a level 1 for a given temperature monitor if it has its corresponding bit maxt_outrg_en = 1 and the temperature reading is reporting to be outside the max temperature supported temp > programmed value" "0,1"
bitfld.long 0x00 14. "LT_TH0_ALERT,This field reflects the status of the lt_th0_alert comparator result" "0,1"
bitfld.long 0x00 13. "GT_TH2_ALERT,This field reflects the status of the gt_th2_alert comparator result" "0,1"
bitfld.long 0x00 12. "GT_TH1_ALERT,This field reflects the status of the gt_th1_alert comparator result" "0,1"
newline
bitfld.long 0x00 11. "EOC_FC_UPDATE,First time end of conversion" "0,1"
bitfld.long 0x00 10. "DATA_VALID,Data_valid signal value from sensor: ADC End of Conversion" "0,1"
hexmask.long.word 0x00 0.--9. 1. "DATA_OUT,Data_out signal value from sensor: Temperature data from the ADC in monitor"
line.long 0x04 "WKUP_VTM_TMPSENS_TH_j,Temperature Sensor Band-gap Threshold register for sensor a"
hexmask.long.word 0x04 16.--25. 1. "TH1_VAL,Threshold point-1 thpt1 temp-value"
hexmask.long.word 0x04 0.--9. 1. "TH0_VAL,Threshold point-0 thpt0 temp-value"
line.long 0x08 "WKUP_VTM_TMPSENS_TH2_j,Temperature Sensor Band-gap Threshold register 2 for sensor a"
hexmask.long.word 0x08 0.--9. 1. "TH2_VAL,Threshold point-2 thpt2 temp-value"
tree.end
tree "WKUP_VTM0_MMR_VBUSP_CFG2"
base ad:0x42040000
group.long 0x10008++0x0B
line.long 0x00 "WKUP_VTM_CLK_CTRL,VTM clock related control MMR"
bitfld.long 0x00 31. "TSENS_CLK_SEL,Temperature sensor clock source selector" "0,1"
bitfld.long 0x00 0.--4. "TSENS_CLK_DIV,Temperature sensor clock source divider selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "WKUP_VTM_MISC_CTRL,VTM miscellaneous control bits"
bitfld.long 0x04 0. "ANY_MAXT_OUTRG_ALERT_EN,This bit when enabled will cause the VTM's output therm_maxtemp_outrange_alert to be driven high if any of the sources for the maxt_outrg_alert is set high" "0,1"
line.long 0x08 "WKUP_VTM_MISC_CTRL2,VTM miscellaneous control bits"
hexmask.long.word 0x08 16.--25. 1. "MAXT_OUTRG_ALERT_THR0,This defines the global max temperature out of range safe sample value"
hexmask.long.word 0x08 0.--9. 1. "MAXT_OUTRG_ALERT_THR,This defines the global max temperature out of range sample value"
group.long 0x10020++0x03
line.long 0x00 "WKUP_VTM_SAMPLE_CTRL,VTM sample related control MMR"
hexmask.long.word 0x00 0.--15. 1. "SAMPLE_PER_CNT,Temperature sensor sample period count selector"
group.long 0x10300++0x07
line.long 0x00 "WKUP_VTM_TMPSENS_CTRL_j,Temperature Sensor Band-gap control register for sensor a"
bitfld.long 0x00 11. "MAXT_OUTRG_EN,Enable out-of-range event" "0,1"
bitfld.long 0x00 6. "CLRZ,Temp-Monitor control" "0,1"
bitfld.long 0x00 5. "SOC,Temp-Monitor control: ADC Start of Conversion" "0,1"
bitfld.long 0x00 4. "CONT,Temp-Monitor control: ADC Continuous mode" "0,1"
line.long 0x04 "WKUP_VTM_TMPSENS_TRIM_j,Temperature Sensor Band-gap trim values register for sensor a"
bitfld.long 0x04 8.--13. "TRIMO,Trim offset bits in the temp sensor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--4. "TRIMG,Trim gain bits in the temp sensor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
endif
else
AUTOINDENT.ON center tree
tree "PRU_ICSSG_CFG"
tree "PRU_ICSSG0_PR1_CFG_SLV"
base ad:0xB026000
rgroup.long 0x00++0x1B
line.long 0x00 "ICSSG_PID_REG,PID Register"
line.long 0x04 "ICSSG_HWDIS_REG,HW Disable Register"
hexmask.long.byte 0x04 0.--7. 1. "HWDIS,Read the state of the efuse bits which drive pr1_hw_disable[7:0]"
line.long 0x08 "ICSSG_GPCFG0_REG,GP Configuration 0 Register"
bitfld.long 0x08 26.--29. "PR1_PRU0_GP_MUX_SEL,Controls the icss_wrap mux sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x08 25. "PRU0_GPO_SH1_SEL,This defines which shadow register is currently getting used for GPO shifting" "0,1"
bitfld.long 0x08 20.--24. "PRU0_GPO_DIV1,Divisor value divide by PRU0_GPO_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 15.--19. "PRU0_GPO_DIV0,Divisor value divide by PRU0_GPO_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x08 13. "PRU0_GPI_SB,PRU0_GPI_SB set when first capture on 1 on r31_status[0]" "0,1"
newline
bitfld.long 0x08 8.--12. "PRU0_GPI_DIV1,Divisor value divide by PRU0_GPI_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 3.--7. "PRU0_GPI_DIV0,Divisor value divide by PRU0_GPI_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 2. "PRU0_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
newline
bitfld.long 0x08 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x0C "ICSSG_GPCFG1_REG,GP Configuration 1 Register"
bitfld.long 0x0C 26.--29. "PR1_PRU1_GP_MUX_SEL,Controls the icss_wrap mux sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x0C 25. "PRU1_GPO_SH1_SEL,This defines which shadow register is currently getting used for GPO shifting" "0,1"
bitfld.long 0x0C 20.--24. "PRU1_GPO_DIV1,Divisor value divide by PRU1_GPO_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 15.--19. "PRU1_GPO_DIV0,Divisor value divide by PRU1_GPO_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x0C 13. "PRU1_GPI_SB,PRU1_GPI_SB set when first capture on 1 on r31_status[0]" "0,1"
newline
bitfld.long 0x0C 8.--12. "PRU1_GPI_DIV1,Divisor value divide by PRU1_GPI_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 3.--7. "PRU1_GPI_DIV0,Divisor value divide by PRU1_GPI_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 2. "PRU1_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
newline
bitfld.long 0x0C 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x10 "ICSSG_CGR_REG,Clock Gating Register"
bitfld.long 0x10 31. "ICSS_STOP_ACK,ICSS" "0,1"
rbitfld.long 0x10 30. "ICSS_STOP_REQ,ICSS" "0,1"
bitfld.long 0x10 29. "ICSS_PWR_IDLE,ICSS" "0,1"
newline
bitfld.long 0x10 17. "IEP_CLK_EN,IEP" "0,1"
rbitfld.long 0x10 16. "IEP_CLK_STOP_ACK,IEP" "0,1"
bitfld.long 0x10 15. "IEP_CLK_STOP_REQ,IEP" "0,1"
newline
bitfld.long 0x10 14. "ECAP_CLK_EN,ECAP" "0,1"
rbitfld.long 0x10 13. "ECAP_CLK_STOP_ACK,ECAP" "0,1"
bitfld.long 0x10 12. "ECAP_CLK_STOP_REQ,ECAP" "0,1"
newline
bitfld.long 0x10 11. "UART_CLK_EN,UART" "0,1"
rbitfld.long 0x10 10. "UART_CLK_STOP_ACK,UART" "0,1"
bitfld.long 0x10 9. "UART_CLK_STOP_REQ,UART" "0,1"
newline
bitfld.long 0x10 8. "INTC_CLK_EN,INTC" "0,1"
rbitfld.long 0x10 7. "INTC_CLK_STOP_ACK,INTC" "0,1"
bitfld.long 0x10 6. "INTC_CLK_STOP_REQ,INTC" "0,1"
line.long 0x14 "ICSSG_GPECFG0_REG,GP Enc Configuration 0 Register"
bitfld.long 0x14 17. "PRU0_GPO_SHIFT_CLK_DONE,Shift Clock Done is active when PRU0_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x14 16. "PRU0_GPO_SHIFT_CLK_HIGH,Shift Clock Stop High" "0,1"
hexmask.long.byte 0x14 8.--15. 1. "PRU0_GPO_SHIFT_CNT,Shift Bit Count"
newline
bitfld.long 0x14 6. "PRU0_GPO_SHIFT_GP_EN,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
bitfld.long 0x14 5. "PRU0_GPO_SHIFT_CLK_FREE,Free Running Clock Mode" "0,1"
bitfld.long 0x14 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
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bitfld.long 0x14 1. "PRU0_GPI_SHIFT_EN,GPI Shift In Enable" "0,1"
bitfld.long 0x14 0. "PRU0_GPI_SB_P,GPI Shift In Start Bit Polarity" "0,1"
line.long 0x18 "ICSSG_GPECFG1_REG,GP Enc Configuration 1 Register"
bitfld.long 0x18 17. "PRU1_GPO_SHIFT_CLK_DONE,Shift Clock Done is active when PRU1_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x18 16. "PRU1_GPO_SHIFT_CLK_HIGH,Shift Clock Stop High" "0,1"
hexmask.long.byte 0x18 8.--15. 1. "PRU1_GPO_SHIFT_CNT,Shift Bit Count"
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bitfld.long 0x18 6. "PRU1_GPO_SHIFT_GP_EN,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
bitfld.long 0x18 5. "PRU1_GPO_SHIFT_CLK_FREE,Free Running Clock Mode" "0,1"
bitfld.long 0x18 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
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bitfld.long 0x18 1. "PRU1_GPI_SHIFT_EN,GPI Shift In Enable" "0,1"
bitfld.long 0x18 0. "PRU1_GPI_SB_P,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x2C++0x0B
line.long 0x00 "ICSSG_MII_RT_REG,MII_RT Event Enable Register"
bitfld.long 0x00 0. "MII_RT_EVENT_EN,Enables the MII_RT Events to the INTC" "0,1"
line.long 0x04 "ICSSG_IEPCLK_REG,IEP Configuration Register"
bitfld.long 0x04 1. "IEP1_SLV_EN,IEP1 Master Counter Slave enable" "0,1"
bitfld.long 0x04 0. "IEP_OCP_CLK_EN,Defines the source of the IEP CLK" "0,1"
line.long 0x08 "ICSSG_SPP_REG,Scratchpad Priority and Shift Register"
bitfld.long 0x08 3. "RTU_XFR_SHIFT_EN,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations" "0,1"
bitfld.long 0x08 2. "XFR_BYTE_SHIFT_EN,Shift enable using R0[6:0] to define the number of 8-bit offset for XIN and XOUT operations" "0,1"
bitfld.long 0x08 1. "XFR_SHIFT_EN,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations" "0,1"
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bitfld.long 0x08 0. "PRU1_PAD_HP_EN,Reserved" "0,1"
group.long 0x3C++0x9F
line.long 0x00 "ICSSG_CORE_SYNC_REG,CoreSync Configuration Register"
bitfld.long 0x00 0. "CORE_VBUSP_SYNC_EN,Defines the source of the internal CORE CLK" "0,1"
line.long 0x04 "ICSSG_SA_MX_REG,SA Mux Selection Register"
bitfld.long 0x04 10.--11. "PWM3_REMAP_EN,PWM3_REMAP_EN controls PRU_ICSSG internal wrapper multiplexing logic" "0,1,2,3"
bitfld.long 0x04 8.--9. "PWM0_REMAP_EN,PWM0_REMAP_EN controls PRU_ICSSG internal wrapper multiplexing logic" "0,1,2,3"
hexmask.long.byte 0x04 0.--7. 1. "SA_MUX_SEL,Reserved"
line.long 0x08 "ICSSG_PRU0_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x08 4. "PRU0_SD_DIVFACTOR_FRAC," "0,1"
bitfld.long 0x08 0.--3. "PRU0_SD_DIVFACTOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ICSSG_PRU0_SD_CLK_SEL_REG0,PRU0 FD. ACC and Clock Selection Register 0"
bitfld.long 0x0C 22. "PRU0_FD_ZERO_MAX_0,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x0C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_0,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16. "PRU0_FD_ZERO_MIN_0,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x0C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_0,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x0C 2. "PRU0_SD_CLK_INV0,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x0C 0.--1. "PRU0_SD_CLK_SEL0,Selects the clock source" "0,1,2,3"
line.long 0x10 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG0,PRU0 FD and Over Sample Size Register 0"
bitfld.long 0x10 23. "PRU0_FD_EN_0,Fast Detect One Enable" "0,1"
bitfld.long 0x10 22. "PRU0_FD_ONE_MAX_0,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x10 17.--21. "PRU0_FD_ONE_MAX_LIMIT_0,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "PRU0_FD_ONE_MIN_0,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x10 11.--15. "PRU0_FD_ONE_MIN_LIMIT_0,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--10. "PRU0_FD_WINDOW_SIZE_0,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,Over Sample Rate"
line.long 0x14 "ICSSG_PRU0_SD_CLK_SEL_REG1,PRU0 FD. ACC and Clock Selection Register 1"
bitfld.long 0x14 22. "PRU0_FD_ZERO_MAX_1,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x14 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_1,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16. "PRU0_FD_ZERO_MIN_1,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x14 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_1,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 4.--5. "PRU0_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x14 2. "PRU0_SD_CLK_INV1,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x14 0.--1. "PRU0_SD_CLK_SEL1,Selects the clock source" "0,1,2,3"
line.long 0x18 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG1,PRU0 FD and Over Sample Size Register 1"
bitfld.long 0x18 23. "PRU0_FD_EN_1,Fast Detect One Enable" "0,1"
bitfld.long 0x18 22. "PRU0_FD_ONE_MAX_1,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x18 17.--21. "PRU0_FD_ONE_MAX_LIMIT_1,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 16. "PRU0_FD_ONE_MIN_1,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x18 11.--15. "PRU0_FD_ONE_MIN_LIMIT_1,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--10. "PRU0_FD_WINDOW_SIZE_1,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 0.--7. 1. "PRU0_SD_SAMPLE_SIZE1,Over Sample Rate"
line.long 0x1C "ICSSG_PRU0_SD_CLK_SEL_REG2,PRU0 FD. ACC and Clock Selection Register 2"
bitfld.long 0x1C 22. "PRU0_FD_ZERO_MAX_2,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x1C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_2,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16. "PRU0_FD_ZERO_MIN_2,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x1C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_2,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 4.--5. "PRU0_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x1C 2. "PRU0_SD_CLK_INV2,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x1C 0.--1. "PRU0_SD_CLK_SEL2,Selects the clock source" "0,1,2,3"
line.long 0x20 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG2,PRU0 FD and Over Sample Size Register 2"
bitfld.long 0x20 23. "PRU0_FD_EN_2,Fast Detect One Enable" "0,1"
bitfld.long 0x20 22. "PRU0_FD_ONE_MAX_2,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x20 17.--21. "PRU0_FD_ONE_MAX_LIMIT_2,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 16. "PRU0_FD_ONE_MIN_2,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x20 11.--15. "PRU0_FD_ONE_MIN_LIMIT_2,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 8.--10. "PRU0_FD_WINDOW_SIZE_2,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--7. 1. "PRU0_SD_SAMPLE_SIZE2,Over Sample Rate"
line.long 0x24 "ICSSG_PRU0_SD_CLK_SEL_REG3,PRU0 FD. ACC and Clock Selection Register 3"
bitfld.long 0x24 22. "PRU0_FD_ZERO_MAX_3,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x24 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_3,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 16. "PRU0_FD_ZERO_MIN_3,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x24 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_3,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 4.--5. "PRU0_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x24 2. "PRU0_SD_CLK_INV3,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x24 0.--1. "PRU0_SD_CLK_SEL3,Selects the clock source" "0,1,2,3"
line.long 0x28 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG3,PRU0 FD and Over Sample Size Register 3"
bitfld.long 0x28 23. "PRU0_FD_EN_3,Fast Detect One Enable" "0,1"
bitfld.long 0x28 22. "PRU0_FD_ONE_MAX_3,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x28 17.--21. "PRU0_FD_ONE_MAX_LIMIT_3,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 16. "PRU0_FD_ONE_MIN_3,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x28 11.--15. "PRU0_FD_ONE_MIN_LIMIT_3,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 8.--10. "PRU0_FD_WINDOW_SIZE_3,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 0.--7. 1. "PRU0_SD_SAMPLE_SIZE3,Over Sample Rate"
line.long 0x2C "ICSSG_PRU0_SD_CLK_SEL_REG4,PRU0 FD. ACC and Clock Selection Register 4"
bitfld.long 0x2C 22. "PRU0_FD_ZERO_MAX_4,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x2C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_4,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 16. "PRU0_FD_ZERO_MIN_4,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x2C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_4,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 4.--5. "PRU0_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x2C 2. "PRU0_SD_CLK_INV4,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x2C 0.--1. "PRU0_SD_CLK_SEL4,Selects the clock source" "0,1,2,3"
line.long 0x30 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG4,PRU0 FD and Over Sample Size Register 4"
bitfld.long 0x30 23. "PRU0_FD_EN_4,Fast Detect One Enable" "0,1"
bitfld.long 0x30 22. "PRU0_FD_ONE_MAX_4,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x30 17.--21. "PRU0_FD_ONE_MAX_LIMIT_4,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 16. "PRU0_FD_ONE_MIN_4,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x30 11.--15. "PRU0_FD_ONE_MIN_LIMIT_4,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 8.--10. "PRU0_FD_WINDOW_SIZE_4,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 0.--7. 1. "PRU0_SD_SAMPLE_SIZE4,Over Sample Rate"
line.long 0x34 "ICSSG_PRU0_SD_CLK_SEL_REG5,PRU0 FD. ACC and Clock Selection Register 5"
bitfld.long 0x34 22. "PRU0_FD_ZERO_MAX_5,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x34 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_5,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 16. "PRU0_FD_ZERO_MIN_5,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x34 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_5,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 4.--5. "PRU0_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x34 2. "PRU0_SD_CLK_INV5,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x34 0.--1. "PRU0_SD_CLK_SEL5,Selects the clock source" "0,1,2,3"
line.long 0x38 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG5,PRU0 FD and Over Sample Size Register 5"
bitfld.long 0x38 23. "PRU0_FD_EN_5,Fast Detect One Enable" "0,1"
bitfld.long 0x38 22. "PRU0_FD_ONE_MAX_5,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x38 17.--21. "PRU0_FD_ONE_MAX_LIMIT_5,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x38 16. "PRU0_FD_ONE_MIN_5,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x38 11.--15. "PRU0_FD_ONE_MIN_LIMIT_5,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 8.--10. "PRU0_FD_WINDOW_SIZE_5,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x38 0.--7. 1. "PRU0_SD_SAMPLE_SIZE5,Over Sample Rate"
line.long 0x3C "ICSSG_PRU0_SD_CLK_SEL_REG6,PRU0 FD. ACC and Clock Selection Register 6"
bitfld.long 0x3C 22. "PRU0_FD_ZERO_MAX_6,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x3C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_6,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 16. "PRU0_FD_ZERO_MIN_6,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x3C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_6,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 4.--5. "PRU0_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x3C 2. "PRU0_SD_CLK_INV6,Optional clock inversion post clock selection multiplexer" "0,1"
newline
bitfld.long 0x3C 0.--1. "PRU0_SD_CLK_SEL6,Selects the clock source" "0,1,2,3"
line.long 0x40 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG6,PRU0 FD and Over Sample Size Register 6"
bitfld.long 0x40 23. "PRU0_FD_EN_6,Fast Detect One Enable" "0,1"
bitfld.long 0x40 22. "PRU0_FD_ONE_MAX_6,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x40 17.--21. "PRU0_FD_ONE_MAX_LIMIT_6,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x40 16. "PRU0_FD_ONE_MIN_6,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x40 11.--15. "PRU0_FD_ONE_MIN_LIMIT_6,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 8.--10. "PRU0_FD_WINDOW_SIZE_6,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x40 0.--7. 1. "PRU0_SD_SAMPLE_SIZE6,Over Sample Rate"
line.long 0x44 "ICSSG_PRU0_SD_CLK_SEL_REG7,PRU0 FD. ACC and Clock Selection Register 7"
bitfld.long 0x44 22. "PRU0_FD_ZERO_MAX_7,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x44 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_7,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 16. "PRU0_FD_ZERO_MIN_7,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x44 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_7,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 4.--5. "PRU0_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x44 2. "PRU0_SD_CLK_INV7,Optional clock inversion post clock selection multiplexer" "0,1"
newline
bitfld.long 0x44 0.--1. "PRU0_SD_CLK_SEL7,Selects the clock source" "0,1,2,3"
line.long 0x48 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG7,PRU0 FD and Over Sample Size Register 7"
bitfld.long 0x48 23. "PRU0_FD_EN_7,Fast Detect One Enable" "0,1"
bitfld.long 0x48 22. "PRU0_FD_ONE_MAX_7,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x48 17.--21. "PRU0_FD_ONE_MAX_LIMIT_7,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 16. "PRU0_FD_ONE_MIN_7,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x48 11.--15. "PRU0_FD_ONE_MIN_LIMIT_7,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 8.--10. "PRU0_FD_WINDOW_SIZE_7,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x48 0.--7. 1. "PRU0_SD_SAMPLE_SIZE7,Over Sample Rate"
line.long 0x4C "ICSSG_PRU0_SD_CLK_SEL_REG8,PRU0 FD. ACC and Clock Selection Register 8"
bitfld.long 0x4C 22. "PRU0_FD_ZERO_MAX_8,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x4C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_8,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 16. "PRU0_FD_ZERO_MIN_8,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x4C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_8,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 4.--5. "PRU0_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x4C 2. "PRU0_SD_CLK_INV8,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x4C 0.--1. "PRU0_SD_CLK_SEL8,Selects the clock source" "0,1,2,3"
line.long 0x50 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG8,PRU0 FD and Over Sample Size Register 8"
bitfld.long 0x50 23. "PRU0_FD_EN_8,Fast Detect One Enable" "0,1"
bitfld.long 0x50 22. "PRU0_FD_ONE_MAX_8,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x50 17.--21. "PRU0_FD_ONE_MAX_LIMIT_8,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 16. "PRU0_FD_ONE_MIN_8,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x50 11.--15. "PRU0_FD_ONE_MIN_LIMIT_8,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 8.--10. "PRU0_FD_WINDOW_SIZE_8,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x50 0.--7. 1. "PRU0_SD_SAMPLE_SIZE8,Over Sample Rate"
line.long 0x54 "ICSSG_PRU1_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x54 4. "PRU1_SD_DIVFACTOR_FRAC," "0,1"
bitfld.long 0x54 0.--3. "PRU1_SD_DIVFACTOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "ICSSG_PRU1_SD_CLK_SEL_REG0,PRU1 FD. ACC and Clock Selection Register 0"
bitfld.long 0x58 22. "PRU1_FD_ZERO_MAX_0,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x58 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_0,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 16. "PRU1_FD_ZERO_MIN_0,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x58 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_0,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x58 2. "PRU1_SD_CLK_INV0,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x58 0.--1. "PRU1_SD_CLK_SEL0,Selects the clock source" "0,1,2,3"
line.long 0x5C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG0,PRU1 FD and Over Sample Size Register 0"
bitfld.long 0x5C 23. "PRU1_FD_EN_0,Fast Detect One Enable" "0,1"
bitfld.long 0x5C 22. "PRU1_FD_ONE_MAX_0,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x5C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_0,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 16. "PRU1_FD_ONE_MIN_0,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x5C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_0,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 8.--10. "PRU1_FD_WINDOW_SIZE_0,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x5C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,Over Sample Rate"
line.long 0x60 "ICSSG_PRU1_SD_CLK_SEL_REG1,PRU1 FD. ACC and Clock Selection Register 1"
bitfld.long 0x60 22. "PRU1_FD_ZERO_MAX_1,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x60 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_1,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 16. "PRU1_FD_ZERO_MIN_1,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x60 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_1,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 4.--5. "PRU1_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x60 2. "PRU1_SD_CLK_INV1,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x60 0.--1. "PRU1_SD_CLK_SEL1,Selects the clock source" "0,1,2,3"
line.long 0x64 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG1,PRU1 FD and Over Sample Size Register 1"
bitfld.long 0x64 23. "PRU1_FD_EN_1,Fast Detect One Enable" "0,1"
bitfld.long 0x64 22. "PRU1_FD_ONE_MAX_1,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x64 17.--21. "PRU1_FD_ONE_MAX_LIMIT_1,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 16. "PRU1_FD_ONE_MIN_1,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x64 11.--15. "PRU1_FD_ONE_MIN_LIMIT_1,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 8.--10. "PRU1_FD_WINDOW_SIZE_1,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x64 0.--7. 1. "PRU1_SD_SAMPLE_SIZE1,Over Sample Rate"
line.long 0x68 "ICSSG_PRU1_SD_CLK_SEL_REG2,PRU1 FD. ACC and Clock Selection Register 2"
bitfld.long 0x68 22. "PRU1_FD_ZERO_MAX_2,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x68 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_2,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 16. "PRU1_FD_ZERO_MIN_2,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x68 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_2,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 4.--5. "PRU1_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x68 2. "PRU1_SD_CLK_INV2,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x68 0.--1. "PRU1_SD_CLK_SEL2,Selects the clock source" "0,1,2,3"
line.long 0x6C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG2,PRU1 FD and Over Sample Size Register 2"
bitfld.long 0x6C 23. "PRU1_FD_EN_2,Fast Detect One Enable" "0,1"
bitfld.long 0x6C 22. "PRU1_FD_ONE_MAX_2,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x6C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_2,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 16. "PRU1_FD_ONE_MIN_2,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x6C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_2,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 8.--10. "PRU1_FD_WINDOW_SIZE_2,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x6C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE2,Over Sample Rate"
line.long 0x70 "ICSSG_PRU1_SD_CLK_SEL_REG3,PRU1 FD. ACC and Clock Selection Register 3"
bitfld.long 0x70 22. "PRU1_FD_ZERO_MAX_3,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x70 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_3,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 16. "PRU1_FD_ZERO_MIN_3,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x70 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_3,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 4.--5. "PRU1_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x70 2. "PRU1_SD_CLK_INV3,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x70 0.--1. "PRU1_SD_CLK_SEL3,Selects the clock source" "0,1,2,3"
line.long 0x74 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG3,PRU1 FD and Over Sample Size Register 3"
bitfld.long 0x74 23. "PRU1_FD_EN_3,Fast Detect One Enable" "0,1"
bitfld.long 0x74 22. "PRU1_FD_ONE_MAX_3,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x74 17.--21. "PRU1_FD_ONE_MAX_LIMIT_3,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 16. "PRU1_FD_ONE_MIN_3,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x74 11.--15. "PRU1_FD_ONE_MIN_LIMIT_3,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 8.--10. "PRU1_FD_WINDOW_SIZE_3,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x74 0.--7. 1. "PRU1_SD_SAMPLE_SIZE3,Over Sample Rate"
line.long 0x78 "ICSSG_PRU1_SD_CLK_SEL_REG4,PRU1 FD. ACC and Clock Selection Register 4"
bitfld.long 0x78 22. "PRU1_FD_ZERO_MAX_4,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x78 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_4,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 16. "PRU1_FD_ZERO_MIN_4,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x78 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_4,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 4.--5. "PRU1_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x78 2. "PRU1_SD_CLK_INV4,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x78 0.--1. "PRU1_SD_CLK_SEL4,Selects the clock source" "0,1,2,3"
line.long 0x7C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG4,PRU1 FD and Over Sample Size Register 4"
bitfld.long 0x7C 23. "PRU1_FD_EN_4,Fast Detect One Enable" "0,1"
bitfld.long 0x7C 22. "PRU1_FD_ONE_MAX_4,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x7C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_4,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 16. "PRU1_FD_ONE_MIN_4,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x7C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_4,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 8.--10. "PRU1_FD_WINDOW_SIZE_4,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x7C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE4,Over Sample Rate"
line.long 0x80 "ICSSG_PRU1_SD_CLK_SEL_REG5,PRU1 FD. ACC and Clock Selection Register 5"
bitfld.long 0x80 22. "PRU1_FD_ZERO_MAX_5,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x80 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_5,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 16. "PRU1_FD_ZERO_MIN_5,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x80 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_5,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 4.--5. "PRU1_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x80 2. "PRU1_SD_CLK_INV5,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x80 0.--1. "PRU1_SD_CLK_SEL5,Selects the clock source" "0,1,2,3"
line.long 0x84 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG5,PRU1 FD and Over Sample Size Register 5"
bitfld.long 0x84 23. "PRU1_FD_EN_5,Fast Detect One Enable" "0,1"
bitfld.long 0x84 22. "PRU1_FD_ONE_MAX_5,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x84 17.--21. "PRU1_FD_ONE_MAX_LIMIT_5,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 16. "PRU1_FD_ONE_MIN_5,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x84 11.--15. "PRU1_FD_ONE_MIN_LIMIT_5,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 8.--10. "PRU1_FD_WINDOW_SIZE_5,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x84 0.--7. 1. "PRU1_SD_SAMPLE_SIZE5,Over Sample Rate"
line.long 0x88 "ICSSG_PRU1_SD_CLK_SEL_REG6,PRU1 FD. ACC and Clock Selection Register 6"
bitfld.long 0x88 22. "PRU1_FD_ZERO_MAX_6,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x88 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_6,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 16. "PRU1_FD_ZERO_MIN_6,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x88 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_6,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 4.--5. "PRU1_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x88 2. "PRU1_SD_CLK_INV6,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x88 0.--1. "PRU1_SD_CLK_SEL6,Selects the clock source" "0,1,2,3"
line.long 0x8C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG6,PRU1 FD and Over Sample Size Register 6"
bitfld.long 0x8C 23. "PRU1_FD_EN_6,Fast Detect One Enable" "0,1"
bitfld.long 0x8C 22. "PRU1_FD_ONE_MAX_6,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x8C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_6,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 16. "PRU1_FD_ONE_MIN_6,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x8C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_6,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 8.--10. "PRU1_FD_WINDOW_SIZE_6,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE6,Over Sample Rate"
line.long 0x90 "ICSSG_PRU1_SD_CLK_SEL_REG7,PRU1 FD. ACC and Clock Selection Register 7"
bitfld.long 0x90 22. "PRU1_FD_ZERO_MAX_7,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x90 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_7,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 16. "PRU1_FD_ZERO_MIN_7,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x90 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_7,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 4.--5. "PRU1_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x90 2. "PRU1_SD_CLK_INV7,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x90 0.--1. "PRU1_SD_CLK_SEL7,Selects the clock source" "0,1,2,3"
line.long 0x94 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG7,PRU1 FD and Over Sample Size Register 7"
bitfld.long 0x94 23. "PRU1_FD_EN_7,Fast Detect One Enable" "0,1"
bitfld.long 0x94 22. "PRU1_FD_ONE_MAX_7,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x94 17.--21. "PRU1_FD_ONE_MAX_LIMIT_7,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x94 16. "PRU1_FD_ONE_MIN_7,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x94 11.--15. "PRU1_FD_ONE_MIN_LIMIT_7,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 8.--10. "PRU1_FD_WINDOW_SIZE_7,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x94 0.--7. 1. "PRU1_SD_SAMPLE_SIZE7,Over Sample Rate"
line.long 0x98 "ICSSG_PRU1_SD_CLK_SEL_REG8,PRU1 FD. ACC and Clock Selection Register 8"
bitfld.long 0x98 22. "PRU1_FD_ZERO_MAX_8,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x98 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_8,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 16. "PRU1_FD_ZERO_MIN_8,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x98 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_8,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 4.--5. "PRU1_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x98 2. "PRU1_SD_CLK_INV8,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x98 0.--1. "PRU1_SD_CLK_SEL8,Selects the clock source" "0,1,2,3"
line.long 0x9C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG8,PRU1 FD and Over Sample Size Register 8"
bitfld.long 0x9C 23. "PRU1_FD_EN_8,Fast Detect One Enable" "0,1"
bitfld.long 0x9C 22. "PRU1_FD_ONE_MAX_8,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x9C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_8,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x9C 16. "PRU1_FD_ONE_MIN_8,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x9C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_8,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 8.--10. "PRU1_FD_WINDOW_SIZE_8,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x9C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE8,Over Sample Rate"
group.long 0xE0++0x3F
line.long 0x00 "ICSSG_PRU0_ED_RX_CFG_REG,PRU0 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,Div factor for divh16"
bitfld.long 0x00 15. "PRU0_ED_RX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
bitfld.long 0x00 4. "PRU0_ED_RX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
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bitfld.long 0x00 3. "PRU0_ED_RX_SB_POL,Defines the polarity of the RX Start Bit" "0,1"
bitfld.long 0x00 0.--2. "PRU0_ED_RX_SAMPLE_SIZE,Over Sample size" "0,1,2,3,4,5,6,7"
line.long 0x04 "ICSSG_PRU0_ED_TX_CFG_REG,PRU0 ED Transmit Global Configuration Register"
hexmask.long.word 0x04 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,Div factor for divh16"
bitfld.long 0x04 15. "PRU0_ED_TX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
rbitfld.long 0x04 10. "PRU0_ENDAT2_CLK_SYNC,Observation of pru<n>_endat2_clk pin state" "0,1"
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rbitfld.long 0x04 9. "PRU0_ENDAT1_CLK_SYNC,Observation of pru<n>_endat1_clk pin state" "0,1"
rbitfld.long 0x04 8. "PRU0_ENDAT0_CLK_SYNC,Observation of pru<n>_endat0_clk pin state" "0,1"
rbitfld.long 0x04 7. "PRU0_ED_BUSY_2,Determines when you can assert tx go for channel 2" "0,1"
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rbitfld.long 0x04 6. "PRU0_ED_BUSY_1,Determines when you can assert tx go for channel 1" "0,1"
rbitfld.long 0x04 5. "PRU0_ED_BUSY_0,Determines when you can assert tx go for channel 0" "0,1"
bitfld.long 0x04 4. "PRU0_ED_TX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
line.long 0x08 "ICSSG_PRU0_ED_CH0_CFG0_REG,PRU0 ED Channel 0 Configuration 0 Register"
bitfld.long 0x08 31. "PRU0_ED_TX_FIFO_SWAP_BITS0,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x08 30. "PRU0_ED_SW_CLK_OUT0,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x08 29. "PRU0_ED_CLK_OUT_OVR_EN0,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x08 28. "PRU0_ED_RX_SNOOP0,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x08 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,RX frame size after SB is detected"
bitfld.long 0x08 11.--15. "PRU0_ED_TX_FRAME_SIZE0,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x08 0.--10. 1. "PRU0_ED_TX_WDLY0,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x0C "ICSSG_PRU0_ED_CH0_CFG1_REG,PRU0 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x0C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x0C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,This counter will start after the tx_wire_delay has been met"
line.long 0x10 "ICSSG_PRU0_ED_CH1_CFG0_REG,PRU0 ED Channel 1 Configuration 0 Register"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,RX frame size after SB is detected"
bitfld.long 0x10 11.--15. "PRU0_ED_TX_FRAME_SIZE1,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x14 "ICSSG_PRU0_ED_CH1_CFG1_REG,PRU0 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,This counter will start after the tx_wire_delay has been met"
line.long 0x18 "ICSSG_PRU0_ED_CH2_CFG0_REG,PRU0 ED Channel 2 Configuration 0 Register"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,RX frame size after SB is detected"
bitfld.long 0x18 11.--15. "PRU0_ED_TX_FRAME_SIZE2,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x1C "ICSSG_PRU0_ED_CH2_CFG1_REG,PRU0 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,This counter will start after the tx_wire_delay has been met"
line.long 0x20 "ICSSG_PRU1_ED_RX_CFG_REG,PRU1 ED Receive Global Configuration Register"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,div factor for divh16"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
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bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL,Defines the polarity of the RX Start Bit" "0,1"
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE,Over Sample size" "0,1,2,3,4,5,6,7"
line.long 0x24 "ICSSG_PRU1_ED_TX_CFG_REG,PRU1 ED Transmit Global Configuration Register"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,div factor for divh16"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC,Observation of pru<n>_endat2_clk pin state" "0,1"
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rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC,Observation of pru<n>_endat1_clk pin state" "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC,Observation of pru<n>_endat0_clk pin state" "0,1"
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2,Determines when you can assert tx go for channel 2" "0,1"
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rbitfld.long 0x24 6. "PRU1_ED_BUSY_1,Determines when you can assert tx go for channel 1" "0,1"
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0,Determines when you can assert tx go for channel 0" "0,1"
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
line.long 0x28 "ICSSG_PRU1_ED_CH0_CFG0_REG,PRU1 ED Channel 0 Configuration 0 Register"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,RX frame size after SB is detected"
bitfld.long 0x28 11.--15. "PRU1_ED_TX_FRAME_SIZE0,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x2C "ICSSG_PRU1_ED_CH0_CFG1_REG,PRU1 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,This counter will start after the tx_wire_delay has been met"
line.long 0x30 "ICSSG_PRU1_ED_CH1_CFG0_REG,PRU1 ED Channel 1 Configuration 0 Register"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,RX frame size after SB is detected"
bitfld.long 0x30 11.--15. "PRU1_ED_TX_FRAME_SIZE1,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x34 "ICSSG_PRU1_ED_CH1_CFG1_REG,PRU1 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,This counter will start after the tx_wire_delay has been met"
line.long 0x38 "ICSSG_PRU1_ED_CH2_CFG0_REG,PRU1 ED Channel 2 Configuration 0 Register"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,RX frame size after SB is detected"
bitfld.long 0x38 11.--15. "PRU1_ED_TX_FRAME_SIZE2,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x3C "ICSSG_PRU1_ED_CH2_CFG1_REG,PRU1 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,This counter will start after the tx_wire_delay has been met"
group.long 0x124++0x03
line.long 0x00 "ICSSG_RTU0_POKE_EN0_REG,RTU0 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. "RTU0_POKE_R27_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RTU0_POKE_R26_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "RTU0_POKE_R25_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RTU0_POKE_R24_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "RTU0_POKE_R23_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RTU0_POKE_R22_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "RTU0_POKE_R21_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RTU0_POKE_R20_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x12C++0x6B
line.long 0x00 "ICSSG_RTU1_POKE_EN0_REG,RTU1 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. "RTU1_POKE_R27_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RTU1_POKE_R26_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "RTU1_POKE_R25_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RTU1_POKE_R24_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "RTU1_POKE_R23_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RTU1_POKE_R22_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "RTU1_POKE_R21_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RTU1_POKE_R20_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ICSSG_PWM0,PWM0 Trip Configuration Register"
bitfld.long 0x04 30. "PWM0_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x04 21.--29. 1. "PWM0_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x04 20. "PWM0_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x04 19. "PWM0_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x04 18. "PWM0_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x04 17. "PWM0_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x04 8.--16. 1. "PWM0_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x04 0.--7. 1. "PWM0_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x08 "ICSSG_PWM1,PWM1 Trip Configuration Register"
bitfld.long 0x08 30. "PWM1_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x08 21.--29. 1. "PWM1_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x08 20. "PWM1_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x08 19. "PWM1_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x08 18. "PWM1_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x08 17. "PWM1_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x08 8.--16. 1. "PWM1_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x08 0.--7. 1. "PWM1_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x0C "ICSSG_PWM2,PWM2 Trip Configuration Register"
bitfld.long 0x0C 30. "PWM2_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x0C 21.--29. 1. "PWM2_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x0C 20. "PWM2_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x0C 19. "PWM2_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x0C 18. "PWM2_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x0C 17. "PWM2_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x0C 8.--16. 1. "PWM2_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x0C 0.--7. 1. "PWM2_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x10 "ICSSG_PWM3,PWM3 Trip Configuration Register"
bitfld.long 0x10 30. "PWM3_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x10 21.--29. 1. "PWM3_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x10 20. "PWM3_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x10 19. "PWM3_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x10 18. "PWM3_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x10 17. "PWM3_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x10 8.--16. 1. "PWM3_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x10 0.--7. 1. "PWM3_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x14 "ICSSG_PWM0_0,PWM0 State Configuration 0 Register"
bitfld.long 0x14 10.--11. "PWM0_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x14 6.--7. "PWM0_0_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x14 4.--5. "PWM0_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x14 2.--3. "PWM0_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x14 0.--1. "PWM0_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x18 "ICSSG_PWM0_1,PWM0 State Configuration 1 Register"
bitfld.long 0x18 10.--11. "PWM0_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x18 8.--9. "PWM0_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x18 6.--7. "PWM0_1_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x18 4.--5. "PWM0_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x18 2.--3. "PWM0_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x18 0.--1. "PWM0_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x1C "ICSSG_PWM0_2,PWM0 State Configuration 2 Register"
bitfld.long 0x1C 10.--11. "PWM0_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x1C 8.--9. "PWM0_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x1C 6.--7. "PWM0_2_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x1C 4.--5. "PWM0_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x1C 2.--3. "PWM0_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x1C 0.--1. "PWM0_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x20 "ICSSG_PWM1_0,PWM1 State Configuration 0 Register"
bitfld.long 0x20 10.--11. "PWM1_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x20 8.--9. "PWM1_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x20 6.--7. "PWM1_0_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x20 4.--5. "PWM1_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x20 2.--3. "PWM1_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x20 0.--1. "PWM1_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x24 "ICSSG_PWM1_1,PWM1 State Configuration 1 Register"
bitfld.long 0x24 10.--11. "PWM1_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x24 8.--9. "PWM1_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x24 6.--7. "PWM1_1_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x24 4.--5. "PWM1_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x24 2.--3. "PWM1_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x24 0.--1. "PWM1_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x28 "ICSSG_PWM1_2,PWM1 State Configuration 2 Register"
bitfld.long 0x28 10.--11. "PWM1_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x28 8.--9. "PWM1_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x28 6.--7. "PWM1_2_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "PWM1_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x28 2.--3. "PWM1_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x28 0.--1. "PWM1_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x2C "ICSSG_PWM2_0,PWM2 State Configuration 0 Register"
bitfld.long 0x2C 10.--11. "PWM2_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x2C 8.--9. "PWM2_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x2C 6.--7. "PWM2_0_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x2C 4.--5. "PWM2_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x2C 2.--3. "PWM2_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x2C 0.--1. "PWM2_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x30 "ICSSG_PWM2_1,PWM2 State Configuration 1 Register"
bitfld.long 0x30 10.--11. "PWM2_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x30 8.--9. "PWM2_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x30 6.--7. "PWM2_1_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x30 4.--5. "PWM2_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x30 2.--3. "PWM2_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x30 0.--1. "PWM2_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x34 "ICSSG_PWM2_2,PWM2 State Configuration 2 Register"
bitfld.long 0x34 10.--11. "PWM2_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x34 8.--9. "PWM2_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x34 6.--7. "PWM2_2_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x34 4.--5. "PWM2_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x34 2.--3. "PWM2_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x34 0.--1. "PWM2_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x38 "ICSSG_PWM3_0,PWM3 State Configuration 0 Register"
bitfld.long 0x38 10.--11. "PWM3_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x38 8.--9. "PWM3_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x38 6.--7. "PWM3_0_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x38 4.--5. "PWM3_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x38 2.--3. "PWM3_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x38 0.--1. "PWM3_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x3C "ICSSG_PWM3_1,PWM3 State Configuration 1 Register"
bitfld.long 0x3C 10.--11. "PWM3_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x3C 8.--9. "PWM3_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x3C 6.--7. "PWM3_1_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x3C 4.--5. "PWM3_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x3C 2.--3. "PWM3_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x3C 0.--1. "PWM3_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x40 "ICSSG_PWM3_2,PWM3 State Configuration 2 Register"
bitfld.long 0x40 10.--11. "PWM3_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x40 8.--9. "PWM3_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x40 6.--7. "PWM3_2_NEG_TRIP,Trip negative state" "0,1,2,3"
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bitfld.long 0x40 4.--5. "PWM3_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x40 2.--3. "PWM3_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x40 0.--1. "PWM3_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x44 "ICSSG_SPIN_LOCK0,Spin Lock 0 Register"
bitfld.long 0x44 8.--13. "MMR_OWN_REQ_VECTOR_0,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x44 1. "MMR_OWN_REQ_CLR_0,Spin Lock Status Clear" "0,1"
rbitfld.long 0x44 0. "MMR_OWN_REQ_STATUS_0,Spin Lock Status" "0,1"
line.long 0x48 "ICSSG_SPIN_LOCK1,Spin Lock 1 Register"
bitfld.long 0x48 8.--13. "MMR_OWN_REQ_VECTOR_1,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x48 1. "MMR_OWN_REQ_CLR_1,Spin Lock Status Clear" "0,1"
rbitfld.long 0x48 0. "MMR_OWN_REQ_STATUS_1,Spin Lock Status" "0,1"
line.long 0x4C "ICSSG_PA_STAT_PDSP_CFG0,PA STATS PRU Vector 0 Register"
bitfld.long 0x4C 31. "PA_PDSP0_INC_TYPE,pa_pdsp0_inc_type" "0,1"
hexmask.long.tbyte 0x4C 14.--30. 1. "PA_PDSP0_INC_VAL,pa_pdsp0_inc_val"
hexmask.long.word 0x4C 0.--13. 1. "PA_PDSP0_INDEX,pa_pdsp0_index"
line.long 0x50 "ICSSG_PA_STAT_PDSP_STAT0,PA STATS PRU Status 0 Register"
bitfld.long 0x50 1.--3. "PA_PDSP0_STATUS,pa_pdsp0_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x50 0. "PA_PDSP0_READY,pa_pdsp0_ready" "0,1"
line.long 0x54 "ICSSG_PA_STAT_PDSP_CFG1,PA STATS PRU Vector 1 Register"
bitfld.long 0x54 31. "PA_PDSP1_INC_TYPE,pa_pdsp1_inc_type" "0,1"
hexmask.long.tbyte 0x54 14.--30. 1. "PA_PDSP1_INC_VAL,pa_pdsp1_inc_val"
hexmask.long.word 0x54 0.--13. 1. "PA_PDSP1_INDEX,pa_pdsp1_index"
line.long 0x58 "ICSSG_PA_STAT_PDSP_STAT1,PA STATS PRU Status 1 Register"
bitfld.long 0x58 1.--3. "PA_PDSP1_STATUS,pa_pdsp1_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x58 0. "PA_PDSP1_READY,pa_pdsp1_ready" "0,1"
line.long 0x5C "ICSSG_PA_STAT_PDSP_CFG2,PA STATS PRU Vector 2 Register"
bitfld.long 0x5C 31. "PA_PDSP2_INC_TYPE,pa_pdsp2_inc_type" "0,1"
hexmask.long.tbyte 0x5C 14.--30. 1. "PA_PDSP2_INC_VAL,pa_pdsp2_inc_val"
hexmask.long.word 0x5C 0.--13. 1. "PA_PDSP2_INDEX,pa_pdsp2_index"
line.long 0x60 "ICSSG_PA_STAT_PDSP_STAT2,PA STATS PRU Status 2 Register"
bitfld.long 0x60 1.--3. "PA_PDSP2_STATUS,pa_pdsp2_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x60 0. "PA_PDSP2_READY,pa_pdsp2_ready" "0,1"
line.long 0x64 "ICSSG_PA_STAT_PDSP_CFG3,PA STATS PRU Vector 3 Register"
bitfld.long 0x64 31. "PA_PDSP3_INC_TYPE,pa_pdsp3_inc_type" "0,1"
hexmask.long.tbyte 0x64 14.--30. 1. "PA_PDSP3_INC_VAL,pa_pdsp3_inc_val"
hexmask.long.word 0x64 0.--13. 1. "PA_PDSP3_INDEX,pa_pdsp3_index"
line.long 0x68 "ICSSG_PA_STAT_PDSP_STAT3,PA STATS PRU Status 3 Register"
bitfld.long 0x68 1.--3. "PA_PDSP3_STATUS,pa_pdsp3_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 0. "PA_PDSP3_READY,pa_pdsp3_ready" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_CFG_SLV"
base ad:0xB126000
rgroup.long 0x00++0x1B
line.long 0x00 "ICSSG_PID_REG,PID Register"
line.long 0x04 "ICSSG_HWDIS_REG,HW Disable Register"
hexmask.long.byte 0x04 0.--7. 1. "HWDIS,Read the state of the efuse bits which drive pr1_hw_disable[7:0]"
line.long 0x08 "ICSSG_GPCFG0_REG,GP Configuration 0 Register"
bitfld.long 0x08 26.--29. "PR1_PRU0_GP_MUX_SEL,Controls the icss_wrap mux sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x08 25. "PRU0_GPO_SH1_SEL,This defines which shadow register is currently getting used for GPO shifting" "0,1"
bitfld.long 0x08 20.--24. "PRU0_GPO_DIV1,Divisor value divide by PRU0_GPO_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 15.--19. "PRU0_GPO_DIV0,Divisor value divide by PRU0_GPO_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x08 13. "PRU0_GPI_SB,PRU0_GPI_SB set when first capture on 1 on r31_status[0]" "0,1"
newline
bitfld.long 0x08 8.--12. "PRU0_GPI_DIV1,Divisor value divide by PRU0_GPI_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 3.--7. "PRU0_GPI_DIV0,Divisor value divide by PRU0_GPI_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 2. "PRU0_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
newline
bitfld.long 0x08 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x0C "ICSSG_GPCFG1_REG,GP Configuration 1 Register"
bitfld.long 0x0C 26.--29. "PR1_PRU1_GP_MUX_SEL,Controls the icss_wrap mux sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x0C 25. "PRU1_GPO_SH1_SEL,This defines which shadow register is currently getting used for GPO shifting" "0,1"
bitfld.long 0x0C 20.--24. "PRU1_GPO_DIV1,Divisor value divide by PRU1_GPO_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 15.--19. "PRU1_GPO_DIV0,Divisor value divide by PRU1_GPO_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x0C 13. "PRU1_GPI_SB,PRU1_GPI_SB set when first capture on 1 on r31_status[0]" "0,1"
newline
bitfld.long 0x0C 8.--12. "PRU1_GPI_DIV1,Divisor value divide by PRU1_GPI_DIV1 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 3.--7. "PRU1_GPI_DIV0,Divisor value divide by PRU1_GPI_DIV0 + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 2. "PRU1_GPI_CLK_MODE,Parallel 16-bit capture mode clock edge" "0,1"
newline
bitfld.long 0x0C 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x10 "ICSSG_CGR_REG,Clock Gating Register"
bitfld.long 0x10 31. "ICSS_STOP_ACK,ICSS" "0,1"
rbitfld.long 0x10 30. "ICSS_STOP_REQ,ICSS" "0,1"
bitfld.long 0x10 29. "ICSS_PWR_IDLE,ICSS" "0,1"
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bitfld.long 0x10 17. "IEP_CLK_EN,IEP" "0,1"
rbitfld.long 0x10 16. "IEP_CLK_STOP_ACK,IEP" "0,1"
bitfld.long 0x10 15. "IEP_CLK_STOP_REQ,IEP" "0,1"
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bitfld.long 0x10 14. "ECAP_CLK_EN,ECAP" "0,1"
rbitfld.long 0x10 13. "ECAP_CLK_STOP_ACK,ECAP" "0,1"
bitfld.long 0x10 12. "ECAP_CLK_STOP_REQ,ECAP" "0,1"
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bitfld.long 0x10 11. "UART_CLK_EN,UART" "0,1"
rbitfld.long 0x10 10. "UART_CLK_STOP_ACK,UART" "0,1"
bitfld.long 0x10 9. "UART_CLK_STOP_REQ,UART" "0,1"
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bitfld.long 0x10 8. "INTC_CLK_EN,INTC" "0,1"
rbitfld.long 0x10 7. "INTC_CLK_STOP_ACK,INTC" "0,1"
bitfld.long 0x10 6. "INTC_CLK_STOP_REQ,INTC" "0,1"
line.long 0x14 "ICSSG_GPECFG0_REG,GP Enc Configuration 0 Register"
bitfld.long 0x14 17. "PRU0_GPO_SHIFT_CLK_DONE,Shift Clock Done is active when PRU0_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x14 16. "PRU0_GPO_SHIFT_CLK_HIGH,Shift Clock Stop High" "0,1"
hexmask.long.byte 0x14 8.--15. 1. "PRU0_GPO_SHIFT_CNT,Shift Bit Count"
newline
bitfld.long 0x14 6. "PRU0_GPO_SHIFT_GP_EN,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
bitfld.long 0x14 5. "PRU0_GPO_SHIFT_CLK_FREE,Free Running Clock Mode" "0,1"
bitfld.long 0x14 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
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bitfld.long 0x14 1. "PRU0_GPI_SHIFT_EN,GPI Shift In Enable" "0,1"
bitfld.long 0x14 0. "PRU0_GPI_SB_P,GPI Shift In Start Bit Polarity" "0,1"
line.long 0x18 "ICSSG_GPECFG1_REG,GP Enc Configuration 1 Register"
bitfld.long 0x18 17. "PRU1_GPO_SHIFT_CLK_DONE,Shift Clock Done is active when PRU1_GPO_SHIFT_CNT is none zero" "0,1"
bitfld.long 0x18 16. "PRU1_GPO_SHIFT_CLK_HIGH,Shift Clock Stop High" "0,1"
hexmask.long.byte 0x18 8.--15. 1. "PRU1_GPO_SHIFT_CNT,Shift Bit Count"
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bitfld.long 0x18 6. "PRU1_GPO_SHIFT_GP_EN,Enable pru<n>r30[15:2] control during shift out mode" "0,1"
bitfld.long 0x18 5. "PRU1_GPO_SHIFT_CLK_FREE,Free Running Clock Mode" "0,1"
bitfld.long 0x18 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
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bitfld.long 0x18 1. "PRU1_GPI_SHIFT_EN,GPI Shift In Enable" "0,1"
bitfld.long 0x18 0. "PRU1_GPI_SB_P,GPI Shift In Start Bit Polarity" "0,1"
group.long 0x2C++0x0B
line.long 0x00 "ICSSG_MII_RT_REG,MII_RT Event Enable Register"
bitfld.long 0x00 0. "MII_RT_EVENT_EN,Enables the MII_RT Events to the INTC" "0,1"
line.long 0x04 "ICSSG_IEPCLK_REG,IEP Configuration Register"
bitfld.long 0x04 1. "IEP1_SLV_EN,IEP1 Master Counter Slave enable" "0,1"
bitfld.long 0x04 0. "IEP_OCP_CLK_EN,Defines the source of the IEP CLK" "0,1"
line.long 0x08 "ICSSG_SPP_REG,Scratchpad Priority and Shift Register"
bitfld.long 0x08 3. "RTU_XFR_SHIFT_EN,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations" "0,1"
bitfld.long 0x08 2. "XFR_BYTE_SHIFT_EN,Shift enable using R0[6:0] to define the number of 8-bit offset for XIN and XOUT operations" "0,1"
bitfld.long 0x08 1. "XFR_SHIFT_EN,Shift enable using R0[4:0] to define the number of 32-bit offset for XIN and XOUT operations" "0,1"
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bitfld.long 0x08 0. "PRU1_PAD_HP_EN,Reserved" "0,1"
group.long 0x3C++0x9F
line.long 0x00 "ICSSG_CORE_SYNC_REG,CoreSync Configuration Register"
bitfld.long 0x00 0. "CORE_VBUSP_SYNC_EN,Defines the source of the internal CORE CLK" "0,1"
line.long 0x04 "ICSSG_SA_MX_REG,SA Mux Selection Register"
bitfld.long 0x04 10.--11. "PWM3_REMAP_EN,PWM3_REMAP_EN controls PRU_ICSSG internal wrapper multiplexing logic" "0,1,2,3"
bitfld.long 0x04 8.--9. "PWM0_REMAP_EN,PWM0_REMAP_EN controls PRU_ICSSG internal wrapper multiplexing logic" "0,1,2,3"
hexmask.long.byte 0x04 0.--7. 1. "SA_MUX_SEL,Reserved"
line.long 0x08 "ICSSG_PRU0_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x08 4. "PRU0_SD_DIVFACTOR_FRAC," "0,1"
bitfld.long 0x08 0.--3. "PRU0_SD_DIVFACTOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "ICSSG_PRU0_SD_CLK_SEL_REG0,PRU0 FD. ACC and Clock Selection Register 0"
bitfld.long 0x0C 22. "PRU0_FD_ZERO_MAX_0,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x0C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_0,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16. "PRU0_FD_ZERO_MIN_0,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x0C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_0,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x0C 2. "PRU0_SD_CLK_INV0,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x0C 0.--1. "PRU0_SD_CLK_SEL0,Selects the clock source" "0,1,2,3"
line.long 0x10 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG0,PRU0 FD and Over Sample Size Register 0"
bitfld.long 0x10 23. "PRU0_FD_EN_0,Fast Detect One Enable" "0,1"
bitfld.long 0x10 22. "PRU0_FD_ONE_MAX_0,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x10 17.--21. "PRU0_FD_ONE_MAX_LIMIT_0,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16. "PRU0_FD_ONE_MIN_0,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x10 11.--15. "PRU0_FD_ONE_MIN_LIMIT_0,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--10. "PRU0_FD_WINDOW_SIZE_0,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,Over Sample Rate"
line.long 0x14 "ICSSG_PRU0_SD_CLK_SEL_REG1,PRU0 FD. ACC and Clock Selection Register 1"
bitfld.long 0x14 22. "PRU0_FD_ZERO_MAX_1,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x14 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_1,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16. "PRU0_FD_ZERO_MIN_1,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x14 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_1,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 4.--5. "PRU0_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x14 2. "PRU0_SD_CLK_INV1,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x14 0.--1. "PRU0_SD_CLK_SEL1,Selects the clock source" "0,1,2,3"
line.long 0x18 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG1,PRU0 FD and Over Sample Size Register 1"
bitfld.long 0x18 23. "PRU0_FD_EN_1,Fast Detect One Enable" "0,1"
bitfld.long 0x18 22. "PRU0_FD_ONE_MAX_1,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x18 17.--21. "PRU0_FD_ONE_MAX_LIMIT_1,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 16. "PRU0_FD_ONE_MIN_1,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x18 11.--15. "PRU0_FD_ONE_MIN_LIMIT_1,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--10. "PRU0_FD_WINDOW_SIZE_1,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x18 0.--7. 1. "PRU0_SD_SAMPLE_SIZE1,Over Sample Rate"
line.long 0x1C "ICSSG_PRU0_SD_CLK_SEL_REG2,PRU0 FD. ACC and Clock Selection Register 2"
bitfld.long 0x1C 22. "PRU0_FD_ZERO_MAX_2,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x1C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_2,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16. "PRU0_FD_ZERO_MIN_2,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x1C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_2,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 4.--5. "PRU0_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x1C 2. "PRU0_SD_CLK_INV2,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x1C 0.--1. "PRU0_SD_CLK_SEL2,Selects the clock source" "0,1,2,3"
line.long 0x20 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG2,PRU0 FD and Over Sample Size Register 2"
bitfld.long 0x20 23. "PRU0_FD_EN_2,Fast Detect One Enable" "0,1"
bitfld.long 0x20 22. "PRU0_FD_ONE_MAX_2,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x20 17.--21. "PRU0_FD_ONE_MAX_LIMIT_2,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 16. "PRU0_FD_ONE_MIN_2,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x20 11.--15. "PRU0_FD_ONE_MIN_LIMIT_2,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 8.--10. "PRU0_FD_WINDOW_SIZE_2,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 0.--7. 1. "PRU0_SD_SAMPLE_SIZE2,Over Sample Rate"
line.long 0x24 "ICSSG_PRU0_SD_CLK_SEL_REG3,PRU0 FD. ACC and Clock Selection Register 3"
bitfld.long 0x24 22. "PRU0_FD_ZERO_MAX_3,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x24 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_3,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 16. "PRU0_FD_ZERO_MIN_3,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x24 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_3,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 4.--5. "PRU0_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x24 2. "PRU0_SD_CLK_INV3,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x24 0.--1. "PRU0_SD_CLK_SEL3,Selects the clock source" "0,1,2,3"
line.long 0x28 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG3,PRU0 FD and Over Sample Size Register 3"
bitfld.long 0x28 23. "PRU0_FD_EN_3,Fast Detect One Enable" "0,1"
bitfld.long 0x28 22. "PRU0_FD_ONE_MAX_3,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x28 17.--21. "PRU0_FD_ONE_MAX_LIMIT_3,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x28 16. "PRU0_FD_ONE_MIN_3,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x28 11.--15. "PRU0_FD_ONE_MIN_LIMIT_3,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 8.--10. "PRU0_FD_WINDOW_SIZE_3,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 0.--7. 1. "PRU0_SD_SAMPLE_SIZE3,Over Sample Rate"
line.long 0x2C "ICSSG_PRU0_SD_CLK_SEL_REG4,PRU0 FD. ACC and Clock Selection Register 4"
bitfld.long 0x2C 22. "PRU0_FD_ZERO_MAX_4,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x2C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_4,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 16. "PRU0_FD_ZERO_MIN_4,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x2C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_4,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 4.--5. "PRU0_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x2C 2. "PRU0_SD_CLK_INV4,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x2C 0.--1. "PRU0_SD_CLK_SEL4,Selects the clock source" "0,1,2,3"
line.long 0x30 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG4,PRU0 FD and Over Sample Size Register 4"
bitfld.long 0x30 23. "PRU0_FD_EN_4,Fast Detect One Enable" "0,1"
bitfld.long 0x30 22. "PRU0_FD_ONE_MAX_4,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x30 17.--21. "PRU0_FD_ONE_MAX_LIMIT_4,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 16. "PRU0_FD_ONE_MIN_4,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x30 11.--15. "PRU0_FD_ONE_MIN_LIMIT_4,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 8.--10. "PRU0_FD_WINDOW_SIZE_4,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 0.--7. 1. "PRU0_SD_SAMPLE_SIZE4,Over Sample Rate"
line.long 0x34 "ICSSG_PRU0_SD_CLK_SEL_REG5,PRU0 FD. ACC and Clock Selection Register 5"
bitfld.long 0x34 22. "PRU0_FD_ZERO_MAX_5,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x34 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_5,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 16. "PRU0_FD_ZERO_MIN_5,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x34 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_5,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 4.--5. "PRU0_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x34 2. "PRU0_SD_CLK_INV5,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x34 0.--1. "PRU0_SD_CLK_SEL5,Selects the clock source" "0,1,2,3"
line.long 0x38 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG5,PRU0 FD and Over Sample Size Register 5"
bitfld.long 0x38 23. "PRU0_FD_EN_5,Fast Detect One Enable" "0,1"
bitfld.long 0x38 22. "PRU0_FD_ONE_MAX_5,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x38 17.--21. "PRU0_FD_ONE_MAX_LIMIT_5,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 16. "PRU0_FD_ONE_MIN_5,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x38 11.--15. "PRU0_FD_ONE_MIN_LIMIT_5,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 8.--10. "PRU0_FD_WINDOW_SIZE_5,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x38 0.--7. 1. "PRU0_SD_SAMPLE_SIZE5,Over Sample Rate"
line.long 0x3C "ICSSG_PRU0_SD_CLK_SEL_REG6,PRU0 FD. ACC and Clock Selection Register 6"
bitfld.long 0x3C 22. "PRU0_FD_ZERO_MAX_6,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x3C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_6,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 16. "PRU0_FD_ZERO_MIN_6,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x3C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_6,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 4.--5. "PRU0_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x3C 2. "PRU0_SD_CLK_INV6,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x3C 0.--1. "PRU0_SD_CLK_SEL6,Selects the clock source" "0,1,2,3"
line.long 0x40 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG6,PRU0 FD and Over Sample Size Register 6"
bitfld.long 0x40 23. "PRU0_FD_EN_6,Fast Detect One Enable" "0,1"
bitfld.long 0x40 22. "PRU0_FD_ONE_MAX_6,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x40 17.--21. "PRU0_FD_ONE_MAX_LIMIT_6,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x40 16. "PRU0_FD_ONE_MIN_6,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x40 11.--15. "PRU0_FD_ONE_MIN_LIMIT_6,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 8.--10. "PRU0_FD_WINDOW_SIZE_6,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x40 0.--7. 1. "PRU0_SD_SAMPLE_SIZE6,Over Sample Rate"
line.long 0x44 "ICSSG_PRU0_SD_CLK_SEL_REG7,PRU0 FD. ACC and Clock Selection Register 7"
bitfld.long 0x44 22. "PRU0_FD_ZERO_MAX_7,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x44 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_7,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 16. "PRU0_FD_ZERO_MIN_7,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x44 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_7,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 4.--5. "PRU0_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x44 2. "PRU0_SD_CLK_INV7,Optional clock inversion post clock selection multiplexer" "0,1"
newline
bitfld.long 0x44 0.--1. "PRU0_SD_CLK_SEL7,Selects the clock source" "0,1,2,3"
line.long 0x48 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG7,PRU0 FD and Over Sample Size Register 7"
bitfld.long 0x48 23. "PRU0_FD_EN_7,Fast Detect One Enable" "0,1"
bitfld.long 0x48 22. "PRU0_FD_ONE_MAX_7,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x48 17.--21. "PRU0_FD_ONE_MAX_LIMIT_7,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 16. "PRU0_FD_ONE_MIN_7,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x48 11.--15. "PRU0_FD_ONE_MIN_LIMIT_7,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 8.--10. "PRU0_FD_WINDOW_SIZE_7,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x48 0.--7. 1. "PRU0_SD_SAMPLE_SIZE7,Over Sample Rate"
line.long 0x4C "ICSSG_PRU0_SD_CLK_SEL_REG8,PRU0 FD. ACC and Clock Selection Register 8"
bitfld.long 0x4C 22. "PRU0_FD_ZERO_MAX_8,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x4C 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_8,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 16. "PRU0_FD_ZERO_MIN_8,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x4C 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_8,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 4.--5. "PRU0_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x4C 2. "PRU0_SD_CLK_INV8,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x4C 0.--1. "PRU0_SD_CLK_SEL8,Selects the clock source" "0,1,2,3"
line.long 0x50 "ICSSG_PRU0_SD_SAMPLE_SIZE_REG8,PRU0 FD and Over Sample Size Register 8"
bitfld.long 0x50 23. "PRU0_FD_EN_8,Fast Detect One Enable" "0,1"
bitfld.long 0x50 22. "PRU0_FD_ONE_MAX_8,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x50 17.--21. "PRU0_FD_ONE_MAX_LIMIT_8,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 16. "PRU0_FD_ONE_MIN_8,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x50 11.--15. "PRU0_FD_ONE_MIN_LIMIT_8,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 8.--10. "PRU0_FD_WINDOW_SIZE_8,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x50 0.--7. 1. "PRU0_SD_SAMPLE_SIZE8,Over Sample Rate"
line.long 0x54 "ICSSG_PRU1_SD_CLK_DIV_REG,SD Register"
bitfld.long 0x54 4. "PRU1_SD_DIVFACTOR_FRAC," "0,1"
bitfld.long 0x54 0.--3. "PRU1_SD_DIVFACTOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "ICSSG_PRU1_SD_CLK_SEL_REG0,PRU1 FD. ACC and Clock Selection Register 0"
bitfld.long 0x58 22. "PRU1_FD_ZERO_MAX_0,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x58 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_0,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 16. "PRU1_FD_ZERO_MIN_0,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x58 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_0,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x58 2. "PRU1_SD_CLK_INV0,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x58 0.--1. "PRU1_SD_CLK_SEL0,Selects the clock source" "0,1,2,3"
line.long 0x5C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG0,PRU1 FD and Over Sample Size Register 0"
bitfld.long 0x5C 23. "PRU1_FD_EN_0,Fast Detect One Enable" "0,1"
bitfld.long 0x5C 22. "PRU1_FD_ONE_MAX_0,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x5C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_0,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x5C 16. "PRU1_FD_ONE_MIN_0,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x5C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_0,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 8.--10. "PRU1_FD_WINDOW_SIZE_0,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x5C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,Over Sample Rate"
line.long 0x60 "ICSSG_PRU1_SD_CLK_SEL_REG1,PRU1 FD. ACC and Clock Selection Register 1"
bitfld.long 0x60 22. "PRU1_FD_ZERO_MAX_1,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x60 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_1,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 16. "PRU1_FD_ZERO_MIN_1,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x60 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_1,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 4.--5. "PRU1_SD_ACC_SEL1," "0,1,2,3"
bitfld.long 0x60 2. "PRU1_SD_CLK_INV1,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x60 0.--1. "PRU1_SD_CLK_SEL1,Selects the clock source" "0,1,2,3"
line.long 0x64 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG1,PRU1 FD and Over Sample Size Register 1"
bitfld.long 0x64 23. "PRU1_FD_EN_1,Fast Detect One Enable" "0,1"
bitfld.long 0x64 22. "PRU1_FD_ONE_MAX_1,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x64 17.--21. "PRU1_FD_ONE_MAX_LIMIT_1,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x64 16. "PRU1_FD_ONE_MIN_1,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x64 11.--15. "PRU1_FD_ONE_MIN_LIMIT_1,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 8.--10. "PRU1_FD_WINDOW_SIZE_1,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x64 0.--7. 1. "PRU1_SD_SAMPLE_SIZE1,Over Sample Rate"
line.long 0x68 "ICSSG_PRU1_SD_CLK_SEL_REG2,PRU1 FD. ACC and Clock Selection Register 2"
bitfld.long 0x68 22. "PRU1_FD_ZERO_MAX_2,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x68 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_2,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 16. "PRU1_FD_ZERO_MIN_2,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x68 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_2,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 4.--5. "PRU1_SD_ACC_SEL2," "0,1,2,3"
bitfld.long 0x68 2. "PRU1_SD_CLK_INV2,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x68 0.--1. "PRU1_SD_CLK_SEL2,Selects the clock source" "0,1,2,3"
line.long 0x6C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG2,PRU1 FD and Over Sample Size Register 2"
bitfld.long 0x6C 23. "PRU1_FD_EN_2,Fast Detect One Enable" "0,1"
bitfld.long 0x6C 22. "PRU1_FD_ONE_MAX_2,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x6C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_2,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x6C 16. "PRU1_FD_ONE_MIN_2,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x6C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_2,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 8.--10. "PRU1_FD_WINDOW_SIZE_2,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x6C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE2,Over Sample Rate"
line.long 0x70 "ICSSG_PRU1_SD_CLK_SEL_REG3,PRU1 FD. ACC and Clock Selection Register 3"
bitfld.long 0x70 22. "PRU1_FD_ZERO_MAX_3,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x70 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_3,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 16. "PRU1_FD_ZERO_MIN_3,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x70 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_3,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 4.--5. "PRU1_SD_ACC_SEL3," "0,1,2,3"
bitfld.long 0x70 2. "PRU1_SD_CLK_INV3,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x70 0.--1. "PRU1_SD_CLK_SEL3,Selects the clock source" "0,1,2,3"
line.long 0x74 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG3,PRU1 FD and Over Sample Size Register 3"
bitfld.long 0x74 23. "PRU1_FD_EN_3,Fast Detect One Enable" "0,1"
bitfld.long 0x74 22. "PRU1_FD_ONE_MAX_3,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x74 17.--21. "PRU1_FD_ONE_MAX_LIMIT_3,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x74 16. "PRU1_FD_ONE_MIN_3,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x74 11.--15. "PRU1_FD_ONE_MIN_LIMIT_3,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 8.--10. "PRU1_FD_WINDOW_SIZE_3,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x74 0.--7. 1. "PRU1_SD_SAMPLE_SIZE3,Over Sample Rate"
line.long 0x78 "ICSSG_PRU1_SD_CLK_SEL_REG4,PRU1 FD. ACC and Clock Selection Register 4"
bitfld.long 0x78 22. "PRU1_FD_ZERO_MAX_4,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x78 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_4,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 16. "PRU1_FD_ZERO_MIN_4,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x78 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_4,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 4.--5. "PRU1_SD_ACC_SEL4," "0,1,2,3"
bitfld.long 0x78 2. "PRU1_SD_CLK_INV4,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x78 0.--1. "PRU1_SD_CLK_SEL4,Selects the clock source" "0,1,2,3"
line.long 0x7C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG4,PRU1 FD and Over Sample Size Register 4"
bitfld.long 0x7C 23. "PRU1_FD_EN_4,Fast Detect One Enable" "0,1"
bitfld.long 0x7C 22. "PRU1_FD_ONE_MAX_4,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x7C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_4,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x7C 16. "PRU1_FD_ONE_MIN_4,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x7C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_4,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 8.--10. "PRU1_FD_WINDOW_SIZE_4,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x7C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE4,Over Sample Rate"
line.long 0x80 "ICSSG_PRU1_SD_CLK_SEL_REG5,PRU1 FD. ACC and Clock Selection Register 5"
bitfld.long 0x80 22. "PRU1_FD_ZERO_MAX_5,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x80 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_5,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 16. "PRU1_FD_ZERO_MIN_5,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x80 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_5,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 4.--5. "PRU1_SD_ACC_SEL5," "0,1,2,3"
bitfld.long 0x80 2. "PRU1_SD_CLK_INV5,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x80 0.--1. "PRU1_SD_CLK_SEL5,Selects the clock source" "0,1,2,3"
line.long 0x84 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG5,PRU1 FD and Over Sample Size Register 5"
bitfld.long 0x84 23. "PRU1_FD_EN_5,Fast Detect One Enable" "0,1"
bitfld.long 0x84 22. "PRU1_FD_ONE_MAX_5,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x84 17.--21. "PRU1_FD_ONE_MAX_LIMIT_5,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x84 16. "PRU1_FD_ONE_MIN_5,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x84 11.--15. "PRU1_FD_ONE_MIN_LIMIT_5,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 8.--10. "PRU1_FD_WINDOW_SIZE_5,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x84 0.--7. 1. "PRU1_SD_SAMPLE_SIZE5,Over Sample Rate"
line.long 0x88 "ICSSG_PRU1_SD_CLK_SEL_REG6,PRU1 FD. ACC and Clock Selection Register 6"
bitfld.long 0x88 22. "PRU1_FD_ZERO_MAX_6,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x88 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_6,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 16. "PRU1_FD_ZERO_MIN_6,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x88 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_6,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 4.--5. "PRU1_SD_ACC_SEL6," "0,1,2,3"
bitfld.long 0x88 2. "PRU1_SD_CLK_INV6,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x88 0.--1. "PRU1_SD_CLK_SEL6,Selects the clock source" "0,1,2,3"
line.long 0x8C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG6,PRU1 FD and Over Sample Size Register 6"
bitfld.long 0x8C 23. "PRU1_FD_EN_6,Fast Detect One Enable" "0,1"
bitfld.long 0x8C 22. "PRU1_FD_ONE_MAX_6,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x8C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_6,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8C 16. "PRU1_FD_ONE_MIN_6,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x8C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_6,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 8.--10. "PRU1_FD_WINDOW_SIZE_6,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE6,Over Sample Rate"
line.long 0x90 "ICSSG_PRU1_SD_CLK_SEL_REG7,PRU1 FD. ACC and Clock Selection Register 7"
bitfld.long 0x90 22. "PRU1_FD_ZERO_MAX_7,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x90 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_7,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 16. "PRU1_FD_ZERO_MIN_7,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x90 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_7,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 4.--5. "PRU1_SD_ACC_SEL7," "0,1,2,3"
bitfld.long 0x90 2. "PRU1_SD_CLK_INV7,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x90 0.--1. "PRU1_SD_CLK_SEL7,Selects the clock source" "0,1,2,3"
line.long 0x94 "ICSSG_PRU1_SD_SAMPLE_SIZE_REG7,PRU1 FD and Over Sample Size Register 7"
bitfld.long 0x94 23. "PRU1_FD_EN_7,Fast Detect One Enable" "0,1"
bitfld.long 0x94 22. "PRU1_FD_ONE_MAX_7,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x94 17.--21. "PRU1_FD_ONE_MAX_LIMIT_7,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x94 16. "PRU1_FD_ONE_MIN_7,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x94 11.--15. "PRU1_FD_ONE_MIN_LIMIT_7,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 8.--10. "PRU1_FD_WINDOW_SIZE_7,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x94 0.--7. 1. "PRU1_SD_SAMPLE_SIZE7,Over Sample Rate"
line.long 0x98 "ICSSG_PRU1_SD_CLK_SEL_REG8,PRU1 FD. ACC and Clock Selection Register 8"
bitfld.long 0x98 22. "PRU1_FD_ZERO_MAX_8,Fast Detect Zero Count Max Threshold Hit" "0,1"
bitfld.long 0x98 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_8,Fast Detect Zero Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 16. "PRU1_FD_ZERO_MIN_8,Fast Detect Zero Count Min Threshold Hit" "0,1"
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bitfld.long 0x98 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_8,Fast Detect Zero Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 4.--5. "PRU1_SD_ACC_SEL8," "0,1,2,3"
bitfld.long 0x98 2. "PRU1_SD_CLK_INV8,Optional clock inversion post clock selection multiplexer" "0,1"
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bitfld.long 0x98 0.--1. "PRU1_SD_CLK_SEL8,Selects the clock source" "0,1,2,3"
line.long 0x9C "ICSSG_PRU1_SD_SAMPLE_SIZE_REG8,PRU1 FD and Over Sample Size Register 8"
bitfld.long 0x9C 23. "PRU1_FD_EN_8,Fast Detect One Enable" "0,1"
bitfld.long 0x9C 22. "PRU1_FD_ONE_MAX_8,Fast Detect One Count Max Threshold Hit" "0,1"
bitfld.long 0x9C 17.--21. "PRU1_FD_ONE_MAX_LIMIT_8,Fast Detect One Count Max Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x9C 16. "PRU1_FD_ONE_MIN_8,Fast Detect One Count Min Threshold Hit" "0,1"
bitfld.long 0x9C 11.--15. "PRU1_FD_ONE_MIN_LIMIT_8,Fast Detect One Count Min Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 8.--10. "PRU1_FD_WINDOW_SIZE_8,Fast Detect Window Size" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x9C 0.--7. 1. "PRU1_SD_SAMPLE_SIZE8,Over Sample Rate"
group.long 0xE0++0x3F
line.long 0x00 "ICSSG_PRU0_ED_RX_CFG_REG,PRU0 ED Receive Global Configuration Register"
hexmask.long.word 0x00 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,Div factor for divh16"
bitfld.long 0x00 15. "PRU0_ED_RX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
bitfld.long 0x00 4. "PRU0_ED_RX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
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bitfld.long 0x00 3. "PRU0_ED_RX_SB_POL,Defines the polarity of the RX Start Bit" "0,1"
bitfld.long 0x00 0.--2. "PRU0_ED_RX_SAMPLE_SIZE,Over Sample size" "0,1,2,3,4,5,6,7"
line.long 0x04 "ICSSG_PRU0_ED_TX_CFG_REG,PRU0 ED Transmit Global Configuration Register"
hexmask.long.word 0x04 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,Div factor for divh16"
bitfld.long 0x04 15. "PRU0_ED_TX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
rbitfld.long 0x04 10. "PRU0_ENDAT2_CLK_SYNC,Observation of pru<n>_endat2_clk pin state" "0,1"
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rbitfld.long 0x04 9. "PRU0_ENDAT1_CLK_SYNC,Observation of pru<n>_endat1_clk pin state" "0,1"
rbitfld.long 0x04 8. "PRU0_ENDAT0_CLK_SYNC,Observation of pru<n>_endat0_clk pin state" "0,1"
rbitfld.long 0x04 7. "PRU0_ED_BUSY_2,Determines when you can assert tx go for channel 2" "0,1"
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rbitfld.long 0x04 6. "PRU0_ED_BUSY_1,Determines when you can assert tx go for channel 1" "0,1"
rbitfld.long 0x04 5. "PRU0_ED_BUSY_0,Determines when you can assert tx go for channel 0" "0,1"
bitfld.long 0x04 4. "PRU0_ED_TX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
line.long 0x08 "ICSSG_PRU0_ED_CH0_CFG0_REG,PRU0 ED Channel 0 Configuration 0 Register"
bitfld.long 0x08 31. "PRU0_ED_TX_FIFO_SWAP_BITS0,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x08 30. "PRU0_ED_SW_CLK_OUT0,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x08 29. "PRU0_ED_CLK_OUT_OVR_EN0,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x08 28. "PRU0_ED_RX_SNOOP0,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x08 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,RX frame size after SB is detected"
bitfld.long 0x08 11.--15. "PRU0_ED_TX_FRAME_SIZE0,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x08 0.--10. 1. "PRU0_ED_TX_WDLY0,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x0C "ICSSG_PRU0_ED_CH0_CFG1_REG,PRU0 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x0C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x0C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,This counter will start after the tx_wire_delay has been met"
line.long 0x10 "ICSSG_PRU0_ED_CH1_CFG0_REG,PRU0 ED Channel 1 Configuration 0 Register"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,RX frame size after SB is detected"
bitfld.long 0x10 11.--15. "PRU0_ED_TX_FRAME_SIZE1,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x14 "ICSSG_PRU0_ED_CH1_CFG1_REG,PRU0 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,This counter will start after the tx_wire_delay has been met"
line.long 0x18 "ICSSG_PRU0_ED_CH2_CFG0_REG,PRU0 ED Channel 2 Configuration 0 Register"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,RX frame size after SB is detected"
bitfld.long 0x18 11.--15. "PRU0_ED_TX_FRAME_SIZE2,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x1C "ICSSG_PRU0_ED_CH2_CFG1_REG,PRU0 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,This counter will start after the tx_wire_delay has been met"
line.long 0x20 "ICSSG_PRU1_ED_RX_CFG_REG,PRU1 ED Receive Global Configuration Register"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,div factor for divh16"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
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bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL,Defines the polarity of the RX Start Bit" "0,1"
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE,Over Sample size" "0,1,2,3,4,5,6,7"
line.long 0x24 "ICSSG_PRU1_ED_TX_CFG_REG,PRU1 ED Transmit Global Configuration Register"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,div factor for divh16"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC,Enable Fractional division before the divh16" "0,1"
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC,Observation of pru<n>_endat2_clk pin state" "0,1"
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rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC,Observation of pru<n>_endat1_clk pin state" "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC,Observation of pru<n>_endat0_clk pin state" "0,1"
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2,Determines when you can assert tx go for channel 2" "0,1"
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rbitfld.long 0x24 6. "PRU1_ED_BUSY_1,Determines when you can assert tx go for channel 1" "0,1"
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0,Determines when you can assert tx go for channel 0" "0,1"
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL,Selects the clock source for the divh16fr" "0,1"
line.long 0x28 "ICSSG_PRU1_ED_CH0_CFG0_REG,PRU1 ED Channel 0 Configuration 0 Register"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,RX frame size after SB is detected"
bitfld.long 0x28 11.--15. "PRU1_ED_TX_FRAME_SIZE0,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x2C "ICSSG_PRU1_ED_CH0_CFG1_REG,PRU1 ED Channel 0 Configuration 1 Register"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,This counter will start after the tx_wire_delay has been met"
line.long 0x30 "ICSSG_PRU1_ED_CH1_CFG0_REG,PRU1 ED Channel 1 Configuration 0 Register"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,RX frame size after SB is detected"
bitfld.long 0x30 11.--15. "PRU1_ED_TX_FRAME_SIZE1,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x34 "ICSSG_PRU1_ED_CH1_CFG1_REG,PRU1 ED Channel 1 Configuration 1 Register"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,This counter will start after the tx_wire_delay has been met"
line.long 0x38 "ICSSG_PRU1_ED_CH2_CFG0_REG,PRU1 ED Channel 2 Configuration 0 Register"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2,This enables the swapping of the bits when they are loaded into the TX FIFO" "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2,This controls the state of pru<n>_ endat<m>_clk when endat_clk_out_override_en is set" "0,1"
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2,When set this gives the software the ablity to have direct control of pru<n>_ endat<m>_clk" "0,1"
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rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2,Direct Read of pru<n>_ endat<m>_in state" "0,1"
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,RX frame size after SB is detected"
bitfld.long 0x38 11.--15. "PRU1_ED_TX_FRAME_SIZE2,TX frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,EnDAT TX wire delay using 200Mhz steps (CORE clock)"
line.long 0x3C "ICSSG_PRU1_ED_CH2_CFG1_REG,PRU1 ED Channel 2 Configuration 1 Register"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,This counter will start counting after the last TX bit is sent and when it expires the HW will automatically arm the receiver (rx_en = 1)"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,This counter will start after the tx_wire_delay has been met"
group.long 0x124++0x03
line.long 0x00 "ICSSG_RTU0_POKE_EN0_REG,RTU0 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. "RTU0_POKE_R27_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RTU0_POKE_R26_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "RTU0_POKE_R25_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RTU0_POKE_R24_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "RTU0_POKE_R23_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RTU0_POKE_R22_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "RTU0_POKE_R21_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RTU0_POKE_R20_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x12C++0x6B
line.long 0x00 "ICSSG_RTU1_POKE_EN0_REG,RTU1 Poke Enable 0 Register"
bitfld.long 0x00 28.--31. "RTU1_POKE_R27_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "RTU1_POKE_R26_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "RTU1_POKE_R25_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RTU1_POKE_R24_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "RTU1_POKE_R23_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "RTU1_POKE_R22_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "RTU1_POKE_R21_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "RTU1_POKE_R20_EN,This enables the external values to get poked into PRU's internal register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ICSSG_PWM0,PWM0 Trip Configuration Register"
bitfld.long 0x04 30. "PWM0_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x04 21.--29. 1. "PWM0_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x04 20. "PWM0_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x04 19. "PWM0_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x04 18. "PWM0_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x04 17. "PWM0_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x04 8.--16. 1. "PWM0_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x04 0.--7. 1. "PWM0_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x08 "ICSSG_PWM1,PWM1 Trip Configuration Register"
bitfld.long 0x08 30. "PWM1_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x08 21.--29. 1. "PWM1_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x08 20. "PWM1_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x08 19. "PWM1_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x08 18. "PWM1_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x08 17. "PWM1_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x08 8.--16. 1. "PWM1_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x08 0.--7. 1. "PWM1_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x0C "ICSSG_PWM2,PWM2 Trip Configuration Register"
bitfld.long 0x0C 30. "PWM2_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x0C 21.--29. 1. "PWM2_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x0C 20. "PWM2_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x0C 19. "PWM2_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x0C 18. "PWM2_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x0C 17. "PWM2_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
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hexmask.long.word 0x0C 8.--16. 1. "PWM2_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x0C 0.--7. 1. "PWM2_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x10 "ICSSG_PWM3,PWM3 Trip Configuration Register"
bitfld.long 0x10 30. "PWM3_TRIP_S,Trip status" "0,1"
hexmask.long.word 0x10 21.--29. 1. "PWM3_TRIP_VEC,Trip trigger cause vector"
bitfld.long 0x10 20. "PWM3_POS_ERR_TRIP,Software position feedback error trip" "0,1"
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bitfld.long 0x10 19. "PWM3_OVER_ERR_TRIP,Software overcurrent error trip" "0,1"
bitfld.long 0x10 18. "PWM3_TRIP_RESET,Software trip reset" "0,1"
bitfld.long 0x10 17. "PWM3_TRIP_CMP0_EN,CMP0 reset trip clear enable" "0,1"
newline
hexmask.long.word 0x10 8.--16. 1. "PWM3_TRIP_MASK,Software mask for trip one hot"
hexmask.long.byte 0x10 0.--7. 1. "PWM3_DEBOUNCE_VALUE,Debounce counter defines the number of core_clk required for the pulse not to get rejected"
line.long 0x14 "ICSSG_PWM0_0,PWM0 State Configuration 0 Register"
bitfld.long 0x14 10.--11. "PWM0_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x14 6.--7. "PWM0_0_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x14 4.--5. "PWM0_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x14 2.--3. "PWM0_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x14 0.--1. "PWM0_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x18 "ICSSG_PWM0_1,PWM0 State Configuration 1 Register"
bitfld.long 0x18 10.--11. "PWM0_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x18 8.--9. "PWM0_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x18 6.--7. "PWM0_1_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x18 4.--5. "PWM0_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x18 2.--3. "PWM0_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x18 0.--1. "PWM0_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x1C "ICSSG_PWM0_2,PWM0 State Configuration 2 Register"
bitfld.long 0x1C 10.--11. "PWM0_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x1C 8.--9. "PWM0_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x1C 6.--7. "PWM0_2_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x1C 4.--5. "PWM0_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x1C 2.--3. "PWM0_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x1C 0.--1. "PWM0_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x20 "ICSSG_PWM1_0,PWM1 State Configuration 0 Register"
bitfld.long 0x20 10.--11. "PWM1_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x20 8.--9. "PWM1_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x20 6.--7. "PWM1_0_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x20 4.--5. "PWM1_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x20 2.--3. "PWM1_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x20 0.--1. "PWM1_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x24 "ICSSG_PWM1_1,PWM1 State Configuration 1 Register"
bitfld.long 0x24 10.--11. "PWM1_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x24 8.--9. "PWM1_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x24 6.--7. "PWM1_1_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x24 4.--5. "PWM1_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x24 2.--3. "PWM1_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x24 0.--1. "PWM1_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x28 "ICSSG_PWM1_2,PWM1 State Configuration 2 Register"
bitfld.long 0x28 10.--11. "PWM1_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x28 8.--9. "PWM1_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x28 6.--7. "PWM1_2_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x28 4.--5. "PWM1_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x28 2.--3. "PWM1_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x28 0.--1. "PWM1_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x2C "ICSSG_PWM2_0,PWM2 State Configuration 0 Register"
bitfld.long 0x2C 10.--11. "PWM2_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x2C 8.--9. "PWM2_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x2C 6.--7. "PWM2_0_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x2C 4.--5. "PWM2_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x2C 2.--3. "PWM2_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x2C 0.--1. "PWM2_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x30 "ICSSG_PWM2_1,PWM2 State Configuration 1 Register"
bitfld.long 0x30 10.--11. "PWM2_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x30 8.--9. "PWM2_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x30 6.--7. "PWM2_1_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x30 4.--5. "PWM2_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x30 2.--3. "PWM2_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x30 0.--1. "PWM2_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x34 "ICSSG_PWM2_2,PWM2 State Configuration 2 Register"
bitfld.long 0x34 10.--11. "PWM2_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x34 8.--9. "PWM2_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x34 6.--7. "PWM2_2_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x34 4.--5. "PWM2_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x34 2.--3. "PWM2_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x34 0.--1. "PWM2_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x38 "ICSSG_PWM3_0,PWM3 State Configuration 0 Register"
bitfld.long 0x38 10.--11. "PWM3_0_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x38 8.--9. "PWM3_0_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x38 6.--7. "PWM3_0_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x38 4.--5. "PWM3_0_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x38 2.--3. "PWM3_0_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x38 0.--1. "PWM3_0_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x3C "ICSSG_PWM3_1,PWM3 State Configuration 1 Register"
bitfld.long 0x3C 10.--11. "PWM3_1_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x3C 8.--9. "PWM3_1_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x3C 6.--7. "PWM3_1_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x3C 4.--5. "PWM3_1_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x3C 2.--3. "PWM3_1_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x3C 0.--1. "PWM3_1_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x40 "ICSSG_PWM3_2,PWM3 State Configuration 2 Register"
bitfld.long 0x40 10.--11. "PWM3_2_NEG_ACT,Active negative state" "0,1,2,3"
bitfld.long 0x40 8.--9. "PWM3_2_POS_ACT,Active positive state" "0,1,2,3"
bitfld.long 0x40 6.--7. "PWM3_2_NEG_TRIP,Trip negative state" "0,1,2,3"
newline
bitfld.long 0x40 4.--5. "PWM3_2_POS_TRIP,Trip positive state" "0,1,2,3"
bitfld.long 0x40 2.--3. "PWM3_2_NEG_INIT,Initial negative state" "0,1,2,3"
bitfld.long 0x40 0.--1. "PWM3_2_POS_INIT,Initial positive state" "0,1,2,3"
line.long 0x44 "ICSSG_SPIN_LOCK0,Spin Lock 0 Register"
bitfld.long 0x44 8.--13. "MMR_OWN_REQ_VECTOR_0,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x44 1. "MMR_OWN_REQ_CLR_0,Spin Lock Status Clear" "0,1"
rbitfld.long 0x44 0. "MMR_OWN_REQ_STATUS_0,Spin Lock Status" "0,1"
line.long 0x48 "ICSSG_SPIN_LOCK1,Spin Lock 1 Register"
bitfld.long 0x48 8.--13. "MMR_OWN_REQ_VECTOR_1,Spin Lock flag Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x48 1. "MMR_OWN_REQ_CLR_1,Spin Lock Status Clear" "0,1"
rbitfld.long 0x48 0. "MMR_OWN_REQ_STATUS_1,Spin Lock Status" "0,1"
line.long 0x4C "ICSSG_PA_STAT_PDSP_CFG0,PA STATS PRU Vector 0 Register"
bitfld.long 0x4C 31. "PA_PDSP0_INC_TYPE,pa_pdsp0_inc_type" "0,1"
hexmask.long.tbyte 0x4C 14.--30. 1. "PA_PDSP0_INC_VAL,pa_pdsp0_inc_val"
hexmask.long.word 0x4C 0.--13. 1. "PA_PDSP0_INDEX,pa_pdsp0_index"
line.long 0x50 "ICSSG_PA_STAT_PDSP_STAT0,PA STATS PRU Status 0 Register"
bitfld.long 0x50 1.--3. "PA_PDSP0_STATUS,pa_pdsp0_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x50 0. "PA_PDSP0_READY,pa_pdsp0_ready" "0,1"
line.long 0x54 "ICSSG_PA_STAT_PDSP_CFG1,PA STATS PRU Vector 1 Register"
bitfld.long 0x54 31. "PA_PDSP1_INC_TYPE,pa_pdsp1_inc_type" "0,1"
hexmask.long.tbyte 0x54 14.--30. 1. "PA_PDSP1_INC_VAL,pa_pdsp1_inc_val"
hexmask.long.word 0x54 0.--13. 1. "PA_PDSP1_INDEX,pa_pdsp1_index"
line.long 0x58 "ICSSG_PA_STAT_PDSP_STAT1,PA STATS PRU Status 1 Register"
bitfld.long 0x58 1.--3. "PA_PDSP1_STATUS,pa_pdsp1_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x58 0. "PA_PDSP1_READY,pa_pdsp1_ready" "0,1"
line.long 0x5C "ICSSG_PA_STAT_PDSP_CFG2,PA STATS PRU Vector 2 Register"
bitfld.long 0x5C 31. "PA_PDSP2_INC_TYPE,pa_pdsp2_inc_type" "0,1"
hexmask.long.tbyte 0x5C 14.--30. 1. "PA_PDSP2_INC_VAL,pa_pdsp2_inc_val"
hexmask.long.word 0x5C 0.--13. 1. "PA_PDSP2_INDEX,pa_pdsp2_index"
line.long 0x60 "ICSSG_PA_STAT_PDSP_STAT2,PA STATS PRU Status 2 Register"
bitfld.long 0x60 1.--3. "PA_PDSP2_STATUS,pa_pdsp2_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x60 0. "PA_PDSP2_READY,pa_pdsp2_ready" "0,1"
line.long 0x64 "ICSSG_PA_STAT_PDSP_CFG3,PA STATS PRU Vector 3 Register"
bitfld.long 0x64 31. "PA_PDSP3_INC_TYPE,pa_pdsp3_inc_type" "0,1"
hexmask.long.tbyte 0x64 14.--30. 1. "PA_PDSP3_INC_VAL,pa_pdsp3_inc_val"
hexmask.long.word 0x64 0.--13. 1. "PA_PDSP3_INDEX,pa_pdsp3_index"
line.long 0x68 "ICSSG_PA_STAT_PDSP_STAT3,PA STATS PRU Status 3 Register"
bitfld.long 0x68 1.--3. "PA_PDSP3_STATUS,pa_pdsp3_status" "0,1,2,3,4,5,6,7"
bitfld.long 0x68 0. "PA_PDSP3_READY,pa_pdsp3_ready" "0,1"
tree.end
tree.end
tree "PRU_ICSSG_DRAM"
tree "PRU_ICSSG0_DRAM0_SLV_RAM"
base ad:0xB000000
group.long 0x00++0x03
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PRU_ICSSG0_DRAM1_SLV_RAM"
base ad:0xB002000
group.long 0x00++0x03
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PRU_ICSSG1_DRAM0_SLV_RAM"
base ad:0xB100000
group.long 0x00++0x03
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PRU_ICSSG1_DRAM1_SLV_RAM"
base ad:0xB102000
group.long 0x00++0x03
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "PRU_ICSSG_ECAP0"
tree "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV"
base ad:0xB030000
group.long 0x00++0x17
line.long 0x00 "ICSSG_TSCNT,Time Stamp Counter Register"
line.long 0x04 "ICSSG_CNTPHS,Counter Phase Control Register"
line.long 0x08 "ICSSG_CAP1,Capture-1 Register"
line.long 0x0C "ICSSG_CAP2,Capture-2 Register"
line.long 0x10 "ICSSG_CAP3,Capture-3 Register"
line.long 0x14 "ICSSG_CAP4,Capture-4 Register"
group.long 0x28++0x0F
line.long 0x00 "ICSSG_ECCTL2_ECCTL1,ECAP Control Register 1"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select:0h = Output is active high (that is compare value defines high time)1h = Output is active low (that is compare value defines low time)Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select:0h = ECAP module operates in capture mode" "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced counter (0h = Writing a zero has no effect will always return a zero1h = Writing a one will force aNote: This provides a convenient software method to synchronize some or all ECAP timebases. In APWM mode the synchronizing can also.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-out select:0h = Select sync-in event to be the sync-out signal (pass through)1h = Select CTR = PRD event to be the sync-out signal2h = Disable sync out signal3h = Disable sync out signalNote: Selection CTR = PRD is meaningful only in APWM.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (0h = Disable sync-in option1h = Enable counter (" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter stop (freeze)" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-shot re-arming that is wait for stop trigger:0h = Writing a zero has no effect (reading always returns a" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for one-shot mode" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode):0h = Operate in continuous mode1h = Operate in one-shot mode" "0,1"
bitfld.long 0x00 15. "FREE,Emulation" "0,1"
bitfld.long 0x00 14. "SOFT,Emulation" "0,1"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event filter prescale select:0h = Divide by 1 (that is no prescale by-pass the prescaler)1h = Divide by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable loading of CAP(1-4) registers on a capture" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter reset on capture event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture event 4 polarity select:0h = Capture event 4 triggered on a rising edge (RE)1h = Capture event 4 triggered on a falling edge (FE)" "0,1"
newline
bitfld.long 0x00 5. "CTRRST3,Counter reset on capture event" "0,1"
bitfld.long 0x00 4. "CAP3POL,Capture event 3 polarity select:0h = Capture event 3 triggered on a rising edge (RE)1h = Capture event 3 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter reset on capture event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture event 2 polarity select:0h = Capture event 2 triggered on a rising edge (RE)1h = Capture event 2 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter reset on capture event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture event 1 polarity select:0h = Capture event 1 triggered on a rising edge (RE)1h = Capture event 1 triggered on a falling edge (FE)" "0,1"
line.long 0x04 "ICSSG_ECFLG_ECEINT,ECAP Interrupt Enable Register"
hexmask.long.byte 0x04 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x04 23. "FLAG_CMPEQ,Compare equal status" "0,1"
rbitfld.long 0x04 22. "FLAG_PRDEQ,Period equal status" "0,1"
rbitfld.long 0x04 21. "FLAG_CNTOVF,Counter overflow status" "0,1"
rbitfld.long 0x04 20. "FLAG_CEVT4,Capture event 4 status" "0,1"
rbitfld.long 0x04 19. "FLAG_CEVT3,Capture event 3 status" "0,1"
rbitfld.long 0x04 18. "FLAG_CEVT2,Capture event 2 status" "0,1"
rbitfld.long 0x04 17. "FLAG_CEVT1,Capture event 1 status" "0,1"
newline
rbitfld.long 0x04 16. "FLAG_INT,Global interrupt status" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "EN_RESV1,"
bitfld.long 0x04 7. "EN_CMPEQ,Compare equal interrupt" "0,1"
bitfld.long 0x04 6. "EN_PRDEQ,Period equal interrupt" "0,1"
bitfld.long 0x04 5. "EN_CNTOVF,Counter overflow interrupt" "0,1"
bitfld.long 0x04 4. "EN_CEVT4,Capture event 4 interrupt" "0,1"
bitfld.long 0x04 3. "EN_CEVT3,Capture event 3 interrupt" "0,1"
bitfld.long 0x04 2. "EN_CEVT2,Capture event 2 interrupt" "0,1"
newline
bitfld.long 0x04 1. "EN_CEVT1,Capture event 1 interrupt" "0,1"
rbitfld.long 0x04 0. "EN_RESV0," "0,1"
line.long 0x08 "ICSSG_ECCLR,ECAP Interrupt Clear Register"
hexmask.long.byte 0x08 8.--15. 1. "RESV0,"
bitfld.long 0x08 7. "CMPEQ,Compare equal status" "0,1"
bitfld.long 0x08 6. "PRDEQ,Period equal status" "0,1"
bitfld.long 0x08 5. "CNTOVF,Counter overflow status" "0,1"
bitfld.long 0x08 4. "CEVT4,Capture event 4 status" "0,1"
bitfld.long 0x08 3. "CEVT3,Capture event 3 status" "0,1"
bitfld.long 0x08 2. "CEVT2,Capture event 2 status" "0,1"
bitfld.long 0x08 1. "CEVT1,Capture event 1 status" "0,1"
newline
bitfld.long 0x08 0. "INT,Global interrupt clear" "0,1"
line.long 0x0C "ICSSG_ECFRC,ECAP Interrupt Forcing Register"
hexmask.long.byte 0x0C 8.--15. 1. "RESV1,"
bitfld.long 0x0C 7. "CMPEQ,Force compare" "0,1"
bitfld.long 0x0C 6. "PRDEQ,Force period" "0,1"
bitfld.long 0x0C 5. "CNTOVF,Force counter overflow:0h = Writing of 0 is ignored" "0,1"
bitfld.long 0x0C 4. "CEVT4,Force capture event" "0,1"
bitfld.long 0x0C 3. "CEVT3,Force capture event" "0,1"
bitfld.long 0x0C 2. "CEVT2,Force capture event" "0,1"
bitfld.long 0x0C 1. "CEVT1,Force capture event" "0,1"
newline
rbitfld.long 0x0C 0. "RESV0," "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "ICSSG_PID,ECAP Peripheral Id Register"
tree.end
tree "PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV"
base ad:0xB130000
group.long 0x00++0x17
line.long 0x00 "ICSSG_TSCNT,Time Stamp Counter Register"
line.long 0x04 "ICSSG_CNTPHS,Counter Phase Control Register"
line.long 0x08 "ICSSG_CAP1,Capture-1 Register"
line.long 0x0C "ICSSG_CAP2,Capture-2 Register"
line.long 0x10 "ICSSG_CAP3,Capture-3 Register"
line.long 0x14 "ICSSG_CAP4,Capture-4 Register"
group.long 0x28++0x0F
line.long 0x00 "ICSSG_ECCTL2_ECCTL1,ECAP Control Register 1"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select:0h = Output is active high (that is compare value defines high time)1h = Output is active low (that is compare value defines low time)Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select:0h = ECAP module operates in capture mode" "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced counter (0h = Writing a zero has no effect will always return a zero1h = Writing a one will force aNote: This provides a convenient software method to synchronize some or all ECAP timebases. In APWM mode the synchronizing can also.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-out select:0h = Select sync-in event to be the sync-out signal (pass through)1h = Select CTR = PRD event to be the sync-out signal2h = Disable sync out signal3h = Disable sync out signalNote: Selection CTR = PRD is meaningful only in APWM.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (0h = Disable sync-in option1h = Enable counter (" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter stop (freeze)" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-shot re-arming that is wait for stop trigger:0h = Writing a zero has no effect (reading always returns a" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for one-shot mode" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode):0h = Operate in continuous mode1h = Operate in one-shot mode" "0,1"
bitfld.long 0x00 15. "FREE,Emulation" "0,1"
bitfld.long 0x00 14. "SOFT,Emulation" "0,1"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event filter prescale select:0h = Divide by 1 (that is no prescale by-pass the prescaler)1h = Divide by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable loading of CAP(1-4) registers on a capture" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter reset on capture event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture event 4 polarity select:0h = Capture event 4 triggered on a rising edge (RE)1h = Capture event 4 triggered on a falling edge (FE)" "0,1"
newline
bitfld.long 0x00 5. "CTRRST3,Counter reset on capture event" "0,1"
bitfld.long 0x00 4. "CAP3POL,Capture event 3 polarity select:0h = Capture event 3 triggered on a rising edge (RE)1h = Capture event 3 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter reset on capture event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture event 2 polarity select:0h = Capture event 2 triggered on a rising edge (RE)1h = Capture event 2 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter reset on capture event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture event 1 polarity select:0h = Capture event 1 triggered on a rising edge (RE)1h = Capture event 1 triggered on a falling edge (FE)" "0,1"
line.long 0x04 "ICSSG_ECFLG_ECEINT,ECAP Interrupt Enable Register"
hexmask.long.byte 0x04 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x04 23. "FLAG_CMPEQ,Compare equal status" "0,1"
rbitfld.long 0x04 22. "FLAG_PRDEQ,Period equal status" "0,1"
rbitfld.long 0x04 21. "FLAG_CNTOVF,Counter overflow status" "0,1"
rbitfld.long 0x04 20. "FLAG_CEVT4,Capture event 4 status" "0,1"
rbitfld.long 0x04 19. "FLAG_CEVT3,Capture event 3 status" "0,1"
rbitfld.long 0x04 18. "FLAG_CEVT2,Capture event 2 status" "0,1"
rbitfld.long 0x04 17. "FLAG_CEVT1,Capture event 1 status" "0,1"
newline
rbitfld.long 0x04 16. "FLAG_INT,Global interrupt status" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "EN_RESV1,"
bitfld.long 0x04 7. "EN_CMPEQ,Compare equal interrupt" "0,1"
bitfld.long 0x04 6. "EN_PRDEQ,Period equal interrupt" "0,1"
bitfld.long 0x04 5. "EN_CNTOVF,Counter overflow interrupt" "0,1"
bitfld.long 0x04 4. "EN_CEVT4,Capture event 4 interrupt" "0,1"
bitfld.long 0x04 3. "EN_CEVT3,Capture event 3 interrupt" "0,1"
bitfld.long 0x04 2. "EN_CEVT2,Capture event 2 interrupt" "0,1"
newline
bitfld.long 0x04 1. "EN_CEVT1,Capture event 1 interrupt" "0,1"
rbitfld.long 0x04 0. "EN_RESV0," "0,1"
line.long 0x08 "ICSSG_ECCLR,ECAP Interrupt Clear Register"
hexmask.long.byte 0x08 8.--15. 1. "RESV0,"
bitfld.long 0x08 7. "CMPEQ,Compare equal status" "0,1"
bitfld.long 0x08 6. "PRDEQ,Period equal status" "0,1"
bitfld.long 0x08 5. "CNTOVF,Counter overflow status" "0,1"
bitfld.long 0x08 4. "CEVT4,Capture event 4 status" "0,1"
bitfld.long 0x08 3. "CEVT3,Capture event 3 status" "0,1"
bitfld.long 0x08 2. "CEVT2,Capture event 2 status" "0,1"
bitfld.long 0x08 1. "CEVT1,Capture event 1 status" "0,1"
newline
bitfld.long 0x08 0. "INT,Global interrupt clear" "0,1"
line.long 0x0C "ICSSG_ECFRC,ECAP Interrupt Forcing Register"
hexmask.long.byte 0x0C 8.--15. 1. "RESV1,"
bitfld.long 0x0C 7. "CMPEQ,Force compare" "0,1"
bitfld.long 0x0C 6. "PRDEQ,Force period" "0,1"
bitfld.long 0x0C 5. "CNTOVF,Force counter overflow:0h = Writing of 0 is ignored" "0,1"
bitfld.long 0x0C 4. "CEVT4,Force capture event" "0,1"
bitfld.long 0x0C 3. "CEVT3,Force capture event" "0,1"
bitfld.long 0x0C 2. "CEVT2,Force capture event" "0,1"
bitfld.long 0x0C 1. "CEVT1,Force capture event" "0,1"
newline
rbitfld.long 0x0C 0. "RESV0," "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "ICSSG_PID,ECAP Peripheral Id Register"
tree.end
tree.end
tree "PRU_ICSSG_ECC_AGGR"
tree "PRU_ICSSG0_ECC_AGGR"
base ad:0xBF00000
rgroup.long 0x00++0x03
line.long 0x00 "ICSSG_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "ICSSG_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ICSSG_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "ICSSG_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ICSSG_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x04 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x04 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x04 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x04 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x04 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x04 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x04 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x04 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ICSSG_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ICSSG_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ICSSG_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ICSSG_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x04 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x04 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x04 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x04 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x04 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x04 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x04 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x04 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ICSSG_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ICSSG_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ICSSG_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ICSSG_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ICSSG_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ICSSG_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PRU_ICSSG1_ECC_AGGR"
base ad:0xBF01000
rgroup.long 0x00++0x03
line.long 0x00 "ICSSG_REV,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "ICSSG_VECTOR,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ICSSG_STAT,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x3C++0x07
line.long 0x00 "ICSSG_SEC_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ICSSG_SEC_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x04 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x04 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x04 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x04 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x04 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x04 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x04 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x04 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ICSSG_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ICSSG_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ICSSG_DED_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ICSSG_DED_STATUS_REG0,Interrupt Status Register 0"
bitfld.long 0x04 8. "PR1_PDSP_TX1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x04 7. "PR1_PDSP_TX0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x04 6. "PR1_RTU1_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x04 5. "PR1_RTU0_IRAM_ECC_PEND,Interrupt Pending Status for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x04 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x04 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x04 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x04 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x04 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ICSSG_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_SET,Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ICSSG_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 8. "PR1_PDSP_TX1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend" "0,1"
bitfld.long 0x00 7. "PR1_PDSP_TX0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend" "0,1"
bitfld.long 0x00 6. "PR1_RTU1_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend" "0,1"
newline
bitfld.long 0x00 5. "PR1_RTU0_IRAM_ECC_ENABLE_CLR,Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend" "0,1"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
newline
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ICSSG_AGGR_ENABLE_SET,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ICSSG_AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ICSSG_AGGR_STATUS_SET,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ICSSG_AGGR_STATUS_CLR,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree.end
tree "PRU_ICSSG_IEP"
repeat 2. (list 0. 1. )(list ad:0xB12E000 ad:0xB12F000 )
tree "PRU_ICSSG1_IEP$1"
base $2
group.long 0x00++0x15B
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "DEFAULT_INC,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "CNT_ENABLE,Counter enable" "0,1"
line.long 0x04 "ICSSG_GLOBAL_STATUS_REG,Status Register"
bitfld.long 0x04 0. "CNT_OVF,Counter overflow status" "0,1"
line.long 0x08 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x08 0.--22. 1. "COMPEN_CNT,"
line.long 0x0C "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
line.long 0x10 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
line.long 0x14 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
line.long 0x18 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x18 18.--23. "EXT_CAP_EN," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
line.long 0x1C "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x1C 16.--23. 1. "CAP_RAW,Raw/Current status bit for each of the capture registers where CAP_RAW[n] maps to CAPR[n]"
hexmask.long.word 0x1C 0.--10. 1. "CAP_VALID,A Capture Valid Status OR tree"
line.long 0x20 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
line.long 0x24 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
line.long 0x28 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
line.long 0x2C "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
line.long 0x30 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
line.long 0x34 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
line.long 0x38 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
line.long 0x3C "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
line.long 0x40 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
line.long 0x44 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
line.long 0x48 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
line.long 0x4C "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
line.long 0x50 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
line.long 0x54 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
line.long 0x58 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
line.long 0x5C "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
line.long 0x60 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
line.long 0x64 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
line.long 0x68 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
line.long 0x6C "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
line.long 0x70 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x70 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x70 1.--16. 1. "CMP_EN,Enable bits for each of the compare registers"
bitfld.long 0x70 0. "CMP0_RST_CNT_EN,Enable the reset of the counter" "0,1"
line.long 0x74 "ICSSG_CMP_STATUS_REG,Compare Status Register"
hexmask.long.word 0x74 0.--15. 1. "CMP_STATUS,Status bit for each of the compare registers"
line.long 0x78 "ICSSG_CMP0_REG0,Compare 0 Low Register"
line.long 0x7C "ICSSG_CMP0_REG1,Compare 0 High Register"
line.long 0x80 "ICSSG_CMP1_REG0,Compare 1 Low Register"
line.long 0x84 "ICSSG_CMP1_REG1,Compare 1 High Register"
line.long 0x88 "ICSSG_CMP2_REG0,Compare 2 Low Register"
line.long 0x8C "ICSSG_CMP2_REG1,Compare 2 High Register"
line.long 0x90 "ICSSG_CMP3_REG0,Compare 3 Low Register"
line.long 0x94 "ICSSG_CMP3_REG1,Compare 3 High Register"
line.long 0x98 "ICSSG_CMP4_REG0,Compare 4 Low Register"
line.long 0x9C "ICSSG_CMP4_REG1,Compare 4 High Register"
line.long 0xA0 "ICSSG_CMP5_REG0,Compare 5 Low Register"
line.long 0xA4 "ICSSG_CMP5_REG1,Compare 5 High Register"
line.long 0xA8 "ICSSG_CMP6_REG0,Compare 6 Low Register"
line.long 0xAC "ICSSG_CMP6_REG1,Compare 6 High Register"
line.long 0xB0 "ICSSG_CMP7_REG0,Compare 7 Low Register"
line.long 0xB4 "ICSSG_CMP7_REG1,Compare 7 High Register"
line.long 0xB8 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0 Register"
hexmask.long.word 0xB8 16.--31. 1. "RX_MIN_IPG0,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low"
hexmask.long.word 0xB8 0.--15. 1. "RX_IPG0,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
line.long 0xBC "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1 Register"
hexmask.long.word 0xBC 16.--31. 1. "RX_MIN_IPG1,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low"
hexmask.long.word 0xBC 0.--15. 1. "RX_IPG1,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
line.long 0xC0 "ICSSG_CMP8_REG0,Compare 8 Low Register"
line.long 0xC4 "ICSSG_CMP8_REG1,Compare 8 High Register"
line.long 0xC8 "ICSSG_CMP9_REG0,Compare 9 Low Register"
line.long 0xCC "ICSSG_CMP9_REG1,Compare 9 High Register"
line.long 0xD0 "ICSSG_CMP10_REG0,Compare 10 Low Register"
line.long 0xD4 "ICSSG_CMP10_REG1,Compare 10 High Register"
line.long 0xD8 "ICSSG_CMP11_REG0,Compare 11 Low Register"
line.long 0xDC "ICSSG_CMP11_REG1,Compare 11 High Register"
line.long 0xE0 "ICSSG_CMP12_REG0,Compare 12 Low Register"
line.long 0xE4 "ICSSG_CMP12_REG1,Compare 12 High Register"
line.long 0xE8 "ICSSG_CMP13_REG0,Compare 13 Low Register"
line.long 0xEC "ICSSG_CMP13_REG1,Compare 13 High Register"
line.long 0xF0 "ICSSG_CMP14_REG0,Compare 14 Low Register"
line.long 0xF4 "ICSSG_CMP14_REG1,Compare 14 High Register"
line.long 0xF8 "ICSSG_CMP15_REG0,Compare 15 Low Register"
line.long 0xFC "ICSSG_CMP15_REG1,Compare 15 High Register"
line.long 0x100 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits) Register"
line.long 0x104 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits) Register"
line.long 0x108 "ICSSG_PWM_REG,PWM Sync Out Register"
bitfld.long 0x108 3. "PWM3_HIT,The raw status bit of eHRPWM3_SYNCO event" "0,1"
bitfld.long 0x108 2. "PWM3_RST_CNT_EN,Enable the reset of the counter by a eHRPWM3_SYNCO event" "0,1"
bitfld.long 0x108 1. "PWM0_HIT,The raw status bit of eHRPWM0_SYNCO event" "0,1"
bitfld.long 0x108 0. "PWM0_RST_CNT_EN,Enable the reset of the counter by a eHRPWM0_SYNCO event" "0,1"
line.long 0x10C "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00 Register"
line.long 0x110 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10 Register"
line.long 0x114 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01 Register"
line.long 0x118 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11 Register"
line.long 0x11C "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02 Register"
line.long 0x120 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12 Register"
line.long 0x124 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03 Register"
line.long 0x128 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13 Register"
line.long 0x12C "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04 Register"
line.long 0x130 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14 Register"
line.long 0x134 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05 Register"
line.long 0x138 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15 Register"
line.long 0x13C "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06 Register"
line.long 0x140 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16 Register"
line.long 0x144 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06 Register"
line.long 0x148 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16 Register"
line.long 0x14C "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07 Register"
line.long 0x150 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17 Register"
line.long 0x154 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07 Register"
line.long 0x158 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17 Register"
group.long 0x180++0x1F
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. "SYNC1_IND_EN,SYNC1 independent mode enable" "0,1"
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
bitfld.long 0x00 6. "SYNC1_ACK_EN,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
bitfld.long 0x00 4. "SYNC0_ACK_EN,SYNC0 acknowledgement mode enable" "0,1"
newline
bitfld.long 0x00 2. "SYNC1_EN,SYNC1 generation enable" "0,1"
bitfld.long 0x00 1. "SYNC0_EN,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "SYNC_EN,SYNC generation enable" "0,1"
line.long 0x04 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x04 1. "FIRST_SYNC1,SYNC1 First Event status" "0,1"
bitfld.long 0x04 0. "FIRST_SYNC0,SYNC0 First Event status" "0,1"
line.long 0x08 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x08 0. "SYNC0_PEND,SYNC0 pending state" "0,1"
line.long 0x0C "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x0C 0. "SYNC1_PEND,SYNC1 pending state" "0,1"
line.long 0x10 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
line.long 0x14 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
line.long 0x18 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
line.long 0x1C "ICSSG_SYNC_START_REG,Sync Start Configure Register"
group.long 0x200++0x17
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,Defines the number of ICSS_IEP_CLK cycles per WD clock event"
line.long 0x04 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,Defines the number of WD ticks (or increments) for PDI WD that is the number of WD increments"
line.long 0x08 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,Defines the number of WD ticks (or increments) for PD WD that is the number of WD increments"
line.long 0x0C "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x0C 16. "PDI_WD_STAT,WD PDI status" "0,1"
bitfld.long 0x0C 0. "PD_WD_STAT,WD PD status (triggered by Sync Mangers status)" "0,1"
line.long 0x10 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,WD PD expiration counter"
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,WD PDI expiration counter"
line.long 0x14 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x14 16. "PDI_WD_EN,Watchdog PDI" "0,1"
bitfld.long 0x14 0. "PD_WD_EN,Watchdog PD" "0,1"
group.long 0x300++0x1B
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. "OUT_MODE,Defines events that triggers data out to be updated" "0,1,2,3"
bitfld.long 0x00 4.--5. "IN_MODE,Defines event that triggers data in to be sampled" "0,1,2,3"
bitfld.long 0x00 3. "WD_MODE,Defines Watchdog behavior" "0,1"
rbitfld.long 0x00 2. "BIDI_MODE,Defines the digital input/output direction" "0,1"
bitfld.long 0x00 1. "OUTVALID_MODE,Defines the outvalid mode behavior" "0,1"
newline
rbitfld.long 0x00 0. "OUTVALID_POL,Defines OUTVALID polarity" "0,1"
line.long 0x04 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
line.long 0x08 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
line.long 0x0C "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
line.long 0x10 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
line.long 0x14 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0] Register"
line.long 0x18 "ICSSG_DIGIO_EXP_REG,DIGIO. Defines which RX_EOF is used Register"
bitfld.long 0x18 13. "EOF_SEL,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x18 12. "SOF_SEL,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x18 8.--11. "SOF_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "OUTVALID_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2. "SW_OUTVALID,PR<k>_EDIO_OUTVALID = SW_OUTVALID only if OUTVALID_OVR_EN is set" "0,1"
newline
bitfld.long 0x18 1. "OUTVALID_OVR_EN,Software override enable" "0,1"
bitfld.long 0x18 0. "SW_DATA_OUT_UP,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1" "0,1"
tree.end
repeat.end
repeat 2. (list 0. 1. )(list ad:0xB02E000 ad:0xB02F000 )
tree "PRU_ICSSG0_IEP$1"
base $2
group.long 0x00++0x15B
line.long 0x00 "ICSSG_GLOBAL_CFG_REG,Global Configuration Register"
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,Defines the increment value when compensation is active"
bitfld.long 0x00 4.--7. "DEFAULT_INC,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "CNT_ENABLE,Counter enable" "0,1"
line.long 0x04 "ICSSG_GLOBAL_STATUS_REG,Status Register"
bitfld.long 0x04 0. "CNT_OVF,Counter overflow status" "0,1"
line.long 0x08 "ICSSG_COMPEN_REG,Compensation Register"
hexmask.long.tbyte 0x08 0.--22. 1. "COMPEN_CNT,"
line.long 0x0C "ICSSG_SLOW_COMPEN_REG,Slow Compensation Register"
line.long 0x10 "ICSSG_COUNT_REG0,64-bit Count Value Low Register"
line.long 0x14 "ICSSG_COUNT_REG1,64-bit Count Value High Register"
line.long 0x18 "ICSSG_CAP_CFG_REG,Capture Configuration Register"
bitfld.long 0x18 18.--23. "EXT_CAP_EN," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,Synchronization of the capture inputs to the ICSS_IEP_CLK/ ICSS_VCLK_CLK enable"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
line.long 0x1C "ICSSG_CAP_STATUS_REG,Capture Status Register"
hexmask.long.byte 0x1C 16.--23. 1. "CAP_RAW,Raw/Current status bit for each of the capture registers where CAP_RAW[n] maps to CAPR[n]"
hexmask.long.word 0x1C 0.--10. 1. "CAP_VALID,A Capture Valid Status OR tree"
line.long 0x20 "ICSSG_CAPR0_REG0,Capture Rise 0 Low Register"
line.long 0x24 "ICSSG_CAPR0_REG1,Capture Rise 0 High Register"
line.long 0x28 "ICSSG_CAPR1_REG0,Capture Rise 1 Low Register"
line.long 0x2C "ICSSG_CAPR1_REG1,Capture Rise 1 High Register"
line.long 0x30 "ICSSG_CAPR2_REG0,Capture Rise 2 Low Register"
line.long 0x34 "ICSSG_CAPR2_REG1,Capture Rise 2 High Register"
line.long 0x38 "ICSSG_CAPR3_REG0,Capture Rise 3 Low Register"
line.long 0x3C "ICSSG_CAPR3_REG1,Capture Rise 3 High Register"
line.long 0x40 "ICSSG_CAPR4_REG0,Capture Rise 4 Low Register"
line.long 0x44 "ICSSG_CAPR4_REG1,Capture Rise 4 High Register"
line.long 0x48 "ICSSG_CAPR5_REG0,Capture Rise 5 Low Register"
line.long 0x4C "ICSSG_CAPR5_REG1,Capture Rise 5 High Register"
line.long 0x50 "ICSSG_CAPR6_REG0,Capture Rise 6 Low Register"
line.long 0x54 "ICSSG_CAPR6_REG1,Capture Rise 6 High Register"
line.long 0x58 "ICSSG_CAPF6_REG0,Capture Fall 6 Low Register"
line.long 0x5C "ICSSG_CAPF6_REG1,Capture Fall 6 High Register"
line.long 0x60 "ICSSG_CAPR7_REG0,Capture Rise 7 Low Register"
line.long 0x64 "ICSSG_CAPR7_REG1,Capture Rise 7 High Register"
line.long 0x68 "ICSSG_CAPF7_REG0,Capture Fall 7 Low Register"
line.long 0x6C "ICSSG_CAPF7_REG1,Capture Fall 7 High Register"
line.long 0x70 "ICSSG_CMP_CFG_REG,Compare Configuration Register"
bitfld.long 0x70 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x70 1.--16. 1. "CMP_EN,Enable bits for each of the compare registers"
bitfld.long 0x70 0. "CMP0_RST_CNT_EN,Enable the reset of the counter" "0,1"
line.long 0x74 "ICSSG_CMP_STATUS_REG,Compare Status Register"
hexmask.long.word 0x74 0.--15. 1. "CMP_STATUS,Status bit for each of the compare registers"
line.long 0x78 "ICSSG_CMP0_REG0,Compare 0 Low Register"
line.long 0x7C "ICSSG_CMP0_REG1,Compare 0 High Register"
line.long 0x80 "ICSSG_CMP1_REG0,Compare 1 Low Register"
line.long 0x84 "ICSSG_CMP1_REG1,Compare 1 High Register"
line.long 0x88 "ICSSG_CMP2_REG0,Compare 2 Low Register"
line.long 0x8C "ICSSG_CMP2_REG1,Compare 2 High Register"
line.long 0x90 "ICSSG_CMP3_REG0,Compare 3 Low Register"
line.long 0x94 "ICSSG_CMP3_REG1,Compare 3 High Register"
line.long 0x98 "ICSSG_CMP4_REG0,Compare 4 Low Register"
line.long 0x9C "ICSSG_CMP4_REG1,Compare 4 High Register"
line.long 0xA0 "ICSSG_CMP5_REG0,Compare 5 Low Register"
line.long 0xA4 "ICSSG_CMP5_REG1,Compare 5 High Register"
line.long 0xA8 "ICSSG_CMP6_REG0,Compare 6 Low Register"
line.long 0xAC "ICSSG_CMP6_REG1,Compare 6 High Register"
line.long 0xB0 "ICSSG_CMP7_REG0,Compare 7 Low Register"
line.long 0xB4 "ICSSG_CMP7_REG1,Compare 7 High Register"
line.long 0xB8 "ICSSG_RXIPG0_REG,Status for the RX port which is attached to PRU0 Register"
hexmask.long.word 0xB8 16.--31. 1. "RX_MIN_IPG0,Defines the minimum number of ICSS_IEP_CLK/ICCS_VCLK_CLK cycles that is RX_DV is sampled low"
hexmask.long.word 0xB8 0.--15. 1. "RX_IPG0,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
line.long 0xBC "ICSSG_RXIPG1_REG,Status for the RX port which is attached to PRU1 Register"
hexmask.long.word 0xBC 16.--31. 1. "RX_MIN_IPG1,Defines the minimum number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles that is RX_DV is sampled low"
hexmask.long.word 0xBC 0.--15. 1. "RX_IPG1,Records the current number of ICSS_IEP_CLK/ICSS_VCLK_CLK cycles RX_DV is sampled low"
line.long 0xC0 "ICSSG_CMP8_REG0,Compare 8 Low Register"
line.long 0xC4 "ICSSG_CMP8_REG1,Compare 8 High Register"
line.long 0xC8 "ICSSG_CMP9_REG0,Compare 9 Low Register"
line.long 0xCC "ICSSG_CMP9_REG1,Compare 9 High Register"
line.long 0xD0 "ICSSG_CMP10_REG0,Compare 10 Low Register"
line.long 0xD4 "ICSSG_CMP10_REG1,Compare 10 High Register"
line.long 0xD8 "ICSSG_CMP11_REG0,Compare 11 Low Register"
line.long 0xDC "ICSSG_CMP11_REG1,Compare 11 High Register"
line.long 0xE0 "ICSSG_CMP12_REG0,Compare 12 Low Register"
line.long 0xE4 "ICSSG_CMP12_REG1,Compare 12 High Register"
line.long 0xE8 "ICSSG_CMP13_REG0,Compare 13 Low Register"
line.long 0xEC "ICSSG_CMP13_REG1,Compare 13 High Register"
line.long 0xF0 "ICSSG_CMP14_REG0,Compare 14 Low Register"
line.long 0xF4 "ICSSG_CMP14_REG1,Compare 14 High Register"
line.long 0xF8 "ICSSG_CMP15_REG0,Compare 15 Low Register"
line.long 0xFC "ICSSG_CMP15_REG1,Compare 15 High Register"
line.long 0x100 "ICSSG_COUNT_RESET_VAL_REG0,Reset value of the Master Counter (lower 32-bits) Register"
line.long 0x104 "ICSSG_COUNT_RESET_VAL_REG1,Reset value of the Master Counter (upper 32-bits) Register"
line.long 0x108 "ICSSG_PWM_REG,PWM Sync Out Register"
bitfld.long 0x108 3. "PWM3_HIT,The raw status bit of eHRPWM3_SYNCO event" "0,1"
bitfld.long 0x108 2. "PWM3_RST_CNT_EN,Enable the reset of the counter by a eHRPWM3_SYNCO event" "0,1"
bitfld.long 0x108 1. "PWM0_HIT,The raw status bit of eHRPWM0_SYNCO event" "0,1"
bitfld.long 0x108 0. "PWM0_RST_CNT_EN,Enable the reset of the counter by a eHRPWM0_SYNCO event" "0,1"
line.long 0x10C "ICSSG_CAPR0_BI_REG0,Capture Big Indian Rise00 Register"
line.long 0x110 "ICSSG_CAPR0_BI_REG1,Capture Big Indian Rise10 Register"
line.long 0x114 "ICSSG_CAPR1_BI_REG0,Capture Big Indian Rise01 Register"
line.long 0x118 "ICSSG_CAPR1_BI_REG1,Capture Big Indian Rise11 Register"
line.long 0x11C "ICSSG_CAPR2_BI_REG0,Capture Big Indian Rise02 Register"
line.long 0x120 "ICSSG_CAPR2_BI_REG1,Capture Big Indian Rise12 Register"
line.long 0x124 "ICSSG_CAPR3_BI_REG0,Capture Big Indian Rise03 Register"
line.long 0x128 "ICSSG_CAPR3_BI_REG1,Capture Big Indian Rise13 Register"
line.long 0x12C "ICSSG_CAPR4_BI_REG0,Capture Big Indian Rise04 Register"
line.long 0x130 "ICSSG_CAPR4_BI_REG1,Capture Big Indian Rise14 Register"
line.long 0x134 "ICSSG_CAPR5_BI_REG0,Capture Big Indian Rise05 Register"
line.long 0x138 "ICSSG_CAPR5_BI_REG1,Capture Big Indian Rise15 Register"
line.long 0x13C "ICSSG_CAPR6_BI_REG0,Capture Big Indian Rise06 Register"
line.long 0x140 "ICSSG_CAPR6_BI_REG1,Capture Big Indian Rise16 Register"
line.long 0x144 "ICSSG_CAPF6_BI_REG0,Capture Big Indian Fall06 Register"
line.long 0x148 "ICSSG_CAPF6_BI_REG1,Capture Big Indian Fall16 Register"
line.long 0x14C "ICSSG_CAPR7_BI_REG0,Capture Big Indian Rise07 Register"
line.long 0x150 "ICSSG_CAPR7_BI_REG1,Capture Big Indian Rise17 Register"
line.long 0x154 "ICSSG_CAPF7_BI_REG0,Capture Big Indian Fall07 Register"
line.long 0x158 "ICSSG_CAPF7_BI_REG1,Capture Big Indian Fall17 Register"
group.long 0x180++0x1F
line.long 0x00 "ICSSG_SYNC_CTRL_REG,Sync Generation Control Register"
bitfld.long 0x00 8. "SYNC1_IND_EN,SYNC1 independent mode enable" "0,1"
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN,SYNC1 single shot or cyclic/auto generation mode enable" "0,1"
bitfld.long 0x00 6. "SYNC1_ACK_EN,SYNC1 acknowledgement mode enable" "0,1"
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN,SYNC0 single shot or cyclic/auto generation mode enable" "0,1"
bitfld.long 0x00 4. "SYNC0_ACK_EN,SYNC0 acknowledgement mode enable" "0,1"
newline
bitfld.long 0x00 2. "SYNC1_EN,SYNC1 generation enable" "0,1"
bitfld.long 0x00 1. "SYNC0_EN,SYNC0 generation enable" "0,1"
bitfld.long 0x00 0. "SYNC_EN,SYNC generation enable" "0,1"
line.long 0x04 "ICSSG_SYNC_FIRST_STAT_REG,Sync Generation First Event Status Register"
bitfld.long 0x04 1. "FIRST_SYNC1,SYNC1 First Event status" "0,1"
bitfld.long 0x04 0. "FIRST_SYNC0,SYNC0 First Event status" "0,1"
line.long 0x08 "ICSSG_SYNC0_STAT_REG,Sync 0 Status Register"
bitfld.long 0x08 0. "SYNC0_PEND,SYNC0 pending state" "0,1"
line.long 0x0C "ICSSG_SYNC1_STAT_REG,Sync 1 Status Register"
bitfld.long 0x0C 0. "SYNC1_PEND,SYNC1 pending state" "0,1"
line.long 0x10 "ICSSG_SYNC_PWIDTH_REG,Sync Pulse Width Configure Register"
line.long 0x14 "ICSSG_SYNC0_PERIOD_REG,Sync 0 Period Configure Register"
line.long 0x18 "ICSSG_SYNC1_DELAY_REG,Sync 1 Delay Register"
line.long 0x1C "ICSSG_SYNC_START_REG,Sync Start Configure Register"
group.long 0x200++0x17
line.long 0x00 "ICSSG_WD_PREDIV_REG,Watchdog Pre-Divider Register"
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,Defines the number of ICSS_IEP_CLK cycles per WD clock event"
line.long 0x04 "ICSSG_PDI_WD_TIM_REG,PDI Watchdog Timer Configure Register"
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,Defines the number of WD ticks (or increments) for PDI WD that is the number of WD increments"
line.long 0x08 "ICSSG_PD_WD_TIM_REG,PD Watchdog Timer Configure Register"
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,Defines the number of WD ticks (or increments) for PD WD that is the number of WD increments"
line.long 0x0C "ICSSG_WD_STATUS_REG,Watchdog Status Register"
bitfld.long 0x0C 16. "PDI_WD_STAT,WD PDI status" "0,1"
bitfld.long 0x0C 0. "PD_WD_STAT,WD PD status (triggered by Sync Mangers status)" "0,1"
line.long 0x10 "ICSSG_WD_EXP_CNT_REG,Watchdog Timer Expiration Counter Register"
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,WD PD expiration counter"
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,WD PDI expiration counter"
line.long 0x14 "ICSSG_WD_CTRL_REG,Watchdog Control Register"
bitfld.long 0x14 16. "PDI_WD_EN,Watchdog PDI" "0,1"
bitfld.long 0x14 0. "PD_WD_EN,Watchdog PD" "0,1"
group.long 0x300++0x1B
line.long 0x00 "ICSSG_DIGIO_CTRL_REG,DIGIO Control Register"
bitfld.long 0x00 6.--7. "OUT_MODE,Defines events that triggers data out to be updated" "0,1,2,3"
bitfld.long 0x00 4.--5. "IN_MODE,Defines event that triggers data in to be sampled" "0,1,2,3"
bitfld.long 0x00 3. "WD_MODE,Defines Watchdog behavior" "0,1"
rbitfld.long 0x00 2. "BIDI_MODE,Defines the digital input/output direction" "0,1"
bitfld.long 0x00 1. "OUTVALID_MODE,Defines the outvalid mode behavior" "0,1"
newline
rbitfld.long 0x00 0. "OUTVALID_POL,Defines OUTVALID polarity" "0,1"
line.long 0x04 "ICSSG_DIGIO_STATUS_REG,DIGIO Status Register"
line.long 0x08 "ICSSG_DIGIO_DATA_IN_REG,DIGIO Data Input Register"
line.long 0x0C "ICSSG_DIGIO_DATA_IN_RAW_REG,DIGIO Data Input Direct Sample Register"
line.long 0x10 "ICSSG_DIGIO_DATA_OUT_REG,DIGIO Data Output Register"
line.long 0x14 "ICSSG_DIGIO_DATA_OUT_EN_REG,DIGIO Data Input which controls tri-state of pr<k>_edio_data_out_en[3:0] Register"
line.long 0x18 "ICSSG_DIGIO_EXP_REG,DIGIO. Defines which RX_EOF is used Register"
bitfld.long 0x18 13. "EOF_SEL,Defines which RX_EOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x18 12. "SOF_SEL,Defines which RX_SOF is used for PR<k>_EDIO_DATA_IN[0:3] capture" "0,1"
bitfld.long 0x18 8.--11. "SOF_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay of SOF PR<k>_EDIO_DATA_IN[0:3] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "OUTVALID_DLY,Define the number of iep_clk (ICSS_IEP_CLK) cycle delay on assertion of PR<k>_EDIO_OUTVALID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2. "SW_OUTVALID,PR<k>_EDIO_OUTVALID = SW_OUTVALID only if OUTVALID_OVR_EN is set" "0,1"
newline
bitfld.long 0x18 1. "OUTVALID_OVR_EN,Software override enable" "0,1"
bitfld.long 0x18 0. "SW_DATA_OUT_UP,Defines the value of pr<k>_edio_data_out when OUTVALID_OVR_EN = 1" "0,1"
tree.end
repeat.end
tree.end
tree "PRU_ICSSG_INTC"
tree "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV"
base ad:0xB020000
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_REVISION_REG,Revision Register"
bitfld.long 0x00 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "REV_MODULE,Module ID"
bitfld.long 0x00 11.--15. "REV_RTL,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "REV_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x04 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x04 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSSG_GLOBAL_ENABLE_HINT_REG,Global Host Int Enable Register"
bitfld.long 0x00 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x13
line.long 0x00 "ICSSG_GLB_NEST_LEVEL_REG,Global Nesting Level Register"
bitfld.long 0x00 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
line.long 0x04 "ICSSG_STATUS_SET_INDEX_REG,Status Set Index Register"
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x08 "ICSSG_STATUS_CLR_INDEX_REG,Status Clear Index Register"
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
line.long 0x0C "ICSSG_ENABLE_SET_INDEX_REG,Enable Set Index Register"
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x10 "ICSSG_ENABLE_CLR_INDEX_REG,Enable Clear Index Register"
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x07
line.long 0x00 "ICSSG_HINT_ENABLE_SET_INDEX_REG,Host Int Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x04 "ICSSG_HINT_ENABLE_CLR_INDEX_REG,Host Int Enable Clear Index Register"
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x03
line.long 0x00 "ICSSG_GLB_PRI_INTR_REG,Global Prioritized Interrupt Register"
bitfld.long 0x00 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
group.long 0x380++0x13
line.long 0x00 "ICSSG_ENABLE_CLR_REG0,Enable Clear Register 0"
bitfld.long 0x00 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
bitfld.long 0x00 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
bitfld.long 0x00 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
bitfld.long 0x00 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
bitfld.long 0x00 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
bitfld.long 0x00 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
bitfld.long 0x00 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
bitfld.long 0x00 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
bitfld.long 0x00 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x04 "ICSSG_ENABLE_CLR_REG1,Enable Clear Register 1"
bitfld.long 0x04 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x04 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x04 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
bitfld.long 0x04 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
newline
bitfld.long 0x04 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x04 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
bitfld.long 0x04 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x04 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
newline
bitfld.long 0x04 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
bitfld.long 0x04 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x04 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x04 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x04 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x04 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
bitfld.long 0x04 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x04 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
bitfld.long 0x04 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x04 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
bitfld.long 0x04 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x04 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x04 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x04 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x04 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
bitfld.long 0x04 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x04 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
bitfld.long 0x04 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x04 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
line.long 0x08 "ICSSG_ENABLE_CLR_REG2,Enable Clear Register 2"
bitfld.long 0x08 31. "ENABLE_95_CLR,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x08 30. "ENABLE_94_CLR,Enable clear for slv_events_in[30]" "0,1"
bitfld.long 0x08 29. "ENABLE_93_CLR,Enable clear for slv_events_in[29]" "0,1"
bitfld.long 0x08 28. "ENABLE_92_CLR,Enable clear for slv_events_in[28]" "0,1"
newline
bitfld.long 0x08 27. "ENABLE_91_CLR,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x08 26. "ENABLE_90_CLR,Enable clear for slv_events_in[26]" "0,1"
bitfld.long 0x08 25. "ENABLE_89_CLR,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x08 24. "ENABLE_88_CLR,Enable clear for slv_events_in[24]" "0,1"
newline
bitfld.long 0x08 23. "ENABLE_87_CLR,Enable clear for slv_events_in[23]" "0,1"
bitfld.long 0x08 22. "ENABLE_86_CLR,Enable clear for slv_events_in[22]" "0,1"
bitfld.long 0x08 21. "ENABLE_85_CLR,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x08 20. "ENABLE_84_CLR,Enable clear for slv_events_in[20]" "0,1"
newline
bitfld.long 0x08 19. "ENABLE_83_CLR,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x08 18. "ENABLE_82_CLR,Enable clear for slv_events_in[18]" "0,1"
bitfld.long 0x08 17. "ENABLE_81_CLR,Enable clear for slv_events_in[17]" "0,1"
bitfld.long 0x08 16. "ENABLE_80_CLR,Enable clear for slv_events_in[16]" "0,1"
newline
bitfld.long 0x08 15. "ENABLE_79_CLR,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x08 14. "ENABLE_78_CLR,Enable clear for slv_events_in[14]" "0,1"
bitfld.long 0x08 13. "ENABLE_77_CLR,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x08 12. "ENABLE_76_CLR,Enable clear for slv_events_in[12]" "0,1"
newline
bitfld.long 0x08 11. "ENABLE_75_CLR,Enable clear for slv_events_in[11]" "0,1"
bitfld.long 0x08 10. "ENABLE_74_CLR,Enable clear for slv_events_in[10]" "0,1"
bitfld.long 0x08 9. "ENABLE_73_CLR,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x08 8. "ENABLE_72_CLR,Enable clear for slv_events_in[8]" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_71_CLR,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x08 6. "ENABLE_70_CLR,Enable clear for slv_events_in[6]" "0,1"
bitfld.long 0x08 5. "ENABLE_69_CLR,Enable clear for slv_events_in[5]" "0,1"
bitfld.long 0x08 4. "ENABLE_68_CLR,Enable clear for slv_events_in[4]" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_67_CLR,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x08 2. "ENABLE_66_CLR,Enable clear for slv_events_in[2]" "0,1"
bitfld.long 0x08 1. "ENABLE_65_CLR,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x08 0. "ENABLE_64_CLR,Enable clear for slv_events_in[0]" "0,1"
line.long 0x0C "ICSSG_ENABLE_CLR_REG3,Enable Clear Register 3"
bitfld.long 0x0C 31. "ENABLE_127_CLR,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0x0C 30. "ENABLE_126_CLR,Enable clear for slv_events_in[62]" "0,1"
bitfld.long 0x0C 29. "ENABLE_125_CLR,Enable clear for slv_events_in[61]" "0,1"
bitfld.long 0x0C 28. "ENABLE_124_CLR,Enable clear for slv_events_in[60]" "0,1"
newline
bitfld.long 0x0C 27. "ENABLE_123_CLR,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0x0C 26. "ENABLE_122_CLR,Enable clear for slv_events_in[58]" "0,1"
bitfld.long 0x0C 25. "ENABLE_121_CLR,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0x0C 24. "ENABLE_120_CLR,Enable clear for slv_events_in[56]" "0,1"
newline
bitfld.long 0x0C 23. "ENABLE_119_CLR,Enable clear for slv_events_in[55]" "0,1"
bitfld.long 0x0C 22. "ENABLE_118_CLR,Enable clear for slv_events_in[54]" "0,1"
bitfld.long 0x0C 21. "ENABLE_117_CLR,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0x0C 20. "ENABLE_116_CLR,Enable clear for slv_events_in[52]" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_115_CLR,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0x0C 18. "ENABLE_114_CLR,Enable clear for slv_events_in[50]" "0,1"
bitfld.long 0x0C 17. "ENABLE_113_CLR,Enable clear for slv_events_in[49]" "0,1"
bitfld.long 0x0C 16. "ENABLE_112_CLR,Enable clear for slv_events_in[48]" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_111_CLR,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0x0C 14. "ENABLE_110_CLR,Enable clear for slv_events_in[46]" "0,1"
bitfld.long 0x0C 13. "ENABLE_109_CLR,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0x0C 12. "ENABLE_108_CLR,Enable clear for slv_events_in[44]" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_107_CLR,Enable clear for slv_events_in[43]" "0,1"
bitfld.long 0x0C 10. "ENABLE_106_CLR,Enable clear for slv_events_in[42]" "0,1"
bitfld.long 0x0C 9. "ENABLE_105_CLR,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0x0C 8. "ENABLE_104_CLR,Enable clear for slv_events_in[40]" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_103_CLR,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0x0C 6. "ENABLE_102_CLR,Enable clear for slv_events_in[38]" "0,1"
bitfld.long 0x0C 5. "ENABLE_101_CLR,Enable clear for slv_events_in[37]" "0,1"
bitfld.long 0x0C 4. "ENABLE_100_CLR,Enable clear for slv_events_in[36]" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_99_CLR,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0x0C 2. "ENABLE_98_CLR,Enable clear for slv_events_in[34]" "0,1"
bitfld.long 0x0C 1. "ENABLE_97_CLR,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0x0C 0. "ENABLE_96_CLR,Enable clear for slv_events_in[32]" "0,1"
line.long 0x10 "ICSSG_ENABLE_CLR_REG4,Enable Clear Register 4"
bitfld.long 0x10 31. "ENABLE_159_CLR,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158_CLR,Enable clear for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157_CLR,Enable clear for slv_events_in[93]" "0,1"
bitfld.long 0x10 28. "ENABLE_156_CLR,Enable clear for slv_events_in[92]" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_155_CLR,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154_CLR,Enable clear for slv_events_in[90]" "0,1"
bitfld.long 0x10 25. "ENABLE_153_CLR,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152_CLR,Enable clear for slv_events_in[88]" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_151_CLR,Enable clear for slv_events_in[87]" "0,1"
bitfld.long 0x10 22. "ENABLE_150_CLR,Enable clear for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149_CLR,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148_CLR,Enable clear for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147_CLR,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146_CLR,Enable clear for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145_CLR,Enable clear for slv_events_in[81]" "0,1"
bitfld.long 0x10 16. "ENABLE_144_CLR,Enable clear for slv_events_in[80]" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_143_CLR,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142_CLR,Enable clear for slv_events_in[78]" "0,1"
bitfld.long 0x10 13. "ENABLE_141_CLR,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140_CLR,Enable clear for slv_events_in[76]" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_139_CLR,Enable clear for slv_events_in[75]" "0,1"
bitfld.long 0x10 10. "ENABLE_138_CLR,Enable clear for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137_CLR,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136_CLR,Enable clear for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135_CLR,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134_CLR,Enable clear for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133_CLR,Enable clear for slv_events_in[69]" "0,1"
bitfld.long 0x10 4. "ENABLE_132_CLR,Enable clear for slv_events_in[68]" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_131_CLR,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130_CLR,Enable clear for slv_events_in[66]" "0,1"
bitfld.long 0x10 1. "ENABLE_129_CLR,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128_CLR,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x9F
line.long 0x00 "ICSSG_CH_MAP_REG0,Interrupt Channel Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. "CH_MAP_3,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "CH_MAP_2,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "CH_MAP_1,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "CH_MAP_0,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "ICSSG_CH_MAP_REG1,Interrupt Channel Map Register for 4 to 4+3"
bitfld.long 0x04 24.--28. "CH_MAP_7,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "CH_MAP_6,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "CH_MAP_5,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "CH_MAP_4,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ICSSG_CH_MAP_REG2,Interrupt Channel Map Register for 8 to 8+3"
bitfld.long 0x08 24.--28. "CH_MAP_11,Interrupt Channel Map for intr_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "CH_MAP_10,Interrupt Channel Map for intr_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "CH_MAP_9,Interrupt Channel Map for intr_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "CH_MAP_8,Interrupt Channel Map for intr_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "ICSSG_CH_MAP_REG3,Interrupt Channel Map Register for 12 to 12+3"
bitfld.long 0x0C 24.--28. "CH_MAP_15,Interrupt Channel Map for intr_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "CH_MAP_14,Interrupt Channel Map for intr_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "CH_MAP_13,Interrupt Channel Map for intr_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 0.--4. "CH_MAP_12,Interrupt Channel Map for intr_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ICSSG_CH_MAP_REG4,Interrupt Channel Map Register for 16 to 16+3"
bitfld.long 0x10 24.--28. "CH_MAP_19,Interrupt Channel Map for intr_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "CH_MAP_18,Interrupt Channel Map for intr_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "CH_MAP_17,Interrupt Channel Map for intr_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0.--4. "CH_MAP_16,Interrupt Channel Map for intr_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "ICSSG_CH_MAP_REG5,Interrupt Channel Map Register for 20 to 20+3"
bitfld.long 0x14 24.--28. "CH_MAP_23,Interrupt Channel Map for intr_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16.--20. "CH_MAP_22,Interrupt Channel Map for intr_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 8.--12. "CH_MAP_21,Interrupt Channel Map for intr_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 0.--4. "CH_MAP_20,Interrupt Channel Map for intr_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "ICSSG_CH_MAP_REG6,Interrupt Channel Map Register for 24 to 24+3"
bitfld.long 0x18 24.--28. "CH_MAP_27,Interrupt Channel Map for intr_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "CH_MAP_26,Interrupt Channel Map for intr_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--12. "CH_MAP_25,Interrupt Channel Map for intr_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 0.--4. "CH_MAP_24,Interrupt Channel Map for intr_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "ICSSG_CH_MAP_REG7,Interrupt Channel Map Register for 28 to 28+3"
bitfld.long 0x1C 24.--28. "CH_MAP_31,Interrupt Channel Map for intr_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--20. "CH_MAP_30,Interrupt Channel Map for intr_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--12. "CH_MAP_29,Interrupt Channel Map for intr_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--4. "CH_MAP_28,Interrupt Channel Map for intr_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "ICSSG_CH_MAP_REG8,Interrupt Channel Map Register for 32 to 32+3"
bitfld.long 0x20 24.--28. "CH_MAP_35,Interrupt Channel Map for intr_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 16.--20. "CH_MAP_34,Interrupt Channel Map for intr_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 8.--12. "CH_MAP_33,Interrupt Channel Map for intr_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 0.--4. "CH_MAP_32,Interrupt Channel Map for intr_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "ICSSG_CH_MAP_REG9,Interrupt Channel Map Register for 36 to 36+3"
bitfld.long 0x24 24.--28. "CH_MAP_39,Interrupt Channel Map for intr_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 16.--20. "CH_MAP_38,Interrupt Channel Map for intr_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 8.--12. "CH_MAP_37,Interrupt Channel Map for intr_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 0.--4. "CH_MAP_36,Interrupt Channel Map for intr_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "ICSSG_CH_MAP_REG10,Interrupt Channel Map Register for 40 to 40+3"
bitfld.long 0x28 24.--28. "CH_MAP_43,Interrupt Channel Map for intr_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 16.--20. "CH_MAP_42,Interrupt Channel Map for intr_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 8.--12. "CH_MAP_41,Interrupt Channel Map for intr_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--4. "CH_MAP_40,Interrupt Channel Map for intr_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "ICSSG_CH_MAP_REG11,Interrupt Channel Map Register for 44 to 44+3"
bitfld.long 0x2C 24.--28. "CH_MAP_47,Interrupt Channel Map for intr_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 16.--20. "CH_MAP_46,Interrupt Channel Map for intr_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 8.--12. "CH_MAP_45,Interrupt Channel Map for intr_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 0.--4. "CH_MAP_44,Interrupt Channel Map for intr_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "ICSSG_CH_MAP_REG12,Interrupt Channel Map Register for 48 to 48+3"
bitfld.long 0x30 24.--28. "CH_MAP_51,Interrupt Channel Map for intr_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 16.--20. "CH_MAP_50,Interrupt Channel Map for intr_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 8.--12. "CH_MAP_49,Interrupt Channel Map for intr_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "CH_MAP_48,Interrupt Channel Map for intr_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_CH_MAP_REG13,Interrupt Channel Map Register for 52 to 52+3"
bitfld.long 0x34 24.--28. "CH_MAP_55,Interrupt Channel Map for intr_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 16.--20. "CH_MAP_54,Interrupt Channel Map for intr_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 8.--12. "CH_MAP_53,Interrupt Channel Map for intr_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 0.--4. "CH_MAP_52,Interrupt Channel Map for intr_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "ICSSG_CH_MAP_REG14,Interrupt Channel Map Register for 56 to 56+3"
bitfld.long 0x38 24.--28. "CH_MAP_59,Interrupt Channel Map for intr_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 16.--20. "CH_MAP_58,Interrupt Channel Map for intr_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 8.--12. "CH_MAP_57,Interrupt Channel Map for intr_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 0.--4. "CH_MAP_56,Interrupt Channel Map for intr_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "ICSSG_CH_MAP_REG15,Interrupt Channel Map Register for 60 to 60+3"
bitfld.long 0x3C 24.--28. "CH_MAP_63,Interrupt Channel Map for intr_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 16.--20. "CH_MAP_62,Interrupt Channel Map for intr_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 8.--12. "CH_MAP_61,Interrupt Channel Map for intr_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 0.--4. "CH_MAP_60,Interrupt Channel Map for intr_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "ICSSG_CH_MAP_REG16,Interrupt Channel Map Register for 64 to 64+3"
bitfld.long 0x40 24.--28. "CH_MAP_67,Interrupt Channel Map for slv_events_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 16.--20. "CH_MAP_66,Interrupt Channel Map for slv_events_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 8.--12. "CH_MAP_65,Interrupt Channel Map for slv_events_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 0.--4. "CH_MAP_64,Interrupt Channel Map for slv_events_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "ICSSG_CH_MAP_REG17,Interrupt Channel Map Register for 68 to 68+3"
bitfld.long 0x44 24.--28. "CH_MAP_71,Interrupt Channel Map for slv_events_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 16.--20. "CH_MAP_70,Interrupt Channel Map for slv_events_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 8.--12. "CH_MAP_69,Interrupt Channel Map for slv_events_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 0.--4. "CH_MAP_68,Interrupt Channel Map for slv_events_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x48 "ICSSG_CH_MAP_REG18,Interrupt Channel Map Register for 72 to 72+3"
bitfld.long 0x48 24.--28. "CH_MAP_75,Interrupt Channel Map for slv_events_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 16.--20. "CH_MAP_74,Interrupt Channel Map for slv_events_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 8.--12. "CH_MAP_73,Interrupt Channel Map for slv_events_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 0.--4. "CH_MAP_72,Interrupt Channel Map for slv_events_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x4C "ICSSG_CH_MAP_REG19,Interrupt Channel Map Register for 76 to 76+3"
bitfld.long 0x4C 24.--28. "CH_MAP_79,Interrupt Channel Map for slv_events_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 16.--20. "CH_MAP_78,Interrupt Channel Map for slv_events_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 8.--12. "CH_MAP_77,Interrupt Channel Map for slv_events_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 0.--4. "CH_MAP_76,Interrupt Channel Map for slv_events_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x50 "ICSSG_CH_MAP_REG20,Interrupt Channel Map Register for 80 to 80+3"
bitfld.long 0x50 24.--28. "CH_MAP_83,Interrupt Channel Map for slv_events_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 16.--20. "CH_MAP_82,Interrupt Channel Map for slv_events_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 8.--12. "CH_MAP_81,Interrupt Channel Map for slv_events_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 0.--4. "CH_MAP_80,Interrupt Channel Map for slv_events_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x54 "ICSSG_CH_MAP_REG21,Interrupt Channel Map Register for 84 to 84+3"
bitfld.long 0x54 24.--28. "CH_MAP_87,Interrupt Channel Map for slv_events_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 16.--20. "CH_MAP_86,Interrupt Channel Map for slv_events_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 8.--12. "CH_MAP_85,Interrupt Channel Map for slv_events_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 0.--4. "CH_MAP_84,Interrupt Channel Map for slv_events_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x58 "ICSSG_CH_MAP_REG22,Interrupt Channel Map Register for 88 to 88+3"
bitfld.long 0x58 24.--28. "CH_MAP_91,Interrupt Channel Map for slv_events_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 16.--20. "CH_MAP_90,Interrupt Channel Map for slv_events_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 8.--12. "CH_MAP_89,Interrupt Channel Map for slv_events_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 0.--4. "CH_MAP_88,Interrupt Channel Map for slv_events_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x5C "ICSSG_CH_MAP_REG23,Interrupt Channel Map Register for 92 to 92+3"
bitfld.long 0x5C 24.--28. "CH_MAP_95,Interrupt Channel Map for slv_events_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 16.--20. "CH_MAP_94,Interrupt Channel Map for slv_events_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 8.--12. "CH_MAP_93,Interrupt Channel Map for slv_events_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 0.--4. "CH_MAP_92,Interrupt Channel Map for slv_events_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "ICSSG_CH_MAP_REG24,Interrupt Channel Map Register for 96 to 96+3"
bitfld.long 0x60 24.--28. "CH_MAP_99,Interrupt Channel Map for slv_events_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 16.--20. "CH_MAP_98,Interrupt Channel Map for slv_events_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 8.--12. "CH_MAP_97,Interrupt Channel Map for slv_events_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 0.--4. "CH_MAP_96,Interrupt Channel Map for slv_events_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "ICSSG_CH_MAP_REG25,Interrupt Channel Map Register for 100 to 100+3"
bitfld.long 0x64 24.--28. "CH_MAP_103,Interrupt Channel Map for slv_events_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 16.--20. "CH_MAP_102,Interrupt Channel Map for slv_events_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 8.--12. "CH_MAP_101,Interrupt Channel Map for slv_events_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 0.--4. "CH_MAP_100,Interrupt Channel Map for slv_events_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "ICSSG_CH_MAP_REG26,Interrupt Channel Map Register for 104 to 104+3"
bitfld.long 0x68 24.--28. "CH_MAP_107,Interrupt Channel Map for slv_events_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 16.--20. "CH_MAP_106,Interrupt Channel Map for slv_events_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 8.--12. "CH_MAP_105,Interrupt Channel Map for slv_events_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 0.--4. "CH_MAP_104,Interrupt Channel Map for slv_events_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x6C "ICSSG_CH_MAP_REG27,Interrupt Channel Map Register for 108 to 108+3"
bitfld.long 0x6C 24.--28. "CH_MAP_111,Interrupt Channel Map for slv_events_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 16.--20. "CH_MAP_110,Interrupt Channel Map for slv_events_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 8.--12. "CH_MAP_109,Interrupt Channel Map for slv_events_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 0.--4. "CH_MAP_108,Interrupt Channel Map for slv_events_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x70 "ICSSG_CH_MAP_REG28,Interrupt Channel Map Register for 112 to 112+3"
bitfld.long 0x70 24.--28. "CH_MAP_115,Interrupt Channel Map for slv_events_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 16.--20. "CH_MAP_114,Interrupt Channel Map for slv_events_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 8.--12. "CH_MAP_113,Interrupt Channel Map for slv_events_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 0.--4. "CH_MAP_112,Interrupt Channel Map for slv_events_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "ICSSG_CH_MAP_REG29,Interrupt Channel Map Register for 116 to 116+3"
bitfld.long 0x74 24.--28. "CH_MAP_119,Interrupt Channel Map for slv_events_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 16.--20. "CH_MAP_118,Interrupt Channel Map for slv_events_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 8.--12. "CH_MAP_117,Interrupt Channel Map for slv_events_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 0.--4. "CH_MAP_116,Interrupt Channel Map for slv_events_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x78 "ICSSG_CH_MAP_REG30,Interrupt Channel Map Register for 120 to 120+3"
bitfld.long 0x78 24.--28. "CH_MAP_123,Interrupt Channel Map for slv_events_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 16.--20. "CH_MAP_122,Interrupt Channel Map for slv_events_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 8.--12. "CH_MAP_121,Interrupt Channel Map for slv_events_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 0.--4. "CH_MAP_120,Interrupt Channel Map for slv_events_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x7C "ICSSG_CH_MAP_REG31,Interrupt Channel Map Register for 124 to 124+3"
bitfld.long 0x7C 24.--28. "CH_MAP_127,Interrupt Channel Map for slv_events_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--20. "CH_MAP_126,Interrupt Channel Map for slv_events_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 8.--12. "CH_MAP_125,Interrupt Channel Map for slv_events_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 0.--4. "CH_MAP_124,Interrupt Channel Map for slv_events_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "ICSSG_CH_MAP_REG32,Interrupt Channel Map Register for 128 to 128+3"
bitfld.long 0x80 24.--28. "CH_MAP_131,Interrupt Channel Map for slv_events_in[67]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 16.--20. "CH_MAP_130,Interrupt Channel Map for slv_events_in[66]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 8.--12. "CH_MAP_129,Interrupt Channel Map for slv_events_in[65]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 0.--4. "CH_MAP_128,Interrupt Channel Map for slv_events_in[64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "ICSSG_CH_MAP_REG33,Interrupt Channel Map Register for 132 to 132+3"
bitfld.long 0x84 24.--28. "CH_MAP_135,Interrupt Channel Map for slv_events_in[71]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 16.--20. "CH_MAP_134,Interrupt Channel Map for slv_events_in[70]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 8.--12. "CH_MAP_133,Interrupt Channel Map for slv_events_in[69]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 0.--4. "CH_MAP_132,Interrupt Channel Map for slv_events_in[68]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x88 "ICSSG_CH_MAP_REG34,Interrupt Channel Map Register for 136 to 136+3"
bitfld.long 0x88 24.--28. "CH_MAP_139,Interrupt Channel Map for slv_events_in[75]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 16.--20. "CH_MAP_138,Interrupt Channel Map for slv_events_in[74]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 8.--12. "CH_MAP_137,Interrupt Channel Map for slv_events_in[73]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 0.--4. "CH_MAP_136,Interrupt Channel Map for slv_events_in[72]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x8C "ICSSG_CH_MAP_REG35,Interrupt Channel Map Register for 140 to 140+3"
bitfld.long 0x8C 24.--28. "CH_MAP_143,Interrupt Channel Map for slv_events_in[79]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 16.--20. "CH_MAP_142,Interrupt Channel Map for slv_events_in[78]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 8.--12. "CH_MAP_141,Interrupt Channel Map for slv_events_in[77]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 0.--4. "CH_MAP_140,Interrupt Channel Map for slv_events_in[76]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x90 "ICSSG_CH_MAP_REG36,Interrupt Channel Map Register for 144 to 144+3"
bitfld.long 0x90 24.--28. "CH_MAP_147,Interrupt Channel Map for slv_events_in[83]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 16.--20. "CH_MAP_146,Interrupt Channel Map for slv_events_in[82]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 8.--12. "CH_MAP_145,Interrupt Channel Map for slv_events_in[81]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 0.--4. "CH_MAP_144,Interrupt Channel Map for slv_events_in[80]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x94 "ICSSG_CH_MAP_REG37,Interrupt Channel Map Register for 148 to 148+3"
bitfld.long 0x94 24.--28. "CH_MAP_151,Interrupt Channel Map for slv_events_in[87]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 16.--20. "CH_MAP_150,Interrupt Channel Map for slv_events_in[86]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 8.--12. "CH_MAP_149,Interrupt Channel Map for slv_events_in[85]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 0.--4. "CH_MAP_148,Interrupt Channel Map for slv_events_in[84]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x98 "ICSSG_CH_MAP_REG38,Interrupt Channel Map Register for 152 to 152+3"
bitfld.long 0x98 24.--28. "CH_MAP_155,Interrupt Channel Map for slv_events_in[91]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 16.--20. "CH_MAP_154,Interrupt Channel Map for slv_events_in[90]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 8.--12. "CH_MAP_153,Interrupt Channel Map for slv_events_in[89]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 0.--4. "CH_MAP_152,Interrupt Channel Map for slv_events_in[88]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x9C "ICSSG_CH_MAP_REG39,Interrupt Channel Map Register for 156 to 156+3"
bitfld.long 0x9C 24.--28. "CH_MAP_159,Interrupt Channel Map for slv_events_in[95]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 16.--20. "CH_MAP_158,Interrupt Channel Map for slv_events_in[94]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 8.--12. "CH_MAP_157,Interrupt Channel Map for slv_events_in[93]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 0.--4. "CH_MAP_156,Interrupt Channel Map for slv_events_in[92]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x800++0x13
line.long 0x00 "ICSSG_HINT_MAP_REG0,Host Interrupt Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. "HINT_MAP_3,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "HINT_MAP_2,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "HINT_MAP_1,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "HINT_MAP_0,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "ICSSG_HINT_MAP_REG1,Host Interrupt Map Register for 4 to 4+3"
bitfld.long 0x04 24.--28. "HINT_MAP_7,Host Interrupt Map for Channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "HINT_MAP_6,Host Interrupt Map for Channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "HINT_MAP_5,Host Interrupt Map for Channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "HINT_MAP_4,Host Interrupt Map for Channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ICSSG_HINT_MAP_REG2,Host Interrupt Map Register for 8 to 8+3"
bitfld.long 0x08 24.--28. "HINT_MAP_11,Host Interrupt Map for Channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "HINT_MAP_10,Host Interrupt Map for Channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "HINT_MAP_9,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "HINT_MAP_8,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "ICSSG_HINT_MAP_REG3,Host Interrupt Map Register for 12 to 12+3"
bitfld.long 0x0C 24.--28. "HINT_MAP_15,Host Interrupt Map for Channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "HINT_MAP_14,Host Interrupt Map for Channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "HINT_MAP_13,Host Interrupt Map for Channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 0.--4. "HINT_MAP_12,Host Interrupt Map for Channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ICSSG_HINT_MAP_REG4,Host Interrupt Map Register for 16 to 16+4"
bitfld.long 0x10 24.--28. "HINT_MAP_19,Host Interrupt Map for Channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "HINT_MAP_18,Host Interrupt Map for Channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "HINT_MAP_17,Host Interrupt Map for Channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0.--4. "HINT_MAP_16,Host Interrupt Map for Channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x900++0x4F
line.long 0x00 "ICSSG_PRI_HINT_REG0,Host Int 0 Prioritized Interrupt Register"
bitfld.long 0x00 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x04 "ICSSG_PRI_HINT_REG1,Host Int 1 Prioritized Interrupt Register"
bitfld.long 0x04 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x08 "ICSSG_PRI_HINT_REG2,Host Int 2 Prioritized Interrupt Register"
bitfld.long 0x08 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0x0C "ICSSG_PRI_HINT_REG3,Host Int 3 Prioritized Interrupt Register"
bitfld.long 0x0C 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "ICSSG_PRI_HINT_REG4,Host Int 4 Prioritized Interrupt Register"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "ICSSG_PRI_HINT_REG5,Host Int 5 Prioritized Interrupt Register"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "ICSSG_PRI_HINT_REG6,Host Int 6 Prioritized Interrupt Register"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "ICSSG_PRI_HINT_REG7,Host Int 7 Prioritized Interrupt Register"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "ICSSG_PRI_HINT_REG8,Host Int 8 Prioritized Interrupt Register"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "ICSSG_PRI_HINT_REG9,Host Int 9 Prioritized Interrupt Register"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
line.long 0x28 "ICSSG_PRI_HINT_REG10,Host Int 10 Prioritized Interrupt Register"
bitfld.long 0x28 31. "NONE_HINT_10,No interrupt pending flag" "0,1"
hexmask.long.word 0x28 0.--9. 1. "PRI_HINT_10,Host Int 10 Prioritized Interrupt"
line.long 0x2C "ICSSG_PRI_HINT_REG11,Host Int 11 Prioritized Interrupt Register"
bitfld.long 0x2C 31. "NONE_HINT_11,No interrupt pending flag" "0,1"
hexmask.long.word 0x2C 0.--9. 1. "PRI_HINT_11,Host Int 11 Prioritized Interrupt"
line.long 0x30 "ICSSG_PRI_HINT_REG12,Host Int 12 Prioritized Interrupt Register"
bitfld.long 0x30 31. "NONE_HINT_12,No interrupt pending flag" "0,1"
hexmask.long.word 0x30 0.--9. 1. "PRI_HINT_12,Host Int 12 Prioritized Interrupt"
line.long 0x34 "ICSSG_PRI_HINT_REG13,Host Int 13 Prioritized Interrupt Register"
bitfld.long 0x34 31. "NONE_HINT_13,No interrupt pending flag" "0,1"
hexmask.long.word 0x34 0.--9. 1. "PRI_HINT_13,Host Int 13 Prioritized Interrupt"
line.long 0x38 "ICSSG_PRI_HINT_REG14,Host Int 14 Prioritized Interrupt Register"
bitfld.long 0x38 31. "NONE_HINT_14,No interrupt pending flag" "0,1"
hexmask.long.word 0x38 0.--9. 1. "PRI_HINT_14,Host Int 14 Prioritized Interrupt"
line.long 0x3C "ICSSG_PRI_HINT_REG15,Host Int 15 Prioritized Interrupt Register"
bitfld.long 0x3C 31. "NONE_HINT_15,No interrupt pending flag" "0,1"
hexmask.long.word 0x3C 0.--9. 1. "PRI_HINT_15,Host Int 15 Prioritized Interrupt"
line.long 0x40 "ICSSG_PRI_HINT_REG16,Host Int 16 Prioritized Interrupt Register"
bitfld.long 0x40 31. "NONE_HINT_16,No interrupt pending flag" "0,1"
hexmask.long.word 0x40 0.--9. 1. "PRI_HINT_16,Host Int 16 Prioritized Interrupt"
line.long 0x44 "ICSSG_PRI_HINT_REG17,Host Int 17 Prioritized Interrupt Register"
bitfld.long 0x44 31. "NONE_HINT_17,No interrupt pending flag" "0,1"
hexmask.long.word 0x44 0.--9. 1. "PRI_HINT_17,Host Int 17 Prioritized Interrupt"
line.long 0x48 "ICSSG_PRI_HINT_REG18,Host Int 18 Prioritized Interrupt Register"
bitfld.long 0x48 31. "NONE_HINT_18,No interrupt pending flag" "0,1"
hexmask.long.word 0x48 0.--9. 1. "PRI_HINT_18,Host Int 18 Prioritized Interrupt"
line.long 0x4C "ICSSG_PRI_HINT_REG19,Host Int 19 Prioritized Interrupt Register"
bitfld.long 0x4C 31. "NONE_HINT_19,No interrupt pending flag" "0,1"
hexmask.long.word 0x4C 0.--9. 1. "PRI_HINT_19,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x13
line.long 0x00 "ICSSG_POLARITY_REG0,Polarity Register 0"
bitfld.long 0x00 31. "POLARITY_31,Polarity for intr_in[31]0=low" "0,1"
bitfld.long 0x00 30. "POLARITY_30,Polarity for intr_in[30]0=low" "0,1"
bitfld.long 0x00 29. "POLARITY_29,Polarity for intr_in[29]0=low" "0,1"
bitfld.long 0x00 28. "POLARITY_28,Polarity for intr_in[28]0=low" "0,1"
newline
bitfld.long 0x00 27. "POLARITY_27,Polarity for intr_in[27]0=low" "0,1"
bitfld.long 0x00 26. "POLARITY_26,Polarity for intr_in[26]0=low" "0,1"
bitfld.long 0x00 25. "POLARITY_25,Polarity for intr_in[25]0=low" "0,1"
bitfld.long 0x00 24. "POLARITY_24,Polarity for intr_in[24]0=low" "0,1"
newline
bitfld.long 0x00 23. "POLARITY_23,Polarity for intr_in[23]0=low" "0,1"
bitfld.long 0x00 22. "POLARITY_22,Polarity for intr_in[22]0=low" "0,1"
bitfld.long 0x00 21. "POLARITY_21,Polarity for intr_in[21]0=low" "0,1"
bitfld.long 0x00 20. "POLARITY_20,Polarity for intr_in[20]0=low" "0,1"
newline
bitfld.long 0x00 19. "POLARITY_19,Polarity for intr_in[19]0=low" "0,1"
bitfld.long 0x00 18. "POLARITY_18,Polarity for intr_in[18]0=low" "0,1"
bitfld.long 0x00 17. "POLARITY_17,Polarity for intr_in[17]0=low" "0,1"
bitfld.long 0x00 16. "POLARITY_16,Polarity for intr_in[16]0=low" "0,1"
newline
bitfld.long 0x00 15. "POLARITY_15,Polarity for intr_in[15]0=low" "0,1"
bitfld.long 0x00 14. "POLARITY_14,Polarity for intr_in[14]0=low" "0,1"
bitfld.long 0x00 13. "POLARITY_13,Polarity for intr_in[13]0=low" "0,1"
bitfld.long 0x00 12. "POLARITY_12,Polarity for intr_in[12]0=low" "0,1"
newline
bitfld.long 0x00 11. "POLARITY_11,Polarity for intr_in[11]0=low" "0,1"
bitfld.long 0x00 10. "POLARITY_10,Polarity for intr_in[10]0=low" "0,1"
bitfld.long 0x00 9. "POLARITY_9,Polarity for intr_in[9]0=low" "0,1"
bitfld.long 0x00 8. "POLARITY_8,Polarity for intr_in[8]0=low" "0,1"
newline
bitfld.long 0x00 7. "POLARITY_7,Polarity for intr_in[7]0=low" "0,1"
bitfld.long 0x00 6. "POLARITY_6,Polarity for intr_in[6]0=low" "0,1"
bitfld.long 0x00 5. "POLARITY_5,Polarity for intr_in[5]0=low" "0,1"
bitfld.long 0x00 4. "POLARITY_4,Polarity for intr_in[4]0=low" "0,1"
newline
bitfld.long 0x00 3. "POLARITY_3,Polarity for intr_in[3]0=low" "0,1"
bitfld.long 0x00 2. "POLARITY_2,Polarity for intr_in[2]0=low" "0,1"
bitfld.long 0x00 1. "POLARITY_1,Polarity for intr_in[1]0=low" "0,1"
bitfld.long 0x00 0. "POLARITY_0,Polarity for intr_in[0]0=low" "0,1"
line.long 0x04 "ICSSG_POLARITY_REG1,Polarity Register 1"
bitfld.long 0x04 31. "POLARITY_63,Polarity for intr_in[63]0=low" "0,1"
bitfld.long 0x04 30. "POLARITY_62,Polarity for intr_in[62]0=low" "0,1"
bitfld.long 0x04 29. "POLARITY_61,Polarity for intr_in[61]0=low" "0,1"
bitfld.long 0x04 28. "POLARITY_60,Polarity for intr_in[60]0=low" "0,1"
newline
bitfld.long 0x04 27. "POLARITY_59,Polarity for intr_in[59]0=low" "0,1"
bitfld.long 0x04 26. "POLARITY_58,Polarity for intr_in[58]0=low" "0,1"
bitfld.long 0x04 25. "POLARITY_57,Polarity for intr_in[57]0=low" "0,1"
bitfld.long 0x04 24. "POLARITY_56,Polarity for intr_in[56]0=low" "0,1"
newline
bitfld.long 0x04 23. "POLARITY_55,Polarity for intr_in[55]0=low" "0,1"
bitfld.long 0x04 22. "POLARITY_54,Polarity for intr_in[54]0=low" "0,1"
bitfld.long 0x04 21. "POLARITY_53,Polarity for intr_in[53]0=low" "0,1"
bitfld.long 0x04 20. "POLARITY_52,Polarity for intr_in[52]0=low" "0,1"
newline
bitfld.long 0x04 19. "POLARITY_51,Polarity for intr_in[51]0=low" "0,1"
bitfld.long 0x04 18. "POLARITY_50,Polarity for intr_in[50]0=low" "0,1"
bitfld.long 0x04 17. "POLARITY_49,Polarity for intr_in[49]0=low" "0,1"
bitfld.long 0x04 16. "POLARITY_48,Polarity for intr_in[48]0=low" "0,1"
newline
bitfld.long 0x04 15. "POLARITY_47,Polarity for intr_in[47]0=low" "0,1"
bitfld.long 0x04 14. "POLARITY_46,Polarity for intr_in[46]0=low" "0,1"
bitfld.long 0x04 13. "POLARITY_45,Polarity for intr_in[45]0=low" "0,1"
bitfld.long 0x04 12. "POLARITY_44,Polarity for intr_in[44]0=low" "0,1"
newline
bitfld.long 0x04 11. "POLARITY_43,Polarity for intr_in[43]0=low" "0,1"
bitfld.long 0x04 10. "POLARITY_42,Polarity for intr_in[42]0=low" "0,1"
bitfld.long 0x04 9. "POLARITY_41,Polarity for intr_in[41]0=low" "0,1"
bitfld.long 0x04 8. "POLARITY_40,Polarity for intr_in[40]0=low" "0,1"
newline
bitfld.long 0x04 7. "POLARITY_39,Polarity for intr_in[39]0=low" "0,1"
bitfld.long 0x04 6. "POLARITY_38,Polarity for intr_in[38]0=low" "0,1"
bitfld.long 0x04 5. "POLARITY_37,Polarity for intr_in[37]0=low" "0,1"
bitfld.long 0x04 4. "POLARITY_36,Polarity for intr_in[36]0=low" "0,1"
newline
bitfld.long 0x04 3. "POLARITY_35,Polarity for intr_in[35]0=low" "0,1"
bitfld.long 0x04 2. "POLARITY_34,Polarity for intr_in[34]0=low" "0,1"
bitfld.long 0x04 1. "POLARITY_33,Polarity for intr_in[33]0=low" "0,1"
bitfld.long 0x04 0. "POLARITY_32,Polarity for intr_in[32]0=low" "0,1"
line.long 0x08 "ICSSG_POLARITY_REG2,Polarity Register 2"
bitfld.long 0x08 31. "POLARITY_95,Polarity for slv_events_in[31]0=low" "0,1"
bitfld.long 0x08 30. "POLARITY_94,Polarity for slv_events_in[30]0=low" "0,1"
bitfld.long 0x08 29. "POLARITY_93,Polarity for slv_events_in[29]0=low" "0,1"
bitfld.long 0x08 28. "POLARITY_92,Polarity for slv_events_in[28]0=low" "0,1"
newline
bitfld.long 0x08 27. "POLARITY_91,Polarity for slv_events_in[27]0=low" "0,1"
bitfld.long 0x08 26. "POLARITY_90,Polarity for slv_events_in[26]0=low" "0,1"
bitfld.long 0x08 25. "POLARITY_89,Polarity for slv_events_in[25]0=low" "0,1"
bitfld.long 0x08 24. "POLARITY_88,Polarity for slv_events_in[24]0=low" "0,1"
newline
bitfld.long 0x08 23. "POLARITY_87,Polarity for slv_events_in[23]0=low" "0,1"
bitfld.long 0x08 22. "POLARITY_86,Polarity for slv_events_in[22]0=low" "0,1"
bitfld.long 0x08 21. "POLARITY_85,Polarity for slv_events_in[21]0=low" "0,1"
bitfld.long 0x08 20. "POLARITY_84,Polarity for slv_events_in[20]0=low" "0,1"
newline
bitfld.long 0x08 19. "POLARITY_83,Polarity for slv_events_in[19]0=low" "0,1"
bitfld.long 0x08 18. "POLARITY_82,Polarity for slv_events_in[18]0=low" "0,1"
bitfld.long 0x08 17. "POLARITY_81,Polarity for slv_events_in[17]0=low" "0,1"
bitfld.long 0x08 16. "POLARITY_80,Polarity for slv_events_in[16]0=low" "0,1"
newline
bitfld.long 0x08 15. "POLARITY_79,Polarity for slv_events_in[15]0=low" "0,1"
bitfld.long 0x08 14. "POLARITY_78,Polarity for slv_events_in[14]0=low" "0,1"
bitfld.long 0x08 13. "POLARITY_77,Polarity for slv_events_in[13]0=low" "0,1"
bitfld.long 0x08 12. "POLARITY_76,Polarity for slv_events_in[12]0=low" "0,1"
newline
bitfld.long 0x08 11. "POLARITY_75,Polarity for slv_events_in[11]0=low" "0,1"
bitfld.long 0x08 10. "POLARITY_74,Polarity for slv_events_in[10]0=low" "0,1"
bitfld.long 0x08 9. "POLARITY_73,Polarity for slv_events_in[9]0=low" "0,1"
bitfld.long 0x08 8. "POLARITY_72,Polarity for slv_events_in[8]0=low" "0,1"
newline
bitfld.long 0x08 7. "POLARITY_71,Polarity for slv_events_in[7]0=low" "0,1"
bitfld.long 0x08 6. "POLARITY_70,Polarity for slv_events_in[6]0=low" "0,1"
bitfld.long 0x08 5. "POLARITY_69,Polarity for slv_events_in[5]0=low" "0,1"
bitfld.long 0x08 4. "POLARITY_68,Polarity for slv_events_in[4]0=low" "0,1"
newline
bitfld.long 0x08 3. "POLARITY_67,Polarity for slv_events_in[3]0=low" "0,1"
bitfld.long 0x08 2. "POLARITY_66,Polarity for slv_events_in[2]0=low" "0,1"
bitfld.long 0x08 1. "POLARITY_65,Polarity for slv_events_in[1]0=low" "0,1"
bitfld.long 0x08 0. "POLARITY_64,Polarity for slv_events_in[0]0=low" "0,1"
line.long 0x0C "ICSSG_POLARITY_REG3,Polarity Register 3"
bitfld.long 0x0C 31. "POLARITY_127,Polarity for slv_events_in[63]0=low" "0,1"
bitfld.long 0x0C 30. "POLARITY_126,Polarity for slv_events_in[62]0=low" "0,1"
bitfld.long 0x0C 29. "POLARITY_125,Polarity for slv_events_in[61]0=low" "0,1"
bitfld.long 0x0C 28. "POLARITY_124,Polarity for slv_events_in[60]0=low" "0,1"
newline
bitfld.long 0x0C 27. "POLARITY_123,Polarity for slv_events_in[59]0=low" "0,1"
bitfld.long 0x0C 26. "POLARITY_122,Polarity for slv_events_in[58]0=low" "0,1"
bitfld.long 0x0C 25. "POLARITY_121,Polarity for slv_events_in[57]0=low" "0,1"
bitfld.long 0x0C 24. "POLARITY_120,Polarity for slv_events_in[56]0=low" "0,1"
newline
bitfld.long 0x0C 23. "POLARITY_119,Polarity for slv_events_in[55]0=low" "0,1"
bitfld.long 0x0C 22. "POLARITY_118,Polarity for slv_events_in[54]0=low" "0,1"
bitfld.long 0x0C 21. "POLARITY_117,Polarity for slv_events_in[53]0=low" "0,1"
bitfld.long 0x0C 20. "POLARITY_116,Polarity for slv_events_in[52]0=low" "0,1"
newline
bitfld.long 0x0C 19. "POLARITY_115,Polarity for slv_events_in[51]0=low" "0,1"
bitfld.long 0x0C 18. "POLARITY_114,Polarity for slv_events_in[50]0=low" "0,1"
bitfld.long 0x0C 17. "POLARITY_113,Polarity for slv_events_in[49]0=low" "0,1"
bitfld.long 0x0C 16. "POLARITY_112,Polarity for slv_events_in[48]0=low" "0,1"
newline
bitfld.long 0x0C 15. "POLARITY_111,Polarity for slv_events_in[47]0=low" "0,1"
bitfld.long 0x0C 14. "POLARITY_110,Polarity for slv_events_in[46]0=low" "0,1"
bitfld.long 0x0C 13. "POLARITY_109,Polarity for slv_events_in[45]0=low" "0,1"
bitfld.long 0x0C 12. "POLARITY_108,Polarity for slv_events_in[44]0=low" "0,1"
newline
bitfld.long 0x0C 11. "POLARITY_107,Polarity for slv_events_in[43]0=low" "0,1"
bitfld.long 0x0C 10. "POLARITY_106,Polarity for slv_events_in[42]0=low" "0,1"
bitfld.long 0x0C 9. "POLARITY_105,Polarity for slv_events_in[41]0=low" "0,1"
bitfld.long 0x0C 8. "POLARITY_104,Polarity for slv_events_in[40]0=low" "0,1"
newline
bitfld.long 0x0C 7. "POLARITY_103,Polarity for slv_events_in[39]0=low" "0,1"
bitfld.long 0x0C 6. "POLARITY_102,Polarity for slv_events_in[38]0=low" "0,1"
bitfld.long 0x0C 5. "POLARITY_101,Polarity for slv_events_in[37]0=low" "0,1"
bitfld.long 0x0C 4. "POLARITY_100,Polarity for slv_events_in[36]0=low" "0,1"
newline
bitfld.long 0x0C 3. "POLARITY_99,Polarity for slv_events_in[35]0=low" "0,1"
bitfld.long 0x0C 2. "POLARITY_98,Polarity for slv_events_in[34]0=low" "0,1"
bitfld.long 0x0C 1. "POLARITY_97,Polarity for slv_events_in[33]0=low" "0,1"
bitfld.long 0x0C 0. "POLARITY_96,Polarity for slv_events_in[32]0=low" "0,1"
line.long 0x10 "ICSSG_POLARITY_REG4,Polarity Register 4"
bitfld.long 0x10 31. "POLARITY_159,Polarity for slv_events_in[95]0=low" "0,1"
bitfld.long 0x10 30. "POLARITY_158,Polarity for slv_events_in[94]0=low" "0,1"
bitfld.long 0x10 29. "POLARITY_157,Polarity for slv_events_in[93]0=low" "0,1"
bitfld.long 0x10 28. "POLARITY_156,Polarity for slv_events_in[92]0=low" "0,1"
newline
bitfld.long 0x10 27. "POLARITY_155,Polarity for slv_events_in[91]0=low" "0,1"
bitfld.long 0x10 26. "POLARITY_154,Polarity for slv_events_in[90]0=low" "0,1"
bitfld.long 0x10 25. "POLARITY_153,Polarity for slv_events_in[89]0=low" "0,1"
bitfld.long 0x10 24. "POLARITY_152,Polarity for slv_events_in[88]0=low" "0,1"
newline
bitfld.long 0x10 23. "POLARITY_151,Polarity for slv_events_in[87]0=low" "0,1"
bitfld.long 0x10 22. "POLARITY_150,Polarity for slv_events_in[86]0=low" "0,1"
bitfld.long 0x10 21. "POLARITY_149,Polarity for slv_events_in[85]0=low" "0,1"
bitfld.long 0x10 20. "POLARITY_148,Polarity for slv_events_in[84]0=low" "0,1"
newline
bitfld.long 0x10 19. "POLARITY_147,Polarity for slv_events_in[83]0=low" "0,1"
bitfld.long 0x10 18. "POLARITY_146,Polarity for slv_events_in[82]0=low" "0,1"
bitfld.long 0x10 17. "POLARITY_145,Polarity for slv_events_in[81]0=low" "0,1"
bitfld.long 0x10 16. "POLARITY_144,Polarity for slv_events_in[80]0=low" "0,1"
newline
bitfld.long 0x10 15. "POLARITY_143,Polarity for slv_events_in[79]0=low" "0,1"
bitfld.long 0x10 14. "POLARITY_142,Polarity for slv_events_in[78]0=low" "0,1"
bitfld.long 0x10 13. "POLARITY_141,Polarity for slv_events_in[77]0=low" "0,1"
bitfld.long 0x10 12. "POLARITY_140,Polarity for slv_events_in[76]0=low" "0,1"
newline
bitfld.long 0x10 11. "POLARITY_139,Polarity for slv_events_in[75]0=low" "0,1"
bitfld.long 0x10 10. "POLARITY_138,Polarity for slv_events_in[74]0=low" "0,1"
bitfld.long 0x10 9. "POLARITY_137,Polarity for slv_events_in[73]0=low" "0,1"
bitfld.long 0x10 8. "POLARITY_136,Polarity for slv_events_in[72]0=low" "0,1"
newline
bitfld.long 0x10 7. "POLARITY_135,Polarity for slv_events_in[71]0=low" "0,1"
bitfld.long 0x10 6. "POLARITY_134,Polarity for slv_events_in[70]0=low" "0,1"
bitfld.long 0x10 5. "POLARITY_133,Polarity for slv_events_in[69]0=low" "0,1"
bitfld.long 0x10 4. "POLARITY_132,Polarity for slv_events_in[68]0=low" "0,1"
newline
bitfld.long 0x10 3. "POLARITY_131,Polarity for slv_events_in[67]0=low" "0,1"
bitfld.long 0x10 2. "POLARITY_130,Polarity for slv_events_in[66]0=low" "0,1"
bitfld.long 0x10 1. "POLARITY_129,Polarity for slv_events_in[65]0=low" "0,1"
bitfld.long 0x10 0. "POLARITY_128,Polarity for slv_events_in[64]0=low" "0,1"
group.long 0xD80++0x13
line.long 0x00 "ICSSG_TYPE_REG0,Type Register 0"
bitfld.long 0x00 31. "TYPE_31,Type for intr_in[31]0=level" "0,1"
bitfld.long 0x00 30. "TYPE_30,Type for intr_in[30]0=level" "0,1"
bitfld.long 0x00 29. "TYPE_29,Type for intr_in[29]0=level" "0,1"
bitfld.long 0x00 28. "TYPE_28,Type for intr_in[28]0=level" "0,1"
newline
bitfld.long 0x00 27. "TYPE_27,Type for intr_in[27]0=level" "0,1"
bitfld.long 0x00 26. "TYPE_26,Type for intr_in[26]0=level" "0,1"
bitfld.long 0x00 25. "TYPE_25,Type for intr_in[25]0=level" "0,1"
bitfld.long 0x00 24. "TYPE_24,Type for intr_in[24]0=level" "0,1"
newline
bitfld.long 0x00 23. "TYPE_23,Type for intr_in[23]0=level" "0,1"
bitfld.long 0x00 22. "TYPE_22,Type for intr_in[22]0=level" "0,1"
bitfld.long 0x00 21. "TYPE_21,Type for intr_in[21]0=level" "0,1"
bitfld.long 0x00 20. "TYPE_20,Type for intr_in[20]0=level" "0,1"
newline
bitfld.long 0x00 19. "TYPE_19,Type for intr_in[19]0=level" "0,1"
bitfld.long 0x00 18. "TYPE_18,Type for intr_in[18]0=level" "0,1"
bitfld.long 0x00 17. "TYPE_17,Type for intr_in[17]0=level" "0,1"
bitfld.long 0x00 16. "TYPE_16,Type for intr_in[16]0=level" "0,1"
newline
bitfld.long 0x00 15. "TYPE_15,Type for intr_in[15]0=level" "0,1"
bitfld.long 0x00 14. "TYPE_14,Type for intr_in[14]0=level" "0,1"
bitfld.long 0x00 13. "TYPE_13,Type for intr_in[13]0=level" "0,1"
bitfld.long 0x00 12. "TYPE_12,Type for intr_in[12]0=level" "0,1"
newline
bitfld.long 0x00 11. "TYPE_11,Type for intr_in[11]0=level" "0,1"
bitfld.long 0x00 10. "TYPE_10,Type for intr_in[10]0=level" "0,1"
bitfld.long 0x00 9. "TYPE_9,Type for intr_in[9]0=level" "0,1"
bitfld.long 0x00 8. "TYPE_8,Type for intr_in[8]0=level" "0,1"
newline
bitfld.long 0x00 7. "TYPE_7,Type for intr_in[7]0=level" "0,1"
bitfld.long 0x00 6. "TYPE_6,Type for intr_in[6]0=level" "0,1"
bitfld.long 0x00 5. "TYPE_5,Type for intr_in[5]0=level" "0,1"
bitfld.long 0x00 4. "TYPE_4,Type for intr_in[4]0=level" "0,1"
newline
bitfld.long 0x00 3. "TYPE_3,Type for intr_in[3]0=level" "0,1"
bitfld.long 0x00 2. "TYPE_2,Type for intr_in[2]0=level" "0,1"
bitfld.long 0x00 1. "TYPE_1,Type for intr_in[1]0=level" "0,1"
bitfld.long 0x00 0. "TYPE_0,Type for intr_in[0]0=level" "0,1"
line.long 0x04 "ICSSG_TYPE_REG1,Type Register 1"
bitfld.long 0x04 31. "TYPE_63,Type for intr_in[63]0=level" "0,1"
bitfld.long 0x04 30. "TYPE_62,Type for intr_in[62]0=level" "0,1"
bitfld.long 0x04 29. "TYPE_61,Type for intr_in[61]0=level" "0,1"
bitfld.long 0x04 28. "TYPE_60,Type for intr_in[60]0=level" "0,1"
newline
bitfld.long 0x04 27. "TYPE_59,Type for intr_in[59]0=level" "0,1"
bitfld.long 0x04 26. "TYPE_58,Type for intr_in[58]0=level" "0,1"
bitfld.long 0x04 25. "TYPE_57,Type for intr_in[57]0=level" "0,1"
bitfld.long 0x04 24. "TYPE_56,Type for intr_in[56]0=level" "0,1"
newline
bitfld.long 0x04 23. "TYPE_55,Type for intr_in[55]0=level" "0,1"
bitfld.long 0x04 22. "TYPE_54,Type for intr_in[54]0=level" "0,1"
bitfld.long 0x04 21. "TYPE_53,Type for intr_in[53]0=level" "0,1"
bitfld.long 0x04 20. "TYPE_52,Type for intr_in[52]0=level" "0,1"
newline
bitfld.long 0x04 19. "TYPE_51,Type for intr_in[51]0=level" "0,1"
bitfld.long 0x04 18. "TYPE_50,Type for intr_in[50]0=level" "0,1"
bitfld.long 0x04 17. "TYPE_49,Type for intr_in[49]0=level" "0,1"
bitfld.long 0x04 16. "TYPE_48,Type for intr_in[48]0=level" "0,1"
newline
bitfld.long 0x04 15. "TYPE_47,Type for intr_in[47]0=level" "0,1"
bitfld.long 0x04 14. "TYPE_46,Type for intr_in[46]0=level" "0,1"
bitfld.long 0x04 13. "TYPE_45,Type for intr_in[45]0=level" "0,1"
bitfld.long 0x04 12. "TYPE_44,Type for intr_in[44]0=level" "0,1"
newline
bitfld.long 0x04 11. "TYPE_43,Type for intr_in[43]0=level" "0,1"
bitfld.long 0x04 10. "TYPE_42,Type for intr_in[42]0=level" "0,1"
bitfld.long 0x04 9. "TYPE_41,Type for intr_in[41]0=level" "0,1"
bitfld.long 0x04 8. "TYPE_40,Type for intr_in[40]0=level" "0,1"
newline
bitfld.long 0x04 7. "TYPE_39,Type for intr_in[39]0=level" "0,1"
bitfld.long 0x04 6. "TYPE_38,Type for intr_in[38]0=level" "0,1"
bitfld.long 0x04 5. "TYPE_37,Type for intr_in[37]0=level" "0,1"
bitfld.long 0x04 4. "TYPE_36,Type for intr_in[36]0=level" "0,1"
newline
bitfld.long 0x04 3. "TYPE_35,Type for intr_in[35]0=level" "0,1"
bitfld.long 0x04 2. "TYPE_34,Type for intr_in[34]0=level" "0,1"
bitfld.long 0x04 1. "TYPE_33,Type for intr_in[33]0=level" "0,1"
bitfld.long 0x04 0. "TYPE_32,Type for intr_in[32]0=level" "0,1"
line.long 0x08 "ICSSG_TYPE_REG2,Type Register 2"
bitfld.long 0x08 31. "TYPE_95,Type for slv_events_in[31]0=level" "0,1"
bitfld.long 0x08 30. "TYPE_94,Type for slv_events_in[30]0=level" "0,1"
bitfld.long 0x08 29. "TYPE_93,Type for slv_events_in[29]0=level" "0,1"
bitfld.long 0x08 28. "TYPE_92,Type for slv_events_in[28]0=level" "0,1"
newline
bitfld.long 0x08 27. "TYPE_91,Type for slv_events_in[27]0=level" "0,1"
bitfld.long 0x08 26. "TYPE_90,Type for slv_events_in[26]0=level" "0,1"
bitfld.long 0x08 25. "TYPE_89,Type for slv_events_in[25]0=level" "0,1"
bitfld.long 0x08 24. "TYPE_88,Type for slv_events_in[24]0=level" "0,1"
newline
bitfld.long 0x08 23. "TYPE_87,Type for slv_events_in[23]0=level" "0,1"
bitfld.long 0x08 22. "TYPE_86,Type for slv_events_in[22]0=level" "0,1"
bitfld.long 0x08 21. "TYPE_85,Type for slv_events_in[21]0=level" "0,1"
bitfld.long 0x08 20. "TYPE_84,Type for slv_events_in[20]0=level" "0,1"
newline
bitfld.long 0x08 19. "TYPE_83,Type for slv_events_in[19]0=level" "0,1"
bitfld.long 0x08 18. "TYPE_82,Type for slv_events_in[18]0=level" "0,1"
bitfld.long 0x08 17. "TYPE_81,Type for slv_events_in[17]0=level" "0,1"
bitfld.long 0x08 16. "TYPE_80,Type for slv_events_in[16]0=level" "0,1"
newline
bitfld.long 0x08 15. "TYPE_79,Type for slv_events_in[15]0=level" "0,1"
bitfld.long 0x08 14. "TYPE_78,Type for slv_events_in[14]0=level" "0,1"
bitfld.long 0x08 13. "TYPE_77,Type for slv_events_in[13]0=level" "0,1"
bitfld.long 0x08 12. "TYPE_76,Type for slv_events_in[12]0=level" "0,1"
newline
bitfld.long 0x08 11. "TYPE_75,Type for slv_events_in[11]0=level" "0,1"
bitfld.long 0x08 10. "TYPE_74,Type for slv_events_in[10]0=level" "0,1"
bitfld.long 0x08 9. "TYPE_73,Type for slv_events_in[9]0=level" "0,1"
bitfld.long 0x08 8. "TYPE_72,Type for slv_events_in[8]0=level" "0,1"
newline
bitfld.long 0x08 7. "TYPE_71,Type for slv_events_in[7]0=level" "0,1"
bitfld.long 0x08 6. "TYPE_70,Type for slv_events_in[6]0=level" "0,1"
bitfld.long 0x08 5. "TYPE_69,Type for slv_events_in[5]0=level" "0,1"
bitfld.long 0x08 4. "TYPE_68,Type for slv_events_in[4]0=level" "0,1"
newline
bitfld.long 0x08 3. "TYPE_67,Type for slv_events_in[3]0=level" "0,1"
bitfld.long 0x08 2. "TYPE_66,Type for slv_events_in[2]0=level" "0,1"
bitfld.long 0x08 1. "TYPE_65,Type for slv_events_in[1]0=level" "0,1"
bitfld.long 0x08 0. "TYPE_64,Type for slv_events_in[0]0=level" "0,1"
line.long 0x0C "ICSSG_TYPE_REG3,Type Register 3"
bitfld.long 0x0C 31. "TYPE_127,Type for slv_events_in[63]0=level" "0,1"
bitfld.long 0x0C 30. "TYPE_126,Type for slv_events_in[62]0=level" "0,1"
bitfld.long 0x0C 29. "TYPE_125,Type for slv_events_in[61]0=level" "0,1"
bitfld.long 0x0C 28. "TYPE_124,Type for slv_events_in[60]0=level" "0,1"
newline
bitfld.long 0x0C 27. "TYPE_123,Type for slv_events_in[59]0=level" "0,1"
bitfld.long 0x0C 26. "TYPE_122,Type for slv_events_in[58]0=level" "0,1"
bitfld.long 0x0C 25. "TYPE_121,Type for slv_events_in[57]0=level" "0,1"
bitfld.long 0x0C 24. "TYPE_120,Type for slv_events_in[56]0=level" "0,1"
newline
bitfld.long 0x0C 23. "TYPE_119,Type for slv_events_in[55]0=level" "0,1"
bitfld.long 0x0C 22. "TYPE_118,Type for slv_events_in[54]0=level" "0,1"
bitfld.long 0x0C 21. "TYPE_117,Type for slv_events_in[53]0=level" "0,1"
bitfld.long 0x0C 20. "TYPE_116,Type for slv_events_in[52]0=level" "0,1"
newline
bitfld.long 0x0C 19. "TYPE_115,Type for slv_events_in[51]0=level" "0,1"
bitfld.long 0x0C 18. "TYPE_114,Type for slv_events_in[50]0=level" "0,1"
bitfld.long 0x0C 17. "TYPE_113,Type for slv_events_in[49]0=level" "0,1"
bitfld.long 0x0C 16. "TYPE_112,Type for slv_events_in[48]0=level" "0,1"
newline
bitfld.long 0x0C 15. "TYPE_111,Type for slv_events_in[47]0=level" "0,1"
bitfld.long 0x0C 14. "TYPE_110,Type for slv_events_in[46]0=level" "0,1"
bitfld.long 0x0C 13. "TYPE_109,Type for slv_events_in[45]0=level" "0,1"
bitfld.long 0x0C 12. "TYPE_108,Type for slv_events_in[44]0=level" "0,1"
newline
bitfld.long 0x0C 11. "TYPE_107,Type for slv_events_in[43]0=level" "0,1"
bitfld.long 0x0C 10. "TYPE_106,Type for slv_events_in[42]0=level" "0,1"
bitfld.long 0x0C 9. "TYPE_105,Type for slv_events_in[41]0=level" "0,1"
bitfld.long 0x0C 8. "TYPE_104,Type for slv_events_in[40]0=level" "0,1"
newline
bitfld.long 0x0C 7. "TYPE_103,Type for slv_events_in[39]0=level" "0,1"
bitfld.long 0x0C 6. "TYPE_102,Type for slv_events_in[38]0=level" "0,1"
bitfld.long 0x0C 5. "TYPE_101,Type for slv_events_in[37]0=level" "0,1"
bitfld.long 0x0C 4. "TYPE_100,Type for slv_events_in[36]0=level" "0,1"
newline
bitfld.long 0x0C 3. "TYPE_99,Type for slv_events_in[35]0=level" "0,1"
bitfld.long 0x0C 2. "TYPE_98,Type for slv_events_in[34]0=level" "0,1"
bitfld.long 0x0C 1. "TYPE_97,Type for slv_events_in[33]0=level" "0,1"
bitfld.long 0x0C 0. "TYPE_96,Type for slv_events_in[32]0=level" "0,1"
line.long 0x10 "ICSSG_TYPE_REG4,Type Register 4"
bitfld.long 0x10 31. "TYPE_159,Type for slv_events_in[95]0=level" "0,1"
bitfld.long 0x10 30. "TYPE_158,Type for slv_events_in[94]0=level" "0,1"
bitfld.long 0x10 29. "TYPE_157,Type for slv_events_in[93]0=level" "0,1"
bitfld.long 0x10 28. "TYPE_156,Type for slv_events_in[92]0=level" "0,1"
newline
bitfld.long 0x10 27. "TYPE_155,Type for slv_events_in[91]0=level" "0,1"
bitfld.long 0x10 26. "TYPE_154,Type for slv_events_in[90]0=level" "0,1"
bitfld.long 0x10 25. "TYPE_153,Type for slv_events_in[89]0=level" "0,1"
bitfld.long 0x10 24. "TYPE_152,Type for slv_events_in[88]0=level" "0,1"
newline
bitfld.long 0x10 23. "TYPE_151,Type for slv_events_in[87]0=level" "0,1"
bitfld.long 0x10 22. "TYPE_150,Type for slv_events_in[86]0=level" "0,1"
bitfld.long 0x10 21. "TYPE_149,Type for slv_events_in[85]0=level" "0,1"
bitfld.long 0x10 20. "TYPE_148,Type for slv_events_in[84]0=level" "0,1"
newline
bitfld.long 0x10 19. "TYPE_147,Type for slv_events_in[83]0=level" "0,1"
bitfld.long 0x10 18. "TYPE_146,Type for slv_events_in[82]0=level" "0,1"
bitfld.long 0x10 17. "TYPE_145,Type for slv_events_in[81]0=level" "0,1"
bitfld.long 0x10 16. "TYPE_144,Type for slv_events_in[80]0=level" "0,1"
newline
bitfld.long 0x10 15. "TYPE_143,Type for slv_events_in[79]0=level" "0,1"
bitfld.long 0x10 14. "TYPE_142,Type for slv_events_in[78]0=level" "0,1"
bitfld.long 0x10 13. "TYPE_141,Type for slv_events_in[77]0=level" "0,1"
bitfld.long 0x10 12. "TYPE_140,Type for slv_events_in[76]0=level" "0,1"
newline
bitfld.long 0x10 11. "TYPE_139,Type for slv_events_in[75]0=level" "0,1"
bitfld.long 0x10 10. "TYPE_138,Type for slv_events_in[74]0=level" "0,1"
bitfld.long 0x10 9. "TYPE_137,Type for slv_events_in[73]0=level" "0,1"
bitfld.long 0x10 8. "TYPE_136,Type for slv_events_in[72]0=level" "0,1"
newline
bitfld.long 0x10 7. "TYPE_135,Type for slv_events_in[71]0=level" "0,1"
bitfld.long 0x10 6. "TYPE_134,Type for slv_events_in[70]0=level" "0,1"
bitfld.long 0x10 5. "TYPE_133,Type for slv_events_in[69]0=level" "0,1"
bitfld.long 0x10 4. "TYPE_132,Type for slv_events_in[68]0=level" "0,1"
newline
bitfld.long 0x10 3. "TYPE_131,Type for slv_events_in[67]0=level" "0,1"
bitfld.long 0x10 2. "TYPE_130,Type for slv_events_in[66]0=level" "0,1"
bitfld.long 0x10 1. "TYPE_129,Type for slv_events_in[65]0=level" "0,1"
bitfld.long 0x10 0. "TYPE_128,Type for slv_events_in[64]0=level" "0,1"
group.long 0x1100++0x4F
line.long 0x00 "ICSSG_NEST_LEVEL_REG0,Host Int 0 Nesting Level Register"
bitfld.long 0x00 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x04 "ICSSG_NEST_LEVEL_REG1,Host Int 1 Nesting Level Register"
bitfld.long 0x04 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x08 "ICSSG_NEST_LEVEL_REG2,Host Int 2 Nesting Level Register"
bitfld.long 0x08 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0x0C "ICSSG_NEST_LEVEL_REG3,Host Int 3 Nesting Level Register"
bitfld.long 0x0C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "ICSSG_NEST_LEVEL_REG4,Host Int 4 Nesting Level Register"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "ICSSG_NEST_LEVEL_REG5,Host Int 5 Nesting Level Register"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "ICSSG_NEST_LEVEL_REG6,Host Int 6 Nesting Level Register"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "ICSSG_NEST_LEVEL_REG7,Host Int 7 Nesting Level Register"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "ICSSG_NEST_LEVEL_REG8,Host Int 8 Nesting Level Register"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "ICSSG_NEST_LEVEL_REG9,Host Int 9 Nesting Level Register"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
line.long 0x28 "ICSSG_NEST_LEVEL_REG10,Host Int 10 Nesting Level Register"
bitfld.long 0x28 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x28 0.--8. 1. "NEST_HINT_10,Host Int 10 Nesting Level"
line.long 0x2C "ICSSG_NEST_LEVEL_REG11,Host Int 11 Nesting Level Register"
bitfld.long 0x2C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x2C 0.--8. 1. "NEST_HINT_11,Host Int 11 Nesting Level"
line.long 0x30 "ICSSG_NEST_LEVEL_REG12,Host Int 11 Nesting Level Register"
bitfld.long 0x30 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x30 0.--8. 1. "NEST_HINT_12,Host Int 12 Nesting Level"
line.long 0x34 "ICSSG_NEST_LEVEL_REG13,Host Int 11 Nesting Level Register"
bitfld.long 0x34 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x34 0.--8. 1. "NEST_HINT_13,Host Int 13 Nesting Level"
line.long 0x38 "ICSSG_NEST_LEVEL_REG14,Host Int 11 Nesting Level Register"
bitfld.long 0x38 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x38 0.--8. 1. "NEST_HINT_14,Host Int 14 Nesting Level"
line.long 0x3C "ICSSG_NEST_LEVEL_REG15,Host Int 11 Nesting Level Register"
bitfld.long 0x3C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x3C 0.--8. 1. "NEST_HINT_15,Host Int 15 Nesting Level"
line.long 0x40 "ICSSG_NEST_LEVEL_REG16,Host Int 11 Nesting Level Register"
bitfld.long 0x40 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x40 0.--8. 1. "NEST_HINT_16,Host Int 16 Nesting Level"
line.long 0x44 "ICSSG_NEST_LEVEL_REG17,Host Int 11 Nesting Level Register"
bitfld.long 0x44 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x44 0.--8. 1. "NEST_HINT_17,Host Int 17 Nesting Level"
line.long 0x48 "ICSSG_NEST_LEVEL_REG18,Host Int 11 Nesting Level Register"
bitfld.long 0x48 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x48 0.--8. 1. "NEST_HINT_18,Host Int 18 Nesting Level"
line.long 0x4C "ICSSG_NEST_LEVEL_REG19,Host Int 11 Nesting Level Register"
bitfld.long 0x4C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4C 0.--8. 1. "NEST_HINT_19,Host Int 19 Nesting Level"
group.long 0x1500++0x03
line.long 0x00 "ICSSG_ENABLE_HINT_REG0,Host Int Enable Register 0"
bitfld.long 0x00 19. "ENABLE_HINT_19,Enable for Host Int 19" "0,1"
bitfld.long 0x00 18. "ENABLE_HINT_18,Enable for Host Int 18" "0,1"
bitfld.long 0x00 17. "ENABLE_HINT_17,Enable for Host Int 17" "0,1"
bitfld.long 0x00 16. "ENABLE_HINT_16,Enable for Host Int 16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_HINT_15,Enable for Host Int 15" "0,1"
bitfld.long 0x00 14. "ENABLE_HINT_14,Enable for Host Int 14" "0,1"
bitfld.long 0x00 13. "ENABLE_HINT_13,Enable for Host Int 13" "0,1"
bitfld.long 0x00 12. "ENABLE_HINT_12,Enable for Host Int 12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_HINT_11,Enable for Host Int 11" "0,1"
bitfld.long 0x00 10. "ENABLE_HINT_10,Enable for Host Int 10" "0,1"
bitfld.long 0x00 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
bitfld.long 0x00 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x00 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
bitfld.long 0x00 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
bitfld.long 0x00 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x308)++0x03
line.long 0x00 "ICSSG_ENABLE_REG$1,Enable Register 2"
bitfld.long 0x00 31. "ENABLE_95,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_94,Enable (set) for slv_events_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_93,Enable (set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "ENABLE_92,Enable (set) for slv_events_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_91,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_90,Enable (set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_89,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_88,Enable (set) for slv_events_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_87,Enable (set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "ENABLE_86,Enable (set) for slv_events_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_85,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_84,Enable (set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_83,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_82,Enable (set) for slv_events_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_81,Enable (set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "ENABLE_80,Enable (set) for slv_events_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_79,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_78,Enable (set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_77,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_76,Enable (set) for slv_events_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_75,Enable (set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "ENABLE_74,Enable (set) for slv_events_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_73,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_72,Enable (set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_71,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_70,Enable (set) for slv_events_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_69,Enable (set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "ENABLE_68,Enable (set) for slv_events_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_67,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_66,Enable (set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_65,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_64,Enable (set) for slv_events_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x300)++0x03
line.long 0x00 "ICSSG_ENABLE_REG$1,Enable Register 0"
bitfld.long 0x00 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
repeat.end
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x288)++0x03
line.long 0x00 "ICSSG_ENA_STATUS_REG$1,Enabled Status Register 2"
bitfld.long 0x00 31. "ENA_STATUS_95,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "ENA_STATUS_94,Enabled Status for slv_events_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENA_STATUS_93,Enabled Status for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "ENA_STATUS_92,Enabled Status for slv_events_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENA_STATUS_91,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "ENA_STATUS_90,Enabled Status for slv_events_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENA_STATUS_89,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "ENA_STATUS_88,Enabled Status for slv_events_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENA_STATUS_87,Enabled Status for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "ENA_STATUS_86,Enabled Status for slv_events_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENA_STATUS_85,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "ENA_STATUS_84,Enabled Status for slv_events_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENA_STATUS_83,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "ENA_STATUS_82,Enabled Status for slv_events_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENA_STATUS_81,Enabled Status for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "ENA_STATUS_80,Enabled Status for slv_events_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENA_STATUS_79,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "ENA_STATUS_78,Enabled Status for slv_events_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENA_STATUS_77,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "ENA_STATUS_76,Enabled Status for slv_events_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENA_STATUS_75,Enabled Status for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "ENA_STATUS_74,Enabled Status for slv_events_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENA_STATUS_73,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "ENA_STATUS_72,Enabled Status for slv_events_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENA_STATUS_71,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "ENA_STATUS_70,Enabled Status for slv_events_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENA_STATUS_69,Enabled Status for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "ENA_STATUS_68,Enabled Status for slv_events_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENA_STATUS_67,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "ENA_STATUS_66,Enabled Status for slv_events_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENA_STATUS_65,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "ENA_STATUS_64,Enabled Status for slv_events_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x280)++0x03
line.long 0x00 "ICSSG_ENA_STATUS_REG$1,Enabled Status Register 0"
bitfld.long 0x00 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
bitfld.long 0x00 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
bitfld.long 0x00 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
bitfld.long 0x00 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
bitfld.long 0x00 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
bitfld.long 0x00 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
repeat.end
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x208)++0x03
line.long 0x00 "ICSSG_RAW_STATUS_REG$1,Raw Status Register 2"
bitfld.long 0x00 31. "RAW_STATUS_95,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "RAW_STATUS_94,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
newline
bitfld.long 0x00 29. "RAW_STATUS_93,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "RAW_STATUS_92,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
newline
bitfld.long 0x00 27. "RAW_STATUS_91,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "RAW_STATUS_90,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x00 25. "RAW_STATUS_89,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "RAW_STATUS_88,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
newline
bitfld.long 0x00 23. "RAW_STATUS_87,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "RAW_STATUS_86,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
newline
bitfld.long 0x00 21. "RAW_STATUS_85,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "RAW_STATUS_84,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x00 19. "RAW_STATUS_83,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "RAW_STATUS_82,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
newline
bitfld.long 0x00 17. "RAW_STATUS_81,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "RAW_STATUS_80,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
newline
bitfld.long 0x00 15. "RAW_STATUS_79,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "RAW_STATUS_78,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x00 13. "RAW_STATUS_77,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "RAW_STATUS_76,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
newline
bitfld.long 0x00 11. "RAW_STATUS_75,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "RAW_STATUS_74,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
newline
bitfld.long 0x00 9. "RAW_STATUS_73,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "RAW_STATUS_72,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x00 7. "RAW_STATUS_71,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "RAW_STATUS_70,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
newline
bitfld.long 0x00 5. "RAW_STATUS_69,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "RAW_STATUS_68,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
newline
bitfld.long 0x00 3. "RAW_STATUS_67,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "RAW_STATUS_66,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x00 1. "RAW_STATUS_65,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "RAW_STATUS_64,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x200)++0x03
line.long 0x00 "ICSSG_RAW_STATUS_REG$1,Raw Status Register 0"
bitfld.long 0x00 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
newline
bitfld.long 0x00 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
newline
bitfld.long 0x00 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
newline
bitfld.long 0x00 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
newline
bitfld.long 0x00 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
newline
bitfld.long 0x00 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
repeat.end
tree.end
tree "PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV"
base ad:0xB120000
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_REVISION_REG,Revision Register"
bitfld.long 0x00 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "REV_MODULE,Module ID"
bitfld.long 0x00 11.--15. "REV_RTL,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "REV_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x04 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x04 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "ICSSG_GLOBAL_ENABLE_HINT_REG,Global Host Int Enable Register"
bitfld.long 0x00 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x13
line.long 0x00 "ICSSG_GLB_NEST_LEVEL_REG,Global Nesting Level Register"
bitfld.long 0x00 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
line.long 0x04 "ICSSG_STATUS_SET_INDEX_REG,Status Set Index Register"
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x08 "ICSSG_STATUS_CLR_INDEX_REG,Status Clear Index Register"
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
line.long 0x0C "ICSSG_ENABLE_SET_INDEX_REG,Enable Set Index Register"
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x10 "ICSSG_ENABLE_CLR_INDEX_REG,Enable Clear Index Register"
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x07
line.long 0x00 "ICSSG_HINT_ENABLE_SET_INDEX_REG,Host Int Enable Set Index Register"
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x04 "ICSSG_HINT_ENABLE_CLR_INDEX_REG,Host Int Enable Clear Index Register"
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x03
line.long 0x00 "ICSSG_GLB_PRI_INTR_REG,Global Prioritized Interrupt Register"
bitfld.long 0x00 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
group.long 0x380++0x13
line.long 0x00 "ICSSG_ENABLE_CLR_REG0,Enable Clear Register 0"
bitfld.long 0x00 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
bitfld.long 0x00 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
bitfld.long 0x00 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
bitfld.long 0x00 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
bitfld.long 0x00 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
bitfld.long 0x00 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
bitfld.long 0x00 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
bitfld.long 0x00 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
bitfld.long 0x00 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x04 "ICSSG_ENABLE_CLR_REG1,Enable Clear Register 1"
bitfld.long 0x04 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x04 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x04 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
bitfld.long 0x04 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
newline
bitfld.long 0x04 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x04 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
bitfld.long 0x04 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x04 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
newline
bitfld.long 0x04 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
bitfld.long 0x04 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x04 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x04 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x04 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x04 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
bitfld.long 0x04 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
newline
bitfld.long 0x04 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x04 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
bitfld.long 0x04 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x04 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
newline
bitfld.long 0x04 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
bitfld.long 0x04 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x04 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x04 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x04 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x04 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
bitfld.long 0x04 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
newline
bitfld.long 0x04 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x04 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
bitfld.long 0x04 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x04 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
line.long 0x08 "ICSSG_ENABLE_CLR_REG2,Enable Clear Register 2"
bitfld.long 0x08 31. "ENABLE_95_CLR,Enable clear for slv_events_in[31]" "0,1"
bitfld.long 0x08 30. "ENABLE_94_CLR,Enable clear for slv_events_in[30]" "0,1"
bitfld.long 0x08 29. "ENABLE_93_CLR,Enable clear for slv_events_in[29]" "0,1"
bitfld.long 0x08 28. "ENABLE_92_CLR,Enable clear for slv_events_in[28]" "0,1"
newline
bitfld.long 0x08 27. "ENABLE_91_CLR,Enable clear for slv_events_in[27]" "0,1"
bitfld.long 0x08 26. "ENABLE_90_CLR,Enable clear for slv_events_in[26]" "0,1"
bitfld.long 0x08 25. "ENABLE_89_CLR,Enable clear for slv_events_in[25]" "0,1"
bitfld.long 0x08 24. "ENABLE_88_CLR,Enable clear for slv_events_in[24]" "0,1"
newline
bitfld.long 0x08 23. "ENABLE_87_CLR,Enable clear for slv_events_in[23]" "0,1"
bitfld.long 0x08 22. "ENABLE_86_CLR,Enable clear for slv_events_in[22]" "0,1"
bitfld.long 0x08 21. "ENABLE_85_CLR,Enable clear for slv_events_in[21]" "0,1"
bitfld.long 0x08 20. "ENABLE_84_CLR,Enable clear for slv_events_in[20]" "0,1"
newline
bitfld.long 0x08 19. "ENABLE_83_CLR,Enable clear for slv_events_in[19]" "0,1"
bitfld.long 0x08 18. "ENABLE_82_CLR,Enable clear for slv_events_in[18]" "0,1"
bitfld.long 0x08 17. "ENABLE_81_CLR,Enable clear for slv_events_in[17]" "0,1"
bitfld.long 0x08 16. "ENABLE_80_CLR,Enable clear for slv_events_in[16]" "0,1"
newline
bitfld.long 0x08 15. "ENABLE_79_CLR,Enable clear for slv_events_in[15]" "0,1"
bitfld.long 0x08 14. "ENABLE_78_CLR,Enable clear for slv_events_in[14]" "0,1"
bitfld.long 0x08 13. "ENABLE_77_CLR,Enable clear for slv_events_in[13]" "0,1"
bitfld.long 0x08 12. "ENABLE_76_CLR,Enable clear for slv_events_in[12]" "0,1"
newline
bitfld.long 0x08 11. "ENABLE_75_CLR,Enable clear for slv_events_in[11]" "0,1"
bitfld.long 0x08 10. "ENABLE_74_CLR,Enable clear for slv_events_in[10]" "0,1"
bitfld.long 0x08 9. "ENABLE_73_CLR,Enable clear for slv_events_in[9]" "0,1"
bitfld.long 0x08 8. "ENABLE_72_CLR,Enable clear for slv_events_in[8]" "0,1"
newline
bitfld.long 0x08 7. "ENABLE_71_CLR,Enable clear for slv_events_in[7]" "0,1"
bitfld.long 0x08 6. "ENABLE_70_CLR,Enable clear for slv_events_in[6]" "0,1"
bitfld.long 0x08 5. "ENABLE_69_CLR,Enable clear for slv_events_in[5]" "0,1"
bitfld.long 0x08 4. "ENABLE_68_CLR,Enable clear for slv_events_in[4]" "0,1"
newline
bitfld.long 0x08 3. "ENABLE_67_CLR,Enable clear for slv_events_in[3]" "0,1"
bitfld.long 0x08 2. "ENABLE_66_CLR,Enable clear for slv_events_in[2]" "0,1"
bitfld.long 0x08 1. "ENABLE_65_CLR,Enable clear for slv_events_in[1]" "0,1"
bitfld.long 0x08 0. "ENABLE_64_CLR,Enable clear for slv_events_in[0]" "0,1"
line.long 0x0C "ICSSG_ENABLE_CLR_REG3,Enable Clear Register 3"
bitfld.long 0x0C 31. "ENABLE_127_CLR,Enable clear for slv_events_in[63]" "0,1"
bitfld.long 0x0C 30. "ENABLE_126_CLR,Enable clear for slv_events_in[62]" "0,1"
bitfld.long 0x0C 29. "ENABLE_125_CLR,Enable clear for slv_events_in[61]" "0,1"
bitfld.long 0x0C 28. "ENABLE_124_CLR,Enable clear for slv_events_in[60]" "0,1"
newline
bitfld.long 0x0C 27. "ENABLE_123_CLR,Enable clear for slv_events_in[59]" "0,1"
bitfld.long 0x0C 26. "ENABLE_122_CLR,Enable clear for slv_events_in[58]" "0,1"
bitfld.long 0x0C 25. "ENABLE_121_CLR,Enable clear for slv_events_in[57]" "0,1"
bitfld.long 0x0C 24. "ENABLE_120_CLR,Enable clear for slv_events_in[56]" "0,1"
newline
bitfld.long 0x0C 23. "ENABLE_119_CLR,Enable clear for slv_events_in[55]" "0,1"
bitfld.long 0x0C 22. "ENABLE_118_CLR,Enable clear for slv_events_in[54]" "0,1"
bitfld.long 0x0C 21. "ENABLE_117_CLR,Enable clear for slv_events_in[53]" "0,1"
bitfld.long 0x0C 20. "ENABLE_116_CLR,Enable clear for slv_events_in[52]" "0,1"
newline
bitfld.long 0x0C 19. "ENABLE_115_CLR,Enable clear for slv_events_in[51]" "0,1"
bitfld.long 0x0C 18. "ENABLE_114_CLR,Enable clear for slv_events_in[50]" "0,1"
bitfld.long 0x0C 17. "ENABLE_113_CLR,Enable clear for slv_events_in[49]" "0,1"
bitfld.long 0x0C 16. "ENABLE_112_CLR,Enable clear for slv_events_in[48]" "0,1"
newline
bitfld.long 0x0C 15. "ENABLE_111_CLR,Enable clear for slv_events_in[47]" "0,1"
bitfld.long 0x0C 14. "ENABLE_110_CLR,Enable clear for slv_events_in[46]" "0,1"
bitfld.long 0x0C 13. "ENABLE_109_CLR,Enable clear for slv_events_in[45]" "0,1"
bitfld.long 0x0C 12. "ENABLE_108_CLR,Enable clear for slv_events_in[44]" "0,1"
newline
bitfld.long 0x0C 11. "ENABLE_107_CLR,Enable clear for slv_events_in[43]" "0,1"
bitfld.long 0x0C 10. "ENABLE_106_CLR,Enable clear for slv_events_in[42]" "0,1"
bitfld.long 0x0C 9. "ENABLE_105_CLR,Enable clear for slv_events_in[41]" "0,1"
bitfld.long 0x0C 8. "ENABLE_104_CLR,Enable clear for slv_events_in[40]" "0,1"
newline
bitfld.long 0x0C 7. "ENABLE_103_CLR,Enable clear for slv_events_in[39]" "0,1"
bitfld.long 0x0C 6. "ENABLE_102_CLR,Enable clear for slv_events_in[38]" "0,1"
bitfld.long 0x0C 5. "ENABLE_101_CLR,Enable clear for slv_events_in[37]" "0,1"
bitfld.long 0x0C 4. "ENABLE_100_CLR,Enable clear for slv_events_in[36]" "0,1"
newline
bitfld.long 0x0C 3. "ENABLE_99_CLR,Enable clear for slv_events_in[35]" "0,1"
bitfld.long 0x0C 2. "ENABLE_98_CLR,Enable clear for slv_events_in[34]" "0,1"
bitfld.long 0x0C 1. "ENABLE_97_CLR,Enable clear for slv_events_in[33]" "0,1"
bitfld.long 0x0C 0. "ENABLE_96_CLR,Enable clear for slv_events_in[32]" "0,1"
line.long 0x10 "ICSSG_ENABLE_CLR_REG4,Enable Clear Register 4"
bitfld.long 0x10 31. "ENABLE_159_CLR,Enable clear for slv_events_in[95]" "0,1"
bitfld.long 0x10 30. "ENABLE_158_CLR,Enable clear for slv_events_in[94]" "0,1"
bitfld.long 0x10 29. "ENABLE_157_CLR,Enable clear for slv_events_in[93]" "0,1"
bitfld.long 0x10 28. "ENABLE_156_CLR,Enable clear for slv_events_in[92]" "0,1"
newline
bitfld.long 0x10 27. "ENABLE_155_CLR,Enable clear for slv_events_in[91]" "0,1"
bitfld.long 0x10 26. "ENABLE_154_CLR,Enable clear for slv_events_in[90]" "0,1"
bitfld.long 0x10 25. "ENABLE_153_CLR,Enable clear for slv_events_in[89]" "0,1"
bitfld.long 0x10 24. "ENABLE_152_CLR,Enable clear for slv_events_in[88]" "0,1"
newline
bitfld.long 0x10 23. "ENABLE_151_CLR,Enable clear for slv_events_in[87]" "0,1"
bitfld.long 0x10 22. "ENABLE_150_CLR,Enable clear for slv_events_in[86]" "0,1"
bitfld.long 0x10 21. "ENABLE_149_CLR,Enable clear for slv_events_in[85]" "0,1"
bitfld.long 0x10 20. "ENABLE_148_CLR,Enable clear for slv_events_in[84]" "0,1"
newline
bitfld.long 0x10 19. "ENABLE_147_CLR,Enable clear for slv_events_in[83]" "0,1"
bitfld.long 0x10 18. "ENABLE_146_CLR,Enable clear for slv_events_in[82]" "0,1"
bitfld.long 0x10 17. "ENABLE_145_CLR,Enable clear for slv_events_in[81]" "0,1"
bitfld.long 0x10 16. "ENABLE_144_CLR,Enable clear for slv_events_in[80]" "0,1"
newline
bitfld.long 0x10 15. "ENABLE_143_CLR,Enable clear for slv_events_in[79]" "0,1"
bitfld.long 0x10 14. "ENABLE_142_CLR,Enable clear for slv_events_in[78]" "0,1"
bitfld.long 0x10 13. "ENABLE_141_CLR,Enable clear for slv_events_in[77]" "0,1"
bitfld.long 0x10 12. "ENABLE_140_CLR,Enable clear for slv_events_in[76]" "0,1"
newline
bitfld.long 0x10 11. "ENABLE_139_CLR,Enable clear for slv_events_in[75]" "0,1"
bitfld.long 0x10 10. "ENABLE_138_CLR,Enable clear for slv_events_in[74]" "0,1"
bitfld.long 0x10 9. "ENABLE_137_CLR,Enable clear for slv_events_in[73]" "0,1"
bitfld.long 0x10 8. "ENABLE_136_CLR,Enable clear for slv_events_in[72]" "0,1"
newline
bitfld.long 0x10 7. "ENABLE_135_CLR,Enable clear for slv_events_in[71]" "0,1"
bitfld.long 0x10 6. "ENABLE_134_CLR,Enable clear for slv_events_in[70]" "0,1"
bitfld.long 0x10 5. "ENABLE_133_CLR,Enable clear for slv_events_in[69]" "0,1"
bitfld.long 0x10 4. "ENABLE_132_CLR,Enable clear for slv_events_in[68]" "0,1"
newline
bitfld.long 0x10 3. "ENABLE_131_CLR,Enable clear for slv_events_in[67]" "0,1"
bitfld.long 0x10 2. "ENABLE_130_CLR,Enable clear for slv_events_in[66]" "0,1"
bitfld.long 0x10 1. "ENABLE_129_CLR,Enable clear for slv_events_in[65]" "0,1"
bitfld.long 0x10 0. "ENABLE_128_CLR,Enable clear for slv_events_in[64]" "0,1"
group.long 0x400++0x9F
line.long 0x00 "ICSSG_CH_MAP_REG0,Interrupt Channel Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. "CH_MAP_3,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "CH_MAP_2,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "CH_MAP_1,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "CH_MAP_0,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "ICSSG_CH_MAP_REG1,Interrupt Channel Map Register for 4 to 4+3"
bitfld.long 0x04 24.--28. "CH_MAP_7,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "CH_MAP_6,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "CH_MAP_5,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "CH_MAP_4,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ICSSG_CH_MAP_REG2,Interrupt Channel Map Register for 8 to 8+3"
bitfld.long 0x08 24.--28. "CH_MAP_11,Interrupt Channel Map for intr_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "CH_MAP_10,Interrupt Channel Map for intr_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "CH_MAP_9,Interrupt Channel Map for intr_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "CH_MAP_8,Interrupt Channel Map for intr_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "ICSSG_CH_MAP_REG3,Interrupt Channel Map Register for 12 to 12+3"
bitfld.long 0x0C 24.--28. "CH_MAP_15,Interrupt Channel Map for intr_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "CH_MAP_14,Interrupt Channel Map for intr_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "CH_MAP_13,Interrupt Channel Map for intr_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 0.--4. "CH_MAP_12,Interrupt Channel Map for intr_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ICSSG_CH_MAP_REG4,Interrupt Channel Map Register for 16 to 16+3"
bitfld.long 0x10 24.--28. "CH_MAP_19,Interrupt Channel Map for intr_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "CH_MAP_18,Interrupt Channel Map for intr_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "CH_MAP_17,Interrupt Channel Map for intr_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0.--4. "CH_MAP_16,Interrupt Channel Map for intr_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "ICSSG_CH_MAP_REG5,Interrupt Channel Map Register for 20 to 20+3"
bitfld.long 0x14 24.--28. "CH_MAP_23,Interrupt Channel Map for intr_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 16.--20. "CH_MAP_22,Interrupt Channel Map for intr_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 8.--12. "CH_MAP_21,Interrupt Channel Map for intr_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 0.--4. "CH_MAP_20,Interrupt Channel Map for intr_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "ICSSG_CH_MAP_REG6,Interrupt Channel Map Register for 24 to 24+3"
bitfld.long 0x18 24.--28. "CH_MAP_27,Interrupt Channel Map for intr_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 16.--20. "CH_MAP_26,Interrupt Channel Map for intr_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 8.--12. "CH_MAP_25,Interrupt Channel Map for intr_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 0.--4. "CH_MAP_24,Interrupt Channel Map for intr_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "ICSSG_CH_MAP_REG7,Interrupt Channel Map Register for 28 to 28+3"
bitfld.long 0x1C 24.--28. "CH_MAP_31,Interrupt Channel Map for intr_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 16.--20. "CH_MAP_30,Interrupt Channel Map for intr_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 8.--12. "CH_MAP_29,Interrupt Channel Map for intr_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--4. "CH_MAP_28,Interrupt Channel Map for intr_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "ICSSG_CH_MAP_REG8,Interrupt Channel Map Register for 32 to 32+3"
bitfld.long 0x20 24.--28. "CH_MAP_35,Interrupt Channel Map for intr_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 16.--20. "CH_MAP_34,Interrupt Channel Map for intr_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 8.--12. "CH_MAP_33,Interrupt Channel Map for intr_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 0.--4. "CH_MAP_32,Interrupt Channel Map for intr_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "ICSSG_CH_MAP_REG9,Interrupt Channel Map Register for 36 to 36+3"
bitfld.long 0x24 24.--28. "CH_MAP_39,Interrupt Channel Map for intr_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 16.--20. "CH_MAP_38,Interrupt Channel Map for intr_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 8.--12. "CH_MAP_37,Interrupt Channel Map for intr_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 0.--4. "CH_MAP_36,Interrupt Channel Map for intr_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "ICSSG_CH_MAP_REG10,Interrupt Channel Map Register for 40 to 40+3"
bitfld.long 0x28 24.--28. "CH_MAP_43,Interrupt Channel Map for intr_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 16.--20. "CH_MAP_42,Interrupt Channel Map for intr_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 8.--12. "CH_MAP_41,Interrupt Channel Map for intr_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--4. "CH_MAP_40,Interrupt Channel Map for intr_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "ICSSG_CH_MAP_REG11,Interrupt Channel Map Register for 44 to 44+3"
bitfld.long 0x2C 24.--28. "CH_MAP_47,Interrupt Channel Map for intr_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 16.--20. "CH_MAP_46,Interrupt Channel Map for intr_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 8.--12. "CH_MAP_45,Interrupt Channel Map for intr_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x2C 0.--4. "CH_MAP_44,Interrupt Channel Map for intr_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "ICSSG_CH_MAP_REG12,Interrupt Channel Map Register for 48 to 48+3"
bitfld.long 0x30 24.--28. "CH_MAP_51,Interrupt Channel Map for intr_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 16.--20. "CH_MAP_50,Interrupt Channel Map for intr_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 8.--12. "CH_MAP_49,Interrupt Channel Map for intr_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "CH_MAP_48,Interrupt Channel Map for intr_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_CH_MAP_REG13,Interrupt Channel Map Register for 52 to 52+3"
bitfld.long 0x34 24.--28. "CH_MAP_55,Interrupt Channel Map for intr_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 16.--20. "CH_MAP_54,Interrupt Channel Map for intr_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 8.--12. "CH_MAP_53,Interrupt Channel Map for intr_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 0.--4. "CH_MAP_52,Interrupt Channel Map for intr_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "ICSSG_CH_MAP_REG14,Interrupt Channel Map Register for 56 to 56+3"
bitfld.long 0x38 24.--28. "CH_MAP_59,Interrupt Channel Map for intr_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 16.--20. "CH_MAP_58,Interrupt Channel Map for intr_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 8.--12. "CH_MAP_57,Interrupt Channel Map for intr_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x38 0.--4. "CH_MAP_56,Interrupt Channel Map for intr_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "ICSSG_CH_MAP_REG15,Interrupt Channel Map Register for 60 to 60+3"
bitfld.long 0x3C 24.--28. "CH_MAP_63,Interrupt Channel Map for intr_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 16.--20. "CH_MAP_62,Interrupt Channel Map for intr_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 8.--12. "CH_MAP_61,Interrupt Channel Map for intr_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x3C 0.--4. "CH_MAP_60,Interrupt Channel Map for intr_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "ICSSG_CH_MAP_REG16,Interrupt Channel Map Register for 64 to 64+3"
bitfld.long 0x40 24.--28. "CH_MAP_67,Interrupt Channel Map for slv_events_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 16.--20. "CH_MAP_66,Interrupt Channel Map for slv_events_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 8.--12. "CH_MAP_65,Interrupt Channel Map for slv_events_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x40 0.--4. "CH_MAP_64,Interrupt Channel Map for slv_events_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "ICSSG_CH_MAP_REG17,Interrupt Channel Map Register for 68 to 68+3"
bitfld.long 0x44 24.--28. "CH_MAP_71,Interrupt Channel Map for slv_events_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 16.--20. "CH_MAP_70,Interrupt Channel Map for slv_events_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 8.--12. "CH_MAP_69,Interrupt Channel Map for slv_events_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 0.--4. "CH_MAP_68,Interrupt Channel Map for slv_events_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x48 "ICSSG_CH_MAP_REG18,Interrupt Channel Map Register for 72 to 72+3"
bitfld.long 0x48 24.--28. "CH_MAP_75,Interrupt Channel Map for slv_events_in[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 16.--20. "CH_MAP_74,Interrupt Channel Map for slv_events_in[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 8.--12. "CH_MAP_73,Interrupt Channel Map for slv_events_in[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x48 0.--4. "CH_MAP_72,Interrupt Channel Map for slv_events_in[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x4C "ICSSG_CH_MAP_REG19,Interrupt Channel Map Register for 76 to 76+3"
bitfld.long 0x4C 24.--28. "CH_MAP_79,Interrupt Channel Map for slv_events_in[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 16.--20. "CH_MAP_78,Interrupt Channel Map for slv_events_in[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 8.--12. "CH_MAP_77,Interrupt Channel Map for slv_events_in[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x4C 0.--4. "CH_MAP_76,Interrupt Channel Map for slv_events_in[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x50 "ICSSG_CH_MAP_REG20,Interrupt Channel Map Register for 80 to 80+3"
bitfld.long 0x50 24.--28. "CH_MAP_83,Interrupt Channel Map for slv_events_in[19]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 16.--20. "CH_MAP_82,Interrupt Channel Map for slv_events_in[18]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 8.--12. "CH_MAP_81,Interrupt Channel Map for slv_events_in[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x50 0.--4. "CH_MAP_80,Interrupt Channel Map for slv_events_in[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x54 "ICSSG_CH_MAP_REG21,Interrupt Channel Map Register for 84 to 84+3"
bitfld.long 0x54 24.--28. "CH_MAP_87,Interrupt Channel Map for slv_events_in[23]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 16.--20. "CH_MAP_86,Interrupt Channel Map for slv_events_in[22]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 8.--12. "CH_MAP_85,Interrupt Channel Map for slv_events_in[21]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x54 0.--4. "CH_MAP_84,Interrupt Channel Map for slv_events_in[20]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x58 "ICSSG_CH_MAP_REG22,Interrupt Channel Map Register for 88 to 88+3"
bitfld.long 0x58 24.--28. "CH_MAP_91,Interrupt Channel Map for slv_events_in[27]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 16.--20. "CH_MAP_90,Interrupt Channel Map for slv_events_in[26]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 8.--12. "CH_MAP_89,Interrupt Channel Map for slv_events_in[25]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 0.--4. "CH_MAP_88,Interrupt Channel Map for slv_events_in[24]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x5C "ICSSG_CH_MAP_REG23,Interrupt Channel Map Register for 92 to 92+3"
bitfld.long 0x5C 24.--28. "CH_MAP_95,Interrupt Channel Map for slv_events_in[31]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 16.--20. "CH_MAP_94,Interrupt Channel Map for slv_events_in[30]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 8.--12. "CH_MAP_93,Interrupt Channel Map for slv_events_in[29]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x5C 0.--4. "CH_MAP_92,Interrupt Channel Map for slv_events_in[28]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "ICSSG_CH_MAP_REG24,Interrupt Channel Map Register for 96 to 96+3"
bitfld.long 0x60 24.--28. "CH_MAP_99,Interrupt Channel Map for slv_events_in[35]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 16.--20. "CH_MAP_98,Interrupt Channel Map for slv_events_in[34]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 8.--12. "CH_MAP_97,Interrupt Channel Map for slv_events_in[33]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x60 0.--4. "CH_MAP_96,Interrupt Channel Map for slv_events_in[32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "ICSSG_CH_MAP_REG25,Interrupt Channel Map Register for 100 to 100+3"
bitfld.long 0x64 24.--28. "CH_MAP_103,Interrupt Channel Map for slv_events_in[39]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 16.--20. "CH_MAP_102,Interrupt Channel Map for slv_events_in[38]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 8.--12. "CH_MAP_101,Interrupt Channel Map for slv_events_in[37]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x64 0.--4. "CH_MAP_100,Interrupt Channel Map for slv_events_in[36]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "ICSSG_CH_MAP_REG26,Interrupt Channel Map Register for 104 to 104+3"
bitfld.long 0x68 24.--28. "CH_MAP_107,Interrupt Channel Map for slv_events_in[43]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 16.--20. "CH_MAP_106,Interrupt Channel Map for slv_events_in[42]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 8.--12. "CH_MAP_105,Interrupt Channel Map for slv_events_in[41]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x68 0.--4. "CH_MAP_104,Interrupt Channel Map for slv_events_in[40]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x6C "ICSSG_CH_MAP_REG27,Interrupt Channel Map Register for 108 to 108+3"
bitfld.long 0x6C 24.--28. "CH_MAP_111,Interrupt Channel Map for slv_events_in[47]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 16.--20. "CH_MAP_110,Interrupt Channel Map for slv_events_in[46]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 8.--12. "CH_MAP_109,Interrupt Channel Map for slv_events_in[45]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x6C 0.--4. "CH_MAP_108,Interrupt Channel Map for slv_events_in[44]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x70 "ICSSG_CH_MAP_REG28,Interrupt Channel Map Register for 112 to 112+3"
bitfld.long 0x70 24.--28. "CH_MAP_115,Interrupt Channel Map for slv_events_in[51]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 16.--20. "CH_MAP_114,Interrupt Channel Map for slv_events_in[50]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 8.--12. "CH_MAP_113,Interrupt Channel Map for slv_events_in[49]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x70 0.--4. "CH_MAP_112,Interrupt Channel Map for slv_events_in[48]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "ICSSG_CH_MAP_REG29,Interrupt Channel Map Register for 116 to 116+3"
bitfld.long 0x74 24.--28. "CH_MAP_119,Interrupt Channel Map for slv_events_in[55]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 16.--20. "CH_MAP_118,Interrupt Channel Map for slv_events_in[54]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 8.--12. "CH_MAP_117,Interrupt Channel Map for slv_events_in[53]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x74 0.--4. "CH_MAP_116,Interrupt Channel Map for slv_events_in[52]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x78 "ICSSG_CH_MAP_REG30,Interrupt Channel Map Register for 120 to 120+3"
bitfld.long 0x78 24.--28. "CH_MAP_123,Interrupt Channel Map for slv_events_in[59]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 16.--20. "CH_MAP_122,Interrupt Channel Map for slv_events_in[58]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 8.--12. "CH_MAP_121,Interrupt Channel Map for slv_events_in[57]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x78 0.--4. "CH_MAP_120,Interrupt Channel Map for slv_events_in[56]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x7C "ICSSG_CH_MAP_REG31,Interrupt Channel Map Register for 124 to 124+3"
bitfld.long 0x7C 24.--28. "CH_MAP_127,Interrupt Channel Map for slv_events_in[63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 16.--20. "CH_MAP_126,Interrupt Channel Map for slv_events_in[62]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 8.--12. "CH_MAP_125,Interrupt Channel Map for slv_events_in[61]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x7C 0.--4. "CH_MAP_124,Interrupt Channel Map for slv_events_in[60]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "ICSSG_CH_MAP_REG32,Interrupt Channel Map Register for 128 to 128+3"
bitfld.long 0x80 24.--28. "CH_MAP_131,Interrupt Channel Map for slv_events_in[67]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 16.--20. "CH_MAP_130,Interrupt Channel Map for slv_events_in[66]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 8.--12. "CH_MAP_129,Interrupt Channel Map for slv_events_in[65]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x80 0.--4. "CH_MAP_128,Interrupt Channel Map for slv_events_in[64]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "ICSSG_CH_MAP_REG33,Interrupt Channel Map Register for 132 to 132+3"
bitfld.long 0x84 24.--28. "CH_MAP_135,Interrupt Channel Map for slv_events_in[71]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 16.--20. "CH_MAP_134,Interrupt Channel Map for slv_events_in[70]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 8.--12. "CH_MAP_133,Interrupt Channel Map for slv_events_in[69]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x84 0.--4. "CH_MAP_132,Interrupt Channel Map for slv_events_in[68]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x88 "ICSSG_CH_MAP_REG34,Interrupt Channel Map Register for 136 to 136+3"
bitfld.long 0x88 24.--28. "CH_MAP_139,Interrupt Channel Map for slv_events_in[75]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 16.--20. "CH_MAP_138,Interrupt Channel Map for slv_events_in[74]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 8.--12. "CH_MAP_137,Interrupt Channel Map for slv_events_in[73]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x88 0.--4. "CH_MAP_136,Interrupt Channel Map for slv_events_in[72]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x8C "ICSSG_CH_MAP_REG35,Interrupt Channel Map Register for 140 to 140+3"
bitfld.long 0x8C 24.--28. "CH_MAP_143,Interrupt Channel Map for slv_events_in[79]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 16.--20. "CH_MAP_142,Interrupt Channel Map for slv_events_in[78]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 8.--12. "CH_MAP_141,Interrupt Channel Map for slv_events_in[77]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x8C 0.--4. "CH_MAP_140,Interrupt Channel Map for slv_events_in[76]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x90 "ICSSG_CH_MAP_REG36,Interrupt Channel Map Register for 144 to 144+3"
bitfld.long 0x90 24.--28. "CH_MAP_147,Interrupt Channel Map for slv_events_in[83]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 16.--20. "CH_MAP_146,Interrupt Channel Map for slv_events_in[82]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 8.--12. "CH_MAP_145,Interrupt Channel Map for slv_events_in[81]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x90 0.--4. "CH_MAP_144,Interrupt Channel Map for slv_events_in[80]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x94 "ICSSG_CH_MAP_REG37,Interrupt Channel Map Register for 148 to 148+3"
bitfld.long 0x94 24.--28. "CH_MAP_151,Interrupt Channel Map for slv_events_in[87]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 16.--20. "CH_MAP_150,Interrupt Channel Map for slv_events_in[86]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 8.--12. "CH_MAP_149,Interrupt Channel Map for slv_events_in[85]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x94 0.--4. "CH_MAP_148,Interrupt Channel Map for slv_events_in[84]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x98 "ICSSG_CH_MAP_REG38,Interrupt Channel Map Register for 152 to 152+3"
bitfld.long 0x98 24.--28. "CH_MAP_155,Interrupt Channel Map for slv_events_in[91]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 16.--20. "CH_MAP_154,Interrupt Channel Map for slv_events_in[90]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 8.--12. "CH_MAP_153,Interrupt Channel Map for slv_events_in[89]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x98 0.--4. "CH_MAP_152,Interrupt Channel Map for slv_events_in[88]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x9C "ICSSG_CH_MAP_REG39,Interrupt Channel Map Register for 156 to 156+3"
bitfld.long 0x9C 24.--28. "CH_MAP_159,Interrupt Channel Map for slv_events_in[95]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 16.--20. "CH_MAP_158,Interrupt Channel Map for slv_events_in[94]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 8.--12. "CH_MAP_157,Interrupt Channel Map for slv_events_in[93]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x9C 0.--4. "CH_MAP_156,Interrupt Channel Map for slv_events_in[92]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x800++0x13
line.long 0x00 "ICSSG_HINT_MAP_REG0,Host Interrupt Map Register for 0 to 0+3"
bitfld.long 0x00 24.--28. "HINT_MAP_3,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "HINT_MAP_2,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "HINT_MAP_1,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "HINT_MAP_0,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "ICSSG_HINT_MAP_REG1,Host Interrupt Map Register for 4 to 4+3"
bitfld.long 0x04 24.--28. "HINT_MAP_7,Host Interrupt Map for Channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 16.--20. "HINT_MAP_6,Host Interrupt Map for Channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "HINT_MAP_5,Host Interrupt Map for Channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--4. "HINT_MAP_4,Host Interrupt Map for Channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ICSSG_HINT_MAP_REG2,Host Interrupt Map Register for 8 to 8+3"
bitfld.long 0x08 24.--28. "HINT_MAP_11,Host Interrupt Map for Channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 16.--20. "HINT_MAP_10,Host Interrupt Map for Channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--12. "HINT_MAP_9,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 0.--4. "HINT_MAP_8,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "ICSSG_HINT_MAP_REG3,Host Interrupt Map Register for 12 to 12+3"
bitfld.long 0x0C 24.--28. "HINT_MAP_15,Host Interrupt Map for Channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 16.--20. "HINT_MAP_14,Host Interrupt Map for Channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 8.--12. "HINT_MAP_13,Host Interrupt Map for Channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 0.--4. "HINT_MAP_12,Host Interrupt Map for Channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ICSSG_HINT_MAP_REG4,Host Interrupt Map Register for 16 to 16+4"
bitfld.long 0x10 24.--28. "HINT_MAP_19,Host Interrupt Map for Channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 16.--20. "HINT_MAP_18,Host Interrupt Map for Channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 8.--12. "HINT_MAP_17,Host Interrupt Map for Channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 0.--4. "HINT_MAP_16,Host Interrupt Map for Channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x900++0x4F
line.long 0x00 "ICSSG_PRI_HINT_REG0,Host Int 0 Prioritized Interrupt Register"
bitfld.long 0x00 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x04 "ICSSG_PRI_HINT_REG1,Host Int 1 Prioritized Interrupt Register"
bitfld.long 0x04 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x08 "ICSSG_PRI_HINT_REG2,Host Int 2 Prioritized Interrupt Register"
bitfld.long 0x08 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0x0C "ICSSG_PRI_HINT_REG3,Host Int 3 Prioritized Interrupt Register"
bitfld.long 0x0C 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "ICSSG_PRI_HINT_REG4,Host Int 4 Prioritized Interrupt Register"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "ICSSG_PRI_HINT_REG5,Host Int 5 Prioritized Interrupt Register"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "ICSSG_PRI_HINT_REG6,Host Int 6 Prioritized Interrupt Register"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "ICSSG_PRI_HINT_REG7,Host Int 7 Prioritized Interrupt Register"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "ICSSG_PRI_HINT_REG8,Host Int 8 Prioritized Interrupt Register"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "ICSSG_PRI_HINT_REG9,Host Int 9 Prioritized Interrupt Register"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
line.long 0x28 "ICSSG_PRI_HINT_REG10,Host Int 10 Prioritized Interrupt Register"
bitfld.long 0x28 31. "NONE_HINT_10,No interrupt pending flag" "0,1"
hexmask.long.word 0x28 0.--9. 1. "PRI_HINT_10,Host Int 10 Prioritized Interrupt"
line.long 0x2C "ICSSG_PRI_HINT_REG11,Host Int 11 Prioritized Interrupt Register"
bitfld.long 0x2C 31. "NONE_HINT_11,No interrupt pending flag" "0,1"
hexmask.long.word 0x2C 0.--9. 1. "PRI_HINT_11,Host Int 11 Prioritized Interrupt"
line.long 0x30 "ICSSG_PRI_HINT_REG12,Host Int 12 Prioritized Interrupt Register"
bitfld.long 0x30 31. "NONE_HINT_12,No interrupt pending flag" "0,1"
hexmask.long.word 0x30 0.--9. 1. "PRI_HINT_12,Host Int 12 Prioritized Interrupt"
line.long 0x34 "ICSSG_PRI_HINT_REG13,Host Int 13 Prioritized Interrupt Register"
bitfld.long 0x34 31. "NONE_HINT_13,No interrupt pending flag" "0,1"
hexmask.long.word 0x34 0.--9. 1. "PRI_HINT_13,Host Int 13 Prioritized Interrupt"
line.long 0x38 "ICSSG_PRI_HINT_REG14,Host Int 14 Prioritized Interrupt Register"
bitfld.long 0x38 31. "NONE_HINT_14,No interrupt pending flag" "0,1"
hexmask.long.word 0x38 0.--9. 1. "PRI_HINT_14,Host Int 14 Prioritized Interrupt"
line.long 0x3C "ICSSG_PRI_HINT_REG15,Host Int 15 Prioritized Interrupt Register"
bitfld.long 0x3C 31. "NONE_HINT_15,No interrupt pending flag" "0,1"
hexmask.long.word 0x3C 0.--9. 1. "PRI_HINT_15,Host Int 15 Prioritized Interrupt"
line.long 0x40 "ICSSG_PRI_HINT_REG16,Host Int 16 Prioritized Interrupt Register"
bitfld.long 0x40 31. "NONE_HINT_16,No interrupt pending flag" "0,1"
hexmask.long.word 0x40 0.--9. 1. "PRI_HINT_16,Host Int 16 Prioritized Interrupt"
line.long 0x44 "ICSSG_PRI_HINT_REG17,Host Int 17 Prioritized Interrupt Register"
bitfld.long 0x44 31. "NONE_HINT_17,No interrupt pending flag" "0,1"
hexmask.long.word 0x44 0.--9. 1. "PRI_HINT_17,Host Int 17 Prioritized Interrupt"
line.long 0x48 "ICSSG_PRI_HINT_REG18,Host Int 18 Prioritized Interrupt Register"
bitfld.long 0x48 31. "NONE_HINT_18,No interrupt pending flag" "0,1"
hexmask.long.word 0x48 0.--9. 1. "PRI_HINT_18,Host Int 18 Prioritized Interrupt"
line.long 0x4C "ICSSG_PRI_HINT_REG19,Host Int 19 Prioritized Interrupt Register"
bitfld.long 0x4C 31. "NONE_HINT_19,No interrupt pending flag" "0,1"
hexmask.long.word 0x4C 0.--9. 1. "PRI_HINT_19,Host Int 19 Prioritized Interrupt"
group.long 0xD00++0x13
line.long 0x00 "ICSSG_POLARITY_REG0,Polarity Register 0"
bitfld.long 0x00 31. "POLARITY_31,Polarity for intr_in[31]0=low" "0,1"
bitfld.long 0x00 30. "POLARITY_30,Polarity for intr_in[30]0=low" "0,1"
bitfld.long 0x00 29. "POLARITY_29,Polarity for intr_in[29]0=low" "0,1"
bitfld.long 0x00 28. "POLARITY_28,Polarity for intr_in[28]0=low" "0,1"
newline
bitfld.long 0x00 27. "POLARITY_27,Polarity for intr_in[27]0=low" "0,1"
bitfld.long 0x00 26. "POLARITY_26,Polarity for intr_in[26]0=low" "0,1"
bitfld.long 0x00 25. "POLARITY_25,Polarity for intr_in[25]0=low" "0,1"
bitfld.long 0x00 24. "POLARITY_24,Polarity for intr_in[24]0=low" "0,1"
newline
bitfld.long 0x00 23. "POLARITY_23,Polarity for intr_in[23]0=low" "0,1"
bitfld.long 0x00 22. "POLARITY_22,Polarity for intr_in[22]0=low" "0,1"
bitfld.long 0x00 21. "POLARITY_21,Polarity for intr_in[21]0=low" "0,1"
bitfld.long 0x00 20. "POLARITY_20,Polarity for intr_in[20]0=low" "0,1"
newline
bitfld.long 0x00 19. "POLARITY_19,Polarity for intr_in[19]0=low" "0,1"
bitfld.long 0x00 18. "POLARITY_18,Polarity for intr_in[18]0=low" "0,1"
bitfld.long 0x00 17. "POLARITY_17,Polarity for intr_in[17]0=low" "0,1"
bitfld.long 0x00 16. "POLARITY_16,Polarity for intr_in[16]0=low" "0,1"
newline
bitfld.long 0x00 15. "POLARITY_15,Polarity for intr_in[15]0=low" "0,1"
bitfld.long 0x00 14. "POLARITY_14,Polarity for intr_in[14]0=low" "0,1"
bitfld.long 0x00 13. "POLARITY_13,Polarity for intr_in[13]0=low" "0,1"
bitfld.long 0x00 12. "POLARITY_12,Polarity for intr_in[12]0=low" "0,1"
newline
bitfld.long 0x00 11. "POLARITY_11,Polarity for intr_in[11]0=low" "0,1"
bitfld.long 0x00 10. "POLARITY_10,Polarity for intr_in[10]0=low" "0,1"
bitfld.long 0x00 9. "POLARITY_9,Polarity for intr_in[9]0=low" "0,1"
bitfld.long 0x00 8. "POLARITY_8,Polarity for intr_in[8]0=low" "0,1"
newline
bitfld.long 0x00 7. "POLARITY_7,Polarity for intr_in[7]0=low" "0,1"
bitfld.long 0x00 6. "POLARITY_6,Polarity for intr_in[6]0=low" "0,1"
bitfld.long 0x00 5. "POLARITY_5,Polarity for intr_in[5]0=low" "0,1"
bitfld.long 0x00 4. "POLARITY_4,Polarity for intr_in[4]0=low" "0,1"
newline
bitfld.long 0x00 3. "POLARITY_3,Polarity for intr_in[3]0=low" "0,1"
bitfld.long 0x00 2. "POLARITY_2,Polarity for intr_in[2]0=low" "0,1"
bitfld.long 0x00 1. "POLARITY_1,Polarity for intr_in[1]0=low" "0,1"
bitfld.long 0x00 0. "POLARITY_0,Polarity for intr_in[0]0=low" "0,1"
line.long 0x04 "ICSSG_POLARITY_REG1,Polarity Register 1"
bitfld.long 0x04 31. "POLARITY_63,Polarity for intr_in[63]0=low" "0,1"
bitfld.long 0x04 30. "POLARITY_62,Polarity for intr_in[62]0=low" "0,1"
bitfld.long 0x04 29. "POLARITY_61,Polarity for intr_in[61]0=low" "0,1"
bitfld.long 0x04 28. "POLARITY_60,Polarity for intr_in[60]0=low" "0,1"
newline
bitfld.long 0x04 27. "POLARITY_59,Polarity for intr_in[59]0=low" "0,1"
bitfld.long 0x04 26. "POLARITY_58,Polarity for intr_in[58]0=low" "0,1"
bitfld.long 0x04 25. "POLARITY_57,Polarity for intr_in[57]0=low" "0,1"
bitfld.long 0x04 24. "POLARITY_56,Polarity for intr_in[56]0=low" "0,1"
newline
bitfld.long 0x04 23. "POLARITY_55,Polarity for intr_in[55]0=low" "0,1"
bitfld.long 0x04 22. "POLARITY_54,Polarity for intr_in[54]0=low" "0,1"
bitfld.long 0x04 21. "POLARITY_53,Polarity for intr_in[53]0=low" "0,1"
bitfld.long 0x04 20. "POLARITY_52,Polarity for intr_in[52]0=low" "0,1"
newline
bitfld.long 0x04 19. "POLARITY_51,Polarity for intr_in[51]0=low" "0,1"
bitfld.long 0x04 18. "POLARITY_50,Polarity for intr_in[50]0=low" "0,1"
bitfld.long 0x04 17. "POLARITY_49,Polarity for intr_in[49]0=low" "0,1"
bitfld.long 0x04 16. "POLARITY_48,Polarity for intr_in[48]0=low" "0,1"
newline
bitfld.long 0x04 15. "POLARITY_47,Polarity for intr_in[47]0=low" "0,1"
bitfld.long 0x04 14. "POLARITY_46,Polarity for intr_in[46]0=low" "0,1"
bitfld.long 0x04 13. "POLARITY_45,Polarity for intr_in[45]0=low" "0,1"
bitfld.long 0x04 12. "POLARITY_44,Polarity for intr_in[44]0=low" "0,1"
newline
bitfld.long 0x04 11. "POLARITY_43,Polarity for intr_in[43]0=low" "0,1"
bitfld.long 0x04 10. "POLARITY_42,Polarity for intr_in[42]0=low" "0,1"
bitfld.long 0x04 9. "POLARITY_41,Polarity for intr_in[41]0=low" "0,1"
bitfld.long 0x04 8. "POLARITY_40,Polarity for intr_in[40]0=low" "0,1"
newline
bitfld.long 0x04 7. "POLARITY_39,Polarity for intr_in[39]0=low" "0,1"
bitfld.long 0x04 6. "POLARITY_38,Polarity for intr_in[38]0=low" "0,1"
bitfld.long 0x04 5. "POLARITY_37,Polarity for intr_in[37]0=low" "0,1"
bitfld.long 0x04 4. "POLARITY_36,Polarity for intr_in[36]0=low" "0,1"
newline
bitfld.long 0x04 3. "POLARITY_35,Polarity for intr_in[35]0=low" "0,1"
bitfld.long 0x04 2. "POLARITY_34,Polarity for intr_in[34]0=low" "0,1"
bitfld.long 0x04 1. "POLARITY_33,Polarity for intr_in[33]0=low" "0,1"
bitfld.long 0x04 0. "POLARITY_32,Polarity for intr_in[32]0=low" "0,1"
line.long 0x08 "ICSSG_POLARITY_REG2,Polarity Register 2"
bitfld.long 0x08 31. "POLARITY_95,Polarity for slv_events_in[31]0=low" "0,1"
bitfld.long 0x08 30. "POLARITY_94,Polarity for slv_events_in[30]0=low" "0,1"
bitfld.long 0x08 29. "POLARITY_93,Polarity for slv_events_in[29]0=low" "0,1"
bitfld.long 0x08 28. "POLARITY_92,Polarity for slv_events_in[28]0=low" "0,1"
newline
bitfld.long 0x08 27. "POLARITY_91,Polarity for slv_events_in[27]0=low" "0,1"
bitfld.long 0x08 26. "POLARITY_90,Polarity for slv_events_in[26]0=low" "0,1"
bitfld.long 0x08 25. "POLARITY_89,Polarity for slv_events_in[25]0=low" "0,1"
bitfld.long 0x08 24. "POLARITY_88,Polarity for slv_events_in[24]0=low" "0,1"
newline
bitfld.long 0x08 23. "POLARITY_87,Polarity for slv_events_in[23]0=low" "0,1"
bitfld.long 0x08 22. "POLARITY_86,Polarity for slv_events_in[22]0=low" "0,1"
bitfld.long 0x08 21. "POLARITY_85,Polarity for slv_events_in[21]0=low" "0,1"
bitfld.long 0x08 20. "POLARITY_84,Polarity for slv_events_in[20]0=low" "0,1"
newline
bitfld.long 0x08 19. "POLARITY_83,Polarity for slv_events_in[19]0=low" "0,1"
bitfld.long 0x08 18. "POLARITY_82,Polarity for slv_events_in[18]0=low" "0,1"
bitfld.long 0x08 17. "POLARITY_81,Polarity for slv_events_in[17]0=low" "0,1"
bitfld.long 0x08 16. "POLARITY_80,Polarity for slv_events_in[16]0=low" "0,1"
newline
bitfld.long 0x08 15. "POLARITY_79,Polarity for slv_events_in[15]0=low" "0,1"
bitfld.long 0x08 14. "POLARITY_78,Polarity for slv_events_in[14]0=low" "0,1"
bitfld.long 0x08 13. "POLARITY_77,Polarity for slv_events_in[13]0=low" "0,1"
bitfld.long 0x08 12. "POLARITY_76,Polarity for slv_events_in[12]0=low" "0,1"
newline
bitfld.long 0x08 11. "POLARITY_75,Polarity for slv_events_in[11]0=low" "0,1"
bitfld.long 0x08 10. "POLARITY_74,Polarity for slv_events_in[10]0=low" "0,1"
bitfld.long 0x08 9. "POLARITY_73,Polarity for slv_events_in[9]0=low" "0,1"
bitfld.long 0x08 8. "POLARITY_72,Polarity for slv_events_in[8]0=low" "0,1"
newline
bitfld.long 0x08 7. "POLARITY_71,Polarity for slv_events_in[7]0=low" "0,1"
bitfld.long 0x08 6. "POLARITY_70,Polarity for slv_events_in[6]0=low" "0,1"
bitfld.long 0x08 5. "POLARITY_69,Polarity for slv_events_in[5]0=low" "0,1"
bitfld.long 0x08 4. "POLARITY_68,Polarity for slv_events_in[4]0=low" "0,1"
newline
bitfld.long 0x08 3. "POLARITY_67,Polarity for slv_events_in[3]0=low" "0,1"
bitfld.long 0x08 2. "POLARITY_66,Polarity for slv_events_in[2]0=low" "0,1"
bitfld.long 0x08 1. "POLARITY_65,Polarity for slv_events_in[1]0=low" "0,1"
bitfld.long 0x08 0. "POLARITY_64,Polarity for slv_events_in[0]0=low" "0,1"
line.long 0x0C "ICSSG_POLARITY_REG3,Polarity Register 3"
bitfld.long 0x0C 31. "POLARITY_127,Polarity for slv_events_in[63]0=low" "0,1"
bitfld.long 0x0C 30. "POLARITY_126,Polarity for slv_events_in[62]0=low" "0,1"
bitfld.long 0x0C 29. "POLARITY_125,Polarity for slv_events_in[61]0=low" "0,1"
bitfld.long 0x0C 28. "POLARITY_124,Polarity for slv_events_in[60]0=low" "0,1"
newline
bitfld.long 0x0C 27. "POLARITY_123,Polarity for slv_events_in[59]0=low" "0,1"
bitfld.long 0x0C 26. "POLARITY_122,Polarity for slv_events_in[58]0=low" "0,1"
bitfld.long 0x0C 25. "POLARITY_121,Polarity for slv_events_in[57]0=low" "0,1"
bitfld.long 0x0C 24. "POLARITY_120,Polarity for slv_events_in[56]0=low" "0,1"
newline
bitfld.long 0x0C 23. "POLARITY_119,Polarity for slv_events_in[55]0=low" "0,1"
bitfld.long 0x0C 22. "POLARITY_118,Polarity for slv_events_in[54]0=low" "0,1"
bitfld.long 0x0C 21. "POLARITY_117,Polarity for slv_events_in[53]0=low" "0,1"
bitfld.long 0x0C 20. "POLARITY_116,Polarity for slv_events_in[52]0=low" "0,1"
newline
bitfld.long 0x0C 19. "POLARITY_115,Polarity for slv_events_in[51]0=low" "0,1"
bitfld.long 0x0C 18. "POLARITY_114,Polarity for slv_events_in[50]0=low" "0,1"
bitfld.long 0x0C 17. "POLARITY_113,Polarity for slv_events_in[49]0=low" "0,1"
bitfld.long 0x0C 16. "POLARITY_112,Polarity for slv_events_in[48]0=low" "0,1"
newline
bitfld.long 0x0C 15. "POLARITY_111,Polarity for slv_events_in[47]0=low" "0,1"
bitfld.long 0x0C 14. "POLARITY_110,Polarity for slv_events_in[46]0=low" "0,1"
bitfld.long 0x0C 13. "POLARITY_109,Polarity for slv_events_in[45]0=low" "0,1"
bitfld.long 0x0C 12. "POLARITY_108,Polarity for slv_events_in[44]0=low" "0,1"
newline
bitfld.long 0x0C 11. "POLARITY_107,Polarity for slv_events_in[43]0=low" "0,1"
bitfld.long 0x0C 10. "POLARITY_106,Polarity for slv_events_in[42]0=low" "0,1"
bitfld.long 0x0C 9. "POLARITY_105,Polarity for slv_events_in[41]0=low" "0,1"
bitfld.long 0x0C 8. "POLARITY_104,Polarity for slv_events_in[40]0=low" "0,1"
newline
bitfld.long 0x0C 7. "POLARITY_103,Polarity for slv_events_in[39]0=low" "0,1"
bitfld.long 0x0C 6. "POLARITY_102,Polarity for slv_events_in[38]0=low" "0,1"
bitfld.long 0x0C 5. "POLARITY_101,Polarity for slv_events_in[37]0=low" "0,1"
bitfld.long 0x0C 4. "POLARITY_100,Polarity for slv_events_in[36]0=low" "0,1"
newline
bitfld.long 0x0C 3. "POLARITY_99,Polarity for slv_events_in[35]0=low" "0,1"
bitfld.long 0x0C 2. "POLARITY_98,Polarity for slv_events_in[34]0=low" "0,1"
bitfld.long 0x0C 1. "POLARITY_97,Polarity for slv_events_in[33]0=low" "0,1"
bitfld.long 0x0C 0. "POLARITY_96,Polarity for slv_events_in[32]0=low" "0,1"
line.long 0x10 "ICSSG_POLARITY_REG4,Polarity Register 4"
bitfld.long 0x10 31. "POLARITY_159,Polarity for slv_events_in[95]0=low" "0,1"
bitfld.long 0x10 30. "POLARITY_158,Polarity for slv_events_in[94]0=low" "0,1"
bitfld.long 0x10 29. "POLARITY_157,Polarity for slv_events_in[93]0=low" "0,1"
bitfld.long 0x10 28. "POLARITY_156,Polarity for slv_events_in[92]0=low" "0,1"
newline
bitfld.long 0x10 27. "POLARITY_155,Polarity for slv_events_in[91]0=low" "0,1"
bitfld.long 0x10 26. "POLARITY_154,Polarity for slv_events_in[90]0=low" "0,1"
bitfld.long 0x10 25. "POLARITY_153,Polarity for slv_events_in[89]0=low" "0,1"
bitfld.long 0x10 24. "POLARITY_152,Polarity for slv_events_in[88]0=low" "0,1"
newline
bitfld.long 0x10 23. "POLARITY_151,Polarity for slv_events_in[87]0=low" "0,1"
bitfld.long 0x10 22. "POLARITY_150,Polarity for slv_events_in[86]0=low" "0,1"
bitfld.long 0x10 21. "POLARITY_149,Polarity for slv_events_in[85]0=low" "0,1"
bitfld.long 0x10 20. "POLARITY_148,Polarity for slv_events_in[84]0=low" "0,1"
newline
bitfld.long 0x10 19. "POLARITY_147,Polarity for slv_events_in[83]0=low" "0,1"
bitfld.long 0x10 18. "POLARITY_146,Polarity for slv_events_in[82]0=low" "0,1"
bitfld.long 0x10 17. "POLARITY_145,Polarity for slv_events_in[81]0=low" "0,1"
bitfld.long 0x10 16. "POLARITY_144,Polarity for slv_events_in[80]0=low" "0,1"
newline
bitfld.long 0x10 15. "POLARITY_143,Polarity for slv_events_in[79]0=low" "0,1"
bitfld.long 0x10 14. "POLARITY_142,Polarity for slv_events_in[78]0=low" "0,1"
bitfld.long 0x10 13. "POLARITY_141,Polarity for slv_events_in[77]0=low" "0,1"
bitfld.long 0x10 12. "POLARITY_140,Polarity for slv_events_in[76]0=low" "0,1"
newline
bitfld.long 0x10 11. "POLARITY_139,Polarity for slv_events_in[75]0=low" "0,1"
bitfld.long 0x10 10. "POLARITY_138,Polarity for slv_events_in[74]0=low" "0,1"
bitfld.long 0x10 9. "POLARITY_137,Polarity for slv_events_in[73]0=low" "0,1"
bitfld.long 0x10 8. "POLARITY_136,Polarity for slv_events_in[72]0=low" "0,1"
newline
bitfld.long 0x10 7. "POLARITY_135,Polarity for slv_events_in[71]0=low" "0,1"
bitfld.long 0x10 6. "POLARITY_134,Polarity for slv_events_in[70]0=low" "0,1"
bitfld.long 0x10 5. "POLARITY_133,Polarity for slv_events_in[69]0=low" "0,1"
bitfld.long 0x10 4. "POLARITY_132,Polarity for slv_events_in[68]0=low" "0,1"
newline
bitfld.long 0x10 3. "POLARITY_131,Polarity for slv_events_in[67]0=low" "0,1"
bitfld.long 0x10 2. "POLARITY_130,Polarity for slv_events_in[66]0=low" "0,1"
bitfld.long 0x10 1. "POLARITY_129,Polarity for slv_events_in[65]0=low" "0,1"
bitfld.long 0x10 0. "POLARITY_128,Polarity for slv_events_in[64]0=low" "0,1"
group.long 0xD80++0x13
line.long 0x00 "ICSSG_TYPE_REG0,Type Register 0"
bitfld.long 0x00 31. "TYPE_31,Type for intr_in[31]0=level" "0,1"
bitfld.long 0x00 30. "TYPE_30,Type for intr_in[30]0=level" "0,1"
bitfld.long 0x00 29. "TYPE_29,Type for intr_in[29]0=level" "0,1"
bitfld.long 0x00 28. "TYPE_28,Type for intr_in[28]0=level" "0,1"
newline
bitfld.long 0x00 27. "TYPE_27,Type for intr_in[27]0=level" "0,1"
bitfld.long 0x00 26. "TYPE_26,Type for intr_in[26]0=level" "0,1"
bitfld.long 0x00 25. "TYPE_25,Type for intr_in[25]0=level" "0,1"
bitfld.long 0x00 24. "TYPE_24,Type for intr_in[24]0=level" "0,1"
newline
bitfld.long 0x00 23. "TYPE_23,Type for intr_in[23]0=level" "0,1"
bitfld.long 0x00 22. "TYPE_22,Type for intr_in[22]0=level" "0,1"
bitfld.long 0x00 21. "TYPE_21,Type for intr_in[21]0=level" "0,1"
bitfld.long 0x00 20. "TYPE_20,Type for intr_in[20]0=level" "0,1"
newline
bitfld.long 0x00 19. "TYPE_19,Type for intr_in[19]0=level" "0,1"
bitfld.long 0x00 18. "TYPE_18,Type for intr_in[18]0=level" "0,1"
bitfld.long 0x00 17. "TYPE_17,Type for intr_in[17]0=level" "0,1"
bitfld.long 0x00 16. "TYPE_16,Type for intr_in[16]0=level" "0,1"
newline
bitfld.long 0x00 15. "TYPE_15,Type for intr_in[15]0=level" "0,1"
bitfld.long 0x00 14. "TYPE_14,Type for intr_in[14]0=level" "0,1"
bitfld.long 0x00 13. "TYPE_13,Type for intr_in[13]0=level" "0,1"
bitfld.long 0x00 12. "TYPE_12,Type for intr_in[12]0=level" "0,1"
newline
bitfld.long 0x00 11. "TYPE_11,Type for intr_in[11]0=level" "0,1"
bitfld.long 0x00 10. "TYPE_10,Type for intr_in[10]0=level" "0,1"
bitfld.long 0x00 9. "TYPE_9,Type for intr_in[9]0=level" "0,1"
bitfld.long 0x00 8. "TYPE_8,Type for intr_in[8]0=level" "0,1"
newline
bitfld.long 0x00 7. "TYPE_7,Type for intr_in[7]0=level" "0,1"
bitfld.long 0x00 6. "TYPE_6,Type for intr_in[6]0=level" "0,1"
bitfld.long 0x00 5. "TYPE_5,Type for intr_in[5]0=level" "0,1"
bitfld.long 0x00 4. "TYPE_4,Type for intr_in[4]0=level" "0,1"
newline
bitfld.long 0x00 3. "TYPE_3,Type for intr_in[3]0=level" "0,1"
bitfld.long 0x00 2. "TYPE_2,Type for intr_in[2]0=level" "0,1"
bitfld.long 0x00 1. "TYPE_1,Type for intr_in[1]0=level" "0,1"
bitfld.long 0x00 0. "TYPE_0,Type for intr_in[0]0=level" "0,1"
line.long 0x04 "ICSSG_TYPE_REG1,Type Register 1"
bitfld.long 0x04 31. "TYPE_63,Type for intr_in[63]0=level" "0,1"
bitfld.long 0x04 30. "TYPE_62,Type for intr_in[62]0=level" "0,1"
bitfld.long 0x04 29. "TYPE_61,Type for intr_in[61]0=level" "0,1"
bitfld.long 0x04 28. "TYPE_60,Type for intr_in[60]0=level" "0,1"
newline
bitfld.long 0x04 27. "TYPE_59,Type for intr_in[59]0=level" "0,1"
bitfld.long 0x04 26. "TYPE_58,Type for intr_in[58]0=level" "0,1"
bitfld.long 0x04 25. "TYPE_57,Type for intr_in[57]0=level" "0,1"
bitfld.long 0x04 24. "TYPE_56,Type for intr_in[56]0=level" "0,1"
newline
bitfld.long 0x04 23. "TYPE_55,Type for intr_in[55]0=level" "0,1"
bitfld.long 0x04 22. "TYPE_54,Type for intr_in[54]0=level" "0,1"
bitfld.long 0x04 21. "TYPE_53,Type for intr_in[53]0=level" "0,1"
bitfld.long 0x04 20. "TYPE_52,Type for intr_in[52]0=level" "0,1"
newline
bitfld.long 0x04 19. "TYPE_51,Type for intr_in[51]0=level" "0,1"
bitfld.long 0x04 18. "TYPE_50,Type for intr_in[50]0=level" "0,1"
bitfld.long 0x04 17. "TYPE_49,Type for intr_in[49]0=level" "0,1"
bitfld.long 0x04 16. "TYPE_48,Type for intr_in[48]0=level" "0,1"
newline
bitfld.long 0x04 15. "TYPE_47,Type for intr_in[47]0=level" "0,1"
bitfld.long 0x04 14. "TYPE_46,Type for intr_in[46]0=level" "0,1"
bitfld.long 0x04 13. "TYPE_45,Type for intr_in[45]0=level" "0,1"
bitfld.long 0x04 12. "TYPE_44,Type for intr_in[44]0=level" "0,1"
newline
bitfld.long 0x04 11. "TYPE_43,Type for intr_in[43]0=level" "0,1"
bitfld.long 0x04 10. "TYPE_42,Type for intr_in[42]0=level" "0,1"
bitfld.long 0x04 9. "TYPE_41,Type for intr_in[41]0=level" "0,1"
bitfld.long 0x04 8. "TYPE_40,Type for intr_in[40]0=level" "0,1"
newline
bitfld.long 0x04 7. "TYPE_39,Type for intr_in[39]0=level" "0,1"
bitfld.long 0x04 6. "TYPE_38,Type for intr_in[38]0=level" "0,1"
bitfld.long 0x04 5. "TYPE_37,Type for intr_in[37]0=level" "0,1"
bitfld.long 0x04 4. "TYPE_36,Type for intr_in[36]0=level" "0,1"
newline
bitfld.long 0x04 3. "TYPE_35,Type for intr_in[35]0=level" "0,1"
bitfld.long 0x04 2. "TYPE_34,Type for intr_in[34]0=level" "0,1"
bitfld.long 0x04 1. "TYPE_33,Type for intr_in[33]0=level" "0,1"
bitfld.long 0x04 0. "TYPE_32,Type for intr_in[32]0=level" "0,1"
line.long 0x08 "ICSSG_TYPE_REG2,Type Register 2"
bitfld.long 0x08 31. "TYPE_95,Type for slv_events_in[31]0=level" "0,1"
bitfld.long 0x08 30. "TYPE_94,Type for slv_events_in[30]0=level" "0,1"
bitfld.long 0x08 29. "TYPE_93,Type for slv_events_in[29]0=level" "0,1"
bitfld.long 0x08 28. "TYPE_92,Type for slv_events_in[28]0=level" "0,1"
newline
bitfld.long 0x08 27. "TYPE_91,Type for slv_events_in[27]0=level" "0,1"
bitfld.long 0x08 26. "TYPE_90,Type for slv_events_in[26]0=level" "0,1"
bitfld.long 0x08 25. "TYPE_89,Type for slv_events_in[25]0=level" "0,1"
bitfld.long 0x08 24. "TYPE_88,Type for slv_events_in[24]0=level" "0,1"
newline
bitfld.long 0x08 23. "TYPE_87,Type for slv_events_in[23]0=level" "0,1"
bitfld.long 0x08 22. "TYPE_86,Type for slv_events_in[22]0=level" "0,1"
bitfld.long 0x08 21. "TYPE_85,Type for slv_events_in[21]0=level" "0,1"
bitfld.long 0x08 20. "TYPE_84,Type for slv_events_in[20]0=level" "0,1"
newline
bitfld.long 0x08 19. "TYPE_83,Type for slv_events_in[19]0=level" "0,1"
bitfld.long 0x08 18. "TYPE_82,Type for slv_events_in[18]0=level" "0,1"
bitfld.long 0x08 17. "TYPE_81,Type for slv_events_in[17]0=level" "0,1"
bitfld.long 0x08 16. "TYPE_80,Type for slv_events_in[16]0=level" "0,1"
newline
bitfld.long 0x08 15. "TYPE_79,Type for slv_events_in[15]0=level" "0,1"
bitfld.long 0x08 14. "TYPE_78,Type for slv_events_in[14]0=level" "0,1"
bitfld.long 0x08 13. "TYPE_77,Type for slv_events_in[13]0=level" "0,1"
bitfld.long 0x08 12. "TYPE_76,Type for slv_events_in[12]0=level" "0,1"
newline
bitfld.long 0x08 11. "TYPE_75,Type for slv_events_in[11]0=level" "0,1"
bitfld.long 0x08 10. "TYPE_74,Type for slv_events_in[10]0=level" "0,1"
bitfld.long 0x08 9. "TYPE_73,Type for slv_events_in[9]0=level" "0,1"
bitfld.long 0x08 8. "TYPE_72,Type for slv_events_in[8]0=level" "0,1"
newline
bitfld.long 0x08 7. "TYPE_71,Type for slv_events_in[7]0=level" "0,1"
bitfld.long 0x08 6. "TYPE_70,Type for slv_events_in[6]0=level" "0,1"
bitfld.long 0x08 5. "TYPE_69,Type for slv_events_in[5]0=level" "0,1"
bitfld.long 0x08 4. "TYPE_68,Type for slv_events_in[4]0=level" "0,1"
newline
bitfld.long 0x08 3. "TYPE_67,Type for slv_events_in[3]0=level" "0,1"
bitfld.long 0x08 2. "TYPE_66,Type for slv_events_in[2]0=level" "0,1"
bitfld.long 0x08 1. "TYPE_65,Type for slv_events_in[1]0=level" "0,1"
bitfld.long 0x08 0. "TYPE_64,Type for slv_events_in[0]0=level" "0,1"
line.long 0x0C "ICSSG_TYPE_REG3,Type Register 3"
bitfld.long 0x0C 31. "TYPE_127,Type for slv_events_in[63]0=level" "0,1"
bitfld.long 0x0C 30. "TYPE_126,Type for slv_events_in[62]0=level" "0,1"
bitfld.long 0x0C 29. "TYPE_125,Type for slv_events_in[61]0=level" "0,1"
bitfld.long 0x0C 28. "TYPE_124,Type for slv_events_in[60]0=level" "0,1"
newline
bitfld.long 0x0C 27. "TYPE_123,Type for slv_events_in[59]0=level" "0,1"
bitfld.long 0x0C 26. "TYPE_122,Type for slv_events_in[58]0=level" "0,1"
bitfld.long 0x0C 25. "TYPE_121,Type for slv_events_in[57]0=level" "0,1"
bitfld.long 0x0C 24. "TYPE_120,Type for slv_events_in[56]0=level" "0,1"
newline
bitfld.long 0x0C 23. "TYPE_119,Type for slv_events_in[55]0=level" "0,1"
bitfld.long 0x0C 22. "TYPE_118,Type for slv_events_in[54]0=level" "0,1"
bitfld.long 0x0C 21. "TYPE_117,Type for slv_events_in[53]0=level" "0,1"
bitfld.long 0x0C 20. "TYPE_116,Type for slv_events_in[52]0=level" "0,1"
newline
bitfld.long 0x0C 19. "TYPE_115,Type for slv_events_in[51]0=level" "0,1"
bitfld.long 0x0C 18. "TYPE_114,Type for slv_events_in[50]0=level" "0,1"
bitfld.long 0x0C 17. "TYPE_113,Type for slv_events_in[49]0=level" "0,1"
bitfld.long 0x0C 16. "TYPE_112,Type for slv_events_in[48]0=level" "0,1"
newline
bitfld.long 0x0C 15. "TYPE_111,Type for slv_events_in[47]0=level" "0,1"
bitfld.long 0x0C 14. "TYPE_110,Type for slv_events_in[46]0=level" "0,1"
bitfld.long 0x0C 13. "TYPE_109,Type for slv_events_in[45]0=level" "0,1"
bitfld.long 0x0C 12. "TYPE_108,Type for slv_events_in[44]0=level" "0,1"
newline
bitfld.long 0x0C 11. "TYPE_107,Type for slv_events_in[43]0=level" "0,1"
bitfld.long 0x0C 10. "TYPE_106,Type for slv_events_in[42]0=level" "0,1"
bitfld.long 0x0C 9. "TYPE_105,Type for slv_events_in[41]0=level" "0,1"
bitfld.long 0x0C 8. "TYPE_104,Type for slv_events_in[40]0=level" "0,1"
newline
bitfld.long 0x0C 7. "TYPE_103,Type for slv_events_in[39]0=level" "0,1"
bitfld.long 0x0C 6. "TYPE_102,Type for slv_events_in[38]0=level" "0,1"
bitfld.long 0x0C 5. "TYPE_101,Type for slv_events_in[37]0=level" "0,1"
bitfld.long 0x0C 4. "TYPE_100,Type for slv_events_in[36]0=level" "0,1"
newline
bitfld.long 0x0C 3. "TYPE_99,Type for slv_events_in[35]0=level" "0,1"
bitfld.long 0x0C 2. "TYPE_98,Type for slv_events_in[34]0=level" "0,1"
bitfld.long 0x0C 1. "TYPE_97,Type for slv_events_in[33]0=level" "0,1"
bitfld.long 0x0C 0. "TYPE_96,Type for slv_events_in[32]0=level" "0,1"
line.long 0x10 "ICSSG_TYPE_REG4,Type Register 4"
bitfld.long 0x10 31. "TYPE_159,Type for slv_events_in[95]0=level" "0,1"
bitfld.long 0x10 30. "TYPE_158,Type for slv_events_in[94]0=level" "0,1"
bitfld.long 0x10 29. "TYPE_157,Type for slv_events_in[93]0=level" "0,1"
bitfld.long 0x10 28. "TYPE_156,Type for slv_events_in[92]0=level" "0,1"
newline
bitfld.long 0x10 27. "TYPE_155,Type for slv_events_in[91]0=level" "0,1"
bitfld.long 0x10 26. "TYPE_154,Type for slv_events_in[90]0=level" "0,1"
bitfld.long 0x10 25. "TYPE_153,Type for slv_events_in[89]0=level" "0,1"
bitfld.long 0x10 24. "TYPE_152,Type for slv_events_in[88]0=level" "0,1"
newline
bitfld.long 0x10 23. "TYPE_151,Type for slv_events_in[87]0=level" "0,1"
bitfld.long 0x10 22. "TYPE_150,Type for slv_events_in[86]0=level" "0,1"
bitfld.long 0x10 21. "TYPE_149,Type for slv_events_in[85]0=level" "0,1"
bitfld.long 0x10 20. "TYPE_148,Type for slv_events_in[84]0=level" "0,1"
newline
bitfld.long 0x10 19. "TYPE_147,Type for slv_events_in[83]0=level" "0,1"
bitfld.long 0x10 18. "TYPE_146,Type for slv_events_in[82]0=level" "0,1"
bitfld.long 0x10 17. "TYPE_145,Type for slv_events_in[81]0=level" "0,1"
bitfld.long 0x10 16. "TYPE_144,Type for slv_events_in[80]0=level" "0,1"
newline
bitfld.long 0x10 15. "TYPE_143,Type for slv_events_in[79]0=level" "0,1"
bitfld.long 0x10 14. "TYPE_142,Type for slv_events_in[78]0=level" "0,1"
bitfld.long 0x10 13. "TYPE_141,Type for slv_events_in[77]0=level" "0,1"
bitfld.long 0x10 12. "TYPE_140,Type for slv_events_in[76]0=level" "0,1"
newline
bitfld.long 0x10 11. "TYPE_139,Type for slv_events_in[75]0=level" "0,1"
bitfld.long 0x10 10. "TYPE_138,Type for slv_events_in[74]0=level" "0,1"
bitfld.long 0x10 9. "TYPE_137,Type for slv_events_in[73]0=level" "0,1"
bitfld.long 0x10 8. "TYPE_136,Type for slv_events_in[72]0=level" "0,1"
newline
bitfld.long 0x10 7. "TYPE_135,Type for slv_events_in[71]0=level" "0,1"
bitfld.long 0x10 6. "TYPE_134,Type for slv_events_in[70]0=level" "0,1"
bitfld.long 0x10 5. "TYPE_133,Type for slv_events_in[69]0=level" "0,1"
bitfld.long 0x10 4. "TYPE_132,Type for slv_events_in[68]0=level" "0,1"
newline
bitfld.long 0x10 3. "TYPE_131,Type for slv_events_in[67]0=level" "0,1"
bitfld.long 0x10 2. "TYPE_130,Type for slv_events_in[66]0=level" "0,1"
bitfld.long 0x10 1. "TYPE_129,Type for slv_events_in[65]0=level" "0,1"
bitfld.long 0x10 0. "TYPE_128,Type for slv_events_in[64]0=level" "0,1"
group.long 0x1100++0x4F
line.long 0x00 "ICSSG_NEST_LEVEL_REG0,Host Int 0 Nesting Level Register"
bitfld.long 0x00 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x04 "ICSSG_NEST_LEVEL_REG1,Host Int 1 Nesting Level Register"
bitfld.long 0x04 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x08 "ICSSG_NEST_LEVEL_REG2,Host Int 2 Nesting Level Register"
bitfld.long 0x08 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0x0C "ICSSG_NEST_LEVEL_REG3,Host Int 3 Nesting Level Register"
bitfld.long 0x0C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "ICSSG_NEST_LEVEL_REG4,Host Int 4 Nesting Level Register"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "ICSSG_NEST_LEVEL_REG5,Host Int 5 Nesting Level Register"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "ICSSG_NEST_LEVEL_REG6,Host Int 6 Nesting Level Register"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "ICSSG_NEST_LEVEL_REG7,Host Int 7 Nesting Level Register"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "ICSSG_NEST_LEVEL_REG8,Host Int 8 Nesting Level Register"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "ICSSG_NEST_LEVEL_REG9,Host Int 9 Nesting Level Register"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
line.long 0x28 "ICSSG_NEST_LEVEL_REG10,Host Int 10 Nesting Level Register"
bitfld.long 0x28 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x28 0.--8. 1. "NEST_HINT_10,Host Int 10 Nesting Level"
line.long 0x2C "ICSSG_NEST_LEVEL_REG11,Host Int 11 Nesting Level Register"
bitfld.long 0x2C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x2C 0.--8. 1. "NEST_HINT_11,Host Int 11 Nesting Level"
line.long 0x30 "ICSSG_NEST_LEVEL_REG12,Host Int 11 Nesting Level Register"
bitfld.long 0x30 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x30 0.--8. 1. "NEST_HINT_12,Host Int 12 Nesting Level"
line.long 0x34 "ICSSG_NEST_LEVEL_REG13,Host Int 11 Nesting Level Register"
bitfld.long 0x34 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x34 0.--8. 1. "NEST_HINT_13,Host Int 13 Nesting Level"
line.long 0x38 "ICSSG_NEST_LEVEL_REG14,Host Int 11 Nesting Level Register"
bitfld.long 0x38 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x38 0.--8. 1. "NEST_HINT_14,Host Int 14 Nesting Level"
line.long 0x3C "ICSSG_NEST_LEVEL_REG15,Host Int 11 Nesting Level Register"
bitfld.long 0x3C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x3C 0.--8. 1. "NEST_HINT_15,Host Int 15 Nesting Level"
line.long 0x40 "ICSSG_NEST_LEVEL_REG16,Host Int 11 Nesting Level Register"
bitfld.long 0x40 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x40 0.--8. 1. "NEST_HINT_16,Host Int 16 Nesting Level"
line.long 0x44 "ICSSG_NEST_LEVEL_REG17,Host Int 11 Nesting Level Register"
bitfld.long 0x44 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x44 0.--8. 1. "NEST_HINT_17,Host Int 17 Nesting Level"
line.long 0x48 "ICSSG_NEST_LEVEL_REG18,Host Int 11 Nesting Level Register"
bitfld.long 0x48 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x48 0.--8. 1. "NEST_HINT_18,Host Int 18 Nesting Level"
line.long 0x4C "ICSSG_NEST_LEVEL_REG19,Host Int 11 Nesting Level Register"
bitfld.long 0x4C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x4C 0.--8. 1. "NEST_HINT_19,Host Int 19 Nesting Level"
group.long 0x1500++0x03
line.long 0x00 "ICSSG_ENABLE_HINT_REG0,Host Int Enable Register 0"
bitfld.long 0x00 19. "ENABLE_HINT_19,Enable for Host Int 19" "0,1"
bitfld.long 0x00 18. "ENABLE_HINT_18,Enable for Host Int 18" "0,1"
bitfld.long 0x00 17. "ENABLE_HINT_17,Enable for Host Int 17" "0,1"
bitfld.long 0x00 16. "ENABLE_HINT_16,Enable for Host Int 16" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_HINT_15,Enable for Host Int 15" "0,1"
bitfld.long 0x00 14. "ENABLE_HINT_14,Enable for Host Int 14" "0,1"
bitfld.long 0x00 13. "ENABLE_HINT_13,Enable for Host Int 13" "0,1"
bitfld.long 0x00 12. "ENABLE_HINT_12,Enable for Host Int 12" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_HINT_11,Enable for Host Int 11" "0,1"
bitfld.long 0x00 10. "ENABLE_HINT_10,Enable for Host Int 10" "0,1"
bitfld.long 0x00 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
bitfld.long 0x00 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x00 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
bitfld.long 0x00 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
bitfld.long 0x00 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x308)++0x03
line.long 0x00 "ICSSG_ENABLE_REG$1,Enable Register 2"
bitfld.long 0x00 31. "ENABLE_95,Enable (set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_94,Enable (set) for slv_events_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_93,Enable (set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "ENABLE_92,Enable (set) for slv_events_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_91,Enable (set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_90,Enable (set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_89,Enable (set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_88,Enable (set) for slv_events_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_87,Enable (set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "ENABLE_86,Enable (set) for slv_events_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_85,Enable (set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_84,Enable (set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_83,Enable (set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_82,Enable (set) for slv_events_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_81,Enable (set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "ENABLE_80,Enable (set) for slv_events_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_79,Enable (set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_78,Enable (set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_77,Enable (set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_76,Enable (set) for slv_events_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_75,Enable (set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "ENABLE_74,Enable (set) for slv_events_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_73,Enable (set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_72,Enable (set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_71,Enable (set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_70,Enable (set) for slv_events_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_69,Enable (set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "ENABLE_68,Enable (set) for slv_events_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_67,Enable (set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_66,Enable (set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_65,Enable (set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_64,Enable (set) for slv_events_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x300)++0x03
line.long 0x00 "ICSSG_ENABLE_REG$1,Enable Register 0"
bitfld.long 0x00 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
repeat.end
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x288)++0x03
line.long 0x00 "ICSSG_ENA_STATUS_REG$1,Enabled Status Register 2"
bitfld.long 0x00 31. "ENA_STATUS_95,Enabled Status for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "ENA_STATUS_94,Enabled Status for slv_events_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENA_STATUS_93,Enabled Status for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "ENA_STATUS_92,Enabled Status for slv_events_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENA_STATUS_91,Enabled Status for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "ENA_STATUS_90,Enabled Status for slv_events_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENA_STATUS_89,Enabled Status for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "ENA_STATUS_88,Enabled Status for slv_events_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENA_STATUS_87,Enabled Status for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "ENA_STATUS_86,Enabled Status for slv_events_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENA_STATUS_85,Enabled Status for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "ENA_STATUS_84,Enabled Status for slv_events_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENA_STATUS_83,Enabled Status for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "ENA_STATUS_82,Enabled Status for slv_events_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENA_STATUS_81,Enabled Status for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "ENA_STATUS_80,Enabled Status for slv_events_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENA_STATUS_79,Enabled Status for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "ENA_STATUS_78,Enabled Status for slv_events_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENA_STATUS_77,Enabled Status for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "ENA_STATUS_76,Enabled Status for slv_events_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENA_STATUS_75,Enabled Status for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "ENA_STATUS_74,Enabled Status for slv_events_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENA_STATUS_73,Enabled Status for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "ENA_STATUS_72,Enabled Status for slv_events_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENA_STATUS_71,Enabled Status for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "ENA_STATUS_70,Enabled Status for slv_events_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENA_STATUS_69,Enabled Status for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "ENA_STATUS_68,Enabled Status for slv_events_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENA_STATUS_67,Enabled Status for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "ENA_STATUS_66,Enabled Status for slv_events_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENA_STATUS_65,Enabled Status for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "ENA_STATUS_64,Enabled Status for slv_events_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x280)++0x03
line.long 0x00 "ICSSG_ENA_STATUS_REG$1,Enabled Status Register 0"
bitfld.long 0x00 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
newline
bitfld.long 0x00 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
bitfld.long 0x00 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
bitfld.long 0x00 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
newline
bitfld.long 0x00 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
newline
bitfld.long 0x00 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
bitfld.long 0x00 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
bitfld.long 0x00 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
newline
bitfld.long 0x00 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
newline
bitfld.long 0x00 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
bitfld.long 0x00 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
repeat.end
repeat 3. (list 2. 3. 4. )(list 0x00 0x04 0x08 )
group.long ($2+0x208)++0x03
line.long 0x00 "ICSSG_RAW_STATUS_REG$1,Raw Status Register 2"
bitfld.long 0x00 31. "RAW_STATUS_95,Raw Status (write 1 to set) for slv_events_in[31]" "0,1"
bitfld.long 0x00 30. "RAW_STATUS_94,Raw Status (write 1 to set) for slv_events_in[30]" "0,1"
newline
bitfld.long 0x00 29. "RAW_STATUS_93,Raw Status (write 1 to set) for slv_events_in[29]" "0,1"
bitfld.long 0x00 28. "RAW_STATUS_92,Raw Status (write 1 to set) for slv_events_in[28]" "0,1"
newline
bitfld.long 0x00 27. "RAW_STATUS_91,Raw Status (write 1 to set) for slv_events_in[27]" "0,1"
bitfld.long 0x00 26. "RAW_STATUS_90,Raw Status (write 1 to set) for slv_events_in[26]" "0,1"
newline
bitfld.long 0x00 25. "RAW_STATUS_89,Raw Status (write 1 to set) for slv_events_in[25]" "0,1"
bitfld.long 0x00 24. "RAW_STATUS_88,Raw Status (write 1 to set) for slv_events_in[24]" "0,1"
newline
bitfld.long 0x00 23. "RAW_STATUS_87,Raw Status (write 1 to set) for slv_events_in[23]" "0,1"
bitfld.long 0x00 22. "RAW_STATUS_86,Raw Status (write 1 to set) for slv_events_in[22]" "0,1"
newline
bitfld.long 0x00 21. "RAW_STATUS_85,Raw Status (write 1 to set) for slv_events_in[21]" "0,1"
bitfld.long 0x00 20. "RAW_STATUS_84,Raw Status (write 1 to set) for slv_events_in[20]" "0,1"
newline
bitfld.long 0x00 19. "RAW_STATUS_83,Raw Status (write 1 to set) for slv_events_in[19]" "0,1"
bitfld.long 0x00 18. "RAW_STATUS_82,Raw Status (write 1 to set) for slv_events_in[18]" "0,1"
newline
bitfld.long 0x00 17. "RAW_STATUS_81,Raw Status (write 1 to set) for slv_events_in[17]" "0,1"
bitfld.long 0x00 16. "RAW_STATUS_80,Raw Status (write 1 to set) for slv_events_in[16]" "0,1"
newline
bitfld.long 0x00 15. "RAW_STATUS_79,Raw Status (write 1 to set) for slv_events_in[15]" "0,1"
bitfld.long 0x00 14. "RAW_STATUS_78,Raw Status (write 1 to set) for slv_events_in[14]" "0,1"
newline
bitfld.long 0x00 13. "RAW_STATUS_77,Raw Status (write 1 to set) for slv_events_in[13]" "0,1"
bitfld.long 0x00 12. "RAW_STATUS_76,Raw Status (write 1 to set) for slv_events_in[12]" "0,1"
newline
bitfld.long 0x00 11. "RAW_STATUS_75,Raw Status (write 1 to set) for slv_events_in[11]" "0,1"
bitfld.long 0x00 10. "RAW_STATUS_74,Raw Status (write 1 to set) for slv_events_in[10]" "0,1"
newline
bitfld.long 0x00 9. "RAW_STATUS_73,Raw Status (write 1 to set) for slv_events_in[9]" "0,1"
bitfld.long 0x00 8. "RAW_STATUS_72,Raw Status (write 1 to set) for slv_events_in[8]" "0,1"
newline
bitfld.long 0x00 7. "RAW_STATUS_71,Raw Status (write 1 to set) for slv_events_in[7]" "0,1"
bitfld.long 0x00 6. "RAW_STATUS_70,Raw Status (write 1 to set) for slv_events_in[6]" "0,1"
newline
bitfld.long 0x00 5. "RAW_STATUS_69,Raw Status (write 1 to set) for slv_events_in[5]" "0,1"
bitfld.long 0x00 4. "RAW_STATUS_68,Raw Status (write 1 to set) for slv_events_in[4]" "0,1"
newline
bitfld.long 0x00 3. "RAW_STATUS_67,Raw Status (write 1 to set) for slv_events_in[3]" "0,1"
bitfld.long 0x00 2. "RAW_STATUS_66,Raw Status (write 1 to set) for slv_events_in[2]" "0,1"
newline
bitfld.long 0x00 1. "RAW_STATUS_65,Raw Status (write 1 to set) for slv_events_in[1]" "0,1"
bitfld.long 0x00 0. "RAW_STATUS_64,Raw Status (write 1 to set) for slv_events_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x200)++0x03
line.long 0x00 "ICSSG_RAW_STATUS_REG$1,Raw Status Register 0"
bitfld.long 0x00 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
newline
bitfld.long 0x00 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
bitfld.long 0x00 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
newline
bitfld.long 0x00 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
newline
bitfld.long 0x00 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
bitfld.long 0x00 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
newline
bitfld.long 0x00 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
newline
bitfld.long 0x00 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
bitfld.long 0x00 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
newline
bitfld.long 0x00 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
newline
bitfld.long 0x00 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
bitfld.long 0x00 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
newline
bitfld.long 0x00 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
newline
bitfld.long 0x00 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
bitfld.long 0x00 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
newline
bitfld.long 0x00 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
repeat.end
tree.end
tree.end
tree "PRU_ICSSG_MDIO"
tree "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO"
base ad:0xB032400
rgroup.long 0x00++0x47
line.long 0x00 "ICSSG_MDIO_VERSION_REG,MDIO Version Register"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module Identification value"
hexmask.long.byte 0x00 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x00 0.--7. 1. "REVMINOR,Minor revision value"
line.long 0x04 "ICSSG_CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
line.long 0x08 "ICSSG_ALIVE_REG,MDIO Alive Register"
line.long 0x0C "ICSSG_LINK_REG,MDIO Link Register"
line.long 0x10 "ICSSG_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "ICSSG_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "ICSSG_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "ICSSG_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "ICSSG_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for ICSSG_USER_ACCESS_REG_1 through ICSSG_USER_ACCESS_REG_0 respectively" "0,1,2,3"
line.long 0x24 "ICSSG_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for ICSSG_USER_ACCESS_REG_1 through ICSSG_USER_ACCESS_REG_0 respectively" "0,1,2,3"
line.long 0x28 "ICSSG_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED[1:0] respectively" "0,1,2,3"
line.long 0x2C "ICSSG_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively" "0,1,2,3"
line.long 0x30 "ICSSG_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x30 0. "MDIO_PIN,MDIO_Pin Value" "0,1"
line.long 0x34 "ICSSG_POLL_REG,MDIO Poll Inter Register"
bitfld.long 0x34 31. "MANUALMODE,Manual Mode" "0,1"
bitfld.long 0x34 30. "STATECHANGEMODE,State Change Mode" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "IPG,Polling Inter Packet Gap Value"
line.long 0x38 "ICSSG_POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "ICSSG_CLAUS45_REG,Claus 45 Register"
line.long 0x40 "ICSSG_USER_ADDR0_REG,MDIO User Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,User Address 0"
line.long 0x44 "ICSSG_USER_ADDR1_REG,MDIO User Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,User Address 1"
group.long 0x80++0x07
line.long 0x00 "ICSSG_USER_ACCESS_REG_j,MDIO User Access j Register"
bitfld.long 0x00 31. "GO,Go" "0,1"
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "ICSSG_USER_PHY_SEL_REG_j,MDIO User PHY Select j Register"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "PRU_ICSSG1_PR1_MDIO_V1P7_MDIO"
base ad:0xB132400
rgroup.long 0x00++0x47
line.long 0x00 "ICSSG_MDIO_VERSION_REG,MDIO Version Register"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module Identification value"
hexmask.long.byte 0x00 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x00 0.--7. 1. "REVMINOR,Minor revision value"
line.long 0x04 "ICSSG_CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1"
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock Divider"
line.long 0x08 "ICSSG_ALIVE_REG,MDIO Alive Register"
line.long 0x0C "ICSSG_LINK_REG,MDIO Link Register"
line.long 0x10 "ICSSG_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "ICSSG_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "ICSSG_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "ICSSG_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "ICSSG_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for ICSSG_USER_ACCESS_REG_1 through ICSSG_USER_ACCESS_REG_0 respectively" "0,1,2,3"
line.long 0x24 "ICSSG_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for ICSSG_USER_ACCESS_REG_1 through ICSSG_USER_ACCESS_REG_0 respectively" "0,1,2,3"
line.long 0x28 "ICSSG_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED[1:0] respectively" "0,1,2,3"
line.long 0x2C "ICSSG_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively" "0,1,2,3"
line.long 0x30 "ICSSG_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x30 0. "MDIO_PIN,MDIO_Pin Value" "0,1"
line.long 0x34 "ICSSG_POLL_REG,MDIO Poll Inter Register"
bitfld.long 0x34 31. "MANUALMODE,Manual Mode" "0,1"
bitfld.long 0x34 30. "STATECHANGEMODE,State Change Mode" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "IPG,Polling Inter Packet Gap Value"
line.long 0x38 "ICSSG_POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "ICSSG_CLAUS45_REG,Claus 45 Register"
line.long 0x40 "ICSSG_USER_ADDR0_REG,MDIO User Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,User Address 0"
line.long 0x44 "ICSSG_USER_ADDR1_REG,MDIO User Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,User Address 1"
group.long 0x80++0x07
line.long 0x00 "ICSSG_USER_ACCESS_REG_j,MDIO User Access j Register"
bitfld.long 0x00 31. "GO,Go" "0,1"
bitfld.long 0x00 30. "WRITE,Write enable" "0,1"
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "ICSSG_USER_PHY_SEL_REG_j,MDIO User PHY Select j Register"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "PRU_ICSSG_MII_G_RT"
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base ad:0xB033000
group.long 0x00++0x2B
line.long 0x00 "ICSSG_ICSS_G_CFG,ICSS_G SGMII mode is supported only for PRU_ICSSG1 instance"
bitfld.long 0x00 16. "SGMII_MODE,SGMII MODE" "Fiber MODE,SGMII MODE"
bitfld.long 0x00 11. "TX_PRU_EN,Enable TX_PRU to gain control of MII TXL2" "0,1"
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bitfld.long 0x00 10. "RX_SFD_TX_SOF_EN,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
bitfld.long 0x00 9. "RTU_PRU_PSI_SHARE_EN,Enable the sharing of xfr2psi attached to PRU for PRU RTU AND HW FIFO" "0,1"
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bitfld.long 0x00 8. "IEP1_TX_EN,Enable IEP1 for TX Enable" "Use IEP0 CMP3_4,Use IEP1 CMP3_4"
bitfld.long 0x00 5.--6. "MII1_MODE,MII1 MODE" "MII,RGMII,SGMII,?..."
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bitfld.long 0x00 3.--4. "MII0_MODE,MII0 MODE" "MII,RGMII,SGMII,?..."
bitfld.long 0x00 2. "RX_L2_G_EN,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L2" "Disabled,Enabled"
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bitfld.long 0x00 1. "TX_L2_EN,Enable the TX L2 Fifo" "Disabled,Enabled"
bitfld.long 0x00 0. "TX_L1_EN,Enable the TX L1 Fifo" "Disabled,Enabled"
line.long 0x04 "ICSSG_RGMII_CFG,RGMII"
bitfld.long 0x04 22. "RGMII1_FULLDUPLEX_IN,RGMII Fullduplex overide" "half,full"
bitfld.long 0x04 21. "RGMII1_GIG_IN,RGMII GigBit Enable" "100 Mbs,1000 Mbs"
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bitfld.long 0x04 20. "RGMII1_INBAND,RGMII In BandEnable or Force" "InBAND is Disabled,InBAND Enable"
bitfld.long 0x04 18. "RGMII0_FULLDUPLEX_IN,RGMII Fullduplex overide" "half,full"
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bitfld.long 0x04 17. "RGMII0_GIG_IN,RGMII GigBit Enable" "100 Mbs,1000 Mbs"
bitfld.long 0x04 16. "RGMII0_INBAND,RGMII In BandEnable or Force" "InBAND is Disabled,InBAND Enable"
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bitfld.long 0x04 9. "RGMII_EEE_PHY_ONLY,RGMII Phy Only Low Power" "disable,enable"
bitfld.long 0x04 8. "RGMII_EEE_EN,RGMII Energy Efficient Enable" "disable,enable"
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bitfld.long 0x04 7. "RGMII1_FULLDUPLEX,RGMII Fullduplex" "half duplex,full duplex"
bitfld.long 0x04 5.--6. "RGMII1_SPEED,RGMII Speed" "10Mpbs,100Mpbs,1000 Mpbs,?..."
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bitfld.long 0x04 4. "RGMII1_LINK,RGMII Link Status" "link is down,link is up"
bitfld.long 0x04 3. "RGMII0_FULLDUPLEX,RGMII Fullduplex" "half duplex,full duplex"
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bitfld.long 0x04 1.--2. "RGMII0_SPEED,RGMII Speed" "10Mpbs,100Mpbs,1000 Mpbs,?..."
bitfld.long 0x04 0. "RGMII0_LINK,RGMII Link Status" "link is down,link is up"
line.long 0x08 "ICSSG_MAC_PRU0_0,PRU0 MAC (DA3:DA0)"
line.long 0x0C "ICSSG_MAC_PRU0_1,PRU0 MAC (DA5:DA4)"
hexmask.long.word 0x0C 0.--15. 1. "MAC_PRU0_1,MAC PRU0 DA5:DA4 Used for SAV and DA match"
line.long 0x10 "ICSSG_MAC_PRU1_0,PRU1 MAC (DA3:DA0)"
line.long 0x14 "ICSSG_MAC_PRU1_1,PRU1 MAC (DA5:DA4)"
hexmask.long.word 0x14 0.--15. 1. "MAC_PRU1_1,MAC PRU1 DA5:DA4 Used for SAV and DA match"
line.long 0x18 "ICSSG_MAC_INTERFACE_0,MAC Host Interface (DA3:DA0)"
line.long 0x1C "ICSSG_MAC_INTERFACE_1,MAC Host Interface (DA5:DA4)"
hexmask.long.word 0x1C 0.--15. 1. "MAC_INF_1,MAC Host interface DA"
line.long 0x20 "ICSSG_PREEMPT_CFG,Preempt Configuration Register"
hexmask.long.byte 0x20 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x20 16.--23. 1. "SMD_V,Verification frame TAG"
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hexmask.long.byte 0x20 8.--15. 1. "EXP_SMD,None preemptable frame start or express frame"
line.long 0x24 "ICSSG_SMDT1S_CFG,SMD Type1S Preemptable Frame Start Configuration"
hexmask.long.byte 0x24 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x24 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
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hexmask.long.byte 0x24 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
hexmask.long.byte 0x24 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x28 "ICSSG_SMDT1C_CFG,SMD Type1C None Initial Frag Configuration"
hexmask.long.byte 0x28 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x28 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
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hexmask.long.byte 0x28 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
hexmask.long.byte 0x28 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
group.long 0x34++0x03
line.long 0x00 "ICSSG_FRAG_CNT_CFG,Frag Count Configuration"
hexmask.long.byte 0x00 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
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hexmask.long.byte 0x00 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
group.long 0x60++0x07
line.long 0x00 "ICSSG_FDB_GEN_CFG1,FDB Configuration1"
hexmask.long.tbyte 0x00 8.--25. 1. "SMEM_VLAN_OFFSET,SMEM VLAN FID table base address"
bitfld.long 0x00 3.--6. "FDB_HASH_SIZE,FDB hash size 0:64 1:128 2:256 3:512 4:1024 5:2048" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. "FDB_BUCKET_SIZE,FDB buket size 0:1 1:2 2:4 3:8" "0,1,2,3"
line.long 0x04 "ICSSG_FDB_GEN_CFG2,FDB Configuration2"
bitfld.long 0x04 9.--12. "FDB_GEN_MODE_BYTE_EN,FDB General Mode Byte compare size" "1 Byte,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16 Bytes"
bitfld.long 0x04 8. "FDB_GEN_MODE_EN_BK1,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
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bitfld.long 0x04 7. "FDB_GEN_MODE_EN_BK0,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x04 6. "FDB_VLAN_EN,FDB Global VLAN Enable" "0,1"
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bitfld.long 0x04 5. "FDB_HSR_EN,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x04 2. "FDB_HOST_EN,FDB HOST Enable" "0,1"
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bitfld.long 0x04 1. "FDB_PRU1_EN,FDB PRU1 Enable" "0,1"
bitfld.long 0x04 0. "FDB_PRU0_EN,FDB PRU0 Enable" "0,1"
group.long 0x6C++0x2B
line.long 0x00 "ICSSG_FDB_DF_VLAN,FDB Default PRU VLAN"
hexmask.long.word 0x00 16.--27. 1. "FDB_PRU1_DF_VLAN,FDB Default VLAN for PRU1"
hexmask.long.word 0x00 0.--11. 1. "FDB_PRU0_DF_VLAN,FDB Default VLAN for PRU0"
line.long 0x04 "ICSSG_FDB_HOST_DA0,FDB HOST DA3:0 Configuration"
line.long 0x08 "ICSSG_FDB_HOST_DA1,FDB HOST DA5:4 Configuration"
hexmask.long.word 0x08 0.--15. 1. "FDB_HOST_DA1,FDB HOST DA 5:4"
line.long 0x0C "ICSSG_FDB_HOST_SA0,FDB HOST SA3:0 Configuration"
line.long 0x10 "ICSSG_FDB_HOST_VLAN_SA1,FDB HOST VLAN SA5:4 Configuration"
hexmask.long.word 0x10 16.--31. 1. "FDB_HOST_VLAN_HSR,FDB HOST VLAN [11:0] OR HSR [15:0]"
hexmask.long.word 0x10 0.--15. 1. "FDB_HOST_SA1,FDB HOST SA 5:4"
line.long 0x14 "ICSSG_FT1_START_LEN_PRU0,Filter1 Start and Length (PRU0)"
bitfld.long 0x14 16.--19. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--14. 1. "FT1_START,Byte count start for Filter1"
line.long 0x18 "ICSSG_FT1_CFG_PRU0,Filter1 Configuration (PRU0)"
bitfld.long 0x18 14.--15. "FT1_7CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 12.--13. "FT1_6CFG," "?,Equal,Greater Than,Less Than"
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bitfld.long 0x18 10.--11. "FT1_5CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 8.--9. "FT1_4CFG," "?,Equal,Greater Than,Less Than"
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bitfld.long 0x18 6.--7. "FT1_3CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 4.--5. "FT1_2CFG," "?,Equal,Greater Than,Less Than"
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bitfld.long 0x18 2.--3. "FT1_1CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 0.--1. "FT1_0CFG," "?,Equal,Greater Than,Less Than"
line.long 0x1C "ICSSG_FT1_k_DA0_PRU0,Filter1<k> DA0 (Pru0)"
line.long 0x20 "ICSSG_FT1_k_DA1_PRU0,Filter1<k> DA1 (PRU0)"
hexmask.long.word 0x20 0.--15. 1. "FT1_k_DA1,Filter1 DA6:DA5"
line.long 0x24 "ICSSG_FT1_k_DA_MASK0_PRU0,Filter1<k> DA0 Mask (PRU0)"
line.long 0x28 "ICSSG_FT1_k_DA_MASK1_PRU0,Filter1<k> DA1 Mask (PRU0)"
hexmask.long.word 0x28 0.--15. 1. "FT1_k_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x108++0x1F
line.long 0x00 "ICSSG_FT3_m_START_PRU0,Filter3 Byte Count Start"
hexmask.long.word 0x00 0.--14. 1. "FT3_START,Byte count start for Filter3"
line.long 0x04 "ICSSG_FT3_m_START_AUTO_PRU0,Filter3 Byte Count Start for Auto Skip mode"
hexmask.long.word 0x04 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
line.long 0x08 "ICSSG_FT3_m_START_LEN_PRU0,Filter3 Start Offset for PRU0"
bitfld.long 0x08 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x0C "ICSSG_FT3_m_JMP_OFFSET_PRU0,Filter3 Jump Offset for PRU0"
hexmask.long.word 0x0C 16.--30. 1. "FT3_m_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x0C 0.--14. 1. "FT3_m_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x10 "ICSSG_FT3_m_LEN_PRU0,Filter3 Length Offset for PRU0"
bitfld.long 0x10 24. "FT3_m_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
bitfld.long 0x10 16.--19. "FT3_m_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x10 0.--8. 1. "FT3_m_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0x14 "ICSSG_FT3_m_CFG_PRU0,Filter3 Configuration for PRU0"
hexmask.long.word 0x14 16.--31. 1. "FT3_m_TRIG_OR_EN,Trigger ft3 select for auto skip enable if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x14 2. "FT3_m_VLAN_SKIP_EN," "0,1"
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bitfld.long 0x14 0.--1. "FT3_mCFG," "?,EQ,GT,LT"
line.long 0x18 "ICSSG_FT3_m_T_PRU0,Filter3 Type for PRU0"
line.long 0x1C "ICSSG_FT3_m_T_MASK_PRU0,Filter3 Mask for PRU0"
group.long 0x308++0x0F
line.long 0x00 "ICSSG_FT3_m_P0_PRU0,Filter3 PRU0 (P4:P1)"
line.long 0x04 "ICSSG_FT3_m_P1_PRU0,Filter3 PRU0 (P8:P5)"
line.long 0x08 "ICSSG_FT3_n_P_MASK0_PRU0,Filter3 Mask0 (MP4:MP1)"
line.long 0x0C "ICSSG_FT3_n_P_MASK1_PRU0,Filter3 Mask1 (MP8:MP5)"
group.long 0x408++0x0B
line.long 0x00 "ICSSG_FT_RX_PTR_PRU0,RX Current Filter Byte Count (PRU0)"
line.long 0x04 "ICSSG_RX_CLASSm_AND_EN_PRU0,RX Class<m> AND Enable Register"
line.long 0x08 "ICSSG_RX_CLASSm_OR_EN_PRU0,RX Class<m> OR Enable Register"
group.long 0x48C++0x0B
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU0,RX Class Configuration 1 Register"
bitfld.long 0x00 30.--31. "RX_CLASS15_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 28.--29. "RX_CLASS14_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 26.--27. "RX_CLASS13_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 24.--25. "RX_CLASS12_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 22.--23. "RX_CLASS11_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 20.--21. "RX_CLASS10_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 18.--19. "RX_CLASS9_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 16.--17. "RX_CLASS8_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 14.--15. "RX_CLASS7_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 12.--13. "RX_CLASS6_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 10.--11. "RX_CLASS5_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 8.--9. "RX_CLASS4_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 6.--7. "RX_CLASS3_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 4.--5. "RX_CLASS2_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 2.--3. "RX_CLASS1_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 0.--1. "RX_CLASS0_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
line.long 0x04 "ICSSG_RX_CLASS_CFG2_PRU0,RX Class Configuration 2 Register"
hexmask.long.word 0x04 16.--31. 1. "RX_CLASS_OR_NV,RX class invert OR not invert enable"
hexmask.long.word 0x04 0.--15. 1. "RX_CLASS_AND_NV,RX class invert AND not invert enable"
line.long 0x08 "ICSSG_RX_CLASS_GATESm_PRU0,RX Class Gate<m> Configuration PRU0 Register"
bitfld.long 0x08 8. "RX_RED_PHASE_ENm,red phase neable" "disable,enable"
bitfld.long 0x08 6. "RX_ALLOW_MASKm,allow mask" "unmask,mask"
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bitfld.long 0x08 5. "RX_CLASS_RAW_MASKm,class raw mask" "unmask,mask"
bitfld.long 0x08 4. "RX_PHASE_MASKm,time phase mask" "unmask,mask"
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bitfld.long 0x08 0.--2. "RX_RATE_GATE_SELm,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D4++0x13
line.long 0x00 "ICSSG_RX_GREEN_PRU0,RX Green Status PRU0"
rbitfld.long 0x00 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "RX_GREEN_CMP_SEL,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ICSSG_SA_HASH_PRU0,SA Hash Seed PRU0"
hexmask.long.word 0x04 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x08 "ICSSG_CONN_HASH_PRU0,Connection Hash Seed PRU0"
hexmask.long.word 0x08 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x0C "ICSSG_CONN_HASH_START_PRU0,Connection Hash Start PRU0"
hexmask.long.word 0x0C 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x10 "ICSSG_RX_RATE_CFGn_PRU0,RX Rate Configuration<n> Register"
group.long 0x504++0x0F
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU0,RX Rate Source Select0"
bitfld.long 0x00 24.--29. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_RX_RATE_SRC_SEL1_PRU0,RX Rate Source Select1"
bitfld.long 0x04 24.--29. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 16.--21. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 8.--13. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--5. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "ICSSG_TX_RATE_CFG1_n_PRU0,TX Rate Configuration1 Registe"
line.long 0x0C "ICSSG_TX_RATE_CFG2_n_PRU0,TX Rate Configuration2 Register"
rbitfld.long 0x0C 17. "TX_RATE_ALLOWn,TX Rate Pkt Enable" "0,1"
bitfld.long 0x0C 16. "TX_RATE_ENn,TX Rate Pkt Enable" "0,1"
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hexmask.long.word 0x0C 0.--15. 1. "TX_RATE_LENn,TX Rate Pkt Length"
group.long 0x54C++0x2F
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU0,RX Good Frame Count (PRU0)"
line.long 0x04 "ICSSG_RX_STAT_BC_PRU0,RX BC Frame Count (PRU0)"
hexmask.long.word 0x04 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type Wrt subtracts"
line.long 0x08 "ICSSG_RX_STAT_MC_PRU0,RX MC Frame Count (PRU0)"
hexmask.long.word 0x08 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type Wrt subtracts"
line.long 0x0C "ICSSG_RX_STAT_CRC_ERR_PRU0,RX CRC Error Frame Count (PRU0)"
hexmask.long.word 0x0C 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err Wrt subtracts"
line.long 0x10 "ICSSG_RX_STAT_MII_ERR_PRU0,RX MII Error Frame Count (PRU0)"
hexmask.long.word 0x10 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err Wrt subtracts"
line.long 0x14 "ICSSG_RX_STAT_ODD_ERR_PRU0,RX Odd Nibble Frame Count (PRU0)"
hexmask.long.word 0x14 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii Wrt subtracts"
line.long 0x18 "ICSSG_RX_STAT_MAX_SIZE_PRU0,RX Max Size Frame Count (PRU0)"
hexmask.long.word 0x18 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x1C "ICSSG_RX_STAT_MAX_ERR_PRU0,RX Max Size Error Frame Count (PRU0)"
hexmask.long.word 0x1C 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit Wrt subtracts"
line.long 0x20 "ICSSG_RX_STAT_MIN_SIZE_PRU0,RX Min Size Frame Count (PRU0)"
hexmask.long.word 0x20 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x24 "ICSSG_RX_STAT_MIN_ERR_PRU0,RX Min Size Error Frame Count (PRU0)"
hexmask.long.word 0x24 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit Wrt subtracts"
line.long 0x28 "ICSSG_RX_STAT_OVERRUN_ERR_PRU0,RX Overrun Frame Count (PRU0)"
hexmask.long.word 0x28 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count"
line.long 0x2C "ICSSG_RX_STAT_CLASSm_HIT_PRU0,RX Class<m> Hit"
group.long 0x5B8++0xAB
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU0,RX SMD Frag Error Count PRU0"
hexmask.long.byte 0x00 24.--31. 1. "RX_STAT_SMD_ERR_PRU0,RX SMDS Error Count Inc when first none 0x55 does not match any valid SMD Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "RX_STAT_FRAG_ERR_PRU0,RX Frag_Cnt Seq Error Count Wrt subtracts"
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hexmask.long.byte 0x00 8.--15. 1. "RX_STAT_SMDC_ERR_PRU0,RX SMDCx Seq Error Count Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "RX_STAT_SMDS_ERR_PRU0,RX SMDSx Seq Error Count Wrt subtracts"
line.long 0x04 "ICSSG_RX_STAT_BKT1_SIZE_PRU0,RX Bucket1 Size Configuration (PRU0)"
hexmask.long.word 0x04 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x08 "ICSSG_RX_STAT_BKT2_SIZE_PRU0,RX Bucket2 Size Configuration (PRU0)"
hexmask.long.word 0x08 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x0C "ICSSG_RX_STAT_BKT3_SIZE_PRU0,RX Bucket3 Size Configuration (PRU0)"
hexmask.long.word 0x0C 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x10 "ICSSG_RX_STAT_BKT4_SIZE_PRU0,RX Bucket4 Size Configuration (PRU0)"
hexmask.long.word 0x10 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x14 "ICSSG_RX_STAT_64_PRU0,RX 64B Sized Frame Count (PRU0)"
hexmask.long.word 0x14 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x18 "ICSSG_RX_STAT_BKT1_PRU0,RX Bucket1 Sized Frame Count (PRU0)"
hexmask.long.word 0x18 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x1C "ICSSG_RX_STAT_BKT2_PRU0,RX Bucket2 Sized Frame Count (PRU0)"
hexmask.long.word 0x1C 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x20 "ICSSG_RX_STAT_BKT3_PRU0,RX Bucket3 Sized Frame Count (PRU0)"
hexmask.long.word 0x20 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x24 "ICSSG_RX_STAT_BKT4_PRU0,RX Bucket4 Sized Frame Count (PRU0)"
hexmask.long.word 0x24 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x28 "ICSSG_RX_STAT_BKT5_PRU0,RX Bucket5 Sized Frame Count (PRU0)"
hexmask.long.word 0x28 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2C "ICSSG_RX_STAT_TOTAL_BYTES_PRU0,RX Total Byte Count (PRU0)"
line.long 0x30 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU0,RX TX Total Byte Count (PRU0)"
line.long 0x34 "ICSSG_TX_STAT_GOOD_PORT0,TX Good Frame Count Port0"
line.long 0x38 "ICSSG_TX_STAT_BC_PORT0,TX BC Frame Count Port0"
hexmask.long.word 0x38 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x3C "ICSSG_TX_STAT_MC_PORT0,TX MC Frame Count Port0"
hexmask.long.word 0x3C 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count"
line.long 0x40 "ICSSG_TX_STAT_ODD_ERR_PORT0,TX Odd Nibble Frame Count Port0"
hexmask.long.word 0x40 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x44 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT0,TX Under Flow Error Count Port0"
hexmask.long.word 0x44 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x48 "ICSSG_TX_STAT_MAX_SIZE_PORT0,TX Max Size Frame Port0"
hexmask.long.word 0x48 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x4C "ICSSG_TX_STAT_MAX_ERR_PORT0,TX Max Size Error Frame Count Port0"
hexmask.long.word 0x4C 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x50 "ICSSG_TX_STAT_MIN_SIZE_PORT0,TX Min Size Frame Port0"
hexmask.long.word 0x50 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x54 "ICSSG_TX_STAT_MIN_ERR_PORT0,TX Min Size ErrorFrame Count Port0"
hexmask.long.word 0x54 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x58 "ICSSG_TX_STAT_BKT1_SIZE_PORT0,TX Bucket1 Size Configuration Port0"
hexmask.long.word 0x58 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x5C "ICSSG_TX_STAT_BKT2_SIZE_PORT0,TX Bucket2 Size Configuration Port0"
hexmask.long.word 0x5C 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x60 "ICSSG_TX_STAT_BKT3_SIZE_PORT0,TX Bucket3 Size Configuration Port0"
hexmask.long.word 0x60 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x64 "ICSSG_TX_STAT_BKT4_SIZE_PORT0,TX Bucket4 Size Configuration Port0"
hexmask.long.word 0x64 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x68 "ICSSG_TX_STAT_64_PORT0,TX 64B Sized Frame Count Port0"
hexmask.long.word 0x68 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count"
line.long 0x6C "ICSSG_TX_STAT_BKT1_PORT0,TX Bucket1 Sized Frame Count Port0"
hexmask.long.word 0x6C 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x70 "ICSSG_TX_STAT_BKT2_PORT0,TX Bucket2 Sized Frame Count Port0"
hexmask.long.word 0x70 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x74 "ICSSG_TX_STAT_BKT3_PORT0,TX Bucket3 Sized Frame Count Port0"
hexmask.long.word 0x74 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x78 "ICSSG_TX_STAT_BKT4_PORT0,TX Bucket4 Sized Frame Count Port0"
hexmask.long.word 0x78 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x7C "ICSSG_TX_STAT_BKT5_PORT0,TX Bucket5 Sized Frame Count Port0"
hexmask.long.word 0x7C 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x80 "ICSSG_TX_STAT_TOTAL_BYTES_PORT0,TX Total Byte Count Port0"
line.long 0x84 "ICSSG_TX_HSR_TAG_PORT0,TX HSR TAG Port0"
line.long 0x88 "ICSSG_TX_HSR_SEQ_PORT0,TX HSR Seq Port0"
hexmask.long.word 0x88 0.--15. 1. "TX_HSR_SEQ,HSR Seq count"
line.long 0x8C "ICSSG_TX_VLAN_TYPE_TAG_PORT0,TX VLAN Type TAG Port0"
hexmask.long.word 0x8C 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag match to enable VLAN removal"
line.long 0x90 "ICSSG_TX_VLAN_INS_TAG_PORT0,TX VLAN Insertion TAG Port0"
line.long 0x94 "ICSSG_FT1_START_LEN_PRU1,Filter1 Start and Length (PRU1)"
bitfld.long 0x94 16.--19. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x94 0.--14. 1. "FT1_START,Byte count start for Filter1"
line.long 0x98 "ICSSG_FT1_CFG_PRU1,Filter1 Configuration (PRU1)"
bitfld.long 0x98 14.--15. "FT1_7CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 12.--13. "FT1_6CFG," "?,Equal,Greater Than,Less Than"
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bitfld.long 0x98 10.--11. "FT1_5CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 8.--9. "FT1_4CFG," "?,Equal,Greater Than,Less Than"
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bitfld.long 0x98 6.--7. "FT1_3CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 4.--5. "FT1_2CFG," "?,Equal,Greater Than,Less Than"
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bitfld.long 0x98 2.--3. "FT1_1CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 0.--1. "FT1_0CFG," "?,Equal,Greater Than,Less Than"
line.long 0x9C "ICSSG_FT1_k_DA0_PRU1,Filter1<k> DA0 (PRU1)"
line.long 0xA0 "ICSSG_FT1_k_DA1_PRU1,Filter1<k> DA1 (PRU1)"
hexmask.long.word 0xA0 0.--15. 1. "FT1_k_DA1,Filter1 DA6:DA5"
line.long 0xA4 "ICSSG_FT1_k_DA_MASK0_PRU1,Filter1<k> DA0 Mask (PRU1)"
line.long 0xA8 "ICSSG_FT1_k_DA_MASK1_PRU1,Filter1<k> DA1 Mask (PRU1)"
hexmask.long.word 0xA8 0.--15. 1. "FT1_k_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6D4++0x1F
line.long 0x00 "ICSSG_FT3_m_START_PRU1,Filter3<m> Start (PRU1)"
hexmask.long.word 0x00 0.--14. 1. "FT3_START,Byte count start for Filter3"
line.long 0x04 "ICSSG_FT3_m_START_AUTO_PRU1,Filter3<m> Start Auto (PRU1)"
hexmask.long.word 0x04 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
line.long 0x08 "ICSSG_FT3_m_START_LEN_PRU1,Filter3<m> Start offset (PRU1)"
bitfld.long 0x08 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x0C "ICSSG_FT3_m_JMP_OFFSET_PRU1,Filter3<m> Jmp offset (PRU1)"
hexmask.long.word 0x0C 16.--30. 1. "FT3_m_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x0C 0.--14. 1. "FT3_m_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x10 "ICSSG_FT3_m_LEN_PRU1,Filter3 Length Offset for (PRU1)"
bitfld.long 0x10 24. "FT3_m_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
bitfld.long 0x10 16.--19. "FT3_m_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x10 0.--8. 1. "FT3_m_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0x14 "ICSSG_FT3_m_CFG_PRU1,Filter3<m> Configuration (PRU1)"
hexmask.long.word 0x14 16.--31. 1. "FT3_m_TRIG_OR_EN,Trigger ft3 select for auto skip enable if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x14 2. "FT3_m_VLAN_SKIP_EN," "0,1"
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bitfld.long 0x14 0.--1. "FT3_mCFG," "?,EQ,GT,LT"
line.long 0x18 "ICSSG_FT3_m_T_PRU1,Filter3<m> T (PRU1)"
line.long 0x1C "ICSSG_FT3_m_T_MASK_PRU1,Filter3<m> T Mask (PRU1)"
group.long 0x8D4++0x0F
line.long 0x00 "ICSSG_FT3_m_P0_PRU1,Filter3<m> P0 (PRU1)"
line.long 0x04 "ICSSG_FT3_m_P1_PRU1,Filter3<m> P1 (PRU1)"
line.long 0x08 "ICSSG_FT3_m_P_MASK0_PRU1,Filter3<m> P Mask0 (PRU1)"
line.long 0x0C "ICSSG_FT3_m_P_MASK1_PRU1,Filter3<m> P Mask1 (PRU1)"
group.long 0x9D4++0x0B
line.long 0x00 "ICSSG_FT_RX_PTR_PRU1,Filter Byte Count (PRU1)"
line.long 0x04 "ICSSG_RX_CLASSm_AND_EN_PRU1,RX Class<m> AND Enable (PRU1)"
line.long 0x08 "ICSSG_RX_CLASSm_OR_EN_PRU1,RX Class<m> OR Enable (PRU1)"
group.long 0xA58++0x0B
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU1,RX Class Configuration 1 Register"
bitfld.long 0x00 30.--31. "RX_CLASS15_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 28.--29. "RX_CLASS14_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 26.--27. "RX_CLASS13_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 24.--25. "RX_CLASS12_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 22.--23. "RX_CLASS11_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 20.--21. "RX_CLASS10_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 18.--19. "RX_CLASS9_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 16.--17. "RX_CLASS8_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 14.--15. "RX_CLASS7_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 12.--13. "RX_CLASS6_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 10.--11. "RX_CLASS5_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 8.--9. "RX_CLASS4_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 6.--7. "RX_CLASS3_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 4.--5. "RX_CLASS2_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 2.--3. "RX_CLASS1_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 0.--1. "RX_CLASS0_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
line.long 0x04 "ICSSG_RX_CLASS_CFG2_PRU1,RX Class Configuration 2 Register"
hexmask.long.word 0x04 16.--31. 1. "RX_CLASS_OR_NV,RX class or nv enable"
hexmask.long.word 0x04 0.--15. 1. "RX_CLASS_AND_NV,RX class and nv enable"
line.long 0x08 "ICSSG_RX_CLASS_GATESm_PRU1,RX Class Gate Configuration PRU1 Register"
bitfld.long 0x08 8. "RX_RED_PHASE_ENm,red phase neable" "disable,enable"
bitfld.long 0x08 6. "RX_ALLOW_MASKm,allow mask" "unmask,mask"
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bitfld.long 0x08 5. "RX_CLASS_RAW_MASKm,class raw mask" "unmask,mask"
bitfld.long 0x08 4. "RX_PHASE_MASKm,time phase mask" "unmask,mask"
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bitfld.long 0x08 0.--2. "RX_RATE_GATE_SELm,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xAA0++0x13
line.long 0x00 "ICSSG_RX_GREEN_PRU1,RX Green Status PRU1"
rbitfld.long 0x00 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "RX_GREEN_CMP_SEL,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ICSSG_SA_HASH_PRU1,SA Hash Seed PRU1"
hexmask.long.word 0x04 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x08 "ICSSG_CONN_HASH_PRU1,Connection Hash Seed PRU1"
hexmask.long.word 0x08 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x0C "ICSSG_CONN_HASH_START_PRU1,Connection Hash Start PRU1"
hexmask.long.word 0x0C 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x10 "ICSSG_RX_RATE_CFGn_PRU1,RX Rate Configuration Register"
group.long 0xAD0++0x0F
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU1,RX Rate Source Select0"
bitfld.long 0x00 24.--29. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_RX_RATE_SRC_SEL1_PRU1,RX Rate Source Select1"
bitfld.long 0x04 24.--29. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 16.--21. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 8.--13. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--5. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "ICSSG_TX_RATE_CFG1_n_PRU1,TX Rate Configuration 1 Register"
line.long 0x0C "ICSSG_TX_RATE_CFG2_n_PRU1,TX Rate Configuration 2 Register"
rbitfld.long 0x0C 17. "TX_RATE_ALLOWn,TX Rate Pkt Enable" "0,1"
bitfld.long 0x0C 16. "TX_RATE_ENn,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x0C 0.--15. 1. "TX_RATE_LENn,TX Rate Pkt Length"
group.long 0xB18++0x2F
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU1,RX Good Frame Count (PRU1)"
line.long 0x04 "ICSSG_RX_STAT_BC_PRU1,RX BC Frame Count (PRU1)"
hexmask.long.word 0x04 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type Wrt subtracts"
line.long 0x08 "ICSSG_RX_STAT_MC_PRU1,RX MC Frame Count (PRU1)"
hexmask.long.word 0x08 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type Wrt subtracts"
line.long 0x0C "ICSSG_RX_STAT_CRC_ERR_PRU1,RX CRC Error Frame Count (PRU1)"
hexmask.long.word 0x0C 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err Wrt subtracts"
line.long 0x10 "ICSSG_RX_STAT_MII_ERR_PRU1,RX MII Error Frame Count (PRU1)"
hexmask.long.word 0x10 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err Wrt subtracts"
line.long 0x14 "ICSSG_RX_STAT_ODD_ERR_PRU1,RX Odd Nibble Frame Count (PRU1)"
hexmask.long.word 0x14 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii Wrt subtracts"
line.long 0x18 "ICSSG_RX_STAT_MAX_SIZE_PRU1,RX Max Size Frame (PRU1)"
hexmask.long.word 0x18 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x1C "ICSSG_RX_STAT_MAX_ERR_PRU1,RX Max Size Error Frame Count (PRU1)"
hexmask.long.word 0x1C 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit Wrt subtracts"
line.long 0x20 "ICSSG_RX_STAT_MIN_SIZE_PRU1,RX Min Size Frame (PRU1)"
hexmask.long.word 0x20 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x24 "ICSSG_RX_STAT_MIN_ERR_PRU1,RX Min Size Error Frame Count (PRU1)"
hexmask.long.word 0x24 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit Wrt subtracts"
line.long 0x28 "ICSSG_RX_STAT_OVERRUN_ERR_PRU1,RX Overrun Frame Count (PRU1)"
hexmask.long.word 0x28 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event Wrt subtracts"
line.long 0x2C "ICSSG_RX_STAT_CLASSm_HIT_PRU1,RX Class<m>"
group.long 0xB84++0x93
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU1,RX SMD Frag Error Count (PRU1)"
hexmask.long.byte 0x00 24.--31. 1. "RX_STAT_SMD_ERR_PRU1,RX SMDS Error Count Inc when first none 0x55 does not match any valid SMD Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "RX_STAT_FRAG_ERR_PRU1,RX Frag_Cnt Seq Error Count Wrt subtracts"
newline
hexmask.long.byte 0x00 8.--15. 1. "RX_STAT_SMDC_ERR_PRU1,RX SMDCx Seq Error Count Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "RX_STAT_SMDS_ERR_PRU1,RX SMDSx Seq Error Count Wrt subtracts"
line.long 0x04 "ICSSG_RX_STAT_BKT1_SIZE_PRU1,RX Bucket1 Size Configuration (PRU1)"
hexmask.long.word 0x04 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x08 "ICSSG_RX_STAT_BKT2_SIZE_PRU1,RX Bucket2 Size Configuration (PRU1)"
hexmask.long.word 0x08 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x0C "ICSSG_RX_STAT_BKT3_SIZE_PRU1,RX Bucket3 Size Configuration (PRU1)"
hexmask.long.word 0x0C 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x10 "ICSSG_RX_STAT_BKT4_SIZE_PRU1,RX Bucket4 Size Configuration (PRU1)"
hexmask.long.word 0x10 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x14 "ICSSG_RX_STAT_64_PRU1,RX 64B Sized Frame Count (PRU1)"
hexmask.long.word 0x14 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x18 "ICSSG_RX_STAT_BKT1_PRU1,RX Bucket1 Sized Frame Count (PRU1)"
hexmask.long.word 0x18 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x1C "ICSSG_RX_STAT_BKT2_PRU1,RX Bucket2 Sized Frame Count (PRU1)"
hexmask.long.word 0x1C 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x20 "ICSSG_RX_STAT_BKT3_PRU1,RX Bucket3 Sized Frame Count (PRU1)"
hexmask.long.word 0x20 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x24 "ICSSG_RX_STAT_BKT4_PRU1,RX Bucket4 Sized Frame Count (PRU1)"
hexmask.long.word 0x24 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x28 "ICSSG_RX_STAT_BKT5_PRU1,RX Bucket5 Sized Frame Count (PRU1)"
hexmask.long.word 0x28 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2C "ICSSG_RX_STAT_TOTAL_BYTES_PRU1,RX Total Byte Count (PRU1)"
line.long 0x30 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU1,RX TX Total Byte Count (PRU1)"
line.long 0x34 "ICSSG_TX_STAT_GOOD_PORT1,TX Good Frame Count Port1"
line.long 0x38 "ICSSG_TX_STAT_BC_PORT1,TX BC Frame Count Port1"
hexmask.long.word 0x38 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x3C "ICSSG_TX_STAT_MC_PORT1,TX MC Frame Count Port1"
hexmask.long.word 0x3C 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x40 "ICSSG_TX_STAT_ODD_ERR_PORT1,TX Odd Nibble Frame Count Port1"
hexmask.long.word 0x40 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x44 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT1,TX Under Flow Error Count Port1"
hexmask.long.word 0x44 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x48 "ICSSG_TX_STAT_MAX_SIZE_PORT1,TX Max Size Frame Port1"
hexmask.long.word 0x48 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x4C "ICSSG_TX_STAT_MAX_ERR_PORT1,TX Max Size Error Frame Count Port1"
hexmask.long.word 0x4C 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x50 "ICSSG_TX_STAT_MIN_SIZE_PORT1,TX Min Size Frame Port1"
hexmask.long.word 0x50 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x54 "ICSSG_TX_STAT_MIN_ERR_PORT1,TX Min Size Error Frame Count Port1"
hexmask.long.word 0x54 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x58 "ICSSG_TX_STAT_BKT1_SIZE_PORT1,TX Bucket1 Size Configuration Port1"
hexmask.long.word 0x58 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x5C "ICSSG_TX_STAT_BKT2_SIZE_PORT1,TX Bucket2 Size Configuration Port1"
hexmask.long.word 0x5C 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x60 "ICSSG_TX_STAT_BKT3_SIZE_PORT1,TX Bucket3 Size Configuration Port1"
hexmask.long.word 0x60 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x64 "ICSSG_TX_STAT_BKT4_SIZE_PORT1,TX Bucket4 Size Configuration Port1"
hexmask.long.word 0x64 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x68 "ICSSG_TX_STAT_64_PORT1,TX 64B Sized Frame Count Port1"
hexmask.long.word 0x68 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x6C "ICSSG_TX_STAT_BKT1_PORT1,TX Bucket1 Sized Frame Count Port1"
hexmask.long.word 0x6C 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x70 "ICSSG_TX_STAT_BKT2_PORT1,TX Bucket2 Sized Frame Count Port1"
hexmask.long.word 0x70 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x74 "ICSSG_TX_STAT_BKT3_PORT1,TX Bucket3 Sized Frame Count Port1"
hexmask.long.word 0x74 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x78 "ICSSG_TX_STAT_BKT4_PORT1,TX Bucket4 Sized Frame Count Port1"
hexmask.long.word 0x78 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x7C "ICSSG_TX_STAT_BKT5_PORT1,TX Bucket5 Sized Frame Count Port1"
hexmask.long.word 0x7C 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x80 "ICSSG_TX_STAT_TOTAL_BYTES_PORT1,TX Total Byte Count Port1"
line.long 0x84 "ICSSG_TX_HSR_TAG_PORT1,TX HSR TAG Port1"
line.long 0x88 "ICSSG_TX_HSR_SEQ_PORT1,TX HSR Seq Port1"
hexmask.long.word 0x88 0.--15. 1. "TX_HSR_SEQ,HSR Seq count"
line.long 0x8C "ICSSG_TX_VLAN_TYPE_TAG_PORT1,TX VLAN Type TAG Port1"
hexmask.long.word 0x8C 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag match to enable VLAN removal"
line.long 0x90 "ICSSG_TX_VLAN_INS_TAG_PORT1,TX VLAN Insertion TAG Port1"
group.long 0xD00++0x03
line.long 0x00 "ICSSG_QUEUEk,Queue<k>"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PTRk,Queue <k> (where k = 0 to 63)"
rgroup.long 0xE00++0x03
line.long 0x00 "ICSSG_QUEUE_PEEKm,Queue Peek<m> Offset = E00h + (m * 4h); where m = 0h to Fh"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PEEK_PTRm,Queue <m> Peek portal (where m = 0 to 15)"
rgroup.long 0xE40++0x03
line.long 0x00 "ICSSG_QUEUE_CNTk,Queue Count<k> Offset = E40h + (k * 4h); where k = 0h to 3Fh"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_CNT_ENTRIESk,Queue Entry Count<k> (where k = 0 to 63)"
group.long 0xF40++0x03
line.long 0x00 "ICSSG_QUEUE_RESET,Queue Reset"
bitfld.long 0x00 0.--5. "RESET_QUEUE_ID,Reset Queue ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x40)++0x03
line.long 0x00 "ICSSG_PA_STAT_PUSH$1,Pa Stat Push0"
hexmask.long.byte 0x00 24.--31. 1. "PA_STAT_PUSH3_0,pa stat push3"
hexmask.long.byte 0x00 16.--23. 1. "PA_STAT_PUSH2_0,pa stat push2"
newline
hexmask.long.byte 0x00 8.--15. 1. "PA_STAT_PUSH1_0,pa stat push1"
hexmask.long.byte 0x00 0.--7. 1. "PA_STAT_PUSH0_0,pa stat push0"
repeat.end
tree.end
tree "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base ad:0xB133000
group.long 0x00++0x2B
line.long 0x00 "ICSSG_ICSS_G_CFG,ICSS_G SGMII mode is supported only for PRU_ICSSG1 instance"
bitfld.long 0x00 16. "SGMII_MODE,SGMII MODE" "Fiber MODE,SGMII MODE"
bitfld.long 0x00 11. "TX_PRU_EN,Enable TX_PRU to gain control of MII TXL2" "0,1"
newline
bitfld.long 0x00 10. "RX_SFD_TX_SOF_EN,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
bitfld.long 0x00 9. "RTU_PRU_PSI_SHARE_EN,Enable the sharing of xfr2psi attached to PRU for PRU RTU AND HW FIFO" "0,1"
newline
bitfld.long 0x00 8. "IEP1_TX_EN,Enable IEP1 for TX Enable" "Use IEP0 CMP3_4,Use IEP1 CMP3_4"
bitfld.long 0x00 5.--6. "MII1_MODE,MII1 MODE" "MII,RGMII,SGMII,?..."
newline
bitfld.long 0x00 3.--4. "MII0_MODE,MII0 MODE" "MII,RGMII,SGMII,?..."
bitfld.long 0x00 2. "RX_L2_G_EN,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L2" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "TX_L2_EN,Enable the TX L2 Fifo" "Disabled,Enabled"
bitfld.long 0x00 0. "TX_L1_EN,Enable the TX L1 Fifo" "Disabled,Enabled"
line.long 0x04 "ICSSG_RGMII_CFG,RGMII"
bitfld.long 0x04 22. "RGMII1_FULLDUPLEX_IN,RGMII Fullduplex overide" "half,full"
bitfld.long 0x04 21. "RGMII1_GIG_IN,RGMII GigBit Enable" "100 Mbs,1000 Mbs"
newline
bitfld.long 0x04 20. "RGMII1_INBAND,RGMII In BandEnable or Force" "InBAND is Disabled,InBAND Enable"
bitfld.long 0x04 18. "RGMII0_FULLDUPLEX_IN,RGMII Fullduplex overide" "half,full"
newline
bitfld.long 0x04 17. "RGMII0_GIG_IN,RGMII GigBit Enable" "100 Mbs,1000 Mbs"
bitfld.long 0x04 16. "RGMII0_INBAND,RGMII In BandEnable or Force" "InBAND is Disabled,InBAND Enable"
newline
bitfld.long 0x04 9. "RGMII_EEE_PHY_ONLY,RGMII Phy Only Low Power" "disable,enable"
bitfld.long 0x04 8. "RGMII_EEE_EN,RGMII Energy Efficient Enable" "disable,enable"
newline
bitfld.long 0x04 7. "RGMII1_FULLDUPLEX,RGMII Fullduplex" "half duplex,full duplex"
bitfld.long 0x04 5.--6. "RGMII1_SPEED,RGMII Speed" "10Mpbs,100Mpbs,1000 Mpbs,?..."
newline
bitfld.long 0x04 4. "RGMII1_LINK,RGMII Link Status" "link is down,link is up"
bitfld.long 0x04 3. "RGMII0_FULLDUPLEX,RGMII Fullduplex" "half duplex,full duplex"
newline
bitfld.long 0x04 1.--2. "RGMII0_SPEED,RGMII Speed" "10Mpbs,100Mpbs,1000 Mpbs,?..."
bitfld.long 0x04 0. "RGMII0_LINK,RGMII Link Status" "link is down,link is up"
line.long 0x08 "ICSSG_MAC_PRU0_0,PRU0 MAC (DA3:DA0)"
line.long 0x0C "ICSSG_MAC_PRU0_1,PRU0 MAC (DA5:DA4)"
hexmask.long.word 0x0C 0.--15. 1. "MAC_PRU0_1,MAC PRU0 DA5:DA4 Used for SAV and DA match"
line.long 0x10 "ICSSG_MAC_PRU1_0,PRU1 MAC (DA3:DA0)"
line.long 0x14 "ICSSG_MAC_PRU1_1,PRU1 MAC (DA5:DA4)"
hexmask.long.word 0x14 0.--15. 1. "MAC_PRU1_1,MAC PRU1 DA5:DA4 Used for SAV and DA match"
line.long 0x18 "ICSSG_MAC_INTERFACE_0,MAC Host Interface (DA3:DA0)"
line.long 0x1C "ICSSG_MAC_INTERFACE_1,MAC Host Interface (DA5:DA4)"
hexmask.long.word 0x1C 0.--15. 1. "MAC_INF_1,MAC Host interface DA"
line.long 0x20 "ICSSG_PREEMPT_CFG,Preempt Configuration Register"
hexmask.long.byte 0x20 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x20 16.--23. 1. "SMD_V,Verification frame TAG"
newline
hexmask.long.byte 0x20 8.--15. 1. "EXP_SMD,None preemptable frame start or express frame"
line.long 0x24 "ICSSG_SMDT1S_CFG,SMD Type1S Preemptable Frame Start Configuration"
hexmask.long.byte 0x24 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x24 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
newline
hexmask.long.byte 0x24 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
hexmask.long.byte 0x24 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x28 "ICSSG_SMDT1C_CFG,SMD Type1C None Initial Frag Configuration"
hexmask.long.byte 0x28 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x28 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
newline
hexmask.long.byte 0x28 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
hexmask.long.byte 0x28 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
group.long 0x34++0x03
line.long 0x00 "ICSSG_FRAG_CNT_CFG,Frag Count Configuration"
hexmask.long.byte 0x00 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
newline
hexmask.long.byte 0x00 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
hexmask.long.byte 0x00 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
group.long 0x60++0x07
line.long 0x00 "ICSSG_FDB_GEN_CFG1,FDB Configuration1"
hexmask.long.tbyte 0x00 8.--25. 1. "SMEM_VLAN_OFFSET,SMEM VLAN FID table base address"
bitfld.long 0x00 3.--6. "FDB_HASH_SIZE,FDB hash size 0:64 1:128 2:256 3:512 4:1024 5:2048" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--1. "FDB_BUCKET_SIZE,FDB buket size 0:1 1:2 2:4 3:8" "0,1,2,3"
line.long 0x04 "ICSSG_FDB_GEN_CFG2,FDB Configuration2"
bitfld.long 0x04 9.--12. "FDB_GEN_MODE_BYTE_EN,FDB General Mode Byte compare size" "1 Byte,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16 Bytes"
bitfld.long 0x04 8. "FDB_GEN_MODE_EN_BK1,FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled" "0,1"
newline
bitfld.long 0x04 7. "FDB_GEN_MODE_EN_BK0,FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled" "0,1"
bitfld.long 0x04 6. "FDB_VLAN_EN,FDB Global VLAN Enable" "0,1"
newline
bitfld.long 0x04 5. "FDB_HSR_EN,FDB Global HSR Enable note VLAN most be disabled" "0,1"
bitfld.long 0x04 2. "FDB_HOST_EN,FDB HOST Enable" "0,1"
newline
bitfld.long 0x04 1. "FDB_PRU1_EN,FDB PRU1 Enable" "0,1"
bitfld.long 0x04 0. "FDB_PRU0_EN,FDB PRU0 Enable" "0,1"
group.long 0x6C++0x2B
line.long 0x00 "ICSSG_FDB_DF_VLAN,FDB Default PRU VLAN"
hexmask.long.word 0x00 16.--27. 1. "FDB_PRU1_DF_VLAN,FDB Default VLAN for PRU1"
hexmask.long.word 0x00 0.--11. 1. "FDB_PRU0_DF_VLAN,FDB Default VLAN for PRU0"
line.long 0x04 "ICSSG_FDB_HOST_DA0,FDB HOST DA3:0 Configuration"
line.long 0x08 "ICSSG_FDB_HOST_DA1,FDB HOST DA5:4 Configuration"
hexmask.long.word 0x08 0.--15. 1. "FDB_HOST_DA1,FDB HOST DA 5:4"
line.long 0x0C "ICSSG_FDB_HOST_SA0,FDB HOST SA3:0 Configuration"
line.long 0x10 "ICSSG_FDB_HOST_VLAN_SA1,FDB HOST VLAN SA5:4 Configuration"
hexmask.long.word 0x10 16.--31. 1. "FDB_HOST_VLAN_HSR,FDB HOST VLAN [11:0] OR HSR [15:0]"
hexmask.long.word 0x10 0.--15. 1. "FDB_HOST_SA1,FDB HOST SA 5:4"
line.long 0x14 "ICSSG_FT1_START_LEN_PRU0,Filter1 Start and Length (PRU0)"
bitfld.long 0x14 16.--19. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--14. 1. "FT1_START,Byte count start for Filter1"
line.long 0x18 "ICSSG_FT1_CFG_PRU0,Filter1 Configuration (PRU0)"
bitfld.long 0x18 14.--15. "FT1_7CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 12.--13. "FT1_6CFG," "?,Equal,Greater Than,Less Than"
newline
bitfld.long 0x18 10.--11. "FT1_5CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 8.--9. "FT1_4CFG," "?,Equal,Greater Than,Less Than"
newline
bitfld.long 0x18 6.--7. "FT1_3CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 4.--5. "FT1_2CFG," "?,Equal,Greater Than,Less Than"
newline
bitfld.long 0x18 2.--3. "FT1_1CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x18 0.--1. "FT1_0CFG," "?,Equal,Greater Than,Less Than"
line.long 0x1C "ICSSG_FT1_k_DA0_PRU0,Filter1<k> DA0 (Pru0)"
line.long 0x20 "ICSSG_FT1_k_DA1_PRU0,Filter1<k> DA1 (PRU0)"
hexmask.long.word 0x20 0.--15. 1. "FT1_k_DA1,Filter1 DA6:DA5"
line.long 0x24 "ICSSG_FT1_k_DA_MASK0_PRU0,Filter1<k> DA0 Mask (PRU0)"
line.long 0x28 "ICSSG_FT1_k_DA_MASK1_PRU0,Filter1<k> DA1 Mask (PRU0)"
hexmask.long.word 0x28 0.--15. 1. "FT1_k_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x108++0x1F
line.long 0x00 "ICSSG_FT3_m_START_PRU0,Filter3 Byte Count Start"
hexmask.long.word 0x00 0.--14. 1. "FT3_START,Byte count start for Filter3"
line.long 0x04 "ICSSG_FT3_m_START_AUTO_PRU0,Filter3 Byte Count Start for Auto Skip mode"
hexmask.long.word 0x04 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
line.long 0x08 "ICSSG_FT3_m_START_LEN_PRU0,Filter3 Start Offset for PRU0"
bitfld.long 0x08 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x0C "ICSSG_FT3_m_JMP_OFFSET_PRU0,Filter3 Jump Offset for PRU0"
hexmask.long.word 0x0C 16.--30. 1. "FT3_m_NJMP_OFFSET_PRU0,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x0C 0.--14. 1. "FT3_m_IJMP_OFFSET_PRU0,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x10 "ICSSG_FT3_m_LEN_PRU0,Filter3 Length Offset for PRU0"
bitfld.long 0x10 24. "FT3_m_LEN_BIG_EN_PRU0,Enable Big Indian on Length" "0,1"
bitfld.long 0x10 16.--19. "FT3_m_LEN_SIZE_BIT_PRU0,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x10 0.--8. 1. "FT3_m_LEN_START_BIT_PRU0,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0x14 "ICSSG_FT3_m_CFG_PRU0,Filter3 Configuration for PRU0"
hexmask.long.word 0x14 16.--31. 1. "FT3_m_TRIG_OR_EN,Trigger ft3 select for auto skip enable if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x14 2. "FT3_m_VLAN_SKIP_EN," "0,1"
newline
bitfld.long 0x14 0.--1. "FT3_mCFG," "?,EQ,GT,LT"
line.long 0x18 "ICSSG_FT3_m_T_PRU0,Filter3 Type for PRU0"
line.long 0x1C "ICSSG_FT3_m_T_MASK_PRU0,Filter3 Mask for PRU0"
group.long 0x308++0x0F
line.long 0x00 "ICSSG_FT3_m_P0_PRU0,Filter3 PRU0 (P4:P1)"
line.long 0x04 "ICSSG_FT3_m_P1_PRU0,Filter3 PRU0 (P8:P5)"
line.long 0x08 "ICSSG_FT3_n_P_MASK0_PRU0,Filter3 Mask0 (MP4:MP1)"
line.long 0x0C "ICSSG_FT3_n_P_MASK1_PRU0,Filter3 Mask1 (MP8:MP5)"
group.long 0x408++0x0B
line.long 0x00 "ICSSG_FT_RX_PTR_PRU0,RX Current Filter Byte Count (PRU0)"
line.long 0x04 "ICSSG_RX_CLASSm_AND_EN_PRU0,RX Class<m> AND Enable Register"
line.long 0x08 "ICSSG_RX_CLASSm_OR_EN_PRU0,RX Class<m> OR Enable Register"
group.long 0x48C++0x0B
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU0,RX Class Configuration 1 Register"
bitfld.long 0x00 30.--31. "RX_CLASS15_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 28.--29. "RX_CLASS14_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 26.--27. "RX_CLASS13_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 24.--25. "RX_CLASS12_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 22.--23. "RX_CLASS11_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 20.--21. "RX_CLASS10_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 18.--19. "RX_CLASS9_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 16.--17. "RX_CLASS8_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 14.--15. "RX_CLASS7_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 12.--13. "RX_CLASS6_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 10.--11. "RX_CLASS5_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 8.--9. "RX_CLASS4_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 6.--7. "RX_CLASS3_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 4.--5. "RX_CLASS2_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
newline
bitfld.long 0x00 2.--3. "RX_CLASS1_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 0.--1. "RX_CLASS0_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
line.long 0x04 "ICSSG_RX_CLASS_CFG2_PRU0,RX Class Configuration 2 Register"
hexmask.long.word 0x04 16.--31. 1. "RX_CLASS_OR_NV,RX class invert OR not invert enable"
hexmask.long.word 0x04 0.--15. 1. "RX_CLASS_AND_NV,RX class invert AND not invert enable"
line.long 0x08 "ICSSG_RX_CLASS_GATESm_PRU0,RX Class Gate<m> Configuration PRU0 Register"
bitfld.long 0x08 8. "RX_RED_PHASE_ENm,red phase neable" "disable,enable"
bitfld.long 0x08 6. "RX_ALLOW_MASKm,allow mask" "unmask,mask"
newline
bitfld.long 0x08 5. "RX_CLASS_RAW_MASKm,class raw mask" "unmask,mask"
bitfld.long 0x08 4. "RX_PHASE_MASKm,time phase mask" "unmask,mask"
newline
bitfld.long 0x08 0.--2. "RX_RATE_GATE_SELm,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0x4D4++0x13
line.long 0x00 "ICSSG_RX_GREEN_PRU0,RX Green Status PRU0"
rbitfld.long 0x00 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "RX_GREEN_CMP_SEL,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ICSSG_SA_HASH_PRU0,SA Hash Seed PRU0"
hexmask.long.word 0x04 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x08 "ICSSG_CONN_HASH_PRU0,Connection Hash Seed PRU0"
hexmask.long.word 0x08 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x0C "ICSSG_CONN_HASH_START_PRU0,Connection Hash Start PRU0"
hexmask.long.word 0x0C 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x10 "ICSSG_RX_RATE_CFGn_PRU0,RX Rate Configuration<n> Register"
group.long 0x504++0x0F
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU0,RX Rate Source Select0"
bitfld.long 0x00 24.--29. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_RX_RATE_SRC_SEL1_PRU0,RX Rate Source Select1"
bitfld.long 0x04 24.--29. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 16.--21. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 8.--13. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--5. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "ICSSG_TX_RATE_CFG1_n_PRU0,TX Rate Configuration1 Registe"
line.long 0x0C "ICSSG_TX_RATE_CFG2_n_PRU0,TX Rate Configuration2 Register"
rbitfld.long 0x0C 17. "TX_RATE_ALLOWn,TX Rate Pkt Enable" "0,1"
bitfld.long 0x0C 16. "TX_RATE_ENn,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x0C 0.--15. 1. "TX_RATE_LENn,TX Rate Pkt Length"
group.long 0x54C++0x2F
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU0,RX Good Frame Count (PRU0)"
line.long 0x04 "ICSSG_RX_STAT_BC_PRU0,RX BC Frame Count (PRU0)"
hexmask.long.word 0x04 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type Wrt subtracts"
line.long 0x08 "ICSSG_RX_STAT_MC_PRU0,RX MC Frame Count (PRU0)"
hexmask.long.word 0x08 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type Wrt subtracts"
line.long 0x0C "ICSSG_RX_STAT_CRC_ERR_PRU0,RX CRC Error Frame Count (PRU0)"
hexmask.long.word 0x0C 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err Wrt subtracts"
line.long 0x10 "ICSSG_RX_STAT_MII_ERR_PRU0,RX MII Error Frame Count (PRU0)"
hexmask.long.word 0x10 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err Wrt subtracts"
line.long 0x14 "ICSSG_RX_STAT_ODD_ERR_PRU0,RX Odd Nibble Frame Count (PRU0)"
hexmask.long.word 0x14 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii Wrt subtracts"
line.long 0x18 "ICSSG_RX_STAT_MAX_SIZE_PRU0,RX Max Size Frame Count (PRU0)"
hexmask.long.word 0x18 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x1C "ICSSG_RX_STAT_MAX_ERR_PRU0,RX Max Size Error Frame Count (PRU0)"
hexmask.long.word 0x1C 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit Wrt subtracts"
line.long 0x20 "ICSSG_RX_STAT_MIN_SIZE_PRU0,RX Min Size Frame Count (PRU0)"
hexmask.long.word 0x20 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x24 "ICSSG_RX_STAT_MIN_ERR_PRU0,RX Min Size Error Frame Count (PRU0)"
hexmask.long.word 0x24 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit Wrt subtracts"
line.long 0x28 "ICSSG_RX_STAT_OVERRUN_ERR_PRU0,RX Overrun Frame Count (PRU0)"
hexmask.long.word 0x28 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count"
line.long 0x2C "ICSSG_RX_STAT_CLASSm_HIT_PRU0,RX Class<m> Hit"
group.long 0x5B8++0xAB
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU0,RX SMD Frag Error Count PRU0"
hexmask.long.byte 0x00 24.--31. 1. "RX_STAT_SMD_ERR_PRU0,RX SMDS Error Count Inc when first none 0x55 does not match any valid SMD Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "RX_STAT_FRAG_ERR_PRU0,RX Frag_Cnt Seq Error Count Wrt subtracts"
newline
hexmask.long.byte 0x00 8.--15. 1. "RX_STAT_SMDC_ERR_PRU0,RX SMDCx Seq Error Count Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "RX_STAT_SMDS_ERR_PRU0,RX SMDSx Seq Error Count Wrt subtracts"
line.long 0x04 "ICSSG_RX_STAT_BKT1_SIZE_PRU0,RX Bucket1 Size Configuration (PRU0)"
hexmask.long.word 0x04 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x08 "ICSSG_RX_STAT_BKT2_SIZE_PRU0,RX Bucket2 Size Configuration (PRU0)"
hexmask.long.word 0x08 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x0C "ICSSG_RX_STAT_BKT3_SIZE_PRU0,RX Bucket3 Size Configuration (PRU0)"
hexmask.long.word 0x0C 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x10 "ICSSG_RX_STAT_BKT4_SIZE_PRU0,RX Bucket4 Size Configuration (PRU0)"
hexmask.long.word 0x10 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x14 "ICSSG_RX_STAT_64_PRU0,RX 64B Sized Frame Count (PRU0)"
hexmask.long.word 0x14 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x18 "ICSSG_RX_STAT_BKT1_PRU0,RX Bucket1 Sized Frame Count (PRU0)"
hexmask.long.word 0x18 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x1C "ICSSG_RX_STAT_BKT2_PRU0,RX Bucket2 Sized Frame Count (PRU0)"
hexmask.long.word 0x1C 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x20 "ICSSG_RX_STAT_BKT3_PRU0,RX Bucket3 Sized Frame Count (PRU0)"
hexmask.long.word 0x20 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x24 "ICSSG_RX_STAT_BKT4_PRU0,RX Bucket4 Sized Frame Count (PRU0)"
hexmask.long.word 0x24 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x28 "ICSSG_RX_STAT_BKT5_PRU0,RX Bucket5 Sized Frame Count (PRU0)"
hexmask.long.word 0x28 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2C "ICSSG_RX_STAT_TOTAL_BYTES_PRU0,RX Total Byte Count (PRU0)"
line.long 0x30 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU0,RX TX Total Byte Count (PRU0)"
line.long 0x34 "ICSSG_TX_STAT_GOOD_PORT0,TX Good Frame Count Port0"
line.long 0x38 "ICSSG_TX_STAT_BC_PORT0,TX BC Frame Count Port0"
hexmask.long.word 0x38 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x3C "ICSSG_TX_STAT_MC_PORT0,TX MC Frame Count Port0"
hexmask.long.word 0x3C 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count"
line.long 0x40 "ICSSG_TX_STAT_ODD_ERR_PORT0,TX Odd Nibble Frame Count Port0"
hexmask.long.word 0x40 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x44 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT0,TX Under Flow Error Count Port0"
hexmask.long.word 0x44 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x48 "ICSSG_TX_STAT_MAX_SIZE_PORT0,TX Max Size Frame Port0"
hexmask.long.word 0x48 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x4C "ICSSG_TX_STAT_MAX_ERR_PORT0,TX Max Size Error Frame Count Port0"
hexmask.long.word 0x4C 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x50 "ICSSG_TX_STAT_MIN_SIZE_PORT0,TX Min Size Frame Port0"
hexmask.long.word 0x50 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x54 "ICSSG_TX_STAT_MIN_ERR_PORT0,TX Min Size ErrorFrame Count Port0"
hexmask.long.word 0x54 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x58 "ICSSG_TX_STAT_BKT1_SIZE_PORT0,TX Bucket1 Size Configuration Port0"
hexmask.long.word 0x58 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x5C "ICSSG_TX_STAT_BKT2_SIZE_PORT0,TX Bucket2 Size Configuration Port0"
hexmask.long.word 0x5C 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x60 "ICSSG_TX_STAT_BKT3_SIZE_PORT0,TX Bucket3 Size Configuration Port0"
hexmask.long.word 0x60 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x64 "ICSSG_TX_STAT_BKT4_SIZE_PORT0,TX Bucket4 Size Configuration Port0"
hexmask.long.word 0x64 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x68 "ICSSG_TX_STAT_64_PORT0,TX 64B Sized Frame Count Port0"
hexmask.long.word 0x68 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count"
line.long 0x6C "ICSSG_TX_STAT_BKT1_PORT0,TX Bucket1 Sized Frame Count Port0"
hexmask.long.word 0x6C 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x70 "ICSSG_TX_STAT_BKT2_PORT0,TX Bucket2 Sized Frame Count Port0"
hexmask.long.word 0x70 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x74 "ICSSG_TX_STAT_BKT3_PORT0,TX Bucket3 Sized Frame Count Port0"
hexmask.long.word 0x74 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x78 "ICSSG_TX_STAT_BKT4_PORT0,TX Bucket4 Sized Frame Count Port0"
hexmask.long.word 0x78 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x7C "ICSSG_TX_STAT_BKT5_PORT0,TX Bucket5 Sized Frame Count Port0"
hexmask.long.word 0x7C 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x80 "ICSSG_TX_STAT_TOTAL_BYTES_PORT0,TX Total Byte Count Port0"
line.long 0x84 "ICSSG_TX_HSR_TAG_PORT0,TX HSR TAG Port0"
line.long 0x88 "ICSSG_TX_HSR_SEQ_PORT0,TX HSR Seq Port0"
hexmask.long.word 0x88 0.--15. 1. "TX_HSR_SEQ,HSR Seq count"
line.long 0x8C "ICSSG_TX_VLAN_TYPE_TAG_PORT0,TX VLAN Type TAG Port0"
hexmask.long.word 0x8C 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag match to enable VLAN removal"
line.long 0x90 "ICSSG_TX_VLAN_INS_TAG_PORT0,TX VLAN Insertion TAG Port0"
line.long 0x94 "ICSSG_FT1_START_LEN_PRU1,Filter1 Start and Length (PRU1)"
bitfld.long 0x94 16.--19. "FT1_LEN,Defines the total number of Bytes Filter1 will check before Valid bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x94 0.--14. 1. "FT1_START,Byte count start for Filter1"
line.long 0x98 "ICSSG_FT1_CFG_PRU1,Filter1 Configuration (PRU1)"
bitfld.long 0x98 14.--15. "FT1_7CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 12.--13. "FT1_6CFG," "?,Equal,Greater Than,Less Than"
newline
bitfld.long 0x98 10.--11. "FT1_5CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 8.--9. "FT1_4CFG," "?,Equal,Greater Than,Less Than"
newline
bitfld.long 0x98 6.--7. "FT1_3CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 4.--5. "FT1_2CFG," "?,Equal,Greater Than,Less Than"
newline
bitfld.long 0x98 2.--3. "FT1_1CFG," "?,Equal,Greater Than,Less Than"
bitfld.long 0x98 0.--1. "FT1_0CFG," "?,Equal,Greater Than,Less Than"
line.long 0x9C "ICSSG_FT1_k_DA0_PRU1,Filter1<k> DA0 (PRU1)"
line.long 0xA0 "ICSSG_FT1_k_DA1_PRU1,Filter1<k> DA1 (PRU1)"
hexmask.long.word 0xA0 0.--15. 1. "FT1_k_DA1,Filter1 DA6:DA5"
line.long 0xA4 "ICSSG_FT1_k_DA_MASK0_PRU1,Filter1<k> DA0 Mask (PRU1)"
line.long 0xA8 "ICSSG_FT1_k_DA_MASK1_PRU1,Filter1<k> DA1 Mask (PRU1)"
hexmask.long.word 0xA8 0.--15. 1. "FT1_k_DA_MASK1,Filter1 MDA6:MDA5 set to 1 to mask that bit"
group.long 0x6D4++0x1F
line.long 0x00 "ICSSG_FT3_m_START_PRU1,Filter3<m> Start (PRU1)"
hexmask.long.word 0x00 0.--14. 1. "FT3_START,Byte count start for Filter3"
line.long 0x04 "ICSSG_FT3_m_START_AUTO_PRU1,Filter3<m> Start Auto (PRU1)"
hexmask.long.word 0x04 0.--14. 1. "FT3_START_AUTO,Byte count start for Auto skip mode"
line.long 0x08 "ICSSG_FT3_m_START_LEN_PRU1,Filter3<m> Start offset (PRU1)"
bitfld.long 0x08 20.--22. "FT3_OFFSET_END,Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "FT3_OFFSET_START,Defines which byte within FT3_[N]P[63:0] to start the compare" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 0.--14. 1. "FT3_OFFSET,Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero"
line.long 0x0C "ICSSG_FT3_m_JMP_OFFSET_PRU1,Filter3<m> Jmp offset (PRU1)"
hexmask.long.word 0x0C 16.--30. 1. "FT3_m_NJMP_OFFSET_PRU1,Defines the Next Offset to compare when auto arm jump is enabled"
hexmask.long.word 0x0C 0.--14. 1. "FT3_m_IJMP_OFFSET_PRU1,Defines the Intial Offset to compare when auto arm jump is enabled"
line.long 0x10 "ICSSG_FT3_m_LEN_PRU1,Filter3 Length Offset for (PRU1)"
bitfld.long 0x10 24. "FT3_m_LEN_BIG_EN_PRU1,Enable Big Indian on Length" "0,1"
bitfld.long 0x10 16.--19. "FT3_m_LEN_SIZE_BIT_PRU1,Defines number of bits to extract the length for the auto skip function" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x10 0.--8. 1. "FT3_m_LEN_START_BIT_PRU1,Defines relative bit offset from the HIT byte location upto 512 bit offset the exraction to determine the on the fly length byte offset"
line.long 0x14 "ICSSG_FT3_m_CFG_PRU1,Filter3<m> Configuration (PRU1)"
hexmask.long.word 0x14 16.--31. 1. "FT3_m_TRIG_OR_EN,Trigger ft3 select for auto skip enable if one or more set the function is enabled note you can not slect the same ft3 only others"
bitfld.long 0x14 2. "FT3_m_VLAN_SKIP_EN," "0,1"
newline
bitfld.long 0x14 0.--1. "FT3_mCFG," "?,EQ,GT,LT"
line.long 0x18 "ICSSG_FT3_m_T_PRU1,Filter3<m> T (PRU1)"
line.long 0x1C "ICSSG_FT3_m_T_MASK_PRU1,Filter3<m> T Mask (PRU1)"
group.long 0x8D4++0x0F
line.long 0x00 "ICSSG_FT3_m_P0_PRU1,Filter3<m> P0 (PRU1)"
line.long 0x04 "ICSSG_FT3_m_P1_PRU1,Filter3<m> P1 (PRU1)"
line.long 0x08 "ICSSG_FT3_m_P_MASK0_PRU1,Filter3<m> P Mask0 (PRU1)"
line.long 0x0C "ICSSG_FT3_m_P_MASK1_PRU1,Filter3<m> P Mask1 (PRU1)"
group.long 0x9D4++0x0B
line.long 0x00 "ICSSG_FT_RX_PTR_PRU1,Filter Byte Count (PRU1)"
line.long 0x04 "ICSSG_RX_CLASSm_AND_EN_PRU1,RX Class<m> AND Enable (PRU1)"
line.long 0x08 "ICSSG_RX_CLASSm_OR_EN_PRU1,RX Class<m> OR Enable (PRU1)"
group.long 0xA58++0x0B
line.long 0x00 "ICSSG_RX_CLASS_CFG1_PRU1,RX Class Configuration 1 Register"
bitfld.long 0x00 30.--31. "RX_CLASS15_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 28.--29. "RX_CLASS14_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 26.--27. "RX_CLASS13_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 24.--25. "RX_CLASS12_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 22.--23. "RX_CLASS11_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 20.--21. "RX_CLASS10_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 18.--19. "RX_CLASS9_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 16.--17. "RX_CLASS8_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 14.--15. "RX_CLASS7_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 12.--13. "RX_CLASS6_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 10.--11. "RX_CLASS5_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 8.--9. "RX_CLASS4_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 6.--7. "RX_CLASS3_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 4.--5. "RX_CLASS2_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
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bitfld.long 0x00 2.--3. "RX_CLASS1_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
bitfld.long 0x00 0.--1. "RX_CLASS0_SEL,rx class final term selection" "OR,AND,OR AND AND OR,OR OR AND"
line.long 0x04 "ICSSG_RX_CLASS_CFG2_PRU1,RX Class Configuration 2 Register"
hexmask.long.word 0x04 16.--31. 1. "RX_CLASS_OR_NV,RX class or nv enable"
hexmask.long.word 0x04 0.--15. 1. "RX_CLASS_AND_NV,RX class and nv enable"
line.long 0x08 "ICSSG_RX_CLASS_GATESm_PRU1,RX Class Gate Configuration PRU1 Register"
bitfld.long 0x08 8. "RX_RED_PHASE_ENm,red phase neable" "disable,enable"
bitfld.long 0x08 6. "RX_ALLOW_MASKm,allow mask" "unmask,mask"
newline
bitfld.long 0x08 5. "RX_CLASS_RAW_MASKm,class raw mask" "unmask,mask"
bitfld.long 0x08 4. "RX_PHASE_MASKm,time phase mask" "unmask,mask"
newline
bitfld.long 0x08 0.--2. "RX_RATE_GATE_SELm,defines which rx_rate will gate rx_class" "0,1,2,3,4,5,6,7"
group.long 0xAA0++0x13
line.long 0x00 "ICSSG_RX_GREEN_PRU1,RX Green Status PRU1"
rbitfld.long 0x00 4. "RX_GREEN_VAL,0 RED 1 GREEN status" "0,1"
bitfld.long 0x00 0.--3. "RX_GREEN_CMP_SEL,define which IEP CMP start green" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ICSSG_SA_HASH_PRU1,SA Hash Seed PRU1"
hexmask.long.word 0x04 0.--9. 1. "SA_HASH_SEED,SA Hash Seed"
line.long 0x08 "ICSSG_CONN_HASH_PRU1,Connection Hash Seed PRU1"
hexmask.long.word 0x08 0.--9. 1. "CONN_HASH_SEED,Connection Hash Seed"
line.long 0x0C "ICSSG_CONN_HASH_START_PRU1,Connection Hash Start PRU1"
hexmask.long.word 0x0C 0.--14. 1. "CONN_HASH_START,Connection Hash Start which 4 Bytes to hash"
line.long 0x10 "ICSSG_RX_RATE_CFGn_PRU1,RX Rate Configuration Register"
group.long 0xAD0++0x0F
line.long 0x00 "ICSSG_RX_RATE_SRC_SEL0_PRU1,RX Rate Source Select0"
bitfld.long 0x00 24.--29. "RX_RATE_SRC_SEL3,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "RX_RATE_SRC_SEL2,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "RX_RATE_SRC_SEL1,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "RX_RATE_SRC_SEL0,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_RX_RATE_SRC_SEL1_PRU1,RX Rate Source Select1"
bitfld.long 0x04 24.--29. "RX_RATE_SRC_SEL7,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 16.--21. "RX_RATE_SRC_SEL6,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 8.--13. "RX_RATE_SRC_SEL5,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 0.--5. "RX_RATE_SRC_SEL4,Map which filter/flag/class hit that rate logic uses see table for mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "ICSSG_TX_RATE_CFG1_n_PRU1,TX Rate Configuration 1 Register"
line.long 0x0C "ICSSG_TX_RATE_CFG2_n_PRU1,TX Rate Configuration 2 Register"
rbitfld.long 0x0C 17. "TX_RATE_ALLOWn,TX Rate Pkt Enable" "0,1"
bitfld.long 0x0C 16. "TX_RATE_ENn,TX Rate Pkt Enable" "0,1"
newline
hexmask.long.word 0x0C 0.--15. 1. "TX_RATE_LENn,TX Rate Pkt Length"
group.long 0xB18++0x2F
line.long 0x00 "ICSSG_RX_STAT_GOOD_PRU1,RX Good Frame Count (PRU1)"
line.long 0x04 "ICSSG_RX_STAT_BC_PRU1,RX BC Frame Count (PRU1)"
hexmask.long.word 0x04 0.--15. 1. "RX_BC_FRM_CNT,RX BC Frame Count Inc on BC type Wrt subtracts"
line.long 0x08 "ICSSG_RX_STAT_MC_PRU1,RX MC Frame Count (PRU1)"
hexmask.long.word 0x08 0.--15. 1. "RX_MC_FRM_CNT,RX MC Frame Count Inc on MC type Wrt subtracts"
line.long 0x0C "ICSSG_RX_STAT_CRC_ERR_PRU1,RX CRC Error Frame Count (PRU1)"
hexmask.long.word 0x0C 0.--15. 1. "RX_CRC_ERR_FRM_CNT,RX CRC Err Frame Count Inc on crc err Wrt subtracts"
line.long 0x10 "ICSSG_RX_STAT_MII_ERR_PRU1,RX MII Error Frame Count (PRU1)"
hexmask.long.word 0x10 0.--15. 1. "RX_MII_ERR_FRM_CNT,RX MII Err Frame Count Inc on mii sgmii rgmii err Wrt subtracts"
line.long 0x14 "ICSSG_RX_STAT_ODD_ERR_PRU1,RX Odd Nibble Frame Count (PRU1)"
hexmask.long.word 0x14 0.--15. 1. "RX_ODD_ERR_FRM_CNT,RX Odd Nibble Frame Count Inc on odd nibble mii Wrt subtracts"
line.long 0x18 "ICSSG_RX_STAT_MAX_SIZE_PRU1,RX Max Size Frame (PRU1)"
hexmask.long.word 0x18 0.--15. 1. "RX_MAX_SIZE_FRM,RX MAX Size Frame Count Limit"
line.long 0x1C "ICSSG_RX_STAT_MAX_ERR_PRU1,RX Max Size Error Frame Count (PRU1)"
hexmask.long.word 0x1C 0.--15. 1. "RX_MAX_ERR_FRM_CNT,RX MAX Size Err Frame Count Inc if > than Limit Wrt subtracts"
line.long 0x20 "ICSSG_RX_STAT_MIN_SIZE_PRU1,RX Min Size Frame (PRU1)"
hexmask.long.word 0x20 0.--15. 1. "RX_MIN_SIZE_FRM,RX MIN Size Frame Limit"
line.long 0x24 "ICSSG_RX_STAT_MIN_ERR_PRU1,RX Min Size Error Frame Count (PRU1)"
hexmask.long.word 0x24 0.--15. 1. "RX_MIN_ERR_FRM_CNT,RX MIN Size Frame Count Inc if < than limit Wrt subtracts"
line.long 0x28 "ICSSG_RX_STAT_OVERRUN_ERR_PRU1,RX Overrun Frame Count (PRU1)"
hexmask.long.word 0x28 0.--15. 1. "RX_OVERRUN_ERR_FRM_CNT,RX L1 FIFO overflow Frame Count Inc on overflow event Wrt subtracts"
line.long 0x2C "ICSSG_RX_STAT_CLASSm_HIT_PRU1,RX Class<m>"
group.long 0xB84++0x93
line.long 0x00 "ICSSG_RX_STAT_SMD_FRAG_ERR_PRU1,RX SMD Frag Error Count (PRU1)"
hexmask.long.byte 0x00 24.--31. 1. "RX_STAT_SMD_ERR_PRU1,RX SMDS Error Count Inc when first none 0x55 does not match any valid SMD Wrt subtracts"
hexmask.long.byte 0x00 16.--23. 1. "RX_STAT_FRAG_ERR_PRU1,RX Frag_Cnt Seq Error Count Wrt subtracts"
newline
hexmask.long.byte 0x00 8.--15. 1. "RX_STAT_SMDC_ERR_PRU1,RX SMDCx Seq Error Count Wrt subtracts"
hexmask.long.byte 0x00 0.--7. 1. "RX_STAT_SMDS_ERR_PRU1,RX SMDSx Seq Error Count Wrt subtracts"
line.long 0x04 "ICSSG_RX_STAT_BKT1_SIZE_PRU1,RX Bucket1 Size Configuration (PRU1)"
hexmask.long.word 0x04 0.--13. 1. "RX_STAT_BKT1_SIZE,RX Bucket1 Byte Size"
line.long 0x08 "ICSSG_RX_STAT_BKT2_SIZE_PRU1,RX Bucket2 Size Configuration (PRU1)"
hexmask.long.word 0x08 0.--13. 1. "RX_STAT_BKT2_SIZE,RX Bucket2 Byte Size"
line.long 0x0C "ICSSG_RX_STAT_BKT3_SIZE_PRU1,RX Bucket3 Size Configuration (PRU1)"
hexmask.long.word 0x0C 0.--13. 1. "RX_STAT_BKT3_SIZE,RX Bucket3 Byte Size"
line.long 0x10 "ICSSG_RX_STAT_BKT4_SIZE_PRU1,RX Bucket4 Size Configuration (PRU1)"
hexmask.long.word 0x10 0.--13. 1. "RX_STAT_BKT4_SIZE,RX Bucket4 Byte Size"
line.long 0x14 "ICSSG_RX_STAT_64_PRU1,RX 64B Sized Frame Count (PRU1)"
hexmask.long.word 0x14 0.--15. 1. "RX_64_FRM_CNT,RX 64Byte Frame Count Inc if 64B size"
line.long 0x18 "ICSSG_RX_STAT_BKT1_PRU1,RX Bucket1 Sized Frame Count (PRU1)"
hexmask.long.word 0x18 0.--15. 1. "RX_STAT_BKT1,RX Bucket1 Frame Count Inc if <= than Bucket1 Byte Size"
line.long 0x1C "ICSSG_RX_STAT_BKT2_PRU1,RX Bucket2 Sized Frame Count (PRU1)"
hexmask.long.word 0x1C 0.--15. 1. "RX_STAT_BKT2,RX Bucket2 Frame Count Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x20 "ICSSG_RX_STAT_BKT3_PRU1,RX Bucket3 Sized Frame Count (PRU1)"
hexmask.long.word 0x20 0.--15. 1. "RX_STAT_BKT3,RX Bucket3 Frame Count Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x24 "ICSSG_RX_STAT_BKT4_PRU1,RX Bucket4 Sized Frame Count (PRU1)"
hexmask.long.word 0x24 0.--15. 1. "RX_STAT_BKT4,RX Bucket4 Frame Count Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x28 "ICSSG_RX_STAT_BKT5_PRU1,RX Bucket5 Sized Frame Count (PRU1)"
hexmask.long.word 0x28 0.--15. 1. "RX_STAT_BKT5,RX Bucket5 Frame Count Inc if > than Bucket4 Byte Size"
line.long 0x2C "ICSSG_RX_STAT_TOTAL_BYTES_PRU1,RX Total Byte Count (PRU1)"
line.long 0x30 "ICSSG_RXTX_STAT_TOTAL_BYTES_PRU1,RX TX Total Byte Count (PRU1)"
line.long 0x34 "ICSSG_TX_STAT_GOOD_PORT1,TX Good Frame Count Port1"
line.long 0x38 "ICSSG_TX_STAT_BC_PORT1,TX BC Frame Count Port1"
hexmask.long.word 0x38 0.--15. 1. "TX_BC_FRM_CNT,TX BC Frame Count Inc if BC"
line.long 0x3C "ICSSG_TX_STAT_MC_PORT1,TX MC Frame Count Port1"
hexmask.long.word 0x3C 0.--15. 1. "TX_MC_FRM_CNT,TX MC Frame Count Inc if MC"
line.long 0x40 "ICSSG_TX_STAT_ODD_ERR_PORT1,TX Odd Nibble Frame Count Port1"
hexmask.long.word 0x40 0.--15. 1. "TX_ODD_ERR_FRM_CNT,TX Odd Nibble Frame Count Inc if mii odd nibble"
line.long 0x44 "ICSSG_TX_STAT_UNDERFLOW_ERR_PORT1,TX Under Flow Error Count Port1"
hexmask.long.word 0x44 0.--15. 1. "TX_UNDERFLOW_CNT,TX MAX Underflow Error Cnt"
line.long 0x48 "ICSSG_TX_STAT_MAX_SIZE_PORT1,TX Max Size Frame Port1"
hexmask.long.word 0x48 0.--15. 1. "TX_MAX_SIZE_FRM,TX MAX Size Frame Count Limit"
line.long 0x4C "ICSSG_TX_STAT_MAX_ERR_PORT1,TX Max Size Error Frame Count Port1"
hexmask.long.word 0x4C 0.--15. 1. "TX_MAX_ERR_FRM_CNT,TX MAX Size Err Frame Count Inc if > max Limit"
line.long 0x50 "ICSSG_TX_STAT_MIN_SIZE_PORT1,TX Min Size Frame Port1"
hexmask.long.word 0x50 0.--15. 1. "TX_MIN_SIZE_FRM,TX MIN Size Frame Count Limit"
line.long 0x54 "ICSSG_TX_STAT_MIN_ERR_PORT1,TX Min Size Error Frame Count Port1"
hexmask.long.word 0x54 0.--15. 1. "TX_MIN_ERR_FRM_CNT,TX MIN Size Err Frame Count Inc if < min Limit"
line.long 0x58 "ICSSG_TX_STAT_BKT1_SIZE_PORT1,TX Bucket1 Size Configuration Port1"
hexmask.long.word 0x58 0.--13. 1. "TX_STAT_BKT1_SIZE,TX Bucket1 Byte Size"
line.long 0x5C "ICSSG_TX_STAT_BKT2_SIZE_PORT1,TX Bucket2 Size Configuration Port1"
hexmask.long.word 0x5C 0.--13. 1. "TX_STAT_BKT2_SIZE,TX Bucket2 Byte Size"
line.long 0x60 "ICSSG_TX_STAT_BKT3_SIZE_PORT1,TX Bucket3 Size Configuration Port1"
hexmask.long.word 0x60 0.--13. 1. "TX_STAT_BKT3_SIZE,TX Bucket3 Byte Size"
line.long 0x64 "ICSSG_TX_STAT_BKT4_SIZE_PORT1,TX Bucket4 Size Configuration Port1"
hexmask.long.word 0x64 0.--13. 1. "TX_STAT_BKT4_SIZE,TX Bucket4 Byte Size"
line.long 0x68 "ICSSG_TX_STAT_64_PORT1,TX 64B Sized Frame Count Port1"
hexmask.long.word 0x68 0.--15. 1. "TX_64_FRM_CNT,TX 64Byte Frame Count Inc if 64B"
line.long 0x6C "ICSSG_TX_STAT_BKT1_PORT1,TX Bucket1 Sized Frame Count Port1"
hexmask.long.word 0x6C 0.--15. 1. "TX_STAT_BKT1,TX Bucket1 Inc if <= than Bucket1"
line.long 0x70 "ICSSG_TX_STAT_BKT2_PORT1,TX Bucket2 Sized Frame Count Port1"
hexmask.long.word 0x70 0.--15. 1. "TX_STAT_BKT2,TX Bucket2 Inc if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size"
line.long 0x74 "ICSSG_TX_STAT_BKT3_PORT1,TX Bucket3 Sized Frame Count Port1"
hexmask.long.word 0x74 0.--15. 1. "TX_STAT_BKT3,TX Bucket3 Inc if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size"
line.long 0x78 "ICSSG_TX_STAT_BKT4_PORT1,TX Bucket4 Sized Frame Count Port1"
hexmask.long.word 0x78 0.--15. 1. "TX_STAT_BKT4,TX Bucket4 Inc if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size"
line.long 0x7C "ICSSG_TX_STAT_BKT5_PORT1,TX Bucket5 Sized Frame Count Port1"
hexmask.long.word 0x7C 0.--15. 1. "TX_STAT_BKT5,TX Bucket5 Inc if > than Bucket4 Byte Size"
line.long 0x80 "ICSSG_TX_STAT_TOTAL_BYTES_PORT1,TX Total Byte Count Port1"
line.long 0x84 "ICSSG_TX_HSR_TAG_PORT1,TX HSR TAG Port1"
line.long 0x88 "ICSSG_TX_HSR_SEQ_PORT1,TX HSR Seq Port1"
hexmask.long.word 0x88 0.--15. 1. "TX_HSR_SEQ,HSR Seq count"
line.long 0x8C "ICSSG_TX_VLAN_TYPE_TAG_PORT1,TX VLAN Type TAG Port1"
hexmask.long.word 0x8C 0.--15. 1. "TX_VLAN_TYPE_TAG,TX VLAN Type Tag match to enable VLAN removal"
line.long 0x90 "ICSSG_TX_VLAN_INS_TAG_PORT1,TX VLAN Insertion TAG Port1"
group.long 0xD00++0x03
line.long 0x00 "ICSSG_QUEUEk,Queue<k>"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PTRk,Queue <k> (where k = 0 to 63)"
rgroup.long 0xE00++0x03
line.long 0x00 "ICSSG_QUEUE_PEEKm,Queue Peek<m> Offset = E00h + (m * 4h); where m = 0h to Fh"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PEEK_PTRm,Queue <m> Peek portal (where m = 0 to 15)"
rgroup.long 0xE40++0x03
line.long 0x00 "ICSSG_QUEUE_CNTk,Queue Count<k> Offset = E40h + (k * 4h); where k = 0h to 3Fh"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_CNT_ENTRIESk,Queue Entry Count<k> (where k = 0 to 63)"
group.long 0xF40++0x03
line.long 0x00 "ICSSG_QUEUE_RESET,Queue Reset"
bitfld.long 0x00 0.--5. "RESET_QUEUE_ID,Reset Queue ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x40)++0x03
line.long 0x00 "ICSSG_PA_STAT_PUSH$1,Pa Stat Push0"
hexmask.long.byte 0x00 24.--31. 1. "PA_STAT_PUSH3_0,pa stat push3"
hexmask.long.byte 0x00 16.--23. 1. "PA_STAT_PUSH2_0,pa stat push2"
newline
hexmask.long.byte 0x00 8.--15. 1. "PA_STAT_PUSH1_0,pa stat push1"
hexmask.long.byte 0x00 0.--7. 1. "PA_STAT_PUSH0_0,pa stat push0"
repeat.end
tree.end
tree.end
tree "PRU_ICSSG_MII_RT"
tree "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG"
base ad:0xB032000
group.long 0x00++0x07
line.long 0x00 "ICSSG_RXCFG0,RX Configuration 0 Register"
bitfld.long 0x00 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x00 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x00 7. "RX_SFD_RAW0," "0,1"
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE0,Auto Forward Preamble Mode" "0,1"
bitfld.long 0x00 5. "RX_BYTE_SWAP0,Controls the order of the Byte0/1 placement for RX R31 and RX L2" "0,1"
newline
bitfld.long 0x00 4. "RX_L2_EN0," "0,1"
bitfld.long 0x00 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x00 2. "RX_CUT_PREAMBLE0," "0,1"
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
bitfld.long 0x00 0. "RX_ENABLE0,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
line.long 0x04 "ICSSG_RXCFG1,RX Configuration 1 Register"
bitfld.long 0x04 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x04 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x04 7. "RX_SFD_RAW1," "0,1"
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE1,Auto Forward Preamble Mode" "0,1"
bitfld.long 0x04 5. "RX_BYTE_SWAP1,Controls the order of the Byte0/1 placement for RX R31 and RX L2" "0,1"
newline
bitfld.long 0x04 4. "RX_L2_EN1," "0,1"
bitfld.long 0x04 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x04 2. "RX_CUT_PREAMBLE1," "0,1"
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
bitfld.long 0x04 0. "RX_ENABLE1,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x10++0x07
line.long 0x00 "ICSSG_TXCFG0,TX Control Register 0"
bitfld.long 0x00 28.--30. "TX_CLK_DELAY0,Number of MII_RT clock cycles to wait before launching data on the MII interface" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY0,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame"
bitfld.long 0x00 12. "TX_IPG_WIRE_CLK_EN," "0,1"
bitfld.long 0x00 11. "TX_32_MODE_EN0," "0,1"
bitfld.long 0x00 10. "PRE_TX_AUTO_ESC_ERR0,This bit enables the HW actions required to implement the ESC Error handing table" "0,1"
newline
bitfld.long 0x00 9. "PRE_TX_AUTO_SEQUENCE0,When set to one it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter" "0,1"
bitfld.long 0x00 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x00 3. "TX_BYTE_SWAP0,Controls the order of the Byte0/1 placement for TX R30" "0,1"
bitfld.long 0x00 2. "TX_EN_MODE0," "0,1"
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE0," "0,1"
newline
bitfld.long 0x00 0. "TX_ENABLE0," "0,1"
line.long 0x04 "ICSSG_TXCFG1,TX Control Register 1"
bitfld.long 0x04 28.--30. "TX_CLK_DELAY1,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must.." "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--25. 1. "TX_START_DELAY1,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame"
bitfld.long 0x04 11. "TX_32_MODE_EN1," "0,1"
bitfld.long 0x04 10. "PRE_TX_AUTO_ESC_ERR1,This bit enables the HW actions required to implement the ESC Error handing table" "0,1"
bitfld.long 0x04 9. "PRE_TX_AUTO_SEQUENCE1,When set to one it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter" "0,1"
newline
bitfld.long 0x04 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x04 3. "TX_BYTE_SWAP1,Controls the order of the Byte0/1 placement for TX R30" "0,1"
bitfld.long 0x04 2. "TX_EN_MODE1," "0,1"
bitfld.long 0x04 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x04 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x07
line.long 0x00 "ICSSG_TX_CRC0,Transmit CRC32 Register 0"
line.long 0x04 "ICSSG_TX_CRC1,Transmit CRC32 Register 1"
rgroup.long 0x38++0x07
line.long 0x00 "ICSSG_PRS0,PORT_RAW_STATUS Register 0"
bitfld.long 0x00 1. "SYNC_MII0_CRS,Read the current state of PR1_MII0_CRS" "0,1"
bitfld.long 0x00 0. "SYNC_MII0_COL,Read the current state of PR1_MII0_COL" "0,1"
line.long 0x04 "ICSSG_PRS1,PORT_RAW_STATUS Register 1"
bitfld.long 0x04 1. "SYNC_MII1_CRS,Read the current state of PR1_MII1_CRS" "0,1"
bitfld.long 0x04 0. "SYNC_MII1_COL,Read the current state of PR1_MII1_COL" "0,1"
rgroup.long 0x60++0x07
line.long 0x00 "ICSSG_RX_FIFO_LEVEL0,RX FIFO Level 0 Register"
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL0,Define the number of valid bytes in the RX FIFO"
line.long 0x04 "ICSSG_RX_FIFO_LEVEL1,RX FIFO Level 1 Register"
hexmask.long.byte 0x04 0.--7. 1. "RX_FIFO_LEVEL1,Define the number of valid bytes in the RX FIFO"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x68)++0x03
line.long 0x00 "ICSSG_TX_FIFO_LEVEL$1,TX FIFO Register 0"
hexmask.long.byte 0x00 0.--7. 1. "TX_FIFO_LEVEL0,Define the number of valid nibbles in the TX FIFO"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x50)++0x03
line.long 0x00 "ICSSG_RX_ERR$1,RX Error Register 0"
bitfld.long 0x00 3. "RX_MAX_FRM_ERR0,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "RX_MIN_FRM_ERR0,Set when the FRAME total byte count is less than defined value" "0,1"
newline
bitfld.long 0x00 1. "RX_MAX_PCNT_ERR0,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "RX_MIN_PCNT_ERR0,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x48)++0x03
line.long 0x00 "ICSSG_RX_PCNT$1,RX Preamble Cnt Register 0"
bitfld.long 0x00 4.--8. "RX_MAX_PCNT0,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "RX_MIN_PCNT0,Define the minimum number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "ICSSG_RX_FRMS$1,RX Frame Size Register 0"
hexmask.long.word 0x00 16.--31. 1. "RX_MAX_FRM0,If the FRAME total byte count is more than defined value RX_MAX_FRM_ERR will get set"
hexmask.long.word 0x00 0.--15. 1. "RX_MIN_FRM0,If the FRAME total byte count is less than defined value RX_MIN_FRM_ERR will get set"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "ICSSG_TX_IPG$1,TX IPG Register 0"
hexmask.long.word 0x00 0.--15. 1. "TX_IPG0,Define the minimum Inter Packet Gap.WhenWhen TX_IPG_WIRE_CLK_EN = 1h"
repeat.end
tree.end
tree "PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG"
base ad:0xB132000
group.long 0x00++0x07
line.long 0x00 "ICSSG_RXCFG0,RX Configuration 0 Register"
bitfld.long 0x00 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x00 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x00 7. "RX_SFD_RAW0," "0,1"
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE0,Auto Forward Preamble Mode" "0,1"
bitfld.long 0x00 5. "RX_BYTE_SWAP0,Controls the order of the Byte0/1 placement for RX R31 and RX L2" "0,1"
newline
bitfld.long 0x00 4. "RX_L2_EN0," "0,1"
bitfld.long 0x00 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x00 2. "RX_CUT_PREAMBLE0," "0,1"
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
bitfld.long 0x00 0. "RX_ENABLE0,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
line.long 0x04 "ICSSG_RXCFG1,RX Configuration 1 Register"
bitfld.long 0x04 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x04 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x04 7. "RX_SFD_RAW1," "0,1"
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE1,Auto Forward Preamble Mode" "0,1"
bitfld.long 0x04 5. "RX_BYTE_SWAP1,Controls the order of the Byte0/1 placement for RX R31 and RX L2" "0,1"
newline
bitfld.long 0x04 4. "RX_L2_EN1," "0,1"
bitfld.long 0x04 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x04 2. "RX_CUT_PREAMBLE1," "0,1"
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
bitfld.long 0x04 0. "RX_ENABLE1,This enables RX traffic which is currently selected by RX_MUX_SELECT" "0,1"
group.long 0x10++0x07
line.long 0x00 "ICSSG_TXCFG0,TX Control Register 0"
bitfld.long 0x00 28.--30. "TX_CLK_DELAY0,Number of MII_RT clock cycles to wait before launching data on the MII interface" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY0,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame"
bitfld.long 0x00 12. "TX_IPG_WIRE_CLK_EN," "0,1"
bitfld.long 0x00 11. "TX_32_MODE_EN0," "0,1"
bitfld.long 0x00 10. "PRE_TX_AUTO_ESC_ERR0,This bit enables the HW actions required to implement the ESC Error handing table" "0,1"
newline
bitfld.long 0x00 9. "PRE_TX_AUTO_SEQUENCE0,When set to one it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter" "0,1"
bitfld.long 0x00 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x00 3. "TX_BYTE_SWAP0,Controls the order of the Byte0/1 placement for TX R30" "0,1"
bitfld.long 0x00 2. "TX_EN_MODE0," "0,1"
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE0," "0,1"
newline
bitfld.long 0x00 0. "TX_ENABLE0," "0,1"
line.long 0x04 "ICSSG_TXCFG1,TX Control Register 1"
bitfld.long 0x04 28.--30. "TX_CLK_DELAY1,Number of MII_RT clock cycles to wait before launching data on the MII interface.Note: In order to guarantee the MII_G_RT I/O timing values published in the device data sheet the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must.." "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--25. 1. "TX_START_DELAY1,The time interval after which transmit interface starts sending data to MII interface after receiving RXDV for the current frame"
bitfld.long 0x04 11. "TX_32_MODE_EN1," "0,1"
bitfld.long 0x04 10. "PRE_TX_AUTO_ESC_ERR1,This bit enables the HW actions required to implement the ESC Error handing table" "0,1"
bitfld.long 0x04 9. "PRE_TX_AUTO_SEQUENCE1,When set to one it enables automated sequencing of transmit state machine based on events on receiver path that is connected to the respective transmitter" "0,1"
newline
bitfld.long 0x04 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x04 3. "TX_BYTE_SWAP1,Controls the order of the Byte0/1 placement for TX R30" "0,1"
bitfld.long 0x04 2. "TX_EN_MODE1," "0,1"
bitfld.long 0x04 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x04 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x07
line.long 0x00 "ICSSG_TX_CRC0,Transmit CRC32 Register 0"
line.long 0x04 "ICSSG_TX_CRC1,Transmit CRC32 Register 1"
rgroup.long 0x38++0x07
line.long 0x00 "ICSSG_PRS0,PORT_RAW_STATUS Register 0"
bitfld.long 0x00 1. "SYNC_MII0_CRS,Read the current state of PR1_MII0_CRS" "0,1"
bitfld.long 0x00 0. "SYNC_MII0_COL,Read the current state of PR1_MII0_COL" "0,1"
line.long 0x04 "ICSSG_PRS1,PORT_RAW_STATUS Register 1"
bitfld.long 0x04 1. "SYNC_MII1_CRS,Read the current state of PR1_MII1_CRS" "0,1"
bitfld.long 0x04 0. "SYNC_MII1_COL,Read the current state of PR1_MII1_COL" "0,1"
rgroup.long 0x60++0x07
line.long 0x00 "ICSSG_RX_FIFO_LEVEL0,RX FIFO Level 0 Register"
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL0,Define the number of valid bytes in the RX FIFO"
line.long 0x04 "ICSSG_RX_FIFO_LEVEL1,RX FIFO Level 1 Register"
hexmask.long.byte 0x04 0.--7. 1. "RX_FIFO_LEVEL1,Define the number of valid bytes in the RX FIFO"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x68)++0x03
line.long 0x00 "ICSSG_TX_FIFO_LEVEL$1,TX FIFO Register 0"
hexmask.long.byte 0x00 0.--7. 1. "TX_FIFO_LEVEL0,Define the number of valid nibbles in the TX FIFO"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x50)++0x03
line.long 0x00 "ICSSG_RX_ERR$1,RX Error Register 0"
bitfld.long 0x00 3. "RX_MAX_FRM_ERR0,Set when the FRAME total byte count is more than defined value" "0,1"
bitfld.long 0x00 2. "RX_MIN_FRM_ERR0,Set when the FRAME total byte count is less than defined value" "0,1"
newline
bitfld.long 0x00 1. "RX_MAX_PCNT_ERR0,Set when of x nibbles before SFD 0xD5 is more than defined value" "0,1"
bitfld.long 0x00 0. "RX_MIN_PCNT_ERR0,Set when of 0x5 before SFD 0xD5 is less than defined value" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x48)++0x03
line.long 0x00 "ICSSG_RX_PCNT$1,RX Preamble Cnt Register 0"
bitfld.long 0x00 4.--8. "RX_MAX_PCNT0,Define the max number of nibbles until first SFD/SMD is matched" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "RX_MIN_PCNT0,Define the minimum number of nibbles before SFD 0xD5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "ICSSG_RX_FRMS$1,RX Frame Size Register 0"
hexmask.long.word 0x00 16.--31. 1. "RX_MAX_FRM0,If the FRAME total byte count is more than defined value RX_MAX_FRM_ERR will get set"
hexmask.long.word 0x00 0.--15. 1. "RX_MIN_FRM0,If the FRAME total byte count is less than defined value RX_MIN_FRM_ERR will get set"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "ICSSG_TX_IPG$1,TX IPG Register 0"
hexmask.long.word 0x00 0.--15. 1. "TX_IPG0,Define the minimum Inter Packet Gap.WhenWhen TX_IPG_WIRE_CLK_EN = 1h"
repeat.end
tree.end
tree.end
tree "PRU_ICSSG_PROTECT"
tree "PRU_ICSSG0_PR1_PROT_SLV"
base ad:0xB024C00
group.long 0x00++0x07
line.long 0x00 "ICSSG_UNLOCK_KEY,LOCK KEY"
line.long 0x04 "ICSSG_CFG,Config"
bitfld.long 0x04 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1" "disable,enable When enabled.."
bitfld.long 0x04 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0" "disable,enable When enabled.."
bitfld.long 0x04 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG" "disable,enable"
newline
bitfld.long 0x04 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 1. "PRU1_WP_EN,Write Protect PRU1 and TX_PRU1 access Debug IMEM" "disable,enable"
newline
bitfld.long 0x04 0. "PRU0_WP_EN,Write Protect PRU0 and TX_PRU0 access Debug IMEM" "disable,enable"
tree.end
tree "PRU_ICSSG1_PR1_PROT_SLV"
base ad:0xB124C00
group.long 0x00++0x07
line.long 0x00 "ICSSG_UNLOCK_KEY,LOCK KEY"
line.long 0x04 "ICSSG_CFG,Config"
bitfld.long 0x04 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1" "disable,enable When enabled.."
bitfld.long 0x04 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0" "disable,enable When enabled.."
bitfld.long 0x04 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG" "disable,enable"
newline
bitfld.long 0x04 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 1. "PRU1_WP_EN,Write Protect PRU1 and TX_PRU1 access Debug IMEM" "disable,enable"
newline
bitfld.long 0x04 0. "PRU0_WP_EN,Write Protect PRU0 and TX_PRU0 access Debug IMEM" "disable,enable"
tree.end
tree.end
tree "PRU_ICSSG_PRU_CTRL_RTU_PRU_CTRL_and_TX_PRU_CTRL"
tree "PRU_ICSSG0_PR1_PDSP0_IRAM"
base ad:0xB022000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG0_PR1_PDSP1_IRAM"
base ad:0xB024000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM"
base ad:0xB023000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM"
base ad:0xB023800
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG0_PR1_TX_PDSP0_IRAM"
base ad:0xB025000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG0_PR1_TX_PDSP1_IRAM"
base ad:0xB025800
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG1_PR1_PDSP0_IRAM"
base ad:0xB122000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG1_PR1_PDSP1_IRAM"
base ad:0xB124000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM"
base ad:0xB123000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM"
base ad:0xB123800
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG1_PR1_TX_PDSP0_IRAM"
base ad:0xB125000
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree "PRU_ICSSG1_PR1_TX_PDSP1_IRAM"
base ad:0xB125800
group.long 0x00++0x13
line.long 0x00 "ICSSG_PRU_CONTROL,PRU Control Register"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset"
rbitfld.long 0x00 15. "RUNSTATE,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1"
rbitfld.long 0x00 13. "TS_ENABLE,Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag" "0,1"
bitfld.long 0x00 8. "SINGLE_STEP,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1"
bitfld.long 0x00 3. "COUNTER_ENABLE,PRU Cycle Counter Enable: Enables PRU cycle counters" "0,1"
bitfld.long 0x00 2. "SLEEPING,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep" "0,1"
newline
bitfld.long 0x00 1. "ENABLE,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions.If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO SBxO SCAN etc.).." "0,1"
bitfld.long 0x00 0. "SOFT_RST_N,Soft Reset: When this bit is cleared the PRU will be reset" "0,1"
line.long 0x04 "ICSSG_PRU_STATUS,PRU Status Register"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter"
line.long 0x08 "ICSSG_PRU_WAKEUP_EN,PRU Wakeup Enable Register"
line.long 0x0C "ICSSG_PRU_CYCLE,PRU Cycle Count"
line.long 0x10 "ICSSG_PRU_STALL,PRU Stall Count Register"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_PRU_CTBIR0,Constant Table Block Index Register 0"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 26"
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 25"
line.long 0x04 "ICSSG_PRU_CTBIR1,Constant Table Block Index Register 1"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 28"
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 27"
line.long 0x08 "ICSSG_PRU_CTPPR0,Constant Table Programmable Pointer Register 0"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 30"
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 29"
line.long 0x0C "ICSSG_PRU_CTPPR1,Constant Table Programmable Pointer Register 1"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 32"
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table.This field while always present is only used if the ctreg_cnt configuration value is less than 31"
tree.end
tree.end
tree "PRU_ICSSG_PRU_DEBUG_RTU_PRU_DEBUG_and_TX_PRU_DEBUG"
tree "PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG"
base ad:0xB022400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG"
base ad:0xB024400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"
base ad:0xB023400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"
base ad:0xB023C00
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG0_PR1_TX_PDSP0_IRAM_DEBUG"
base ad:0xB025400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG0_PR1_TX_PDSP1_IRAM_DEBUG"
base ad:0xB025C00
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG"
base ad:0xB122400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG"
base ad:0xB124400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"
base ad:0xB123400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"
base ad:0xB123C00
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG1_PR1_TX_PDSP0_IRAM_DEBUG"
base ad:0xB125400
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree "PRU_ICSSG1_PR1_TX_PDSP1_IRAM_DEBUG"
base ad:0xB125C00
group.long 0x00++0x03
line.long 0x00 "ICSSG_DBG_GPREG_y,DEBUG PRU General Purpose Registers 0 to 31"
group.long 0x80++0x03
line.long 0x00 "ICSSG_DBG_CT_REG_y,DEBUG PRU Constant Table Entry Registers 0 to 31"
tree.end
tree.end
tree "PRU_ICSSG_RAM"
tree "PRU_ICSSG0_RAM_SLV_RAM"
base ad:0xB010000
group.long 0x00++0x03
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PRU_ICSSG1_RAM_SLV_RAM"
base ad:0xB110000
group.long 0x00++0x03
line.long 0x00 "ICSSG_RAM_REG_y,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree.end
tree "PRU_ICSSG_RAT_SLICE"
tree "PRU_ICSSG0_RAT_SLICE0_CFG"
base ad:0xB008000
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,ICSSG_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits.0 = 1 byte " "?,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "ICSSG_BASE_j,The Base Address for Region a"
line.long 0x08 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a"
line.long 0x0C "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
group.long 0x804++0x03
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type.4 = RAT"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code.1 = Boundary crossing error"
line.long 0x0C "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "ICSSG_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PRU_ICSSG0_RAT_SLICE1_CFG"
base ad:0xB009000
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,ICSSG_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits.0 = 1 byte " "?,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "ICSSG_BASE_j,The Base Address for Region a"
line.long 0x08 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a"
line.long 0x0C "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
group.long 0x804++0x03
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type.4 = RAT"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code.1 = Boundary crossing error"
line.long 0x0C "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "ICSSG_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PRU_ICSSG1_RAT_SLICE0_CFG"
base ad:0xB108000
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,ICSSG_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits.0 = 1 byte " "?,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "ICSSG_BASE_j,The Base Address for Region a"
line.long 0x08 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a"
line.long 0x0C "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
group.long 0x804++0x03
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type.4 = RAT"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code.1 = Boundary crossing error"
line.long 0x0C "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "ICSSG_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "PRU_ICSSG1_RAT_SLICE1_CFG"
base ad:0xB109000
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,ICSSG_PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit:10 = Processors" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ICSSG_CONFIG,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x20++0x0F
line.long 0x00 "ICSSG_CTRL_j,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits.0 = 1 byte " "?,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "ICSSG_BASE_j,The Base Address for Region a"
line.long 0x08 "ICSSG_TRANS_l_j,The Translated Lower Address Bits for Region a"
line.long 0x0C "ICSSG_TRANS_U_j,The Translated Upper Address Bits for Region a"
hexmask.long.word 0x0C 0.--15. 1. "UPPER,Translated Upper Address Bits for the Region"
group.long 0x804++0x03
line.long 0x00 "ICSSG_DESTINATION_ID,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "ICSSG_EXCEPTION_LOGGING_CONTROL,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_LOGGING_HEADER0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type.4 = RAT"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "ICSSG_EXCEPTION_LOGGING_HEADER1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code.1 = Boundary crossing error"
line.long 0x0C "ICSSG_EXCEPTION_LOGGING_DATA0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "ICSSG_EXCEPTION_LOGGING_DATA1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "ICSSG_EXCEPTION_LOGGING_DATA2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "ICSSG_EXCEPTION_LOGGING_DATA3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "ICSSG_EXCEPTION_PEND_SET,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "ICSSG_EXCEPTION_PEND_CLEAR,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "ICSSG_EXCEPTION_ENABLE_SET,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "ICSSG_EXCEPTION_ENABLE_CLEAR,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "ICSSG_EOI_REG,EOI Register The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree.end
tree "PRU_ICSSG_SGMII"
tree "PRU_ICSSG1_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0"
base ad:0xB132100
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_SGMII_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,TX Identification Value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor Version Value"
line.long 0x04 "ICSSG_SOFT_RESET_REG,Software reset register"
bitfld.long 0x04 1. "RT_SOFT_RESET,Transmit and Receive Software Reset" "0,1"
bitfld.long 0x04 0. "SOFT_RESET,Software Reset" "0,1"
group.long 0x10++0x17
line.long 0x00 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x00 6. "TEST_PATTERN_EN,Test Pattern Enable" "0,1"
bitfld.long 0x00 5. "MASTER,Master Mode" "0,1"
bitfld.long 0x00 4. "LOOPBACK,Loopback mode" "0,1"
bitfld.long 0x00 3. "MR_NP_LOADED,Next Page Loaded" "0,1"
bitfld.long 0x00 2. "FAST_LINK_TIMER,Fast Link Timer" "0,1"
newline
bitfld.long 0x00 1. "MR_AN_RESTART,Auto-Negotiation Restart" "0,1"
bitfld.long 0x00 0. "MR_AN_ENABLE,Auto-Negotiation Enable" "0,1"
line.long 0x04 "ICSSG_STATUS_REG,Status Register"
bitfld.long 0x04 5. "FIB_SIG_DETECT,Fiber Signal Detect" "0,1"
bitfld.long 0x04 4. "LOCK,Lock" "0,1"
bitfld.long 0x04 3. "MR_PAGE_RX,Next Page Received" "0,1"
bitfld.long 0x04 2. "MR_AN_COMPLETE,Auto-negotiation complete" "0,1"
bitfld.long 0x04 1. "AN_ERROR,Auto-negotiation error" "0,1"
newline
bitfld.long 0x04 0. "LINK,Link indicator" "0,1"
line.long 0x08 "ICSSG_MR_ADV_ABILITY_REG,Advertised Ability Register"
hexmask.long.word 0x08 0.--15. 1. "MR_ADV_ABILITY,Advertised Ability"
line.long 0x0C "ICSSG_MR_NP_TX_REG,Next Page Transmit Register"
hexmask.long.word 0x0C 0.--15. 1. "MR_NP_TX,Next Page Transmit"
line.long 0x10 "ICSSG_MR_LP_ADV_ABILITY_REG,Link Partner Advertised Ability Register"
hexmask.long.word 0x10 0.--15. 1. "MR_LP_ADV_ABILITY,Link Partner Advertised Ability"
line.long 0x14 "ICSSG_MR_LP_NP_RX_REG,Link Partner Next Page Received Register"
hexmask.long.word 0x14 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received"
group.long 0x30++0x0B
line.long 0x00 "ICSSG_TX_CFG_REG,Transmit Configuration Register"
line.long 0x04 "ICSSG_RX_CFG_REG,Receive Configuration Register"
line.long 0x08 "ICSSG_AUX_CFG_REG,Auxiliary Configuration Register"
group.long 0x40++0x0B
line.long 0x00 "ICSSG_DIAG_CLEAR_REG,Diagnostics Clear Register"
bitfld.long 0x00 0. "DIAG_CLEAR,Diagnostics Clear" "0,1"
line.long 0x04 "ICSSG_DIAG_CONTROL_REG,Diagnostics Control Register"
bitfld.long 0x04 4.--6. "DIAG_SM_SEL,Diagnostic Select" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--1. "DIAG_EDGE_SEL,Diagnostis Hold Signals Edge Select" "0,1,2,3"
line.long 0x08 "ICSSG_DIAG_STATUS_REG,Diagnostics Status Register"
hexmask.long.word 0x08 0.--15. 1. "DIAG_STATUS,Diagnostics Status"
tree.end
tree "PRU_ICSSG1_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1"
base ad:0xB132200
rgroup.long 0x00++0x07
line.long 0x00 "ICSSG_SGMII_IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,TX Identification Value"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor Version Value"
line.long 0x04 "ICSSG_SOFT_RESET_REG,Software reset register"
bitfld.long 0x04 1. "RT_SOFT_RESET,Transmit and Receive Software Reset" "0,1"
bitfld.long 0x04 0. "SOFT_RESET,Software Reset" "0,1"
group.long 0x10++0x17
line.long 0x00 "ICSSG_CONTROL_REG,Control Register"
bitfld.long 0x00 6. "TEST_PATTERN_EN,Test Pattern Enable" "0,1"
bitfld.long 0x00 5. "MASTER,Master Mode" "0,1"
bitfld.long 0x00 4. "LOOPBACK,Loopback mode" "0,1"
bitfld.long 0x00 3. "MR_NP_LOADED,Next Page Loaded" "0,1"
bitfld.long 0x00 2. "FAST_LINK_TIMER,Fast Link Timer" "0,1"
newline
bitfld.long 0x00 1. "MR_AN_RESTART,Auto-Negotiation Restart" "0,1"
bitfld.long 0x00 0. "MR_AN_ENABLE,Auto-Negotiation Enable" "0,1"
line.long 0x04 "ICSSG_STATUS_REG,Status Register"
bitfld.long 0x04 5. "FIB_SIG_DETECT,Fiber Signal Detect" "0,1"
bitfld.long 0x04 4. "LOCK,Lock" "0,1"
bitfld.long 0x04 3. "MR_PAGE_RX,Next Page Received" "0,1"
bitfld.long 0x04 2. "MR_AN_COMPLETE,Auto-negotiation complete" "0,1"
bitfld.long 0x04 1. "AN_ERROR,Auto-negotiation error" "0,1"
newline
bitfld.long 0x04 0. "LINK,Link indicator" "0,1"
line.long 0x08 "ICSSG_MR_ADV_ABILITY_REG,Advertised Ability Register"
hexmask.long.word 0x08 0.--15. 1. "MR_ADV_ABILITY,Advertised Ability"
line.long 0x0C "ICSSG_MR_NP_TX_REG,Next Page Transmit Register"
hexmask.long.word 0x0C 0.--15. 1. "MR_NP_TX,Next Page Transmit"
line.long 0x10 "ICSSG_MR_LP_ADV_ABILITY_REG,Link Partner Advertised Ability Register"
hexmask.long.word 0x10 0.--15. 1. "MR_LP_ADV_ABILITY,Link Partner Advertised Ability"
line.long 0x14 "ICSSG_MR_LP_NP_RX_REG,Link Partner Next Page Received Register"
hexmask.long.word 0x14 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received"
group.long 0x30++0x0B
line.long 0x00 "ICSSG_TX_CFG_REG,Transmit Configuration Register"
line.long 0x04 "ICSSG_RX_CFG_REG,Receive Configuration Register"
line.long 0x08 "ICSSG_AUX_CFG_REG,Auxiliary Configuration Register"
group.long 0x40++0x0B
line.long 0x00 "ICSSG_DIAG_CLEAR_REG,Diagnostics Clear Register"
bitfld.long 0x00 0. "DIAG_CLEAR,Diagnostics Clear" "0,1"
line.long 0x04 "ICSSG_DIAG_CONTROL_REG,Diagnostics Control Register"
bitfld.long 0x04 4.--6. "DIAG_SM_SEL,Diagnostic Select" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--1. "DIAG_EDGE_SEL,Diagnostis Hold Signals Edge Select" "0,1,2,3"
line.long 0x08 "ICSSG_DIAG_STATUS_REG,Diagnostics Status Register"
hexmask.long.word 0x08 0.--15. 1. "DIAG_STATUS,Diagnostics Status"
tree.end
tree.end
tree "PRU_ICSSG_TASKS_MGR_PRU_RTU"
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR"
base ad:0xB02A000
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG0_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR"
base ad:0xB02A200
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG0_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR"
base ad:0xB02A100
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG0_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR"
base ad:0xB02A300
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR"
base ad:0xB12A000
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_PRU1_PR1_TASKS_MGR_PRU1_MMR"
base ad:0xB12A200
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_RTU0_PR1_TASKS_MGR_RTU0_MMR"
base ad:0xB12A100
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
newline
bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
newline
bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_TASKS_MGR_RTU1_PR1_TASKS_MGR_RTU1_MMR"
base ad:0xB12A300
group.long 0x00++0x4B
line.long 0x00 "ICSSG_GLOBAL_CFG,Global Configuration"
bitfld.long 0x00 11. "TS2_EN_S4,TS2 Sub4" "Disabled,Enabled"
bitfld.long 0x00 10. "TS2_EN_S3,TS2 Sub3" "Disabled,Enabled"
bitfld.long 0x00 9. "TS2_EN_S2,TS2 Sub2" "Disabled,Enabled"
bitfld.long 0x00 8. "TS2_EN_S1,TS2 Sub1" "Disabled,Enabled"
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bitfld.long 0x00 7. "TS2_EN_S0,TS2 Sub0" "Disabled,Enabled"
bitfld.long 0x00 6. "TS1_EN_S4,TS1 Sub4" "Disabled,Enabled"
bitfld.long 0x00 5. "TS1_EN_S3,TS1 Sub3" "Disabled,Enabled"
bitfld.long 0x00 4. "TS1_EN_S2,TS1 Sub2" "Disabled,Enabled"
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bitfld.long 0x00 3. "TS1_EN_S1,TS1 Sub1" "Disabled,Enabled"
bitfld.long 0x00 2. "TS1_EN_S0,TS1 Sub0" "Disabled,Enabled"
bitfld.long 0x00 0.--1. "TASKS_MGR_MODE,TaskSwap Mode" "Disabled,RXTX,General_HW,?..."
line.long 0x04 "ICSSG_GLOBAL_STATUS,Global Status"
bitfld.long 0x04 17. "TS2_SUB_PEND_4,Task2 Sub4 Pend State" "0,1"
bitfld.long 0x04 16. "TS2_SUB_PEND_3,Task2 Sub3 Pend State" "0,1"
bitfld.long 0x04 15. "TS2_SUB_PEND_2,Task2 Sub2 Pend State" "0,1"
bitfld.long 0x04 14. "TS2_SUB_PEND_1,Task2 Sub1 Pend State" "0,1"
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bitfld.long 0x04 13. "TS2_SUB_PEND_0,Task2 Sub0 Pend State" "0,1"
bitfld.long 0x04 12. "TS1_SUB_PEND_4,Task1 Sub4 Pend State" "0,1"
bitfld.long 0x04 11. "TS1_SUB_PEND_3,Task1 Sub3 Pend State" "0,1"
bitfld.long 0x04 10. "TS1_SUB_PEND_2,Task1 Sub2 Pend State" "0,1"
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bitfld.long 0x04 9. "TS1_SUB_PEND_1,Task1 Sub1 Pend State" "0,1"
bitfld.long 0x04 8. "TS1_SUB_PEND_0,Task1 Sub0 Pend State" "0,1"
bitfld.long 0x04 4.--7. "TS2_STATE,Task2 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "TS1_STATE,Task1 State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "ICSSG_TS1_PC_S0,TS1 Sub0 PC"
hexmask.long.word 0x08 0.--13. 1. "TS1_PC_S0,TS1 Sub0 PC"
line.long 0x0C "ICSSG_TS1_PC_S1,TS1 Sub1 PC"
hexmask.long.word 0x0C 0.--13. 1. "TS1_PC_S1,TS1 Sub1 PC"
line.long 0x10 "ICSSG_TS1_PC_S2,TS1 Sub2 PC"
hexmask.long.word 0x10 0.--13. 1. "TS1_PC_S2,TS1 Sub2 PC"
line.long 0x14 "ICSSG_TS1_PC_S3,TS1 Sub3 PC"
hexmask.long.word 0x14 0.--13. 1. "TS1_PC_S3,TS1 Sub3 PC"
line.long 0x18 "ICSSG_TS1_PC_S4,TS1 Sub4 PC"
hexmask.long.word 0x18 0.--13. 1. "TS1_PC_S4,TS1 Sub4 PC"
line.long 0x1C "ICSSG_TS2_PC_S0,TS2 Sub0 PC"
hexmask.long.word 0x1C 0.--13. 1. "TS2_PC_S0,TS2 Sub0 PC"
line.long 0x20 "ICSSG_TS2_PC_S1,TS2 Sub1 PC"
hexmask.long.word 0x20 0.--13. 1. "TS2_PC_S1,TS2 Sub1 PC"
line.long 0x24 "ICSSG_TS2_PC_S2,TS2 Sub2 PC"
hexmask.long.word 0x24 0.--13. 1. "TS2_PC_S2,TS2 Sub2 PC"
line.long 0x28 "ICSSG_TS2_PC_S3,TS2 Sub3 PC"
hexmask.long.word 0x28 0.--13. 1. "TS2_PC_S3,TS2 Sub3 PC"
line.long 0x2C "ICSSG_TS2_PC_S4,TS2 Sub4 PC"
hexmask.long.word 0x2C 0.--13. 1. "TS2_PC_S4,TS2 Sub4 PC"
line.long 0x30 "ICSSG_RX_CFG,RX Configuration"
bitfld.long 0x30 10.--14. "BKN_SIZE,RX BKN Size After BK1 and BK@ then after another 1 to 32 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 5.--9. "BK2_SIZE,RX BK2 Size The Second 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 0.--4. "BK1_SIZE,RX BK1 Size The first 1 to 32 Bytes trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "ICSSG_TX_CFG,TX Configuration"
bitfld.long 0x34 0.--5. "TX_WM,TX L2 Water Mark Level 1 to 64 Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "ICSSG_TS1_GEN_CFG1,Generic TS1 Configuration1"
hexmask.long.byte 0x38 24.--31. 1. "TS1_GEN_S3_MX,TS1 Generic Sub3 MX Select"
hexmask.long.byte 0x38 16.--23. 1. "TS1_GEN_S2_MX,TS1 Generic Sub2 MX Select"
hexmask.long.byte 0x38 8.--15. 1. "TS1_GEN_S1_MX,TS1 Generic Sub1 MX Select"
hexmask.long.byte 0x38 0.--7. 1. "TS1_GEN_S0_MX,TS1 Generic Sub0 MX Select"
line.long 0x3C "ICSSG_TS1_GEN_CFG2,Generic TS1 Configuration2"
hexmask.long.byte 0x3C 0.--7. 1. "TS1_GEN_S4_MX,TS1 Generic Sub4 MX Select"
line.long 0x40 "ICSSG_TS2_GEN_CFG1,Generic TS2 Configuration1"
hexmask.long.byte 0x40 24.--31. 1. "TS2_GEN_S3_MX,TS2 Generic Sub3 MX Select"
hexmask.long.byte 0x40 16.--23. 1. "TS2_GEN_S2_MX,TS2 Generic Sub2 MX Select"
hexmask.long.byte 0x40 8.--15. 1. "TS2_GEN_S1_MX,TS2 Generic Sub1 MX Select"
hexmask.long.byte 0x40 0.--7. 1. "TS2_GEN_S0_MX,TS2 Generic Sub0 MX Select"
line.long 0x44 "ICSSG_TS2_GEN_CFG2,Generic TS2 Configuration2"
hexmask.long.byte 0x44 0.--7. 1. "TS2_GEN_S4_MX,TS2 Generic Sub4 MX Select"
line.long 0x48 "ICSSG_CAP_EN_CFG,This register allows you to enable a capture of a new event when you are active in the sub task"
bitfld.long 0x48 4. "CAP_NEW_TS1_EN_S4,Capture new event enable" "0,1"
bitfld.long 0x48 3. "CAP_NEW_TS1_EN_S3,Capture new event enable" "0,1"
bitfld.long 0x48 2. "CAP_NEW_TS1_EN_S2,Capture new event enable" "0,1"
bitfld.long 0x48 1. "CAP_NEW_TS1_EN_S1,Capture new event enable" "0,1"
newline
bitfld.long 0x48 0. "CAP_NEW_TS1_EN_S0,Capture new event enable" "0,1"
tree.end
tree.end
tree "PRU_ICSSG_UART0"
tree "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV"
base ad:0xB028000
group.long 0x00++0x2B
line.long 0x00 "ICSSG_RBR_TBR,Registers"
hexmask.long.word 0x00 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x04 "ICSSG_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x04 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x04 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x04 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x04 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x08 "ICSSG_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x08 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x08 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x08 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x08 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x08 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x08 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
rbitfld.long 0x08 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x08 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0x0C "ICSSG_LCTR,Line Control Register"
bitfld.long 0x0C 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
bitfld.long 0x0C 5. "SP,Stick Parity" "0,1"
bitfld.long 0x0C 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0x0C 3. "PEN,Parity Enable" "0,1"
bitfld.long 0x0C 2. "STB,Number of Stop Bits" "0,1"
bitfld.long 0x0C 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0x0C 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "ICSSG_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
line.long 0x14 "ICSSG_LSR1,Line Status Register1"
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x14 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x14 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x14 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x14 3. "FE,Framing Error" "0,1"
bitfld.long 0x14 2. "PE,Parity Error" "0,1"
bitfld.long 0x14 1. "OE,Overrun Error" "0,1"
bitfld.long 0x14 0. "DR,Data Ready" "0,1"
line.long 0x18 "ICSSG_MSR,Modem Status Register"
bitfld.long 0x18 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x18 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x18 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x18 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x18 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x18 2. "TERI,Trailing Edge Ring Indicator" "0,1"
bitfld.long 0x18 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x18 0. "DCTS,Delta Clear To Send" "0,1"
line.long 0x1C "ICSSG_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x1C 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x20 "ICSSG_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x20 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x24 "ICSSG_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x24 0.--7. 1. "DLH,Divisor Latch [MSB]"
line.long 0x28 "ICSSG_PID,Peripheral ID Register"
group.long 0x30++0x07
line.long 0x00 "ICSSG_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x00 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x00 1. "RES,Free Bit" "0,1"
bitfld.long 0x00 0. "FREE,Free Bit" "0,1"
line.long 0x04 "ICSSG_MODE,UART Mode Definition Register"
bitfld.long 0x04 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
tree "PRU_ICSSG1_PR1_ICSS_UART_UART_SLV"
base ad:0xB128000
group.long 0x00++0x2B
line.long 0x00 "ICSSG_RBR_TBR,Registers"
hexmask.long.word 0x00 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x04 "ICSSG_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x04 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x04 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x04 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x04 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x08 "ICSSG_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x08 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x08 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x08 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x08 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x08 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x08 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
rbitfld.long 0x08 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x08 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0x0C "ICSSG_LCTR,Line Control Register"
bitfld.long 0x0C 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
bitfld.long 0x0C 5. "SP,Stick Parity" "0,1"
bitfld.long 0x0C 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0x0C 3. "PEN,Parity Enable" "0,1"
bitfld.long 0x0C 2. "STB,Number of Stop Bits" "0,1"
bitfld.long 0x0C 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0x0C 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "ICSSG_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
line.long 0x14 "ICSSG_LSR1,Line Status Register1"
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x14 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x14 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x14 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x14 3. "FE,Framing Error" "0,1"
bitfld.long 0x14 2. "PE,Parity Error" "0,1"
bitfld.long 0x14 1. "OE,Overrun Error" "0,1"
bitfld.long 0x14 0. "DR,Data Ready" "0,1"
line.long 0x18 "ICSSG_MSR,Modem Status Register"
bitfld.long 0x18 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x18 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x18 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x18 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x18 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x18 2. "TERI,Trailing Edge Ring Indicator" "0,1"
bitfld.long 0x18 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x18 0. "DCTS,Delta Clear To Send" "0,1"
line.long 0x1C "ICSSG_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x1C 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x20 "ICSSG_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x20 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x24 "ICSSG_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x24 0.--7. 1. "DLH,Divisor Latch [MSB]"
line.long 0x28 "ICSSG_PID,Peripheral ID Register"
group.long 0x30++0x07
line.long 0x00 "ICSSG_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x00 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x00 1. "RES,Free Bit" "0,1"
bitfld.long 0x00 0. "FREE,Free Bit" "0,1"
line.long 0x04 "ICSSG_MODE,UART Mode Definition Register"
bitfld.long 0x04 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
tree.end
endif
autoindent.off
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